`timescale 1ns / 1ps

module factorial(
    input clk,
    input [31:0] in,
    output reg [31:0] out
);

    reg [31:0] outNext;
    
    always@(posedge clk) begin
        out <= outNext;
    end
    
    always@(*) begin
        outNext = out;
        if(in == 0)
            outNext = 1;
        else if (in == 1)
            outNext = 1;
        else if(in == 2)
            outNext = 2;
        else if(in == 3)
            outNext = 6;
        else if(in == 4)
            outNext = 24;
        else if(in == 5)
            outNext = 120;
        else
            outNext = 0;
    end
    
endmodule
