#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Fri Jan  8 11:04:41 2021
# Process ID: 6648
# Current directory: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1
# Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace
# Log file: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/design_1_wrapper.vdi
# Journal file: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
add_files: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 427.453 ; gain = 54.785
Command: link_design -top design_1_wrapper -part xcku5p-ffvb676-2-e
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-e
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.dcp' for cell 'design_1_i/axi_gpio_0'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.dcp' for cell 'design_1_i/clk_wiz_1'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_factorial_0_0/design_1_factorial_0_0.dcp' for cell 'design_1_i/factorial_0'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.dcp' for cell 'design_1_i/mdm_1'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.dcp' for cell 'design_1_i/microblaze_0'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.dcp' for cell 'design_1_i/rst_clk_wiz_1_100M'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0.dcp' for cell 'design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.dcp' for cell 'design_1_i/microblaze_0_local_memory/dlmb_v10'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0.dcp' for cell 'design_1_i/microblaze_0_local_memory/ilmb_bram_if_cntlr'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.dcp' for cell 'design_1_i/microblaze_0_local_memory/ilmb_v10'
INFO: [Project 1-454] Reading design checkpoint 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0.dcp' for cell 'design_1_i/microblaze_0_local_memory/lmb_bram'
INFO: [Netlist 29-17] Analyzing 231 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xdc] for cell 'design_1_i/microblaze_0/U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0.xdc] for cell 'design_1_i/microblaze_0/U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xdc] for cell 'design_1_i/microblaze_0_local_memory/dlmb_v10/U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0.xdc] for cell 'design_1_i/microblaze_0_local_memory/dlmb_v10/U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xdc] for cell 'design_1_i/microblaze_0_local_memory/ilmb_v10/U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0.xdc] for cell 'design_1_i/microblaze_0_local_memory/ilmb_v10/U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xdc] for cell 'design_1_i/mdm_1/U0'
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xdc:51]
get_clocks: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1819.145 ; gain = 372.594
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0.xdc] for cell 'design_1_i/mdm_1/U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_board.xdc] for cell 'design_1_i/clk_wiz_1/inst'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_board.xdc] for cell 'design_1_i/clk_wiz_1/inst'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xdc] for cell 'design_1_i/clk_wiz_1/inst'
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xdc:57]
WARNING: [Vivado 12-2489] -input_jitter contains time 0.033330 which will be rounded to 0.033 to ensure it is an integer multiple of 1 picosecond [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xdc:57]
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0.xdc] for cell 'design_1_i/clk_wiz_1/inst'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_board.xdc] for cell 'design_1_i/rst_clk_wiz_1_100M/U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_board.xdc] for cell 'design_1_i/rst_clk_wiz_1_100M/U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xdc] for cell 'design_1_i/rst_clk_wiz_1_100M/U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xdc] for cell 'design_1_i/rst_clk_wiz_1_100M/U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'design_1_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'design_1_i/axi_gpio_0/U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'design_1_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'design_1_i/axi_gpio_0/U0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
INFO: [Opt 31-422] The CLOCK_DOMAINS attribute on the BRAM cell design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram has been changed from INDEPENDENT to COMMON to match the clocking topology used for the BRAM.
Generating merged BMM file for the design top 'design_1_wrapper'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/data/mb_bootloop_le.elf 
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1819.145 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 98 instances were transformed.
  IBUF => IBUF (IBUFCTRL, INBUF): 1 instances
  IBUFDS => IBUFDS (DIFFINBUF, IBUFCTRL): 1 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 80 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 16 instances

32 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 1819.145 ; gain = 1391.691
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1819.145 ; gain = 0.000

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 831a9bca

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.391 . Memory (MB): peak = 1838.426 ; gain = 19.281

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 5 inverter(s) to 43 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: d0677901

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.419 . Memory (MB): peak = 1988.602 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 21 cells and removed 50 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: efd357ba

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.486 . Memory (MB): peak = 1988.602 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 9 cells and removed 48 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 5b30d404

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1988.602 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 606 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 5b30d404

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1988.602 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 5b30d404

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1988.602 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 5b30d404

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1988.602 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |              21  |              50  |                                              1  |
|  Constant propagation         |               9  |              48  |                                              0  |
|  Sweep                        |               0  |             606  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1988.602 ; gain = 0.000
Ending Logic Optimization Task | Checksum: fb7de85c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1988.602 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=7.901 | TNS=0.000 |
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 8 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 16
Ending PowerOpt Patch Enables Task | Checksum: fb7de85c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 4063.941 ; gain = 0.000
Ending Power Optimization Task | Checksum: fb7de85c

Time (s): cpu = 00:00:32 ; elapsed = 00:00:32 . Memory (MB): peak = 4063.941 ; gain = 2075.340

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: fb7de85c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4063.941 ; gain = 0.000

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: fb7de85c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
56 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:37 . Memory (MB): peak = 4063.941 ; gain = 2244.797
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/design_1_wrapper_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/design_1_wrapper_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 513240c0

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 4063.941 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 13063b483

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 159ccf3f4

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 159ccf3f4

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 159ccf3f4

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 199055987

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 2.2 Global Placement Core

Phase 2.2.1 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for HD net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000

Summary of Physical Synthesis Optimizations
============================================


----------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                  |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
----------------------------------------------------------------------------------------------------------------------------------------
|  Very High Fanout              |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                  |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                 |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  HD Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                         |            0  |              0  |                     0  |           0  |           2  |  00:00:00  |
----------------------------------------------------------------------------------------------------------------------------------------


Phase 2.2.1 Physical Synthesis In Placer | Checksum: 1be1dae50

Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 2.2 Global Placement Core | Checksum: 255c0159b

Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 2 Global Placement | Checksum: 255c0159b

Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 2595f6d30

Time (s): cpu = 00:00:17 ; elapsed = 00:00:11 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1dbe5a2e9

Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1f2881bdc

Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.4 Small Shape Clustering
Phase 3.4 Small Shape Clustering | Checksum: 27b00ab02

Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.5 Flow Legalize Slice Clusters
Phase 3.5 Flow Legalize Slice Clusters | Checksum: 27f30db34

Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.6 Slice Area Swap
Phase 3.6 Slice Area Swap | Checksum: 2726a64e6

Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.7 Commit Slice Clusters
Phase 3.7 Commit Slice Clusters | Checksum: 1f1f715a9

Time (s): cpu = 00:00:19 ; elapsed = 00:00:13 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 1490af4f3

Time (s): cpu = 00:00:19 ; elapsed = 00:00:13 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 11a832d34

Time (s): cpu = 00:00:19 ; elapsed = 00:00:13 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 3 Detail Placement | Checksum: 11a832d34

Time (s): cpu = 00:00:19 ; elapsed = 00:00:13 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: bd409d13

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Phase 4.1.1.1 BUFG Insertion | Checksum: bd409d13

Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Place 30-746] Post Placement Timing Summary WNS=7.159. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 158ddfa02

Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 4.1 Post Commit Optimization | Checksum: 158ddfa02

Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 158ddfa02

Time (s): cpu = 00:00:21 ; elapsed = 00:00:14 . Memory (MB): peak = 4063.941 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 15c9bb08d

Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 4.4 Final Placement Cleanup | Checksum: 1652aba59

Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1652aba59

Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 4063.941 ; gain = 0.000
Ending Placer Task | Checksum: b0285e00

Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
83 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:22 . Memory (MB): peak = 4063.941 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.257 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/design_1_wrapper_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 4063.941 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 38262d4b ConstDB: 0 ShapeSum: 74447a2a RouteDB: 3bdb68b

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 11e1db72a

Time (s): cpu = 00:00:54 ; elapsed = 00:00:45 . Memory (MB): peak = 4063.941 ; gain = 0.000
Post Restoration Checksum: NetGraph: 9ed60929 NumContArr: af1eda7e Constraints: a524d0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 14e9a0877

Time (s): cpu = 00:00:54 ; elapsed = 00:00:45 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 14e9a0877

Time (s): cpu = 00:00:54 ; elapsed = 00:00:45 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 14e9a0877

Time (s): cpu = 00:00:55 ; elapsed = 00:00:45 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 2.4 Global Clock Net Routing
 Number of Nodes with overlaps = 0
Phase 2.4 Global Clock Net Routing | Checksum: 18b683c4d

Time (s): cpu = 00:00:55 ; elapsed = 00:00:46 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 2.5 Update Timing
Phase 2.5 Update Timing | Checksum: 18fe6a47d

Time (s): cpu = 00:00:57 ; elapsed = 00:00:47 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Route 35-416] Intermediate Timing Summary | WNS=7.292  | TNS=0.000  | WHS=-1.177 | THS=-5.708 |

Phase 2 Router Initialization | Checksum: 17b401bd2

Time (s): cpu = 00:00:58 ; elapsed = 00:00:47 . Memory (MB): peak = 4063.941 ; gain = 0.000

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.000747251 %
  Global Horizontal Routing Utilization  = 0.00196186 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 2560
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 2057
  Number of Partially Routed Nets     = 503
  Number of Node Overlaps             = 0


Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1f2f56319

Time (s): cpu = 00:01:01 ; elapsed = 00:00:50 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 554
 Number of Nodes with overlaps = 34
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.014  | TNS=0.000  | WHS=-0.756 | THS=-3.411 |

Phase 4.1 Global Iteration 0 | Checksum: 218fc1c60

Time (s): cpu = 00:01:06 ; elapsed = 00:00:53 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 4.2 Additional Iteration for Hold
Phase 4.2 Additional Iteration for Hold | Checksum: 223c79a00

Time (s): cpu = 00:01:07 ; elapsed = 00:00:53 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 4 Rip-up And Reroute | Checksum: 223c79a00

Time (s): cpu = 00:01:07 ; elapsed = 00:00:53 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1d3083fe0

Time (s): cpu = 00:01:07 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.014  | TNS=0.000  | WHS=0.019  | THS=0.000  |

Phase 5.1 Delay CleanUp | Checksum: 1d3083fe0

Time (s): cpu = 00:01:07 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1d3083fe0

Time (s): cpu = 00:01:07 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 5 Delay and Skew Optimization | Checksum: 1d3083fe0

Time (s): cpu = 00:01:07 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 19775625d

Time (s): cpu = 00:01:08 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Route 35-416] Intermediate Timing Summary | WNS=6.014  | TNS=0.000  | WHS=0.019  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: f2b12a53

Time (s): cpu = 00:01:08 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000
Phase 6 Post Hold Fix | Checksum: f2b12a53

Time (s): cpu = 00:01:08 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.132984 %
  Global Horizontal Routing Utilization  = 0.169956 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: fcfaec55

Time (s): cpu = 00:01:08 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: fcfaec55

Time (s): cpu = 00:01:08 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: fcfaec55

Time (s): cpu = 00:01:08 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=6.014  | TNS=0.000  | WHS=0.019  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: fcfaec55

Time (s): cpu = 00:01:09 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:01:09 ; elapsed = 00:00:54 . Memory (MB): peak = 4063.941 ; gain = 0.000

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
101 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:12 ; elapsed = 00:00:56 . Memory (MB): peak = 4063.941 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.326 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/design_1_wrapper_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/design_1_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
113 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force design_1_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xcku5p'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcku5p'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./design_1_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Jan  8 11:08:13 2021. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2019.1/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
133 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 4063.941 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Fri Jan  8 11:08:14 2021...
