//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Fri Jan  8 11:01:23 2021
//Host        : Nemesys4 running 64-bit Service Pack 1  (build 7601)
//Command     : generate_target design_1_wrapper.bd
//Design      : design_1_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module design_1_wrapper
   (default_sysclk1_300_clk_n,
    default_sysclk1_300_clk_p,
    reset);
  input default_sysclk1_300_clk_n;
  input default_sysclk1_300_clk_p;
  input reset;

  wire default_sysclk1_300_clk_n;
  wire default_sysclk1_300_clk_p;
  wire reset;

  design_1 design_1_i
       (.default_sysclk1_300_clk_n(default_sysclk1_300_clk_n),
        .default_sysclk1_300_clk_p(default_sysclk1_300_clk_p),
        .reset(reset));
endmodule
