Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version      : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date              : Fri Jan  8 11:07:38 2021
| Host              : Nemesys4 running 64-bit Service Pack 1  (build 7601)
| Command           : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : design_1_wrapper
| Device            : xcku5p-ffvb676
| Speed File        : -2  PRODUCTION 1.23 03-18-2019
| Temperature Grade : E
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 0 ports with no output delay specified.

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      6.021        0.000                      0                 4374        0.019        0.000                      0                 4374        0.500        0.000                       0                  1710  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                             Waveform(ns)         Period(ns)      Frequency(MHz)
-----                                                             ------------         ----------      --------------
default_sysclk1_300_clk_p                                         {0.000 1.666}        3.333           300.030         
  clk_out1_design_1_clk_wiz_1_0                                   {0.000 4.999}        9.999           100.010         
design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK  {0.000 16.666}       33.333          30.000          
  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK        {0.000 16.666}       33.333          30.000          
  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE      {0.000 33.333}       66.666          15.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
default_sysclk1_300_clk_p                                                                                                                                                                                       0.500        0.000                       0                     1  
  clk_out1_design_1_clk_wiz_1_0                                     6.021        0.000                      0                 4100        0.019        0.000                      0                 4100        4.457        0.000                       0                  1437  
  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK         14.880        0.000                      0                  228        0.039        0.000                      0                  228       16.134        0.000                       0                   233  
  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE       31.507        0.000                      0                   46        0.117        0.000                      0                   46       33.058        0.000                       0                    39  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  default_sysclk1_300_clk_p
  To Clock:  default_sysclk1_300_clk_p

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         default_sysclk1_300_clk_p
Waveform(ns):       { 0.000 1.666 }
Period(ns):         3.333
Sources:            { default_sysclk1_300_clk_p }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location   Pin
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.333       2.262      MMCM_X0Y2  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.666       0.500      MMCM_X0Y2  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y2  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y2  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y2  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_design_1_clk_wiz_1_0
  To Clock:  clk_out1_design_1_clk_wiz_1_0

Setup :            0  Failing Endpoints,  Worst Slack        6.021ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.019ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.457ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.021ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.598ns  (logic 0.605ns (16.815%)  route 2.993ns (83.185%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.013ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.620ns = ( 13.619 - 9.999 ) 
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.406ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.166ns (routing 1.236ns, distribution 0.930ns)
  Clock Net Delay (Destination): 1.994ns (routing 1.125ns, distribution 0.869ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.166     3.227    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X94Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y90         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.306 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/Q
                         net (fo=2, routed)           0.511     3.817    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X93Y90         LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     3.965 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.022     3.987    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/lopt_25
    SLICE_X93Y90         CARRY8 (Prop_CARRY8_SLICEM_S[5]_CO[7])
                                                      0.159     4.146 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.172    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     4.258 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[4]
                         net (fo=10, routed)          1.125     5.383    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/if_pc_reg[0]_0[7]
    SLICE_X99Y91         LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.133     5.516 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[22]_INST_0/O
                         net (fo=9, routed)           1.309     6.825    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/addrb[7]
    RAMB36_X8Y15         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.994    13.619    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y15         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.406    13.213    
                         clock uncertainty           -0.062    13.151    
    RAMB36_X8Y15         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[9])
                                                     -0.305    12.846    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.846    
                         arrival time                          -6.825    
  -------------------------------------------------------------------
                         slack                                  6.021    

Slack (MET) :             6.159ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.364ns  (logic 0.605ns (17.985%)  route 2.759ns (82.015%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.109ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.532ns = ( 13.531 - 9.999 ) 
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.166ns (routing 1.236ns, distribution 0.930ns)
  Clock Net Delay (Destination): 1.906ns (routing 1.125ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.166     3.227    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X94Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y90         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.306 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/Q
                         net (fo=2, routed)           0.511     3.817    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X93Y90         LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     3.965 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.022     3.987    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/lopt_25
    SLICE_X93Y90         CARRY8 (Prop_CARRY8_SLICEM_S[5]_CO[7])
                                                      0.159     4.146 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.172    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     4.258 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[4]
                         net (fo=10, routed)          1.125     5.383    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/if_pc_reg[0]_0[7]
    SLICE_X99Y91         LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.133     5.516 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[22]_INST_0/O
                         net (fo=9, routed)           1.075     6.591    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/addrb[7]
    RAMB36_X7Y15         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.906    13.531    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y15         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.117    
                         clock uncertainty           -0.062    13.056    
    RAMB36_X7Y15         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[9])
                                                     -0.305    12.751    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.751    
                         arrival time                          -6.591    
  -------------------------------------------------------------------
                         slack                                  6.159    

Slack (MET) :             6.247ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.278ns  (logic 0.557ns (16.992%)  route 2.721ns (83.008%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.127ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.514ns = ( 13.513 - 9.999 ) 
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.166ns (routing 1.236ns, distribution 0.930ns)
  Clock Net Delay (Destination): 1.888ns (routing 1.125ns, distribution 0.763ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.166     3.227    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X94Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y90         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.306 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/Q
                         net (fo=2, routed)           0.511     3.817    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X93Y90         LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     3.965 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.022     3.987    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/lopt_25
    SLICE_X93Y90         CARRY8 (Prop_CARRY8_SLICEM_S[5]_CO[7])
                                                      0.159     4.146 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.172    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_CI_O[2])
                                                      0.067     4.239 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[2]
                         net (fo=10, routed)          0.876     5.115    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/if_pc_reg[0]_0[5]
    SLICE_X99Y90         LUT3 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.104     5.219 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[24]_INST_0/O
                         net (fo=9, routed)           1.286     6.505    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[5]
    RAMB36_X7Y18         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.888    13.513    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y18         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.099    
                         clock uncertainty           -0.062    13.038    
    RAMB36_X7Y18         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[7])
                                                     -0.285    12.753    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.753    
                         arrival time                          -6.505    
  -------------------------------------------------------------------
                         slack                                  6.247    

Slack (MET) :             6.265ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.253ns  (logic 0.605ns (18.598%)  route 2.648ns (81.402%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.527ns = ( 13.526 - 9.999 ) 
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.166ns (routing 1.236ns, distribution 0.930ns)
  Clock Net Delay (Destination): 1.901ns (routing 1.125ns, distribution 0.776ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.166     3.227    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X94Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y90         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.306 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/Q
                         net (fo=2, routed)           0.511     3.817    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X93Y90         LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     3.965 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.022     3.987    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/lopt_25
    SLICE_X93Y90         CARRY8 (Prop_CARRY8_SLICEM_S[5]_CO[7])
                                                      0.159     4.146 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.172    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     4.258 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[4]
                         net (fo=10, routed)          1.125     5.383    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/if_pc_reg[0]_0[7]
    SLICE_X99Y91         LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.133     5.516 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[22]_INST_0/O
                         net (fo=9, routed)           0.964     6.480    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/addrb[7]
    RAMB36_X7Y16         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.901    13.526    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y16         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.112    
                         clock uncertainty           -0.062    13.051    
    RAMB36_X7Y16         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[9])
                                                     -0.305    12.746    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.746    
                         arrival time                          -6.480    
  -------------------------------------------------------------------
                         slack                                  6.265    

Slack (MET) :             6.336ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Use_Async_Reset.sync_reset_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.134ns  (logic 0.388ns (12.380%)  route 2.746ns (87.620%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.125ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.532ns = ( 13.531 - 9.999 ) 
    Source Clock Delay      (SCD):    3.243ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.182ns (routing 1.236ns, distribution 0.946ns)
  Clock Net Delay (Destination): 1.906ns (routing 1.125ns, distribution 0.781ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.182     3.243    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Clk
    SLICE_X99Y102        FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Use_Async_Reset.sync_reset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y102        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     3.323 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Use_Async_Reset.sync_reset_reg/Q
                         net (fo=638, routed)         1.256     4.579    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/reset_bool_for_rst
    SLICE_X99Y100        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     4.728 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/IFetch_INST_0_i_1/O
                         net (fo=3, routed)           0.059     4.787    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/out
    SLICE_X99Y100        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     4.911 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=4, routed)           0.343     5.254    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/enb
    SLICE_X99Y88         LUT2 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.035     5.289 r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=8, routed)           1.088     6.377    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X7Y15         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.906    13.531    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y15         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.117    
                         clock uncertainty           -0.062    13.056    
    RAMB36_X7Y15         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342    12.714    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.714    
                         arrival time                          -6.377    
  -------------------------------------------------------------------
                         slack                                  6.336    

Slack (MET) :             6.369ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.142ns  (logic 0.605ns (19.255%)  route 2.537ns (80.745%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.121ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.520ns = ( 13.519 - 9.999 ) 
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.166ns (routing 1.236ns, distribution 0.930ns)
  Clock Net Delay (Destination): 1.894ns (routing 1.125ns, distribution 0.769ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.166     3.227    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X94Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y90         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.306 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/Q
                         net (fo=2, routed)           0.511     3.817    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X93Y90         LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     3.965 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.022     3.987    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/lopt_25
    SLICE_X93Y90         CARRY8 (Prop_CARRY8_SLICEM_S[5]_CO[7])
                                                      0.159     4.146 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.172    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     4.258 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[4]
                         net (fo=10, routed)          1.125     5.383    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/if_pc_reg[0]_0[7]
    SLICE_X99Y91         LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.133     5.516 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[22]_INST_0/O
                         net (fo=9, routed)           0.853     6.369    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/addrb[7]
    RAMB36_X7Y17         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.894    13.519    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y17         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.105    
                         clock uncertainty           -0.062    13.044    
    RAMB36_X7Y17         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[9])
                                                     -0.305    12.739    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.739    
                         arrival time                          -6.369    
  -------------------------------------------------------------------
                         slack                                  6.369    

Slack (MET) :             6.384ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.147ns  (logic 0.557ns (17.699%)  route 2.590ns (82.301%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.121ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.520ns = ( 13.519 - 9.999 ) 
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.166ns (routing 1.236ns, distribution 0.930ns)
  Clock Net Delay (Destination): 1.894ns (routing 1.125ns, distribution 0.769ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.166     3.227    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X94Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y90         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.306 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/Q
                         net (fo=2, routed)           0.511     3.817    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X93Y90         LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     3.965 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.022     3.987    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/lopt_25
    SLICE_X93Y90         CARRY8 (Prop_CARRY8_SLICEM_S[5]_CO[7])
                                                      0.159     4.146 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.172    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_CI_O[2])
                                                      0.067     4.239 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[2]
                         net (fo=10, routed)          0.876     5.115    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/if_pc_reg[0]_0[5]
    SLICE_X99Y90         LUT3 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.104     5.219 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[24]_INST_0/O
                         net (fo=9, routed)           1.155     6.374    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/addrb[5]
    RAMB36_X7Y17         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[7]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.894    13.519    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y17         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.105    
                         clock uncertainty           -0.062    13.044    
    RAMB36_X7Y17         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[7])
                                                     -0.285    12.759    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.759    
                         arrival time                          -6.374    
  -------------------------------------------------------------------
                         slack                                  6.384    

Slack (MET) :             6.461ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Use_Async_Reset.sync_reset_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.004ns  (logic 0.388ns (12.916%)  route 2.616ns (87.084%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.130ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.527ns = ( 13.526 - 9.999 ) 
    Source Clock Delay      (SCD):    3.243ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.182ns (routing 1.236ns, distribution 0.946ns)
  Clock Net Delay (Destination): 1.901ns (routing 1.125ns, distribution 0.776ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.182     3.243    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Clk
    SLICE_X99Y102        FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Use_Async_Reset.sync_reset_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y102        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     3.323 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Use_Async_Reset.sync_reset_reg/Q
                         net (fo=638, routed)         1.256     4.579    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/reset_bool_for_rst
    SLICE_X99Y100        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     4.728 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/IFetch_INST_0_i_1/O
                         net (fo=3, routed)           0.059     4.787    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/out
    SLICE_X99Y100        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     4.911 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=4, routed)           0.343     5.254    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/enb
    SLICE_X99Y88         LUT2 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.035     5.289 r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=8, routed)           0.958     6.247    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X7Y16         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.901    13.526    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y16         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.112    
                         clock uncertainty           -0.062    13.051    
    RAMB36_X7Y16         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342    12.709    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.709    
                         arrival time                          -6.247    
  -------------------------------------------------------------------
                         slack                                  6.461    

Slack (MET) :             6.474ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op1_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/WEA[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.007ns  (logic 0.569ns (18.923%)  route 2.438ns (81.077%))
  Logic Levels:           6  (CARRY8=4 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.602ns = ( 13.601 - 9.999 ) 
    Source Clock Delay      (SCD):    3.258ns
    Clock Pessimism Removal (CPR):    -0.406ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.197ns (routing 1.236ns, distribution 0.961ns)
  Clock Net Delay (Destination): 1.976ns (routing 1.125ns, distribution 0.851ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.197     3.258    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X96Y94         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op1_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y94         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.336 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op1_reg[19]/Q
                         net (fo=6, routed)           0.665     4.001    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[19].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I2
    SLICE_X93Y91         LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.101     4.102 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[19].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.015     4.117    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/lopt_25
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_S[7]_CO[7])
                                                      0.117     4.234 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.260    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[18].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y92         CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     4.275 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[18].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.301    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[10].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y93         CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     4.316 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[10].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.342    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[2].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y94         CARRY8 (Prop_CARRY8_SLICEM_CI_O[1])
                                                      0.076     4.418 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[2].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[1]
                         net (fo=7, routed)           0.554     4.972    design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr/U0/LMB_ABus[1]
    SLICE_X95Y85         LUT3 (Prop_B5LUT_SLICEM_I0_O)
                                                      0.167     5.139 r  design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr/U0/BRAM_WEN_A[3]_INST_0/O
                         net (fo=8, routed)           1.126     6.265    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/wea[0]
    RAMB36_X8Y18         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/WEA[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.976    13.601    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/clka
    RAMB36_X8Y18         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
                         clock pessimism             -0.406    13.195    
                         clock uncertainty           -0.062    13.133    
    RAMB36_X8Y18         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_WEA[0])
                                                     -0.394    12.739    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.739    
                         arrival time                          -6.265    
  -------------------------------------------------------------------
                         slack                                  6.474    

Slack (MET) :             6.501ns  (required time - arrival time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            9.999ns  (clk_out1_design_1_clk_wiz_1_0 rise@9.999ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.004ns  (logic 0.605ns (20.140%)  route 2.399ns (79.860%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.127ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.514ns = ( 13.513 - 9.999 ) 
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.413ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.166ns (routing 1.236ns, distribution 0.930ns)
  Clock Net Delay (Destination): 1.888ns (routing 1.125ns, distribution 0.763ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.166     3.227    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X94Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y90         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.306 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[29]/Q
                         net (fo=2, routed)           0.511     3.817    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X93Y90         LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     3.965 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[29].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.022     3.987    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/lopt_25
    SLICE_X93Y90         CARRY8 (Prop_CARRY8_SLICEM_S[5]_CO[7])
                                                      0.159     4.146 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_DAXI_ALU_Carry.Direct_MUXCY_I/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     4.172    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X93Y91         CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     4.258 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[26].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[4]
                         net (fo=10, routed)          1.125     5.383    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/if_pc_reg[0]_0[7]
    SLICE_X99Y91         LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.133     5.516 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[22]_INST_0/O
                         net (fo=9, routed)           0.715     6.231    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[7]
    RAMB36_X7Y18         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      9.999     9.999 r  
    K22                                               0.000     9.999 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     9.999    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374    10.373 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    10.413    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    10.413 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344    10.757    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630    11.387 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214    11.601    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    11.625 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.888    13.513    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/clkb
    RAMB36_X7Y18         RAMB36E2                                     r  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.413    13.099    
                         clock uncertainty           -0.062    13.038    
    RAMB36_X7Y18         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[9])
                                                     -0.305    12.733    design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                         12.733    
                         arrival time                          -6.231    
  -------------------------------------------------------------------
                         slack                                  6.501    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 design_1_i/axi_gpio_0/U0/ip2bus_data_i_D1_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.128ns  (logic 0.058ns (45.312%)  route 0.070ns (54.687%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.260ns
    Source Clock Delay      (SCD):    3.572ns
    Clock Pessimism Removal (CPR):    -0.358ns
  Clock Net Delay (Source):      1.946ns (routing 1.125ns, distribution 0.821ns)
  Clock Net Delay (Destination): 2.199ns (routing 1.236ns, distribution 0.963ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.946     3.572    design_1_i/axi_gpio_0/U0/s_axi_aclk
    SLICE_X94Y80         FDRE                                         r  design_1_i/axi_gpio_0/U0/ip2bus_data_i_D1_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y80         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.630 r  design_1_i/axi_gpio_0/U0/ip2bus_data_i_D1_reg[0]/Q
                         net (fo=1, routed)           0.070     3.700    design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/Q[31]
    SLICE_X94Y81         FDRE                                         r  design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.199     3.260    design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_aclk
    SLICE_X94Y81         FDRE                                         r  design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[31]/C
                         clock pessimism              0.358     3.618    
    SLICE_X94Y81         FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     3.680    design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[31]
  -------------------------------------------------------------------
                         required time                         -3.680    
                         arrival time                           3.700    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.022ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[13]/D
                            (rising edge-triggered cell FDSE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.190ns  (logic 0.057ns (30.000%)  route 0.133ns (70.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.106ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.274ns
    Source Clock Delay      (SCD):    3.577ns
    Clock Pessimism Removal (CPR):    -0.408ns
  Clock Net Delay (Source):      1.951ns (routing 1.125ns, distribution 0.826ns)
  Clock Net Delay (Destination): 2.213ns (routing 1.236ns, distribution 0.977ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.951     3.577    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/Clk
    SLICE_X93Y79         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y79         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     3.634 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[13]/Q
                         net (fo=2, routed)           0.133     3.767    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_wdata[18]
    SLICE_X96Y79         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.213     3.274    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X96Y79         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[13]/C
                         clock pessimism              0.408     3.682    
    SLICE_X96Y79         FDSE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     3.744    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[13]
  -------------------------------------------------------------------
                         required time                         -3.744    
                         arrival time                           3.767    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[24]/D
                            (rising edge-triggered cell FDSE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.059ns (44.030%)  route 0.075ns (55.970%))
  Logic Levels:           0  
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.267ns
    Source Clock Delay      (SCD):    3.576ns
    Clock Pessimism Removal (CPR):    -0.357ns
  Clock Net Delay (Source):      1.950ns (routing 1.125ns, distribution 0.825ns)
  Clock Net Delay (Destination): 2.206ns (routing 1.236ns, distribution 0.970ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.950     3.576    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/Clk
    SLICE_X97Y82         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y82         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.635 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[24]/Q
                         net (fo=2, routed)           0.075     3.710    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_wdata[7]
    SLICE_X97Y81         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.206     3.267    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X97Y81         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[24]/C
                         clock pessimism              0.357     3.624    
    SLICE_X97Y81         FDSE (Hold_HFF_SLICEL_C_D)
                                                      0.060     3.684    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[24]
  -------------------------------------------------------------------
                         required time                         -3.684    
                         arrival time                           3.710    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.025ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_DataBus_Addr_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.201ns  (logic 0.057ns (28.358%)  route 0.144ns (71.642%))
  Logic Levels:           0  
  Clock Path Skew:        0.116ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.260ns
    Source Clock Delay      (SCD):    3.553ns
    Clock Pessimism Removal (CPR):    -0.408ns
  Clock Net Delay (Source):      1.927ns (routing 1.125ns, distribution 0.802ns)
  Clock Net Delay (Destination): 2.199ns (routing 1.236ns, distribution 0.963ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.927     3.553    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X93Y90         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_DataBus_Addr_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y90         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     3.610 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/MEM_DataBus_Addr_reg[29]/Q
                         net (fo=1, routed)           0.144     3.754    design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_araddr[0]
    SLICE_X93Y85         FDRE                                         r  design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.199     3.260    design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_aclk
    SLICE_X93Y85         FDRE                                         r  design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[2]/C
                         clock pessimism              0.408     3.668    
    SLICE_X93Y85         FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.060     3.728    design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.728    
                         arrival time                           3.754    
  -------------------------------------------------------------------
                         slack                                  0.025    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.132ns  (logic 0.059ns (44.697%)  route 0.073ns (55.303%))
  Logic Levels:           0  
  Clock Path Skew:        0.042ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.254ns
    Source Clock Delay      (SCD):    3.572ns
    Clock Pessimism Removal (CPR):    -0.359ns
  Clock Net Delay (Source):      1.946ns (routing 1.125ns, distribution 0.821ns)
  Clock Net Delay (Destination): 2.193ns (routing 1.236ns, distribution 0.957ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.946     3.572    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X97Y102        FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y102        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.631 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[0]/Q
                         net (fo=7, routed)           0.073     3.704    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg_n_0_[0]
    SLICE_X97Y101        FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.193     3.254    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X97Y101        FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[0]/C
                         clock pessimism              0.359     3.613    
    SLICE_X97Y101        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.675    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.675    
                         arrival time                           3.704    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[8]/D
                            (rising edge-triggered cell FDSE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.141ns  (logic 0.060ns (42.553%)  route 0.081ns (57.447%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.263ns
    Source Clock Delay      (SCD):    3.575ns
    Clock Pessimism Removal (CPR):    -0.358ns
  Clock Net Delay (Source):      1.949ns (routing 1.125ns, distribution 0.824ns)
  Clock Net Delay (Destination): 2.202ns (routing 1.236ns, distribution 0.966ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.949     3.575    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/Clk
    SLICE_X93Y82         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y82         FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     3.635 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[8]/Q
                         net (fo=2, routed)           0.081     3.716    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_wdata[23]
    SLICE_X93Y83         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.202     3.263    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X93Y83         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[8]/C
                         clock pessimism              0.358     3.621    
    SLICE_X93Y83         FDSE (Hold_GFF2_SLICEM_C_D)
                                                      0.062     3.683    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.683    
                         arrival time                           3.716    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_In_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.099ns  (logic 0.052ns (52.525%)  route 0.047ns (47.475%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.849ns
    Source Clock Delay      (SCD):    2.061ns
    Clock Pessimism Removal (CPR):    -0.231ns
  Clock Net Delay (Source):      1.197ns (routing 0.671ns, distribution 0.526ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.749ns, distribution 0.605ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.229     0.229 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.269    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.269 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.203     0.472    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.702 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     0.847    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.864 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.197     2.061    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X95Y78         FDRE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_In_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y78         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.099 r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_In_reg[6]/Q
                         net (fo=2, routed)           0.029     2.128    design_1_i/axi_gpio_0/U0/gpio_core_1/gpio_Data_In[6]
    SLICE_X95Y79         LUT5 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.014     2.142 r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1/O
                         net (fo=1, routed)           0.018     2.160    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2[6]_i_1_n_0
    SLICE_X95Y79         FDRE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.326     0.326 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.376    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.376 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.230     0.606    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.311 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     0.476    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.495 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.354     1.849    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X95Y79         FDRE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg[6]/C
                         clock pessimism              0.231     2.081    
    SLICE_X95Y79         FDRE (Hold_AFF_SLICEM_C_D)
                                                      0.046     2.127    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].reg2_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.127    
                         arrival time                           2.160    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/WB_DAXI_Read_Data_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.131ns  (logic 0.060ns (45.801%)  route 0.071ns (54.198%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.242ns
    Source Clock Delay      (SCD):    3.564ns
    Clock Pessimism Removal (CPR):    -0.357ns
  Clock Net Delay (Source):      1.938ns (routing 1.125ns, distribution 0.813ns)
  Clock Net Delay (Destination): 2.181ns (routing 1.236ns, distribution 0.945ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.938     3.564    design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_aclk
    SLICE_X94Y85         FDRE                                         r  design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y85         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     3.624 r  design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rdata_i_reg[3]/Q
                         net (fo=1, routed)           0.071     3.695    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/M_AXI_DP_RDATA[3]
    SLICE_X94Y86         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/WB_DAXI_Read_Data_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.181     3.242    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/Clk
    SLICE_X94Y86         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/WB_DAXI_Read_Data_reg[28]/C
                         clock pessimism              0.357     3.600    
    SLICE_X94Y86         FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     3.662    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_DBUS.DAXI_Interface_I1/WB_DAXI_Read_Data_reg[28]
  -------------------------------------------------------------------
                         required time                         -3.662    
                         arrival time                           3.695    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[18]/D
                            (rising edge-triggered cell FDSE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.203ns  (logic 0.058ns (28.571%)  route 0.145ns (71.429%))
  Logic Levels:           0  
  Clock Path Skew:        0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.278ns
    Source Clock Delay      (SCD):    3.579ns
    Clock Pessimism Removal (CPR):    -0.408ns
  Clock Net Delay (Source):      1.953ns (routing 1.125ns, distribution 0.828ns)
  Clock Net Delay (Destination): 2.217ns (routing 1.236ns, distribution 0.981ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.374     0.374 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.414    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.414 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.344     0.758    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.388 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     1.602    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.626 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.953     3.579    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/Clk
    SLICE_X97Y79         FDRE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y79         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     3.637 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Byte_Doublet_Handle_gti_I/MEM_DataBus_Write_Data_reg[18]/Q
                         net (fo=2, routed)           0.145     3.782    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_wdata[13]
    SLICE_X98Y79         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.469     0.469 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.519    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.519 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.397     0.916    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.789 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     1.033    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.061 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        2.217     3.278    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X98Y79         FDSE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[18]/C
                         clock pessimism              0.408     3.686    
    SLICE_X98Y79         FDSE (Hold_GFF2_SLICEM_C_D)
                                                      0.062     3.748    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_OE_reg[18]
  -------------------------------------------------------------------
                         required time                         -3.748    
                         arrival time                           3.782    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_In_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Destination:            design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_design_1_clk_wiz_1_0  {rise@0.000ns fall@4.999ns period=9.999ns})
  Path Group:             clk_out1_design_1_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_design_1_clk_wiz_1_0 rise@0.000ns - clk_out1_design_1_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.096ns  (logic 0.053ns (55.208%)  route 0.043ns (44.792%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.853ns
    Source Clock Delay      (SCD):    2.069ns
    Clock Pessimism Removal (CPR):    -0.232ns
  Clock Net Delay (Source):      1.205ns (routing 0.671ns, distribution 0.534ns)
  Clock Net Delay (Destination): 1.358ns (routing 0.749ns, distribution 0.609ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.229     0.229 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.269    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.269 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.203     0.472    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.702 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     0.847    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.864 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.205     2.069    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X97Y77         FDRE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_In_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y77         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.108 r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.gpio_Data_In_reg[19]/Q
                         net (fo=2, routed)           0.027     2.135    design_1_i/axi_gpio_0/U0/gpio_core_1/gpio_Data_In[19]
    SLICE_X97Y78         LUT5 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.014     2.149 r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1/O
                         net (fo=1, routed)           0.016     2.165    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2[19]_i_1_n_0
    SLICE_X97Y78         FDRE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_design_1_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    K22                                               0.000     0.000 r  default_sysclk1_300_clk_p (IN)
                         net (fo=0)                   0.000     0.000    design_1_i/clk_wiz_1/inst/clkin1_ibufds/I
    HPIOBDIFFINBUF_X0Y58 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.326     0.326 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.376    design_1_i/clk_wiz_1/inst/clkin1_ibufds/OUT
    K22                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.376 r  design_1_i/clk_wiz_1/inst/clkin1_ibufds/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.230     0.606    design_1_i/clk_wiz_1/inst/clk_in1_design_1_clk_wiz_1_0
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.311 r  design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     0.476    design_1_i/clk_wiz_1/inst/clk_out1_design_1_clk_wiz_1_0
    BUFGCE_X0Y50         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.495 r  design_1_i/clk_wiz_1/inst/clkout1_buf/O
    X2Y1 (CLOCK_ROOT)    net (fo=1435, routed)        1.358     1.853    design_1_i/axi_gpio_0/U0/gpio_core_1/s_axi_aclk
    SLICE_X97Y78         FDRE                                         r  design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg[19]/C
                         clock pessimism              0.232     2.085    
    SLICE_X97Y78         FDRE (Hold_AFF_SLICEL_C_D)
                                                      0.046     2.131    design_1_i/axi_gpio_0/U0/gpio_core_1/Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].reg2_reg[19]
  -------------------------------------------------------------------
                         required time                         -2.131    
                         arrival time                           2.165    
  -------------------------------------------------------------------
                         slack                                  0.034    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_design_1_clk_wiz_1_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         9.999
Sources:            { design_1_i/clk_wiz_1/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         9.999       8.644      RAMB36_X8Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         9.999       8.644      RAMB36_X8Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         9.999       8.644      RAMB36_X7Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         9.999       8.644      RAMB36_X7Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         9.999       8.644      RAMB36_X7Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         9.999       8.644      RAMB36_X7Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         9.999       8.644      RAMB36_X8Y15  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         9.999       8.644      RAMB36_X8Y15  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         9.999       8.644      RAMB36_X8Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         9.999       8.644      RAMB36_X8Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X8Y15  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         4.999       4.457      RAMB36_X8Y15  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X8Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         4.999       4.457      RAMB36_X8Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y15  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y18  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         5.000       4.458      RAMB36_X8Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[6].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X8Y16  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y15  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         4.999       4.457      RAMB36_X7Y15  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         4.999       4.457      RAMB36_X8Y18  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         5.000       4.458      RAMB36_X8Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         5.000       4.458      RAMB36_X8Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         5.000       4.458      RAMB36_X8Y17  design_1_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  To Clock:  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK

Setup :            0  Failing Endpoints,  Worst Slack       14.880ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.039ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       16.134ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             14.880ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/CE
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        1.465ns  (logic 0.179ns (12.218%)  route 1.286ns (87.782%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.724ns = ( 20.391 - 16.667 ) 
    Source Clock Delay      (SCD):    10.070ns
    Clock Pessimism Removal (CPR):    6.320ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.942ns (routing 1.120ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.727ns (routing 1.027ns, distribution 0.700ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200     8.100    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     8.128 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.942    10.070    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X100Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDCE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081    10.151 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg[6]/Q
                         net (fo=3, routed)           0.848    10.999    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/completion_ctrl_reg[0]_0[1]
    SLICE_X100Y107       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.098    11.097 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native_i_1/O
                         net (fo=1, routed)           0.438    11.535    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/CE
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    17.132 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    18.639    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    18.663 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.727    20.390    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
                         clock pessimism              6.320    26.710    
                         clock uncertainty           -0.235    26.475    
    SLICE_X100Y107       FDRE (Setup_AFF_SLICEL_C_CE)
                                                     -0.060    26.415    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native
  -------------------------------------------------------------------
                         required time                         26.415    
                         arrival time                         -11.535    
  -------------------------------------------------------------------
                         slack                                 14.880    

Slack (MET) :             15.238ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.161ns  (logic 0.180ns (15.504%)  route 0.981ns (84.496%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.748ns = ( 37.081 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.751ns (routing 1.027ns, distribution 0.724ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.594    27.582    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X102Y101       LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065    27.647 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[2]_i_1/O
                         net (fo=1, routed)           0.246    27.893    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[2]
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.751    37.081    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[2]/C
                         clock pessimism              6.259    43.340    
                         clock uncertainty           -0.235    43.105    
    SLICE_X102Y101       FDCE (Setup_EFF_SLICEL_C_D)
                                                      0.025    43.130    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[2]
  -------------------------------------------------------------------
                         required time                         43.130    
                         arrival time                         -27.892    
  -------------------------------------------------------------------
                         slack                                 15.238    

Slack (MET) :             15.405ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[4]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.992ns  (logic 0.204ns (20.564%)  route 0.788ns (79.435%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.746ns = ( 37.079 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.749ns (routing 1.027ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.598    27.586    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X102Y101       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.089    27.675 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[4]_i_1/O
                         net (fo=1, routed)           0.049    27.724    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[4]
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.749    37.079    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[4]/C
                         clock pessimism              6.259    43.338    
                         clock uncertainty           -0.235    43.103    
    SLICE_X102Y101       FDCE (Setup_DFF_SLICEL_C_D)
                                                      0.025    43.128    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[4]
  -------------------------------------------------------------------
                         required time                         43.128    
                         arrival time                         -27.724    
  -------------------------------------------------------------------
                         slack                                 15.405    

Slack (MET) :             15.405ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[6]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.992ns  (logic 0.203ns (20.464%)  route 0.789ns (79.536%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.746ns = ( 37.079 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.749ns (routing 1.027ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.598    27.586    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X102Y101       LUT3 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.088    27.674 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[6]_i_1/O
                         net (fo=1, routed)           0.050    27.723    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[6]
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.749    37.079    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[6]/C
                         clock pessimism              6.259    43.338    
                         clock uncertainty           -0.235    43.103    
    SLICE_X102Y101       FDCE (Setup_CFF_SLICEL_C_D)
                                                      0.025    43.128    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[6]
  -------------------------------------------------------------------
                         required time                         43.128    
                         arrival time                         -27.723    
  -------------------------------------------------------------------
                         slack                                 15.405    

Slack (MET) :             15.421ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.975ns  (logic 0.165ns (16.923%)  route 0.810ns (83.077%))
  Logic Levels:           2  (LUT2=1 LUT6=1)
  Clock Path Skew:        -0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.745ns = ( 37.078 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.748ns (routing 1.027ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.620    27.608    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X102Y100       LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.050    27.658 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[0]_i_1/O
                         net (fo=1, routed)           0.049    27.707    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[0]_i_1_n_0
    SLICE_X102Y100       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.748    37.078    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y100       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[0]/C
                         clock pessimism              6.259    43.337    
                         clock uncertainty           -0.235    43.102    
    SLICE_X102Y100       FDCE (Setup_DFF_SLICEL_C_D)
                                                      0.025    43.127    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[0]
  -------------------------------------------------------------------
                         required time                         43.127    
                         arrival time                         -27.707    
  -------------------------------------------------------------------
                         slack                                 15.421    

Slack (MET) :             15.429ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.968ns  (logic 0.213ns (22.004%)  route 0.755ns (77.996%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.746ns = ( 37.079 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.749ns (routing 1.027ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.598    27.586    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X102Y101       LUT4 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.098    27.684 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[7]_i_1/O
                         net (fo=1, routed)           0.016    27.700    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[7]
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.749    37.079    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[7]/C
                         clock pessimism              6.259    43.338    
                         clock uncertainty           -0.235    43.103    
    SLICE_X102Y101       FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    43.128    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[7]
  -------------------------------------------------------------------
                         required time                         43.128    
                         arrival time                         -27.699    
  -------------------------------------------------------------------
                         slack                                 15.429    

Slack (MET) :             15.439ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.957ns  (logic 0.181ns (18.913%)  route 0.776ns (81.087%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.745ns = ( 37.078 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.748ns (routing 1.027ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.620    27.608    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X102Y100       LUT3 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.066    27.674 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[1]_i_1/O
                         net (fo=1, routed)           0.015    27.689    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[1]
    SLICE_X102Y100       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.748    37.078    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y100       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[1]/C
                         clock pessimism              6.259    43.337    
                         clock uncertainty           -0.235    43.102    
    SLICE_X102Y100       FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    43.127    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[1]
  -------------------------------------------------------------------
                         required time                         43.127    
                         arrival time                         -27.688    
  -------------------------------------------------------------------
                         slack                                 15.439    

Slack (MET) :             15.514ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.865ns  (logic 0.264ns (30.520%)  route 0.601ns (69.480%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.728ns = ( 37.061 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.731ns (routing 1.027ns, distribution 0.704ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.401    27.389    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X101Y102       LUT3 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.149    27.538 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[5]_i_1/O
                         net (fo=1, routed)           0.059    27.597    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[5]
    SLICE_X101Y102       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.731    37.061    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y102       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5]/C
                         clock pessimism              6.259    43.320    
                         clock uncertainty           -0.235    43.085    
    SLICE_X101Y102       FDCE (Setup_BFF_SLICEM_C_D)
                                                      0.025    43.110    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[5]
  -------------------------------------------------------------------
                         required time                         43.110    
                         arrival time                         -27.597    
  -------------------------------------------------------------------
                         slack                                 15.514    

Slack (MET) :             15.548ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.868ns  (logic 0.226ns (26.037%)  route 0.642ns (73.963%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.717ns = ( 37.050 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.308ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.720ns (routing 1.027ns, distribution 0.693ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.141    26.952    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X100Y107       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036    26.988 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Dbg_Shift_31_INST_0/O
                         net (fo=8, routed)           0.218    27.206    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X100Y102       LUT5 (Prop_G5LUT_SLICEL_I4_O)
                                                      0.111    27.317 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count[3]_i_1/O
                         net (fo=1, routed)           0.283    27.600    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[3]
    SLICE_X100Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.720    37.050    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X100Y101       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[3]/C
                         clock pessimism              6.308    43.358    
                         clock uncertainty           -0.235    43.123    
    SLICE_X100Y101       FDCE (Setup_EFF_SLICEL_C_D)
                                                      0.025    43.148    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_count_reg[3]
  -------------------------------------------------------------------
                         required time                         43.148    
                         arrival time                         -27.599    
  -------------------------------------------------------------------
                         slack                                 15.548    

Slack (MET) :             15.694ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C
                            (falling edge-triggered cell FDRE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        0.596ns  (logic 0.169ns (28.356%)  route 0.427ns (71.644%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.724ns = ( 37.057 - 33.333 ) 
    Source Clock Delay      (SCD):    10.065ns = ( 26.732 - 16.667 ) 
    Clock Pessimism Removal (CPR):    6.259ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.937ns (routing 1.120ns, distribution 0.817ns)
  Clock Net Delay (Destination): 1.727ns (routing 1.027ns, distribution 0.700ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    16.667 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900    22.566 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.200    24.767    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028    24.795 f  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.937    26.732    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native_0
    SLICE_X100Y107       FDRE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y107       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079    26.811 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Using_FPGA.Native/Q
                         net (fo=3, routed)           0.240    27.051    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/sync
    SLICE_X99Y108        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.090    27.141 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/Use_Serial_Unified_Completion.count[0]_i_1/O
                         net (fo=2, routed)           0.187    27.328    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/count
    SLICE_X99Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465    33.798 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.508    35.306    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    35.330 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.727    37.057    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X99Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]/C
                         clock pessimism              6.259    43.316    
                         clock uncertainty           -0.235    43.081    
    SLICE_X99Y108        FDCE (Setup_DFF_SLICEL_C_CE)
                                                     -0.060    43.021    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]
  -------------------------------------------------------------------
                         required time                         43.021    
                         arrival time                         -27.327    
  -------------------------------------------------------------------
                         slack                                 15.694    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.unchanged_reg/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.235%)  route 0.063ns (61.765%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.636ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    5.931ns
  Clock Net Delay (Source):      1.058ns (routing 0.604ns, distribution 0.454ns)
  Clock Net Delay (Destination): 1.187ns (routing 0.665ns, distribution 0.522ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.058     2.689    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y104       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.unchanged_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y104       FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.728 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.unchanged_reg/Q
                         net (fo=2, routed)           0.063     2.791    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/unchanged
    SLICE_X101Y103       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.187     8.636    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y103       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29]/C
                         clock pessimism             -5.931     2.705    
    SLICE_X101Y103       FDCE (Hold_EFF2_SLICEM_C_D)
                                                      0.047     2.752    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[29]
  -------------------------------------------------------------------
                         required time                         -2.752    
                         arrival time                           2.791    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg[31]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[30]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.631ns
    Source Clock Delay      (SCD):    2.683ns
    Clock Pessimism Removal (CPR):    5.931ns
  Clock Net Delay (Source):      1.052ns (routing 0.604ns, distribution 0.448ns)
  Clock Net Delay (Destination): 1.182ns (routing 0.665ns, distribution 0.517ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.052     2.683    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X100Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y97        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.722 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg[31]/Q
                         net (fo=3, routed)           0.064     2.786    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg_n_0_[31]
    SLICE_X100Y96        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.182     8.631    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X100Y96        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[30]/C
                         clock pessimism             -5.931     2.700    
    SLICE_X100Y96        FDCE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     2.747    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[30]
  -------------------------------------------------------------------
                         required time                         -2.747    
                         arrival time                           2.786    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg[23]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[22]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.109ns  (logic 0.039ns (35.780%)  route 0.070ns (64.220%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.635ns
    Source Clock Delay      (SCD):    2.684ns
    Clock Pessimism Removal (CPR):    5.931ns
  Clock Net Delay (Source):      1.053ns (routing 0.604ns, distribution 0.449ns)
  Clock Net Delay (Destination): 1.186ns (routing 0.665ns, distribution 0.521ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.053     2.684    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y96        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y96        FDCE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     2.723 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg[23]/Q
                         net (fo=3, routed)           0.070     2.793    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.shift_datain_reg_n_0_[23]
    SLICE_X101Y95        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.186     8.635    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y95        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[22]/C
                         clock pessimism             -5.931     2.704    
    SLICE_X101Y95        FDCE (Hold_HFF2_SLICEM_C_D)
                                                      0.047     2.751    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[22]
  -------------------------------------------------------------------
                         required time                         -2.751    
                         arrival time                           2.793    
  -------------------------------------------------------------------
                         slack                                  0.042    

Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.sync_running_clock/Single_Synchronize.use_async_reset.sync_reg/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[24]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.640ns
    Source Clock Delay      (SCD):    2.691ns
    Clock Pessimism Removal (CPR):    5.943ns
  Clock Net Delay (Source):      1.060ns (routing 0.604ns, distribution 0.456ns)
  Clock Net Delay (Destination): 1.191ns (routing 0.665ns, distribution 0.526ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.060     2.691    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.sync_running_clock/Dbg_Clk
    SLICE_X101Y102       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.sync_running_clock/Single_Synchronize.use_async_reset.sync_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y102       FDCE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     2.730 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.sync_running_clock/Single_Synchronize.use_async_reset.sync_reg/Q
                         net (fo=1, routed)           0.058     2.788    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/running_clock_synced
    SLICE_X101Y102       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.191     8.640    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y102       FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[24]/C
                         clock pessimism             -5.943     2.697    
    SLICE_X101Y102       FDCE (Hold_HFF2_SLICEM_C_D)
                                                      0.047     2.744    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.status_reg_reg[24]
  -------------------------------------------------------------------
                         required time                         -2.744    
                         arrival time                           2.788    
  -------------------------------------------------------------------
                         slack                                  0.044    

Slack (MET) :             0.047ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.099ns  (logic 0.053ns (53.535%)  route 0.046ns (46.465%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.636ns
    Source Clock Delay      (SCD):    2.688ns
    Clock Pessimism Removal (CPR):    5.942ns
  Clock Net Delay (Source):      1.057ns (routing 0.604ns, distribution 0.453ns)
  Clock Net Delay (Destination): 1.187ns (routing 0.665ns, distribution 0.522ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.057     2.688    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X99Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y108        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.727 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[1]/Q
                         net (fo=4, routed)           0.030     2.757    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[1]_0[0]
    SLICE_X99Y108        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.014     2.771 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count[0]_i_2/O
                         net (fo=1, routed)           0.016     2.787    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count[0]_i_2_n_0
    SLICE_X99Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.187     8.636    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X99Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]/C
                         clock pessimism             -5.942     2.694    
    SLICE_X99Y108        FDCE (Hold_DFF_SLICEL_C_D)
                                                      0.046     2.740    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.740    
                         arrival time                           2.787    
  -------------------------------------------------------------------
                         slack                                  0.047    

Slack (MET) :             0.048ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.100ns  (logic 0.053ns (53.000%)  route 0.047ns (47.000%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.637ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    5.942ns
  Clock Net Delay (Source):      1.058ns (routing 0.604ns, distribution 0.454ns)
  Clock Net Delay (Destination): 1.188ns (routing 0.665ns, distribution 0.523ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.058     2.689    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y107        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y107        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.728 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/Q
                         net (fo=4, routed)           0.031     2.759    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status_reg[9][6]
    SLICE_X97Y107        LUT5 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     2.773 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status[6]_i_1/O
                         net (fo=1, routed)           0.016     2.789    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/p_1_in[6]
    SLICE_X97Y107        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.188     8.637    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y107        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/C
                         clock pessimism             -5.942     2.695    
    SLICE_X97Y107        FDCE (Hold_DFF_SLICEL_C_D)
                                                      0.046     2.741    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.741    
                         arrival time                           2.789    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.048ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.100ns  (logic 0.054ns (54.000%)  route 0.046ns (46.000%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.645ns
    Source Clock Delay      (SCD):    2.695ns
    Clock Pessimism Removal (CPR):    5.944ns
  Clock Net Delay (Source):      1.064ns (routing 0.604ns, distribution 0.460ns)
  Clock Net Delay (Destination): 1.196ns (routing 0.665ns, distribution 0.531ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.064     2.695    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y108        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.734 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[2]/Q
                         net (fo=6, routed)           0.029     2.763    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status_reg[9][2]
    SLICE_X97Y108        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     2.778 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status[2]_i_1/O
                         net (fo=1, routed)           0.017     2.795    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/p_1_in[2]
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.196     8.645    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[2]/C
                         clock pessimism             -5.944     2.701    
    SLICE_X97Y108        FDCE (Hold_HFF_SLICEL_C_D)
                                                      0.046     2.747    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.747    
                         arrival time                           2.795    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.049ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.101ns  (logic 0.053ns (52.475%)  route 0.048ns (47.525%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.637ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    5.942ns
  Clock Net Delay (Source):      1.058ns (routing 0.604ns, distribution 0.454ns)
  Clock Net Delay (Destination): 1.188ns (routing 0.665ns, distribution 0.523ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.058     2.689    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y107        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y107        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.728 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[6]/Q
                         net (fo=4, routed)           0.031     2.759    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status_reg[9][6]
    SLICE_X97Y107        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     2.773 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status[7]_i_1/O
                         net (fo=1, routed)           0.017     2.790    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/p_1_in[7]
    SLICE_X97Y107        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.188     8.637    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y107        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[7]/C
                         clock pessimism             -5.942     2.695    
    SLICE_X97Y107        FDCE (Hold_CFF_SLICEL_C_D)
                                                      0.046     2.741    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[7]
  -------------------------------------------------------------------
                         required time                         -2.741    
                         arrival time                           2.790    
  -------------------------------------------------------------------
                         slack                                  0.049    

Slack (MET) :             0.049ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.101ns  (logic 0.053ns (52.475%)  route 0.048ns (47.525%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.641ns
    Source Clock Delay      (SCD):    2.692ns
    Clock Pessimism Removal (CPR):    5.943ns
  Clock Net Delay (Source):      1.061ns (routing 0.604ns, distribution 0.457ns)
  Clock Net Delay (Destination): 1.192ns (routing 0.665ns, distribution 0.527ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.061     2.692    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y108        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.731 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/Q
                         net (fo=4, routed)           0.032     2.763    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status_reg[9][4]
    SLICE_X97Y108        LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.014     2.777 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status[3]_i_1/O
                         net (fo=1, routed)           0.016     2.793    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/p_1_in[3]
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.192     8.641    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[3]/C
                         clock pessimism             -5.943     2.698    
    SLICE_X97Y108        FDCE (Hold_DFF_SLICEL_C_D)
                                                      0.046     2.744    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.744    
                         arrival time                           2.793    
  -------------------------------------------------------------------
                         slack                                  0.049    

Slack (MET) :             0.050ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.102ns  (logic 0.053ns (51.961%)  route 0.049ns (48.039%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    8.641ns
    Source Clock Delay      (SCD):    2.692ns
    Clock Pessimism Removal (CPR):    5.943ns
  Clock Net Delay (Source):      1.061ns (routing 0.604ns, distribution 0.457ns)
  Clock Net Delay (Destination): 1.192ns (routing 0.665ns, distribution 0.527ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.149     1.614    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.631 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.061     2.692    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y108        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.731 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/Q
                         net (fo=4, routed)           0.032     2.763    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status_reg[9][4]
    SLICE_X97Y108        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.014     2.777 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_Serial_Unified_Completion.completion_status[4]_i_1/O
                         net (fo=1, routed)           0.017     2.794    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/p_1_in[4]
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_DRCK)
                                                      5.900     5.900 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.530     7.430    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/DRCK
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     7.449 r  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/O
    X3Y1 (CLOCK_ROOT)    net (fo=232, routed)         1.192     8.641    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Using_FPGA.Native
    SLICE_X97Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]/C
                         clock pessimism             -5.943     2.698    
    SLICE_X97Y108        FDCE (Hold_CFF_SLICEL_C_D)
                                                      0.046     2.744    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_status_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.744    
                         arrival time                           2.794    
  -------------------------------------------------------------------
                         slack                                  0.050    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK
Waveform(ns):       { 0.000 16.667 }
Period(ns):         33.333
Sources:            { design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/DRCK }

Check Type        Corner  Lib Pin      Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFGCE/I     n/a            1.290         33.333      32.043     BUFGCE_X0Y32    design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Using_FPGA.Native/I
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y111  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y108  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y108  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_1/Use_unisim.MB_SRL16E_I1/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_3/Use_unisim.MB_SRL16E_I1/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_4/Use_unisim.MB_SRL16E_I1/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[1].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1/CLK
Min Period        n/a     SRL16E/CLK   n/a            1.064         33.333      32.269     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[5].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1/CLK
Low Pulse Width   Slow    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y111  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11/CLK
Low Pulse Width   Slow    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X98Y106   design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_1/Use_unisim.MB_SRL16E_I1/CLK
Low Pulse Width   Slow    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X98Y106   design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_2/Use_unisim.MB_SRL16E_I1/CLK
Low Pulse Width   Slow    SRLC16E/CLK  n/a            0.532         16.666      16.134     SLICE_X101Y91   design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I/Compare[2].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK
Low Pulse Width   Slow    SRLC16E/CLK  n/a            0.532         16.666      16.134     SLICE_X101Y93   design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I/Compare[3].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK
Low Pulse Width   Slow    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X98Y106   design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_1/Use_unisim.MB_SRL16E_I1/CLK
Low Pulse Width   Slow    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X98Y106   design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_2/Use_unisim.MB_SRL16E_I1/CLK
Low Pulse Width   Slow    SRLC16E/CLK  n/a            0.532         16.666      16.134     SLICE_X101Y94   design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I/Compare[4].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK
Low Pulse Width   Slow    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_1/Use_unisim.MB_SRL16E_I1/CLK
Low Pulse Width   Slow    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_3/Use_unisim.MB_SRL16E_I1/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y111  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y108  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y108  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_1/Use_unisim.MB_SRL16E_I1/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_3/Use_unisim.MB_SRL16E_I1/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_4/Use_unisim.MB_SRL16E_I1/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[1].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[5].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1/CLK
High Pulse Width  Fast    SRL16E/CLK   n/a            0.532         16.666      16.134     SLICE_X101Y100  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1/CLK



---------------------------------------------------------------------------------------------------
From Clock:  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  To Clock:  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE

Setup :            0  Failing Endpoints,  Worst Slack       31.507ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.117ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       33.058ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             31.507ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.single_Step_TClk_reg/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.532ns  (logic 0.403ns (26.305%)  route 1.129ns (73.694%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        0.001ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.909ns = ( 67.575 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.681ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.444ns (routing 0.055ns, distribution 0.389ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.642    40.454    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X102Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.single_Step_TClk_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.444    67.575    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X102Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.single_Step_TClk_reg/C
                         clock pessimism              4.681    72.256    
                         clock uncertainty           -0.235    72.021    
    SLICE_X102Y97        FDCE (Setup_EFF_SLICEL_C_CE)
                                                     -0.060    71.961    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.single_Step_TClk_reg
  -------------------------------------------------------------------
                         required time                         71.961    
                         arrival time                         -40.454    
  -------------------------------------------------------------------
                         slack                                 31.507    

Slack (MET) :             31.576ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.462ns  (logic 0.417ns (28.523%)  route 1.045ns (71.477%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.910ns = ( 67.576 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.445ns (routing 0.055ns, distribution 0.390ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.114    39.738    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051    39.789 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg[0]_i_1/O
                         net (fo=2, routed)           0.595    40.384    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Command_Reg_En
    SLICE_X102Y99        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.445    67.576    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X102Y99        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[1]/C
                         clock pessimism              4.679    72.255    
                         clock uncertainty           -0.235    72.020    
    SLICE_X102Y99        FDCE (Setup_EFF2_SLICEL_C_CE)
                                                     -0.060    71.960    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         71.960    
                         arrival time                         -40.384    
  -------------------------------------------------------------------
                         slack                                 31.576    

Slack (MET) :             31.578ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.460ns  (logic 0.417ns (28.562%)  route 1.043ns (71.438%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.910ns = ( 67.576 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.445ns (routing 0.055ns, distribution 0.390ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.114    39.738    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051    39.789 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg[0]_i_1/O
                         net (fo=2, routed)           0.593    40.382    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Command_Reg_En
    SLICE_X102Y99        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.445    67.576    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X102Y99        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[0]/C
                         clock pessimism              4.679    72.255    
                         clock uncertainty           -0.235    72.020    
    SLICE_X102Y99        FDCE (Setup_EFF_SLICEL_C_CE)
                                                     -0.060    71.960    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.command_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         71.960    
                         arrival time                         -40.382    
  -------------------------------------------------------------------
                         slack                                 31.578    

Slack (MET) :             31.600ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[4]/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.279ns  (logic 0.403ns (31.509%)  route 0.876ns (68.491%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.158ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.752ns = ( 67.418 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.287ns (routing 0.055ns, distribution 0.232ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.389    40.201    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.287    67.418    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[4]/C
                         clock pessimism              4.679    72.097    
                         clock uncertainty           -0.235    71.862    
    SLICE_X101Y97        FDCE (Setup_EFF2_SLICEM_C_CE)
                                                     -0.061    71.801    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[4]
  -------------------------------------------------------------------
                         required time                         71.801    
                         arrival time                         -40.201    
  -------------------------------------------------------------------
                         slack                                 31.600    

Slack (MET) :             31.600ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.279ns  (logic 0.403ns (31.509%)  route 0.876ns (68.491%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.158ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.752ns = ( 67.418 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.287ns (routing 0.055ns, distribution 0.232ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.389    40.201    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.287    67.418    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[8]/C
                         clock pessimism              4.679    72.097    
                         clock uncertainty           -0.235    71.862    
    SLICE_X101Y97        FDCE (Setup_FFF2_SLICEM_C_CE)
                                                     -0.061    71.801    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[8]
  -------------------------------------------------------------------
                         required time                         71.801    
                         arrival time                         -40.201    
  -------------------------------------------------------------------
                         slack                                 31.600    

Slack (MET) :             31.601ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.278ns  (logic 0.403ns (31.534%)  route 0.875ns (68.466%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.158ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.752ns = ( 67.418 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.287ns (routing 0.055ns, distribution 0.232ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.388    40.200    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.287    67.418    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[0]/C
                         clock pessimism              4.679    72.097    
                         clock uncertainty           -0.235    71.862    
    SLICE_X101Y97        FDCE (Setup_EFF_SLICEM_C_CE)
                                                     -0.061    71.801    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         71.801    
                         arrival time                         -40.200    
  -------------------------------------------------------------------
                         slack                                 31.601    

Slack (MET) :             31.601ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[5]/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.278ns  (logic 0.403ns (31.534%)  route 0.875ns (68.466%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.158ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.752ns = ( 67.418 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.287ns (routing 0.055ns, distribution 0.232ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.388    40.200    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.287    67.418    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[5]/C
                         clock pessimism              4.679    72.097    
                         clock uncertainty           -0.235    71.862    
    SLICE_X101Y97        FDCE (Setup_FFF_SLICEM_C_CE)
                                                     -0.061    71.801    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.control_reg_reg[5]
  -------------------------------------------------------------------
                         required time                         71.801    
                         arrival time                         -40.200    
  -------------------------------------------------------------------
                         slack                                 31.601    

Slack (MET) :             31.627ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.normal_stop_TClk_reg/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.254ns  (logic 0.403ns (32.137%)  route 0.851ns (67.863%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.157ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.753ns = ( 67.419 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.288ns (routing 0.055ns, distribution 0.233ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.364    40.176    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.normal_stop_TClk_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.288    67.419    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y97        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.normal_stop_TClk_reg/C
                         clock pessimism              4.679    72.098    
                         clock uncertainty           -0.235    71.863    
    SLICE_X101Y97        FDCE (Setup_AFF2_SLICEM_C_CE)
                                                     -0.060    71.803    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.normal_stop_TClk_reg
  -------------------------------------------------------------------
                         required time                         71.803    
                         arrival time                         -40.176    
  -------------------------------------------------------------------
                         slack                                 31.627    

Slack (MET) :             31.637ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.force_stop_TClk_reg/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.248ns  (logic 0.403ns (32.292%)  route 0.845ns (67.708%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.756ns = ( 67.422 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.681ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.291ns (routing 0.055ns, distribution 0.236ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.358    40.170    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y98        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.force_stop_TClk_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.291    67.422    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y98        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.force_stop_TClk_reg/C
                         clock pessimism              4.681    72.103    
                         clock uncertainty           -0.235    71.868    
    SLICE_X101Y98        FDCE (Setup_AFF_SLICEM_C_CE)
                                                     -0.061    71.807    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.force_stop_TClk_reg
  -------------------------------------------------------------------
                         required time                         71.807    
                         arrival time                         -40.170    
  -------------------------------------------------------------------
                         slack                                 31.637    

Slack (MET) :             31.671ns  (required time - arrival time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.continue_from_brk_TClk_reg/CE
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            33.333ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@66.666ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        1.201ns  (logic 0.403ns (33.555%)  route 0.798ns (66.444%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.165ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.743ns = ( 67.409 - 66.666 ) 
    Source Clock Delay      (SCD):    5.589ns = ( 38.922 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.681ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      0.489ns (routing 0.069ns, distribution 0.420ns)
  Clock Net Delay (Destination): 0.278ns (routing 0.055ns, distribution 0.223ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.489    38.922    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079    39.001 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.119    39.120    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X101Y106       LUT3 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135    39.255 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Dbg_Reg_En_0[0]_INST_0/O
                         net (fo=4, routed)           0.217    39.472    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[0]
    SLICE_X101Y106       LUT4 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152    39.624 f  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_3/O
                         net (fo=5, routed)           0.151    39.775    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En_0_sn_1
    SLICE_X101Y104       LUT5 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037    39.812 r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.dbg_wakeup_i_i_1/O
                         net (fo=8, routed)           0.311    40.123    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y99        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.continue_from_brk_TClk_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     66.666    66.666 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    66.666 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    67.131 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.278    67.409    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y99        FDCE                                         r  design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.continue_from_brk_TClk_reg/C
                         clock pessimism              4.681    72.090    
                         clock uncertainty           -0.235    71.855    
    SLICE_X101Y99        FDCE (Setup_EFF_SLICEM_C_CE)
                                                     -0.061    71.794    design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.continue_from_brk_TClk_reg
  -------------------------------------------------------------------
                         required time                         71.794    
                         arrival time                         -40.123    
  -------------------------------------------------------------------
                         slack                                 31.671    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.117ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[1]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.335ns  (logic 0.082ns (24.478%)  route 0.253ns (75.523%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.232ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.652ns = ( 38.985 - 33.333 ) 
    Source Clock Delay      (SCD):    0.741ns = ( 34.074 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Net Delay (Source):      0.276ns (routing 0.055ns, distribution 0.221ns)
  Clock Net Delay (Destination): 0.552ns (routing 0.069ns, distribution 0.483ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.276    34.074    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.060    34.134 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.144    34.278    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.022    34.300 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.109    34.409    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X100Y108       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.552    38.985    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X100Y108       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[1]/C  (IS_INVERTED)
                         clock pessimism             -4.679    34.306    
    SLICE_X100Y108       FDCE (Hold_AFF_SLICEL_C_CE)
                                                     -0.014    34.292    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[1]
  -------------------------------------------------------------------
                         required time                        -34.292    
                         arrival time                          34.409    
  -------------------------------------------------------------------
                         slack                                  0.117    

Slack (MET) :             0.196ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@0.000ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise@0.000ns)
  Data Path Delay:        0.248ns  (logic 0.062ns (25.000%)  route 0.186ns (75.000%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.524ns
    Source Clock Delay      (SCD):    0.775ns
    Clock Pessimism Removal (CPR):    4.743ns
  Clock Net Delay (Source):      0.310ns (routing 0.055ns, distribution 0.255ns)
  Clock Net Delay (Destination): 0.424ns (routing 0.069ns, distribution 0.355ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465     0.465 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.310     0.775    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X98Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y108        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     0.814 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/Q
                         net (fo=2, routed)           0.165     0.979    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/completion_ctrl
    SLICE_X98Y108        LUT3 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.023     1.002 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/completion_ctrl[0]_i_1/O
                         net (fo=1, routed)           0.021     1.023    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I_n_35
    SLICE_X98Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                      0.000     0.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100     5.100 r  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.424     5.524    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X98Y108        FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
                         clock pessimism             -4.743     0.781    
    SLICE_X98Y108        FDCE (Hold_HFF_SLICEM_C_D)
                                                      0.046     0.827    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]
  -------------------------------------------------------------------
                         required time                         -0.827    
                         arrival time                           1.023    
  -------------------------------------------------------------------
                         slack                                  0.196    

Slack (MET) :             0.227ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/D
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.279ns  (logic 0.062ns (22.222%)  route 0.217ns (77.777%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.426ns = ( 38.759 - 33.333 ) 
    Source Clock Delay      (SCD):    0.696ns = ( 34.029 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.724ns
  Clock Net Delay (Source):      0.231ns (routing 0.055ns, distribution 0.176ns)
  Clock Net Delay (Destination): 0.326ns (routing 0.069ns, distribution 0.257ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.231    34.029    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y106       FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039    34.068 f  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/Q
                         net (fo=18, routed)          0.150    34.218    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0
    SLICE_X100Y108       LUT1 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.023    34.241 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native_i_1__0/O
                         net (fo=1, routed)           0.067    34.308    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/D_1
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/D
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.326    38.759    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CLK
    SLICE_X100Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C  (IS_INVERTED)
                         clock pessimism             -4.724    34.035    
    SLICE_X100Y106       FDCE (Hold_EFF_SLICEL_C_D)
                                                      0.046    34.081    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native
  -------------------------------------------------------------------
                         required time                        -34.081    
                         arrival time                          34.308    
  -------------------------------------------------------------------
                         slack                                  0.227    

Slack (MET) :             0.229ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[0]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.343ns  (logic 0.082ns (23.907%)  route 0.261ns (76.094%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.129ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.549ns = ( 38.882 - 33.333 ) 
    Source Clock Delay      (SCD):    0.741ns = ( 34.074 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.679ns
  Clock Net Delay (Source):      0.276ns (routing 0.055ns, distribution 0.221ns)
  Clock Net Delay (Destination): 0.449ns (routing 0.069ns, distribution 0.380ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.276    34.074    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.060    34.134 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.144    34.278    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.022    34.300 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.117    34.417    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X101Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.449    38.882    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X101Y106       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[0]/C  (IS_INVERTED)
                         clock pessimism             -4.679    34.203    
    SLICE_X101Y106       FDCE (Hold_EFF_SLICEM_C_CE)
                                                     -0.015    34.188    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[0]
  -------------------------------------------------------------------
                         required time                        -34.188    
                         arrival time                          34.417    
  -------------------------------------------------------------------
                         slack                                  0.229    

Slack (MET) :             0.305ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[3]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.326ns  (logic 0.054ns (16.564%)  route 0.272ns (83.435%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.420ns = ( 38.753 - 33.333 ) 
    Source Clock Delay      (SCD):    0.684ns = ( 34.017 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.708ns
  Clock Net Delay (Source):      0.219ns (routing 0.055ns, distribution 0.164ns)
  Clock Net Delay (Destination): 0.320ns (routing 0.069ns, distribution 0.251ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.219    34.017    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040    34.057 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.110    34.167    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014    34.181 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.162    34.343    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.320    38.753    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[3]/C  (IS_INVERTED)
                         clock pessimism             -4.708    34.045    
    SLICE_X101Y107       FDCE (Hold_EFF2_SLICEM_C_CE)
                                                     -0.007    34.038    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[3]
  -------------------------------------------------------------------
                         required time                        -34.038    
                         arrival time                          34.343    
  -------------------------------------------------------------------
                         slack                                  0.305    

Slack (MET) :             0.305ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[5]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.326ns  (logic 0.054ns (16.564%)  route 0.272ns (83.435%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.420ns = ( 38.753 - 33.333 ) 
    Source Clock Delay      (SCD):    0.684ns = ( 34.017 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.708ns
  Clock Net Delay (Source):      0.219ns (routing 0.055ns, distribution 0.164ns)
  Clock Net Delay (Destination): 0.320ns (routing 0.069ns, distribution 0.251ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.219    34.017    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040    34.057 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.110    34.167    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014    34.181 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.162    34.343    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.320    38.753    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[5]/C  (IS_INVERTED)
                         clock pessimism             -4.708    34.045    
    SLICE_X101Y107       FDCE (Hold_FFF2_SLICEM_C_CE)
                                                     -0.007    34.038    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[5]
  -------------------------------------------------------------------
                         required time                        -34.038    
                         arrival time                          34.343    
  -------------------------------------------------------------------
                         slack                                  0.305    

Slack (MET) :             0.305ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[7]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.326ns  (logic 0.054ns (16.564%)  route 0.272ns (83.435%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.420ns = ( 38.753 - 33.333 ) 
    Source Clock Delay      (SCD):    0.684ns = ( 34.017 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.708ns
  Clock Net Delay (Source):      0.219ns (routing 0.055ns, distribution 0.164ns)
  Clock Net Delay (Destination): 0.320ns (routing 0.069ns, distribution 0.251ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.219    34.017    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040    34.057 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.110    34.167    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014    34.181 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.162    34.343    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.320    38.753    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[7]/C  (IS_INVERTED)
                         clock pessimism             -4.708    34.045    
    SLICE_X101Y107       FDCE (Hold_GFF2_SLICEM_C_CE)
                                                     -0.007    34.038    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[7]
  -------------------------------------------------------------------
                         required time                        -34.038    
                         arrival time                          34.343    
  -------------------------------------------------------------------
                         slack                                  0.305    

Slack (MET) :             0.306ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[2]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.326ns  (logic 0.054ns (16.564%)  route 0.272ns (83.435%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.420ns = ( 38.753 - 33.333 ) 
    Source Clock Delay      (SCD):    0.684ns = ( 34.017 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.708ns
  Clock Net Delay (Source):      0.219ns (routing 0.055ns, distribution 0.164ns)
  Clock Net Delay (Destination): 0.320ns (routing 0.069ns, distribution 0.251ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.219    34.017    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040    34.057 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.110    34.167    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014    34.181 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.162    34.343    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.320    38.753    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[2]/C  (IS_INVERTED)
                         clock pessimism             -4.708    34.045    
    SLICE_X101Y107       FDCE (Hold_EFF_SLICEM_C_CE)
                                                     -0.008    34.037    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[2]
  -------------------------------------------------------------------
                         required time                        -34.037    
                         arrival time                          34.343    
  -------------------------------------------------------------------
                         slack                                  0.306    

Slack (MET) :             0.306ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[4]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.326ns  (logic 0.054ns (16.564%)  route 0.272ns (83.435%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.420ns = ( 38.753 - 33.333 ) 
    Source Clock Delay      (SCD):    0.684ns = ( 34.017 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.708ns
  Clock Net Delay (Source):      0.219ns (routing 0.055ns, distribution 0.164ns)
  Clock Net Delay (Destination): 0.320ns (routing 0.069ns, distribution 0.251ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.219    34.017    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040    34.057 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.110    34.167    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014    34.181 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.162    34.343    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.320    38.753    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[4]/C  (IS_INVERTED)
                         clock pessimism             -4.708    34.045    
    SLICE_X101Y107       FDCE (Hold_FFF_SLICEM_C_CE)
                                                     -0.008    34.037    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[4]
  -------------------------------------------------------------------
                         required time                        -34.037    
                         arrival time                          34.343    
  -------------------------------------------------------------------
                         slack                                  0.306    

Slack (MET) :             0.306ns  (arrival time - required time)
  Source:                 design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Destination:            design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[6]/CE
                            (falling edge-triggered cell FDCE clocked by design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@33.333ns period=66.666ns})
  Path Group:             design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns - design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall@33.333ns)
  Data Path Delay:        0.326ns  (logic 0.054ns (16.564%)  route 0.272ns (83.435%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.420ns = ( 38.753 - 33.333 ) 
    Source Clock Delay      (SCD):    0.684ns = ( 34.017 - 33.333 ) 
    Clock Pessimism Removal (CPR):    4.708ns
  Clock Net Delay (Source):      0.219ns (routing 0.055ns, distribution 0.164ns)
  Clock Net Delay (Destination): 0.320ns (routing 0.069ns, distribution 0.251ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      0.465    33.798 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.219    34.017    design_1_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X101Y105       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y105       FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040    34.057 f  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[3]/Q
                         net (fo=7, routed)           0.110    34.167    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]_0[3]
    SLICE_X100Y106       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014    34.181 r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1/O
                         net (fo=9, routed)           0.162    34.343    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     33.333    33.333 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    33.333 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN2_CONFIG_SITE_INTERNAL_TCK_UPDATE)
                                                      5.100    38.433 f  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
    X3Y1 (CLOCK_ROOT)    net (fo=39, routed)          0.320    38.753    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X101Y107       FDCE                                         r  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[6]/C  (IS_INVERTED)
                         clock pessimism             -4.708    34.045    
    SLICE_X101Y107       FDCE (Hold_GFF_SLICEM_C_CE)
                                                     -0.008    34.037    design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg[6]
  -------------------------------------------------------------------
                         required time                        -34.037    
                         arrival time                          34.343    
  -------------------------------------------------------------------
                         slack                                  0.306    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE
Waveform(ns):       { 0.000 33.333 }
Period(ns):         66.666
Sources:            { design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_E2.BSCANE2_I/UPDATE }

Check Type        Corner  Lib Pin   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X101Y106  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[0]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X100Y108  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[1]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[2]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[3]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[4]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[5]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[6]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]/C
Min Period        n/a     FDCE/C    n/a            0.550         66.666      66.116     SLICE_X98Y108   design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
Min Period        n/a     FDPE/PRE  n/a            0.550         66.666      66.116     SLICE_X100Y106  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sel_n_reg/PRE
Low Pulse Width   Fast    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y106  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[0]/C
Low Pulse Width   Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X100Y108  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[1]/C
Low Pulse Width   Fast    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X100Y108  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[1]/C
Low Pulse Width   Fast    FDPE/PRE  n/a            0.275         33.333      33.058     SLICE_X100Y106  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sel_n_reg/PRE
Low Pulse Width   Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y105  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[0]/C
Low Pulse Width   Fast    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y105  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[0]/C
Low Pulse Width   Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y105  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[1]/C
Low Pulse Width   Fast    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y105  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[1]/C
Low Pulse Width   Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y105  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[2]/C
Low Pulse Width   Fast    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y105  design_1_i/mdm_1/U0/MDM_Core_I1/Use_BSCAN.PORT_Selector_reg[2]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y106  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[0]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[2]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[3]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[4]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[5]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[6]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X101Y107  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[7]/C
High Pulse Width  Slow    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X98Y108   design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
High Pulse Width  Fast    FDCE/C    n/a            0.275         33.333      33.058     SLICE_X98Y108   design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
High Pulse Width  Slow    FDPE/PRE  n/a            0.275         33.333      33.058     SLICE_X100Y106  design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sel_n_reg/PRE



