Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date         : Fri Jan  8 11:06:25 2021
| Host         : Nemesys4 running 64-bit Service Pack 1  (build 7601)
| Command      : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt
| Design       : design_1_wrapper
| Device       : xcku5p
---------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    66 |
|    Minimum number of control sets                        |    66 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |    75 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    66 |
| >= 0 to < 4        |    21 |
| >= 4 to < 6        |    11 |
| >= 6 to < 8        |     4 |
| >= 8 to < 10       |     4 |
| >= 10 to < 12      |     1 |
| >= 12 to < 14      |     0 |
| >= 14 to < 16      |     0 |
| >= 16              |    25 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             301 |           80 |
| No           | No                    | Yes                    |              29 |            8 |
| No           | Yes                   | No                     |             308 |           97 |
| Yes          | No                    | No                     |             173 |           42 |
| Yes          | No                    | Yes                    |              15 |            8 |
| Yes          | Yes                   | No                     |             635 |          161 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|                          Clock Signal                          |                                                                                                Enable Signal                                                                                               |                                                                Set/Reset Signal                                                                | Slice Load Count | Bel Load Count |
+----------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.continue_from_brk_reg_n_0 |                1 |              1 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/capture_1                                 |                1 |              1 |
| ~design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/CE                                                                                                                                          | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Q_0                                                                             |                1 |              1 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0 |                1 |              1 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.force_stop_cmd_i_reg_0    |                1 |              1 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               |                                                                                                                                                                                                            |                                                                                                                                                |                1 |              1 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/start_single_step_reg_n_0                 |                1 |              1 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_BSCAN.PORT_Selector_reg[0]                                                                                                                                          | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sel_with_scan_reset19_out                                                                       |                1 |              1 |
| ~design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               |                                                                                                                                                                                                            | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sel_n                                                                                           |                1 |              1 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Command_Reg_En                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_clear                         |                1 |              2 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Debug_Rst_i0                                                                                                                                |                                                                                                                                                |                2 |              2 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/if_fetch_in_progress_i_1_n_0                                            |                1 |              2 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/single_step_count[0]_i_1_n_0                                                                          | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |                1 |              2 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/MUXCY_I/lopt_13                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/flush_pipe                                                              |                2 |              2 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/is_read_i_1_n_0                                                                                                                                | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0]                                                                              |                1 |              2 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[7].OF_Piperun_Stage/MUXCY_I/lopt_10                                                                                       | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[11].OF_Piperun_Stage/MUXCY_I/wb_exception_i_reg               |                1 |              2 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[7].OF_Piperun_Stage/MUXCY_I/lopt_10                                                                                       |                                                                                                                                                |                1 |              2 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.SYNC_FDRE/E[0]                                                                                                                                    |                                                                                                                                                |                1 |              2 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/dbg_stop_i                                                              |                1 |              3 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_PipeRun_i_reg_0[0]                                                                                                               | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |                3 |              3 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_sleep_i0                                                                                                                         | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_hibernate_i_i_1_n_0                                                  |                1 |              3 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2                                                                                                                                         | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                                |                1 |              4 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                        |                                                                                                                                                |                1 |              4 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/mdm_1/U0/MDM_Core_I1/MDM_SEL                                                                                                                                                                    | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/SEL                                                                                                         |                1 |              4 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/rst_clk_wiz_1_100M/U0/bus_struct_reset[0]                                                                                           |                3 |              4 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear                                                                              |                2 |              4 |
| ~design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               |                                                                                                                                                                                                            | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/SEL                                                                                                         |                1 |              4 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/MDM_Core_I1/p_3_out                                                                                                                                                                    | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/SEL                                                                                                         |                1 |              4 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/bus2ip_addr_i[8]_i_1_n_0                                                                                                                       | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0]                                                                              |                1 |              4 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_Halted                                                                                                                           | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |                4 |              5 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/rst_clk_wiz_1_100M/U0/EXT_LPF/lpf_int                                                                                               |                3 |              5 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/factorial_0/inst/out[6]_i_1_n_0                                                                                                     |                1 |              5 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/rst_clk_wiz_1_100M/U0/SEQ/seq_cnt_en                                                                                                                                                            | design_1_i/rst_clk_wiz_1_100M/U0/SEQ/seq_clr                                                                                                   |                1 |              6 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/E[0]                                                                                                                                                                    |                                                                                                                                                |                2 |              6 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_BSCAN.command_reg[5][0]                                                                                                                                             |                                                                                                                                                |                3 |              6 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_BSCAN.command_reg[5][0]                                                                                                                 |                                                                                                                                                |                3 |              6 |
|  design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Use_BSCAN.PORT_Selector_reg[2][0]                                                                                                           |                                                                                                                                                |                3 |              8 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I/Compare[0].SRLC16E_I/which_pc__0 |                                                                                                                                                |                7 |              8 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter0                                                                                                                                                |                                                                                                                                                |                2 |              8 |
| ~design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Dbg_Update_0               | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command[0]_i_1_n_0                                                                                                                                |                                                                                                                                                |                3 |              8 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/E[0]                                                                                                                                        |                                                                                                                                                |                3 |             10 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/Using_FPGA.Native_1[0]                                                                              | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               12 |             16 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/MUXCY_I/lopt_1                                                                                         | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               10 |             20 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK |                                                                                                                                                                                                            | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_BSCAN.PORT_Selector_reg[0]_0                                                                            |                5 |             23 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_rnw_i_reg[0]                                                                                                                  | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0]                                                                              |               10 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i                                                                                                                                  | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0]                                                                              |                8 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rvalid_i_reg_0                                                                                                                           | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               10 |             32 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Dbg_Instr_TCK                                                                                     |                                                                                                                                                |               10 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/p_1_out                                                                          |                9 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/MUXCY_I/lopt_1                                                                                         |                                                                                                                                                |                4 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/MUXCY_I/lopt_1                                                                                         | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/SR[0]                                                                   |               10 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/MUXCY_I/lopt_13                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/R                                                                       |               15 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[3].OF_Piperun_Stage/MUXCY_I/wb_exception_kind_i_reg[28][0]                                                                | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               10 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/if_fetch_in_progress_reg[0]                                                   | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |                9 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/data_rd_reg[0]_i_1_n_0                                                                                | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               11 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0]                                                                                                                                 | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0]                                                                              |               18 |             32 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/SR[0]                                                                              |               18 |             45 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK | design_1_i/mdm_1/U0/Use_E2.BSCAN_I/Use_BSCAN.PORT_Selector_reg[0]                                                                                                                                          |                                                                                                                                                |               14 |             47 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/MUXCY_I/lopt_13                                                                                        | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               31 |             59 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_rnw_i_reg_0                                                       |               18 |             64 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[42].Instr_Mux_MUXF7/IReady_0                                                            |                                                                                                                                                |                6 |             75 |
|  design_1_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/Ext_JTAG_DRCK |                                                                                                                                                                                                            |                                                                                                                                                |               22 |             78 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Performance_Debug_Control.dbg_state_nohalt_reg[34]                                                                                  |                                                                                                                                                |                8 |            128 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               60 |            144 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[7].OF_Piperun_Stage/MUXCY_I/lopt_10                                                                                       | design_1_i/microblaze_0/U0/MicroBlaze_Core_I/sync_reset                                                                                        |               78 |            218 |
|  design_1_i/clk_wiz_1/inst/clk_out1                            |                                                                                                                                                                                                            |                                                                                                                                                |               60 |            239 |
+----------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+


