Device Usage Statistics Report

### Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
beta | FALSE | build_version | 2552052
date_generated | Fri Jan 8 11:08:09 2021 | os_platform | WIN64
product_version | Vivado v2019.1 (64-bit) | project_id | 69c37fd6f60741fcb52e1bca582c3e7e
project_iteration | 1 | random_id | a47eea47618459a3b67dacc8aed22e13
registration_id | a47eea47618459a3b67dacc8aed22e13 | route_design | TRUE
target_device | xcku5p | target_family | kintexuplus
target_package | ffvb676 | target_speed | -2
tool_flow | Vivado

user_environment
cpu_name | Intel(R) Xeon(R) CPU E5-1650 v3 @ 3.50GHz | cpu_speed | 3491 MHz
os_name | Windows Server 2008 R2 or Windows 7 | os_release | Service Pack 1 (build 7601)
system_ram | 34.000 GB | total_processors | 1

vivado_usage

gui_handlers
applyrsbmultiautomationdialog_checkbox_tree=1 | basedialog_cancel=1 | basedialog_ok=5 | basedialog_yes=2
cmdmsgdialog_ok=1 | coretreetablepanel_core_tree_table=6 | filesetpanel_file_set_panel_tree=9 | flownavigatortreepanel_flow_navigator_tree=3
msgtreepanel_message_view_tree=7 | pacommandnames_create_top_hdl=1 | pacommandnames_regenerate_layout=2 | paviews_project_summary=1
rsbapplyautomationbar_run_block_automation=1 | rsbapplyautomationbar_run_connection_automation=1 | saveprojectutils_save=1 | systembuildermenu_add_ip=1
systembuilderview_add_ip=1

java_command_handlers
createtophdl=1 | customizersbblock=2 | editdelete=1 | regeneratersblayout=2
runbitgen=2 | saversbdesign=2 | showview=1


other_data
guimode=2

project_data
constraintsetcount=0 | core_container=false | currentimplrun=impl_1 | currentsynthesisrun=synth_1
default_library=xil_defaultlib | designmode=RTL | export_simulation_activehdl=0 | export_simulation_ies=0
export_simulation_modelsim=0 | export_simulation_questa=0 | export_simulation_riviera=0 | export_simulation_vcs=0
export_simulation_xsim=0 | implstrategy=Vivado Implementation Defaults | launch_simulation_activehdl=0 | launch_simulation_ies=0
launch_simulation_modelsim=0 | launch_simulation_questa=0 | launch_simulation_riviera=0 | launch_simulation_vcs=0
launch_simulation_xsim=0 | simulator_language=Mixed | srcsetcount=3 | synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog | target_simulator=XSim | totalimplruns=12 | totalsynthesisruns=12


unisim_transformation

post_unisim_transformation
and2b1l=1 | bscane2=1 | bufgce=2 | carry8=21
diffinbuf=1 | fdce=244 | fdpe=7 | fdre=1739
fdse=76 | gnd=217 | ibufctrl=2 | inbuf=1
lut1=29 | lut2=128 | lut3=291 | lut4=193
lut5=399 | lut6=459 | mmcme4_adv=1 | muxf7=111
ramb36e2=8 | ramd32=96 | rams32=32 | srl16e=99
srlc16e=8 | vcc=204

pre_unisim_transformation
and2b1l=1 | bscane2=1 | bufgce=2 | carry8=21
fdce=244 | fdpe=7 | fdre=1739 | fdse=76
gnd=217 | ibuf=1 | ibufds=1 | lut1=29
lut2=128 | lut3=291 | lut4=193 | lut5=319
lut6=379 | lut6_2=80 | mmcme4_adv=1 | muxf7=111
ram32m=16 | ramb36e2=8 | srl16e=99 | srlc16e=8
vcc=204

power_opt_design

command_line_options_spo
-cell_types=default::all | -clocks=default::[not_specified] | -exclude_cells=default::[not_specified] | -include_cells=default::[not_specified]

usage
bram_ports_augmented=0 | bram_ports_newly_gated=0 | bram_ports_total=16 | flow_state=default
slice_registers_augmented=0 | slice_registers_newly_gated=0 | slice_registers_total=1461 | srls_augmented=0
srls_newly_gated=0 | srls_total=100

ip_statistics

IP_Integrator/1
bdsource=USER | core_container=NA | da_axi4_cnt=1 | da_board_cnt=4
da_mb_cnt=1 | iptotal=1 | maxhierdepth=1 | numblks=14
numhdlrefblks=1 | numhierblks=3 | numhlsblks=0 | numnonxlnxblks=0
numpkgbdblks=0 | numreposblks=11 | numsysgenblks=0 | synth_mode=OOC_per_IP
x_iplanguage=VERILOG | x_iplibrary=BlockDiagram | x_ipname=design_1 | x_ipvendor=xilinx.com
x_ipversion=1.00.a

MDM/1
c_addr_size=32 | c_avoid_primitives=0 | c_bscanid=76547328 | c_data_size=32
c_dbg_mem_access=0 | c_dbg_reg_access=0 | c_debug_interface=0 | c_ext_trig_reset_value=0xF1234
c_family=kintexuplus | c_interconnect=2 | c_jtag_chain=2 | c_m_axi_addr_width=32
c_m_axi_data_width=32 | c_m_axi_thread_id_width=1 | c_m_axis_data_width=32 | c_m_axis_id_width=7
c_mb_dbg_ports=1 | c_s_axi_aclk_freq_hz=100000000 | c_s_axi_addr_width=4 | c_s_axi_data_width=32
c_trace_async_reset=0 | c_trace_clk_freq_hz=200000000 | c_trace_clk_out_phase=90 | c_trace_data_width=32
c_trace_id=110 | c_trace_output=0 | c_trace_protocol=1 | c_use_bscan=0
c_use_config_reset=0 | c_use_cross_trigger=0 | c_use_uart=0 | core_container=NA
iptotal=1 | x_ipcorerevision=16 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=mdm | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=3.2

MicroBlaze/1
c_addr_tag_bits=17 | c_allow_dcache_wr=1 | c_allow_icache_wr=1 | c_area_optimized=0
c_async_interrupt=1 | c_async_wakeup=3 | c_avoid_primitives=0 | c_base_vectors=0x0000000000000000
c_branch_target_cache_size=0 | c_cache_byte_size=8192 | c_d_axi=1 | c_d_lmb=1
c_daddr_size=32 | c_data_size=32 | c_dcache_addr_tag=17 | c_dcache_always_used=0
c_dcache_baseaddr=0x0000000000000000 | c_dcache_byte_size=8192 | c_dcache_data_width=0 | c_dcache_force_tag_lutram=0
c_dcache_highaddr=0x000000003FFFFFFF | c_dcache_line_len=4 | c_dcache_use_writeback=0 | c_dcache_victims=0
c_debug_counter_width=32 | c_debug_enabled=1 | c_debug_event_counters=5 | c_debug_external_trace=0
c_debug_interface=0 | c_debug_latency_counters=1 | c_debug_profile_size=0 | c_debug_trace_async_reset=0
c_debug_trace_size=8192 | c_div_zero_exception=0 | c_dynamic_bus_sizing=0 | c_ecc_use_ce_exception=0
c_edge_is_positive=1 | c_endianness=1 | c_family=kintexuplus | c_fault_tolerant=0
c_fpu_exception=0 | c_freq=100000000 | c_fsl_exception=0 | c_fsl_links=0
c_i_axi=0 | c_i_lmb=1 | c_iaddr_size=32 | c_icache_always_used=0
c_icache_baseaddr=0x0000000000000000 | c_icache_data_width=0 | c_icache_force_tag_lutram=0 | c_icache_highaddr=0x000000003FFFFFFF
c_icache_line_len=4 | c_icache_streams=0 | c_icache_victims=0 | c_ill_opcode_exception=0
c_imprecise_exceptions=0 | c_instance=design_1_microblaze_0_0 | c_instr_size=32 | c_interconnect=2
c_interrupt_is_edge=0 | c_lmb_data_size=32 | c_lockstep_master=0 | c_lockstep_slave=0
c_m0_axis_data_width=32 | c_m10_axis_data_width=32 | c_m11_axis_data_width=32 | c_m12_axis_data_width=32
c_m13_axis_data_width=32 | c_m14_axis_data_width=32 | c_m15_axis_data_width=32 | c_m1_axis_data_width=32
c_m2_axis_data_width=32 | c_m3_axis_data_width=32 | c_m4_axis_data_width=32 | c_m5_axis_data_width=32
c_m6_axis_data_width=32 | c_m7_axis_data_width=32 | c_m8_axis_data_width=32 | c_m9_axis_data_width=32
c_m_axi_d_bus_exception=0 | c_m_axi_dc_addr_width=32 | c_m_axi_dc_aruser_width=5 | c_m_axi_dc_awuser_width=5
c_m_axi_dc_buser_width=1 | c_m_axi_dc_data_width=32 | c_m_axi_dc_exclusive_access=0 | c_m_axi_dc_ruser_width=1
c_m_axi_dc_thread_id_width=1 | c_m_axi_dc_user_value=31 | c_m_axi_dc_wuser_width=1 | c_m_axi_dp_addr_width=32
c_m_axi_dp_data_width=32 | c_m_axi_dp_exclusive_access=0 | c_m_axi_dp_thread_id_width=1 | c_m_axi_i_bus_exception=0
c_m_axi_ic_addr_width=32 | c_m_axi_ic_aruser_width=5 | c_m_axi_ic_awuser_width=5 | c_m_axi_ic_buser_width=1
c_m_axi_ic_data_width=32 | c_m_axi_ic_ruser_width=1 | c_m_axi_ic_thread_id_width=1 | c_m_axi_ic_user_value=31
c_m_axi_ic_wuser_width=1 | c_m_axi_ip_addr_width=32 | c_m_axi_ip_data_width=32 | c_m_axi_ip_thread_id_width=1
c_mmu_dtlb_size=4 | c_mmu_itlb_size=2 | c_mmu_privileged_instr=0 | c_mmu_tlb_access=3
c_mmu_zones=16 | c_num_sync_ff_clk=2 | c_num_sync_ff_clk_debug=2 | c_num_sync_ff_clk_irq=1
c_num_sync_ff_dbg_clk=1 | c_num_sync_ff_dbg_trace_clk=2 | c_number_of_pc_brk=1 | c_number_of_rd_addr_brk=0
c_number_of_wr_addr_brk=0 | c_opcode_0x0_illegal=0 | c_optimization=0 | c_pc_width=32
c_piaddr_size=32 | c_pvr=0 | c_pvr_user1=0x00 | c_pvr_user2=0x00000000
c_reset_msr=0x00000000 | c_s0_axis_data_width=32 | c_s10_axis_data_width=32 | c_s11_axis_data_width=32
c_s12_axis_data_width=32 | c_s13_axis_data_width=32 | c_s14_axis_data_width=32 | c_s15_axis_data_width=32
c_s1_axis_data_width=32 | c_s2_axis_data_width=32 | c_s3_axis_data_width=32 | c_s4_axis_data_width=32
c_s5_axis_data_width=32 | c_s6_axis_data_width=32 | c_s7_axis_data_width=32 | c_s8_axis_data_width=32
c_s9_axis_data_width=32 | c_sco=0 | c_unaligned_exceptions=0 | c_use_barrel=0
c_use_branch_target_cache=0 | c_use_config_reset=0 | c_use_dcache=0 | c_use_div=0
c_use_ext_brk=0 | c_use_ext_nm_brk=0 | c_use_extended_fsl_instr=0 | c_use_fpu=0
c_use_hw_mul=0 | c_use_icache=0 | c_use_interrupt=0 | c_use_mmu=0
c_use_msr_instr=0 | c_use_non_secure=0 | c_use_pcmp_instr=0 | c_use_reorder_instr=1
c_use_stack_protection=0 | core_container=NA | iptotal=1 | x_ipcorerevision=1
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=microblaze | x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=11.0

axi_gpio/1
c_all_inputs=0 | c_all_inputs_2=0 | c_all_outputs=0 | c_all_outputs_2=0
c_dout_default=0x00000000 | c_dout_default_2=0x00000000 | c_family=kintexuplus | c_gpio2_width=32
c_gpio_width=32 | c_interrupt_present=0 | c_is_dual=0 | c_s_axi_addr_width=9
c_s_axi_data_width=32 | c_tri_default=0xFFFFFFFF | c_tri_default_2=0xFFFFFFFF | core_container=NA
iptotal=1 | x_ipcorerevision=21 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=axi_gpio | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=2.0

blk_mem_gen_v8_4_3/1
c_addra_width=32 | c_addrb_width=32 | c_algorithm=1 | c_axi_id_width=4
c_axi_slave_type=0 | c_axi_type=1 | c_byte_size=8 | c_common_clk=0
c_count_18k_bram=0 | c_count_36k_bram=8 | c_ctrl_ecc_algo=NONE | c_default_data=0
c_disable_warn_bhv_coll=0 | c_disable_warn_bhv_range=0 | c_elaboration_dir=./ | c_en_deepsleep_pin=0
c_en_ecc_pipe=0 | c_en_rdaddra_chg=0 | c_en_rdaddrb_chg=0 | c_en_safety_ckt=1
c_en_shutdown_pin=0 | c_en_sleep_pin=0 | c_enable_32bit_address=1 | c_est_power_summary=Estimated Power for IP _ 17.246228 mW
c_family=kintexuplus | c_has_axi_id=0 | c_has_ena=1 | c_has_enb=1
c_has_injecterr=0 | c_has_mem_output_regs_a=0 | c_has_mem_output_regs_b=0 | c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 | c_has_regcea=0 | c_has_regceb=0 | c_has_rsta=1
c_has_rstb=1 | c_has_softecc_input_regs_a=0 | c_has_softecc_output_regs_b=0 | c_init_file=design_1_lmb_bram_0.mem
c_init_file_name=no_coe_file_loaded | c_inita_val=0 | c_initb_val=0 | c_interface_type=0
c_load_init_file=0 | c_mem_type=2 | c_mux_pipeline_stages=0 | c_prim_type=1
c_read_depth_a=8192 | c_read_depth_b=8192 | c_read_latency_a=1 | c_read_latency_b=1
c_read_width_a=32 | c_read_width_b=32 | c_rst_priority_a=CE | c_rst_priority_b=CE
c_rstram_a=0 | c_rstram_b=0 | c_sim_collision_check=ALL | c_use_bram_block=1
c_use_byte_wea=1 | c_use_byte_web=1 | c_use_default_data=0 | c_use_ecc=0
c_use_softecc=0 | c_use_uram=0 | c_wea_width=4 | c_web_width=4
c_write_depth_a=8192 | c_write_depth_b=8192 | c_write_mode_a=WRITE_FIRST | c_write_mode_b=WRITE_FIRST
c_write_width_a=32 | c_write_width_b=32 | c_xdevicefamily=kintexuplus | core_container=false
iptotal=1 | x_ipcorerevision=3 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=blk_mem_gen | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=8.4

clk_wiz_v6_0_3_0_0/1
clkin1_period=3.333 | clkin2_period=10.0 | clock_mgr_type=NA | component_name=design_1_clk_wiz_1_0
core_container=NA | enable_axi=0 | feedback_source=FDBK_AUTO | feedback_type=SINGLE
iptotal=1 | manual_override=false | num_out_clk=1 | primitive=MMCM
use_dyn_phase_shift=false | use_dyn_reconfig=false | use_inclk_stopped=false | use_inclk_switchover=false
use_locked=true | use_max_i_jitter=false | use_min_o_jitter=false | use_phase_alignment=false
use_power_down=false | use_reset=true

factorial/1
core_container=NA | iptotal=1 | x_ipcorerevision=1 | x_iplanguage=VERILOG
x_iplibrary=module_ref | x_ipname=factorial | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=1.0

lmb_bram_if_cntlr/1
c_baseaddr=0x0000000000000000 | c_bram_awidth=32 | c_ce_counter_width=0 | c_ce_failing_registers=0
c_ecc=0 | c_ecc_onoff_register=0 | c_ecc_onoff_reset_value=1 | c_ecc_status_registers=0
c_family=kintexuplus | c_fault_inject=0 | c_highaddr=0x0000000000007FFF | c_interconnect=0
c_lmb_awidth=32 | c_lmb_dwidth=32 | c_mask=0x0000000040000000 | c_mask1=0x0000000000800000
c_mask2=0x0000000000800000 | c_mask3=0x0000000000800000 | c_num_lmb=1 | c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 | c_ue_failing_registers=0 | c_write_access=2 | core_container=NA
iptotal=1 | x_ipcorerevision=16 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=4.0

lmb_bram_if_cntlr/2
c_baseaddr=0x0000000000000000 | c_bram_awidth=32 | c_ce_counter_width=0 | c_ce_failing_registers=0
c_ecc=0 | c_ecc_onoff_register=0 | c_ecc_onoff_reset_value=1 | c_ecc_status_registers=0
c_family=kintexuplus | c_fault_inject=0 | c_highaddr=0x0000000000007FFF | c_interconnect=0
c_lmb_awidth=32 | c_lmb_dwidth=32 | c_mask=0x0000000000000000 | c_mask1=0x0000000000800000
c_mask2=0x0000000000800000 | c_mask3=0x0000000000800000 | c_num_lmb=1 | c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 | c_ue_failing_registers=0 | c_write_access=2 | core_container=NA
iptotal=1 | x_ipcorerevision=16 | x_iplanguage=VERILOG | x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com
x_ipversion=4.0

lmb_v10/1
c_ext_reset_high=1 | c_lmb_awidth=32 | c_lmb_dwidth=32 | c_lmb_num_slaves=1
core_container=NA | iptotal=2 | x_ipcorerevision=9 | x_iplanguage=VERILOG
x_iplibrary=ip | x_ipname=lmb_v10 | x_ipproduct=Vivado 2019.1 | x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com | x_ipversion=3.0

proc_sys_reset/1
c_aux_reset_high=0 | c_aux_rst_width=4 | c_ext_reset_high=1 | c_ext_rst_width=4
c_family=kintexuplus | c_num_bus_rst=1 | c_num_interconnect_aresetn=1 | c_num_perp_aresetn=1
c_num_perp_rst=1 | core_container=NA | iptotal=1 | x_ipcorerevision=13
x_iplanguage=VERILOG | x_iplibrary=ip | x_ipname=proc_sys_reset | x_ipproduct=Vivado 2019.1
x_ipsimlanguage=MIXED | x_ipvendor=xilinx.com | x_ipversion=5.0

report_drc

command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -internal=default::[not_specified] | -internal_only=default::[not_specified] | -messages=default::[not_specified]
-name=default::[not_specified] | -no_waivers=default::[not_specified] | -return_string=default::[not_specified] | -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] | -waived=default::[not_specified]

report_methodology

command_line_options
-append=default::[not_specified] | -checks=default::[not_specified] | -fail_on=default::[not_specified] | -force=default::[not_specified]
-format=default::[not_specified] | -messages=default::[not_specified] | -name=default::[not_specified] | -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] | -waived=default::[not_specified]

results
lutar-1=1 | timing-10=1 | timing-9=1

report_power

command_line_options
-advisory=default::[not_specified] | -append=default::[not_specified] | -file=[specified] | -format=default::text
-hier=default::power | -hierarchical_depth=default::4 | -l=default::[not_specified] | -name=default::[not_specified]
-no_propagation=default::[not_specified] | -return_string=default::[not_specified] | -rpx=[specified] | -verbose=default::[not_specified]
-vid=default::[not_specified] | -xpe=default::[not_specified]

usage
airflow=250 (LFM) | ambient_temp=25.0 (C) | bi-dir_toggle=12.500000 | bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) | board_selection=medium (10"x10") | bram=0.003836 | clocks=0.006264
confidence_level_clock_activity=High | confidence_level_design_state=High | confidence_level_device_models=High | confidence_level_internal_activity=Medium
confidence_level_io_activity=Medium | confidence_level_overall=Medium | customer=TBD | customer_class=TBD
devstatic=0.451315 | die=xcku5p-ffvb676-2-e | dsp_output_toggle=12.500000 | dynamic=0.118268
effective_thetaja=1.7 | enable_probability=0.990000 | family=kintexuplus | ff_toggle=12.500000
flow_state=routed | heatsink=medium (Medium Profile) | i/o=0.003186 | input_toggle=12.500000
junction_temp=26.0 (C) | logic=0.003604 | mgtyavcc_dynamic_current=0.000000 | mgtyavcc_static_current=0.000000
mgtyavcc_total_current=0.000000 | mgtyavcc_voltage=0.900000 | mgtyavtt_dynamic_current=0.000000 | mgtyavtt_static_current=0.000000
mgtyavtt_total_current=0.000000 | mgtyavtt_voltage=1.200000 | mgtyvccaux_dynamic_current=0.000000 | mgtyvccaux_static_current=0.000000
mgtyvccaux_total_current=0.000000 | mgtyvccaux_voltage=1.800000 | mmcm=0.098289 | netlist_net_matched=NA
off-chip_power=0.000000 | on-chip_power=0.569583 | output_enable=1.000000 | output_load=0.000000
output_toggle=12.500000 | package=ffvb676 | pct_clock_constrained=12.000000 | pct_inputs_defined=50
platform=nt64 | process=typical | ram_enable=50.000000 | ram_write=50.000000
read_saif=False | set/reset_probability=0.000000 | signal_rate=False | signals=0.003087
simulation_file=None | speedgrade=-2 | static_prob=False | temp_grade=extended
thetajb=2.1 (C/W) | thetasa=2.8 (C/W) | toggle_rate=False | user_board_temp=25.0 (C)
user_effective_thetaja=1.7 | user_junc_temp=26.0 (C) | user_thetajb=2.1 (C/W) | user_thetasa=2.8 (C/W)
vccadc_dynamic_current=0.000000 | vccadc_static_current=0.008000 | vccadc_total_current=0.008000 | vccadc_voltage=1.800000
vccaux_dynamic_current=0.054419 | vccaux_io_dynamic_current=0.001500 | vccaux_io_static_current=0.031297 | vccaux_io_total_current=0.032798
vccaux_io_voltage=1.800000 | vccaux_static_current=0.128471 | vccaux_total_current=0.182889 | vccaux_voltage=1.800000
vccbram_dynamic_current=0.000094 | vccbram_static_current=0.001998 | vccbram_total_current=0.002092 | vccbram_voltage=0.850000
vccint_dynamic_current=0.020058 | vccint_io_dynamic_current=0.000570 | vccint_io_static_current=0.035362 | vccint_io_total_current=0.035932
vccint_io_voltage=0.850000 | vccint_static_current=0.138324 | vccint_total_current=0.158382 | vccint_voltage=0.850000
vcco10_dynamic_current=0.000000 | vcco10_static_current=0.000000 | vcco10_total_current=0.000000 | vcco10_voltage=1.000000
vcco12_dynamic_current=0.000000 | vcco12_static_current=0.000000 | vcco12_total_current=0.000000 | vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 | vcco135_static_current=0.000000 | vcco135_total_current=0.000000 | vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 | vcco15_static_current=0.000000 | vcco15_total_current=0.000000 | vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 | vcco18_static_current=0.000000 | vcco18_total_current=0.000000 | vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 | vcco25_static_current=0.000000 | vcco25_total_current=0.000000 | vcco25_voltage=2.500000
vcco33_dynamic_current=0.000000 | vcco33_static_current=0.000000 | vcco33_total_current=0.000000 | vcco33_voltage=3.300000
version=2019.1

report_utilization

io_standard
analog=0 | analog_se=0 | diff_hstl_i=0 | diff_hstl_i_12=0
diff_hstl_i_18=0 | diff_hstl_i_dci=0 | diff_hstl_i_dci_12=0 | diff_hstl_i_dci_18=0
diff_hsul_12=0 | diff_hsul_12_dci=0 | diff_pod10=0 | diff_pod10_dci=0
diff_pod12=0 | diff_pod12_dci=0 | diff_sstl12=1 | diff_sstl12_dci=0
diff_sstl135=0 | diff_sstl135_dci=0 | diff_sstl135_ii=0 | diff_sstl15=0
diff_sstl15_dci=0 | diff_sstl15_ii=0 | diff_sstl18_i=0 | diff_sstl18_i_dci=0
diff_sstl18_ii=0 | hslvdci_15=0 | hslvdci_18=0 | hstl_i=0
hstl_i_12=0 | hstl_i_18=0 | hstl_i_dci=0 | hstl_i_dci_12=0
hstl_i_dci_18=0 | hsul_12=0 | hsul_12_dci=0 | lvcmos12=0
lvcmos15=0 | lvcmos18=0 | lvcmos25=0 | lvcmos33=1
lvdci_15=0 | lvdci_18=0 | lvds=0 | lvds_25=0
lvpecl=0 | lvttl=0 | mipi_dphy_dci=0 | pod10=0
pod10_dci=0 | pod12=0 | pod12_dci=0 | slvs_400_18=0
slvs_400_25=0 | sstl12=0 | sstl12_dci=0 | sstl135=0
sstl135_dci=0 | sstl135_ii=0 | sstl15=0 | sstl15_dci=0
sstl15_ii=0 | sstl18_i=0 | sstl18_i_dci=0 | sstl18_ii=0
sub_lvds=0

primitives
and2b1l_functional_category=Others | and2b1l_used=1 | bscane2_functional_category=Configuration | bscane2_used=1
bufgce_functional_category=Clock | bufgce_used=2 | carry8_functional_category=CLB | carry8_used=21
diffinbuf_functional_category=I/O | diffinbuf_used=1 | fdce_functional_category=Register | fdce_used=239
fdpe_functional_category=Register | fdpe_used=6 | fdre_functional_category=Register | fdre_used=1142
fdse_functional_category=Register | fdse_used=74 | ibufctrl_functional_category=Others | ibufctrl_used=2
inbuf_functional_category=I/O | inbuf_used=1 | lut1_functional_category=CLB | lut1_used=12
lut2_functional_category=CLB | lut2_used=127 | lut3_functional_category=CLB | lut3_used=285
lut4_functional_category=CLB | lut4_used=176 | lut5_functional_category=CLB | lut5_used=393
lut6_functional_category=CLB | lut6_used=443 | mmcme4_adv_functional_category=Clock | mmcme4_adv_used=1
muxf7_functional_category=CLB | muxf7_used=111 | ramb36e2_functional_category=Block Ram | ramb36e2_used=8
ramd32_functional_category=CLB | ramd32_used=96 | rams32_functional_category=CLB | rams32_used=32
srl16e_functional_category=CLB | srl16e_used=93 | srlc16e_functional_category=CLB | srlc16e_used=7

synthesis

command_line_options
-assert=default::[not_specified] | -bufg=default::12 | -cascade_dsp=default::auto | -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto | -directive=default::default | -fanout_limit=default::10000 | -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto | -gated_clock_conversion=default::off | -generic=default::[not_specified] | -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] | -max_bram=default::-1 | -max_bram_cascade_height=default::-1 | -max_dsp=default::-1
-max_uram=default::-1 | -max_uram_cascade_height=default::-1 | -mode=default::default | -name=default::[not_specified]
-no_lc=default::[not_specified] | -no_srlextract=default::[not_specified] | -no_timing_driven=default::[not_specified] | -part=xcku5p-ffvb676-2-e
-resource_sharing=default::auto | -retiming=default::[not_specified] | -rtl=default::[not_specified] | -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] | -seu_protect=default::none | -sfcu=default::[not_specified] | -shreg_min_size=default::3
-top=design_1_wrapper | -verilog_define=default::[not_specified]

usage
elapsed=00:00:36s | hls_ip=0 | memory_gain=1604.258MB | memory_peak=2030.590MB