#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Fri Jan  8 11:01:41 2021
# Process ID: 2908
# Current directory: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1
# Command line: vivado.exe -log design_1_axi_gpio_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_axi_gpio_0_0.tcl
# Log file: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1/design_1_axi_gpio_0_0.vds
# Journal file: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1\vivado.jou
#-----------------------------------------------------------
source design_1_axi_gpio_0_0.tcl -notrace
Command: synth_design -top design_1_axi_gpio_0_0 -part xcku5p-ffvb676-2-e -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcku5p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcku5p'
INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-e
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 6580 
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Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1447.633 ; gain = 58.695
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INFO: [Synth 8-638] synthesizing module 'design_1_axi_gpio_0_0' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86]
	Parameter C_FAMILY bound to: kintexuplus - type: string 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO2_WIDTH bound to: 32 - type: integer 
	Parameter C_ALL_INPUTS bound to: 0 - type: integer 
	Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer 
	Parameter C_ALL_OUTPUTS bound to: 0 - type: integer 
	Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer 
	Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer 
	Parameter C_DOUT_DEFAULT bound to: 32'b00000000000000000000000000000000 
	Parameter C_TRI_DEFAULT bound to: 32'b11111111111111111111111111111111 
	Parameter C_IS_DUAL bound to: 0 - type: integer 
	Parameter C_DOUT_DEFAULT_2 bound to: 32'b00000000000000000000000000000000 
	Parameter C_TRI_DEFAULT_2 bound to: 32'b11111111111111111111111111111111 
INFO: [Synth 8-3491] module 'axi_gpio' declared at 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1265' bound to instance 'U0' of component 'axi_gpio' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:172]
INFO: [Synth 8-638] synthesizing module 'axi_gpio' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
	Parameter C_FAMILY bound to: kintexuplus - type: string 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO2_WIDTH bound to: 32 - type: integer 
	Parameter C_ALL_INPUTS bound to: 0 - type: integer 
	Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer 
	Parameter C_ALL_OUTPUTS bound to: 0 - type: integer 
	Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer 
	Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer 
	Parameter C_DOUT_DEFAULT bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT bound to: -1 - type: integer 
	Parameter C_IS_DUAL bound to: 0 - type: integer 
	Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer 
INFO: [Synth 8-638] synthesizing module 'axi_lite_ipif' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
	Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_ADDR_WIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000000111111111 
	Parameter C_USE_WSTRB bound to: 0 - type: integer 
	Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer 
	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 
	Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 
	Parameter C_FAMILY bound to: kintexuplus - type: string 
INFO: [Synth 8-638] synthesizing module 'slave_attachment' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 
	Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 
	Parameter C_IPIF_ABUS_WIDTH bound to: 9 - type: integer 
	Parameter C_IPIF_DBUS_WIDTH bound to: 32 - type: integer 
	Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer 
	Parameter C_USE_WSTRB bound to: 0 - type: integer 
	Parameter C_DPHASE_TIMEOUT bound to: 8 - type: integer 
	Parameter C_FAMILY bound to: kintexuplus - type: string 
INFO: [Synth 8-638] synthesizing module 'address_decoder' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
	Parameter C_BUS_AWIDTH bound to: 9 - type: integer 
	Parameter C_S_AXI_MIN_SIZE bound to: 511 - type: integer 
	Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111 
	Parameter C_ARD_NUM_CE_ARRAY bound to: 32'b00000000000000000000000000000100 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-638] synthesizing module 'pselect_f' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b00 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f' (1#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized0' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b01 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized0' (1#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized1' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b10 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized1' (1#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-638] synthesizing module 'pselect_f__parameterized2' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
	Parameter C_AB bound to: 2 - type: integer 
	Parameter C_AW bound to: 2 - type: integer 
	Parameter C_BAR bound to: 2'b11 
	Parameter C_FAMILY bound to: nofamily - type: string 
INFO: [Synth 8-256] done synthesizing module 'pselect_f__parameterized2' (1#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1534]
INFO: [Synth 8-256] done synthesizing module 'address_decoder' (2#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:1775]
INFO: [Synth 8-226] default block is never used [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2550]
INFO: [Synth 8-256] done synthesizing module 'slave_attachment' (3#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2341]
INFO: [Synth 8-256] done synthesizing module 'axi_lite_ipif' (4#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/66ea/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd:2948]
INFO: [Synth 8-638] synthesizing module 'GPIO_Core' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
	Parameter C_DW bound to: 32 - type: integer 
	Parameter C_AW bound to: 9 - type: integer 
	Parameter C_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_GPIO2_WIDTH bound to: 32 - type: integer 
	Parameter C_MAX_GPIO_WIDTH bound to: 32 - type: integer 
	Parameter C_INTERRUPT_PRESENT bound to: 0 - type: integer 
	Parameter C_DOUT_DEFAULT bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT bound to: -1 - type: integer 
	Parameter C_IS_DUAL bound to: 0 - type: integer 
	Parameter C_ALL_OUTPUTS bound to: 0 - type: integer 
	Parameter C_ALL_OUTPUTS_2 bound to: 0 - type: integer 
	Parameter C_ALL_INPUTS bound to: 0 - type: integer 
	Parameter C_ALL_INPUTS_2 bound to: 0 - type: integer 
	Parameter C_DOUT_DEFAULT_2 bound to: 0 - type: integer 
	Parameter C_TRI_DEFAULT_2 bound to: -1 - type: integer 
	Parameter C_FAMILY bound to: kintexuplus - type: string 
INFO: [Synth 8-226] default block is never used [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:443]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
	Parameter C_CDC_TYPE bound to: 1 - type: integer 
	Parameter C_RESET_STATE bound to: 0 - type: integer 
	Parameter C_SINGLE_BIT bound to: 0 - type: integer 
	Parameter C_FLOP_INPUT bound to: 0 - type: integer 
	Parameter C_VECTOR_WIDTH bound to: 32 - type: integer 
	Parameter C_MTBF_STAGES bound to: 4 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:736]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:772]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:788]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:804]
INFO: [Common 17-14] Message 'Synth 8-113' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (5#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[2].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[3].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[4].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[5].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[6].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[7].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[8].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[9].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[10].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[11].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[12].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[13].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[14].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[15].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[16].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[17].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[18].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[19].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[20].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[21].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[22].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[23].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[24].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[25].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[26].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[27].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[28].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[29].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[30].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
WARNING: [Synth 8-6014] Unused sequential element Not_Dual.ALLOUT0_ND.READ_REG_GEN[31].GPIO_DBus_i_reg was removed.  [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:384]
INFO: [Synth 8-256] done synthesizing module 'GPIO_Core' (6#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:178]
INFO: [Synth 8-256] done synthesizing module 'axi_gpio' (7#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1351]
INFO: [Synth 8-256] done synthesizing module 'design_1_axi_gpio_0_0' (8#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/synth/design_1_axi_gpio_0_0.vhd:86]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_in
WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[1]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[2]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[3]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[4]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[7]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port ABus_Reg[8]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[0]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[1]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[2]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port BE_Reg[3]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[0]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[1]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[2]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[3]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[4]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[5]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[6]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[7]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[8]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[9]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[10]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[11]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[12]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[13]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[14]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[15]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[16]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[17]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[18]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[19]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[20]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[21]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[22]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[23]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[24]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[25]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[26]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[27]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[28]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[29]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[30]
WARNING: [Synth 8-3331] design GPIO_Core has unconnected port GPIO2_IO_I[31]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[0]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[1]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[2]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[3]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[4]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[7]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Address_In_Erly[8]
WARNING: [Synth 8-3331] design address_decoder has unconnected port Bus_RNW
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[3]
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[2]
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[1]
WARNING: [Synth 8-3331] design slave_attachment has unconnected port S_AXI_WSTRB[0]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1509.516 ; gain = 120.578
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1513.375 ; gain = 124.438
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1513.375 ; gain = 124.438
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 192 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_ooc.xdc] for cell 'U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_board.xdc] for cell 'U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0.xdc] for cell 'U0'
Parsing XDC File [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1631.910 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 192 instances were transformed.
  FDR => FDRE: 192 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1631.910 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1631.910 ; gain = 242.973
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcku5p-ffvb676-2-e
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1631.910 ; gain = 242.973
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for U0. (constraint file  C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1631.910 ; gain = 242.973
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'slave_attachment'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 iSTATE2 |                             0001 |                               00
                  iSTATE |                             0010 |                               01
                 iSTATE0 |                             0100 |                               10
                 iSTATE1 |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'slave_attachment'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1631.910 ; gain = 242.973
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 5     
	                9 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                2 Bit    Registers := 3     
	                1 Bit    Registers := 82    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   5 Input     32 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 1     
	   4 Input      4 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 5     
	   7 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 43    
	   4 Input      1 Bit        Muxes := 3     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module pselect_f 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized0 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized1 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module pselect_f__parameterized2 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module address_decoder 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 6     
Module slave_attachment 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	               32 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                2 Bit    Registers := 3     
	                1 Bit    Registers := 7     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 1     
	   4 Input      4 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 5     
	   7 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 4     
	   4 Input      1 Bit        Muxes := 3     
Module GPIO_Core 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 3     
	                1 Bit    Registers := 66    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   5 Input     32 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 35    
Module axi_gpio 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 1     
	                1 Bit    Registers := 3     
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 1824 (col length:96)
BRAMs: 960 (col length: RAMB18 96 RAMB36 48)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
INFO: [Synth 8-4471] merging register 'bus2ip_reset_reg' into 'AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst_reg' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/9c6e/hdl/axi_gpio_v2_0_vh_rfs.vhd:1677]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[3]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[2]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[1]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port s_axi_wstrb[0]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[31]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[30]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[29]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[28]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[27]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[26]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[25]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[24]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[23]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[22]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[21]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[20]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[19]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[18]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[17]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[16]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[15]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[14]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[13]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[12]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[11]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[10]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[9]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[8]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[7]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[6]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[5]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[4]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[3]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[2]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[1]
WARNING: [Synth 8-3331] design axi_gpio has unconnected port gpio2_io_i[0]
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/\AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_bresp_i_reg[1] )
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d5[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d5) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[16].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[17].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[18].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[19].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[20].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[21].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[22].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[23].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[24].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[25].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[26].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[27].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[28].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[29].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[30].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
INFO: [Synth 8-3332] Sequential element (gpio_core_1/Not_Dual.INPUT_DOUBLE_REGS3/GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d6[31].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d6) is unused and will be removed from module axi_gpio.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1631.910 ; gain = 242.973
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 2016.355 ; gain = 627.418
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 2026.723 ; gain = 637.785
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:37 ; elapsed = 00:00:39 . Memory (MB): peak = 2038.246 ; gain = 649.309
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-----+------+
|      |Cell |Count |
+------+-----+------+
|1     |LUT1 |     2|
|2     |LUT2 |    10|
|3     |LUT3 |     7|
|4     |LUT4 |     7|
|5     |LUT5 |   107|
|6     |LUT6 |     7|
|7     |FDR  |   128|
|8     |FDRE |   221|
|9     |FDSE |    33|
+------+-----+------+

Report Instance Areas: 
+------+------------------------------------+-----------------+------+
|      |Instance                            |Module           |Cells |
+------+------------------------------------+-----------------+------+
|1     |top                                 |                 |   522|
|2     |  U0                                |axi_gpio         |   522|
|3     |    AXI_LITE_IPIF_I                 |axi_lite_ipif    |   131|
|4     |      I_SLAVE_ATTACHMENT            |slave_attachment |   131|
|5     |        I_DECODER                   |address_decoder  |    55|
|6     |    gpio_core_1                     |GPIO_Core        |   357|
|7     |      \Not_Dual.INPUT_DOUBLE_REGS3  |cdc_sync         |   128|
+------+------------------------------------+-----------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 36 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:25 ; elapsed = 00:00:34 . Memory (MB): peak = 2043.066 ; gain = 535.594
Synthesis Optimization Complete : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2043.066 ; gain = 654.129
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 128 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2081.762 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 128 instances were transformed.
  FDR => FDRE: 128 instances

INFO: [Common 17-83] Releasing license: Synthesis
211 Infos, 126 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:59 ; elapsed = 00:01:01 . Memory (MB): peak = 2081.762 ; gain = 1666.777
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2081.762 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1/design_1_axi_gpio_0_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_axi_gpio_0_0, cache-ID = f07c908f6ec71c9a
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2081.762 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_axi_gpio_0_0_synth_1/design_1_axi_gpio_0_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file design_1_axi_gpio_0_0_utilization_synth.rpt -pb design_1_axi_gpio_0_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Jan  8 11:02:52 2021...
