<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1 (64-bit)              -->
<!-- SW Build 2552052 on Fri May 24 14:49:42 MDT 2019  -->
<!--                                                         -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.   -->
<!-- May 24 2019                                             -->
<!--                                                         -->
<!-- This file is generated by the software with the Tcl write_mem_info command. -->
<!-- Do not edit this file.                                                      -->

<MemInfo Version="1" Minor="6">
  <Processor Endianness="Little" InstPath="design_1_i/microblaze_0">
    <AddressSpace Name="design_1_i_microblaze_0.design_1_i_microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="32767">
      <BusBlock>
        <BitLane MemType="RAMB36" Placement="X8Y18">
          <DataWidth MSB="7" LSB="4"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X7Y18">
          <DataWidth MSB="3" LSB="0"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X8Y15">
          <DataWidth MSB="15" LSB="12"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X8Y17">
          <DataWidth MSB="11" LSB="8"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X8Y16">
          <DataWidth MSB="23" LSB="20"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X7Y17">
          <DataWidth MSB="19" LSB="16"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X7Y15">
          <DataWidth MSB="31" LSB="28"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
        <BitLane MemType="RAMB36" Placement="X7Y16">
          <DataWidth MSB="27" LSB="24"/>
          <AddressRange Begin="0" End="8191"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>
      </BusBlock>
    </AddressSpace>
  </Processor>
  <Config>
    <Option Name="Part" Val="xcku5p-ffvb676-2-e"/>
  </Config>
  <DRC>
    <Rule Name="RDADDRCHANGE" Val="false"/>
  </DRC>
</MemInfo>
