-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Fri Jan  8 11:02:42 2021
-- Host        : Nemesys4 running 64-bit Service Pack 1  (build 7601)
-- Command     : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_factorial_0_0_sim_netlist.vhdl
-- Design      : design_1_factorial_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xcku5p-ffvb676-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_factorial is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    clk : in STD_LOGIC;
    \in\ : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_factorial;

architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_factorial is
  signal \out[0]_i_1_n_0\ : STD_LOGIC;
  signal \out[1]_i_1_n_0\ : STD_LOGIC;
  signal \out[2]_i_1_n_0\ : STD_LOGIC;
  signal \out[4]_i_1_n_0\ : STD_LOGIC;
  signal \out[6]_i_1_n_0\ : STD_LOGIC;
  signal \out[6]_i_2_n_0\ : STD_LOGIC;
  signal \out[6]_i_3_n_0\ : STD_LOGIC;
  signal \out[6]_i_4_n_0\ : STD_LOGIC;
  signal \out[6]_i_5_n_0\ : STD_LOGIC;
  signal \out[6]_i_6_n_0\ : STD_LOGIC;
  signal \out[6]_i_7_n_0\ : STD_LOGIC;
  signal \out[6]_i_8_n_0\ : STD_LOGIC;
  signal \out[6]_i_9_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \out[0]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \out[1]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \out[2]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \out[6]_i_2\ : label is "soft_lutpair0";
begin
\out[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \in\(1),
      I1 => \in\(2),
      O => \out[0]_i_1_n_0\
    );
\out[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \in\(1),
      I1 => \in\(2),
      O => \out[1]_i_1_n_0\
    );
\out[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \in\(2),
      I1 => \in\(0),
      I2 => \in\(1),
      O => \out[2]_i_1_n_0\
    );
\out[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \in\(2),
      I1 => \in\(1),
      O => \out[4]_i_1_n_0\
    );
\out[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \out[6]_i_3_n_0\,
      I1 => \out[6]_i_4_n_0\,
      I2 => \out[6]_i_5_n_0\,
      O => \out[6]_i_1_n_0\
    );
\out[6]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \in\(1),
      I1 => \in\(0),
      I2 => \in\(2),
      O => \out[6]_i_2_n_0\
    );
\out[6]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \out[6]_i_6_n_0\,
      I1 => \out[6]_i_7_n_0\,
      I2 => \in\(25),
      I3 => \in\(26),
      I4 => \in\(23),
      I5 => \in\(24),
      O => \out[6]_i_3_n_0\
    );
\out[6]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \in\(8),
      I1 => \in\(7),
      I2 => \in\(10),
      I3 => \in\(9),
      I4 => \out[6]_i_8_n_0\,
      O => \out[6]_i_4_n_0\
    );
\out[6]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \in\(16),
      I1 => \in\(15),
      I2 => \in\(18),
      I3 => \in\(17),
      I4 => \out[6]_i_9_n_0\,
      O => \out[6]_i_5_n_0\
    );
\out[6]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \in\(31),
      I1 => \in\(28),
      I2 => \in\(27),
      I3 => \in\(30),
      I4 => \in\(29),
      O => \out[6]_i_6_n_0\
    );
\out[6]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \in\(21),
      I1 => \in\(22),
      I2 => \in\(19),
      I3 => \in\(20),
      O => \out[6]_i_7_n_0\
    );
\out[6]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \in\(5),
      I1 => \in\(6),
      I2 => \in\(3),
      I3 => \in\(4),
      O => \out[6]_i_8_n_0\
    );
\out[6]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \in\(13),
      I1 => \in\(14),
      I2 => \in\(11),
      I3 => \in\(12),
      O => \out[6]_i_9_n_0\
    );
\out_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \out[0]_i_1_n_0\,
      Q => \out\(0),
      R => \out[6]_i_1_n_0\
    );
\out_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \out[1]_i_1_n_0\,
      Q => \out\(1),
      R => \out[6]_i_1_n_0\
    );
\out_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \out[2]_i_1_n_0\,
      Q => \out\(2),
      R => \out[6]_i_1_n_0\
    );
\out_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \out[4]_i_1_n_0\,
      Q => \out\(3),
      R => \out[6]_i_1_n_0\
    );
\out_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \out[6]_i_2_n_0\,
      Q => \out\(4),
      R => \out[6]_i_1_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
  port (
    clk : in STD_LOGIC;
    \in\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \out\ : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "design_1_factorial_0_0,factorial,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
  attribute IP_DEFINITION_SOURCE : string;
  attribute IP_DEFINITION_SOURCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "module_ref";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "factorial,Vivado 2019.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;

architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
  signal \<const0>\ : STD_LOGIC;
  signal \^out\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_clk_wiz_1_0_clk_out1, INSERT_VIP 0";
begin
  \out\(31) <= \<const0>\;
  \out\(30) <= \<const0>\;
  \out\(29) <= \<const0>\;
  \out\(28) <= \<const0>\;
  \out\(27) <= \<const0>\;
  \out\(26) <= \<const0>\;
  \out\(25) <= \<const0>\;
  \out\(24) <= \<const0>\;
  \out\(23) <= \<const0>\;
  \out\(22) <= \<const0>\;
  \out\(21) <= \<const0>\;
  \out\(20) <= \<const0>\;
  \out\(19) <= \<const0>\;
  \out\(18) <= \<const0>\;
  \out\(17) <= \<const0>\;
  \out\(16) <= \<const0>\;
  \out\(15) <= \<const0>\;
  \out\(14) <= \<const0>\;
  \out\(13) <= \<const0>\;
  \out\(12) <= \<const0>\;
  \out\(11) <= \<const0>\;
  \out\(10) <= \<const0>\;
  \out\(9) <= \<const0>\;
  \out\(8) <= \<const0>\;
  \out\(7) <= \<const0>\;
  \out\(6) <= \^out\(5);
  \out\(5) <= \^out\(5);
  \out\(4) <= \^out\(3);
  \out\(3 downto 0) <= \^out\(3 downto 0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_factorial
     port map (
      clk => clk,
      \in\(31 downto 0) => \in\(31 downto 0),
      \out\(4) => \^out\(5),
      \out\(3 downto 0) => \^out\(3 downto 0)
    );
end STRUCTURE;
