// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Fri Jan  8 11:02:42 2021
// Host        : Nemesys4 running 64-bit Service Pack 1  (build 7601)
// Command     : write_verilog -force -mode funcsim
//               c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_factorial_0_0/design_1_factorial_0_0_sim_netlist.v
// Design      : design_1_factorial_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xcku5p-ffvb676-2-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "design_1_factorial_0_0,factorial,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *) 
(* X_CORE_INFO = "factorial,Vivado 2019.1" *) 
(* NotValidForBitStream *)
module design_1_factorial_0_0
   (clk,
    in,
    out);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_clk_wiz_1_0_clk_out1, INSERT_VIP 0" *) input clk;
  input [31:0]in;
  output [31:0]out;

  wire \<const0> ;
  wire clk;
  wire [31:0]in;
  wire [5:0]\^out ;

  assign out[31] = \<const0> ;
  assign out[30] = \<const0> ;
  assign out[29] = \<const0> ;
  assign out[28] = \<const0> ;
  assign out[27] = \<const0> ;
  assign out[26] = \<const0> ;
  assign out[25] = \<const0> ;
  assign out[24] = \<const0> ;
  assign out[23] = \<const0> ;
  assign out[22] = \<const0> ;
  assign out[21] = \<const0> ;
  assign out[20] = \<const0> ;
  assign out[19] = \<const0> ;
  assign out[18] = \<const0> ;
  assign out[17] = \<const0> ;
  assign out[16] = \<const0> ;
  assign out[15] = \<const0> ;
  assign out[14] = \<const0> ;
  assign out[13] = \<const0> ;
  assign out[12] = \<const0> ;
  assign out[11] = \<const0> ;
  assign out[10] = \<const0> ;
  assign out[9] = \<const0> ;
  assign out[8] = \<const0> ;
  assign out[7] = \<const0> ;
  assign out[6] = \^out [5];
  assign out[5] = \^out [5];
  assign out[4] = \^out [3];
  assign out[3:0] = \^out [3:0];
  GND GND
       (.G(\<const0> ));
  design_1_factorial_0_0_factorial inst
       (.clk(clk),
        .in(in),
        .out({\^out [5],\^out [3:0]}));
endmodule

(* ORIG_REF_NAME = "factorial" *) 
module design_1_factorial_0_0_factorial
   (out,
    clk,
    in);
  output [4:0]out;
  input clk;
  input [31:0]in;

  wire clk;
  wire [31:0]in;
  wire [4:0]out;
  wire \out[0]_i_1_n_0 ;
  wire \out[1]_i_1_n_0 ;
  wire \out[2]_i_1_n_0 ;
  wire \out[4]_i_1_n_0 ;
  wire \out[6]_i_1_n_0 ;
  wire \out[6]_i_2_n_0 ;
  wire \out[6]_i_3_n_0 ;
  wire \out[6]_i_4_n_0 ;
  wire \out[6]_i_5_n_0 ;
  wire \out[6]_i_6_n_0 ;
  wire \out[6]_i_7_n_0 ;
  wire \out[6]_i_8_n_0 ;
  wire \out[6]_i_9_n_0 ;

  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \out[0]_i_1 
       (.I0(in[1]),
        .I1(in[2]),
        .O(\out[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \out[1]_i_1 
       (.I0(in[1]),
        .I1(in[2]),
        .O(\out[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \out[2]_i_1 
       (.I0(in[2]),
        .I1(in[0]),
        .I2(in[1]),
        .O(\out[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \out[4]_i_1 
       (.I0(in[2]),
        .I1(in[1]),
        .O(\out[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \out[6]_i_1 
       (.I0(\out[6]_i_3_n_0 ),
        .I1(\out[6]_i_4_n_0 ),
        .I2(\out[6]_i_5_n_0 ),
        .O(\out[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \out[6]_i_2 
       (.I0(in[1]),
        .I1(in[0]),
        .I2(in[2]),
        .O(\out[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \out[6]_i_3 
       (.I0(\out[6]_i_6_n_0 ),
        .I1(\out[6]_i_7_n_0 ),
        .I2(in[25]),
        .I3(in[26]),
        .I4(in[23]),
        .I5(in[24]),
        .O(\out[6]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \out[6]_i_4 
       (.I0(in[8]),
        .I1(in[7]),
        .I2(in[10]),
        .I3(in[9]),
        .I4(\out[6]_i_8_n_0 ),
        .O(\out[6]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \out[6]_i_5 
       (.I0(in[16]),
        .I1(in[15]),
        .I2(in[18]),
        .I3(in[17]),
        .I4(\out[6]_i_9_n_0 ),
        .O(\out[6]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \out[6]_i_6 
       (.I0(in[31]),
        .I1(in[28]),
        .I2(in[27]),
        .I3(in[30]),
        .I4(in[29]),
        .O(\out[6]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \out[6]_i_7 
       (.I0(in[21]),
        .I1(in[22]),
        .I2(in[19]),
        .I3(in[20]),
        .O(\out[6]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \out[6]_i_8 
       (.I0(in[5]),
        .I1(in[6]),
        .I2(in[3]),
        .I3(in[4]),
        .O(\out[6]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \out[6]_i_9 
       (.I0(in[13]),
        .I1(in[14]),
        .I2(in[11]),
        .I3(in[12]),
        .O(\out[6]_i_9_n_0 ));
  FDRE \out_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\out[0]_i_1_n_0 ),
        .Q(out[0]),
        .R(\out[6]_i_1_n_0 ));
  FDRE \out_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\out[1]_i_1_n_0 ),
        .Q(out[1]),
        .R(\out[6]_i_1_n_0 ));
  FDRE \out_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\out[2]_i_1_n_0 ),
        .Q(out[2]),
        .R(\out[6]_i_1_n_0 ));
  FDRE \out_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(\out[4]_i_1_n_0 ),
        .Q(out[3]),
        .R(\out[6]_i_1_n_0 ));
  FDRE \out_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(\out[6]_i_2_n_0 ),
        .Q(out[4]),
        .R(\out[6]_i_1_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
