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        <spirit:parameter>
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              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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      <spirit:description>Local Memory Bus Mirrored Slave interface 5</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
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            <spirit:name>LMB_ABus</spirit:name>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
            <spirit:name>BE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_BE</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>CE</spirit:name>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
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          <spirit:physicalPort>
            <spirit:name>LMB_ReadStrobe</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>READY</spirit:name>
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              <spirit:left spirit:format="long">5</spirit:left>
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          <spirit:logicalPort>
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            <spirit:name>LMB_Rst</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>UE</spirit:name>
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              <spirit:left spirit:format="long">5</spirit:left>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteDBus</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>WRITESTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteStrobe</spirit:name>
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          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:value>
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            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:value>
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            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_5" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 5">false</xilinx:isEnabled>
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      <spirit:name>LMB_Sl_6</spirit:name>
      <spirit:displayName>LMB_Sl_06</spirit:displayName>
      <spirit:description>Local Memory Bus Mirrored Slave interface 6</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
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            <spirit:name>LMB_ABus</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>ADDRSTROBE</spirit:name>
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            <spirit:name>LMB_AddrStrobe</spirit:name>
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            <spirit:name>BE</spirit:name>
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              <spirit:left spirit:format="long">6</spirit:left>
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          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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            <spirit:name>LMB_WriteDBus</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>WRITESTROBE</spirit:name>
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            <spirit:name>LMB_WriteStrobe</spirit:name>
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              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:value>
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              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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      <spirit:description>Local Memory Bus Mirrored Slave interface 7</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
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        <spirit:parameter>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
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        <spirit:parameter>
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              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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      <spirit:name>LMB_Sl_9</spirit:name>
      <spirit:displayName>LMB_Sl_09</spirit:displayName>
      <spirit:description>Local Memory Bus Mirrored Slave interface 9</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
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            <spirit:name>LMB_ABus</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>ADDRSTROBE</spirit:name>
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            <spirit:name>LMB_AddrStrobe</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>BE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_BE</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>CE</spirit:name>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
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          <spirit:physicalPort>
            <spirit:name>LMB_ReadStrobe</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>READY</spirit:name>
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          <spirit:logicalPort>
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            <spirit:name>LMB_Rst</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>UE</spirit:name>
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              <spirit:left spirit:format="long">9</spirit:left>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteDBus</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>WRITESTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteStrobe</spirit:name>
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          <spirit:name>ADDR_WIDTH</spirit:name>
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            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:value>
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            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <xilinx:busInterfaceInfo>
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            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_9" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 9">false</xilinx:isEnabled>
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      <spirit:name>LMB_Sl_10</spirit:name>
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      <spirit:description>Local Memory Bus Mirrored Slave interface 10</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
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            <spirit:name>LMB_ABus</spirit:name>
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          <spirit:logicalPort>
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            <spirit:name>BE</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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            <spirit:name>WRITESTROBE</spirit:name>
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          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:value>
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              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:portMap>
          <spirit:logicalPort>
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        <spirit:parameter>
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          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
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              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <xilinx:busInterfaceInfo>
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      <spirit:displayName>LMB_Sl_12</spirit:displayName>
      <spirit:description>Local Memory Bus Mirrored Slave interface 12</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
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          <spirit:logicalPort>
            <spirit:name>ADDRSTROBE</spirit:name>
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            <spirit:name>BE</spirit:name>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
            <spirit:name>READDBUS</spirit:name>
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          <spirit:physicalPort>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>READSTROBE</spirit:name>
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          <spirit:physicalPort>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
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          <spirit:physicalPort>
            <spirit:name>LMB_Rst</spirit:name>
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          <spirit:logicalPort>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteDBus</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITESTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteStrobe</spirit:name>
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          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_12" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 12">false</xilinx:isEnabled>
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      <spirit:name>LMB_Sl_13</spirit:name>
      <spirit:displayName>LMB_Sl_13</spirit:displayName>
      <spirit:description>Local Memory Bus Mirrored Slave interface 13</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
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          <spirit:logicalPort>
            <spirit:name>ABUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_ABus</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDRSTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_AddrStrobe</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_BE</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>CE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>Sl_CE</spirit:name>
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              <spirit:left spirit:format="long">13</spirit:left>
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          <spirit:logicalPort>
            <spirit:name>READDBUS</spirit:name>
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          <spirit:physicalPort>
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            <spirit:vector>
              <spirit:left spirit:format="long">416</spirit:left>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>READSTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_ReadStrobe</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>READY</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>Sl_Ready</spirit:name>
            <spirit:vector>
              <spirit:left spirit:format="long">13</spirit:left>
              <spirit:right spirit:format="long">13</spirit:right>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>RST</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_Rst</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>UE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>Sl_UE</spirit:name>
            <spirit:vector>
              <spirit:left spirit:format="long">13</spirit:left>
              <spirit:right spirit:format="long">13</spirit:right>
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          <spirit:logicalPort>
            <spirit:name>WAIT</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>Sl_Wait</spirit:name>
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              <spirit:left spirit:format="long">13</spirit:left>
              <spirit:right spirit:format="long">13</spirit:right>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteDBus</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITESTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteStrobe</spirit:name>
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          <spirit:name>ADDR_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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          </spirit:vendorExtensions>
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        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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      <spirit:vendorExtensions>
        <xilinx:busInterfaceInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.LMB_Sl_13" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) > 13">false</xilinx:isEnabled>
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    <spirit:busInterface>
      <spirit:name>LMB_Sl_14</spirit:name>
      <spirit:displayName>LMB_Sl_14</spirit:displayName>
      <spirit:description>Local Memory Bus Mirrored Slave interface 14</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
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            <spirit:name>ABUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_ABus</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>ADDRSTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_AddrStrobe</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>BE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_BE</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>CE</spirit:name>
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              <spirit:left spirit:format="long">14</spirit:left>
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          <spirit:logicalPort>
            <spirit:name>READDBUS</spirit:name>
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              <spirit:left spirit:format="long">448</spirit:left>
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          <spirit:logicalPort>
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          <spirit:physicalPort>
            <spirit:name>LMB_ReadStrobe</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>READY</spirit:name>
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              <spirit:left spirit:format="long">14</spirit:left>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
            <spirit:name>UE</spirit:name>
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            <spirit:name>Sl_UE</spirit:name>
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              <spirit:left spirit:format="long">14</spirit:left>
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              <spirit:left spirit:format="long">14</spirit:left>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteDBus</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITESTROBE</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteStrobe</spirit:name>
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          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:value>
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              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:value>
          <spirit:vendorExtensions>
            <xilinx:parameterInfo>
              <xilinx:parameterUsage>none</xilinx:parameterUsage>
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        <xilinx:busInterfaceInfo>
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      <spirit:description>Local Memory Bus Mirrored Slave interface 15</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb" spirit:version="1.0"/>
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          <spirit:logicalPort>
            <spirit:name>ADDRSTROBE</spirit:name>
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            <spirit:name>LMB_AddrStrobe</spirit:name>
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          <spirit:logicalPort>
            <spirit:name>BE</spirit:name>
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          <spirit:physicalPort>
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          <spirit:logicalPort>
            <spirit:name>CE</spirit:name>
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              <spirit:left spirit:format="long">15</spirit:left>
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          <spirit:logicalPort>
            <spirit:name>READDBUS</spirit:name>
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              <spirit:left spirit:format="long">480</spirit:left>
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          <spirit:logicalPort>
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          <spirit:physicalPort>
            <spirit:name>LMB_ReadStrobe</spirit:name>
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          <spirit:logicalPort>
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              <spirit:left spirit:format="long">15</spirit:left>
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        <spirit:portMap>
          <spirit:logicalPort>
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            <spirit:name>LMB_Rst</spirit:name>
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        <spirit:portMap>
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              <spirit:left spirit:format="long">15</spirit:left>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITEDBUS</spirit:name>
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          <spirit:physicalPort>
            <spirit:name>LMB_WriteDBus</spirit:name>
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        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>WRITESTROBE</spirit:name>
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          <spirit:physicalPort>
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        <spirit:parameter>
          <spirit:name>DATA_WIDTH</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:value>
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            <xilinx:parameterInfo>
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      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="lmb_rtl" spirit:version="1.0"/>
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            <spirit:name>M_AddrStrobe</spirit:name>
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            <spirit:name>READDBUS</spirit:name>
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          <spirit:logicalPort>
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          <spirit:logicalPort>
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          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:value>
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            <xilinx:parameterInfo>
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        <spirit:parameter>
          <spirit:name>READ_WRITE_MODE</spirit:name>
          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:value>
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            <spirit:name>LMB_Clk</spirit:name>
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          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
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          <spirit:name>ASSOCIATED_RESET</spirit:name>
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          <spirit:name>CLK_DOMAIN</spirit:name>
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        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:value>
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            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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    <spirit:busInterface>
      <spirit:name>RST.SYS_Rst</spirit:name>
      <spirit:displayName>SYS_Rst</spirit:displayName>
      <spirit:description>Reset</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
      <spirit:slave/>
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            <spirit:name>RST</spirit:name>
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            <spirit:name>SYS_Rst</spirit:name>
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          <spirit:name>POLARITY</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.POLARITY">ACTIVE_HIGH</spirit:value>
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          <spirit:name>TYPE</spirit:name>
          <spirit:value spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.TYPE">INTERCONNECT</spirit:value>
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        <spirit:parameter>
          <spirit:name>INSERT_VIP</spirit:name>
          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:value>
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            <xilinx:parameterInfo>
              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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      <spirit:name>LMB_Channel</spirit:name>
      <spirit:busInterfaceRef>LMB_M</spirit:busInterfaceRef>
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      <spirit:busInterfaceRef>LMB_Sl_1</spirit:busInterfaceRef>
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      <spirit:busInterfaceRef>LMB_Sl_3</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_4</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_5</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_6</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_7</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_8</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_9</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_10</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_11</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_12</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_13</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_14</spirit:busInterfaceRef>
      <spirit:busInterfaceRef>LMB_Sl_15</spirit:busInterfaceRef>
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    <spirit:views>
      <spirit:view>
        <spirit:name>xilinx_vhdlsynthesis</spirit:name>
        <spirit:displayName>VHDL Synthesis</spirit:displayName>
        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
        <spirit:language>vhdl</spirit:language>
        <spirit:modelName>lmb_v10</spirit:modelName>
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          <spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
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        <spirit:parameters>
          <spirit:parameter>
            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Fri Jan 08 08:01:24 UTC 2021</spirit:value>
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          <spirit:parameter>
            <spirit:name>outputProductCRC</spirit:name>
            <spirit:value>9:83c823d6</spirit:value>
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      <spirit:view>
        <spirit:name>xilinx_synthesisconstraints</spirit:name>
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          <spirit:localName>xilinx_synthesisconstraints_view_fileset</spirit:localName>
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            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Fri Jan 08 08:01:24 UTC 2021</spirit:value>
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            <spirit:name>outputProductCRC</spirit:name>
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      <spirit:view>
        <spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
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        <spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
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            <spirit:value>Fri Jan 08 08:01:24 UTC 2021</spirit:value>
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            <spirit:value>Fri Jan 08 08:01:24 UTC 2021</spirit:value>
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        <spirit:name>xilinx_externalfiles</spirit:name>
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            <spirit:name>GENtimestamp</spirit:name>
            <spirit:value>Fri Jan 08 08:02:48 UTC 2021</spirit:value>
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      <spirit:port>
        <spirit:name>SYS_Rst</spirit:name>
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      <spirit:port>
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      <spirit:port>
        <spirit:name>M_ABus</spirit:name>
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            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
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            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
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          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>M_BE</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
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            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
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          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>Sl_DBus</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) * spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;))) - 1)">31</spirit:right>
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            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
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          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>Sl_Ready</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">0</spirit:right>
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            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
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            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>Sl_Wait</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">0</spirit:right>
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            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
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        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>Sl_UE</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>Sl_CE</spirit:name>
        <spirit:wire>
          <spirit:direction>in</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_NUM_SLAVES&apos;)) - 1)">0</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
          <spirit:driver>
            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
          </spirit:driver>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_ABus</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_AWIDTH&apos;)) - 1)">31</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_ReadStrobe</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_WriteStrobe</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_AddrStrobe</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_ReadDBus</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_WriteDBus</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) - 1)">31</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_Ready</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_Wait</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_UE</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_CE</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
      <spirit:port>
        <spirit:name>LMB_BE</spirit:name>
        <spirit:wire>
          <spirit:direction>out</spirit:direction>
          <spirit:vector>
            <spirit:left spirit:format="long">0</spirit:left>
            <spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_LMB_DWIDTH&apos;)) + 7) / 8) - 1)">3</spirit:right>
          </spirit:vector>
          <spirit:wireTypeDefs>
            <spirit:wireTypeDef>
              <spirit:typeName>std_logic_vector</spirit:typeName>
              <spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
              <spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
            </spirit:wireTypeDef>
          </spirit:wireTypeDefs>
        </spirit:wire>
      </spirit:port>
    </spirit:ports>
    <spirit:modelParameters>
      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
        <spirit:name>C_LMB_NUM_SLAVES</spirit:name>
        <spirit:displayName>LMB Number of Slaves</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_NUM_SLAVES" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>C_LMB_DWIDTH</spirit:name>
        <spirit:displayName>C Lmb Dwidth</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>C_LMB_AWIDTH</spirit:name>
        <spirit:displayName>C Lmb Awidth</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LMB_AWIDTH" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
      </spirit:modelParameter>
      <spirit:modelParameter spirit:dataType="integer">
        <spirit:name>C_EXT_RESET_HIGH</spirit:name>
        <spirit:displayName>C Ext Reset High</spirit:displayName>
        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b">1</spirit:value>
      </spirit:modelParameter>
    </spirit:modelParameters>
  </spirit:model>
  <spirit:choices>
    <spirit:choice>
      <spirit:name>choice_list_6fc15197</spirit:name>
      <spirit:enumeration>32</spirit:enumeration>
    </spirit:choice>
    <spirit:choice>
      <spirit:name>choice_pairs_4873554b</spirit:name>
      <spirit:enumeration spirit:text="false">0</spirit:enumeration>
      <spirit:enumeration spirit:text="true">1</spirit:enumeration>
    </spirit:choice>
  </spirit:choices>
  <spirit:fileSets>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>design_1_ilmb_v10_0.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
      </spirit:file>
      <spirit:file>
        <spirit:name>../../ipshared/78eb/hdl/lmb_v10_v3_0_vh_rfs.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:logicalName>lmb_v10_v3_0_9</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_synthesisconstraints_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>design_1_ilmb_v10_0_ooc.xdc</spirit:name>
        <spirit:userFileType>xdc</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>synth/design_1_ilmb_v10_0.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>../../ipshared/78eb/hdl/lmb_v10_v3_0_vh_rfs.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
        <spirit:logicalName>lmb_v10_v3_0_9</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>sim/design_1_ilmb_v10_0.vhd</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
    <spirit:fileSet>
      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
      <spirit:file>
        <spirit:name>design_1_ilmb_v10_0.dcp</spirit:name>
        <spirit:userFileType>dcp</spirit:userFileType>
        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_ilmb_v10_0_stub.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_ilmb_v10_0_stub.vhdl</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_ilmb_v10_0_sim_netlist.v</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
      <spirit:file>
        <spirit:name>design_1_ilmb_v10_0_sim_netlist.vhdl</spirit:name>
        <spirit:fileType>vhdlSource</spirit:fileType>
        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
      </spirit:file>
    </spirit:fileSet>
  </spirit:fileSets>
  <spirit:description>The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM</spirit:description>
  <spirit:parameters>
    <spirit:parameter>
      <spirit:name>C_LMB_DWIDTH</spirit:name>
      <spirit:displayName>C Lmb Dwidth</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_DWIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="1200" spirit:configGroups="1 LMB">32</spirit:value>
      <spirit:vendorExtensions>
        <xilinx:parameterInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_DWIDTH">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:parameterInfo>
      </spirit:vendorExtensions>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>C_LMB_AWIDTH</spirit:name>
      <spirit:displayName>C Lmb Awidth</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_AWIDTH" spirit:order="1300" spirit:configGroups="1 LMB" spirit:minimum="32" spirit:maximum="64" spirit:rangeType="long">32</spirit:value>
      <spirit:vendorExtensions>
        <xilinx:parameterInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_AWIDTH">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:parameterInfo>
      </spirit:vendorExtensions>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>C_EXT_RESET_HIGH</spirit:name>
      <spirit:displayName>C Ext Reset High</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:choiceRef="choice_pairs_4873554b" spirit:order="1100" spirit:configGroups="1 LMB">1</spirit:value>
      <spirit:vendorExtensions>
        <xilinx:parameterInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_EXT_RESET_HIGH">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:parameterInfo>
      </spirit:vendorExtensions>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>C_LMB_NUM_SLAVES</spirit:name>
      <spirit:displayName>LMB Number of Slaves</spirit:displayName>
      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_LMB_NUM_SLAVES" spirit:order="1000" spirit:configGroups="1 LMB" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
      <spirit:vendorExtensions>
        <xilinx:parameterInfo>
          <xilinx:enablement>
            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.C_LMB_NUM_SLAVES">true</xilinx:isEnabled>
          </xilinx:enablement>
        </xilinx:parameterInfo>
      </spirit:vendorExtensions>
    </spirit:parameter>
    <spirit:parameter>
      <spirit:name>Component_Name</spirit:name>
      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">design_1_ilmb_v10_0</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
  <spirit:vendorExtensions>
    <xilinx:coreExtensions>
      <xilinx:displayName>Local Memory Bus (LMB) 1.0</xilinx:displayName>
      <xilinx:coreRevision>9</xilinx:coreRevision>
      <xilinx:configElementInfos>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valuePermission="bd"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
      </xilinx:configElementInfos>
    </xilinx:coreExtensions>
    <xilinx:packagingInfo>
      <xilinx:xilinxVersion>2019.1</xilinx:xilinxVersion>
      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="dc44e9b7"/>
      <xilinx:checksum xilinx:scope="channels" xilinx:value="7bb81c1f"/>
      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c4c4312b"/>
      <xilinx:checksum xilinx:scope="ports" xilinx:value="f1995a09"/>
      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ff84d2b9"/>
      <xilinx:checksum xilinx:scope="parameters" xilinx:value="e33d80b9"/>
    </xilinx:packagingInfo>
  </spirit:vendorExtensions>
</spirit:component>
