Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date         : Fri Jan  8 11:07:27 2021
| Host         : Nemesys4 running 64-bit Service Pack 1  (build 7601)
| Command      : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx
| Design       : design_1_wrapper
| Device       : xcku5p-ffvb676-2-e
| Speed File   : -2
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 3
+-----------+----------+----------------------------------+------------+
| Rule      | Severity | Description                      | Violations |
+-----------+----------+----------------------------------+------------+
| LUTAR-1   | Warning  | LUT drives async reset alert     | 1          |
| TIMING-9  | Warning  | Unknown CDC Logic                | 1          |
| TIMING-10 | Warning  | Missing property on synchronizer | 1          |
+-----------+----------+----------------------------------+------------+

2. REPORT DETAILS
-----------------
LUTAR-1#1 Warning
LUT drives async reset alert  
LUT cell design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sel_n_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) design_1_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sel_n_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
Related violations: <none>

TIMING-9#1 Warning
Unknown CDC Logic  
One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities
Related violations: <none>

TIMING-10#1 Warning
Missing property on synchronizer  
One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
Related violations: <none>


