// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Fri Jan  8 11:02:42 2021
// Host        : Nemesys4 running 64-bit Service Pack 1  (build 7601)
// Command     : write_verilog -force -mode synth_stub
//               c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_factorial_0_0/design_1_factorial_0_0_stub.v
// Design      : design_1_factorial_0_0
// Purpose     : Stub declaration of top-level module interface
// Device      : xcku5p-ffvb676-2-e
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "factorial,Vivado 2019.1" *)
module design_1_factorial_0_0(clk, in, out)
/* synthesis syn_black_box black_box_pad_pin="clk,in[31:0],out[31:0]" */;
  input clk;
  input [31:0]in;
  output [31:0]out;
endmodule
