-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Fri Jan  8 11:03:33 2021
-- Host        : Nemesys4 running 64-bit Service Pack 1  (build 7601)
-- Command     : write_vhdl -force -mode funcsim
--               c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0_sim_netlist.vhdl
-- Design      : design_1_microblaze_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xcku5p-ffvb676-2-e
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Byte_Doublet_Handle_gti is
  port (
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0\ : out STD_LOGIC;
    wb_read_msb_doublet_sel : out STD_LOGIC;
    \MEM_DataBus_Write_Data_reg[0]_0\ : out STD_LOGIC_VECTOR ( 35 downto 0 );
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    sync_reset : in STD_LOGIC;
    mem_reverse_byteorder_reg_0 : in STD_LOGIC;
    ex_reverse_mem_access : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \MEM_DataBus_Byte_Enable_reg[0]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \mem_byte_selects_reg[0]_0\ : in STD_LOGIC;
    \mem_byte_selects_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    mem_byte_access : in STD_LOGIC;
    mem_doublet_access : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Byte_Doublet_Handle_gti : entity is "Byte_Doublet_Handle_gti";
end design_1_microblaze_0_0_Byte_Doublet_Handle_gti;

architecture STRUCTURE of design_1_microblaze_0_0_Byte_Doublet_Handle_gti is
  signal \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1_n_0\ : STD_LOGIC;
  signal \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1_n_0\ : STD_LOGIC;
  signal \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1_n_0\ : STD_LOGIC;
  signal \mem_byte_selects_reg_n_0_[1]\ : STD_LOGIC;
  signal mem_reverse_byteorder : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1\ : label is "soft_lutpair0";
begin
\MEM_DataBus_Byte_Enable_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => \MEM_DataBus_Byte_Enable_reg[0]_0\(3),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(3),
      R => sync_reset
    );
\MEM_DataBus_Byte_Enable_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => \MEM_DataBus_Byte_Enable_reg[0]_0\(2),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(2),
      R => sync_reset
    );
\MEM_DataBus_Byte_Enable_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => \MEM_DataBus_Byte_Enable_reg[0]_0\(1),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(1),
      R => sync_reset
    );
\MEM_DataBus_Byte_Enable_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => \MEM_DataBus_Byte_Enable_reg[0]_0\(0),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(0),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(31),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(35),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(21),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(25),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(20),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(24),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(19),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(23),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(18),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(22),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(17),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(21),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(16),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(20),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(15),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(19),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(14),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(18),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(13),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(17),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(12),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(16),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(30),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(34),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(11),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(15),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(10),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(14),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(9),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(13),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(8),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(12),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(7),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(11),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(6),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(10),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(5),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(9),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(4),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(8),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(3),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(7),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(2),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(6),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(29),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(33),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(1),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(5),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(0),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(4),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(28),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(32),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(27),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(31),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(26),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(30),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(25),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(29),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(24),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(28),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(23),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(27),
      R => sync_reset
    );
\MEM_DataBus_Write_Data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => D(22),
      Q => \MEM_DataBus_Write_Data_reg[0]_0\(26),
      R => sync_reset
    );
\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => p_0_in,
      I1 => mem_doublet_access,
      I2 => mem_reverse_byteorder,
      O => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1_n_0\
    );
\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0\,
      D => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1_n_0\,
      Q => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0\,
      R => sync_reset
    );
\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C8CD"
    )
        port map (
      I0 => mem_byte_access,
      I1 => p_0_in,
      I2 => mem_doublet_access,
      I3 => mem_reverse_byteorder,
      O => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1_n_0\
    );
\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8B"
    )
        port map (
      I0 => \mem_byte_selects_reg_n_0_[1]\,
      I1 => mem_byte_access,
      I2 => mem_reverse_byteorder,
      O => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1_n_0\
    );
\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0\,
      D => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1_n_0\,
      Q => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0\(1),
      R => sync_reset
    );
\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0\,
      D => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1_n_0\,
      Q => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0\(0),
      R => sync_reset
    );
\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0\,
      D => mem_reverse_byteorder,
      Q => wb_read_msb_doublet_sel,
      R => sync_reset
    );
\mem_byte_selects_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => \mem_byte_selects_reg[0]_0\,
      Q => p_0_in,
      R => sync_reset
    );
\mem_byte_selects_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => \mem_byte_selects_reg[1]_0\(0),
      Q => \mem_byte_selects_reg_n_0_[1]\,
      R => sync_reset
    );
mem_reverse_byteorder_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => mem_reverse_byteorder_reg_0,
      D => ex_reverse_mem_access,
      Q => mem_reverse_byteorder,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_DAXI_interface is
  port (
    active_access_d1 : out STD_LOGIC;
    active_access : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    MEM_DataBus_Ready : out STD_LOGIC;
    wb_databus_steered_read_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg\ : out STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0\ : out STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1\ : out STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2\ : out STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3\ : out STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4\ : out STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5\ : out STD_LOGIC;
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[23]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[22]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[21]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[20]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[19]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[18]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[17]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[16]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[31]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[30]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[29]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[28]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[27]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[26]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[25]\ : out STD_LOGIC;
    \Use_DLMB.wb_dlmb_valid_read_data_reg[24]\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Clk : in STD_LOGIC;
    active_access_reg_0 : in STD_LOGIC;
    M_AXI_DP_AWVALID_i_reg_0 : in STD_LOGIC;
    M_AXI_DP_WVALID_i_reg_0 : in STD_LOGIC;
    M_AXI_DP_ARVALID_i_reg_0 : in STD_LOGIC;
    DReady : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3031]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wb_read_msb_doublet_sel : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3023]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_RVALID : in STD_LOGIC;
    M_AXI_DP_BVALID : in STD_LOGIC;
    M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_DAXI_interface : entity is "DAXI_interface";
end design_1_microblaze_0_0_DAXI_interface;

architecture STRUCTURE of design_1_microblaze_0_0_DAXI_interface is
  signal MEM_DAXI_Data_Strobe : STD_LOGIC;
  signal \^active_access\ : STD_LOGIC;
  signal mem_access_completed0 : STD_LOGIC;
  signal wb_databus_read_data : STD_LOGIC_VECTOR ( 0 to 31 );
  signal wb_dext_Data_Strobe : STD_LOGIC;
  signal wb_dext_read_data : STD_LOGIC_VECTOR ( 0 to 31 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[16]_INST_0_i_2\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[16]_INST_0_i_3\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[16]_INST_0_i_4\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[16]_INST_0_i_5\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[17]_INST_0_i_2\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[17]_INST_0_i_3\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[17]_INST_0_i_4\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[17]_INST_0_i_5\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[18]_INST_0_i_2\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[18]_INST_0_i_3\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[18]_INST_0_i_4\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[18]_INST_0_i_5\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[19]_INST_0_i_2\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[19]_INST_0_i_3\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[19]_INST_0_i_4\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[19]_INST_0_i_5\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[20]_INST_0_i_2\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[20]_INST_0_i_3\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[20]_INST_0_i_4\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[20]_INST_0_i_5\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[21]_INST_0_i_2\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[21]_INST_0_i_3\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[21]_INST_0_i_4\ : label is "soft_lutpair59";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[21]_INST_0_i_5\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[22]_INST_0_i_2\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[22]_INST_0_i_3\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[22]_INST_0_i_4\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[22]_INST_0_i_5\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[23]_INST_0_i_2\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[23]_INST_0_i_3\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[23]_INST_0_i_4\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \Trace_New_Reg_Value[23]_INST_0_i_5\ : label is "soft_lutpair72";
begin
  active_access <= \^active_access\;
M_AXI_DP_ARVALID_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => M_AXI_DP_ARVALID_i_reg_0,
      Q => D(0),
      R => '0'
    );
M_AXI_DP_AWVALID_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => M_AXI_DP_AWVALID_i_reg_0,
      Q => D(2),
      R => '0'
    );
M_AXI_DP_WVALID_i_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => M_AXI_DP_WVALID_i_reg_0,
      Q => D(1),
      R => '0'
    );
\Trace_New_Reg_Value[0]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(7),
      I1 => wb_dext_read_data(24),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(31),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(0),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[24]\
    );
\Trace_New_Reg_Value[10]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(13),
      I1 => wb_dext_read_data(18),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(21),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(10),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[18]\
    );
\Trace_New_Reg_Value[11]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(12),
      I1 => wb_dext_read_data(19),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(20),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(11),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[19]\
    );
\Trace_New_Reg_Value[12]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(11),
      I1 => wb_dext_read_data(20),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(19),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(12),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[20]\
    );
\Trace_New_Reg_Value[13]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(10),
      I1 => wb_dext_read_data(21),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(18),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(13),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[21]\
    );
\Trace_New_Reg_Value[14]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(9),
      I1 => wb_dext_read_data(22),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(17),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(14),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[22]\
    );
\Trace_New_Reg_Value[15]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(8),
      I1 => wb_dext_read_data(23),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(16),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(15),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[23]\
    );
\Trace_New_Reg_Value[16]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(8),
      I1 => wb_databus_read_data(0),
      I2 => wb_databus_read_data(24),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(16),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg\
    );
\Trace_New_Reg_Value[16]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(23),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(8),
      O => wb_databus_read_data(8)
    );
\Trace_New_Reg_Value[16]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(31),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(0),
      O => wb_databus_read_data(0)
    );
\Trace_New_Reg_Value[16]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(7),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(24),
      O => wb_databus_read_data(24)
    );
\Trace_New_Reg_Value[16]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(15),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(16),
      O => wb_databus_read_data(16)
    );
\Trace_New_Reg_Value[17]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(9),
      I1 => wb_databus_read_data(1),
      I2 => wb_databus_read_data(25),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(17),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0\
    );
\Trace_New_Reg_Value[17]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(22),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(9),
      O => wb_databus_read_data(9)
    );
\Trace_New_Reg_Value[17]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(30),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(1),
      O => wb_databus_read_data(1)
    );
\Trace_New_Reg_Value[17]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(6),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(25),
      O => wb_databus_read_data(25)
    );
\Trace_New_Reg_Value[17]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(14),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(17),
      O => wb_databus_read_data(17)
    );
\Trace_New_Reg_Value[18]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(10),
      I1 => wb_databus_read_data(2),
      I2 => wb_databus_read_data(26),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(18),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1\
    );
\Trace_New_Reg_Value[18]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(21),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(10),
      O => wb_databus_read_data(10)
    );
\Trace_New_Reg_Value[18]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(29),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(2),
      O => wb_databus_read_data(2)
    );
\Trace_New_Reg_Value[18]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(5),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(26),
      O => wb_databus_read_data(26)
    );
\Trace_New_Reg_Value[18]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(13),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(18),
      O => wb_databus_read_data(18)
    );
\Trace_New_Reg_Value[19]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(11),
      I1 => wb_databus_read_data(3),
      I2 => wb_databus_read_data(27),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(19),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2\
    );
\Trace_New_Reg_Value[19]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(20),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(11),
      O => wb_databus_read_data(11)
    );
\Trace_New_Reg_Value[19]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(28),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(3),
      O => wb_databus_read_data(3)
    );
\Trace_New_Reg_Value[19]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(4),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(27),
      O => wb_databus_read_data(27)
    );
\Trace_New_Reg_Value[19]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(12),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(19),
      O => wb_databus_read_data(19)
    );
\Trace_New_Reg_Value[1]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(6),
      I1 => wb_dext_read_data(25),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(30),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(1),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[25]\
    );
\Trace_New_Reg_Value[20]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(12),
      I1 => wb_databus_read_data(4),
      I2 => wb_databus_read_data(28),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(20),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3\
    );
\Trace_New_Reg_Value[20]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(19),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(12),
      O => wb_databus_read_data(12)
    );
\Trace_New_Reg_Value[20]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(27),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(4),
      O => wb_databus_read_data(4)
    );
\Trace_New_Reg_Value[20]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(3),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(28),
      O => wb_databus_read_data(28)
    );
\Trace_New_Reg_Value[20]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(11),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(20),
      O => wb_databus_read_data(20)
    );
\Trace_New_Reg_Value[21]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(13),
      I1 => wb_databus_read_data(5),
      I2 => wb_databus_read_data(29),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(21),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4\
    );
\Trace_New_Reg_Value[21]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(18),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(13),
      O => wb_databus_read_data(13)
    );
\Trace_New_Reg_Value[21]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(26),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(5),
      O => wb_databus_read_data(5)
    );
\Trace_New_Reg_Value[21]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(2),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(29),
      O => wb_databus_read_data(29)
    );
\Trace_New_Reg_Value[21]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(10),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(21),
      O => wb_databus_read_data(21)
    );
\Trace_New_Reg_Value[22]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(14),
      I1 => wb_databus_read_data(6),
      I2 => wb_databus_read_data(30),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(22),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5\
    );
\Trace_New_Reg_Value[22]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(17),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(14),
      O => wb_databus_read_data(14)
    );
\Trace_New_Reg_Value[22]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(25),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(6),
      O => wb_databus_read_data(6)
    );
\Trace_New_Reg_Value[22]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(1),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(30),
      O => wb_databus_read_data(30)
    );
\Trace_New_Reg_Value[22]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(9),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(22),
      O => wb_databus_read_data(22)
    );
\Trace_New_Reg_Value[23]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(15),
      I1 => wb_databus_read_data(7),
      I2 => wb_databus_read_data(31),
      I3 => wb_read_msb_doublet_sel,
      I4 => \LOCKSTEP_Out_reg[3023]\,
      I5 => wb_databus_read_data(23),
      O => \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6\
    );
\Trace_New_Reg_Value[23]_INST_0_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(16),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(15),
      O => wb_databus_read_data(15)
    );
\Trace_New_Reg_Value[23]_INST_0_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(24),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(7),
      O => wb_databus_read_data(7)
    );
\Trace_New_Reg_Value[23]_INST_0_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(0),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(31),
      O => wb_databus_read_data(31)
    );
\Trace_New_Reg_Value[23]_INST_0_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => Q(8),
      I1 => wb_dext_Data_Strobe,
      I2 => wb_dext_read_data(23),
      O => wb_databus_read_data(23)
    );
\Trace_New_Reg_Value[24]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(8),
      I1 => wb_databus_read_data(0),
      I2 => wb_databus_read_data(24),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(16),
      O => wb_databus_steered_read_data(7)
    );
\Trace_New_Reg_Value[25]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(9),
      I1 => wb_databus_read_data(1),
      I2 => wb_databus_read_data(25),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(17),
      O => wb_databus_steered_read_data(6)
    );
\Trace_New_Reg_Value[26]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(10),
      I1 => wb_databus_read_data(2),
      I2 => wb_databus_read_data(26),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(18),
      O => wb_databus_steered_read_data(5)
    );
\Trace_New_Reg_Value[27]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(11),
      I1 => wb_databus_read_data(3),
      I2 => wb_databus_read_data(27),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(19),
      O => wb_databus_steered_read_data(4)
    );
\Trace_New_Reg_Value[28]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(12),
      I1 => wb_databus_read_data(4),
      I2 => wb_databus_read_data(28),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(20),
      O => wb_databus_steered_read_data(3)
    );
\Trace_New_Reg_Value[29]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(13),
      I1 => wb_databus_read_data(5),
      I2 => wb_databus_read_data(29),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(21),
      O => wb_databus_steered_read_data(2)
    );
\Trace_New_Reg_Value[2]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(5),
      I1 => wb_dext_read_data(26),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(29),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(2),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[26]\
    );
\Trace_New_Reg_Value[30]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(14),
      I1 => wb_databus_read_data(6),
      I2 => wb_databus_read_data(30),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(22),
      O => wb_databus_steered_read_data(1)
    );
\Trace_New_Reg_Value[31]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0FFAACCF000AACC"
    )
        port map (
      I0 => wb_databus_read_data(15),
      I1 => wb_databus_read_data(7),
      I2 => wb_databus_read_data(31),
      I3 => \LOCKSTEP_Out_reg[3031]\(0),
      I4 => \LOCKSTEP_Out_reg[3031]\(1),
      I5 => wb_databus_read_data(23),
      O => wb_databus_steered_read_data(0)
    );
\Trace_New_Reg_Value[3]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(4),
      I1 => wb_dext_read_data(27),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(28),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(3),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[27]\
    );
\Trace_New_Reg_Value[4]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(3),
      I1 => wb_dext_read_data(28),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(27),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(4),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[28]\
    );
\Trace_New_Reg_Value[5]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(2),
      I1 => wb_dext_read_data(29),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(26),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(5),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[29]\
    );
\Trace_New_Reg_Value[6]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(1),
      I1 => wb_dext_read_data(30),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(25),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(6),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[30]\
    );
\Trace_New_Reg_Value[7]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(0),
      I1 => wb_dext_read_data(31),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(24),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(7),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[31]\
    );
\Trace_New_Reg_Value[8]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(15),
      I1 => wb_dext_read_data(16),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(23),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(8),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[16]\
    );
\Trace_New_Reg_Value[9]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFAFA0EFE0AFA0"
    )
        port map (
      I0 => Q(14),
      I1 => wb_dext_read_data(17),
      I2 => wb_read_msb_doublet_sel,
      I3 => Q(22),
      I4 => wb_dext_Data_Strobe,
      I5 => wb_dext_read_data(9),
      O => \Use_DLMB.wb_dlmb_valid_read_data_reg[17]\
    );
\Using_FPGA.Native_i_2__25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => DReady,
      I1 => MEM_DAXI_Data_Strobe,
      O => MEM_DataBus_Ready
    );
WB_DAXI_Data_Strobe_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => MEM_DAXI_Data_Strobe,
      Q => wb_dext_Data_Strobe,
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(31),
      Q => wb_dext_read_data(0),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(21),
      Q => wb_dext_read_data(10),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(20),
      Q => wb_dext_read_data(11),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(19),
      Q => wb_dext_read_data(12),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(18),
      Q => wb_dext_read_data(13),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(17),
      Q => wb_dext_read_data(14),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(16),
      Q => wb_dext_read_data(15),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(15),
      Q => wb_dext_read_data(16),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(14),
      Q => wb_dext_read_data(17),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(13),
      Q => wb_dext_read_data(18),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(12),
      Q => wb_dext_read_data(19),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(30),
      Q => wb_dext_read_data(1),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(11),
      Q => wb_dext_read_data(20),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(10),
      Q => wb_dext_read_data(21),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(9),
      Q => wb_dext_read_data(22),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(8),
      Q => wb_dext_read_data(23),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(7),
      Q => wb_dext_read_data(24),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(6),
      Q => wb_dext_read_data(25),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(5),
      Q => wb_dext_read_data(26),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(4),
      Q => wb_dext_read_data(27),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(3),
      Q => wb_dext_read_data(28),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(2),
      Q => wb_dext_read_data(29),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(29),
      Q => wb_dext_read_data(2),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(1),
      Q => wb_dext_read_data(30),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(0),
      Q => wb_dext_read_data(31),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(28),
      Q => wb_dext_read_data(3),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(27),
      Q => wb_dext_read_data(4),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(26),
      Q => wb_dext_read_data(5),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(25),
      Q => wb_dext_read_data(6),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(24),
      Q => wb_dext_read_data(7),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(23),
      Q => wb_dext_read_data(8),
      R => sync_reset
    );
\WB_DAXI_Read_Data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => M_AXI_DP_RVALID,
      D => M_AXI_DP_RDATA(22),
      Q => wb_dext_read_data(9),
      R => sync_reset
    );
active_access_d1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^active_access\,
      Q => active_access_d1,
      R => sync_reset
    );
active_access_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => active_access_reg_0,
      Q => \^active_access\,
      R => '0'
    );
mem_access_completed_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => M_AXI_DP_RVALID,
      I1 => M_AXI_DP_BVALID,
      I2 => \^active_access\,
      O => mem_access_completed0
    );
mem_access_completed_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => mem_access_completed0,
      Q => MEM_DAXI_Data_Strobe,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_AND2B1L is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    SRI : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_AND2B1L : entity is "MB_AND2B1L";
end design_1_microblaze_0_0_MB_AND2B1L;

architecture STRUCTURE of design_1_microblaze_0_0_MB_AND2B1L is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.AND2B1L
    generic map(
      IS_SRI_INVERTED => '0'
    )
        port map (
      DI => E(0),
      O => D(0),
      SRI => SRI
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_311 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_311 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_311;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_311 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_314 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_314 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_314;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_314 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_317 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_317 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_317;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_317 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_320 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_320 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_320;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_320 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_323 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_323 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_323;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_323 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_326 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_326 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_326;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_326 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_329 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_329 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_329;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_329 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_332 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_332 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_332;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_332 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_335 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_335 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_335;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_335 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_338 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_338 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_338;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_338 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_341 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_341 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_341;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_341 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_344 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_344 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_344;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_344 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_347 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_347 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_347;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_347 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_350 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_350 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_350;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_350 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_353 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_353 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_353;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_353 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_356 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_356 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_356;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_356 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_359 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_359 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_359;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_359 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_362 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_362 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_362;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_362 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_365 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_365 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_365;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_365 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_368 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_368 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_368;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_368 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_371 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_371 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_371;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_371 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_374 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_374 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_374;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_374 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_377 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_377 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_377;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_377 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_380 is
  port (
    DI : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    O5 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_380 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_380;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_380 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => O5,
      Q => DI,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_383 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_383 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_383;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_383 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_386 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_386 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_386;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_386 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_389 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_389 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_389;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_389 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_392 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_392 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_392;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_392 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_395 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_395 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_395;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_395 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_398 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_398 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_398;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_398 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDE_401 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDE_401 : entity is "MB_FDE";
end design_1_microblaze_0_0_MB_FDE_401;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDE_401 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDE";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => \Using_FPGA.Native_2\,
      Q => \Using_FPGA.Native_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR is
  port (
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    I0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR is
  signal \Using_FPGA.Native_i_1__95_n_0\ : STD_LOGIC;
  signal \of_clear_MSR_BIP__0\ : STD_LOGIC;
  signal of_clear_MSR_BIP_hold_s : STD_LOGIC;
  signal of_set_MSR_EE1 : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA.Native_i_1__95_n_0\,
      Q => of_clear_MSR_BIP_hold_s,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFA2000000"
    )
        port map (
      I0 => of_set_MSR_EE1,
      I1 => \Using_FPGA.Native_0\,
      I2 => \Using_FPGA.Native_1\,
      I3 => \Using_FPGA.Native_2\,
      I4 => I0,
      I5 => of_clear_MSR_BIP_hold_s,
      O => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\
    );
\Using_FPGA.Native_i_1__95\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00EA"
    )
        port map (
      I0 => of_clear_MSR_BIP_hold_s,
      I1 => \of_clear_MSR_BIP__0\,
      I2 => E(0),
      I3 => \Using_FPGA.Native_3\,
      O => \Using_FPGA.Native_i_1__95_n_0\
    );
\Using_FPGA.Native_i_2__23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80880000"
    )
        port map (
      I0 => I0,
      I1 => \Using_FPGA.Native_2\,
      I2 => \Using_FPGA.Native_1\,
      I3 => \Using_FPGA.Native_0\,
      I4 => of_set_MSR_EE1,
      O => \of_clear_MSR_BIP__0\
    );
\Using_FPGA.Native_i_2__82\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => Q(1),
      I1 => Q(4),
      I2 => Q(3),
      I3 => Q(0),
      I4 => Q(5),
      I5 => Q(2),
      O => of_set_MSR_EE1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_exception_no_load_store_mask : in STD_LOGIC;
    Clk : in STD_LOGIC;
    mem_exception_from_ex : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE is
  signal Q2_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_exception_no_load_store_mask,
      Q => Q2_out,
      R => sync_reset
    );
\wb_exception_kind_i[28]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => mem_exception_from_ex,
      I1 => Q2_out,
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_456 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_456 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_456;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_456 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => EX_Fwd(0),
      Q => \Using_FPGA.Native_0\(0),
      R => R
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_457 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_457 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_457;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_457 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 10 to 10 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(10),
      R => R
    );
\WB_MEM_Result[10]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(10),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_458 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_458 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_458;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_458 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 11 to 11 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(11),
      R => R
    );
\WB_MEM_Result[11]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(11),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_459 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_459 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_459;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_459 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 12 to 12 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(12),
      R => R
    );
\WB_MEM_Result[12]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(12),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_460 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_460 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_460;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_460 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 13 to 13 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(13),
      R => R
    );
\WB_MEM_Result[13]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(13),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_461 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_461 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_461;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_461 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 14 to 14 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(14),
      R => R
    );
\WB_MEM_Result[14]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(14),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_462 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_462 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_462;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_462 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 15 to 15 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(15),
      R => R
    );
\WB_MEM_Result[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(15),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_463 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_463 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_463;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_463 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 16 to 16 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(16),
      R => R
    );
\WB_MEM_Result[16]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(16),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_464 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_464 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_464;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_464 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 17 to 17 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(17),
      R => R
    );
\WB_MEM_Result[17]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(17),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_465 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_465 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_465;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_465 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 18 to 18 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(18),
      R => R
    );
\WB_MEM_Result[18]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(18),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_466 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_466 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_466;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_466 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 19 to 19 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(19),
      R => R
    );
\WB_MEM_Result[19]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(19),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_467 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_467 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_467;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_467 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 1 to 1 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(1),
      R => R
    );
\WB_MEM_Result[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(1),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_468 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_468 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_468;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_468 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 20 to 20 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(20),
      R => R
    );
\WB_MEM_Result[20]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(20),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_469 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_469 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_469;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_469 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 21 to 21 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(21),
      R => R
    );
\WB_MEM_Result[21]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(21),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_470 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_470 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_470;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_470 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 22 to 22 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(22),
      R => R
    );
\WB_MEM_Result[22]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(22),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_471 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_471 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_471;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_471 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 23 to 23 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(23),
      R => R
    );
\WB_MEM_Result[23]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(23),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_472 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_472 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_472;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_472 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 24 to 24 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(24),
      R => R
    );
\WB_MEM_Result[24]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(24),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_473 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_473 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_473;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_473 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 25 to 25 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(25),
      R => R
    );
\WB_MEM_Result[25]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(25),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_474 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_474 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_474;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_474 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 26 to 26 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(26),
      R => R
    );
\WB_MEM_Result[26]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(26),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_475 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_475 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_475;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_475 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 27 to 27 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(27),
      R => R
    );
\WB_MEM_Result[27]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(27),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_476 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_476 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_476;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_476 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => EX_Fwd(0),
      Q => \Using_FPGA.Native_0\(0),
      R => R
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_477 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_477 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_477;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_477 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => EX_Fwd(0),
      Q => \Using_FPGA.Native_0\(0),
      R => R
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_478 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_478 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_478;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_478 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 2 to 2 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(2),
      R => R
    );
\WB_MEM_Result[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(2),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_479 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_479 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_479;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_479 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_1\,
      D => EX_Fwd(0),
      Q => \Using_FPGA.Native_0\(0),
      R => R
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_480 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_480 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_480;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_480 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 31 to 31 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(31),
      R => R
    );
\WB_MEM_Result[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(31),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_481 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_481 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_481;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_481 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(3),
      R => R
    );
\WB_MEM_Result[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(3),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_482 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_482 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_482;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_482 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 4 to 4 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(4),
      R => R
    );
\WB_MEM_Result[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(4),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_483 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_483 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_483;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_483 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 5 to 5 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(5),
      R => R
    );
\WB_MEM_Result[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(5),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_484 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_484 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_484;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_484 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 6 to 6 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(6),
      R => R
    );
\WB_MEM_Result[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(6),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_485 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_485 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_485;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_485 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 7 to 7 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(7),
      R => R
    );
\WB_MEM_Result[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(7),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_486 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_486 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_486;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_486 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 8 to 8 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(8),
      R => R
    );
\WB_MEM_Result[8]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(8),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_487 is
  port (
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_487 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_487;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_487 is
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 9 to 9 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => EX_Fwd(0),
      Q => MEM_EX_Result(9),
      R => R
    );
\WB_MEM_Result[9]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => MEM_EX_Result(9),
      I1 => mem_sel_msr,
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_67 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_exception_no_load_store_mask : in STD_LOGIC;
    Clk : in STD_LOGIC;
    mem_exception_from_ex : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_67 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_67;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_67 is
  signal \Using_FPGA.Native_n_0\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_exception_no_load_store_mask,
      Q => \Using_FPGA.Native_n_0\,
      R => sync_reset
    );
\wb_exception_kind_i[31]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => mem_exception_from_ex,
      I1 => \Using_FPGA.Native_n_0\,
      O => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_68 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \MEM_DataBus_Write_Data_reg[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \MEM_DataBus_Write_Data_reg[0]_0\ : in STD_LOGIC;
    \MEM_DataBus_Write_Data_reg[0]_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_68 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_68;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_68 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Data_Write[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(15),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(7),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(31),
      O => \Using_FPGA.Native_1\(23)
    );
\Data_Write[10]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(5),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(13),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(21),
      O => \Using_FPGA.Native_1\(13)
    );
\Data_Write[11]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(4),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(12),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(20),
      O => \Using_FPGA.Native_1\(12)
    );
\Data_Write[12]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(3),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(11),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(19),
      O => \Using_FPGA.Native_1\(11)
    );
\Data_Write[13]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(2),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(10),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(18),
      O => \Using_FPGA.Native_1\(10)
    );
\Data_Write[14]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(1),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(9),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(17),
      O => \Using_FPGA.Native_1\(9)
    );
\Data_Write[15]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(0),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(8),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(16),
      O => \Using_FPGA.Native_1\(8)
    );
\Data_Write[1]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(14),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(6),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(30),
      O => \Using_FPGA.Native_1\(22)
    );
\Data_Write[24]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(31),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(7),
      O => \Using_FPGA.Native_1\(7)
    );
\Data_Write[25]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(30),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(6),
      O => \Using_FPGA.Native_1\(6)
    );
\Data_Write[26]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(29),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(5),
      O => \Using_FPGA.Native_1\(5)
    );
\Data_Write[27]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(28),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(4),
      O => \Using_FPGA.Native_1\(4)
    );
\Data_Write[28]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(27),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(3),
      O => \Using_FPGA.Native_1\(3)
    );
\Data_Write[29]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(26),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(2),
      O => \Using_FPGA.Native_1\(2)
    );
\Data_Write[2]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(13),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(5),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(29),
      O => \Using_FPGA.Native_1\(21)
    );
\Data_Write[30]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(25),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(1),
      O => \Using_FPGA.Native_1\(1)
    );
\Data_Write[31]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EF40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(24),
      I2 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(0),
      O => \Using_FPGA.Native_1\(0)
    );
\Data_Write[3]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(12),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(4),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(28),
      O => \Using_FPGA.Native_1\(20)
    );
\Data_Write[4]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(11),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(3),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(27),
      O => \Using_FPGA.Native_1\(19)
    );
\Data_Write[5]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(10),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(2),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(26),
      O => \Using_FPGA.Native_1\(18)
    );
\Data_Write[6]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(9),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(1),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(25),
      O => \Using_FPGA.Native_1\(17)
    );
\Data_Write[7]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00EF45FF00EA40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(8),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(0),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(24),
      O => \Using_FPGA.Native_1\(16)
    );
\Data_Write[8]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(7),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(15),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(23),
      O => \Using_FPGA.Native_1\(15)
    );
\Data_Write[9]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DD88CDCDDD88C8C8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \MEM_DataBus_Write_Data_reg[0]\(6),
      I2 => \MEM_DataBus_Write_Data_reg[0]_1\,
      I3 => \MEM_DataBus_Write_Data_reg[0]\(14),
      I4 => \MEM_DataBus_Write_Data_reg[0]_0\,
      I5 => \MEM_DataBus_Write_Data_reg[0]\(22),
      O => \Using_FPGA.Native_1\(14)
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_2\,
      D => \Using_FPGA.Native_3\,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_69 is
  port (
    ex_doublet_access : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_69 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_69;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_69 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => \Using_FPGA.Native_1\,
      Q => ex_doublet_access,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_70 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    mem_is_multi_or_load_instr0 : out STD_LOGIC;
    ex_Sel_SPR_PVR_reg : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_load_store_instr_s : in STD_LOGIC;
    ex_reservation : in STD_LOGIC;
    ex_is_swx_instr_s : in STD_LOGIC;
    p_231_in : in STD_LOGIC;
    ex_is_multi_instr2 : in STD_LOGIC;
    ex_Sel_SPR_PVR : in STD_LOGIC;
    ex_Sel_SPR_BTR : in STD_LOGIC;
    ex_Sel_SPR_EDR : in STD_LOGIC;
    ex_Sel_SPR_ESR : in STD_LOGIC;
    ex_Sel_SPR_FSR : in STD_LOGIC;
    ex_Sel_SPR_SLR : in STD_LOGIC;
    ex_Sel_SPR_SHR : in STD_LOGIC;
    ex_Sel_SPR_EAR : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_70 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_70;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_70 is
  signal MEM_Sel_MEM_Res_I_i_2_n_0 : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of MEM_Sel_MEM_Res_I_i_2 : label is "soft_lutpair25";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of mem_is_multi_or_load_instr_i_1 : label is "soft_lutpair25";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
MEM_Sel_MEM_Res_I_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => ex_Sel_SPR_PVR,
      I1 => ex_Sel_SPR_BTR,
      I2 => MEM_Sel_MEM_Res_I_i_2_n_0,
      I3 => ex_Sel_SPR_EDR,
      I4 => ex_Sel_SPR_ESR,
      I5 => ex_Sel_SPR_FSR,
      O => ex_Sel_SPR_PVR_reg
    );
MEM_Sel_MEM_Res_I_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => ex_Sel_SPR_SLR,
      I1 => \^using_fpga.native_0\,
      I2 => ex_Sel_SPR_SHR,
      I3 => ex_Sel_SPR_EAR,
      O => MEM_Sel_MEM_Res_I_i_2_n_0
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_2\,
      D => \Using_FPGA.Native_3\,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
Write_Strobe_INST_0: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40440000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_load_store_instr_s,
      I2 => ex_reservation,
      I3 => ex_is_swx_instr_s,
      I4 => p_231_in,
      O => \Using_FPGA.Native_1\(0)
    );
mem_is_multi_or_load_instr_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ex_is_multi_instr2,
      I1 => \^using_fpga.native_0\,
      O => mem_is_multi_or_load_instr0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_71 is
  port (
    ex_MSR_Load_LWX_SWX_C : out STD_LOGIC;
    \Using_LWX_SWX_instr.ex_reservation_reg\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_is_swx_instr_s : in STD_LOGIC;
    ex_load_store_instr_s : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    \Using_FPGA.Native_i_2__21\ : in STD_LOGIC;
    p_231_in : in STD_LOGIC;
    ex_reservation : in STD_LOGIC;
    p_227_in : in STD_LOGIC;
    \Using_LWX_SWX_instr.ex_reservation_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_71 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_71;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_71 is
  signal ex_is_lwx_instr_s : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => \Using_FPGA.Native_1\,
      Q => ex_is_lwx_instr_s,
      R => sync_reset
    );
\Using_FPGA.Native_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000E000000000"
    )
        port map (
      I0 => ex_is_lwx_instr_s,
      I1 => ex_is_swx_instr_s,
      I2 => ex_load_store_instr_s,
      I3 => wb_exception,
      I4 => \Using_FPGA.Native_i_2__21\,
      I5 => p_231_in,
      O => ex_MSR_Load_LWX_SWX_C
    );
\Using_LWX_SWX_instr.ex_reservation_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000EA"
    )
        port map (
      I0 => ex_reservation,
      I1 => ex_is_lwx_instr_s,
      I2 => p_227_in,
      I3 => \Using_LWX_SWX_instr.ex_reservation_reg_0\,
      I4 => sync_reset,
      O => \Using_LWX_SWX_instr.ex_reservation_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_72 is
  port (
    ex_is_swx_instr_s : out STD_LOGIC;
    MEM_DataBus_Access_reg : out STD_LOGIC;
    \ex_swx_access__0\ : out STD_LOGIC;
    SRI : out STD_LOGIC;
    wb_exception_i_reg : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    D224_out : in STD_LOGIC;
    Clk : in STD_LOGIC;
    MEM_DataBus_Access_reg_0 : in STD_LOGIC;
    p_227_in : in STD_LOGIC;
    MEM_DataBus_Access_reg_1 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_reservation : in STD_LOGIC;
    p_231_in : in STD_LOGIC;
    D_AS : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    ex_load_store_instr_s : in STD_LOGIC;
    \Using_LWX_SWX_instr.ex_reservation_reg\ : in STD_LOGIC;
    ex_MSR_Set_SW_BIP : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_72 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_72;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_72 is
  signal \^ex_is_swx_instr_s\ : STD_LOGIC;
  signal \^ex_swx_access__0\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  ex_is_swx_instr_s <= \^ex_is_swx_instr_s\;
  \ex_swx_access__0\ <= \^ex_swx_access__0\;
MEM_DataBus_Access_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000C0C000AA"
    )
        port map (
      I0 => MEM_DataBus_Access_reg_0,
      I1 => \^ex_swx_access__0\,
      I2 => p_227_in,
      I3 => MEM_DataBus_Access_reg_1,
      I4 => E(0),
      I5 => sync_reset,
      O => MEM_DataBus_Access_reg
    );
MEM_DataBus_Access_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => ex_reservation,
      I1 => \^ex_is_swx_instr_s\,
      O => \^ex_swx_access__0\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => D224_out,
      Q => \^ex_is_swx_instr_s\,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFF4FFFFFFFFF"
    )
        port map (
      I0 => ex_reservation,
      I1 => \^ex_is_swx_instr_s\,
      I2 => p_231_in,
      I3 => D_AS,
      I4 => wb_exception,
      I5 => ex_load_store_instr_s,
      O => SRI
    );
\Using_LWX_SWX_instr.ex_reservation_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF2F2F2F2F2F2F2"
    )
        port map (
      I0 => wb_exception,
      I1 => \Using_LWX_SWX_instr.ex_reservation_reg\,
      I2 => ex_MSR_Set_SW_BIP,
      I3 => \^ex_is_swx_instr_s\,
      I4 => E(0),
      I5 => p_227_in,
      O => wb_exception_i_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_73 is
  port (
    ex_load_store_instr_s : out STD_LOGIC;
    p_227_in : out STD_LOGIC;
    mem_load_store_access0 : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    p_231_in : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    mem_exception_from_ex : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    ex_reservation : in STD_LOGIC;
    ex_is_swx_instr_s : in STD_LOGIC;
    mem_load_store_access_reg : in STD_LOGIC;
    mem_load_store_access_reg_0 : in STD_LOGIC;
    mem_load_store_access_reg_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_73 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_73;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_73 is
  signal \^ex_load_store_instr_s\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  ex_load_store_instr_s <= \^ex_load_store_instr_s\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => \Using_FPGA.Native_1\,
      Q => \^ex_load_store_instr_s\,
      R => sync_reset
    );
\Using_LWX_SWX_instr.ex_reservation_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"002A0000"
    )
        port map (
      I0 => p_231_in,
      I1 => mem_valid_instr,
      I2 => mem_exception_from_ex,
      I3 => wb_exception,
      I4 => \^ex_load_store_instr_s\,
      O => p_227_in
    );
mem_load_store_access_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A8A8A8A008A8A8A"
    )
        port map (
      I0 => \^ex_load_store_instr_s\,
      I1 => ex_reservation,
      I2 => ex_is_swx_instr_s,
      I3 => mem_load_store_access_reg,
      I4 => mem_load_store_access_reg_0,
      I5 => mem_load_store_access_reg_1,
      O => mem_load_store_access0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_74 is
  port (
    ex_reverse_mem_access : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_74 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_74;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_74 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => \Using_FPGA.Native_1\,
      Q => ex_reverse_mem_access,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDRE_75 is
  port (
    ex_set_bip_reg : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    p_231_in : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_MSR : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDRE_75 : entity is "MB_FDRE";
end design_1_microblaze_0_0_MB_FDRE_75;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDRE_75 is
  signal ex_clear_MSR_BIP_instr_s : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0',
      IS_C_INVERTED => '0',
      IS_D_INVERTED => '0',
      IS_R_INVERTED => '0'
    )
        port map (
      C => Clk,
      CE => \Using_FPGA.Native_0\,
      D => \Using_FPGA.Native_1\,
      Q => ex_clear_MSR_BIP_instr_s,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFA0FFFFBFA00000"
    )
        port map (
      I0 => \Using_FPGA.Native_2\,
      I1 => ex_clear_MSR_BIP_instr_s,
      I2 => p_231_in,
      I3 => \Using_FPGA.Native_3\,
      I4 => E(0),
      I5 => ex_MSR(0),
      O => ex_set_bip_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_112 is
  port (
    addr : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    sel_input_iii_3 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_jump : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    IB_Ready : in STD_LOGIC;
    if_fetch_in_progress : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_112 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_112;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_112 is
  signal \^addr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  addr(0) <= \^addr\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sel_input_iii_3,
      Q => \^addr\(0),
      R => sync_reset
    );
if_fetch_in_progress_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F100FFFFF100F100"
    )
        port map (
      I0 => \^addr\(0),
      I1 => if_sel_input(0),
      I2 => ex_jump,
      I3 => \out\,
      I4 => IB_Ready,
      I5 => if_fetch_in_progress,
      O => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_113 is
  port (
    if_sel_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    addr : out STD_LOGIC_VECTOR ( 0 to 0 );
    if_fetch_in_progress_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    if_fetch_for_timing_optimization1 : out STD_LOGIC;
    if_missed_fetch_reg : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    sel_input_iii_2 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Serial_Dbg_Intf.status_reg_reg[25]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_jump : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    if_fetch_in_progress : in STD_LOGIC;
    IB_Ready : in STD_LOGIC;
    in0 : in STD_LOGIC;
    if_missed_fetch : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_113 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_113;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_113 is
  signal \^using_fpga.native_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^if_sel_input\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of if_missed_fetch_i_1 : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \if_pc[0]_i_1\ : label is "soft_lutpair4";
begin
  \Using_FPGA.Native_0\(1 downto 0) <= \^using_fpga.native_0\(1 downto 0);
  if_sel_input(0) <= \^if_sel_input\(0);
IFetch_INST_0: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFAB00"
    )
        port map (
      I0 => ex_jump,
      I1 => \^if_sel_input\(0),
      I2 => \Serial_Dbg_Intf.status_reg_reg[25]\(0),
      I3 => in0,
      I4 => if_fetch_in_progress,
      O => \^using_fpga.native_0\(1)
    );
I_AS_INST_0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A200A200A200A2A2"
    )
        port map (
      I0 => \out\,
      I1 => if_fetch_in_progress,
      I2 => IB_Ready,
      I3 => ex_jump,
      I4 => \^if_sel_input\(0),
      I5 => \Serial_Dbg_Intf.status_reg_reg[25]\(0),
      O => \^using_fpga.native_0\(0)
    );
\PC_Buffer_reg[3][31]_srl4_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^if_sel_input\(0),
      I1 => \Serial_Dbg_Intf.status_reg_reg[25]\(0),
      O => addr(0)
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sel_input_iii_2,
      Q => \^if_sel_input\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^if_sel_input\(0),
      I1 => \Serial_Dbg_Intf.status_reg_reg[25]\(0),
      O => if_fetch_for_timing_optimization1
    );
if_missed_fetch_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1310"
    )
        port map (
      I0 => IB_Ready,
      I1 => \^using_fpga.native_0\(0),
      I2 => if_missed_fetch,
      I3 => ex_jump,
      O => if_missed_fetch_reg
    );
\if_pc[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^using_fpga.native_0\(0),
      I1 => ex_jump,
      O => if_fetch_in_progress_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_115 is
  port (
    if_sel_input : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    sel_input_iii_1 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_115 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_115;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_115 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sel_input_iii_1,
      Q => if_sel_input(0),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_117 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    I187_out : out STD_LOGIC;
    I1 : out STD_LOGIC;
    I191_out : out STD_LOGIC;
    I13_out : out STD_LOGIC;
    I195_out : out STD_LOGIC;
    I17_out : out STD_LOGIC;
    I199_out : out STD_LOGIC;
    I111_out : out STD_LOGIC;
    I1103_out : out STD_LOGIC;
    I115_out : out STD_LOGIC;
    I1107_out : out STD_LOGIC;
    I119_out : out STD_LOGIC;
    I1111_out : out STD_LOGIC;
    I123_out : out STD_LOGIC;
    I1115_out : out STD_LOGIC;
    I127_out : out STD_LOGIC;
    I1119_out : out STD_LOGIC;
    I131_out : out STD_LOGIC;
    I1123_out : out STD_LOGIC;
    I135_out : out STD_LOGIC;
    I143_out : out STD_LOGIC;
    I147_out : out STD_LOGIC;
    I151_out : out STD_LOGIC;
    I155_out : out STD_LOGIC;
    I159_out : out STD_LOGIC;
    I163_out : out STD_LOGIC;
    I167_out : out STD_LOGIC;
    I171_out : out STD_LOGIC;
    I175_out : out STD_LOGIC;
    I179_out : out STD_LOGIC;
    I183_out : out STD_LOGIC;
    I1127_out : out STD_LOGIC;
    I1131_out : out STD_LOGIC;
    I1135_out : out STD_LOGIC;
    I1139_out : out STD_LOGIC;
    I1143_out : out STD_LOGIC;
    I1147_out : out STD_LOGIC;
    I1151_out : out STD_LOGIC;
    I1155_out : out STD_LOGIC;
    I1159_out : out STD_LOGIC;
    I1163_out : out STD_LOGIC;
    I1167_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    sel_input_i_1 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 41 downto 0 );
    \in\ : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_117 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_117;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_117 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sel_input_i_1,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(21),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(0),
      O => I187_out
    );
\Using_FPGA.Native_i_2__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(0),
      O => I1
    );
\Using_FPGA.Native_i_2__10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(26),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(5),
      O => I1107_out
    );
\Using_FPGA.Native_i_2__11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(5),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(5),
      O => I119_out
    );
\Using_FPGA.Native_i_2__12\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(27),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(6),
      O => I1111_out
    );
\Using_FPGA.Native_i_2__13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(6),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(6),
      O => I123_out
    );
\Using_FPGA.Native_i_2__14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(28),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(7),
      O => I1115_out
    );
\Using_FPGA.Native_i_2__15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(7),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(7),
      O => I127_out
    );
\Using_FPGA.Native_i_2__16\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(29),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(8),
      O => I1119_out
    );
\Using_FPGA.Native_i_2__17\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(8),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(8),
      O => I131_out
    );
\Using_FPGA.Native_i_2__18\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(30),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(9),
      O => I1123_out
    );
\Using_FPGA.Native_i_2__19\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(9),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(9),
      O => I135_out
    );
\Using_FPGA.Native_i_2__2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(22),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(1),
      O => I191_out
    );
\Using_FPGA.Native_i_2__3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(1),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(1),
      O => I13_out
    );
\Using_FPGA.Native_i_2__4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(23),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(2),
      O => I195_out
    );
\Using_FPGA.Native_i_2__5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(2),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(2),
      O => I17_out
    );
\Using_FPGA.Native_i_2__59\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(10),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(10),
      O => I143_out
    );
\Using_FPGA.Native_i_2__6\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(24),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(3),
      O => I199_out
    );
\Using_FPGA.Native_i_2__60\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(11),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(11),
      O => I147_out
    );
\Using_FPGA.Native_i_2__61\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(12),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(12),
      O => I151_out
    );
\Using_FPGA.Native_i_2__62\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(13),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(13),
      O => I155_out
    );
\Using_FPGA.Native_i_2__63\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(14),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(14),
      O => I159_out
    );
\Using_FPGA.Native_i_2__64\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(15),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(15),
      O => I163_out
    );
\Using_FPGA.Native_i_2__65\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(16),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(16),
      O => I167_out
    );
\Using_FPGA.Native_i_2__66\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(17),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(17),
      O => I171_out
    );
\Using_FPGA.Native_i_2__67\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(18),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(18),
      O => I175_out
    );
\Using_FPGA.Native_i_2__68\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(19),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(19),
      O => I179_out
    );
\Using_FPGA.Native_i_2__69\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(20),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(20),
      O => I183_out
    );
\Using_FPGA.Native_i_2__7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(3),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(3),
      O => I111_out
    );
\Using_FPGA.Native_i_2__70\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(31),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(21),
      O => I1127_out
    );
\Using_FPGA.Native_i_2__71\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(32),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(22),
      O => I1131_out
    );
\Using_FPGA.Native_i_2__72\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(33),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(23),
      O => I1135_out
    );
\Using_FPGA.Native_i_2__73\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(34),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(24),
      O => I1139_out
    );
\Using_FPGA.Native_i_2__74\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(35),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(25),
      O => I1143_out
    );
\Using_FPGA.Native_i_2__75\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(36),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(26),
      O => I1147_out
    );
\Using_FPGA.Native_i_2__76\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(37),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(27),
      O => I1151_out
    );
\Using_FPGA.Native_i_2__77\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(38),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(28),
      O => I1155_out
    );
\Using_FPGA.Native_i_2__78\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(39),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(29),
      O => I1159_out
    );
\Using_FPGA.Native_i_2__79\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(40),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(30),
      O => I1163_out
    );
\Using_FPGA.Native_i_2__8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(25),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(4),
      O => I1103_out
    );
\Using_FPGA.Native_i_2__80\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(41),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(31),
      O => I1167_out
    );
\Using_FPGA.Native_i_2__9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(4),
      I1 => \^using_fpga.native_0\,
      I2 => \in\(4),
      O => I115_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_119 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \OF_Op1_Sel_SPR_PC0__0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC;
    \Using_FPGA.Native_5\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_42 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_6\ : in STD_LOGIC;
    EX_Use_Carry_reg : in STD_LOGIC;
    \Using_FPGA.Native_7\ : in STD_LOGIC;
    ex_jump_nodelay : in STD_LOGIC;
    ex_jump : in STD_LOGIC;
    EX_CMP_Op_reg : in STD_LOGIC;
    EX_Unsigned_Op_reg : in STD_LOGIC;
    \EX_ALU_Op1142_out__0\ : in STD_LOGIC;
    EX_Unsigned_Op_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_119 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_119;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_119 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EX_Use_Carry_i_1 : label is "soft_lutpair6";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__102\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__96\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_4__1\ : label is "soft_lutpair6";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
EX_CMP_Op_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_7\,
      I2 => EX_CMP_Op_reg,
      I3 => EX_Unsigned_Op_reg,
      I4 => \EX_ALU_Op1142_out__0\,
      O => \Using_FPGA.Native_2\
    );
EX_Unsigned_Op_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_7\,
      I2 => EX_Unsigned_Op_reg_0,
      I3 => EX_Unsigned_Op_reg,
      I4 => \EX_ALU_Op1142_out__0\,
      O => \Using_FPGA.Native_3\
    );
EX_Use_Carry_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0010"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_7\,
      I2 => EX_Use_Carry_reg,
      I3 => \EX_ALU_Op1142_out__0\,
      O => \Using_FPGA.Native_4\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_42,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__102\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_7\,
      I2 => \Using_FPGA.Native_6\,
      O => \Using_FPGA.Native_5\
    );
\Using_FPGA.Native_i_1__96\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0888"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_7\,
      I2 => ex_jump_nodelay,
      I3 => ex_jump,
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native_i_4__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_6\,
      I2 => EX_Use_Carry_reg,
      I3 => \Using_FPGA.Native_7\,
      O => \OF_Op1_Sel_SPR_PC0__0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_121 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \mem_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    \wb_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    \ex_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_32 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \EX_Op3[0]_i_4\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \EX_Op3[0]_i_6\ : in STD_LOGIC;
    \EX_Op3[0]_i_6_0\ : in STD_LOGIC;
    \EX_Op3[0]_i_5\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \EX_Op3[0]_i_6_1\ : in STD_LOGIC;
    I4 : in STD_LOGIC;
    I0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_121 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_121;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_121 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op3[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \EX_Op3[0]_i_6_1\,
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op3[0]_i_6\,
      I3 => I4,
      I4 => \EX_Op3[0]_i_6_0\,
      I5 => I0,
      O => \ex_gpr_write_addr_reg[4]\
    );
\EX_Op3[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \EX_Op3[0]_i_4\(0),
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op3[0]_i_6\,
      I3 => \EX_Op3[0]_i_4\(2),
      I4 => \EX_Op3[0]_i_6_0\,
      I5 => \EX_Op3[0]_i_4\(1),
      O => \mem_gpr_write_addr_reg[4]\
    );
\EX_Op3[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \EX_Op3[0]_i_5\(0),
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op3[0]_i_6\,
      I3 => \EX_Op3[0]_i_5\(2),
      I4 => \EX_Op3[0]_i_6_0\,
      I5 => \EX_Op3[0]_i_5\(1),
      O => \wb_gpr_write_addr_reg[4]\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_32,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_123 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \ex_set_bip0__1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_31 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_set_bip_reg : in STD_LOGIC;
    ex_set_bip_reg_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_123 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_123;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_123 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_31,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
ex_set_bip_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_set_bip_reg,
      I2 => ex_set_bip_reg_0,
      O => \ex_set_bip0__1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_125 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_ALU_Op1142_out__0\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_30 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \EX_ALU_Op_reg[1]\ : in STD_LOGIC;
    ex_enable_alu_i_reg : in STD_LOGIC;
    \EX_ALU_Op_reg[1]_0\ : in STD_LOGIC;
    ex_enable_alu_i_reg_0 : in STD_LOGIC;
    ex_enable_alu_i_reg_1 : in STD_LOGIC;
    ex_enable_alu_i_reg_2 : in STD_LOGIC;
    ex_enable_alu_i_reg_3 : in STD_LOGIC;
    p_28_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_125 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_125;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_125 is
  signal \^ex_alu_op1142_out__0\ : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \EX_ALU_Op1142_out__0\ <= \^ex_alu_op1142_out__0\;
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_ALU_Op[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAEAEAEAEEE"
    )
        port map (
      I0 => \^ex_alu_op1142_out__0\,
      I1 => \EX_ALU_Op_reg[1]\,
      I2 => ex_enable_alu_i_reg,
      I3 => \EX_ALU_Op_reg[1]_0\,
      I4 => ex_enable_alu_i_reg_0,
      I5 => ex_enable_alu_i_reg_1,
      O => \Using_FPGA.Native_1\(0)
    );
EX_CMP_Op_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => p_28_in,
      O => \^ex_alu_op1142_out__0\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_30,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
ex_enable_alu_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEBFFFF"
    )
        port map (
      I0 => \^ex_alu_op1142_out__0\,
      I1 => ex_enable_alu_i_reg_1,
      I2 => ex_enable_alu_i_reg,
      I3 => ex_enable_alu_i_reg_2,
      I4 => ex_enable_alu_i_reg_3,
      I5 => ex_enable_alu_i_reg_0,
      O => \Using_FPGA.Native_2\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_127 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_29 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_127 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_127;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_127 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_29,
      Q => \Using_FPGA.Native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_129 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_28 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    p_1_in26_in : in STD_LOGIC;
    ex_mbar_decode_reg : in STD_LOGIC;
    ex_mbar_decode : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_129 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_129;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_129 is
  signal \^using_fpga.native_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\(0) <= \^using_fpga.native_0\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_28,
      Q => \^using_fpga.native_0\(0),
      R => sync_reset
    );
ex_mbar_decode_cmb_inferred_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80808F80"
    )
        port map (
      I0 => \^using_fpga.native_0\(0),
      I1 => p_1_in26_in,
      I2 => ex_mbar_decode_reg,
      I3 => ex_mbar_decode,
      I4 => E(0),
      O => \Using_FPGA.Native_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_131 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    of_instr_ii_27 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_131 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_131;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_131 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_27,
      Q => \Using_FPGA.Native_0\(0),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_133 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \imm_reg_reg[15]\ : out STD_LOGIC;
    \imm_reg_reg[14]\ : out STD_LOGIC;
    \imm_reg_reg[13]\ : out STD_LOGIC;
    \imm_reg_reg[12]\ : out STD_LOGIC;
    \imm_reg_reg[11]\ : out STD_LOGIC;
    \imm_reg_reg[10]\ : out STD_LOGIC;
    \imm_reg_reg[9]\ : out STD_LOGIC;
    \imm_reg_reg[8]\ : out STD_LOGIC;
    \imm_reg_reg[7]\ : out STD_LOGIC;
    \imm_reg_reg[6]\ : out STD_LOGIC;
    \imm_reg_reg[5]\ : out STD_LOGIC;
    \imm_reg_reg[4]\ : out STD_LOGIC;
    \imm_reg_reg[3]\ : out STD_LOGIC;
    \imm_reg_reg[2]\ : out STD_LOGIC;
    \imm_reg_reg[1]\ : out STD_LOGIC;
    \imm_reg_reg[0]\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_26 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 16 downto 0 );
    \EX_Op2_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \EX_Op2_reg[0]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_133 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_133;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_133 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(15),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(16),
      O => \imm_reg_reg[0]\
    );
\EX_Op2[10]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(5),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(6),
      O => \imm_reg_reg[10]\
    );
\EX_Op2[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(4),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(5),
      O => \imm_reg_reg[11]\
    );
\EX_Op2[12]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(3),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(4),
      O => \imm_reg_reg[12]\
    );
\EX_Op2[13]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(2),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(3),
      O => \imm_reg_reg[13]\
    );
\EX_Op2[14]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(1),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(2),
      O => \imm_reg_reg[14]\
    );
\EX_Op2[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(0),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(1),
      O => \imm_reg_reg[15]\
    );
\EX_Op2[16]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\EX_Op2[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(14),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(15),
      O => \imm_reg_reg[1]\
    );
\EX_Op2[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(13),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(14),
      O => \imm_reg_reg[2]\
    );
\EX_Op2[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(12),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(13),
      O => \imm_reg_reg[3]\
    );
\EX_Op2[4]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(11),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(12),
      O => \imm_reg_reg[4]\
    );
\EX_Op2[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(10),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(11),
      O => \imm_reg_reg[5]\
    );
\EX_Op2[6]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(9),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(10),
      O => \imm_reg_reg[6]\
    );
\EX_Op2[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(8),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(9),
      O => \imm_reg_reg[7]\
    );
\EX_Op2[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(7),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(8),
      O => \imm_reg_reg[8]\
    );
\EX_Op2[9]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8FFB800"
    )
        port map (
      I0 => \EX_Op2_reg[0]\(6),
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \^using_fpga.native_0\,
      I3 => of_op2_sel_imm,
      I4 => GPR_Op2(7),
      O => \imm_reg_reg[9]\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_26,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_135 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_25 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_135 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_135;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_135 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \EX_Op2[17]_i_2\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \Performance_Debug_Control.ex_dbg_pc_hit_i_i_7\ : label is "soft_lutpair7";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[17]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Performance_Debug_Control.ex_dbg_pc_hit_i_i_7\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\,
      I2 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\,
      O => \Using_FPGA.Native_2\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_25,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_137 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_24 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_137 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_137;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_137 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[18]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_24,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_139 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_23 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_139 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_139;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_139 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[19]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_23,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_141 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_gpr_write_reg : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_28_in : out STD_LOGIC;
    of_op2_sel_imm : out STD_LOGIC;
    of_use_op2_s : out STD_LOGIC;
    wb_exception_i_reg : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    ex_set_bip : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_41 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_gpr_write_reg_0 : in STD_LOGIC;
    ex_gpr_write_reg_1 : in STD_LOGIC;
    \ex_gpr_write111_out__0\ : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    ex_set_bip_reg : in STD_LOGIC;
    \EX_ALU_Op_reg[0]\ : in STD_LOGIC;
    ex_set_bip_reg_0 : in STD_LOGIC;
    ex_set_bip_reg_1 : in STD_LOGIC;
    \EX_ALU_Op1142_out__0\ : in STD_LOGIC;
    p_0_in30_in : in STD_LOGIC;
    ex_gpr_write_dbg_reg : in STD_LOGIC;
    ex_gpr_write_dbg_reg_0 : in STD_LOGIC;
    ex_gpr_write_i_2_0 : in STD_LOGIC;
    ex_gpr_write_i_2_1 : in STD_LOGIC;
    ex_gpr_write_i_2_2 : in STD_LOGIC;
    ex_gpr_write_i_2_3 : in STD_LOGIC;
    ex_set_bip_reg_2 : in STD_LOGIC;
    \EX_Op2[0]_i_2\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \ex_gpr_write_dbg__0\ : in STD_LOGIC;
    \ex_set_bip0__1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_141 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_141;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_141 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal ex_gpr_write : STD_LOGIC;
  signal ex_gpr_write_dbg108_in : STD_LOGIC;
  signal ex_gpr_write_i_5_n_0 : STD_LOGIC;
  signal \^p_28_in\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of EX_CMP_Op_i_3 : label is "soft_lutpair8";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of ex_gpr_write_i_5 : label is "soft_lutpair8";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  p_28_in <= \^p_28_in\;
\EX_ALU_Op[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFFFF9"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_set_bip_reg,
      I2 => \EX_ALU_Op_reg[0]\,
      I3 => ex_set_bip_reg_0,
      I4 => ex_set_bip_reg_1,
      I5 => \EX_ALU_Op1142_out__0\,
      O => \Using_FPGA.Native_1\(0)
    );
EX_CMP_Op_i_3: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_set_bip_reg_0,
      I2 => ex_set_bip_reg_1,
      I3 => ex_set_bip_reg,
      I4 => ex_set_bip_reg_2,
      O => \^p_28_in\
    );
\EX_Op2[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00004000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_set_bip_reg,
      I2 => ex_set_bip_reg_2,
      I3 => ex_set_bip_reg_1,
      I4 => ex_set_bip_reg_0,
      I5 => \EX_Op2[0]_i_2\,
      O => of_op2_sel_imm
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_41,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_2__117\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"33332333"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \EX_Op2[0]_i_2\,
      I2 => ex_set_bip_reg,
      I3 => ex_set_bip_reg_1,
      I4 => ex_set_bip_reg_0,
      O => of_use_op2_s
    );
ex_alu_sel_logic_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_set_bip_reg,
      I2 => ex_set_bip_reg_1,
      I3 => \EX_ALU_Op1142_out__0\,
      O => \Using_FPGA.Native_2\
    );
ex_gpr_write_dbg_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0200020302000200"
    )
        port map (
      I0 => ex_gpr_write,
      I1 => wb_exception,
      I2 => sync_reset,
      I3 => ex_gpr_write_reg_1,
      I4 => E(0),
      I5 => \ex_gpr_write_dbg__0\,
      O => wb_exception_i_reg
    );
ex_gpr_write_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000E2"
    )
        port map (
      I0 => ex_gpr_write_reg_0,
      I1 => ex_gpr_write_reg_1,
      I2 => ex_gpr_write,
      I3 => \ex_gpr_write111_out__0\,
      I4 => sync_reset,
      I5 => wb_exception,
      O => ex_gpr_write_reg
    );
ex_gpr_write_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"222A"
    )
        port map (
      I0 => ex_gpr_write_dbg108_in,
      I1 => p_0_in30_in,
      I2 => ex_gpr_write_dbg_reg,
      I3 => ex_gpr_write_dbg_reg_0,
      O => ex_gpr_write
    );
ex_gpr_write_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8888888888888BBB"
    )
        port map (
      I0 => ex_gpr_write_i_2_0,
      I1 => \^p_28_in\,
      I2 => ex_gpr_write_i_2_1,
      I3 => ex_gpr_write_i_2_2,
      I4 => ex_gpr_write_i_5_n_0,
      I5 => ex_gpr_write_i_2_3,
      O => ex_gpr_write_dbg108_in
    );
ex_gpr_write_i_5: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_set_bip_reg_0,
      I2 => ex_set_bip_reg_1,
      I3 => ex_set_bip_reg_2,
      I4 => ex_set_bip_reg,
      O => ex_gpr_write_i_5_n_0
    );
ex_set_bip_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000000000000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_set_bip_reg_2,
      I2 => \ex_set_bip0__1\,
      I3 => ex_set_bip_reg_0,
      I4 => ex_set_bip_reg_1,
      I5 => ex_set_bip_reg,
      O => ex_set_bip
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_143 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_22 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0\ : in STD_LOGIC;
    \ex_set_bip0__1\ : in STD_LOGIC;
    p_1_in26_in : in STD_LOGIC;
    of_Imm180 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_143 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_143;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_143 is
  signal \Performance_Debug_Control.ex_dbg_pc_hit_i_i_6_n_0\ : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[20]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_6_n_0\,
      I1 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2\,
      I2 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0\,
      I3 => \ex_set_bip0__1\,
      I4 => p_1_in26_in,
      I5 => of_Imm180,
      O => \Using_FPGA.Native_2\
    );
\Performance_Debug_Control.ex_dbg_pc_hit_i_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\,
      I2 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\,
      I3 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2\,
      O => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_6_n_0\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_22,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_145 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_21 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_brki_hit_reg\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_0\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_brki_hit_reg_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_145 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_145;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_145 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[21]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Performance_Debug_Control.ex_brki_hit_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Performance_Debug_Control.ex_brki_hit_reg\,
      I2 => \Performance_Debug_Control.ex_brki_hit_reg_0\,
      I3 => \Performance_Debug_Control.ex_brki_hit_reg_1\(0),
      I4 => \Performance_Debug_Control.ex_brki_hit_reg_2\,
      O => \Using_FPGA.Native_2\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_21,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_147 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_20 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_147 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_147;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_147 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \EX_Op2[22]_i_2\ : label is "soft_lutpair9";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__103\ : label is "soft_lutpair9";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[22]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_20,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__103\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_3\,
      O => \Using_FPGA.Native_2\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_149 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_19 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_149 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_149;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_149 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[23]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_19,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_151 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_18 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_151 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_151;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_151 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[24]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Performance_Debug_Control.ex_brki_hit_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\,
      I2 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\,
      I3 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\,
      O => \Using_FPGA.Native_2\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_18,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_153 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_17 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_153 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_153;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_153 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[25]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_17,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_155 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_16 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Sext_Op_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_155 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_155;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_155 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \EX_Op2[26]_i_2\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \EX_Sext_Op[0]_i_2\ : label is "soft_lutpair10";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[26]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\EX_Sext_Op[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \EX_Sext_Op_reg[0]\,
      O => \Using_FPGA.Native_2\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_16,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_157 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Serial_Dbg_Intf.control_reg_reg[8]\ : out STD_LOGIC;
    of_Imm180 : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_15 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_brki_hit_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_brki_hit_reg_0\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_1\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_2\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_3\ : in STD_LOGIC;
    p_1_in26_in : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_4\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_5\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_6\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_157 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_157;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_157 is
  signal \Performance_Debug_Control.ex_brki_hit_i_2_n_0\ : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \^of_imm180\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  of_Imm180 <= \^of_imm180\;
\EX_Op2[27]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Performance_Debug_Control.ex_brki_hit_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => \Performance_Debug_Control.ex_brki_hit_reg\(0),
      I1 => \Performance_Debug_Control.ex_brki_hit_i_2_n_0\,
      I2 => \Performance_Debug_Control.ex_brki_hit_reg_0\,
      I3 => \Performance_Debug_Control.ex_brki_hit_reg_1\,
      I4 => \Performance_Debug_Control.ex_brki_hit_reg_2\,
      I5 => \Performance_Debug_Control.ex_brki_hit_reg_3\,
      O => \Serial_Dbg_Intf.control_reg_reg[8]\
    );
\Performance_Debug_Control.ex_brki_hit_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F7FFFFFF"
    )
        port map (
      I0 => \^of_imm180\,
      I1 => p_1_in26_in,
      I2 => \Performance_Debug_Control.ex_brki_hit_reg_4\,
      I3 => \Performance_Debug_Control.ex_brki_hit_reg_5\,
      I4 => \Performance_Debug_Control.ex_brki_hit_reg_6\,
      O => \Performance_Debug_Control.ex_brki_hit_i_2_n_0\
    );
\Performance_Debug_Control.ex_brki_hit_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000020"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\,
      I2 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\,
      I3 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\,
      I4 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2\,
      O => \^of_imm180\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_15,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_159 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_move_to_MSR_instr93_out : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_14 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_move_to_MSR_instr_reg : in STD_LOGIC;
    ex_move_to_MSR_instr_reg_0 : in STD_LOGIC;
    ex_move_to_MSR_instr_reg_1 : in STD_LOGIC;
    ex_move_to_MSR_instr_reg_2 : in STD_LOGIC;
    ex_move_to_MSR_instr_reg_3 : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_159 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_159;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_159 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[28]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_14,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
ex_move_to_MSR_instr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0100000000000000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_move_to_MSR_instr_reg,
      I2 => ex_move_to_MSR_instr_reg_0,
      I3 => ex_move_to_MSR_instr_reg_1,
      I4 => ex_move_to_MSR_instr_reg_2,
      I5 => ex_move_to_MSR_instr_reg_3,
      O => ex_move_to_MSR_instr93_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_161 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_13 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_161 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_161;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_161 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[29]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_13,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_163 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    p_1_in26_in : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_40 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_mbar_decode_reg : in STD_LOGIC;
    \Using_FPGA.Native_5\ : in STD_LOGIC;
    \Using_FPGA.Native_6\ : in STD_LOGIC;
    ex_mbar_decode_reg_0 : in STD_LOGIC;
    ex_mbar_decode_reg_1 : in STD_LOGIC;
    \EX_ALU_Op_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_163 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_163;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_163 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \EX_Sext_Op[1]_i_2\ : label is "soft_lutpair11";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_2__84\ : label is "soft_lutpair11";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_ALU_Op[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \EX_ALU_Op_reg[0]\,
      I2 => ex_mbar_decode_reg,
      O => \Using_FPGA.Native_3\
    );
\EX_Sext_Op[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFFF"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_mbar_decode_reg_1,
      I2 => \Using_FPGA.Native_6\,
      I3 => ex_mbar_decode_reg,
      O => \Using_FPGA.Native_4\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_40,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_2__84\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_5\,
      I2 => \Using_FPGA.Native_6\,
      O => \Using_FPGA.Native_2\
    );
ex_gpr_write_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0C00CC0000008800"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_mbar_decode_reg,
      I2 => \Using_FPGA.Native_5\,
      I3 => \Using_FPGA.Native_6\,
      I4 => ex_mbar_decode_reg_0,
      I5 => ex_mbar_decode_reg_1,
      O => \Using_FPGA.Native_1\
    );
ex_mbar_decode_cmb_inferred_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008000000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_mbar_decode_reg,
      I2 => \Using_FPGA.Native_5\,
      I3 => \Using_FPGA.Native_6\,
      I4 => ex_mbar_decode_reg_0,
      I5 => ex_mbar_decode_reg_1,
      O => p_1_in26_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_165 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_12 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_165 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_165;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_165 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \EX_Op2[30]_i_2\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of EX_SWAP_BYTE_Instr_i_1 : label is "soft_lutpair12";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[30]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
EX_SWAP_BYTE_Instr_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      O => p_2_in
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_12,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_167 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_11 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    of_op2_sel_imm : in STD_LOGIC;
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_167 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_167;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_167 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[31]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => of_op2_sel_imm,
      I2 => GPR_Op2(0),
      O => \Using_FPGA.Native_1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_11,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_169 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_sel_alu_i_reg : out STD_LOGIC_VECTOR ( 31 downto 0 );
    mem_valid_reg : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_10 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \EX_Op3_reg[0]\ : in STD_LOGIC;
    GPR_Op3 : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Op3_reg[0]_0\ : in STD_LOGIC;
    MEM_Fwd : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Op3_reg[1]\ : in STD_LOGIC;
    \EX_Op3_reg[1]_0\ : in STD_LOGIC;
    \EX_Op3_reg[2]\ : in STD_LOGIC;
    \EX_Op3_reg[2]_0\ : in STD_LOGIC;
    \EX_Op3_reg[3]\ : in STD_LOGIC;
    \EX_Op3_reg[3]_0\ : in STD_LOGIC;
    \EX_Op3_reg[4]\ : in STD_LOGIC;
    \EX_Op3_reg[4]_0\ : in STD_LOGIC;
    \EX_Op3_reg[5]\ : in STD_LOGIC;
    \EX_Op3_reg[5]_0\ : in STD_LOGIC;
    \EX_Op3_reg[6]\ : in STD_LOGIC;
    \EX_Op3_reg[6]_0\ : in STD_LOGIC;
    \EX_Op3_reg[7]\ : in STD_LOGIC;
    \EX_Op3_reg[7]_0\ : in STD_LOGIC;
    \EX_Op3_reg[8]\ : in STD_LOGIC;
    \EX_Op3_reg[8]_0\ : in STD_LOGIC;
    \EX_Op3_reg[9]\ : in STD_LOGIC;
    \EX_Op3_reg[9]_0\ : in STD_LOGIC;
    \EX_Op3_reg[10]\ : in STD_LOGIC;
    \EX_Op3_reg[10]_0\ : in STD_LOGIC;
    \EX_Op3_reg[11]\ : in STD_LOGIC;
    \EX_Op3_reg[11]_0\ : in STD_LOGIC;
    \EX_Op3_reg[12]\ : in STD_LOGIC;
    \EX_Op3_reg[12]_0\ : in STD_LOGIC;
    \EX_Op3_reg[13]\ : in STD_LOGIC;
    \EX_Op3_reg[13]_0\ : in STD_LOGIC;
    \EX_Op3_reg[14]\ : in STD_LOGIC;
    \EX_Op3_reg[14]_0\ : in STD_LOGIC;
    \EX_Op3_reg[15]\ : in STD_LOGIC;
    \EX_Op3_reg[15]_0\ : in STD_LOGIC;
    \EX_Op3_reg[16]\ : in STD_LOGIC;
    \EX_Op3_reg[16]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \EX_Op3_reg[17]\ : in STD_LOGIC;
    \EX_Op3_reg[18]\ : in STD_LOGIC;
    \EX_Op3_reg[19]\ : in STD_LOGIC;
    \EX_Op3_reg[20]\ : in STD_LOGIC;
    \EX_Op3_reg[21]\ : in STD_LOGIC;
    \EX_Op3_reg[22]\ : in STD_LOGIC;
    \EX_Op3_reg[23]\ : in STD_LOGIC;
    \EX_Op3_reg[24]\ : in STD_LOGIC;
    \EX_Op3_reg[24]_0\ : in STD_LOGIC;
    \EX_Op3_reg[25]\ : in STD_LOGIC;
    \EX_Op3_reg[25]_0\ : in STD_LOGIC;
    \EX_Op3_reg[26]\ : in STD_LOGIC;
    \EX_Op3_reg[26]_0\ : in STD_LOGIC;
    \EX_Op3_reg[27]\ : in STD_LOGIC;
    \EX_Op3_reg[27]_0\ : in STD_LOGIC;
    \EX_Op3_reg[28]\ : in STD_LOGIC;
    \EX_Op3_reg[28]_0\ : in STD_LOGIC;
    \EX_Op3_reg[29]\ : in STD_LOGIC;
    \EX_Op3_reg[29]_0\ : in STD_LOGIC;
    \EX_Op3_reg[30]\ : in STD_LOGIC;
    \EX_Op3_reg[30]_0\ : in STD_LOGIC;
    \EX_Op3_reg[31]\ : in STD_LOGIC;
    \EX_Op3_reg[31]_0\ : in STD_LOGIC;
    \of_read_mem_write_op3_conflict__1\ : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    mem_gpr_write : in STD_LOGIC;
    p_216_in : in STD_LOGIC;
    \EX_Op3[0]_i_2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op3[0]_i_2_1\ : in STD_LOGIC;
    \EX_Op3[0]_i_2_2\ : in STD_LOGIC;
    \EX_Op3[0]_i_2_3\ : in STD_LOGIC;
    \EX_Op3[0]_i_2_4\ : in STD_LOGIC;
    \EX_Op3[0]_i_2_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op3[0]_i_2_6\ : in STD_LOGIC;
    \EX_Op3[0]_i_2_7\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_169 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_169;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_169 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal of_op3_sel : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \of_read_ex_write_op3_conflict__1\ : STD_LOGIC;
  signal \of_read_wb_write_op3_conflict__1\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op3[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[0]\,
      I1 => GPR_Op3(0),
      I2 => \EX_Op3_reg[0]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(0),
      O => ex_sel_alu_i_reg(31)
    );
\EX_Op3[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \of_read_mem_write_op3_conflict__1\,
      I1 => \of_read_wb_write_op3_conflict__1\,
      I2 => \of_read_ex_write_op3_conflict__1\,
      O => of_op3_sel(0)
    );
\EX_Op3[0]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \of_read_mem_write_op3_conflict__1\,
      I1 => \of_read_wb_write_op3_conflict__1\,
      I2 => \of_read_ex_write_op3_conflict__1\,
      O => of_op3_sel(1)
    );
\EX_Op3[0]_i_5\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8008000000000000"
    )
        port map (
      I0 => \EX_Op3[0]_i_2_4\,
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op3[0]_i_2_5\(0),
      I3 => \EX_Op3[0]_i_2_1\,
      I4 => \EX_Op3[0]_i_2_6\,
      I5 => \EX_Op3[0]_i_2_7\,
      O => \of_read_wb_write_op3_conflict__1\
    );
\EX_Op3[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8008000000000000"
    )
        port map (
      I0 => p_216_in,
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op3[0]_i_2_0\(0),
      I3 => \EX_Op3[0]_i_2_1\,
      I4 => \EX_Op3[0]_i_2_2\,
      I5 => \EX_Op3[0]_i_2_3\,
      O => \of_read_ex_write_op3_conflict__1\
    );
\EX_Op3[0]_i_8\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => mem_valid_instr,
      I1 => mem_gpr_write,
      I2 => \^using_fpga.native_0\,
      O => mem_valid_reg
    );
\EX_Op3[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[10]\,
      I1 => GPR_Op3(10),
      I2 => \EX_Op3_reg[10]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(10),
      O => ex_sel_alu_i_reg(21)
    );
\EX_Op3[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[11]\,
      I1 => GPR_Op3(11),
      I2 => \EX_Op3_reg[11]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(11),
      O => ex_sel_alu_i_reg(20)
    );
\EX_Op3[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[12]\,
      I1 => GPR_Op3(12),
      I2 => \EX_Op3_reg[12]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(12),
      O => ex_sel_alu_i_reg(19)
    );
\EX_Op3[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[13]\,
      I1 => GPR_Op3(13),
      I2 => \EX_Op3_reg[13]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(13),
      O => ex_sel_alu_i_reg(18)
    );
\EX_Op3[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[14]\,
      I1 => GPR_Op3(14),
      I2 => \EX_Op3_reg[14]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(14),
      O => ex_sel_alu_i_reg(17)
    );
\EX_Op3[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[15]\,
      I1 => GPR_Op3(15),
      I2 => \EX_Op3_reg[15]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(15),
      O => ex_sel_alu_i_reg(16)
    );
\EX_Op3[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[16]\,
      I1 => GPR_Op3(16),
      I2 => \EX_Op3_reg[16]_0\(7),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(16),
      O => ex_sel_alu_i_reg(15)
    );
\EX_Op3[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[17]\,
      I1 => GPR_Op3(17),
      I2 => \EX_Op3_reg[16]_0\(6),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(17),
      O => ex_sel_alu_i_reg(14)
    );
\EX_Op3[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[18]\,
      I1 => GPR_Op3(18),
      I2 => \EX_Op3_reg[16]_0\(5),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(18),
      O => ex_sel_alu_i_reg(13)
    );
\EX_Op3[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[19]\,
      I1 => GPR_Op3(19),
      I2 => \EX_Op3_reg[16]_0\(4),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(19),
      O => ex_sel_alu_i_reg(12)
    );
\EX_Op3[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[1]\,
      I1 => GPR_Op3(1),
      I2 => \EX_Op3_reg[1]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(1),
      O => ex_sel_alu_i_reg(30)
    );
\EX_Op3[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[20]\,
      I1 => GPR_Op3(20),
      I2 => \EX_Op3_reg[16]_0\(3),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(20),
      O => ex_sel_alu_i_reg(11)
    );
\EX_Op3[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[21]\,
      I1 => GPR_Op3(21),
      I2 => \EX_Op3_reg[16]_0\(2),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(21),
      O => ex_sel_alu_i_reg(10)
    );
\EX_Op3[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[22]\,
      I1 => GPR_Op3(22),
      I2 => \EX_Op3_reg[16]_0\(1),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(22),
      O => ex_sel_alu_i_reg(9)
    );
\EX_Op3[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[23]\,
      I1 => GPR_Op3(23),
      I2 => \EX_Op3_reg[16]_0\(0),
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(23),
      O => ex_sel_alu_i_reg(8)
    );
\EX_Op3[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[24]\,
      I1 => GPR_Op3(24),
      I2 => \EX_Op3_reg[24]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(24),
      O => ex_sel_alu_i_reg(7)
    );
\EX_Op3[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[25]\,
      I1 => GPR_Op3(25),
      I2 => \EX_Op3_reg[25]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(25),
      O => ex_sel_alu_i_reg(6)
    );
\EX_Op3[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[26]\,
      I1 => GPR_Op3(26),
      I2 => \EX_Op3_reg[26]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(26),
      O => ex_sel_alu_i_reg(5)
    );
\EX_Op3[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[27]\,
      I1 => GPR_Op3(27),
      I2 => \EX_Op3_reg[27]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(27),
      O => ex_sel_alu_i_reg(4)
    );
\EX_Op3[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[28]\,
      I1 => GPR_Op3(28),
      I2 => \EX_Op3_reg[28]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(28),
      O => ex_sel_alu_i_reg(3)
    );
\EX_Op3[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[29]\,
      I1 => GPR_Op3(29),
      I2 => \EX_Op3_reg[29]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(29),
      O => ex_sel_alu_i_reg(2)
    );
\EX_Op3[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[2]\,
      I1 => GPR_Op3(2),
      I2 => \EX_Op3_reg[2]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(2),
      O => ex_sel_alu_i_reg(29)
    );
\EX_Op3[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[30]\,
      I1 => GPR_Op3(30),
      I2 => \EX_Op3_reg[30]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(30),
      O => ex_sel_alu_i_reg(1)
    );
\EX_Op3[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[31]\,
      I1 => GPR_Op3(31),
      I2 => \EX_Op3_reg[31]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(31),
      O => ex_sel_alu_i_reg(0)
    );
\EX_Op3[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[3]\,
      I1 => GPR_Op3(3),
      I2 => \EX_Op3_reg[3]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(3),
      O => ex_sel_alu_i_reg(28)
    );
\EX_Op3[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[4]\,
      I1 => GPR_Op3(4),
      I2 => \EX_Op3_reg[4]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(4),
      O => ex_sel_alu_i_reg(27)
    );
\EX_Op3[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[5]\,
      I1 => GPR_Op3(5),
      I2 => \EX_Op3_reg[5]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(5),
      O => ex_sel_alu_i_reg(26)
    );
\EX_Op3[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[6]\,
      I1 => GPR_Op3(6),
      I2 => \EX_Op3_reg[6]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(6),
      O => ex_sel_alu_i_reg(25)
    );
\EX_Op3[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[7]\,
      I1 => GPR_Op3(7),
      I2 => \EX_Op3_reg[7]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(7),
      O => ex_sel_alu_i_reg(24)
    );
\EX_Op3[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[8]\,
      I1 => GPR_Op3(8),
      I2 => \EX_Op3_reg[8]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(8),
      O => ex_sel_alu_i_reg(23)
    );
\EX_Op3[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op3_reg[9]\,
      I1 => GPR_Op3(9),
      I2 => \EX_Op3_reg[9]_0\,
      I3 => of_op3_sel(0),
      I4 => of_op3_sel(1),
      I5 => MEM_Fwd(9),
      O => ex_sel_alu_i_reg(22)
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_10,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_171 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_sel_alu_i_reg : out STD_LOGIC_VECTOR ( 31 downto 0 );
    sync_reset : in STD_LOGIC;
    of_instr_ii_9 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[0]\ : in STD_LOGIC;
    GPR_Op1 : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Branch_CMP_Op1_reg[0]_0\ : in STD_LOGIC;
    MEM_Fwd : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Branch_CMP_Op1_reg[1]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[1]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[2]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[2]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[3]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[3]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[4]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[4]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[5]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[5]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[6]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[6]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[7]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[7]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[8]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[8]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[9]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[9]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[10]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[10]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[11]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[11]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[12]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[12]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[13]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[13]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[14]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[14]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[15]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[15]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[16]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[16]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \EX_Branch_CMP_Op1_reg[17]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[18]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[19]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[20]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[21]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[22]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[23]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[24]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[24]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[25]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[25]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[26]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[26]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[27]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[27]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[28]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[28]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[29]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[29]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[30]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[30]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[31]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[31]_0\ : in STD_LOGIC;
    \Using_FPGA.Native_i_5__0_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_i_5__0_1\ : in STD_LOGIC;
    \Using_FPGA.Native_i_5__0_2\ : in STD_LOGIC;
    p_213_in : in STD_LOGIC;
    \Using_FPGA.Native_i_5__0_3\ : in STD_LOGIC;
    \Using_FPGA.Native_i_5__0_4\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_i_5__0_5\ : in STD_LOGIC;
    \Using_FPGA.Native_i_5__0_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_i_5__0_7\ : in STD_LOGIC;
    p_216_in : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_171 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_171;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_171 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal of_op1_sel : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \of_read_ex_write_op1_conflict__0\ : STD_LOGIC;
  signal \of_read_mem_write_op1_conflict__0\ : STD_LOGIC;
  signal \of_read_wb_write_op1_conflict__0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_9,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[1]\,
      I1 => GPR_Op1(1),
      I2 => \EX_Branch_CMP_Op1_reg[1]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(1),
      O => ex_sel_alu_i_reg(30)
    );
\Using_FPGA.Native_i_1__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[2]\,
      I1 => GPR_Op1(2),
      I2 => \EX_Branch_CMP_Op1_reg[2]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(2),
      O => ex_sel_alu_i_reg(29)
    );
\Using_FPGA.Native_i_1__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[3]\,
      I1 => GPR_Op1(3),
      I2 => \EX_Branch_CMP_Op1_reg[3]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(3),
      O => ex_sel_alu_i_reg(28)
    );
\Using_FPGA.Native_i_1__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[4]\,
      I1 => GPR_Op1(4),
      I2 => \EX_Branch_CMP_Op1_reg[4]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(4),
      O => ex_sel_alu_i_reg(27)
    );
\Using_FPGA.Native_i_1__15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[5]\,
      I1 => GPR_Op1(5),
      I2 => \EX_Branch_CMP_Op1_reg[5]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(5),
      O => ex_sel_alu_i_reg(26)
    );
\Using_FPGA.Native_i_1__16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[6]\,
      I1 => GPR_Op1(6),
      I2 => \EX_Branch_CMP_Op1_reg[6]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(6),
      O => ex_sel_alu_i_reg(25)
    );
\Using_FPGA.Native_i_1__17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[7]\,
      I1 => GPR_Op1(7),
      I2 => \EX_Branch_CMP_Op1_reg[7]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(7),
      O => ex_sel_alu_i_reg(24)
    );
\Using_FPGA.Native_i_1__18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[8]\,
      I1 => GPR_Op1(8),
      I2 => \EX_Branch_CMP_Op1_reg[8]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(8),
      O => ex_sel_alu_i_reg(23)
    );
\Using_FPGA.Native_i_1__19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[9]\,
      I1 => GPR_Op1(9),
      I2 => \EX_Branch_CMP_Op1_reg[9]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(9),
      O => ex_sel_alu_i_reg(22)
    );
\Using_FPGA.Native_i_1__20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[10]\,
      I1 => GPR_Op1(10),
      I2 => \EX_Branch_CMP_Op1_reg[10]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(10),
      O => ex_sel_alu_i_reg(21)
    );
\Using_FPGA.Native_i_1__21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[11]\,
      I1 => GPR_Op1(11),
      I2 => \EX_Branch_CMP_Op1_reg[11]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(11),
      O => ex_sel_alu_i_reg(20)
    );
\Using_FPGA.Native_i_1__22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[12]\,
      I1 => GPR_Op1(12),
      I2 => \EX_Branch_CMP_Op1_reg[12]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(12),
      O => ex_sel_alu_i_reg(19)
    );
\Using_FPGA.Native_i_1__23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[13]\,
      I1 => GPR_Op1(13),
      I2 => \EX_Branch_CMP_Op1_reg[13]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(13),
      O => ex_sel_alu_i_reg(18)
    );
\Using_FPGA.Native_i_1__24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[14]\,
      I1 => GPR_Op1(14),
      I2 => \EX_Branch_CMP_Op1_reg[14]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(14),
      O => ex_sel_alu_i_reg(17)
    );
\Using_FPGA.Native_i_1__25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[15]\,
      I1 => GPR_Op1(15),
      I2 => \EX_Branch_CMP_Op1_reg[15]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(15),
      O => ex_sel_alu_i_reg(16)
    );
\Using_FPGA.Native_i_1__26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[16]\,
      I1 => GPR_Op1(16),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(7),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(16),
      O => ex_sel_alu_i_reg(15)
    );
\Using_FPGA.Native_i_1__27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[17]\,
      I1 => GPR_Op1(17),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(6),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(17),
      O => ex_sel_alu_i_reg(14)
    );
\Using_FPGA.Native_i_1__28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[18]\,
      I1 => GPR_Op1(18),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(5),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(18),
      O => ex_sel_alu_i_reg(13)
    );
\Using_FPGA.Native_i_1__29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[19]\,
      I1 => GPR_Op1(19),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(4),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(19),
      O => ex_sel_alu_i_reg(12)
    );
\Using_FPGA.Native_i_1__30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[20]\,
      I1 => GPR_Op1(20),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(3),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(20),
      O => ex_sel_alu_i_reg(11)
    );
\Using_FPGA.Native_i_1__31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[21]\,
      I1 => GPR_Op1(21),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(2),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(21),
      O => ex_sel_alu_i_reg(10)
    );
\Using_FPGA.Native_i_1__32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[22]\,
      I1 => GPR_Op1(22),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(1),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(22),
      O => ex_sel_alu_i_reg(9)
    );
\Using_FPGA.Native_i_1__33\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[23]\,
      I1 => GPR_Op1(23),
      I2 => \EX_Branch_CMP_Op1_reg[16]_0\(0),
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(23),
      O => ex_sel_alu_i_reg(8)
    );
\Using_FPGA.Native_i_1__34\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[24]\,
      I1 => GPR_Op1(24),
      I2 => \EX_Branch_CMP_Op1_reg[24]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(24),
      O => ex_sel_alu_i_reg(7)
    );
\Using_FPGA.Native_i_1__35\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[25]\,
      I1 => GPR_Op1(25),
      I2 => \EX_Branch_CMP_Op1_reg[25]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(25),
      O => ex_sel_alu_i_reg(6)
    );
\Using_FPGA.Native_i_1__36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[26]\,
      I1 => GPR_Op1(26),
      I2 => \EX_Branch_CMP_Op1_reg[26]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(26),
      O => ex_sel_alu_i_reg(5)
    );
\Using_FPGA.Native_i_1__37\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[27]\,
      I1 => GPR_Op1(27),
      I2 => \EX_Branch_CMP_Op1_reg[27]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(27),
      O => ex_sel_alu_i_reg(4)
    );
\Using_FPGA.Native_i_1__38\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[28]\,
      I1 => GPR_Op1(28),
      I2 => \EX_Branch_CMP_Op1_reg[28]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(28),
      O => ex_sel_alu_i_reg(3)
    );
\Using_FPGA.Native_i_1__39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[29]\,
      I1 => GPR_Op1(29),
      I2 => \EX_Branch_CMP_Op1_reg[29]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(29),
      O => ex_sel_alu_i_reg(2)
    );
\Using_FPGA.Native_i_1__40\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[30]\,
      I1 => GPR_Op1(30),
      I2 => \EX_Branch_CMP_Op1_reg[30]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(30),
      O => ex_sel_alu_i_reg(1)
    );
\Using_FPGA.Native_i_1__41\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[31]\,
      I1 => GPR_Op1(31),
      I2 => \EX_Branch_CMP_Op1_reg[31]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(31),
      O => ex_sel_alu_i_reg(0)
    );
\Using_FPGA.Native_i_2__24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Branch_CMP_Op1_reg[0]\,
      I1 => GPR_Op1(0),
      I2 => \EX_Branch_CMP_Op1_reg[0]_0\,
      I3 => of_op1_sel(0),
      I4 => of_op1_sel(1),
      I5 => MEM_Fwd(0),
      O => ex_sel_alu_i_reg(31)
    );
\Using_FPGA.Native_i_5__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => \of_read_mem_write_op1_conflict__0\,
      I1 => \of_read_wb_write_op1_conflict__0\,
      I2 => \of_read_ex_write_op1_conflict__0\,
      O => of_op1_sel(0)
    );
\Using_FPGA.Native_i_6__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \of_read_mem_write_op1_conflict__0\,
      I1 => \of_read_wb_write_op1_conflict__0\,
      I2 => \of_read_ex_write_op1_conflict__0\,
      O => of_op1_sel(1)
    );
\Using_FPGA.Native_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9000009000000000"
    )
        port map (
      I0 => \Using_FPGA.Native_i_5__0_0\(1),
      I1 => \^using_fpga.native_0\,
      I2 => \Using_FPGA.Native_i_5__0_1\,
      I3 => \Using_FPGA.Native_i_5__0_2\,
      I4 => \Using_FPGA.Native_i_5__0_0\(0),
      I5 => p_213_in,
      O => \of_read_mem_write_op1_conflict__0\
    );
\Using_FPGA.Native_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200000000008200"
    )
        port map (
      I0 => \Using_FPGA.Native_i_5__0_3\,
      I1 => \Using_FPGA.Native_i_5__0_4\(1),
      I2 => \^using_fpga.native_0\,
      I3 => \Using_FPGA.Native_i_5__0_5\,
      I4 => \Using_FPGA.Native_i_5__0_2\,
      I5 => \Using_FPGA.Native_i_5__0_4\(0),
      O => \of_read_wb_write_op1_conflict__0\
    );
\Using_FPGA.Native_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9000009000000000"
    )
        port map (
      I0 => \Using_FPGA.Native_i_5__0_6\(1),
      I1 => \^using_fpga.native_0\,
      I2 => \Using_FPGA.Native_i_5__0_7\,
      I3 => \Using_FPGA.Native_i_5__0_2\,
      I4 => \Using_FPGA.Native_i_5__0_6\(0),
      I5 => p_216_in,
      O => \of_read_ex_write_op1_conflict__0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_173 is
  port (
    of_predecode : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    of_instr_ii_8 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_173 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_173;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_173 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_8,
      Q => of_predecode(0),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_175 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_7 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_175 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_175;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_175 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_7,
      Q => \Using_FPGA.Native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_177 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_6 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_177 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_177;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_177 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_6,
      Q => \Using_FPGA.Native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_179 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \mem_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    \wb_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    \ex_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_5 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_i_7\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \Using_FPGA.Native_i_7_0\ : in STD_LOGIC;
    \Using_FPGA.Native_i_7_1\ : in STD_LOGIC;
    \Using_FPGA.Native_i_8\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \Using_FPGA.Native_i_9\ : in STD_LOGIC;
    I4 : in STD_LOGIC;
    I0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_179 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_179;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_179 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_5,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \Using_FPGA.Native_i_7\(0),
      I1 => \^using_fpga.native_0\,
      I2 => \Using_FPGA.Native_i_7_0\,
      I3 => \Using_FPGA.Native_i_7\(2),
      I4 => \Using_FPGA.Native_i_7_1\,
      I5 => \Using_FPGA.Native_i_7\(1),
      O => \mem_gpr_write_addr_reg[4]\
    );
\Using_FPGA.Native_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \Using_FPGA.Native_i_8\(0),
      I1 => \^using_fpga.native_0\,
      I2 => \Using_FPGA.Native_i_7_0\,
      I3 => \Using_FPGA.Native_i_8\(2),
      I4 => \Using_FPGA.Native_i_7_1\,
      I5 => \Using_FPGA.Native_i_8\(1),
      O => \wb_gpr_write_addr_reg[4]\
    );
\Using_FPGA.Native_i_13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \Using_FPGA.Native_i_9\,
      I1 => \^using_fpga.native_0\,
      I2 => \Using_FPGA.Native_i_7_0\,
      I3 => I4,
      I4 => \Using_FPGA.Native_i_7_1\,
      I5 => I0,
      O => \ex_gpr_write_addr_reg[4]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_181 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_sel_alu_i_reg : out STD_LOGIC_VECTOR ( 31 downto 0 );
    sync_reset : in STD_LOGIC;
    of_instr_ii_4 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \EX_Op2_reg[31]\ : in STD_LOGIC;
    \EX_Op2_reg[31]_0\ : in STD_LOGIC;
    \EX_Op2_reg[31]_1\ : in STD_LOGIC;
    MEM_Fwd : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Op2_reg[30]\ : in STD_LOGIC;
    \EX_Op2_reg[30]_0\ : in STD_LOGIC;
    \EX_Op2_reg[30]_1\ : in STD_LOGIC;
    \EX_Op2_reg[29]\ : in STD_LOGIC;
    \EX_Op2_reg[29]_0\ : in STD_LOGIC;
    \EX_Op2_reg[29]_1\ : in STD_LOGIC;
    \EX_Op2_reg[28]\ : in STD_LOGIC;
    \EX_Op2_reg[28]_0\ : in STD_LOGIC;
    \EX_Op2_reg[28]_1\ : in STD_LOGIC;
    \EX_Op2_reg[27]\ : in STD_LOGIC;
    \EX_Op2_reg[27]_0\ : in STD_LOGIC;
    \EX_Op2_reg[27]_1\ : in STD_LOGIC;
    \EX_Op2_reg[26]\ : in STD_LOGIC;
    \EX_Op2_reg[26]_0\ : in STD_LOGIC;
    \EX_Op2_reg[26]_1\ : in STD_LOGIC;
    \EX_Op2_reg[25]\ : in STD_LOGIC;
    \EX_Op2_reg[25]_0\ : in STD_LOGIC;
    \EX_Op2_reg[25]_1\ : in STD_LOGIC;
    \EX_Op2_reg[24]\ : in STD_LOGIC;
    \EX_Op2_reg[24]_0\ : in STD_LOGIC;
    \EX_Op2_reg[24]_1\ : in STD_LOGIC;
    \EX_Op2_reg[23]\ : in STD_LOGIC;
    \EX_Op2_reg[23]_0\ : in STD_LOGIC;
    \EX_Op2_reg[16]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \EX_Op2_reg[22]\ : in STD_LOGIC;
    \EX_Op2_reg[22]_0\ : in STD_LOGIC;
    \EX_Op2_reg[21]\ : in STD_LOGIC;
    \EX_Op2_reg[21]_0\ : in STD_LOGIC;
    \EX_Op2_reg[20]\ : in STD_LOGIC;
    \EX_Op2_reg[20]_0\ : in STD_LOGIC;
    \EX_Op2_reg[19]\ : in STD_LOGIC;
    \EX_Op2_reg[19]_0\ : in STD_LOGIC;
    \EX_Op2_reg[18]\ : in STD_LOGIC;
    \EX_Op2_reg[18]_0\ : in STD_LOGIC;
    \EX_Op2_reg[17]\ : in STD_LOGIC;
    \EX_Op2_reg[17]_0\ : in STD_LOGIC;
    \EX_Op2_reg[16]_0\ : in STD_LOGIC;
    \EX_Op2_reg[16]_1\ : in STD_LOGIC;
    \EX_Op2_reg[15]\ : in STD_LOGIC;
    \EX_Op2_reg[15]_0\ : in STD_LOGIC;
    \EX_Op2_reg[15]_1\ : in STD_LOGIC;
    \EX_Op2_reg[14]\ : in STD_LOGIC;
    \EX_Op2_reg[14]_0\ : in STD_LOGIC;
    \EX_Op2_reg[14]_1\ : in STD_LOGIC;
    \EX_Op2_reg[13]\ : in STD_LOGIC;
    \EX_Op2_reg[13]_0\ : in STD_LOGIC;
    \EX_Op2_reg[13]_1\ : in STD_LOGIC;
    \EX_Op2_reg[12]\ : in STD_LOGIC;
    \EX_Op2_reg[12]_0\ : in STD_LOGIC;
    \EX_Op2_reg[12]_1\ : in STD_LOGIC;
    \EX_Op2_reg[11]\ : in STD_LOGIC;
    \EX_Op2_reg[11]_0\ : in STD_LOGIC;
    \EX_Op2_reg[11]_1\ : in STD_LOGIC;
    \EX_Op2_reg[10]\ : in STD_LOGIC;
    \EX_Op2_reg[10]_0\ : in STD_LOGIC;
    \EX_Op2_reg[10]_1\ : in STD_LOGIC;
    \EX_Op2_reg[9]\ : in STD_LOGIC;
    \EX_Op2_reg[9]_0\ : in STD_LOGIC;
    \EX_Op2_reg[9]_1\ : in STD_LOGIC;
    \EX_Op2_reg[8]\ : in STD_LOGIC;
    \EX_Op2_reg[8]_0\ : in STD_LOGIC;
    \EX_Op2_reg[8]_1\ : in STD_LOGIC;
    \EX_Op2_reg[7]\ : in STD_LOGIC;
    \EX_Op2_reg[7]_0\ : in STD_LOGIC;
    \EX_Op2_reg[7]_1\ : in STD_LOGIC;
    \EX_Op2_reg[6]\ : in STD_LOGIC;
    \EX_Op2_reg[6]_0\ : in STD_LOGIC;
    \EX_Op2_reg[6]_1\ : in STD_LOGIC;
    \EX_Op2_reg[5]\ : in STD_LOGIC;
    \EX_Op2_reg[5]_0\ : in STD_LOGIC;
    \EX_Op2_reg[5]_1\ : in STD_LOGIC;
    \EX_Op2_reg[4]\ : in STD_LOGIC;
    \EX_Op2_reg[4]_0\ : in STD_LOGIC;
    \EX_Op2_reg[4]_1\ : in STD_LOGIC;
    \EX_Op2_reg[3]\ : in STD_LOGIC;
    \EX_Op2_reg[3]_0\ : in STD_LOGIC;
    \EX_Op2_reg[3]_1\ : in STD_LOGIC;
    \EX_Op2_reg[2]\ : in STD_LOGIC;
    \EX_Op2_reg[2]_0\ : in STD_LOGIC;
    \EX_Op2_reg[2]_1\ : in STD_LOGIC;
    \EX_Op2_reg[1]\ : in STD_LOGIC;
    \EX_Op2_reg[1]_0\ : in STD_LOGIC;
    \EX_Op2_reg[1]_1\ : in STD_LOGIC;
    \EX_Op2_reg[0]\ : in STD_LOGIC;
    \EX_Op2_reg[0]_0\ : in STD_LOGIC;
    \EX_Op2_reg[0]_1\ : in STD_LOGIC;
    of_use_op2_s : in STD_LOGIC;
    \EX_Op2[0]_i_3_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Op2[0]_i_3_1\ : in STD_LOGIC;
    \EX_Op2[0]_i_3_2\ : in STD_LOGIC;
    p_213_in : in STD_LOGIC;
    \EX_Op2[0]_i_3_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Op2[0]_i_3_4\ : in STD_LOGIC;
    p_216_in : in STD_LOGIC;
    \EX_Op2[0]_i_3_5\ : in STD_LOGIC;
    \EX_Op2[0]_i_3_6\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Op2[0]_i_3_7\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_181 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_181;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_181 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal of_op2_sel : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \of_read_ex_write_op2_conflict__0\ : STD_LOGIC;
  signal \of_read_mem_write_op2_conflict__0\ : STD_LOGIC;
  signal \of_read_wb_write_op2_conflict__0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[0]\,
      I1 => \EX_Op2_reg[0]_0\,
      I2 => \EX_Op2_reg[0]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(0),
      O => ex_sel_alu_i_reg(31)
    );
\EX_Op2[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2220"
    )
        port map (
      I0 => of_use_op2_s,
      I1 => \of_read_ex_write_op2_conflict__0\,
      I2 => \of_read_wb_write_op2_conflict__0\,
      I3 => \of_read_mem_write_op2_conflict__0\,
      O => of_op2_sel(0)
    );
\EX_Op2[0]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88A8"
    )
        port map (
      I0 => of_use_op2_s,
      I1 => \of_read_ex_write_op2_conflict__0\,
      I2 => \of_read_wb_write_op2_conflict__0\,
      I3 => \of_read_mem_write_op2_conflict__0\,
      O => of_op2_sel(1)
    );
\EX_Op2[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9000009000000000"
    )
        port map (
      I0 => \EX_Op2[0]_i_3_3\(1),
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op2[0]_i_3_4\,
      I3 => \EX_Op2[0]_i_3_2\,
      I4 => \EX_Op2[0]_i_3_3\(0),
      I5 => p_216_in,
      O => \of_read_ex_write_op2_conflict__0\
    );
\EX_Op2[0]_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8200000000008200"
    )
        port map (
      I0 => \EX_Op2[0]_i_3_5\,
      I1 => \EX_Op2[0]_i_3_6\(1),
      I2 => \^using_fpga.native_0\,
      I3 => \EX_Op2[0]_i_3_7\,
      I4 => \EX_Op2[0]_i_3_2\,
      I5 => \EX_Op2[0]_i_3_6\(0),
      O => \of_read_wb_write_op2_conflict__0\
    );
\EX_Op2[0]_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9000009000000000"
    )
        port map (
      I0 => \EX_Op2[0]_i_3_0\(1),
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op2[0]_i_3_1\,
      I3 => \EX_Op2[0]_i_3_2\,
      I4 => \EX_Op2[0]_i_3_0\(0),
      I5 => p_213_in,
      O => \of_read_mem_write_op2_conflict__0\
    );
\EX_Op2[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[10]\,
      I1 => \EX_Op2_reg[10]_0\,
      I2 => \EX_Op2_reg[10]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(10),
      O => ex_sel_alu_i_reg(21)
    );
\EX_Op2[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[11]\,
      I1 => \EX_Op2_reg[11]_0\,
      I2 => \EX_Op2_reg[11]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(11),
      O => ex_sel_alu_i_reg(20)
    );
\EX_Op2[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[12]\,
      I1 => \EX_Op2_reg[12]_0\,
      I2 => \EX_Op2_reg[12]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(12),
      O => ex_sel_alu_i_reg(19)
    );
\EX_Op2[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[13]\,
      I1 => \EX_Op2_reg[13]_0\,
      I2 => \EX_Op2_reg[13]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(13),
      O => ex_sel_alu_i_reg(18)
    );
\EX_Op2[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[14]\,
      I1 => \EX_Op2_reg[14]_0\,
      I2 => \EX_Op2_reg[14]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(14),
      O => ex_sel_alu_i_reg(17)
    );
\EX_Op2[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[15]\,
      I1 => \EX_Op2_reg[15]_0\,
      I2 => \EX_Op2_reg[15]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(15),
      O => ex_sel_alu_i_reg(16)
    );
\EX_Op2[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[16]_0\,
      I1 => \EX_Op2_reg[16]_1\,
      I2 => \EX_Op2_reg[16]\(7),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(16),
      O => ex_sel_alu_i_reg(15)
    );
\EX_Op2[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[17]\,
      I1 => \EX_Op2_reg[17]_0\,
      I2 => \EX_Op2_reg[16]\(6),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(17),
      O => ex_sel_alu_i_reg(14)
    );
\EX_Op2[18]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[18]\,
      I1 => \EX_Op2_reg[18]_0\,
      I2 => \EX_Op2_reg[16]\(5),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(18),
      O => ex_sel_alu_i_reg(13)
    );
\EX_Op2[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[19]\,
      I1 => \EX_Op2_reg[19]_0\,
      I2 => \EX_Op2_reg[16]\(4),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(19),
      O => ex_sel_alu_i_reg(12)
    );
\EX_Op2[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[1]\,
      I1 => \EX_Op2_reg[1]_0\,
      I2 => \EX_Op2_reg[1]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(1),
      O => ex_sel_alu_i_reg(30)
    );
\EX_Op2[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[20]\,
      I1 => \EX_Op2_reg[20]_0\,
      I2 => \EX_Op2_reg[16]\(3),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(20),
      O => ex_sel_alu_i_reg(11)
    );
\EX_Op2[21]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[21]\,
      I1 => \EX_Op2_reg[21]_0\,
      I2 => \EX_Op2_reg[16]\(2),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(21),
      O => ex_sel_alu_i_reg(10)
    );
\EX_Op2[22]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[22]\,
      I1 => \EX_Op2_reg[22]_0\,
      I2 => \EX_Op2_reg[16]\(1),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(22),
      O => ex_sel_alu_i_reg(9)
    );
\EX_Op2[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[23]\,
      I1 => \EX_Op2_reg[23]_0\,
      I2 => \EX_Op2_reg[16]\(0),
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(23),
      O => ex_sel_alu_i_reg(8)
    );
\EX_Op2[24]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[24]\,
      I1 => \EX_Op2_reg[24]_0\,
      I2 => \EX_Op2_reg[24]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(24),
      O => ex_sel_alu_i_reg(7)
    );
\EX_Op2[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[25]\,
      I1 => \EX_Op2_reg[25]_0\,
      I2 => \EX_Op2_reg[25]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(25),
      O => ex_sel_alu_i_reg(6)
    );
\EX_Op2[26]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[26]\,
      I1 => \EX_Op2_reg[26]_0\,
      I2 => \EX_Op2_reg[26]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(26),
      O => ex_sel_alu_i_reg(5)
    );
\EX_Op2[27]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[27]\,
      I1 => \EX_Op2_reg[27]_0\,
      I2 => \EX_Op2_reg[27]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(27),
      O => ex_sel_alu_i_reg(4)
    );
\EX_Op2[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[28]\,
      I1 => \EX_Op2_reg[28]_0\,
      I2 => \EX_Op2_reg[28]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(28),
      O => ex_sel_alu_i_reg(3)
    );
\EX_Op2[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[29]\,
      I1 => \EX_Op2_reg[29]_0\,
      I2 => \EX_Op2_reg[29]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(29),
      O => ex_sel_alu_i_reg(2)
    );
\EX_Op2[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[2]\,
      I1 => \EX_Op2_reg[2]_0\,
      I2 => \EX_Op2_reg[2]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(2),
      O => ex_sel_alu_i_reg(29)
    );
\EX_Op2[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[30]\,
      I1 => \EX_Op2_reg[30]_0\,
      I2 => \EX_Op2_reg[30]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(30),
      O => ex_sel_alu_i_reg(1)
    );
\EX_Op2[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[31]\,
      I1 => \EX_Op2_reg[31]_0\,
      I2 => \EX_Op2_reg[31]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(31),
      O => ex_sel_alu_i_reg(0)
    );
\EX_Op2[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[3]\,
      I1 => \EX_Op2_reg[3]_0\,
      I2 => \EX_Op2_reg[3]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(3),
      O => ex_sel_alu_i_reg(28)
    );
\EX_Op2[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[4]\,
      I1 => \EX_Op2_reg[4]_0\,
      I2 => \EX_Op2_reg[4]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(4),
      O => ex_sel_alu_i_reg(27)
    );
\EX_Op2[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[5]\,
      I1 => \EX_Op2_reg[5]_0\,
      I2 => \EX_Op2_reg[5]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(5),
      O => ex_sel_alu_i_reg(26)
    );
\EX_Op2[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[6]\,
      I1 => \EX_Op2_reg[6]_0\,
      I2 => \EX_Op2_reg[6]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(6),
      O => ex_sel_alu_i_reg(25)
    );
\EX_Op2[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[7]\,
      I1 => \EX_Op2_reg[7]_0\,
      I2 => \EX_Op2_reg[7]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(7),
      O => ex_sel_alu_i_reg(24)
    );
\EX_Op2[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[8]\,
      I1 => \EX_Op2_reg[8]_0\,
      I2 => \EX_Op2_reg[8]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(8),
      O => ex_sel_alu_i_reg(23)
    );
\EX_Op2[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F0AAFFCCF0AA00CC"
    )
        port map (
      I0 => \EX_Op2_reg[9]\,
      I1 => \EX_Op2_reg[9]_0\,
      I2 => \EX_Op2_reg[9]_1\,
      I3 => of_op2_sel(0),
      I4 => of_op2_sel(1),
      I5 => MEM_Fwd(9),
      O => ex_sel_alu_i_reg(22)
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_4,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_183 is
  port (
    of_predecode : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    of_instr_ii_3 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_183 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_183;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_183 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_3,
      Q => of_predecode(0),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_185 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_branch_with_delayslot_i_reg : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    ex_op1_cmp_eq_n5_out : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    use_Reg_Neg_DI1_out : out STD_LOGIC;
    force_Val10_out : out STD_LOGIC;
    use_Reg_Neg_S3_out : out STD_LOGIC;
    force12_out : out STD_LOGIC;
    ex_sel_alu_i0 : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ex_enable_sext_shift_i0 : out STD_LOGIC;
    \Using_FPGA.Native_5\ : out STD_LOGIC;
    \Using_FPGA.Native_6\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_39 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_branch_with_delayslot_i : in STD_LOGIC;
    ex_branch_with_delayslot_i_reg_0 : in STD_LOGIC;
    ex_branch_with_delayslot_i_reg_1 : in STD_LOGIC;
    ex_op1_cmp_eq_n_reg : in STD_LOGIC;
    ex_op1_cmp_eq_n_reg_0 : in STD_LOGIC;
    ex_op1_cmp_eq_n_reg_1 : in STD_LOGIC;
    force2_reg : in STD_LOGIC;
    force2_reg_0 : in STD_LOGIC;
    force2_reg_1 : in STD_LOGIC;
    force2_reg_2 : in STD_LOGIC;
    \EX_Sext_Op_reg[0]\ : in STD_LOGIC;
    ex_sel_alu_i_reg : in STD_LOGIC;
    \EX_Sext_Op_reg[0]_0\ : in STD_LOGIC;
    \EX_Sext_Op_reg[0]_1\ : in STD_LOGIC;
    ex_branch_with_delayslot_reg : in STD_LOGIC;
    ex_branch_with_delayslot_reg_0 : in STD_LOGIC;
    \EX_ALU_Op1142_out__0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_185 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_185;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_185 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \^using_fpga.native_1\ : STD_LOGIC;
  signal \^using_fpga.native_2\ : STD_LOGIC;
  signal ex_branch_with_delayslot_i_2_n_0 : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_2__83\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of ex_branch_with_delayslot_i_1 : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of ex_enable_sext_shift_i_i_1 : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of ex_load_alu_carry_i_1 : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of ex_op1_cmp_eq_n_i_1 : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of ex_sel_alu_i_i_1 : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of force2_i_1 : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of force_Val1_i_1 : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of use_Reg_Neg_DI_i_1 : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of use_Reg_Neg_S_i_1 : label is "soft_lutpair15";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  \Using_FPGA.Native_1\ <= \^using_fpga.native_1\;
  \Using_FPGA.Native_2\ <= \^using_fpga.native_2\;
\EX_Sext_Op[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF7FFF"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \EX_Sext_Op_reg[0]_0\,
      I2 => force2_reg,
      I3 => \EX_Sext_Op_reg[0]_1\,
      I4 => force2_reg_1,
      I5 => \EX_Sext_Op_reg[0]\,
      O => \Using_FPGA.Native_4\(0)
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_39,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_2__83\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => force2_reg,
      I2 => force2_reg_0,
      I3 => \EX_Sext_Op_reg[0]\,
      O => \Using_FPGA.Native_5\
    );
ex_branch_with_delayslot_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => ex_branch_with_delayslot_i_2_n_0,
      I1 => force2_reg,
      I2 => force2_reg_1,
      O => \^using_fpga.native_1\
    );
ex_branch_with_delayslot_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AA80A0800A800080"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_branch_with_delayslot_reg,
      I2 => force2_reg_2,
      I3 => force2_reg_0,
      I4 => \EX_Sext_Op_reg[0]\,
      I5 => ex_branch_with_delayslot_reg_0,
      O => ex_branch_with_delayslot_i_2_n_0
    );
ex_branch_with_delayslot_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => ex_branch_with_delayslot_i,
      I1 => ex_branch_with_delayslot_i_reg_0,
      I2 => \^using_fpga.native_1\,
      I3 => ex_branch_with_delayslot_i_reg_1,
      I4 => sync_reset,
      O => ex_branch_with_delayslot_i_reg
    );
ex_enable_sext_shift_i_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => force2_reg_1,
      I2 => force2_reg,
      O => ex_enable_sext_shift_i0
    );
ex_load_alu_carry_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => force2_reg,
      I2 => force2_reg_1,
      I3 => \EX_ALU_Op1142_out__0\,
      O => \Using_FPGA.Native_6\
    );
ex_op1_cmp_eq_n_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => \^using_fpga.native_2\,
      I1 => ex_op1_cmp_eq_n_reg,
      I2 => ex_op1_cmp_eq_n_reg_0,
      I3 => ex_op1_cmp_eq_n_reg_1,
      O => ex_op1_cmp_eq_n5_out
    );
ex_sel_alu_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"51FF"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_sel_alu_i_reg,
      I2 => \EX_Sext_Op_reg[0]\,
      I3 => force2_reg,
      O => ex_sel_alu_i0
    );
force1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^using_fpga.native_2\,
      I1 => ex_op1_cmp_eq_n_reg_1,
      I2 => ex_op1_cmp_eq_n_reg,
      O => force12_out
    );
force2_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"08000000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => force2_reg_2,
      I2 => force2_reg_1,
      I3 => force2_reg_0,
      I4 => force2_reg,
      O => \^using_fpga.native_2\
    );
force_Val1_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => \^using_fpga.native_2\,
      I1 => ex_op1_cmp_eq_n_reg_1,
      I2 => ex_op1_cmp_eq_n_reg,
      O => force_Val10_out
    );
force_Val2_N_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF7FF7FFFF7FFFF"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => force2_reg,
      I2 => force2_reg_0,
      I3 => force2_reg_1,
      I4 => force2_reg_2,
      I5 => \EX_Sext_Op_reg[0]\,
      O => \Using_FPGA.Native_3\
    );
use_Reg_Neg_DI_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0820"
    )
        port map (
      I0 => \^using_fpga.native_2\,
      I1 => ex_op1_cmp_eq_n_reg_1,
      I2 => ex_op1_cmp_eq_n_reg,
      I3 => ex_op1_cmp_eq_n_reg_0,
      O => use_Reg_Neg_DI1_out
    );
use_Reg_Neg_S_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0820"
    )
        port map (
      I0 => \^using_fpga.native_2\,
      I1 => ex_op1_cmp_eq_n_reg,
      I2 => ex_op1_cmp_eq_n_reg_1,
      I3 => ex_op1_cmp_eq_n_reg_0,
      O => use_Reg_Neg_S3_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_187 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_2 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_187 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_187;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_187 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_2,
      Q => \Using_FPGA.Native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_189 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_1 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_189 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_189;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_189 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_1,
      Q => \Using_FPGA.Native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_191 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \mem_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    \wb_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    \ex_gpr_write_addr_reg[4]\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_0 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \EX_Op2[0]_i_8\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \EX_Op2[0]_i_8_0\ : in STD_LOGIC;
    \EX_Op2[0]_i_8_1\ : in STD_LOGIC;
    \EX_Op2[0]_i_7\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \EX_Op2[0]_i_6\ : in STD_LOGIC;
    I4 : in STD_LOGIC;
    I0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_191 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_191;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_191 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op2[0]_i_10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \EX_Op2[0]_i_7\(0),
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op2[0]_i_8_0\,
      I3 => \EX_Op2[0]_i_7\(2),
      I4 => \EX_Op2[0]_i_8_1\,
      I5 => \EX_Op2[0]_i_7\(1),
      O => \wb_gpr_write_addr_reg[4]\
    );
\EX_Op2[0]_i_11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \EX_Op2[0]_i_8\(0),
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op2[0]_i_8_0\,
      I3 => \EX_Op2[0]_i_8\(2),
      I4 => \EX_Op2[0]_i_8_1\,
      I5 => \EX_Op2[0]_i_8\(1),
      O => \mem_gpr_write_addr_reg[4]\
    );
\EX_Op2[0]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => \EX_Op2[0]_i_6\,
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op2[0]_i_8_0\,
      I3 => I4,
      I4 => \EX_Op2[0]_i_8_1\,
      I5 => I0,
      O => \ex_gpr_write_addr_reg[4]\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_0,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_193 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    of_Sel_SPR_MSR1 : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    ex_load_shift_carry0 : out STD_LOGIC;
    p_0_in30_in : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    D224_out : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_5\ : out STD_LOGIC;
    p_9_in : out STD_LOGIC;
    \Using_FPGA.Native_6\ : out STD_LOGIC;
    \Using_FPGA.Native_7\ : out STD_LOGIC;
    \Using_FPGA.Native_8\ : out STD_LOGIC;
    \Using_FPGA.Native_9\ : out STD_LOGIC;
    \Using_FPGA.Native_10\ : out STD_LOGIC;
    \Using_FPGA.Native_11\ : out STD_LOGIC;
    \Using_FPGA.Native_12\ : out STD_LOGIC;
    \Using_FPGA.Native_13\ : out STD_LOGIC;
    \Using_FPGA.Native_14\ : out STD_LOGIC;
    \Using_FPGA.Native_15\ : out STD_LOGIC;
    \Using_FPGA.Native_16\ : out STD_LOGIC;
    \Using_FPGA.Native_17\ : out STD_LOGIC;
    \Using_FPGA.Native_18\ : out STD_LOGIC;
    \Using_FPGA.Native_19\ : out STD_LOGIC;
    \Using_FPGA.Native_20\ : out STD_LOGIC;
    \Using_FPGA.Native_21\ : out STD_LOGIC;
    \Using_FPGA.Native_22\ : out STD_LOGIC;
    \Using_FPGA.Native_23\ : out STD_LOGIC;
    \Using_FPGA.Native_24\ : out STD_LOGIC;
    \Using_FPGA.Native_25\ : out STD_LOGIC;
    \Using_FPGA.Native_26\ : out STD_LOGIC;
    \Using_FPGA.Native_27\ : out STD_LOGIC;
    \Using_FPGA.Native_28\ : out STD_LOGIC;
    \Using_FPGA.Native_29\ : out STD_LOGIC;
    \Using_FPGA.Native_30\ : out STD_LOGIC;
    \Using_FPGA.Native_31\ : out STD_LOGIC;
    \Using_FPGA.Native_32\ : out STD_LOGIC;
    \Using_FPGA.Native_33\ : out STD_LOGIC;
    \Using_FPGA.Native_34\ : out STD_LOGIC;
    \Using_FPGA.Native_35\ : out STD_LOGIC;
    \Using_FPGA.Native_36\ : out STD_LOGIC;
    I1_0 : out STD_LOGIC;
    of_Sel_SPR_MSR88_out : out STD_LOGIC;
    ex_is_multi_or_load_instr0 : out STD_LOGIC;
    of_op1_sel_spr : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_38 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_is_multi_instr2_reg : in STD_LOGIC;
    \Using_FPGA.Native_37\ : in STD_LOGIC;
    EX_SWAP_Instr_reg : in STD_LOGIC;
    EX_SWAP_Instr_reg_0 : in STD_LOGIC;
    EX_SWAP_Instr_reg_1 : in STD_LOGIC;
    EX_SWAP_Instr_reg_2 : in STD_LOGIC;
    ex_is_multi_or_load_instr_reg : in STD_LOGIC;
    ex_is_multi_or_load_instr_reg_0 : in STD_LOGIC;
    \Using_FPGA.Native_38\ : in STD_LOGIC;
    \Using_FPGA.Native_39\ : in STD_LOGIC;
    \Using_FPGA.Native_40\ : in STD_LOGIC;
    \EX_Sext_Op_reg[1]\ : in STD_LOGIC;
    ex_load_shift_carry_reg : in STD_LOGIC;
    ex_is_multi_or_load_instr_reg_1 : in STD_LOGIC;
    \OF_Op1_Sel_SPR_PC0__0\ : in STD_LOGIC;
    \EX_Op1_reg[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ex_MSR : in STD_LOGIC_VECTOR ( 2 downto 0 );
    ex_mfsmsr_i_reg : in STD_LOGIC;
    ex_mfsmsr_i_reg_0 : in STD_LOGIC;
    ex_mfsmsr_i_reg_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_193 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_193;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_193 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \^using_fpga.native_1\ : STD_LOGIC;
  signal \^p_0_in30_in\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__43\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__47\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of ex_is_multi_instr2_i_1 : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of ex_is_multi_or_load_instr_i_1 : label is "soft_lutpair18";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  \Using_FPGA.Native_1\ <= \^using_fpga.native_1\;
  p_0_in30_in <= \^p_0_in30_in\;
Dbg_Clean_Stop_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000400000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_load_shift_carry_reg,
      I2 => ex_is_multi_or_load_instr_reg_0,
      I3 => \Using_FPGA.Native_37\,
      I4 => ex_is_multi_or_load_instr_reg_1,
      I5 => ex_is_multi_or_load_instr_reg,
      O => p_9_in
    );
EX_SWAP_Instr_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_37\,
      I2 => EX_SWAP_Instr_reg,
      I3 => EX_SWAP_Instr_reg_0,
      I4 => EX_SWAP_Instr_reg_1,
      I5 => EX_SWAP_Instr_reg_2,
      O => \Using_FPGA.Native_2\
    );
\EX_Sext_Op[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010111111"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_37\,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => EX_SWAP_Instr_reg_0,
      I4 => EX_SWAP_Instr_reg_1,
      I5 => EX_SWAP_Instr_reg_2,
      O => \Using_FPGA.Native_4\(0)
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_38,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__179\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F2"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \OF_Op1_Sel_SPR_PC0__0\,
      O => of_op1_sel_spr
    );
\Using_FPGA.Native_i_1__42\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00080000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_is_multi_or_load_instr_reg,
      I2 => ex_is_multi_or_load_instr_reg_0,
      I3 => \Using_FPGA.Native_38\,
      I4 => \Using_FPGA.Native_39\,
      O => \Using_FPGA.Native_3\
    );
\Using_FPGA.Native_i_1__43\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_40\,
      I2 => ex_is_multi_or_load_instr_reg,
      I3 => \Using_FPGA.Native_39\,
      O => D224_out
    );
\Using_FPGA.Native_i_1__47\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_37\,
      O => \Using_FPGA.Native_5\
    );
\Using_FPGA.Native_i_2__118\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(0),
      O => \Using_FPGA.Native_6\
    );
\Using_FPGA.Native_i_2__119\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF00FDFF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(1),
      I5 => ex_MSR(0),
      O => \Using_FPGA.Native_7\
    );
\Using_FPGA.Native_i_2__120\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF00FDFF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(2),
      I5 => ex_MSR(1),
      O => \Using_FPGA.Native_8\
    );
\Using_FPGA.Native_i_2__121\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF00FDFF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(3),
      I5 => ex_MSR(2),
      O => \Using_FPGA.Native_9\
    );
\Using_FPGA.Native_i_2__122\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(4),
      O => \Using_FPGA.Native_10\
    );
\Using_FPGA.Native_i_2__123\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(5),
      O => \Using_FPGA.Native_11\
    );
\Using_FPGA.Native_i_2__124\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(6),
      O => \Using_FPGA.Native_12\
    );
\Using_FPGA.Native_i_2__125\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(7),
      O => \Using_FPGA.Native_13\
    );
\Using_FPGA.Native_i_2__126\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(8),
      O => \Using_FPGA.Native_14\
    );
\Using_FPGA.Native_i_2__127\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(9),
      O => \Using_FPGA.Native_15\
    );
\Using_FPGA.Native_i_2__128\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(10),
      O => \Using_FPGA.Native_16\
    );
\Using_FPGA.Native_i_2__129\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(11),
      O => \Using_FPGA.Native_17\
    );
\Using_FPGA.Native_i_2__130\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(12),
      O => \Using_FPGA.Native_18\
    );
\Using_FPGA.Native_i_2__131\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(13),
      O => \Using_FPGA.Native_19\
    );
\Using_FPGA.Native_i_2__132\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(14),
      O => \Using_FPGA.Native_20\
    );
\Using_FPGA.Native_i_2__133\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(15),
      O => \Using_FPGA.Native_21\
    );
\Using_FPGA.Native_i_2__134\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(16),
      O => \Using_FPGA.Native_22\
    );
\Using_FPGA.Native_i_2__135\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(17),
      O => \Using_FPGA.Native_23\
    );
\Using_FPGA.Native_i_2__136\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(18),
      O => \Using_FPGA.Native_24\
    );
\Using_FPGA.Native_i_2__137\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(19),
      O => \Using_FPGA.Native_25\
    );
\Using_FPGA.Native_i_2__138\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(20),
      O => \Using_FPGA.Native_26\
    );
\Using_FPGA.Native_i_2__139\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(21),
      O => \Using_FPGA.Native_27\
    );
\Using_FPGA.Native_i_2__140\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(22),
      O => \Using_FPGA.Native_28\
    );
\Using_FPGA.Native_i_2__141\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(23),
      O => \Using_FPGA.Native_29\
    );
\Using_FPGA.Native_i_2__142\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(24),
      O => \Using_FPGA.Native_30\
    );
\Using_FPGA.Native_i_2__143\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(25),
      O => \Using_FPGA.Native_31\
    );
\Using_FPGA.Native_i_2__144\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(26),
      O => \Using_FPGA.Native_32\
    );
\Using_FPGA.Native_i_2__145\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(27),
      O => \Using_FPGA.Native_33\
    );
\Using_FPGA.Native_i_2__146\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(28),
      O => \Using_FPGA.Native_34\
    );
\Using_FPGA.Native_i_2__147\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(29),
      O => \Using_FPGA.Native_35\
    );
\Using_FPGA.Native_i_2__148\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(30),
      O => \Using_FPGA.Native_36\
    );
\Using_FPGA.Native_i_3__32\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF00FDFF020000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => \EX_Sext_Op_reg[1]\,
      I3 => \OF_Op1_Sel_SPR_PC0__0\,
      I4 => \EX_Op1_reg[0]\(31),
      I5 => ex_MSR(1),
      O => I1_0
    );
ex_is_multi_instr2_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      O => of_Sel_SPR_MSR1
    );
ex_is_multi_or_load_instr_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2F22FF22"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => ex_is_multi_or_load_instr_reg_1,
      I3 => ex_is_multi_or_load_instr_reg,
      I4 => ex_is_multi_or_load_instr_reg_0,
      O => ex_is_multi_or_load_instr0
    );
ex_load_shift_carry_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \^p_0_in30_in\,
      I1 => EX_SWAP_Instr_reg_0,
      I2 => EX_SWAP_Instr_reg_1,
      O => ex_load_shift_carry0
    );
ex_load_shift_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000040"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_is_multi_or_load_instr_reg_0,
      I2 => ex_is_multi_or_load_instr_reg_1,
      I3 => \Using_FPGA.Native_37\,
      I4 => ex_load_shift_carry_reg,
      I5 => ex_is_multi_or_load_instr_reg,
      O => \^p_0_in30_in\
    );
ex_mfsmsr_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000200000000"
    )
        port map (
      I0 => \^using_fpga.native_1\,
      I1 => ex_is_multi_instr2_reg,
      I2 => ex_mfsmsr_i_reg,
      I3 => ex_mfsmsr_i_reg_0,
      I4 => ex_mfsmsr_i_reg_1,
      I5 => \EX_Sext_Op_reg[1]\,
      O => of_Sel_SPR_MSR88_out
    );
ex_move_to_MSR_instr_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000010000000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_load_shift_carry_reg,
      I2 => ex_is_multi_or_load_instr_reg_0,
      I3 => \Using_FPGA.Native_37\,
      I4 => ex_is_multi_or_load_instr_reg_1,
      I5 => ex_is_multi_or_load_instr_reg,
      O => \^using_fpga.native_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_195 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_is_div_instr_I_reg : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_37 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    EX_Is_Div_Instr : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_is_div_instr_I_reg_0 : in STD_LOGIC;
    ex_is_div_instr_I_reg_1 : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    ex_is_div_instr_I_reg_2 : in STD_LOGIC;
    ex_is_div_instr_I_reg_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_195 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_195;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_195 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal ex_is_div_instr_I0 : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__48\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of ex_is_div_instr_I_i_2 : label is "soft_lutpair20";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_37,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__48\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_2\,
      O => \Using_FPGA.Native_1\
    );
ex_is_div_instr_I_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC0A"
    )
        port map (
      I0 => EX_Is_Div_Instr,
      I1 => ex_is_div_instr_I0,
      I2 => E(0),
      I3 => ex_is_div_instr_I_reg_0,
      I4 => sync_reset,
      O => ex_is_div_instr_I_reg
    );
ex_is_div_instr_I_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100000"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_is_div_instr_I_reg_1,
      I2 => \Using_FPGA.Native_2\,
      I3 => ex_is_div_instr_I_reg_2,
      I4 => ex_is_div_instr_I_reg_3,
      O => ex_is_div_instr_I0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_197 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \of_read_mem_write_op3_conflict__1\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_36 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \EX_Op3[0]_i_3\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Op3[0]_i_3_0\ : in STD_LOGIC;
    \EX_Op3[0]_i_3_1\ : in STD_LOGIC;
    \EX_Op3[0]_i_3_2\ : in STD_LOGIC;
    \EX_Op3[0]_i_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op3[0]_i_6\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_197 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_197;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_197 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \EX_Op3[0]_i_10\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \EX_Op3[0]_i_12\ : label is "soft_lutpair21";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\EX_Op3[0]_i_10\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \EX_Op3[0]_i_5\(0),
      O => \Using_FPGA.Native_1\
    );
\EX_Op3[0]_i_12\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \EX_Op3[0]_i_6\(0),
      O => \Using_FPGA.Native_2\
    );
\EX_Op3[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9000009000000000"
    )
        port map (
      I0 => \EX_Op3[0]_i_3\(1),
      I1 => \^using_fpga.native_0\,
      I2 => \EX_Op3[0]_i_3_0\,
      I3 => \EX_Op3[0]_i_3_1\,
      I4 => \EX_Op3[0]_i_3\(0),
      I5 => \EX_Op3[0]_i_3_2\,
      O => \of_read_mem_write_op3_conflict__1\
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_36,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_199 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_35 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_mbar_is_sleep_reg : in STD_LOGIC;
    ex_mbar_is_sleep_reg_0 : in STD_LOGIC;
    ex_mbar_is_sleep : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_199 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_199;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_199 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_35,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
ex_mbar_is_sleep_cmb_inferred_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFE0"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_mbar_is_sleep_reg,
      I2 => ex_mbar_is_sleep_reg_0,
      I3 => ex_mbar_is_sleep,
      O => \Using_FPGA.Native_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_201 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \ex_gpr_write111_out__0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_34 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_op1_cmp_eq_reg : in STD_LOGIC;
    ex_op1_cmp_eq_reg_0 : in STD_LOGIC;
    ex_op1_cmp_eq1 : in STD_LOGIC;
    ex_gpr_write_reg : in STD_LOGIC;
    ex_gpr_write_reg_0 : in STD_LOGIC;
    ex_gpr_write_reg_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_201 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_201;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_201 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_34,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
ex_gpr_write_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000002"
    )
        port map (
      I0 => ex_gpr_write_reg,
      I1 => \^using_fpga.native_0\,
      I2 => ex_op1_cmp_eq_reg_0,
      I3 => ex_op1_cmp_eq_reg,
      I4 => ex_gpr_write_reg_0,
      I5 => ex_gpr_write_reg_1,
      O => \ex_gpr_write111_out__0\
    );
ex_op1_cmp_eq_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F9FF"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_op1_cmp_eq_reg,
      I2 => ex_op1_cmp_eq_reg_0,
      I3 => ex_op1_cmp_eq1,
      O => \Using_FPGA.Native_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_203 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_instr_ii_33 : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_203 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_203;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_203 is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_instr_ii_33,
      Q => \Using_FPGA.Native_0\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_205 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ex_branch_with_delayslot_reg : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    Dbg_Clean_Stop0 : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_Valid_II : in STD_LOGIC;
    Clk : in STD_LOGIC;
    p_9_in : in STD_LOGIC;
    ex_branch_with_delayslot : in STD_LOGIC;
    ex_jump_q : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_jump_nodelay : in STD_LOGIC;
    ex_jump : in STD_LOGIC;
    Dbg_Clean_Stop_reg : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_205 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_205;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_205 is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of Dbg_Clean_Stop_i_1 : label is "soft_lutpair22";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM of \imm_reg[0]_i_1\ : label is "soft_lutpair22";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
Dbg_Clean_Stop_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F000F777"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => p_9_in,
      I2 => ex_jump_nodelay,
      I3 => ex_jump,
      I4 => Dbg_Clean_Stop_reg,
      O => Dbg_Clean_Stop0
    );
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_Valid_II,
      Q => \^using_fpga.native_0\,
      R => sync_reset
    );
\Using_FPGA.Native_i_1__101\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAA"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => wb_exception,
      I2 => Q(0),
      I3 => Q(1),
      O => \Using_FPGA.Native_2\
    );
\Using_FPGA.Native_i_1__99\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => ex_branch_with_delayslot,
      I1 => \^using_fpga.native_0\,
      I2 => ex_jump_q,
      O => ex_branch_with_delayslot_reg
    );
\imm_reg[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => p_9_in,
      O => \Using_FPGA.Native_1\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_206 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0125_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_31 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_206 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_206;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_206 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_31,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__127\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0125_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_208 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I085_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_21 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_208 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_208;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_208 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_21,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__137\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I085_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_210 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I081_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_20 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_210 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_210;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_210 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_20,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__138\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I081_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_212 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I077_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_19 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_212 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_212;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_212 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_19,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__139\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I077_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_214 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I073_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_18 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_214 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_214;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_214 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_18,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__140\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I073_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_216 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I069_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_17 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_216 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_216;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_216 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_17,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__141\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I069_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_218 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I065_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_16 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_218 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_218;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_218 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_16,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__142\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I065_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_220 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I061_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_15 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_220 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_220;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_220 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_15,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__143\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I061_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_222 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I057_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_14 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_222 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_222;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_222 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_14,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__144\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I057_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_224 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I053_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_13 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_224 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_224;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_224 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_13,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__145\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I053_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_226 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I049_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_12 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_226 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_226;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_226 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_12,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__146\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I049_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_228 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0121_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_30 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_228 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_228;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_228 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_30,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__128\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0121_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_230 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I045_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_11 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_230 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_230;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_230 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_11,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__147\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I045_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_232 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I041_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_10 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_232 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_232;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_232 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_10,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__148\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I041_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_234 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I037_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_9 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_234 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_234;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_234 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_9,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__149\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I037_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_236 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I033_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_8 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_236 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_236;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_236 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_8,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__150\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I033_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_238 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I029_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_7 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_238 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_238;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_238 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_7,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__151\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I029_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_240 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I025_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_6 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_240 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_240;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_240 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_6,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__152\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I025_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_242 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I021_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_5 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_242 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_242;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_242 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_5,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__153\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I021_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_244 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I017_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_4 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_244 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_244;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_244 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_4,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__154\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I017_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_246 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I013_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_3 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_246 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_246;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_246 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_3,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__155\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I013_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_248 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I09_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_2 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_248 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_248;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_248 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_2,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__156\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I09_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_250 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0117_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_29 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_250 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_250;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_250 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_29,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__129\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0117_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_252 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I05_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_1 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_252 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_252;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_252 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_1,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__157\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I05_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_254 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0 : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_0 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_254 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_254;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_254 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_0,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__158\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_256 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0113_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_28 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_256 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_256;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_256 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_28,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__130\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0113_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_258 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0109_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_27 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_258 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_258;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_258 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_27,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__131\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0109_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_260 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0105_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_26 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_260 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_260;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_260 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_26,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__132\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0105_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_262 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I0101_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_25 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_262 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_262;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_262 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_25,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__133\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I0101_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_264 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I097_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_24 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_264 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_264;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_264 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_24,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__134\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I097_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_266 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I093_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_23 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_266 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_266;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_266 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_23,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__135\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I093_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_268 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    I089_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    of_pc_ii_22 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_268 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_268;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_268 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => of_pc_ii_22,
      Q => \^d\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__136\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => \Using_FPGA.Native_0\,
      I2 => \^d\(0),
      I3 => Q(0),
      O => I089_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_301 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC;
    \WB_MEM_Result_reg[28]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_301 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_301;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_301 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA.Native_0\,
      Q => \^d\(0),
      R => sync_reset
    );
\WB_MEM_Result[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^d\(0),
      I1 => mem_sel_msr,
      I2 => \WB_MEM_Result_reg[28]\(0),
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_302 is
  port (
    mem_MSR : out STD_LOGIC_VECTOR ( 0 to 0 );
    MEM_Fwd : out STD_LOGIC_VECTOR ( 1 downto 0 );
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC;
    \WB_MEM_Result_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_302 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_302;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_302 is
  signal \^mem_msr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \WB_MEM_Result[0]_i_2\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \WB_MEM_Result[29]_i_1\ : label is "soft_lutpair3";
begin
  mem_MSR(0) <= \^mem_msr\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA.Native_0\,
      Q => \^mem_msr\(0),
      R => sync_reset
    );
\WB_MEM_Result[0]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^mem_msr\(0),
      I1 => mem_sel_msr,
      I2 => \WB_MEM_Result_reg[0]\(1),
      O => MEM_Fwd(1)
    );
\WB_MEM_Result[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^mem_msr\(0),
      I1 => mem_sel_msr,
      I2 => \WB_MEM_Result_reg[0]\(0),
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_303 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC;
    \WB_MEM_Result_reg[30]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_303 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_303;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_303 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  D(0) <= \^d\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA.Native_0\,
      Q => \^d\(0),
      R => sync_reset
    );
\WB_MEM_Result[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^d\(0),
      I1 => mem_sel_msr,
      I2 => \WB_MEM_Result_reg[30]\(0),
      O => MEM_Fwd(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_304 is
  port (
    ex_MSR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_304 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_304;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_304 is
  signal \^ex_msr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  ex_MSR(0) <= \^ex_msr\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA.Native_1\,
      Q => \^ex_msr\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__93\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^ex_msr\(0),
      I1 => \Using_FPGA.Native_2\,
      I2 => D(0),
      O => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_305 is
  port (
    ex_MSR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_305 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_305;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_305 is
  signal \^ex_msr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  ex_MSR(0) <= \^ex_msr\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA.Native_1\,
      Q => \^ex_msr\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__92\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^ex_msr\(0),
      I1 => \Using_FPGA.Native_2\,
      I2 => D(0),
      O => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDR_306 is
  port (
    ex_MSR : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDR_306 : entity is "MB_FDR";
end design_1_microblaze_0_0_MB_FDR_306;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDR_306 is
  signal \^ex_msr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDR";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  ex_MSR(0) <= \^ex_msr\(0);
\Using_FPGA.Native\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA.Native_1\,
      Q => \^ex_msr\(0),
      R => sync_reset
    );
\Using_FPGA.Native_i_1__91\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \^ex_msr\(0),
      I1 => \Using_FPGA.Native_2\,
      I2 => D(0),
      O => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_FDS is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    I041_out : out STD_LOGIC;
    I045_out : out STD_LOGIC;
    I049_out : out STD_LOGIC;
    I053_out : out STD_LOGIC;
    I057_out : out STD_LOGIC;
    I061_out : out STD_LOGIC;
    I065_out : out STD_LOGIC;
    I069_out : out STD_LOGIC;
    I073_out : out STD_LOGIC;
    I077_out : out STD_LOGIC;
    I081_out : out STD_LOGIC;
    I085_out : out STD_LOGIC;
    I0129_out : out STD_LOGIC;
    I0133_out : out STD_LOGIC;
    I0137_out : out STD_LOGIC;
    I0141_out : out STD_LOGIC;
    I0145_out : out STD_LOGIC;
    I0149_out : out STD_LOGIC;
    I0153_out : out STD_LOGIC;
    I0157_out : out STD_LOGIC;
    I0161_out : out STD_LOGIC;
    I0165_out : out STD_LOGIC;
    I0169_out : out STD_LOGIC;
    I0125_out : out STD_LOGIC;
    I0121_out : out STD_LOGIC;
    I0117_out : out STD_LOGIC;
    I0113_out : out STD_LOGIC;
    I0109_out : out STD_LOGIC;
    I0105_out : out STD_LOGIC;
    I0101_out : out STD_LOGIC;
    I097_out : out STD_LOGIC;
    I093_out : out STD_LOGIC;
    I089_out : out STD_LOGIC;
    I037_out : out STD_LOGIC;
    I033_out : out STD_LOGIC;
    I029_out : out STD_LOGIC;
    I025_out : out STD_LOGIC;
    I021_out : out STD_LOGIC;
    I017_out : out STD_LOGIC;
    I013_out : out STD_LOGIC;
    I09_out : out STD_LOGIC;
    I05_out : out STD_LOGIC;
    I0_1 : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    sel_input_i_0 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    of_predecode : in STD_LOGIC_VECTOR ( 0 to 10 );
    \in\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    \Using_FPGA.Native_4\ : in STD_LOGIC;
    \Using_FPGA.Native_5\ : in STD_LOGIC;
    \Using_FPGA.Native_6\ : in STD_LOGIC_VECTOR ( 16 downto 0 );
    \Using_FPGA.Native_7\ : in STD_LOGIC;
    \Using_FPGA.Native_8\ : in STD_LOGIC;
    \Using_FPGA.Native_9\ : in STD_LOGIC;
    \Using_FPGA.Native_10\ : in STD_LOGIC;
    \Using_FPGA.Native_11\ : in STD_LOGIC;
    \Using_FPGA.Native_12\ : in STD_LOGIC;
    \Using_FPGA.Native_13\ : in STD_LOGIC;
    \Using_FPGA.Native_14\ : in STD_LOGIC;
    \Using_FPGA.Native_15\ : in STD_LOGIC;
    \Using_FPGA.Native_16\ : in STD_LOGIC;
    \Using_FPGA.Native_17\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_FDS : entity is "MB_FDS";
end design_1_microblaze_0_0_MB_FDS;

architecture STRUCTURE of design_1_microblaze_0_0_MB_FDS is
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "FDS";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Using_FPGA.Native\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sel_input_i_0,
      Q => \^using_fpga.native_0\,
      S => sync_reset
    );
\Using_FPGA.Native_i_1__104\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F870707070707070"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(0),
      I3 => \in\(31),
      I4 => \in\(30),
      I5 => \in\(28),
      O => I041_out
    );
\Using_FPGA.Native_i_1__105\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_2\,
      I3 => \in\(10),
      O => I045_out
    );
\Using_FPGA.Native_i_1__106\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_3\,
      I3 => \in\(11),
      O => I049_out
    );
\Using_FPGA.Native_i_1__107\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_4\,
      I3 => \in\(12),
      O => I053_out
    );
\Using_FPGA.Native_i_1__108\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_5\,
      I3 => \in\(13),
      O => I057_out
    );
\Using_FPGA.Native_i_1__109\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(0),
      I3 => \in\(14),
      O => I061_out
    );
\Using_FPGA.Native_i_1__110\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(1),
      I3 => \in\(15),
      O => I065_out
    );
\Using_FPGA.Native_i_1__111\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(2),
      I3 => \in\(16),
      O => I069_out
    );
\Using_FPGA.Native_i_1__112\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(3),
      I3 => \in\(17),
      O => I073_out
    );
\Using_FPGA.Native_i_1__113\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(4),
      I3 => \in\(18),
      O => I077_out
    );
\Using_FPGA.Native_i_1__114\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(5),
      I3 => \in\(19),
      O => I081_out
    );
\Using_FPGA.Native_i_1__115\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(6),
      I3 => \in\(20),
      O => I085_out
    );
\Using_FPGA.Native_i_1__116\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_7\,
      I3 => \in\(21),
      O => I0129_out
    );
\Using_FPGA.Native_i_1__117\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_8\,
      I3 => \in\(22),
      O => I0133_out
    );
\Using_FPGA.Native_i_1__118\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_9\,
      I3 => \in\(23),
      O => I0137_out
    );
\Using_FPGA.Native_i_1__119\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_10\,
      I3 => \in\(24),
      O => I0141_out
    );
\Using_FPGA.Native_i_1__120\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_11\,
      I3 => \in\(25),
      O => I0145_out
    );
\Using_FPGA.Native_i_1__121\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_12\,
      I3 => \in\(26),
      O => I0149_out
    );
\Using_FPGA.Native_i_1__122\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_13\,
      I3 => \in\(27),
      O => I0153_out
    );
\Using_FPGA.Native_i_1__123\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_14\,
      I3 => \in\(28),
      O => I0157_out
    );
\Using_FPGA.Native_i_1__124\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_15\,
      I3 => \in\(29),
      O => I0161_out
    );
\Using_FPGA.Native_i_1__125\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_16\,
      I3 => \in\(30),
      O => I0165_out
    );
\Using_FPGA.Native_i_1__126\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_17\,
      I3 => \in\(31),
      O => I0169_out
    );
\Using_FPGA.Native_i_1__159\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(16),
      I3 => \in\(9),
      O => I0125_out
    );
\Using_FPGA.Native_i_1__160\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(15),
      I3 => \in\(8),
      O => I0121_out
    );
\Using_FPGA.Native_i_1__161\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(14),
      I3 => \in\(7),
      O => I0117_out
    );
\Using_FPGA.Native_i_1__162\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(13),
      I3 => \in\(6),
      O => I0113_out
    );
\Using_FPGA.Native_i_1__163\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(12),
      I3 => \in\(5),
      O => I0109_out
    );
\Using_FPGA.Native_i_1__164\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(11),
      I3 => \in\(4),
      O => I0105_out
    );
\Using_FPGA.Native_i_1__165\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(10),
      I3 => \in\(3),
      O => I0101_out
    );
\Using_FPGA.Native_i_1__166\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(9),
      I3 => \in\(2),
      O => I097_out
    );
\Using_FPGA.Native_i_1__167\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(8),
      I3 => \in\(1),
      O => I093_out
    );
\Using_FPGA.Native_i_1__168\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_6\(7),
      I3 => \in\(0),
      O => I089_out
    );
\Using_FPGA.Native_i_1__169\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(1),
      I3 => \in\(9),
      O => I037_out
    );
\Using_FPGA.Native_i_1__170\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(2),
      I3 => \in\(8),
      O => I033_out
    );
\Using_FPGA.Native_i_1__171\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(3),
      I3 => \in\(7),
      O => I029_out
    );
\Using_FPGA.Native_i_1__172\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(4),
      I3 => \in\(6),
      O => I025_out
    );
\Using_FPGA.Native_i_1__173\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(5),
      I3 => \in\(5),
      O => I021_out
    );
\Using_FPGA.Native_i_1__174\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(6),
      I3 => \in\(4),
      O => I017_out
    );
\Using_FPGA.Native_i_1__175\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(7),
      I3 => \in\(3),
      O => I013_out
    );
\Using_FPGA.Native_i_1__176\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(8),
      I3 => \in\(2),
      O => I09_out
    );
\Using_FPGA.Native_i_1__177\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(9),
      I3 => \in\(1),
      O => I05_out
    );
\Using_FPGA.Native_i_1__178\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F870"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => of_predecode(10),
      I3 => \in\(0),
      O => I0_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT4 is
  port (
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    I2 : in STD_LOGIC;
    alu_AddSub_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT4 : entity is "MB_LUT4";
end design_1_microblaze_0_0_MB_LUT4;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT4 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FA0A"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[0]\(0),
      I2 => I2,
      I3 => alu_AddSub_1,
      O => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6 is
  port (
    sel_input_iii_3 : out STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    addr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    I5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6 : entity is "MB_LUT6";
end design_1_microblaze_0_0_MB_LUT6;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCF0AACC"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => addr(0),
      I2 => '0',
      I3 => \Using_FPGA.Native_0\,
      I4 => \Using_FPGA.Native_1\,
      I5 => I5,
      O => sel_input_iii_3
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_114 is
  port (
    sel_input_iii_2 : out STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 1 downto 0 );
    addr : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    I5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_114 : entity is "MB_LUT6";
end design_1_microblaze_0_0_MB_LUT6_114;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_114 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCF0AACC"
    )
        port map (
      I0 => if_sel_input(0),
      I1 => if_sel_input(1),
      I2 => addr(0),
      I3 => \Using_FPGA.Native_0\,
      I4 => \Using_FPGA.Native_1\,
      I5 => I5,
      O => sel_input_iii_2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_116 is
  port (
    sel_input_iii_1 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    I5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_116 : entity is "MB_LUT6";
end design_1_microblaze_0_0_MB_LUT6_116;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_116 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCF0AACC"
    )
        port map (
      I0 => \Using_FPGA.Native_0\,
      I1 => if_sel_input(0),
      I2 => if_sel_input(1),
      I3 => \Using_FPGA.Native_1\,
      I4 => \Using_FPGA.Native_2\,
      I5 => I5,
      O => sel_input_iii_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_118 is
  port (
    sel_input_iii_0 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    I5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_118 : entity is "MB_LUT6";
end design_1_microblaze_0_0_MB_LUT6_118;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_118 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000CCF0AACC"
    )
        port map (
      I0 => \Using_FPGA.Native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => if_sel_input(0),
      I3 => \Using_FPGA.Native_2\,
      I4 => \Using_FPGA.Native_3\,
      I5 => I5,
      O => sel_input_iii_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[9]\(1),
      I2 => \MEM_DataBus_Addr_reg[9]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[9]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_520 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[8]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_520 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_520;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_520 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[8]\(1),
      I2 => \MEM_DataBus_Addr_reg[8]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[8]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_522 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[7]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_522 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_522;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_522 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[7]\(1),
      I2 => \MEM_DataBus_Addr_reg[7]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[7]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_524 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[6]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_524 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_524;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_524 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[6]\(1),
      I2 => \MEM_DataBus_Addr_reg[6]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[6]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_526 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_526 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_526;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_526 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[5]\(1),
      I2 => \MEM_DataBus_Addr_reg[5]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[5]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_528 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_528 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_528;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_528 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[4]\(1),
      I2 => \MEM_DataBus_Addr_reg[4]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[4]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_530 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_530 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_530;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_530 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[3]\(1),
      I2 => \MEM_DataBus_Addr_reg[3]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[3]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_532 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_I2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_532 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_532;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_532 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \Using_FPGA.Native_I2\(1),
      I2 => \Using_FPGA.Native_I2_0\(0),
      I3 => \Using_FPGA.Native_I2\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_534 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_I2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_534 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_534;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_534 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \Using_FPGA.Native_I2\(1),
      I2 => \Using_FPGA.Native_I2_0\(0),
      I3 => \Using_FPGA.Native_I2\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_536 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_536 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_536;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_536 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[2]\(1),
      I2 => \MEM_DataBus_Addr_reg[2]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[2]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_538 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[29]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_538 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_538;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_538 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[29]\(1),
      I2 => \MEM_DataBus_Addr_reg[29]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[29]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_540 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[28]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[28]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_540 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_540;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_540 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[28]\(1),
      I2 => \MEM_DataBus_Addr_reg[28]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[28]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_542 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[27]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_542 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_542;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_542 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[27]\(1),
      I2 => \MEM_DataBus_Addr_reg[27]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[27]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_544 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[26]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[26]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_544 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_544;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_544 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[26]\(1),
      I2 => \MEM_DataBus_Addr_reg[26]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[26]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_546 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[25]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_546 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_546;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_546 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[25]\(1),
      I2 => \MEM_DataBus_Addr_reg[25]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[25]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_548 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[24]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[24]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_548 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_548;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_548 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[24]\(1),
      I2 => \MEM_DataBus_Addr_reg[24]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[24]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_550 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[23]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_550 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_550;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_550 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[23]\(1),
      I2 => \MEM_DataBus_Addr_reg[23]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[23]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_552 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[22]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[22]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_552 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_552;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_552 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[22]\(1),
      I2 => \MEM_DataBus_Addr_reg[22]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[22]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_554 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[21]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_554 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_554;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_554 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[21]\(1),
      I2 => \MEM_DataBus_Addr_reg[21]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[21]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_556 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[20]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[20]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_556 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_556;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_556 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[20]\(1),
      I2 => \MEM_DataBus_Addr_reg[20]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[20]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_558 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_558 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_558;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_558 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[1]\(1),
      I2 => \MEM_DataBus_Addr_reg[1]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[1]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_560 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[19]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_560 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_560;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_560 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[19]\(1),
      I2 => \MEM_DataBus_Addr_reg[19]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[19]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_562 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[18]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[18]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_562 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_562;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_562 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[18]\(1),
      I2 => \MEM_DataBus_Addr_reg[18]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[18]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_564 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[17]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_564 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_564;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_564 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[17]\(1),
      I2 => \MEM_DataBus_Addr_reg[17]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[17]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_566 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[16]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[16]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_566 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_566;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_566 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[16]\(1),
      I2 => \MEM_DataBus_Addr_reg[16]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[16]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_568 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[15]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_568 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_568;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_568 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[15]\(1),
      I2 => \MEM_DataBus_Addr_reg[15]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[15]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_570 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[14]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[14]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_570 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_570;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_570 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[14]\(1),
      I2 => \MEM_DataBus_Addr_reg[14]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[14]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_572 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[13]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_572 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_572;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_572 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[13]\(1),
      I2 => \MEM_DataBus_Addr_reg[13]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[13]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_574 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[12]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[12]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_574 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_574;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_574 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[12]\(1),
      I2 => \MEM_DataBus_Addr_reg[12]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[12]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_576 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_576 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_576;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_576 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[11]\(1),
      I2 => \MEM_DataBus_Addr_reg[11]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[11]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_LUT6_2_578 is
  port (
    DI : out STD_LOGIC;
    S : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[10]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[10]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_LUT6_2_578 : entity is "MB_LUT6_2";
end design_1_microblaze_0_0_MB_LUT6_2_578;

architecture STRUCTURE of design_1_microblaze_0_0_MB_LUT6_2_578 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \MEM_DataBus_Addr_reg[10]\(1),
      I2 => \MEM_DataBus_Addr_reg[10]_0\(0),
      I3 => \MEM_DataBus_Addr_reg[10]\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O5 => DI,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized1\ is
  port (
    muxcy_di : out STD_LOGIC;
    muxcy_sel : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized1\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized1\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized1\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"00FF00FFFEFEFEFE"
    )
        port map (
      I0 => '0',
      I1 => '0',
      I2 => '0',
      I3 => '0',
      I4 => '0',
      I5 => '1',
      O5 => muxcy_di,
      O6 => muxcy_sel
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    I139_out : out STD_LOGIC;
    \in\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3\ is
  signal \^y\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  Y(1 downto 0) <= \^y\(1 downto 0);
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => \^y\(1),
      O6 => \^y\(0)
    );
\Using_FPGA.Native_i_2__58\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E2222222"
    )
        port map (
      I0 => \Using_FPGA.Native_0\(0),
      I1 => \Using_FPGA.Native_1\(0),
      I2 => \^y\(1),
      I3 => \Using_FPGA.Native_2\(1),
      I4 => \Using_FPGA.Native_2\(0),
      O => I139_out
    );
\ibuffer_reg[3][32]_srl4_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^y\(1),
      I1 => \Using_FPGA.Native_2\(1),
      I2 => \Using_FPGA.Native_2\(0),
      O => \in\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_10\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_10\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_10\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_10\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_11\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_11\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_11\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_11\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_12\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_12\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_12\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_12\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_13\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_13\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_13\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_13\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_14\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_14\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_14\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_14\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_15\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_15\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_15\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_15\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_16\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_16\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_16\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_16\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_2\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_2\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_2\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_2\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_3\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_3\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_3\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_3\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_4\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_4\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_4\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_4\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_5\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_5\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_5\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_5\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_6\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_6\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_6\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_6\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_7\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_7\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_7\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_7\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_8\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_8\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_8\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_8\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_9\ is
  port (
    Y : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Instr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_9\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_9\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized3_9\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"FF00F0F0CCCCAAAA"
    )
        port map (
      I0 => Instr(1),
      I1 => LOCKSTEP_Master_Out(1),
      I2 => Instr(0),
      I3 => LOCKSTEP_Master_Out(0),
      I4 => LOCKSTEP_Master_Out(2),
      I5 => '1',
      O5 => Y(1),
      O6 => Y(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    addr_AddSub_31 : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\(0),
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => addr_AddSub_31
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_309\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_309\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_309\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_309\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_312\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_312\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_312\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_312\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_315\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_315\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_315\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_315\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_318\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_318\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_318\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_318\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_321\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_321\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_321\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_321\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_324\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_324\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_324\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_324\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_327\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_327\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_327\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_327\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_330\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_330\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_330\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_330\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_333\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_333\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_333\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_333\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_336\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_336\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_336\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_336\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_339\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_339\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_339\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_339\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_342\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_342\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_342\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_342\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_345\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_345\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_345\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_345\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_348\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_348\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_348\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_348\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_351\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_351\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_351\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_351\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_2\(0),
      I4 => \Using_FPGA.Native_3\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_354\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_354\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_354\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_354\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_357\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_357\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_357\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_357\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_360\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_360\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_360\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_360\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_363\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_363\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_363\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_363\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_366\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_366\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_366\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_366\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_369\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    I1_1 : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_369\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_369\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_369\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => I1_1,
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_372\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_372\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_372\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_372\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_375\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_375\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_375\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_375\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_378\ is
  port (
    O5 : out STD_LOGIC;
    S : out STD_LOGIC;
    DI : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_378\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_378\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_378\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => DI,
      I1 => '0',
      I2 => \Using_FPGA.Native_0\(0),
      I3 => \Using_FPGA.Native_1\(0),
      I4 => \Using_FPGA.Native_2\,
      I5 => '1',
      O5 => O5,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_381\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_381\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_381\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_381\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_384\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_384\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_384\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_384\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_387\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_387\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_387\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_387\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_390\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_390\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_390\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_390\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_393\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_393\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_393\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_393\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_396\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_396\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_396\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_396\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_399\ is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_399\ : entity is "MB_LUT6_2";
end \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_399\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6_2__parameterized5_399\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6_2
    generic map(
      INIT => X"96969696FF00AAAA"
    )
        port map (
      I0 => \Using_FPGA.Native_1\,
      I1 => '0',
      I2 => \Using_FPGA.Native_2\(0),
      I3 => \Using_FPGA.Native_3\(0),
      I4 => \Using_FPGA.Native_4\,
      I5 => '1',
      O5 => \Using_FPGA.Native_0\,
      O6 => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized10\ is
  port (
    A : out STD_LOGIC;
    I0 : in STD_LOGIC;
    of_predecode : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_i_1__58_0\ : in STD_LOGIC;
    \Using_FPGA.Native_i_1__58_1\ : in STD_LOGIC;
    ex_is_multi_or_load_instr : in STD_LOGIC;
    O : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized10\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized10\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized10\ is
  signal of_read_ex_write_op1_conflict_part2 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => I0,
      I1 => of_predecode(1),
      I2 => D(0),
      I3 => of_predecode(0),
      I4 => \Using_FPGA.Native_i_1__58_0\,
      I5 => \Using_FPGA.Native_i_1__58_1\,
      O => of_read_ex_write_op1_conflict_part2
    );
\Using_FPGA.Native_i_1__58\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => of_read_ex_write_op1_conflict_part2,
      I1 => ex_is_multi_or_load_instr,
      I2 => O,
      O => A
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized10_77\ is
  port (
    ex_is_multi_or_load_instr_reg : out STD_LOGIC;
    I0 : in STD_LOGIC;
    of_predecode : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_i_1__9_0\ : in STD_LOGIC;
    \Using_FPGA.Native_i_1__9_1\ : in STD_LOGIC;
    of_use_op2_s : in STD_LOGIC;
    ex_is_multi_or_load_instr : in STD_LOGIC;
    of_read_ex_write_op2_conflict_part1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized10_77\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized10_77\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized10_77\ is
  signal of_read_ex_write_op2_conflict_part2 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => I0,
      I1 => of_predecode(1),
      I2 => D(0),
      I3 => of_predecode(0),
      I4 => \Using_FPGA.Native_i_1__9_0\,
      I5 => \Using_FPGA.Native_i_1__9_1\,
      O => of_read_ex_write_op2_conflict_part2
    );
\Using_FPGA.Native_i_1__9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => of_read_ex_write_op2_conflict_part2,
      I1 => of_use_op2_s,
      I2 => ex_is_multi_or_load_instr,
      I3 => of_read_ex_write_op2_conflict_part1,
      O => ex_is_multi_or_load_instr_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized10_79\ is
  port (
    ex_is_multi_or_load_instr_reg : out STD_LOGIC;
    I0 : in STD_LOGIC;
    \Using_FPGA.Native_i_1__56_0\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_i_1__56_1\ : in STD_LOGIC;
    \Using_FPGA.Native_i_1__56_2\ : in STD_LOGIC;
    \Using_FPGA.Native_i_1__56_3\ : in STD_LOGIC;
    of_read_ex_write_op3_conflict_part1 : in STD_LOGIC;
    ex_is_multi_or_load_instr : in STD_LOGIC;
    of_predecode : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized10_79\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized10_79\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized10_79\ is
  signal of_read_ex_write_op3_conflict_part2 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => I0,
      I1 => \Using_FPGA.Native_i_1__56_0\,
      I2 => D(0),
      I3 => \Using_FPGA.Native_i_1__56_1\,
      I4 => \Using_FPGA.Native_i_1__56_2\,
      I5 => \Using_FPGA.Native_i_1__56_3\,
      O => of_read_ex_write_op3_conflict_part2
    );
\Using_FPGA.Native_i_1__56\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => of_read_ex_write_op3_conflict_part2,
      I1 => of_read_ex_write_op3_conflict_part1,
      I2 => ex_is_multi_or_load_instr,
      I3 => of_predecode(0),
      O => ex_is_multi_or_load_instr_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized10_81\ is
  port (
    of_read_mem_write_op1_conflict_part2 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_predecode : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_gpr_write : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized10_81\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized10_81\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized10_81\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => Q(1),
      I1 => of_predecode(1),
      I2 => Q(0),
      I3 => of_predecode(0),
      I4 => mem_gpr_write,
      I5 => mem_valid_instr,
      O => of_read_mem_write_op1_conflict_part2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized10_83\ is
  port (
    mem_is_multi_or_load_instr_reg : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_predecode : in STD_LOGIC_VECTOR ( 1 downto 0 );
    mem_gpr_write : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    of_use_op2_s : in STD_LOGIC;
    mem_is_multi_or_load_instr : in STD_LOGIC;
    of_read_mem_write_op2_conflict_part1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized10_83\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized10_83\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized10_83\ is
  signal of_read_mem_write_op2_conflict_part2 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => Q(1),
      I1 => of_predecode(1),
      I2 => Q(0),
      I3 => of_predecode(0),
      I4 => mem_gpr_write,
      I5 => mem_valid_instr,
      O => of_read_mem_write_op2_conflict_part2
    );
\Using_FPGA.Native_i_1__10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => of_read_mem_write_op2_conflict_part2,
      I1 => of_use_op2_s,
      I2 => mem_is_multi_or_load_instr,
      I3 => of_read_mem_write_op2_conflict_part1,
      O => mem_is_multi_or_load_instr_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized10_85\ is
  port (
    mem_is_multi_or_load_instr_reg : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_i_1__55_0\ : in STD_LOGIC;
    \Using_FPGA.Native_i_1__55_1\ : in STD_LOGIC;
    mem_gpr_write : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    of_read_mem_write_op3_conflict_part1 : in STD_LOGIC;
    mem_is_multi_or_load_instr : in STD_LOGIC;
    of_predecode : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized10_85\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized10_85\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized10_85\ is
  signal of_read_mem_write_op3_conflict_part2 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000000000"
    )
        port map (
      I0 => Q(1),
      I1 => \Using_FPGA.Native_i_1__55_0\,
      I2 => Q(0),
      I3 => \Using_FPGA.Native_i_1__55_1\,
      I4 => mem_gpr_write,
      I5 => mem_valid_instr,
      O => of_read_mem_write_op3_conflict_part2
    );
\Using_FPGA.Native_i_1__55\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => of_read_mem_write_op3_conflict_part2,
      I1 => of_read_mem_write_op3_conflict_part1,
      I2 => mem_is_multi_or_load_instr,
      I3 => of_predecode(0),
      O => mem_is_multi_or_load_instr_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized12\ is
  port (
    alu_AddSub_1 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized12\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized12\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized12\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"607AA67800008888"
    )
        port map (
      I0 => Q(0),
      I1 => \Using_FPGA.Native_0\(1),
      I2 => \Using_FPGA.Native_1\(0),
      I3 => \Using_FPGA.Native_0\(0),
      I4 => EX_ALU_Sel_Logic,
      I5 => EX_Enable_ALU,
      O => alu_AddSub_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized2\ is
  port (
    sel_input_delayslot : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    I5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized2\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized2\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized2\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000FFFFCCF0AACC"
    )
        port map (
      I0 => \Using_FPGA.Native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => if_sel_input(0),
      I3 => \Using_FPGA.Native_2\,
      I4 => \Using_FPGA.Native_3\,
      I5 => I5,
      O => sel_input_delayslot
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized4\ is
  port (
    sel_input_i_0 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    I4_0 : in STD_LOGIC;
    I5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized4\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized4\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized4\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FFFFAE0AAE0A"
    )
        port map (
      I0 => \Using_FPGA.Native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_2\,
      I3 => \Using_FPGA.Native_3\,
      I4 => I4_0,
      I5 => I5,
      O => sel_input_i_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized6\ is
  port (
    of_Valid_II : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    I4_0 : in STD_LOGIC;
    I5 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized6\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized6\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized6\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00FF000051F551F5"
    )
        port map (
      I0 => \Using_FPGA.Native_0\,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_2\,
      I3 => \Using_FPGA.Native_3\,
      I4 => I4_0,
      I5 => I5,
      O => of_Valid_II
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized8\ is
  port (
    O : out STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    of_predecode : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized8\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized8\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized8\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => D(2),
      I1 => of_predecode(2),
      I2 => D(1),
      I3 => of_predecode(1),
      I4 => D(0),
      I5 => of_predecode(0),
      O => O
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized8_76\ is
  port (
    of_read_ex_write_op2_conflict_part1 : out STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    of_predecode : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized8_76\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized8_76\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized8_76\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => D(2),
      I1 => of_predecode(2),
      I2 => D(1),
      I3 => of_predecode(1),
      I4 => D(0),
      I5 => of_predecode(0),
      O => of_read_ex_write_op2_conflict_part1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized8_78\ is
  port (
    of_read_ex_write_op3_conflict_part1 : out STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \Using_FPGA.Native_i_1__56\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_i_1__56_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized8_78\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized8_78\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized8_78\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => D(2),
      I1 => \Using_FPGA.Native_i_1__56\(1),
      I2 => D(1),
      I3 => \Using_FPGA.Native_i_1__56\(0),
      I4 => D(0),
      I5 => \Using_FPGA.Native_i_1__56_0\,
      O => of_read_ex_write_op3_conflict_part1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized8_80\ is
  port (
    mem_is_multi_or_load_instr_reg : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    of_predecode : in STD_LOGIC_VECTOR ( 2 downto 0 );
    mem_is_multi_or_load_instr : in STD_LOGIC;
    of_read_mem_write_op1_conflict_part2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized8_80\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized8_80\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized8_80\ is
  signal of_read_mem_write_op1_conflict_part1 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => Q(2),
      I1 => of_predecode(2),
      I2 => Q(1),
      I3 => of_predecode(1),
      I4 => Q(0),
      I5 => of_predecode(0),
      O => of_read_mem_write_op1_conflict_part1
    );
\Using_FPGA.Native_i_1__57\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => of_read_mem_write_op1_conflict_part1,
      I1 => mem_is_multi_or_load_instr,
      I2 => of_read_mem_write_op1_conflict_part2,
      O => mem_is_multi_or_load_instr_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized8_82\ is
  port (
    of_read_mem_write_op2_conflict_part1 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    of_predecode : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized8_82\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized8_82\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized8_82\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => Q(2),
      I1 => of_predecode(2),
      I2 => Q(1),
      I3 => of_predecode(1),
      I4 => Q(0),
      I5 => of_predecode(0),
      O => of_read_mem_write_op2_conflict_part1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_LUT6__parameterized8_84\ is
  port (
    of_read_mem_write_op3_conflict_part1 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_i_1__55\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_LUT6__parameterized8_84\ : entity is "MB_LUT6";
end \design_1_microblaze_0_0_MB_LUT6__parameterized8_84\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_LUT6__parameterized8_84\ is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => Q(2),
      I1 => D(1),
      I2 => Q(1),
      I3 => D(0),
      I4 => Q(0),
      I5 => \Using_FPGA.Native_i_1__55\,
      O => of_read_mem_write_op3_conflict_part1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MULT_AND is
  port (
    DI : out STD_LOGIC;
    I0 : in STD_LOGIC;
    \Using_FPGA.Native_I1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MULT_AND : entity is "MB_MULT_AND";
end design_1_microblaze_0_0_MB_MULT_AND;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MULT_AND is
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native\ : label is "MULT_AND";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => I0,
      I1 => \Using_FPGA.Native_I1\(0),
      O => DI
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY is
  port (
    carry_7 : out STD_LOGIC;
    SRL16_Sel_7 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal lopt_21 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_14\ <= lopt_13;
  \^lopt_15\ <= lopt_14;
  \^lopt_16\ <= lopt_15;
  \^lopt_17\ <= lopt_16;
  \^lopt_18\ <= lopt_17;
  \^lopt_19\ <= lopt_18;
  \^lopt_2\ <= lopt_1;
  \^lopt_20\ <= lopt_19;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_21 <= lopt_20;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => Q(0),
      CI_TOP => '0',
      CO(7) => \^lopt_10\,
      CO(6) => \^lopt_11\,
      CO(5) => \^lopt_12\,
      CO(4) => \^lopt_13\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => carry_7,
      DI(7) => \^lopt_14\,
      DI(6) => \^lopt_15\,
      DI(5) => \^lopt_16\,
      DI(4) => \^lopt_17\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 0),
      S(7) => \^lopt_18\,
      S(6) => \^lopt_19\,
      S(5) => \^lopt_20\,
      S(4) => lopt_21,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => SRL16_Sel_7
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_100 is
  port (
    if_pc_incr_carry1 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    if_pc_incr_carry0 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_100 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_100;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_100 is
  signal \<const0>\ : STD_LOGIC;
  signal \^if_pc_incr_carry1\ : STD_LOGIC;
begin
  \^if_pc_incr_carry1\ <= lopt;
  if_pc_incr_carry1 <= \^if_pc_incr_carry1\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_101 is
  port (
    of_PipeRun_carry_2 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    of_PipeRun_carry_3 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_101 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_101;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_101 is
  signal \<const0>\ : STD_LOGIC;
  signal \^of_piperun_carry_2\ : STD_LOGIC;
begin
  \^of_piperun_carry_2\ <= lopt;
  lopt_1 <= \<const0>\;
  of_PipeRun_carry_2 <= \^of_piperun_carry_2\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_102 is
  port (
    of_PipeRun_carry_3 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    of_PipeRun_carry_4 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_102 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_102;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_102 is
  signal \<const0>\ : STD_LOGIC;
  signal \^of_piperun_carry_3\ : STD_LOGIC;
begin
  \^of_piperun_carry_3\ <= lopt;
  lopt_1 <= \<const0>\;
  of_PipeRun_carry_3 <= \^of_piperun_carry_3\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_103 is
  port (
    of_PipeRun_carry_4 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    of_PipeRun_carry_5 : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_103 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_103;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_103 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal lopt_12 : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_11\ <= lopt_10;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_12 <= lopt_11;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => of_PipeRun_carry_5,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \^lopt_10\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => of_PipeRun_carry_4,
      DI(7 downto 5) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED\(7 downto 5),
      DI(4) => \^lopt_11\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 0),
      S(7 downto 5) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED\(7 downto 5),
      S(4) => lopt_12,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_104 is
  port (
    of_PipeRun_carry_5 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    of_PipeRun_carry_6 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_104 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_104;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_104 is
  signal \<const0>\ : STD_LOGIC;
  signal \^of_piperun_carry_5\ : STD_LOGIC;
begin
  \^of_piperun_carry_5\ <= lopt;
  lopt_1 <= \<const0>\;
  of_PipeRun_carry_5 <= \^of_piperun_carry_5\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_105 is
  port (
    of_PipeRun_carry_6 : out STD_LOGIC;
    A : in STD_LOGIC;
    of_PipeRun_carry_7 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_105 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_105;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_105 is
  signal \<const0>\ : STD_LOGIC;
  signal \^of_piperun_carry_6\ : STD_LOGIC;
begin
  \^of_piperun_carry_6\ <= lopt;
  lopt_1 <= \<const0>\;
  of_PipeRun_carry_6 <= \^of_piperun_carry_6\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_106 is
  port (
    of_PipeRun_carry_7 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_106 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_106;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_106 is
  signal \<const0>\ : STD_LOGIC;
  signal \^of_piperun_carry_7\ : STD_LOGIC;
begin
  \^of_piperun_carry_7\ <= lopt;
  lopt_1 <= \<const0>\;
  of_PipeRun_carry_7 <= \^of_piperun_carry_7\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_107 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \wb_exception_kind_i_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : out STD_LOGIC;
    ex_Write_ICache_i_reg : out STD_LOGIC;
    of_PipeRun_carry_9 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wb_exception : in STD_LOGIC;
    \mem_pc_i_reg[0]\ : in STD_LOGIC;
    ex_Write_DCache_decode_reg : in STD_LOGIC;
    ex_write_dcache_instr : in STD_LOGIC;
    ex_Write_ICache_i : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : in STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_107 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_107;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_107 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of ex_Write_DCache_decode_cmb_inferred_i_1 : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of ex_Write_ICache_i_cmb_inferred_i_1 : label is "soft_lutpair24";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  \^lopt_1\ <= lopt_11;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_10;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_9;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \^using_fpga.native_0\ <= lopt_12;
  lopt <= \^lopt_1\;
  lopt_13 <= \<const0>\;
  lopt_14 <= \<const1>\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
ex_Write_DCache_decode_cmb_inferred_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_Write_DCache_decode_reg,
      I2 => ex_write_dcache_instr,
      O => in0
    );
ex_Write_ICache_i_cmb_inferred_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^using_fpga.native_0\,
      I1 => ex_Write_DCache_decode_reg,
      I2 => ex_Write_ICache_i,
      O => ex_Write_ICache_i_reg
    );
\mem_pc_i[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"007F0000"
    )
        port map (
      I0 => Q(1),
      I1 => Q(0),
      I2 => wb_exception,
      I3 => \mem_pc_i_reg[0]\,
      I4 => \^using_fpga.native_0\,
      O => \wb_exception_kind_i_reg[28]\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_108 is
  port (
    of_PipeRun_carry_9 : out STD_LOGIC;
    \EX_MBAR_Stall__1\ : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    of_PipeRun_carry_10 : in STD_LOGIC;
    ex_mbar_sleep : in STD_LOGIC;
    ex_mbar_decode : in STD_LOGIC;
    ex_first_cycle : in STD_LOGIC;
    ex_mbar_stall_no_sleep_1 : in STD_LOGIC;
    ex_jump_hold : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_108 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_108;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_108 is
  signal \<const0>\ : STD_LOGIC;
  signal \^of_piperun_carry_9\ : STD_LOGIC;
begin
  \^of_piperun_carry_9\ <= lopt;
  lopt_1 <= \<const0>\;
  of_PipeRun_carry_9 <= \^of_piperun_carry_9\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\Using_FPGA.Native_i_2__81\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAEEEA"
    )
        port map (
      I0 => ex_mbar_sleep,
      I1 => ex_mbar_decode,
      I2 => ex_first_cycle,
      I3 => ex_mbar_stall_no_sleep_1,
      I4 => ex_jump_hold,
      O => \EX_MBAR_Stall__1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_109 is
  port (
    of_PipeRun_carry_10 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_109 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_109;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_109 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^of_piperun_carry_10\ : STD_LOGIC;
begin
  \^of_piperun_carry_10\ <= lopt;
  lopt_1 <= \<const0>\;
  lopt_2 <= \<const1>\;
  of_PipeRun_carry_10 <= \^of_piperun_carry_10\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_110 is
  port (
    of_pause_reg : out STD_LOGIC;
    ex_jump_nodelay_reg : out STD_LOGIC;
    of_read_imm_reg_ii_reg : out STD_LOGIC;
    wb_exception_i_reg : out STD_LOGIC;
    wb_exception_i_reg_0 : out STD_LOGIC;
    of_PipeRun_carry_1 : in STD_LOGIC;
    ex_jump_nodelay : in STD_LOGIC;
    ex_jump : in STD_LOGIC;
    ex_jump_nodelay_reg_0 : in STD_LOGIC;
    IB_Ready : in STD_LOGIC;
    if_missed_fetch : in STD_LOGIC;
    of_read_imm_reg_ii : in STD_LOGIC;
    p_9_in : in STD_LOGIC;
    of_read_imm_reg_ii_reg_0 : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    of_pause : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_110 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_110;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_110 is
  signal \<const0>\ : STD_LOGIC;
  signal \Using_FPGA.Native_i_1__46_n_0\ : STD_LOGIC;
  signal \^of_pause_reg\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of ex_first_cycle_i_1 : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of ex_valid_i_1 : label is "soft_lutpair23";
begin
  \^of_pause_reg\ <= lopt;
  lopt_1 <= \<const0>\;
  lopt_2 <= \Using_FPGA.Native_i_1__46_n_0\;
  of_pause_reg <= \^of_pause_reg\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\Using_FPGA.Native_i_1__46\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => of_pause,
      O => \Using_FPGA.Native_i_1__46_n_0\
    );
ex_first_cycle_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^of_pause_reg\,
      I1 => wb_exception,
      I2 => sync_reset,
      O => wb_exception_i_reg_0
    );
ex_jump_nodelay_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000226E226E226E"
    )
        port map (
      I0 => ex_jump_nodelay,
      I1 => \^of_pause_reg\,
      I2 => ex_jump,
      I3 => ex_jump_nodelay_reg_0,
      I4 => IB_Ready,
      I5 => if_missed_fetch,
      O => ex_jump_nodelay_reg
    );
ex_valid_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EFEE"
    )
        port map (
      I0 => wb_exception,
      I1 => sync_reset,
      I2 => \^of_pause_reg\,
      I3 => E(0),
      O => wb_exception_i_reg
    );
of_read_imm_reg_ii_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000002EEE2222"
    )
        port map (
      I0 => of_read_imm_reg_ii,
      I1 => \^of_pause_reg\,
      I2 => ex_jump,
      I3 => ex_jump_nodelay,
      I4 => p_9_in,
      I5 => of_read_imm_reg_ii_reg_0,
      O => of_read_imm_reg_ii_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_111 is
  port (
    of_PipeRun_carry_1 : out STD_LOGIC;
    use_Reg_Neg_S_reg : in STD_LOGIC;
    of_PipeRun_carry_2 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_111 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_111;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_111 is
  signal \<const0>\ : STD_LOGIC;
  signal \^of_piperun_carry_1\ : STD_LOGIC;
begin
  \^of_piperun_carry_1\ <= lopt;
  lopt_1 <= \<const0>\;
  of_PipeRun_carry_1 <= \^of_piperun_carry_1\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_299 is
  port (
    ex_pre_alu_carry : out STD_LOGIC;
    muxcy_sel : in STD_LOGIC;
    muxcy_di : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_299 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_299;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_299 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal lopt_26 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_19\ <= lopt_18;
  \^lopt_2\ <= lopt_1;
  \^lopt_20\ <= lopt_19;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_26 <= lopt_25;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => \Using_FPGA.Native_0\,
      CI_TOP => '0',
      CO(7) => \^lopt_11\,
      CO(6) => \^lopt_12\,
      CO(5) => \^lopt_13\,
      CO(4) => \^lopt_14\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => ex_pre_alu_carry,
      DI(7) => \^lopt_19\,
      DI(6) => \^lopt_20\,
      DI(5) => \^lopt_21\,
      DI(4) => \^lopt_22\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => muxcy_di,
      O(7) => \^lopt_15\,
      O(6) => \^lopt_16\,
      O(5) => \^lopt_17\,
      O(4) => \^lopt_18\,
      O(3) => \^lopt_10\,
      O(2 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(2 downto 0),
      S(7) => \^lopt_23\,
      S(6) => \^lopt_24\,
      S(5) => \^lopt_25\,
      S(4) => lopt_26,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => muxcy_sel
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_300 is
  port (
    ex_alu_carryin : out STD_LOGIC;
    ex_pre_alu_carry : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_300 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_300;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_300 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^ex_alu_carryin\ : STD_LOGIC;
begin
  \^ex_alu_carryin\ <= lopt;
  ex_alu_carryin <= \^ex_alu_carryin\;
  lopt_1 <= \<const0>\;
  lopt_2 <= \<const1>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_307 is
  port (
    CI : out STD_LOGIC;
    \Using_FPGA.Native_I2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_307 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_307;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_307 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => CI,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(0),
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => \Using_FPGA.Native_I2\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_31 is
  port (
    carry_6 : out STD_LOGIC;
    SRL16_Sel_6 : in STD_LOGIC;
    carry_7 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_31 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_31;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_31 is
  signal \<const0>\ : STD_LOGIC;
  signal \^carry_6\ : STD_LOGIC;
begin
  \^carry_6\ <= lopt;
  carry_6 <= \^carry_6\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_33 is
  port (
    carry_5 : out STD_LOGIC;
    SRL16_Sel_5 : in STD_LOGIC;
    carry_6 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_33 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_33;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_33 is
  signal \<const0>\ : STD_LOGIC;
  signal \^carry_5\ : STD_LOGIC;
begin
  \^carry_5\ <= lopt;
  carry_5 <= \^carry_5\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_35 is
  port (
    carry_4 : out STD_LOGIC;
    SRL16_Sel_4 : in STD_LOGIC;
    carry_5 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_35 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_35;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_35 is
  signal \<const0>\ : STD_LOGIC;
  signal \^carry_4\ : STD_LOGIC;
begin
  \^carry_4\ <= lopt;
  carry_4 <= \^carry_4\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_37 is
  port (
    carry_3 : out STD_LOGIC;
    SRL16_Sel_3 : in STD_LOGIC;
    carry_4 : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : in STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_37 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_37;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_37 is
  signal \<const0>\ : STD_LOGIC;
  signal \^carry_3\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  \^carry_3\ <= lopt_12;
  \^lopt_1\ <= lopt_11;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_10;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_9;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  carry_3 <= \^carry_3\;
  lopt <= \^lopt_1\;
  lopt_13 <= \<const0>\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_39 is
  port (
    carry_2 : out STD_LOGIC;
    SRL16_Sel_2 : in STD_LOGIC;
    carry_3 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_39 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_39;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_39 is
  signal \<const0>\ : STD_LOGIC;
  signal \^carry_2\ : STD_LOGIC;
begin
  \^carry_2\ <= lopt;
  carry_2 <= \^carry_2\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_402 is
  port (
    zero_CI_6 : out STD_LOGIC;
    ex_op1_cmp_equal : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : out STD_LOGIC;
    lopt_6 : in STD_LOGIC;
    lopt_7 : out STD_LOGIC;
    lopt_8 : out STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : in STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_402 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_402;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_402 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal lopt_16 : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_12\ <= lopt_11;
  \^lopt_13\ <= lopt_12;
  \^lopt_14\ <= lopt_13;
  \^lopt_15\ <= lopt_14;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_7\ <= lopt_6;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_16 <= lopt_15;
  lopt_3 <= \^lopt_4\;
  lopt_5 <= \^lopt_6\;
  lopt_7 <= \^lopt_8\;
  lopt_8 <= \^lopt_9\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \^lopt_8\,
      CO(6) => \^lopt_9\,
      CO(5) => \^lopt_10\,
      CO(4) => \^lopt_11\,
      CO(3) => \^lopt_6\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => zero_CI_6,
      DI(7) => \^lopt_12\,
      DI(6) => \^lopt_2\,
      DI(5) => \^lopt_2\,
      DI(4) => \^lopt_2\,
      DI(3) => \^lopt_2\,
      DI(2) => \^lopt_2\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 0),
      S(7) => \^lopt_13\,
      S(6) => \^lopt_14\,
      S(5) => \^lopt_15\,
      S(4) => lopt_16,
      S(3) => \^lopt_7\,
      S(2) => \^lopt_5\,
      S(1) => \^lopt_3\,
      S(0) => ex_op1_cmp_equal
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_403 is
  port (
    ex_op1_zero : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    zero_CI_1 : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_403 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_403;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_403 is
  signal \^ex_op1_zero\ : STD_LOGIC;
begin
  \^ex_op1_zero\ <= lopt;
  ex_op1_zero <= \^ex_op1_zero\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_404 is
  port (
    zero_CI_1 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    zero_CI_2 : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_404 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_404;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_404 is
  signal \^zero_ci_1\ : STD_LOGIC;
begin
  \^zero_ci_1\ <= lopt;
  zero_CI_1 <= \^zero_ci_1\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_405 is
  port (
    zero_CI_2 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    zero_CI_3 : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC;
    lopt_4 : out STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : in STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : in STD_LOGIC;
    lopt_10 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_405 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_405;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_405 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^zero_ci_2\ : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_9;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_8;
  \^lopt_4\ <= lopt_3;
  \^lopt_5\ <= lopt_7;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_6;
  \^zero_ci_2\ <= lopt_10;
  lopt <= \^lopt_1\;
  lopt_2 <= \^lopt_3\;
  lopt_4 <= \^lopt_5\;
  zero_CI_2 <= \^zero_ci_2\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_406 is
  port (
    zero_CI_3 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    zero_CI_4 : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_406 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_406;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_406 is
  signal \^zero_ci_3\ : STD_LOGIC;
begin
  \^zero_ci_3\ <= lopt;
  zero_CI_3 <= \^zero_ci_3\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_407 is
  port (
    zero_CI_4 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    zero_CI_5 : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_407 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_407;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_407 is
  signal \^zero_ci_4\ : STD_LOGIC;
begin
  \^zero_ci_4\ <= lopt;
  zero_CI_4 <= \^zero_ci_4\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_408 is
  port (
    zero_CI_5 : out STD_LOGIC;
    S : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    zero_CI_6 : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_408 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_408;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_408 is
  signal \^zero_ci_5\ : STD_LOGIC;
begin
  \^zero_ci_5\ <= lopt;
  zero_CI_5 <= \^zero_ci_5\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_41 is
  port (
    carry_1 : out STD_LOGIC;
    SRL16_Sel_1 : in STD_LOGIC;
    carry_2 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_41 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_41;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_41 is
  signal \<const0>\ : STD_LOGIC;
  signal \^carry_1\ : STD_LOGIC;
begin
  \^carry_1\ <= lopt;
  carry_1 <= \^carry_1\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_43 is
  port (
    carry_0 : out STD_LOGIC;
    SRL16_Sel_0 : in STD_LOGIC;
    carry_1 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_43 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_43;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_43 is
  signal \<const0>\ : STD_LOGIC;
  signal \^carry_0\ : STD_LOGIC;
begin
  \^carry_0\ <= lopt;
  carry_0 <= \^carry_0\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_45 is
  port (
    Hit : out STD_LOGIC;
    single_Step_N_reg : out STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg\ : out STD_LOGIC;
    carry_0 : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0\ : in STD_LOGIC;
    force_stop_i : in STD_LOGIC;
    single_Step_N : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0\ : in STD_LOGIC;
    ex_Exception_Taken : in STD_LOGIC;
    mem_Exception_Taken : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_45 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_45;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_45 is
  signal \^hit\ : STD_LOGIC;
  signal \Performance_Debug_Control.ex_dbg_pc_hit_i_i_5_n_0\ : STD_LOGIC;
  signal p_45_out : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  Hit <= \^hit\;
\Performance_Debug_Control.ex_dbg_pc_hit_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFDF55FFFF0000"
    )
        port map (
      I0 => \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0\,
      I1 => mem_Exception_Taken,
      I2 => ex_Exception_Taken,
      I3 => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3\,
      I4 => p_45_out,
      I5 => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4\,
      O => \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg\
    );
\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEA00000000"
    )
        port map (
      I0 => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\,
      I1 => Q(0),
      I2 => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\,
      I3 => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\,
      I4 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_5_n_0\,
      I5 => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2\,
      O => p_45_out
    );
\Performance_Debug_Control.ex_dbg_pc_hit_i_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F4"
    )
        port map (
      I0 => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0\,
      I1 => \^hit\,
      I2 => force_stop_i,
      O => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_5_n_0\
    );
\Performance_Debug_Control.ex_dbg_pc_hit_single_step_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555555CCCC0CCC"
    )
        port map (
      I0 => single_Step_N,
      I1 => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3\,
      I2 => \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0\,
      I3 => ex_Exception_Taken,
      I4 => mem_Exception_Taken,
      I5 => p_45_out,
      O => single_Step_N_reg
    );
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => carry_0,
      CI_TOP => '0',
      CO(7 downto 1) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED\(7 downto 1),
      CO(0) => \^hit\,
      DI(7 downto 1) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED\(7 downto 1),
      DI(0) => '1',
      O(7 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 0),
      S(7 downto 1) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED\(7 downto 1),
      S(0) => '1'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_488 is
  port (
    CI : out STD_LOGIC;
    ex_use_carry : in STD_LOGIC;
    DI_0 : in STD_LOGIC;
    ex_alu_carryin : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_488 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_488;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_488 is
  signal \^ci\ : STD_LOGIC;
begin
  CI <= \^ci\;
  \^ci\ <= lopt;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_581 is
  port (
    CI : out STD_LOGIC;
    S : in STD_LOGIC;
    ex_unsigned_op : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_581 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_581;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_581 is
  signal \^ci\ : STD_LOGIC;
begin
  CI <= \^ci\;
  \^ci\ <= lopt;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_90 is
  port (
    mem_wait_on_ready_N : out STD_LOGIC;
    MEM_DataBus_Ready : in STD_LOGIC;
    mem_load_store_access : in STD_LOGIC;
    mem_Write_DCache : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_90 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_90;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_90 is
  signal \Using_FPGA.Native_i_1__97_n_0\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal lopt_21 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_14\ <= lopt_13;
  \^lopt_15\ <= lopt_14;
  \^lopt_16\ <= lopt_15;
  \^lopt_17\ <= lopt_16;
  \^lopt_18\ <= lopt_17;
  \^lopt_19\ <= lopt_18;
  \^lopt_2\ <= lopt_1;
  \^lopt_20\ <= lopt_19;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_21 <= lopt_20;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => MEM_DataBus_Ready,
      CI_TOP => '0',
      CO(7) => \^lopt_10\,
      CO(6) => \^lopt_11\,
      CO(5) => \^lopt_12\,
      CO(4) => \^lopt_13\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => mem_wait_on_ready_N,
      DI(7) => \^lopt_14\,
      DI(6) => \^lopt_15\,
      DI(5) => \^lopt_16\,
      DI(4) => \^lopt_17\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '1',
      O(7 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 0),
      S(7) => \^lopt_18\,
      S(6) => \^lopt_19\,
      S(5) => \^lopt_20\,
      S(4) => lopt_21,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => \Using_FPGA.Native_i_1__97_n_0\
    );
\Using_FPGA.Native_i_1__97\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E0"
    )
        port map (
      I0 => mem_load_store_access,
      I1 => mem_Write_DCache,
      I2 => mem_valid_instr,
      O => \Using_FPGA.Native_i_1__97_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_91 is
  port (
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    mem_valid_reg : out STD_LOGIC;
    wb_valid_reg : out STD_LOGIC;
    wb_gpr_write_dbg0 : out STD_LOGIC;
    wb_gpr_write_i0 : out STD_LOGIC;
    mem_wait_on_ready_N : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    mem_exception_from_ex : in STD_LOGIC;
    mem_valid_reg_0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    flush_pipe : in STD_LOGIC;
    wb_valid_reg_0 : in STD_LOGIC;
    wb_valid_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    mem_gpr_write_dbg : in STD_LOGIC;
    mem_gpr_write : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_91 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_91;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_91 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of wb_gpr_write_dbg_i_1 : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of wb_gpr_write_i_i_1 : label is "soft_lutpair45";
begin
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  \^using_fpga.native_0\ <= lopt;
  lopt_1 <= \<const0>\;
  lopt_2 <= \<const1>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
mem_valid_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000707000AA"
    )
        port map (
      I0 => mem_valid_instr,
      I1 => mem_exception_from_ex,
      I2 => mem_valid_reg_0,
      I3 => \^using_fpga.native_0\,
      I4 => E(0),
      I5 => flush_pipe,
      O => mem_valid_reg
    );
wb_gpr_write_dbg_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => sync_reset,
      I1 => wb_exception,
      I2 => \^using_fpga.native_0\,
      I3 => mem_gpr_write_dbg,
      O => wb_gpr_write_dbg0
    );
wb_gpr_write_i_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1000"
    )
        port map (
      I0 => sync_reset,
      I1 => wb_exception,
      I2 => \^using_fpga.native_0\,
      I3 => mem_gpr_write,
      O => wb_gpr_write_i0
    );
wb_valid_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000CC0A"
    )
        port map (
      I0 => wb_valid_reg_0,
      I1 => mem_valid_instr,
      I2 => wb_valid_reg_1(0),
      I3 => \^using_fpga.native_0\,
      I4 => sync_reset,
      O => wb_valid_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_92 is
  port (
    jump_carry1 : out STD_LOGIC;
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    ex_op1_zero : in STD_LOGIC;
    lopt : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_92 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_92;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_92 is
  signal \^jump_carry1\ : STD_LOGIC;
begin
  \^jump_carry1\ <= lopt;
  jump_carry1 <= \^jump_carry1\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_93 is
  port (
    jump_carry2 : out STD_LOGIC;
    jump_carry1 : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    force_Val2_N : in STD_LOGIC;
    force2 : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_93 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_93;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_93 is
  signal force_DI2 : STD_LOGIC;
  signal force_jump2 : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal lopt_12 : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 5 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_11\ <= lopt_10;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_12 <= lopt_11;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => jump_carry1,
      CI_TOP => '0',
      CO(7 downto 5) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED\(7 downto 5),
      CO(4) => \^lopt_10\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => jump_carry2,
      DI(7 downto 5) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED\(7 downto 5),
      DI(4) => \^lopt_11\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => force_DI2,
      O(7 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 0),
      S(7 downto 5) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED\(7 downto 5),
      S(4) => lopt_12,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => force_jump2
    );
\Using_FPGA.Native_i_1__1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \out\,
      I1 => force2,
      O => force_jump2
    );
\Using_FPGA.Native_i_2__20\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \out\,
      I1 => force_Val2_N,
      O => force_DI2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_94 is
  port (
    ex_jump_wanted : out STD_LOGIC;
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    jump_carry2 : in STD_LOGIC;
    of_valid : in STD_LOGIC;
    ex_branch_with_delayslot : in STD_LOGIC;
    \EX_MBAR_Stall__1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_94 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_94;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_94 is
  signal \<const0>\ : STD_LOGIC;
  signal \^ex_jump_wanted\ : STD_LOGIC;
begin
  \^ex_jump_wanted\ <= lopt;
  ex_jump_wanted <= \^ex_jump_wanted\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\Using_FPGA.Native_i_1__100\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"55DF"
    )
        port map (
      I0 => \^ex_jump_wanted\,
      I1 => of_valid,
      I2 => ex_branch_with_delayslot,
      I3 => \EX_MBAR_Stall__1\,
      O => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_95 is
  port (
    jump_carry4 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    ex_jump_wanted : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_95 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_95;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_95 is
  signal \<const0>\ : STD_LOGIC;
  signal \^jump_carry4\ : STD_LOGIC;
begin
  \^jump_carry4\ <= lopt;
  jump_carry4 <= \^jump_carry4\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_96 is
  port (
    jump_carry5 : out STD_LOGIC;
    jump_carry4 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_96 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_96;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_96 is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^jump_carry5\ : STD_LOGIC;
begin
  \^jump_carry5\ <= lopt;
  jump_carry5 <= \^jump_carry5\;
  lopt_1 <= \<const0>\;
  lopt_2 <= \<const1>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_97 is
  port (
    ex_jump_hold_reg : out STD_LOGIC;
    I5 : out STD_LOGIC;
    of_next_ex_valid : out STD_LOGIC;
    ex_jump_hold_reg_0 : out STD_LOGIC;
    ex_delayslot_Instr0 : out STD_LOGIC;
    keep_jump_taken_with_ds_reg : out STD_LOGIC;
    mem_jump_taken0 : out STD_LOGIC;
    \if_pc_reg[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ex_jump_q_reg : out STD_LOGIC;
    jump_carry5 : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_Exception_Taken : in STD_LOGIC;
    ex_jump_nodelay : in STD_LOGIC;
    of_valid : in STD_LOGIC;
    mem_exception_from_ex : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    ex_jump_hold : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    keep_jump_taken_with_ds : in STD_LOGIC;
    ex_branch_with_delayslot : in STD_LOGIC;
    keep_jump_taken_with_ds_reg_0 : in STD_LOGIC;
    ex_mbar_stall_no_sleep_1 : in STD_LOGIC;
    ex_first_cycle : in STD_LOGIC;
    ex_mbar_decode : in STD_LOGIC;
    ex_mbar_sleep : in STD_LOGIC;
    ex_databus_addr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \if_pc_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \if_pc_reg[0]_0\ : in STD_LOGIC_VECTOR ( 29 downto 0 );
    O : in STD_LOGIC;
    \if_pc_reg[28]\ : in STD_LOGIC;
    \if_pc_reg[27]\ : in STD_LOGIC;
    \if_pc_reg[26]\ : in STD_LOGIC;
    \if_pc_reg[25]\ : in STD_LOGIC;
    \if_pc_reg[24]\ : in STD_LOGIC;
    \if_pc_reg[23]\ : in STD_LOGIC;
    \if_pc_reg[22]\ : in STD_LOGIC;
    \if_pc_reg[21]\ : in STD_LOGIC;
    \if_pc_reg[20]\ : in STD_LOGIC;
    \if_pc_reg[19]\ : in STD_LOGIC;
    \if_pc_reg[18]\ : in STD_LOGIC;
    \if_pc_reg[17]\ : in STD_LOGIC;
    \if_pc_reg[16]\ : in STD_LOGIC;
    \if_pc_reg[15]\ : in STD_LOGIC;
    \if_pc_reg[14]\ : in STD_LOGIC;
    \if_pc_reg[13]\ : in STD_LOGIC;
    \if_pc_reg[12]\ : in STD_LOGIC;
    \if_pc_reg[11]\ : in STD_LOGIC;
    \if_pc_reg[10]\ : in STD_LOGIC;
    \if_pc_reg[9]\ : in STD_LOGIC;
    \if_pc_reg[8]\ : in STD_LOGIC;
    \if_pc_reg[7]\ : in STD_LOGIC;
    \if_pc_reg[6]\ : in STD_LOGIC;
    \if_pc_reg[5]\ : in STD_LOGIC;
    \if_pc_reg[4]\ : in STD_LOGIC;
    \if_pc_reg[3]\ : in STD_LOGIC;
    \if_pc_reg[2]\ : in STD_LOGIC;
    \if_pc_reg[1]\ : in STD_LOGIC;
    O56_out : in STD_LOGIC;
    ex_jump_q : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_97 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_97;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_97 is
  signal \<const0>\ : STD_LOGIC;
  signal \Using_FPGA.Native_i_1__44_n_0\ : STD_LOGIC;
  signal \^ex_jump_hold_reg\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Instr_Addr[0]_INST_0\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \Instr_Addr[10]_INST_0\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \Instr_Addr[11]_INST_0\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \Instr_Addr[12]_INST_0\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \Instr_Addr[13]_INST_0\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \Instr_Addr[14]_INST_0\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \Instr_Addr[15]_INST_0\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \Instr_Addr[16]_INST_0\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \Instr_Addr[17]_INST_0\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \Instr_Addr[18]_INST_0\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \Instr_Addr[19]_INST_0\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \Instr_Addr[1]_INST_0\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \Instr_Addr[20]_INST_0\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \Instr_Addr[21]_INST_0\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \Instr_Addr[22]_INST_0\ : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \Instr_Addr[23]_INST_0\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \Instr_Addr[24]_INST_0\ : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of \Instr_Addr[25]_INST_0\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \Instr_Addr[26]_INST_0\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \Instr_Addr[27]_INST_0\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \Instr_Addr[28]_INST_0\ : label is "soft_lutpair41";
  attribute SOFT_HLUTNM of \Instr_Addr[29]_INST_0\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \Instr_Addr[2]_INST_0\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \Instr_Addr[30]_INST_0\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \Instr_Addr[31]_INST_0\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \Instr_Addr[3]_INST_0\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \Instr_Addr[4]_INST_0\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \Instr_Addr[5]_INST_0\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \Instr_Addr[6]_INST_0\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \Instr_Addr[7]_INST_0\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \Instr_Addr[8]_INST_0\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \Instr_Addr[9]_INST_0\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_2\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of ex_delayslot_Instr_i_1 : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of ex_jump_hold_i_1 : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of ex_jump_q_i_1 : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of keep_jump_taken_with_ds_i_1 : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of mem_jump_taken_i_1 : label is "soft_lutpair27";
begin
  \^ex_jump_hold_reg\ <= lopt;
  ex_jump_hold_reg <= \^ex_jump_hold_reg\;
  lopt_1 <= \<const0>\;
  lopt_2 <= \Using_FPGA.Native_i_1__44_n_0\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\Instr_Addr[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(29),
      I1 => \^ex_jump_hold_reg\,
      I2 => O56_out,
      O => \if_pc_reg[0]\(31)
    );
\Instr_Addr[10]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(19),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[10]\,
      O => \if_pc_reg[0]\(21)
    );
\Instr_Addr[11]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(18),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[11]\,
      O => \if_pc_reg[0]\(20)
    );
\Instr_Addr[12]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(17),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[12]\,
      O => \if_pc_reg[0]\(19)
    );
\Instr_Addr[13]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(16),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[13]\,
      O => \if_pc_reg[0]\(18)
    );
\Instr_Addr[14]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(15),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[14]\,
      O => \if_pc_reg[0]\(17)
    );
\Instr_Addr[15]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(14),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[15]\,
      O => \if_pc_reg[0]\(16)
    );
\Instr_Addr[16]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(13),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[16]\,
      O => \if_pc_reg[0]\(15)
    );
\Instr_Addr[17]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(12),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[17]\,
      O => \if_pc_reg[0]\(14)
    );
\Instr_Addr[18]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(11),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[18]\,
      O => \if_pc_reg[0]\(13)
    );
\Instr_Addr[19]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(10),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[19]\,
      O => \if_pc_reg[0]\(12)
    );
\Instr_Addr[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(28),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[1]\,
      O => \if_pc_reg[0]\(30)
    );
\Instr_Addr[20]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(9),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[20]\,
      O => \if_pc_reg[0]\(11)
    );
\Instr_Addr[21]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(8),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[21]\,
      O => \if_pc_reg[0]\(10)
    );
\Instr_Addr[22]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(7),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[22]\,
      O => \if_pc_reg[0]\(9)
    );
\Instr_Addr[23]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(6),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[23]\,
      O => \if_pc_reg[0]\(8)
    );
\Instr_Addr[24]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(5),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[24]\,
      O => \if_pc_reg[0]\(7)
    );
\Instr_Addr[25]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(4),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[25]\,
      O => \if_pc_reg[0]\(6)
    );
\Instr_Addr[26]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(3),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[26]\,
      O => \if_pc_reg[0]\(5)
    );
\Instr_Addr[27]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(2),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[27]\,
      O => \if_pc_reg[0]\(4)
    );
\Instr_Addr[28]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(1),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[28]\,
      O => \if_pc_reg[0]\(3)
    );
\Instr_Addr[29]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(0),
      I1 => \^ex_jump_hold_reg\,
      I2 => O,
      O => \if_pc_reg[0]\(2)
    );
\Instr_Addr[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(27),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[2]\,
      O => \if_pc_reg[0]\(29)
    );
\Instr_Addr[30]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => ex_databus_addr(1),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[30]\(1),
      O => \if_pc_reg[0]\(1)
    );
\Instr_Addr[31]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => ex_databus_addr(0),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[30]\(0),
      O => \if_pc_reg[0]\(0)
    );
\Instr_Addr[3]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(26),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[3]\,
      O => \if_pc_reg[0]\(28)
    );
\Instr_Addr[4]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(25),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[4]\,
      O => \if_pc_reg[0]\(27)
    );
\Instr_Addr[5]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(24),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[5]\,
      O => \if_pc_reg[0]\(26)
    );
\Instr_Addr[6]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(23),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[6]\,
      O => \if_pc_reg[0]\(25)
    );
\Instr_Addr[7]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(22),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[7]\,
      O => \if_pc_reg[0]\(24)
    );
\Instr_Addr[8]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(21),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[8]\,
      O => \if_pc_reg[0]\(23)
    );
\Instr_Addr[9]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \if_pc_reg[0]_0\(20),
      I1 => \^ex_jump_hold_reg\,
      I2 => \if_pc_reg[9]\,
      O => \if_pc_reg[0]\(22)
    );
\Using_FPGA.Native_i_1__44\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000ABFF"
    )
        port map (
      I0 => ex_jump_hold,
      I1 => ex_mbar_stall_no_sleep_1,
      I2 => ex_first_cycle,
      I3 => ex_mbar_decode,
      I4 => ex_mbar_sleep,
      O => \Using_FPGA.Native_i_1__44_n_0\
    );
\Using_FPGA.Native_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => \^ex_jump_hold_reg\,
      I1 => wb_exception,
      I2 => Q(0),
      I3 => Q(1),
      O => I5
    );
ex_delayslot_Instr_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => keep_jump_taken_with_ds,
      I1 => ex_branch_with_delayslot,
      I2 => \^ex_jump_hold_reg\,
      O => ex_delayslot_Instr0
    );
ex_jump_hold_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => ex_jump_hold,
      I1 => \^ex_jump_hold_reg\,
      I2 => E(0),
      I3 => sync_reset,
      O => ex_jump_hold_reg_0
    );
ex_jump_q_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => ex_jump_q,
      I1 => \^ex_jump_hold_reg\,
      I2 => E(0),
      O => ex_jump_q_reg
    );
ex_valid_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000150015001500"
    )
        port map (
      I0 => ex_Exception_Taken,
      I1 => \^ex_jump_hold_reg\,
      I2 => ex_jump_nodelay,
      I3 => of_valid,
      I4 => mem_exception_from_ex,
      I5 => mem_valid_instr,
      O => of_next_ex_valid
    );
keep_jump_taken_with_ds_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000EA"
    )
        port map (
      I0 => keep_jump_taken_with_ds,
      I1 => \^ex_jump_hold_reg\,
      I2 => ex_branch_with_delayslot,
      I3 => sync_reset,
      I4 => keep_jump_taken_with_ds_reg_0,
      O => keep_jump_taken_with_ds_reg
    );
mem_jump_taken_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => ex_jump_hold,
      I1 => \^ex_jump_hold_reg\,
      O => mem_jump_taken0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_98 is
  port (
    CI : out STD_LOGIC;
    if_fetch_for_timing_optimization1 : in STD_LOGIC;
    if_pc_incr_carry1 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_98 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_98;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_98 is
  signal \<const0>\ : STD_LOGIC;
  signal \^ci\ : STD_LOGIC;
begin
  CI <= \^ci\;
  \^ci\ <= lopt;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_99 is
  port (
    if_pc_incr_carry0 : out STD_LOGIC;
    if_missed_fetch : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_99 : entity is "MB_MUXCY";
end design_1_microblaze_0_0_MB_MUXCY_99;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_99 is
  signal if_valid : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal lopt_26 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_19\ <= lopt_18;
  \^lopt_2\ <= lopt_1;
  \^lopt_20\ <= lopt_19;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_26 <= lopt_25;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => '1',
      CI_TOP => '0',
      CO(7) => \^lopt_11\,
      CO(6) => \^lopt_12\,
      CO(5) => \^lopt_13\,
      CO(4) => \^lopt_14\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => if_pc_incr_carry0,
      DI(7) => \^lopt_19\,
      DI(6) => \^lopt_20\,
      DI(5) => \^lopt_21\,
      DI(4) => \^lopt_22\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7) => \^lopt_15\,
      O(6) => \^lopt_16\,
      O(5) => \^lopt_17\,
      O(4) => \^lopt_18\,
      O(3) => \^lopt_10\,
      O(2 downto 0) => \NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED\(2 downto 0),
      S(7) => \^lopt_23\,
      S(6) => \^lopt_24\,
      S(5) => \^lopt_25\,
      S(4) => lopt_26,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => if_valid
    );
\Using_FPGA.Native_i_1__45\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => if_missed_fetch,
      O => if_valid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY is
  port (
    O56_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    LO : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY is
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I2_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I2_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I2_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native_I2_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => LO,
      CI_TOP => '0',
      CO(7 downto 0) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED\(7 downto 0),
      DI(7 downto 0) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED\(7 downto 0),
      O(7 downto 1) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 1),
      O(0) => O56_out,
      S(7 downto 1) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED\(7 downto 1),
      S(0) => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_270 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[10]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[10]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_270 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_270;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_270 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[10]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[10]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[10]\ <= \^if_pc_reg[10]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_271 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[11]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[11]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_271 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_271;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_271 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[11]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[11]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[11]\ <= \^if_pc_reg[11]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_272 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[12]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[12]_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_272 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_272;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_272 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[12]\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[12]\ <= lopt_19;
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \if_pc_reg[12]\ <= \^if_pc_reg[12]\;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_20 <= \<const0>\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_273 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[13]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[13]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_273 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_273;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_273 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[13]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[13]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[13]\ <= \^if_pc_reg[13]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_274 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[14]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[14]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_274 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_274;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_274 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[14]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[14]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[14]\ <= \^if_pc_reg[14]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_275 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[15]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[15]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_275 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_275;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_275 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[15]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[15]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[15]\ <= \^if_pc_reg[15]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_276 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[16]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[16]_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_276 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_276;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_276 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => \if_pc_reg[16]_0\,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => LO,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \if_pc_reg[16]\,
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_277 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[17]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[17]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_277 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_277;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_277 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[17]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[17]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[17]\ <= \^if_pc_reg[17]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_278 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[18]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[18]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_278 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_278;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_278 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[18]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[18]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[18]\ <= \^if_pc_reg[18]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_279 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[19]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[19]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_279 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_279;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_279 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[19]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[19]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[19]\ <= \^if_pc_reg[19]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_280 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[1]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[1]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_280 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_280;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_280 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[1]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[1]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[1]\ <= \^if_pc_reg[1]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_281 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[20]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[20]_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_281 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_281;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_281 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[20]\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[20]\ <= lopt_19;
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \if_pc_reg[20]\ <= \^if_pc_reg[20]\;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_20 <= \<const0>\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_282 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[21]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[21]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_282 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_282;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_282 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[21]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[21]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[21]\ <= \^if_pc_reg[21]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_283 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[22]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[22]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_283 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_283;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_283 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[22]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[22]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[22]\ <= \^if_pc_reg[22]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_284 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[23]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[23]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_284 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_284;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_284 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[23]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[23]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[23]\ <= \^if_pc_reg[23]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_285 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[24]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[24]_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_285 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_285;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_285 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => \if_pc_reg[24]_0\,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => LO,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \if_pc_reg[24]\,
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_286 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[25]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[25]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_286 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_286;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_286 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[25]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[25]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[25]\ <= \^if_pc_reg[25]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_287 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[26]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[26]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_287 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_287;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_287 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[26]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[26]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[26]\ <= \^if_pc_reg[26]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_288 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[27]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[27]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_288 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_288;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_288 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[27]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[27]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[27]\ <= \^if_pc_reg[27]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_289 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[28]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[28]_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_289 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_289;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_289 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[28]\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[28]\ <= lopt_19;
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \if_pc_reg[28]\ <= \^if_pc_reg[28]\;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_20 <= \<const0>\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_290 is
  port (
    LO : out STD_LOGIC;
    O : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    CI : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_290 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_290;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_290 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^o\ : STD_LOGIC;
begin
  LO <= \^lo\;
  O <= \^o\;
  \^lo\ <= lopt;
  \^o\ <= lopt_2;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_291 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[2]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[2]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_291 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_291;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_291 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[2]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[2]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[2]\ <= \^if_pc_reg[2]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_292 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[3]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[3]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_292 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_292;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_292 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[3]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[3]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[3]\ <= \^if_pc_reg[3]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_293 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[4]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[4]_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_293 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_293;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_293 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[4]\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[4]\ <= lopt_19;
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \if_pc_reg[4]\ <= \^if_pc_reg[4]\;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_20 <= \<const0>\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_294 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[5]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[5]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_294 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_294;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_294 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[5]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[5]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[5]\ <= \^if_pc_reg[5]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_295 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[6]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[6]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_295 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_295;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_295 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[6]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[6]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[6]\ <= \^if_pc_reg[6]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_296 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[7]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[7]_0\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_296 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_296;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_296 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[7]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[7]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[7]\ <= \^if_pc_reg[7]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_297 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[8]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[8]_0\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_297 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_297;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_297 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => \if_pc_reg[8]_0\,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => LO,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => '0',
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \if_pc_reg[8]\,
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => Q(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_298 is
  port (
    LO : out STD_LOGIC;
    \if_pc_reg[9]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    CI : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_298 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_298;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_298 is
  signal \<const0>\ : STD_LOGIC;
  signal \^lo\ : STD_LOGIC;
  signal \^if_pc_reg[9]\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \^if_pc_reg[9]\ <= lopt_2;
  \^lo\ <= lopt;
  \if_pc_reg[9]\ <= \^if_pc_reg[9]\;
  lopt_1 <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_308 is
  port (
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    addr_AddSub_31 : in STD_LOGIC;
    LO : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_308 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_308;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_308 is
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 1 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I2_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I2_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I2_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native_I2_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => LO,
      CI_TOP => '0',
      CO(7 downto 0) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED\(7 downto 0),
      DI(7 downto 0) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED\(7 downto 0),
      O(7 downto 1) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 1),
      O(0) => \Using_FPGA.Native\(0),
      S(7 downto 1) => \NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED\(7 downto 1),
      S(0) => addr_AddSub_31
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_310 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3017]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_310 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_310;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_310 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_313 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3018]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_313 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_313;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_313 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_316 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3019]\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_316 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_316;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_316 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \^using_fpga.native\(0) <= lopt_19;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_319 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3020]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_319 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_319;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_319 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_322 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3021]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_322 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_322;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_322 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_325 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3022]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_325 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_325;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_325 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_328 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[16]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[16]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3023]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3023]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3023]_1\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_328 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_328;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_328 is
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 16 to 16 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Trace_New_Reg_Value[16]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(16),
      I1 => \LOCKSTEP_Out_reg[3023]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3023]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => \LOCKSTEP_Out_reg[3023]_1\,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => LO,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => DI,
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => wb_excep_return_addr(16),
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => S
    );
\data_rd_reg[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[16]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[16]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_331 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[17]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[17]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3024]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3024]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3024]_1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_331 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_331;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_331 is
  signal \^lo\ : STD_LOGIC;
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 17 to 17 );
begin
  LO <= \^lo\;
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lo\ <= lopt;
  wb_excep_return_addr(17) <= lopt_1;
\Trace_New_Reg_Value[17]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(17),
      I1 => \LOCKSTEP_Out_reg[3024]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3024]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\data_rd_reg[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[17]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[17]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_334 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[18]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[18]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3025]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3025]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3025]_1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_334 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_334;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_334 is
  signal \^lo\ : STD_LOGIC;
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 18 to 18 );
begin
  LO <= \^lo\;
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lo\ <= lopt;
  wb_excep_return_addr(18) <= lopt_1;
\Trace_New_Reg_Value[18]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(18),
      I1 => \LOCKSTEP_Out_reg[3025]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3025]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\data_rd_reg[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[18]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[18]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_337 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[19]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[19]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3026]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3026]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3026]_1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_337 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_337;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_337 is
  signal \^lo\ : STD_LOGIC;
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 19 to 19 );
begin
  LO <= \^lo\;
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lo\ <= lopt;
  wb_excep_return_addr(19) <= lopt_1;
\Trace_New_Reg_Value[19]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(19),
      I1 => \LOCKSTEP_Out_reg[3026]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3026]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\data_rd_reg[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[19]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[19]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_340 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3008]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_340 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_340;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_340 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_343 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[20]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[20]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3027]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3027]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3027]_1\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_343 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_343;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_343 is
  signal \^lo\ : STD_LOGIC;
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 20 to 20 );
begin
  LO <= \^lo\;
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
  wb_excep_return_addr(20) <= lopt_19;
\Trace_New_Reg_Value[20]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(20),
      I1 => \LOCKSTEP_Out_reg[3027]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3027]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\data_rd_reg[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[20]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[20]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_346 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[21]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[21]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3028]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3028]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3028]_1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_346 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_346;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_346 is
  signal \^lo\ : STD_LOGIC;
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 21 to 21 );
begin
  LO <= \^lo\;
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lo\ <= lopt;
  wb_excep_return_addr(21) <= lopt_1;
\Trace_New_Reg_Value[21]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(21),
      I1 => \LOCKSTEP_Out_reg[3028]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3028]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\data_rd_reg[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[21]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[21]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_349 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[22]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[22]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3029]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3029]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3029]_1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_349 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_349;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_349 is
  signal \^lo\ : STD_LOGIC;
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 22 to 22 );
begin
  LO <= \^lo\;
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lo\ <= lopt;
  wb_excep_return_addr(22) <= lopt_1;
\Trace_New_Reg_Value[22]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(22),
      I1 => \LOCKSTEP_Out_reg[3029]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3029]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\data_rd_reg[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[22]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[22]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_352 is
  port (
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    WB_Byte_Access_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    LO : out STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[23]\ : in STD_LOGIC;
    DI : in STD_LOGIC;
    \data_rd_reg_reg[23]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3030]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3030]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3030]_1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_352 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_352;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_352 is
  signal \^lo\ : STD_LOGIC;
  signal \^wb_byte_access_reg\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 23 to 23 );
begin
  LO <= \^lo\;
  WB_Byte_Access_reg(0) <= \^wb_byte_access_reg\(0);
  \^lo\ <= lopt;
  wb_excep_return_addr(23) <= lopt_1;
\Trace_New_Reg_Value[23]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BBBB8B88"
    )
        port map (
      I0 => wb_excep_return_addr(23),
      I1 => \LOCKSTEP_Out_reg[3030]\,
      I2 => wb_byte_access,
      I3 => \LOCKSTEP_Out_reg[3030]_0\,
      I4 => Q(0),
      O => \^wb_byte_access_reg\(0)
    );
\data_rd_reg[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^wb_byte_access_reg\(0),
      I1 => wb_gpr_wr_dbg,
      I2 => \data_rd_reg_reg[23]\,
      I3 => DI,
      I4 => \data_rd_reg_reg[23]_0\,
      O => wb_gpr_write_dbg_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_355 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3031]\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_355 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_355;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_355 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => \LOCKSTEP_Out_reg[3031]\,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => LO,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => \Using_FPGA.Native_I2_0\,
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \Using_FPGA.Native\(0),
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_358 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3032]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_358 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_358;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_358 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_361 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3033]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_361 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_361;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_361 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_364 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3034]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_364 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_364;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_364 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_367 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3035]\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_367 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_367;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_367 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \^using_fpga.native\(0) <= lopt_19;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_370 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3036]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_370 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_370;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_370 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_373 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3009]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_373 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_373;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_373 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_376 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3037]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_376 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_376;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_376 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_379 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    CI : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_379 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_379;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_379 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_382 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3010]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_382 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_382;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_382 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_385 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3011]\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_385 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_385;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_385 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt_15;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  \^using_fpga.native\(0) <= lopt_19;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_388 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3012]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_388 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_388;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_388 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_391 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3013]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_391 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_391;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_391 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_394 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3014]\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_394 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_394;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_394 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_397 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3015]\ : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_397 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_397;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_397 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => \LOCKSTEP_Out_reg[3015]\,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => LO,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => \Using_FPGA.Native_I2_0\,
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \Using_FPGA.Native\(0),
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_400 is
  port (
    LO : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC;
    CI : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_400 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_400;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_400 is
  signal \^lo\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  LO <= \^lo\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \^lo\ <= lopt;
  \^using_fpga.native\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_519 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    EX_CarryIn : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_519 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_519;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_519 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[9]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[9]\(0) <= \^ex_op2_reg[9]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[9]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_521 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_521 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_521;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_521 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[8]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[8]\(0) <= \^ex_op2_reg[8]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[8]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_523 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_523 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_523;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_523 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[7]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[7]\(0) <= \^ex_op2_reg[7]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[7]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_525 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[6]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_525 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_525;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_525 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[6]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[6]\(0) <= \^ex_op2_reg[6]\(0);
  \^ex_carryout\ <= lopt_15;
  \^ex_op2_reg[6]\(0) <= lopt_19;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_527 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_527 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_527;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_527 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[5]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[5]\(0) <= \^ex_op2_reg[5]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[5]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_529 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_529 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_529;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_529 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[4]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[4]\(0) <= \^ex_op2_reg[4]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[4]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_531 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_531 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_531;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_531 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[3]\(0) <= \^ex_op2_reg[3]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[3]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_533 is
  port (
    EX_CarryOut : out STD_LOGIC;
    ex_databus_addr : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    EX_CarryIn : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_533 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_533;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_533 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_databus_addr\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \^ex_carryout\ <= lopt;
  \^ex_databus_addr\(0) <= lopt_1;
  ex_databus_addr(0) <= \^ex_databus_addr\(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_535 is
  port (
    EX_CarryOut : out STD_LOGIC;
    ex_databus_addr : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_535 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_535;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_535 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_databus_addr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  EX_CarryOut <= \^ex_carryout\;
  \^ex_carryout\ <= lopt_15;
  \^ex_databus_addr\(0) <= lopt_19;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  ex_databus_addr(0) <= \^ex_databus_addr\(0);
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_537 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_537 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_537;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_537 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal lopt_11 : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 2 );
  signal \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= lopt_11;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => LO,
      CI_TOP => '0',
      CO(7 downto 4) => \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_CO_UNCONNECTED\(7 downto 4),
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => EX_CarryOut,
      DI(7 downto 4) => \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_DI_UNCONNECTED\(7 downto 4),
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => DI,
      O(7 downto 4) => \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_O_UNCONNECTED\(7 downto 4),
      O(3) => lopt_11,
      O(2) => \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_O_UNCONNECTED\(2),
      O(1) => \^lopt_10\,
      O(0) => \EX_Op2_reg[2]\(0),
      S(7 downto 4) => \NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_S_UNCONNECTED\(7 downto 4),
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_539 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[29]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_539 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_539;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_539 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[29]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[29]\(0) <= \^ex_op2_reg[29]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[29]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_541 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_541 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_541;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_541 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[28]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[28]\(0) <= \^ex_op2_reg[28]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[28]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_543 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[27]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_543 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_543;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_543 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[27]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[27]\(0) <= \^ex_op2_reg[27]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[27]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_545 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_545 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_545;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_545 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => LO,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => EX_CarryOut,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => DI,
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \EX_Op2_reg[26]\(0),
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_547 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[25]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_547 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_547;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_547 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[25]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[25]\(0) <= \^ex_op2_reg[25]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[25]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_549 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_549 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_549;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_549 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[24]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[24]\(0) <= \^ex_op2_reg[24]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[24]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_551 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_551 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_551;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_551 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[23]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[23]\(0) <= \^ex_op2_reg[23]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[23]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_553 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[22]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_553 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_553;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_553 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[22]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[22]\(0) <= \^ex_op2_reg[22]\(0);
  \^ex_carryout\ <= lopt_15;
  \^ex_op2_reg[22]\(0) <= lopt_19;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_555 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_555 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_555;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_555 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[21]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[21]\(0) <= \^ex_op2_reg[21]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[21]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_557 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[20]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_557 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_557;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_557 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[20]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[20]\(0) <= \^ex_op2_reg[20]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[20]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_559 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_559 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_559;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_559 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[1]\(0) <= \^ex_op2_reg[1]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[1]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_561 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[19]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_561 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_561;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_561 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[19]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[19]\(0) <= \^ex_op2_reg[19]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[19]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_563 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_563 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_563;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_563 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => LO,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => EX_CarryOut,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => DI,
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \EX_Op2_reg[18]\(0),
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_565 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[17]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_565 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_565;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_565 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[17]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[17]\(0) <= \^ex_op2_reg[17]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[17]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_567 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_567 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_567;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_567 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[16]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[16]\(0) <= \^ex_op2_reg[16]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[16]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_569 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_569 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_569;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_569 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[15]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[15]\(0) <= \^ex_op2_reg[15]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[15]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_571 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[14]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_571 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_571;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_571 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[14]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[14]\(0) <= \^ex_op2_reg[14]\(0);
  \^ex_carryout\ <= lopt_15;
  \^ex_op2_reg[14]\(0) <= lopt_19;
  \^lopt_1\ <= lopt_14;
  \^lopt_10\ <= lopt_18;
  \^lopt_11\ <= lopt_17;
  \^lopt_12\ <= lopt_16;
  \^lopt_2\ <= lopt_1;
  \^lopt_3\ <= lopt_2;
  \^lopt_4\ <= lopt_13;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_7\ <= lopt_12;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_573 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[13]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_573 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_573;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_573 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[13]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[13]\(0) <= \^ex_op2_reg[13]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[13]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_575 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[12]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_575 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_575;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_575 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[12]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[12]\(0) <= \^ex_op2_reg[12]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[12]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_577 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_577 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_577;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_577 is
  signal \^ex_carryout\ : STD_LOGIC;
  signal \^ex_op2_reg[11]\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  EX_CarryOut <= \^ex_carryout\;
  \EX_Op2_reg[11]\(0) <= \^ex_op2_reg[11]\(0);
  \^ex_carryout\ <= lopt;
  \^ex_op2_reg[11]\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_579 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_579 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_579;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_579 is
  signal \^lopt_1\ : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal \^lopt_21\ : STD_LOGIC;
  signal \^lopt_22\ : STD_LOGIC;
  signal \^lopt_23\ : STD_LOGIC;
  signal \^lopt_24\ : STD_LOGIC;
  signal \^lopt_25\ : STD_LOGIC;
  signal \^lopt_26\ : STD_LOGIC;
  signal \^lopt_27\ : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  attribute OPT_MODIFIED : string;
  attribute OPT_MODIFIED of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "MLO";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "(CARRY4)";
  attribute XILINX_TRANSFORM_PINMAP : string;
  attribute XILINX_TRANSFORM_PINMAP of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "LO:O";
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native_I1_CARRY4_CARRY8\ : label is "PRIMITIVE";
begin
  \^lopt_2\ <= lopt_1;
  \^lopt_21\ <= lopt_20;
  \^lopt_22\ <= lopt_21;
  \^lopt_23\ <= lopt_22;
  \^lopt_24\ <= lopt_23;
  \^lopt_25\ <= lopt_24;
  \^lopt_26\ <= lopt_25;
  \^lopt_27\ <= lopt_26;
  \^lopt_3\ <= lopt_2;
  \^lopt_5\ <= lopt_4;
  \^lopt_6\ <= lopt_5;
  \^lopt_8\ <= lopt_7;
  \^lopt_9\ <= lopt_8;
  lopt <= \^lopt_1\;
  lopt_10 <= \^lopt_11\;
  lopt_11 <= \^lopt_12\;
  lopt_12 <= \^lopt_13\;
  lopt_13 <= \^lopt_14\;
  lopt_14 <= \^lopt_15\;
  lopt_15 <= \^lopt_16\;
  lopt_16 <= \^lopt_17\;
  lopt_17 <= \^lopt_18\;
  lopt_18 <= \^lopt_19\;
  lopt_19 <= \^lopt_20\;
  lopt_28 <= lopt_27;
  lopt_3 <= \^lopt_4\;
  lopt_6 <= \^lopt_7\;
  lopt_9 <= \^lopt_10\;
\Using_FPGA.Native_I1_CARRY4_CARRY8\: unisim.vcomponents.CARRY8
     port map (
      CI => LO,
      CI_TOP => '0',
      CO(7) => \^lopt_13\,
      CO(6) => \^lopt_14\,
      CO(5) => \^lopt_15\,
      CO(4) => \^lopt_16\,
      CO(3) => \^lopt_7\,
      CO(2) => \^lopt_4\,
      CO(1) => \^lopt_1\,
      CO(0) => EX_CarryOut,
      DI(7) => \^lopt_21\,
      DI(6) => \^lopt_22\,
      DI(5) => \^lopt_23\,
      DI(4) => \^lopt_24\,
      DI(3) => \^lopt_8\,
      DI(2) => \^lopt_5\,
      DI(1) => \^lopt_2\,
      DI(0) => DI,
      O(7) => \^lopt_17\,
      O(6) => \^lopt_18\,
      O(5) => \^lopt_19\,
      O(4) => \^lopt_20\,
      O(3) => \^lopt_12\,
      O(2) => \^lopt_11\,
      O(1) => \^lopt_10\,
      O(0) => \EX_Op2_reg[10]\(0),
      S(7) => \^lopt_25\,
      S(6) => \^lopt_26\,
      S(5) => \^lopt_27\,
      S(4) => lopt_28,
      S(3) => \^lopt_9\,
      S(2) => \^lopt_6\,
      S(1) => \^lopt_3\,
      S(0) => S
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXCY_XORCY_580 is
  port (
    \EX_Op2_reg[0]\ : out STD_LOGIC;
    \EX_Op2_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    DI : in STD_LOGIC;
    CI : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXCY_XORCY_580 : entity is "MB_MUXCY_XORCY";
end design_1_microblaze_0_0_MB_MUXCY_XORCY_580;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXCY_XORCY_580 is
  signal \^ex_op2_reg[0]\ : STD_LOGIC;
  signal \^ex_op2_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
  \EX_Op2_reg[0]\ <= \^ex_op2_reg[0]\;
  \EX_Op2_reg[0]_0\(0) <= \^ex_op2_reg[0]_0\(0);
  \^ex_op2_reg[0]\ <= lopt;
  \^ex_op2_reg[0]_0\(0) <= lopt_1;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7 is
  port (
    sel_input_i_1 : out STD_LOGIC;
    I4_0 : out STD_LOGIC;
    sel_input_iii_0 : in STD_LOGIC;
    sel_input_delayslot : in STD_LOGIC;
    ex_branch_with_delayslot_i : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7 is
  signal \^i4_0\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
  I4_0 <= \^i4_0\;
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => sel_input_iii_0,
      I1 => sel_input_delayslot,
      O => sel_input_i_1,
      S => \^i4_0\
    );
\Using_FPGA.Native_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAA"
    )
        port map (
      I0 => ex_branch_with_delayslot_i,
      I1 => wb_exception,
      I2 => Q(0),
      I3 => Q(1),
      O => \^i4_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_120 is
  port (
    of_instr_ii_42 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0169_out : in STD_LOGIC;
    I1167_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_120 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_120;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_120 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0169_out,
      I1 => I1167_out,
      O => of_instr_ii_42,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_122 is
  port (
    of_instr_ii_32 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0129_out : in STD_LOGIC;
    I1127_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_122 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_122;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_122 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0129_out,
      I1 => I1127_out,
      O => of_instr_ii_32,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_124 is
  port (
    of_instr_ii_31 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0125_out : in STD_LOGIC;
    I1123_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_124 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_124;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_124 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0125_out,
      I1 => I1123_out,
      O => of_instr_ii_31,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_126 is
  port (
    of_instr_ii_30 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0121_out : in STD_LOGIC;
    I1119_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_126 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_126;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_126 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0121_out,
      I1 => I1119_out,
      O => of_instr_ii_30,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_128 is
  port (
    of_instr_ii_29 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0117_out : in STD_LOGIC;
    I1115_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_128 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_128;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_128 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0117_out,
      I1 => I1115_out,
      O => of_instr_ii_29,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_130 is
  port (
    of_instr_ii_28 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0113_out : in STD_LOGIC;
    I1111_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_130 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_130;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_130 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0113_out,
      I1 => I1111_out,
      O => of_instr_ii_28,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_132 is
  port (
    of_instr_ii_27 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0109_out : in STD_LOGIC;
    I1107_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_132 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_132;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_132 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0109_out,
      I1 => I1107_out,
      O => of_instr_ii_27,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_134 is
  port (
    of_instr_ii_26 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0105_out : in STD_LOGIC;
    I1103_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_134 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_134;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_134 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0105_out,
      I1 => I1103_out,
      O => of_instr_ii_26,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_136 is
  port (
    of_instr_ii_25 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0101_out : in STD_LOGIC;
    I199_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_136 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_136;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_136 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0101_out,
      I1 => I199_out,
      O => of_instr_ii_25,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_138 is
  port (
    of_instr_ii_24 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I097_out : in STD_LOGIC;
    I195_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_138 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_138;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_138 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I097_out,
      I1 => I195_out,
      O => of_instr_ii_24,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_140 is
  port (
    of_instr_ii_23 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I093_out : in STD_LOGIC;
    I191_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_140 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_140;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_140 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I093_out,
      I1 => I191_out,
      O => of_instr_ii_23,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_142 is
  port (
    of_instr_ii_41 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0165_out : in STD_LOGIC;
    I1163_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_142 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_142;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_142 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0165_out,
      I1 => I1163_out,
      O => of_instr_ii_41,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_144 is
  port (
    of_instr_ii_22 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I089_out : in STD_LOGIC;
    I187_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_144 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_144;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_144 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I089_out,
      I1 => I187_out,
      O => of_instr_ii_22,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_146 is
  port (
    of_instr_ii_21 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I085_out : in STD_LOGIC;
    I183_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_146 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_146;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_146 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I085_out,
      I1 => I183_out,
      O => of_instr_ii_21,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_148 is
  port (
    of_instr_ii_20 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I081_out : in STD_LOGIC;
    I179_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_148 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_148;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_148 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I081_out,
      I1 => I179_out,
      O => of_instr_ii_20,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_150 is
  port (
    of_instr_ii_19 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I077_out : in STD_LOGIC;
    I175_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_150 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_150;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_150 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I077_out,
      I1 => I175_out,
      O => of_instr_ii_19,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_152 is
  port (
    of_instr_ii_18 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I073_out : in STD_LOGIC;
    I171_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_152 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_152;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_152 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I073_out,
      I1 => I171_out,
      O => of_instr_ii_18,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_154 is
  port (
    of_instr_ii_17 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I069_out : in STD_LOGIC;
    I167_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_154 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_154;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_154 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I069_out,
      I1 => I167_out,
      O => of_instr_ii_17,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_156 is
  port (
    of_instr_ii_16 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I065_out : in STD_LOGIC;
    I163_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_156 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_156;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_156 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I065_out,
      I1 => I163_out,
      O => of_instr_ii_16,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_158 is
  port (
    of_instr_ii_15 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I061_out : in STD_LOGIC;
    I159_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_158 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_158;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_158 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I061_out,
      I1 => I159_out,
      O => of_instr_ii_15,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_160 is
  port (
    of_instr_ii_14 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I057_out : in STD_LOGIC;
    I155_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_160 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_160;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_160 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I057_out,
      I1 => I155_out,
      O => of_instr_ii_14,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_162 is
  port (
    of_instr_ii_13 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I053_out : in STD_LOGIC;
    I151_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_162 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_162;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_162 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I053_out,
      I1 => I151_out,
      O => of_instr_ii_13,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_164 is
  port (
    of_instr_ii_40 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0161_out : in STD_LOGIC;
    I1159_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_164 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_164;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_164 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0161_out,
      I1 => I1159_out,
      O => of_instr_ii_40,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_166 is
  port (
    of_instr_ii_12 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I049_out : in STD_LOGIC;
    I147_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_166 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_166;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_166 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I049_out,
      I1 => I147_out,
      O => of_instr_ii_12,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_168 is
  port (
    of_instr_ii_11 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I045_out : in STD_LOGIC;
    I143_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_168 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_168;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_168 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I045_out,
      I1 => I143_out,
      O => of_instr_ii_11,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_170 is
  port (
    of_instr_ii_10 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I041_out : in STD_LOGIC;
    I139_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_170 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_170;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_170 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I041_out,
      I1 => I139_out,
      O => of_instr_ii_10,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_172 is
  port (
    of_instr_ii_9 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I037_out : in STD_LOGIC;
    I135_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_172 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_172;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_172 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I037_out,
      I1 => I135_out,
      O => of_instr_ii_9,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_174 is
  port (
    of_instr_ii_8 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I033_out : in STD_LOGIC;
    I131_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_174 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_174;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_174 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I033_out,
      I1 => I131_out,
      O => of_instr_ii_8,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_176 is
  port (
    of_instr_ii_7 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I029_out : in STD_LOGIC;
    I127_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_176 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_176;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_176 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I029_out,
      I1 => I127_out,
      O => of_instr_ii_7,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_178 is
  port (
    of_instr_ii_6 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I025_out : in STD_LOGIC;
    I123_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_178 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_178;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_178 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I025_out,
      I1 => I123_out,
      O => of_instr_ii_6,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_180 is
  port (
    of_instr_ii_5 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I021_out : in STD_LOGIC;
    I119_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_180 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_180;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_180 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I021_out,
      I1 => I119_out,
      O => of_instr_ii_5,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_182 is
  port (
    of_instr_ii_4 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I017_out : in STD_LOGIC;
    I115_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_182 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_182;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_182 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I017_out,
      I1 => I115_out,
      O => of_instr_ii_4,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_184 is
  port (
    of_instr_ii_3 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I013_out : in STD_LOGIC;
    I111_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_184 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_184;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_184 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I013_out,
      I1 => I111_out,
      O => of_instr_ii_3,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_186 is
  port (
    of_instr_ii_39 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0157_out : in STD_LOGIC;
    I1155_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_186 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_186;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_186 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0157_out,
      I1 => I1155_out,
      O => of_instr_ii_39,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_188 is
  port (
    of_instr_ii_2 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I09_out : in STD_LOGIC;
    I17_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_188 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_188;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_188 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I09_out,
      I1 => I17_out,
      O => of_instr_ii_2,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_190 is
  port (
    of_instr_ii_1 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I05_out : in STD_LOGIC;
    I13_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_190 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_190;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_190 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I05_out,
      I1 => I13_out,
      O => of_instr_ii_1,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_192 is
  port (
    of_instr_ii_0 : out STD_LOGIC;
    IReady_0 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0_1 : in STD_LOGIC;
    I1 : in STD_LOGIC;
    IReady : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    if_missed_fetch : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_192 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_192;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_192 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\PC_Buffer_reg[3][31]_srl4_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FF02"
    )
        port map (
      I0 => IReady,
      I1 => \Using_FPGA.Native_1\,
      I2 => \Using_FPGA.Native_2\,
      I3 => \Using_FPGA.Native_3\,
      I4 => if_missed_fetch,
      O => IReady_0
    );
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0_1,
      I1 => I1,
      O => of_instr_ii_0,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_194 is
  port (
    of_instr_ii_38 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0153_out : in STD_LOGIC;
    I1151_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_194 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_194;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_194 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0153_out,
      I1 => I1151_out,
      O => of_instr_ii_38,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_196 is
  port (
    of_instr_ii_37 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0149_out : in STD_LOGIC;
    I1147_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_196 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_196;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_196 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0149_out,
      I1 => I1147_out,
      O => of_instr_ii_37,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_198 is
  port (
    of_instr_ii_36 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0145_out : in STD_LOGIC;
    I1143_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_198 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_198;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_198 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0145_out,
      I1 => I1143_out,
      O => of_instr_ii_36,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_200 is
  port (
    of_instr_ii_35 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0141_out : in STD_LOGIC;
    I1139_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_200 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_200;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_200 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0141_out,
      I1 => I1139_out,
      O => of_instr_ii_35,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_202 is
  port (
    of_instr_ii_34 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0137_out : in STD_LOGIC;
    I1135_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_202 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_202;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_202 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0137_out,
      I1 => I1135_out,
      O => of_instr_ii_34,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_204 is
  port (
    of_instr_ii_33 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0133_out : in STD_LOGIC;
    I1131_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_204 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_204;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_204 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0133_out,
      I1 => I1131_out,
      O => of_instr_ii_33,
      S => \Using_FPGA.Native_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_207 is
  port (
    of_pc_ii_31 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0125_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_207 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_207;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_207 is
  signal I1123_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0125_out,
      I1 => I1123_out,
      O => of_pc_ii_31,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__57\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I1123_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_209 is
  port (
    of_pc_ii_21 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I085_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_209 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_209;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_209 is
  signal I183_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I085_out,
      I1 => I183_out,
      O => of_pc_ii_21,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__47\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I183_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_211 is
  port (
    of_pc_ii_20 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I081_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_211 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_211;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_211 is
  signal I179_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I081_out,
      I1 => I179_out,
      O => of_pc_ii_20,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__46\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I179_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_213 is
  port (
    of_pc_ii_19 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I077_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_213 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_213;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_213 is
  signal I175_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I077_out,
      I1 => I175_out,
      O => of_pc_ii_19,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__45\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I175_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_215 is
  port (
    of_pc_ii_18 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I073_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_215 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_215;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_215 is
  signal I171_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I073_out,
      I1 => I171_out,
      O => of_pc_ii_18,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I171_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_217 is
  port (
    of_pc_ii_17 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I069_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_217 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_217;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_217 is
  signal I167_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I069_out,
      I1 => I167_out,
      O => of_pc_ii_17,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__43\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I167_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_219 is
  port (
    of_pc_ii_16 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I065_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_219 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_219;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_219 is
  signal I163_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I065_out,
      I1 => I163_out,
      O => of_pc_ii_16,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__42\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I163_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_221 is
  port (
    of_pc_ii_15 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I061_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_221 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_221;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_221 is
  signal I159_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I061_out,
      I1 => I159_out,
      O => of_pc_ii_15,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__41\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I159_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_223 is
  port (
    of_pc_ii_14 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I057_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_223 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_223;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_223 is
  signal I155_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I057_out,
      I1 => I155_out,
      O => of_pc_ii_14,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__40\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I155_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_225 is
  port (
    of_pc_ii_13 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I053_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_225 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_225;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_225 is
  signal I151_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I053_out,
      I1 => I151_out,
      O => of_pc_ii_13,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__39\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I151_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_227 is
  port (
    of_pc_ii_12 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I049_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_227 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_227;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_227 is
  signal I147_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I049_out,
      I1 => I147_out,
      O => of_pc_ii_12,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__38\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I147_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_229 is
  port (
    of_pc_ii_30 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0121_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_229 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_229;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_229 is
  signal I1119_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0121_out,
      I1 => I1119_out,
      O => of_pc_ii_30,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__56\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I1119_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_231 is
  port (
    of_pc_ii_11 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I045_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_231 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_231;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_231 is
  signal I143_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I045_out,
      I1 => I143_out,
      O => of_pc_ii_11,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__37\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I143_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_233 is
  port (
    of_pc_ii_10 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I041_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_233 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_233;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_233 is
  signal I139_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I041_out,
      I1 => I139_out,
      O => of_pc_ii_10,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__36\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I139_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_235 is
  port (
    of_pc_ii_9 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I037_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_235 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_235;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_235 is
  signal I135_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I037_out,
      I1 => I135_out,
      O => of_pc_ii_9,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I135_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_237 is
  port (
    of_pc_ii_8 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I033_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_237 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_237;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_237 is
  signal I131_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I033_out,
      I1 => I131_out,
      O => of_pc_ii_8,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__34\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I131_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_239 is
  port (
    of_pc_ii_7 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I029_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_239 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_239;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_239 is
  signal I127_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I029_out,
      I1 => I127_out,
      O => of_pc_ii_7,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__33\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I127_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_241 is
  port (
    of_pc_ii_6 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I025_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_241 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_241;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_241 is
  signal I123_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I025_out,
      I1 => I123_out,
      O => of_pc_ii_6,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__32\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I123_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_243 is
  port (
    of_pc_ii_5 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I021_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_243 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_243;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_243 is
  signal I119_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I021_out,
      I1 => I119_out,
      O => of_pc_ii_5,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I119_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_245 is
  port (
    of_pc_ii_4 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I017_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_245 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_245;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_245 is
  signal I115_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I017_out,
      I1 => I115_out,
      O => of_pc_ii_4,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__30\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I115_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_247 is
  port (
    of_pc_ii_3 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I013_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_247 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_247;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_247 is
  signal I111_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I013_out,
      I1 => I111_out,
      O => of_pc_ii_3,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__29\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I111_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_249 is
  port (
    of_pc_ii_2 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I09_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_249 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_249;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_249 is
  signal I17_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I09_out,
      I1 => I17_out,
      O => of_pc_ii_2,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__28\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I17_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_251 is
  port (
    of_pc_ii_29 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0117_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_251 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_251;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_251 is
  signal I1115_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0117_out,
      I1 => I1115_out,
      O => of_pc_ii_29,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__55\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I1115_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_253 is
  port (
    of_pc_ii_1 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I05_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_253 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_253;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_253 is
  signal I13_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I05_out,
      I1 => I13_out,
      O => of_pc_ii_1,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I13_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_255 is
  port (
    of_pc_ii_0 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0 : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_255 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_255;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_255 is
  signal I1 : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0,
      I1 => I1,
      O => of_pc_ii_0,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_257 is
  port (
    of_pc_ii_28 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0113_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_257 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_257;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_257 is
  signal I1111_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0113_out,
      I1 => I1111_out,
      O => of_pc_ii_28,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__54\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I1111_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_259 is
  port (
    of_pc_ii_27 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0109_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_259 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_259;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_259 is
  signal I1107_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0109_out,
      I1 => I1107_out,
      O => of_pc_ii_27,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__53\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I1107_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_261 is
  port (
    of_pc_ii_26 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0105_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_261 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_261;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_261 is
  signal I1103_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0105_out,
      I1 => I1103_out,
      O => of_pc_ii_26,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__52\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I1103_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_263 is
  port (
    of_pc_ii_25 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I0101_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_263 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_263;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_263 is
  signal I199_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I0101_out,
      I1 => I199_out,
      O => of_pc_ii_25,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__51\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I199_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_265 is
  port (
    of_pc_ii_24 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I097_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_265 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_265;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_265 is
  signal I195_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I097_out,
      I1 => I195_out,
      O => of_pc_ii_24,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__50\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I195_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_267 is
  port (
    of_pc_ii_23 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I093_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_267 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_267;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_267 is
  signal I191_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I093_out,
      I1 => I191_out,
      O => of_pc_ii_23,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__49\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I191_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_269 is
  port (
    of_pc_ii_22 : out STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    I089_out : in STD_LOGIC;
    \out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_269 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_269;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_269 is
  signal I187_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => I089_out,
      I1 => I187_out,
      O => of_pc_ii_22,
      S => \Using_FPGA.Native_0\
    );
\Using_FPGA.Native_i_2__48\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => \out\(0),
      I1 => \Using_FPGA.Native_1\,
      I2 => Q(0),
      O => I187_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_424 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    I1 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_424 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_424;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_424 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[0]\(0),
      I1 => I1,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_4__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_425 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[10]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[10]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_425 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_425;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_425 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[10]\(0),
      I1 => \EX_Op1_reg[10]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__107\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_426 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[11]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[11]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_426 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_426;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_426 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[11]\(0),
      I1 => \EX_Op1_reg[11]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__106\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_427 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[12]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[12]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_427 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_427;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_427 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[12]\(0),
      I1 => \EX_Op1_reg[12]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__105\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_428 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[13]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[13]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_428 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_428;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_428 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[13]\(0),
      I1 => \EX_Op1_reg[13]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__104\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_429 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[14]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[14]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_429 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_429;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_429 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[14]\(0),
      I1 => \EX_Op1_reg[14]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__103\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_430 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[15]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[15]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_430 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_430;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_430 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[15]\(0),
      I1 => \EX_Op1_reg[15]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__102\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_431 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[16]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[16]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_431 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_431;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_431 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[16]\(0),
      I1 => \EX_Op1_reg[16]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__101\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_432 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[17]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[17]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_432 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_432;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_432 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[17]\(0),
      I1 => \EX_Op1_reg[17]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__100\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_433 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[18]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_433 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_433;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_433 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[18]\(0),
      I1 => \EX_Op1_reg[18]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__99\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_434 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[19]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[19]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_434 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_434;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_434 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[19]\(0),
      I1 => \EX_Op1_reg[19]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__98\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_435 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[1]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_435 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_435;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_435 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[1]\(0),
      I1 => \EX_Op1_reg[1]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__116\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_436 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[20]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[20]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_436 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_436;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_436 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[20]\(0),
      I1 => \EX_Op1_reg[20]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__97\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_437 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[21]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[21]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_437 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_437;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_437 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[21]\(0),
      I1 => \EX_Op1_reg[21]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__96\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_438 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[22]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_438 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_438;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_438 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[22]\(0),
      I1 => \EX_Op1_reg[22]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__95\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_439 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[23]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[23]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_439 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_439;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_439 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[23]\(0),
      I1 => \EX_Op1_reg[23]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__94\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_440 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[24]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_440 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_440;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_440 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[24]\(0),
      I1 => \EX_Op1_reg[24]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__93\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_441 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[25]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[25]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_441 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_441;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_441 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[25]\(0),
      I1 => \EX_Op1_reg[25]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__92\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_442 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[26]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[26]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_442 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_442;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_442 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[26]\(0),
      I1 => \EX_Op1_reg[26]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__91\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_443 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[27]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[27]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_443 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_443;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_443 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[27]\(0),
      I1 => \EX_Op1_reg[27]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__90\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_444 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[28]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[28]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_444 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_444;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_444 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[28]\(0),
      I1 => \EX_Op1_reg[28]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__89\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_445 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[29]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[29]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_445 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_445;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_445 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[29]\(0),
      I1 => \EX_Op1_reg[29]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__88\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_446 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[2]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_446 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_446;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_446 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[2]\(0),
      I1 => \EX_Op1_reg[2]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__115\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_447 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[30]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[30]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_447 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_447;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_447 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[30]\(0),
      I1 => \EX_Op1_reg[30]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__87\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_448 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[31]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[31]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_448 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_448;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_448 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[31]\(0),
      I1 => \EX_Op1_reg[31]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__86\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_449 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[3]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_449 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_449;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_449 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[3]\(0),
      I1 => \EX_Op1_reg[3]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__114\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_450 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[4]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_450 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_450;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_450 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[4]\(0),
      I1 => \EX_Op1_reg[4]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__113\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_451 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[5]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[5]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_451 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_451;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_451 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[5]\(0),
      I1 => \EX_Op1_reg[5]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__112\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_452 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[6]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[6]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_452 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_452;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_452 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[6]\(0),
      I1 => \EX_Op1_reg[6]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__111\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_453 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[7]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[7]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_453 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_453;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_453 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[7]\(0),
      I1 => \EX_Op1_reg[7]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__110\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(0),
      I1 => ex_swap_byte_instr,
      I2 => Q(1),
      O => swap_result_reg(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_454 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[8]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[8]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_454 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_454;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_454 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[8]\(0),
      I1 => \EX_Op1_reg[8]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__109\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_MUXF7_455 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    swap_result : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_op1_sel_spr : in STD_LOGIC;
    \EX_Op1_reg[9]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[9]_0\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_MUXF7_455 : entity is "MB_MUXF7";
end design_1_microblaze_0_0_MB_MUXF7_455;

architecture STRUCTURE of design_1_microblaze_0_0_MB_MUXF7_455 is
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.MUXF7
     port map (
      I0 => \EX_Op1_reg[9]\(0),
      I1 => \EX_Op1_reg[9]_0\,
      O => D(0),
      S => of_op1_sel_spr
    );
\Using_FPGA.Native_i_2__108\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => Q(1),
      I1 => ex_swap_byte_instr,
      I2 => Q(0),
      O => swap_result(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[0]\ : in STD_LOGIC;
    DID : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[0]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[0]_0\(4 downto 0),
      DIA(1 downto 0) => DID(1 downto 0),
      DIB(1 downto 0) => DID(1 downto 0),
      DIC(1 downto 0) => DID(1 downto 0),
      DID(1 downto 0) => DID(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_409 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[20]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[20]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[20]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_409 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_409;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_409 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[20]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[20]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[20]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[20]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[20]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[20]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_410 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[22]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[22]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[22]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_410 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_410;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_410 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[22]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[22]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[22]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[22]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[22]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[22]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_411 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[24]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[24]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[24]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_411 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_411;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_411 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[24]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[24]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[24]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[24]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[24]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[24]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_412 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[26]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[26]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[26]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_412 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_412;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_412 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[26]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[26]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[26]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[26]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[26]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[26]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_413 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[28]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[28]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[28]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_413 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_413;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_413 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[28]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[28]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[28]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[28]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[28]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[28]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_414 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[30]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[30]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[30]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_414 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_414;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_414 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[30]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[30]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[30]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[30]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[30]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[30]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_415 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[2]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[2]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_415 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_415;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_415 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[2]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[2]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[2]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[2]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[2]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[2]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_416 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[4]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[4]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[4]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_416 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_416;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_416 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[4]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[4]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[4]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[4]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[4]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[4]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_417 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[6]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[6]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[6]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_417 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_417;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_417 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[6]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[6]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[6]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[6]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[6]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[6]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_418 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[8]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[8]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[8]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_418 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_418;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_418 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[8]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[8]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[8]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[8]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[8]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[8]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_419 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[10]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[10]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[10]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_419 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_419;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_419 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[10]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[10]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[10]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[10]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[10]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[10]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_420 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[12]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[12]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[12]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_420 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_420;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_420 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[12]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[12]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[12]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[12]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[12]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[12]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_421 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[14]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[14]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[14]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_421 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_421;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_421 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[14]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[14]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[14]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[14]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[14]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[14]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_422 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[16]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[16]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[16]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_422 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_422;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_422 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[16]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[16]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[16]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[16]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[16]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[16]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_RAM32M_423 is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[18]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[18]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[18]_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_RAM32M_423 : entity is "MB_RAM32M";
end design_1_microblaze_0_0_MB_RAM32M_423;

architecture STRUCTURE of design_1_microblaze_0_0_MB_RAM32M_423 is
  signal \Using_FPGA.Native_n_6\ : STD_LOGIC;
  signal \Using_FPGA.Native_n_7\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Using_FPGA.Native\ : label is "PRIMITIVE";
begin
\Using_FPGA.Native\: unisim.vcomponents.RAM32M
    generic map(
      INIT_A => X"0000000000000000",
      INIT_B => X"0000000000000000",
      INIT_C => X"0000000000000000",
      INIT_D => X"0000000000000000",
      IS_WCLK_INVERTED => '0'
    )
        port map (
      ADDRA(4) => of_gpr_op1_rd_addr(0),
      ADDRA(3) => of_gpr_op1_rd_addr(1),
      ADDRA(2) => of_gpr_op1_rd_addr(2),
      ADDRA(1) => of_gpr_op1_rd_addr(3),
      ADDRA(0) => of_gpr_op1_rd_addr(4),
      ADDRB(4 downto 0) => of_imm_data(4 downto 0),
      ADDRC(4) => of_gpr_op3_rd_addr(0),
      ADDRC(3) => of_gpr_op3_rd_addr(1),
      ADDRC(2) => of_gpr_op3_rd_addr(2),
      ADDRC(1) => of_gpr_op3_rd_addr(3),
      ADDRC(0) => of_gpr_op3_rd_addr(4),
      ADDRD(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_1\(4 downto 0),
      DIA(1 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(1 downto 0),
      DIB(1 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(1 downto 0),
      DIC(1 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(1 downto 0),
      DID(1 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(1 downto 0),
      DOA(1 downto 0) => GPR_Op1(1 downto 0),
      DOB(1 downto 0) => GPR_Op2(1 downto 0),
      DOC(1 downto 0) => GPR_Op3(1 downto 0),
      DOD(1) => \Using_FPGA.Native_n_6\,
      DOD(0) => \Using_FPGA.Native_n_7\,
      WCLK => Clk,
      WE => \EX_Branch_CMP_Op1_reg[18]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRL16E is
  port (
    Q_0 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRL16E : entity is "MB_SRL16E";
end design_1_microblaze_0_0_MB_SRL16E;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRL16E is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"001B",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized1\ is
  port (
    Q11_in : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized1\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized1\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized1\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
  attribute srl_name : string;
  attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_2/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q11_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized1_17\ is
  port (
    \Serial_Dbg_Intf.shift_count_reg[0]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_17\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized1_17\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_17\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector ";
  attribute srl_name : string;
  attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => \Serial_Dbg_Intf.shift_count_reg[0]\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized1_18\ is
  port (
    tdo_config_word1_0 : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_18\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized1_18\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_18\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector ";
  attribute srl_name : string;
  attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector[2].SRL16E_Base_Vector/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => tdo_config_word1_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized1_19\ is
  port (
    Q4_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_19\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized1_19\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_19\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses ";
  attribute srl_name : string;
  attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[3].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q4_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized1_20\ is
  port (
    Q3_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_20\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized1_20\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_20\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses ";
  attribute srl_name : string;
  attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[4].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q3_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized1_23\ is
  port (
    Q0_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_23\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized1_23\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_23\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses ";
  attribute srl_name : string;
  attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[7].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q0_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized1_24\ is
  port (
    Q3_in : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_24\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized1_24\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized1_24\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
  attribute srl_bus_name : string;
  attribute srl_bus_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses ";
  attribute srl_name : string;
  attribute srl_name of \Use_unisim.MB_SRL16E_I1\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[8].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 ";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q3_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized3\ is
  port (
    Q6_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized3\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized3\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized3\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"FFFF",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q6_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized3_21\ is
  port (
    Q2_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized3_21\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized3_21\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized3_21\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"FFFF",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q2_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized5\ is
  port (
    \Serial_Dbg_Intf.shift_count_reg[6]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 6 downto 0 );
    Dbg_Clk : in STD_LOGIC;
    Dbg_TDO_INST_0_i_5 : in STD_LOGIC;
    Q6_out : in STD_LOGIC;
    Q11_in : in STD_LOGIC;
    Q_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized5\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized5\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized5\ is
  signal Dbg_TDO_INST_0_i_24_n_0 : STD_LOGIC;
  signal Q5_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
begin
Dbg_TDO_INST_0_i_13: unisim.vcomponents.MUXF7
     port map (
      I0 => Dbg_TDO_INST_0_i_24_n_0,
      I1 => Dbg_TDO_INST_0_i_5,
      O => \Serial_Dbg_Intf.shift_count_reg[6]\,
      S => Q(6)
    );
Dbg_TDO_INST_0_i_24: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => Q5_out,
      I1 => Q6_out,
      I2 => Q(5),
      I3 => Q11_in,
      I4 => Q(4),
      I5 => Q_0,
      O => Dbg_TDO_INST_0_i_24_n_0
    );
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"3FFF",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q5_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized5_22\ is
  port (
    \Serial_Dbg_Intf.shift_count_reg[5]\ : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 5 downto 0 );
    Dbg_Clk : in STD_LOGIC;
    Q2_out : in STD_LOGIC;
    Q3_out : in STD_LOGIC;
    Q4_out : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized5_22\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized5_22\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized5_22\ is
  signal Q1_out : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
begin
Dbg_TDO_INST_0_i_25: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => Q1_out,
      I1 => Q2_out,
      I2 => Q(5),
      I3 => Q3_out,
      I4 => Q(4),
      I5 => Q4_out,
      O => \Serial_Dbg_Intf.shift_count_reg[5]\
    );
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"3FFF",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q1_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized7\ is
  port (
    Q2_in : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized7\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized7\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized7\ is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0064",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q2_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_MB_SRL16E__parameterized9\ is
  port (
    Dbg_TDO : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
    Dbg_Clk : in STD_LOGIC;
    Data_Read_Reg_En : in STD_LOGIC;
    \TDO_Data_Reg__31\ : in STD_LOGIC;
    Dbg_TDO_INST_0_i_2_0 : in STD_LOGIC;
    Config_Reg_En : in STD_LOGIC;
    \TDO_Instr_Reg__0\ : in STD_LOGIC;
    Instr_Insert_Reg_En : in STD_LOGIC;
    tdo_config_word1_0 : in STD_LOGIC;
    Dbg_TDO_INST_0_i_5_0 : in STD_LOGIC;
    Q2_in : in STD_LOGIC;
    Q3_in : in STD_LOGIC;
    Q0_out : in STD_LOGIC;
    Status_Reg_En : in STD_LOGIC;
    \TDO_Status_Reg__17\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_MB_SRL16E__parameterized9\ : entity is "MB_SRL16E";
end \design_1_microblaze_0_0_MB_SRL16E__parameterized9\;

architecture STRUCTURE of \design_1_microblaze_0_0_MB_SRL16E__parameterized9\ is
  signal Dbg_TDO_INST_0_i_12_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_23_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_2_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_5_n_0 : STD_LOGIC;
  signal Q1_in : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16E_I1\ : label is "PRIMITIVE";
begin
Dbg_TDO_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E4"
    )
        port map (
      I0 => Status_Reg_En,
      I1 => Dbg_TDO_INST_0_i_2_n_0,
      I2 => \TDO_Status_Reg__17\,
      O => Dbg_TDO
    );
Dbg_TDO_INST_0_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CA0ACACACA0A0A0A"
    )
        port map (
      I0 => Dbg_TDO_INST_0_i_23_n_0,
      I1 => Q(5),
      I2 => Q(6),
      I3 => tdo_config_word1_0,
      I4 => Q(4),
      I5 => Dbg_TDO_INST_0_i_5_0,
      O => Dbg_TDO_INST_0_i_12_n_0
    );
Dbg_TDO_INST_0_i_2: unisim.vcomponents.MUXF7
     port map (
      I0 => Dbg_TDO_INST_0_i_5_n_0,
      I1 => \TDO_Data_Reg__31\,
      O => Dbg_TDO_INST_0_i_2_n_0,
      S => Data_Read_Reg_En
    );
Dbg_TDO_INST_0_i_23: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => Q1_in,
      I1 => Q2_in,
      I2 => Q(5),
      I3 => Q3_in,
      I4 => Q(4),
      I5 => Q0_out,
      O => Dbg_TDO_INST_0_i_23_n_0
    );
Dbg_TDO_INST_0_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B8FFB800B800B800"
    )
        port map (
      I0 => Dbg_TDO_INST_0_i_12_n_0,
      I1 => Q(7),
      I2 => Dbg_TDO_INST_0_i_2_0,
      I3 => Config_Reg_En,
      I4 => \TDO_Instr_Reg__0\,
      I5 => Instr_Insert_Reg_En,
      O => Dbg_TDO_INST_0_i_5_n_0
    );
\Use_unisim.MB_SRL16E_I1\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"2500",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Q(0),
      A1 => Q(1),
      A2 => Q(2),
      A3 => Q(3),
      CE => '0',
      CLK => Dbg_Clk,
      D => '0',
      Q => Q1_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E is
  port (
    SRL16_Sel_7 : out STD_LOGIC;
    \which_pc__0\ : out STD_LOGIC;
    SRL16_MC15_7 : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC;
    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E is
  signal \Use_unisim.MB_SRL16CE_I1_i_2_n_0\ : STD_LOGIC;
  signal \Use_unisim.MB_SRL16CE_I1_i_3_n_0\ : STD_LOGIC;
  signal \Use_unisim.MB_SRL16CE_I1_n_1\ : STD_LOGIC;
  signal \^which_pc__0\ : STD_LOGIC;
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
  \which_pc__0\ <= \^which_pc__0\;
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \^which_pc__0\,
      CLK => Dbg_Clk,
      D => SRL16_MC15_7,
      Q => SRL16_Sel_7,
      Q15 => \Use_unisim.MB_SRL16CE_I1_n_1\
    );
\Use_unisim.MB_SRL16CE_I1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010000"
    )
        port map (
      I0 => Dbg_Reg_En(2),
      I1 => Dbg_Reg_En(7),
      I2 => \Use_unisim.MB_SRL16CE_I1_i_2_n_0\,
      I3 => Dbg_Reg_En(6),
      I4 => Dbg_Reg_En(3),
      I5 => \Use_unisim.MB_SRL16CE_I1_i_3_n_0\,
      O => \^which_pc__0\
    );
\Use_unisim.MB_SRL16CE_I1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => Dbg_Reg_En(1),
      I1 => Dbg_Reg_En(0),
      O => \Use_unisim.MB_SRL16CE_I1_i_2_n_0\
    );
\Use_unisim.MB_SRL16CE_I1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => Dbg_Reg_En(4),
      I1 => Dbg_Reg_En(5),
      O => \Use_unisim.MB_SRL16CE_I1_i_3_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E_32 is
  port (
    SRL16_Sel_6 : out STD_LOGIC;
    SRL16_MC15_7 : out STD_LOGIC;
    \which_pc__0\ : in STD_LOGIC;
    SRL16_MC15_6 : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E_32 : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E_32;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E_32 is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \which_pc__0\,
      CLK => Dbg_Clk,
      D => SRL16_MC15_6,
      Q => SRL16_Sel_6,
      Q15 => SRL16_MC15_7
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E_34 is
  port (
    SRL16_Sel_5 : out STD_LOGIC;
    SRL16_MC15_6 : out STD_LOGIC;
    \which_pc__0\ : in STD_LOGIC;
    SRL16_MC15_5 : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E_34 : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E_34;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E_34 is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \which_pc__0\,
      CLK => Dbg_Clk,
      D => SRL16_MC15_5,
      Q => SRL16_Sel_5,
      Q15 => SRL16_MC15_6
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E_36 is
  port (
    SRL16_Sel_4 : out STD_LOGIC;
    SRL16_MC15_5 : out STD_LOGIC;
    \which_pc__0\ : in STD_LOGIC;
    SRL16_MC15_4 : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E_36 : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E_36;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E_36 is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \which_pc__0\,
      CLK => Dbg_Clk,
      D => SRL16_MC15_4,
      Q => SRL16_Sel_4,
      Q15 => SRL16_MC15_5
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E_38 is
  port (
    SRL16_Sel_3 : out STD_LOGIC;
    SRL16_MC15_4 : out STD_LOGIC;
    \which_pc__0\ : in STD_LOGIC;
    SRL16_MC15_3 : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E_38 : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E_38;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E_38 is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \which_pc__0\,
      CLK => Dbg_Clk,
      D => SRL16_MC15_3,
      Q => SRL16_Sel_3,
      Q15 => SRL16_MC15_4
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E_40 is
  port (
    SRL16_Sel_2 : out STD_LOGIC;
    SRL16_MC15_3 : out STD_LOGIC;
    \which_pc__0\ : in STD_LOGIC;
    SRL16_MC15_2 : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E_40 : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E_40;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E_40 is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \which_pc__0\,
      CLK => Dbg_Clk,
      D => SRL16_MC15_2,
      Q => SRL16_Sel_2,
      Q15 => SRL16_MC15_3
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E_42 is
  port (
    SRL16_Sel_1 : out STD_LOGIC;
    SRL16_MC15_2 : out STD_LOGIC;
    \which_pc__0\ : in STD_LOGIC;
    SRL16_MC15_1 : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E_42 : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E_42;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E_42 is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \which_pc__0\,
      CLK => Dbg_Clk,
      D => SRL16_MC15_1,
      Q => SRL16_Sel_1,
      Q15 => SRL16_MC15_2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MB_SRLC16E_44 is
  port (
    SRL16_Sel_0 : out STD_LOGIC;
    SRL16_MC15_1 : out STD_LOGIC;
    \which_pc__0\ : in STD_LOGIC;
    Dbg_TDI : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MB_SRLC16E_44 : entity is "MB_SRLC16E";
end design_1_microblaze_0_0_MB_SRLC16E_44;

architecture STRUCTURE of design_1_microblaze_0_0_MB_SRLC16E_44 is
  attribute box_type : string;
  attribute box_type of \Use_unisim.MB_SRL16CE_I1\ : label is "PRIMITIVE";
begin
\Use_unisim.MB_SRL16CE_I1\: unisim.vcomponents.SRLC16E
    generic map(
      INIT => X"0000",
      IS_CLK_INVERTED => '0'
    )
        port map (
      A0 => Address(0),
      A1 => Address(1),
      A2 => Address(2),
      A3 => Address(3),
      CE => \which_pc__0\,
      CLK => Dbg_Clk,
      D => Dbg_TDI,
      Q => SRL16_Sel_0,
      Q15 => SRL16_MC15_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Shift_Logic_Module_gti is
  port (
    \out\ : out STD_LOGIC;
    \EX_Op1_reg[24]\ : out STD_LOGIC;
    in0 : in STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Shift_Logic_Module_gti : entity is "Shift_Logic_Module_gti";
end design_1_microblaze_0_0_Shift_Logic_Module_gti;

architecture STRUCTURE of design_1_microblaze_0_0_Shift_Logic_Module_gti is
  signal sign_byte : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of sign_byte : signal is "true";
  signal sign_doublet : STD_LOGIC;
  attribute RTL_KEEP of sign_doublet : signal is "true";
begin
  \EX_Op1_reg[24]\ <= sign_doublet;
  \out\ <= sign_byte;
  sign_byte <= in0;
  sign_doublet <= \Using_FPGA.Native\;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    reset_temp : in STD_LOGIC;
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  \out\(0) <= sync(2);
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => reset_temp,
      Q => sync(1),
      R => '0'
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_0 is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    Wakeup : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_0 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_0;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_0 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  \out\(0) <= sync(2);
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => Wakeup(0),
      Q => sync(1),
      R => SR(0)
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_1 is
  port (
    \out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    Wakeup : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_1 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_1;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_1 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  \out\(0) <= sync(2);
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => Wakeup(0),
      Q => sync(1),
      R => SR(0)
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_46 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_94_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_46 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_46;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_46 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.normal_stop_cmd_i_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sync(2),
      I1 => Q(0),
      O => p_94_out
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => D(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_47 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_91_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_47 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_47;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_47 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.force_stop_cmd_i_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sync(2),
      I1 => Q(0),
      O => p_91_out
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_48 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_88_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_48 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_48;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_48 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.start_single_cmd_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sync(2),
      I1 => Q(0),
      O => p_88_out
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_49 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_86_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_49 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_49;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_49 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.read_register_MSR_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sync(2),
      I1 => Q(0),
      O => p_86_out
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_50 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_83_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_50 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_50;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_50 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.read_register_PC_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sync(2),
      I1 => Q(0),
      O => p_83_out
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_51 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Use_Async_Reset.sync_reset_reg\ : out STD_LOGIC;
    p_11_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Serial_Dbg_Intf.trig_in_1_reg\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
    Dbg_Trig_In : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_51 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_51;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_51 is
  signal \Serial_Dbg_Intf.trig_in_1_i_2_n_0\ : STD_LOGIC;
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.continue_from_brk_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => Q(2),
      I1 => sync(2),
      I2 => Q(1),
      I3 => \Serial_Dbg_Intf.trig_in_1_reg\(1),
      O => p_11_out
    );
\Serial_Dbg_Intf.trig_in_1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2202"
    )
        port map (
      I0 => \Serial_Dbg_Intf.trig_in_1_i_2_n_0\,
      I1 => sync_reset,
      I2 => \Serial_Dbg_Intf.trig_in_1_reg\(0),
      I3 => Q(0),
      O => \Use_Async_Reset.sync_reset_reg\
    );
\Serial_Dbg_Intf.trig_in_1_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF22F2"
    )
        port map (
      I0 => sync(2),
      I1 => Q(2),
      I2 => \Serial_Dbg_Intf.trig_in_1_reg\(2),
      I3 => Q(3),
      I4 => Dbg_Trig_In(0),
      O => \Serial_Dbg_Intf.trig_in_1_i_2_n_0\
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_52 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_76_out : out STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_52 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_52;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_52 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.if_debug_ready_i_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => sync(2),
      I1 => Q(0),
      O => p_76_out
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_53 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Serial_Dbg_Intf.trig_ack_out_1_reg\ : out STD_LOGIC;
    Dbg_Trig_Ack_Out : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Trig_Out : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_53 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_53;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_53 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Serial_Dbg_Intf.trig_ack_out_1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2302"
    )
        port map (
      I0 => Dbg_Trig_Ack_Out(0),
      I1 => sync_reset,
      I2 => Q(0),
      I3 => sync(2),
      O => \Serial_Dbg_Intf.trig_ack_out_1_reg\
    );
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => Dbg_Trig_Out(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_54 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    Dbg_Trig_Ack_In : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_54 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_54;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_54 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => Dbg_Trig_Ack_In(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_bit_55 is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_bit_55 : entity is "mb_sync_bit";
end design_1_microblaze_0_0_mb_sync_bit_55;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_bit_55 is
  signal sync : STD_LOGIC_VECTOR ( 1 to 2 );
  attribute async_reg : string;
  attribute async_reg of sync : signal is "true";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[1]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[1]\ : label is "yes";
  attribute ASYNC_REG_boolean of \Synchronize.use_sync_reset.sync_reg[2]\ : label is std.standard.true;
  attribute KEEP of \Synchronize.use_sync_reset.sync_reg[2]\ : label is "yes";
begin
  sample_synced(0) <= sync(2);
\Synchronize.use_sync_reset.sync_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      Q => sync(1),
      R => sync_reset
    );
\Synchronize.use_sync_reset.sync_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => sync(1),
      Q => sync(2),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized2\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    dbg_brki_hit : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    \Single_Synchronize.use_async_reset.sync_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized2\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized2\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized2\ is
begin
\Single_Synchronize.use_async_reset.sync_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Single_Synchronize.use_async_reset.sync_reg_0\,
      D => dbg_brki_hit,
      Q => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized2_25\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Single_Synchronize.use_async_reset.sync_i_1_0\ : out STD_LOGIC;
    Pause : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    Scan_En : in STD_LOGIC;
    Scan_Reset_Sel : in STD_LOGIC;
    Scan_Reset : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_25\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized2_25\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_25\ is
  signal \^single_synchronize.use_async_reset.sync_i_1_0\ : STD_LOGIC;
begin
  \Single_Synchronize.use_async_reset.sync_i_1_0\ <= \^single_synchronize.use_async_reset.sync_i_1_0\;
\Single_Synchronize.use_async_reset.sync_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => Scan_En,
      I1 => Scan_Reset_Sel,
      I2 => Scan_Reset,
      O => \^single_synchronize.use_async_reset.sync_i_1_0\
    );
\Single_Synchronize.use_async_reset.sync_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \^single_synchronize.use_async_reset.sync_i_1_0\,
      D => Pause,
      Q => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized2_26\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    running_clock : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    \Single_Synchronize.use_async_reset.sync_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_26\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized2_26\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_26\ is
begin
\Single_Synchronize.use_async_reset.sync_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Single_Synchronize.use_async_reset.sync_reg_0\,
      D => running_clock,
      Q => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized2_27\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    Sleep : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    \Single_Synchronize.use_async_reset.sync_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_27\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized2_27\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_27\ is
begin
\Single_Synchronize.use_async_reset.sync_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Single_Synchronize.use_async_reset.sync_reg_0\,
      D => Sleep,
      Q => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized2_28\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Single_Synchronize.use_async_reset.sync_reg_0\ : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    \Single_Synchronize.use_async_reset.sync_reg_1\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_28\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized2_28\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_28\ is
begin
\Single_Synchronize.use_async_reset.sync_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Single_Synchronize.use_async_reset.sync_reg_1\,
      D => \Single_Synchronize.use_async_reset.sync_reg_0\,
      Q => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized2_56\ is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    dbg_hit : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Clk : in STD_LOGIC;
    \Single_Synchronize.use_async_reset.sync_reg_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_56\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized2_56\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized2_56\ is
begin
\Single_Synchronize.use_async_reset.sync_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Single_Synchronize.use_async_reset.sync_reg_0\,
      D => dbg_hit(0),
      Q => D(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized4\ is
  port (
    \Performance_Debug_Control.dbg_stop_i_reg\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    dbg_continue_i_reg : in STD_LOGIC;
    dbg_continue_i_reg_0 : in STD_LOGIC;
    dbg_continue_i_reg_1 : in STD_LOGIC;
    of_pause : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized4\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized4\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized4\ is
  signal dbg_wakeup_synced : STD_LOGIC;
begin
\Single_Synchronize.use_sync_reset.sync_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => LOCKSTEP_Master_Out(1),
      Q => dbg_wakeup_synced,
      R => sync_reset
    );
dbg_continue_i_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF0000FFFE0000"
    )
        port map (
      I0 => dbg_continue_i_reg,
      I1 => dbg_wakeup_synced,
      I2 => dbg_continue_i_reg_0,
      I3 => dbg_continue_i_reg_1,
      I4 => of_pause,
      I5 => LOCKSTEP_Master_Out(0),
      O => \Performance_Debug_Control.dbg_stop_i_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized4_29\ is
  port (
    trig_ack_in_0_synced : out STD_LOGIC;
    trig_in_0_reg : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Dbg_Trig_Ack_In : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    Dbg_Trig_In : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    mb_halted_1 : in STD_LOGIC;
    trig_ack_in_0_synced_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized4_29\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized4_29\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized4_29\ is
  signal \^trig_ack_in_0_synced\ : STD_LOGIC;
begin
  trig_ack_in_0_synced <= \^trig_ack_in_0_synced\;
\Single_Synchronize.use_sync_reset.sync_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => Dbg_Trig_Ack_In(0),
      Q => \^trig_ack_in_0_synced\,
      R => sync_reset
    );
trig_in_0_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AE00AE000000AE"
    )
        port map (
      I0 => Dbg_Trig_In(0),
      I1 => D(0),
      I2 => mb_halted_1,
      I3 => sync_reset,
      I4 => \^trig_ack_in_0_synced\,
      I5 => trig_ack_in_0_synced_1,
      O => trig_in_0_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_bit__parameterized4_30\ is
  port (
    trig_out_0_synced : out STD_LOGIC;
    \Performance_Debug_Control.trig_ack_out_0_reg\ : out STD_LOGIC;
    \Performance_Debug_Control.trig_out_0_synced_1_reg\ : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Dbg_Trig_Out : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    Dbg_Trig_Ack_Out : in STD_LOGIC_VECTOR ( 0 to 0 );
    trig_out_0_synced_1 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Stop : in STD_LOGIC;
    dbg_stop_1 : in STD_LOGIC;
    \Performance_Debug_Control.dbg_stop_i_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_bit__parameterized4_30\ : entity is "mb_sync_bit";
end \design_1_microblaze_0_0_mb_sync_bit__parameterized4_30\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_bit__parameterized4_30\ is
  signal \^trig_out_0_synced\ : STD_LOGIC;
begin
  trig_out_0_synced <= \^trig_out_0_synced\;
\Performance_Debug_Control.dbg_stop_i_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF04040F04"
    )
        port map (
      I0 => trig_out_0_synced_1,
      I1 => \^trig_out_0_synced\,
      I2 => D(0),
      I3 => Dbg_Stop,
      I4 => dbg_stop_1,
      I5 => \Performance_Debug_Control.dbg_stop_i_reg\,
      O => \Performance_Debug_Control.trig_out_0_synced_1_reg\
    );
\Performance_Debug_Control.trig_ack_out_0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2302"
    )
        port map (
      I0 => Dbg_Trig_Ack_Out(0),
      I1 => sync_reset,
      I2 => trig_out_0_synced_1,
      I3 => \^trig_out_0_synced\,
      O => \Performance_Debug_Control.trig_ack_out_0_reg\
    );
\Single_Synchronize.use_sync_reset.sync_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => Dbg_Trig_Out(0),
      Q => \^trig_out_0_synced\,
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[10]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[10]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_578
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[10]\(1 downto 0) => \MEM_DataBus_Addr_reg[10]\(1 downto 0),
      \MEM_DataBus_Addr_reg[10]_0\(0) => \MEM_DataBus_Addr_reg[10]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_579
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[10]\(0) => \EX_Op2_reg[10]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_20 => lopt_20,
      lopt_21 => lopt_21,
      lopt_22 => lopt_22,
      lopt_23 => lopt_23,
      lopt_24 => lopt_24,
      lopt_25 => lopt_25,
      lopt_26 => lopt_26,
      lopt_27 => lopt_27,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_489 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[11]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[11]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_489 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_489;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_489 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_576
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[11]\(1 downto 0) => \MEM_DataBus_Addr_reg[11]\(1 downto 0),
      \MEM_DataBus_Addr_reg[11]_0\(0) => \MEM_DataBus_Addr_reg[11]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_577
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[11]\(0) => \EX_Op2_reg[11]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_490 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[12]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[12]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[12]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_490 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_490;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_490 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_574
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[12]\(1 downto 0) => \MEM_DataBus_Addr_reg[12]\(1 downto 0),
      \MEM_DataBus_Addr_reg[12]_0\(0) => \MEM_DataBus_Addr_reg[12]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_575
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[12]\(0) => \EX_Op2_reg[12]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_491 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[13]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[13]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[13]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_491 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_491;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_491 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_572
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[13]\(1 downto 0) => \MEM_DataBus_Addr_reg[13]\(1 downto 0),
      \MEM_DataBus_Addr_reg[13]_0\(0) => \MEM_DataBus_Addr_reg[13]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_573
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[13]\(0) => \EX_Op2_reg[13]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_492 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[14]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[14]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[14]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC;
    lopt_21 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_492 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_492;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_492 is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  lopt_20 <= op2_is_1;
  lopt_21 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_570
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[14]\(1 downto 0) => \MEM_DataBus_Addr_reg[14]\(1 downto 0),
      \MEM_DataBus_Addr_reg[14]_0\(0) => \MEM_DataBus_Addr_reg[14]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_571
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[14]\(0) => \EX_Op2_reg[14]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_493 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[15]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[15]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_493 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_493;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_493 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_568
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[15]\(1 downto 0) => \MEM_DataBus_Addr_reg[15]\(1 downto 0),
      \MEM_DataBus_Addr_reg[15]_0\(0) => \MEM_DataBus_Addr_reg[15]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_569
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[15]\(0) => \EX_Op2_reg[15]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_494 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[16]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[16]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_494 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_494;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_494 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_566
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[16]\(1 downto 0) => \MEM_DataBus_Addr_reg[16]\(1 downto 0),
      \MEM_DataBus_Addr_reg[16]_0\(0) => \MEM_DataBus_Addr_reg[16]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_567
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[16]\(0) => \EX_Op2_reg[16]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_495 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[17]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[17]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[17]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_495 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_495;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_495 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_564
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[17]\(1 downto 0) => \MEM_DataBus_Addr_reg[17]\(1 downto 0),
      \MEM_DataBus_Addr_reg[17]_0\(0) => \MEM_DataBus_Addr_reg[17]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_565
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[17]\(0) => \EX_Op2_reg[17]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_496 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[18]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[18]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_496 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_496;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_496 is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_562
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[18]\(1 downto 0) => \MEM_DataBus_Addr_reg[18]\(1 downto 0),
      \MEM_DataBus_Addr_reg[18]_0\(0) => \MEM_DataBus_Addr_reg[18]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_563
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[18]\(0) => \EX_Op2_reg[18]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_20 => lopt_20,
      lopt_21 => lopt_21,
      lopt_22 => lopt_22,
      lopt_23 => lopt_23,
      lopt_24 => lopt_24,
      lopt_25 => lopt_25,
      lopt_26 => lopt_26,
      lopt_27 => lopt_27,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_497 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[19]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[19]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[19]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_497 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_497;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_497 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_560
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[19]\(1 downto 0) => \MEM_DataBus_Addr_reg[19]\(1 downto 0),
      \MEM_DataBus_Addr_reg[19]_0\(0) => \MEM_DataBus_Addr_reg[19]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_561
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[19]\(0) => \EX_Op2_reg[19]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_498 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_498 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_498;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_498 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_558
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[1]\(1 downto 0) => \MEM_DataBus_Addr_reg[1]\(1 downto 0),
      \MEM_DataBus_Addr_reg[1]_0\(0) => \MEM_DataBus_Addr_reg[1]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_559
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[1]\(0) => \EX_Op2_reg[1]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_499 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[20]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[20]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[20]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_499 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_499;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_499 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_556
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[20]\(1 downto 0) => \MEM_DataBus_Addr_reg[20]\(1 downto 0),
      \MEM_DataBus_Addr_reg[20]_0\(0) => \MEM_DataBus_Addr_reg[20]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_557
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[20]\(0) => \EX_Op2_reg[20]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_500 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[21]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[21]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[21]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_500 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_500;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_500 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_554
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[21]\(1 downto 0) => \MEM_DataBus_Addr_reg[21]\(1 downto 0),
      \MEM_DataBus_Addr_reg[21]_0\(0) => \MEM_DataBus_Addr_reg[21]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_555
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[21]\(0) => \EX_Op2_reg[21]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_501 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[22]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[22]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[22]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC;
    lopt_21 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_501 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_501;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_501 is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  lopt_20 <= op2_is_1;
  lopt_21 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_552
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[22]\(1 downto 0) => \MEM_DataBus_Addr_reg[22]\(1 downto 0),
      \MEM_DataBus_Addr_reg[22]_0\(0) => \MEM_DataBus_Addr_reg[22]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_553
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[22]\(0) => \EX_Op2_reg[22]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_502 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[23]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[23]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[23]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_502 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_502;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_502 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_550
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[23]\(1 downto 0) => \MEM_DataBus_Addr_reg[23]\(1 downto 0),
      \MEM_DataBus_Addr_reg[23]_0\(0) => \MEM_DataBus_Addr_reg[23]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_551
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[23]\(0) => \EX_Op2_reg[23]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_503 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[24]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[24]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_503 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_503;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_503 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_548
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[24]\(1 downto 0) => \MEM_DataBus_Addr_reg[24]\(1 downto 0),
      \MEM_DataBus_Addr_reg[24]_0\(0) => \MEM_DataBus_Addr_reg[24]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_549
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[24]\(0) => \EX_Op2_reg[24]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_504 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[25]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[25]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[25]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_504 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_504;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_504 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_546
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[25]\(1 downto 0) => \MEM_DataBus_Addr_reg[25]\(1 downto 0),
      \MEM_DataBus_Addr_reg[25]_0\(0) => \MEM_DataBus_Addr_reg[25]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_547
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[25]\(0) => \EX_Op2_reg[25]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_505 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[26]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[26]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC;
    lopt_26 : in STD_LOGIC;
    lopt_27 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_505 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_505;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_505 is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_544
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[26]\(1 downto 0) => \MEM_DataBus_Addr_reg[26]\(1 downto 0),
      \MEM_DataBus_Addr_reg[26]_0\(0) => \MEM_DataBus_Addr_reg[26]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_545
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[26]\(0) => \EX_Op2_reg[26]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_20 => lopt_20,
      lopt_21 => lopt_21,
      lopt_22 => lopt_22,
      lopt_23 => lopt_23,
      lopt_24 => lopt_24,
      lopt_25 => lopt_25,
      lopt_26 => lopt_26,
      lopt_27 => lopt_27,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_506 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[27]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[27]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[27]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_506 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_506;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_506 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_542
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[27]\(1 downto 0) => \MEM_DataBus_Addr_reg[27]\(1 downto 0),
      \MEM_DataBus_Addr_reg[27]_0\(0) => \MEM_DataBus_Addr_reg[27]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_543
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[27]\(0) => \EX_Op2_reg[27]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_507 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[28]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[28]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_507 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_507;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_507 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_540
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[28]\(1 downto 0) => \MEM_DataBus_Addr_reg[28]\(1 downto 0),
      \MEM_DataBus_Addr_reg[28]_0\(0) => \MEM_DataBus_Addr_reg[28]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_541
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[28]\(0) => \EX_Op2_reg[28]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_508 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[29]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[29]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[29]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_508 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_508;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_508 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_538
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[29]\(1 downto 0) => \MEM_DataBus_Addr_reg[29]\(1 downto 0),
      \MEM_DataBus_Addr_reg[29]_0\(0) => \MEM_DataBus_Addr_reg[29]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_539
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[29]\(0) => \EX_Op2_reg[29]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_509 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_509 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_509;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_509 is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_536
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[2]\(1 downto 0) => \MEM_DataBus_Addr_reg[2]\(1 downto 0),
      \MEM_DataBus_Addr_reg[2]_0\(0) => \MEM_DataBus_Addr_reg[2]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_537
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[2]\(0) => \EX_Op2_reg[2]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_2 => lopt_2,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_510 is
  port (
    EX_CarryOut : out STD_LOGIC;
    ex_databus_addr : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_I2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC;
    lopt_21 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_510 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_510;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_510 is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  lopt_20 <= op2_is_1;
  lopt_21 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_534
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      Q(0) => Q(0),
      S => alu_AddSub,
      \Using_FPGA.Native_I2\(1 downto 0) => \Using_FPGA.Native_I2\(1 downto 0),
      \Using_FPGA.Native_I2_0\(0) => \Using_FPGA.Native_I2_0\(0)
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_535
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      LO => LO,
      S => alu_AddSub,
      ex_databus_addr(0) => ex_databus_addr(0),
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_511 is
  port (
    EX_CarryOut : out STD_LOGIC;
    ex_databus_addr : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_I2\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_I2_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    EX_CarryIn : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_511 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_511;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_511 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_532
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      Q(0) => Q(0),
      S => alu_AddSub,
      \Using_FPGA.Native_I2\(1 downto 0) => \Using_FPGA.Native_I2\(1 downto 0),
      \Using_FPGA.Native_I2_0\(0) => \Using_FPGA.Native_I2_0\(0)
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_533
     port map (
      DI => op2_is_1,
      EX_CarryIn => EX_CarryIn,
      EX_CarryOut => EX_CarryOut,
      S => alu_AddSub,
      ex_databus_addr(0) => ex_databus_addr(0),
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_512 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_512 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_512;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_512 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_530
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[3]\(1 downto 0) => \MEM_DataBus_Addr_reg[3]\(1 downto 0),
      \MEM_DataBus_Addr_reg[3]_0\(0) => \MEM_DataBus_Addr_reg[3]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_531
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[3]\(0) => \EX_Op2_reg[3]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_513 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_513 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_513;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_513 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_528
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[4]\(1 downto 0) => \MEM_DataBus_Addr_reg[4]\(1 downto 0),
      \MEM_DataBus_Addr_reg[4]_0\(0) => \MEM_DataBus_Addr_reg[4]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_529
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[4]\(0) => \EX_Op2_reg[4]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_514 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[5]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[5]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_514 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_514;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_514 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_526
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[5]\(1 downto 0) => \MEM_DataBus_Addr_reg[5]\(1 downto 0),
      \MEM_DataBus_Addr_reg[5]_0\(0) => \MEM_DataBus_Addr_reg[5]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_527
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[5]\(0) => \EX_Op2_reg[5]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_515 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[6]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[6]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : out STD_LOGIC;
    lopt_21 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_515 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_515;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_515 is
  signal alu_AddSub : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  lopt_20 <= op2_is_1;
  lopt_21 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_524
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[6]\(1 downto 0) => \MEM_DataBus_Addr_reg[6]\(1 downto 0),
      \MEM_DataBus_Addr_reg[6]_0\(0) => \MEM_DataBus_Addr_reg[6]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_525
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[6]\(0) => \EX_Op2_reg[6]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_516 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[7]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[7]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_516 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_516;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_516 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_522
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[7]\(1 downto 0) => \MEM_DataBus_Addr_reg[7]\(1 downto 0),
      \MEM_DataBus_Addr_reg[7]_0\(0) => \MEM_DataBus_Addr_reg[7]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_523
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[7]\(0) => \EX_Op2_reg[7]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_517 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[8]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[8]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    LO : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_517 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_517;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_517 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2_520
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[8]\(1 downto 0) => \MEM_DataBus_Addr_reg[8]\(1 downto 0),
      \MEM_DataBus_Addr_reg[8]_0\(0) => \MEM_DataBus_Addr_reg[8]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_521
     port map (
      DI => op2_is_1,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[8]\(0) => \EX_Op2_reg[8]\(0),
      LO => LO,
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU_Bit_518 is
  port (
    EX_CarryOut : out STD_LOGIC;
    \EX_Op2_reg[9]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \MEM_DataBus_Addr_reg[9]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    EX_CarryIn : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU_Bit_518 : entity is "ALU_Bit";
end design_1_microblaze_0_0_ALU_Bit_518;

architecture STRUCTURE of design_1_microblaze_0_0_ALU_Bit_518 is
  signal alu_AddSub : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_1\ <= lopt_3;
  lopt_1 <= op2_is_1;
  lopt_2 <= alu_AddSub;
\Not_Last_Bit.I_ALU_LUT_V5\: entity work.design_1_microblaze_0_0_MB_LUT6_2
     port map (
      DI => op2_is_1,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \MEM_DataBus_Addr_reg[9]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[9]_0\(0) => \MEM_DataBus_Addr_reg[9]_0\(0),
      Q(0) => Q(0),
      S => alu_AddSub
    );
\Not_Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_519
     port map (
      DI => op2_is_1,
      EX_CarryIn => EX_CarryIn,
      EX_CarryOut => EX_CarryOut,
      \EX_Op2_reg[9]\(0) => \EX_Op2_reg[9]\(0),
      S => alu_AddSub,
      lopt => lopt,
      lopt_1 => \^lopt_1\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_ALU_Bit__parameterized2\ is
  port (
    \EX_Op2_reg[0]\ : out STD_LOGIC;
    \EX_Op2_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : in STD_LOGIC;
    ex_unsigned_op : in STD_LOGIC;
    LO : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \MEM_DataBus_Addr_reg[0]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    I2 : in STD_LOGIC;
    I0 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_ALU_Bit__parameterized2\ : entity is "ALU_Bit";
end \design_1_microblaze_0_0_ALU_Bit__parameterized2\;

architecture STRUCTURE of \design_1_microblaze_0_0_ALU_Bit__parameterized2\ is
  signal alu_AddSub : STD_LOGIC;
  signal alu_AddSub_1 : STD_LOGIC;
  signal invert_result : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal op2_is_1 : STD_LOGIC;
begin
  \^lopt_2\ <= lopt_4;
  lopt_2 <= op2_is_1;
  lopt_3 <= alu_AddSub;
\Last_Bit.I_ALU_LUT_2\: entity work.design_1_microblaze_0_0_MB_LUT4
     port map (
      I2 => I2,
      \MEM_DataBus_Addr_reg[0]\(0) => \MEM_DataBus_Addr_reg[0]\(1),
      Q(0) => Q(0),
      S => alu_AddSub,
      alu_AddSub_1 => alu_AddSub_1
    );
\Last_Bit.I_ALU_LUT_V5\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized12\
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      Q(0) => Q(0),
      \Using_FPGA.Native_0\(1 downto 0) => \MEM_DataBus_Addr_reg[0]\(1 downto 0),
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native\(0),
      alu_AddSub_1 => alu_AddSub_1
    );
\Last_Bit.MULT_AND_I\: entity work.design_1_microblaze_0_0_MB_MULT_AND
     port map (
      DI => op2_is_1,
      I0 => I0,
      \Using_FPGA.Native_I1\(0) => \MEM_DataBus_Addr_reg[0]\(1)
    );
\Last_Bit.MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_580
     port map (
      CI => invert_result,
      DI => op2_is_1,
      \EX_Op2_reg[0]\ => \EX_Op2_reg[0]\,
      \EX_Op2_reg[0]_0\(0) => \EX_Op2_reg[0]_0\(0),
      S => alu_AddSub,
      lopt => lopt_1,
      lopt_1 => \^lopt_2\
    );
\Last_Bit.Pre_MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_581
     port map (
      CI => invert_result,
      LO => LO,
      S => S,
      ex_unsigned_op => ex_unsigned_op,
      lopt => lopt
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Data_Flow_Logic is
  port (
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    MEM_Fwd : out STD_LOGIC_VECTOR ( 27 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    R : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 31 );
    Clk : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \WB_MEM_Result_reg[0]_0\ : in STD_LOGIC;
    \WB_MEM_Result_reg[0]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Data_Flow_Logic : entity is "Data_Flow_Logic";
end design_1_microblaze_0_0_Data_Flow_Logic;

architecture STRUCTURE of design_1_microblaze_0_0_Data_Flow_Logic is
  signal \^mem_fwd\ : STD_LOGIC_VECTOR ( 27 downto 0 );
begin
  MEM_Fwd(27 downto 0) <= \^mem_fwd\(27 downto 0);
\Gen_Bits[0].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_456
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(0),
      R => R,
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native\(3),
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_0\
    );
\Gen_Bits[10].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_457
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(10),
      MEM_Fwd(0) => \^mem_fwd\(18),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[11].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_458
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(11),
      MEM_Fwd(0) => \^mem_fwd\(17),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[12].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_459
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(12),
      MEM_Fwd(0) => \^mem_fwd\(16),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[13].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_460
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(13),
      MEM_Fwd(0) => \^mem_fwd\(15),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[14].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_461
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(14),
      MEM_Fwd(0) => \^mem_fwd\(14),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[15].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_462
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(15),
      MEM_Fwd(0) => \^mem_fwd\(13),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[16].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_463
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(16),
      MEM_Fwd(0) => \^mem_fwd\(12),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[17].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_464
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(17),
      MEM_Fwd(0) => \^mem_fwd\(11),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[18].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_465
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(18),
      MEM_Fwd(0) => \^mem_fwd\(10),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[19].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_466
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(19),
      MEM_Fwd(0) => \^mem_fwd\(9),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[1].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_467
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(1),
      MEM_Fwd(0) => \^mem_fwd\(27),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[20].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_468
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(20),
      MEM_Fwd(0) => \^mem_fwd\(8),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[21].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_469
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(21),
      MEM_Fwd(0) => \^mem_fwd\(7),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[22].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_470
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(22),
      MEM_Fwd(0) => \^mem_fwd\(6),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[23].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_471
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(23),
      MEM_Fwd(0) => \^mem_fwd\(5),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[24].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_472
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(24),
      MEM_Fwd(0) => \^mem_fwd\(4),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[25].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_473
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(25),
      MEM_Fwd(0) => \^mem_fwd\(3),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[26].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_474
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(26),
      MEM_Fwd(0) => \^mem_fwd\(2),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[27].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_475
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(27),
      MEM_Fwd(0) => \^mem_fwd\(1),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[28].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_476
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(28),
      R => R,
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native\(2),
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_0\
    );
\Gen_Bits[29].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_477
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(29),
      R => R,
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native\(1),
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_0\
    );
\Gen_Bits[2].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_478
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(2),
      MEM_Fwd(0) => \^mem_fwd\(26),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[30].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_479
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(30),
      R => R,
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native\(0),
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_0\
    );
\Gen_Bits[31].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_480
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(31),
      MEM_Fwd(0) => \^mem_fwd\(0),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[3].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_481
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(3),
      MEM_Fwd(0) => \^mem_fwd\(25),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[4].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_482
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(4),
      MEM_Fwd(0) => \^mem_fwd\(24),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[5].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_483
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(5),
      MEM_Fwd(0) => \^mem_fwd\(23),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[6].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_484
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(6),
      MEM_Fwd(0) => \^mem_fwd\(22),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[7].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_485
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(7),
      MEM_Fwd(0) => \^mem_fwd\(21),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[8].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_486
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(8),
      MEM_Fwd(0) => \^mem_fwd\(20),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\Gen_Bits[9].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_487
     port map (
      Clk => Clk,
      EX_Fwd(0) => EX_Fwd(9),
      MEM_Fwd(0) => \^mem_fwd\(19),
      R => R,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      mem_sel_msr => mem_sel_msr
    );
\WB_MEM_Result_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \WB_MEM_Result_reg[0]_1\(3),
      Q => Q(31),
      R => SR(0)
    );
\WB_MEM_Result_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(18),
      Q => Q(21),
      R => SR(0)
    );
\WB_MEM_Result_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(17),
      Q => Q(20),
      R => SR(0)
    );
\WB_MEM_Result_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(16),
      Q => Q(19),
      R => SR(0)
    );
\WB_MEM_Result_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(15),
      Q => Q(18),
      R => SR(0)
    );
\WB_MEM_Result_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(14),
      Q => Q(17),
      R => SR(0)
    );
\WB_MEM_Result_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(13),
      Q => Q(16),
      R => SR(0)
    );
\WB_MEM_Result_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(12),
      Q => Q(15),
      R => SR(0)
    );
\WB_MEM_Result_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(11),
      Q => Q(14),
      R => SR(0)
    );
\WB_MEM_Result_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(10),
      Q => Q(13),
      R => SR(0)
    );
\WB_MEM_Result_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(9),
      Q => Q(12),
      R => SR(0)
    );
\WB_MEM_Result_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(27),
      Q => Q(30),
      R => SR(0)
    );
\WB_MEM_Result_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(8),
      Q => Q(11),
      R => SR(0)
    );
\WB_MEM_Result_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(7),
      Q => Q(10),
      R => SR(0)
    );
\WB_MEM_Result_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(6),
      Q => Q(9),
      R => SR(0)
    );
\WB_MEM_Result_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(5),
      Q => Q(8),
      R => SR(0)
    );
\WB_MEM_Result_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(4),
      Q => Q(7),
      R => SR(0)
    );
\WB_MEM_Result_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(3),
      Q => Q(6),
      R => SR(0)
    );
\WB_MEM_Result_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(2),
      Q => Q(5),
      R => SR(0)
    );
\WB_MEM_Result_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(1),
      Q => Q(4),
      R => SR(0)
    );
\WB_MEM_Result_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \WB_MEM_Result_reg[0]_1\(2),
      Q => Q(3),
      R => SR(0)
    );
\WB_MEM_Result_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \WB_MEM_Result_reg[0]_1\(1),
      Q => Q(2),
      R => SR(0)
    );
\WB_MEM_Result_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(26),
      Q => Q(29),
      R => SR(0)
    );
\WB_MEM_Result_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \WB_MEM_Result_reg[0]_1\(0),
      Q => Q(1),
      R => SR(0)
    );
\WB_MEM_Result_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(0),
      Q => Q(0),
      R => SR(0)
    );
\WB_MEM_Result_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(25),
      Q => Q(28),
      R => SR(0)
    );
\WB_MEM_Result_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(24),
      Q => Q(27),
      R => SR(0)
    );
\WB_MEM_Result_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(23),
      Q => Q(26),
      R => SR(0)
    );
\WB_MEM_Result_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(22),
      Q => Q(25),
      R => SR(0)
    );
\WB_MEM_Result_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(21),
      Q => Q(24),
      R => SR(0)
    );
\WB_MEM_Result_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(20),
      Q => Q(23),
      R => SR(0)
    );
\WB_MEM_Result_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \WB_MEM_Result_reg[0]_0\,
      D => \^mem_fwd\(19),
      Q => Q(22),
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Operand_Select_gti is
  port (
    ex_load_alu_carry_reg : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \EX_Op1_reg[30]_0\ : out STD_LOGIC;
    \EX_Op1_reg[28]_0\ : out STD_LOGIC;
    S : out STD_LOGIC;
    \EX_Op2_reg[0]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    I0 : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    I2 : out STD_LOGIC;
    in0 : out STD_LOGIC;
    swap_result : out STD_LOGIC_VECTOR ( 23 downto 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 7 );
    \EX_Op3_reg[0]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \EX_Branch_CMP_Op1_reg[30]_0\ : out STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[0]_0\ : out STD_LOGIC_VECTOR ( 29 downto 0 );
    \Using_FPGA.Native_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \imm_reg_reg[0]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    of_op1_sel_spr : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 31 downto 0 );
    I1 : in STD_LOGIC;
    \EX_Op1_reg[1]_0\ : in STD_LOGIC;
    \EX_Op1_reg[2]_0\ : in STD_LOGIC;
    \EX_Op1_reg[3]_0\ : in STD_LOGIC;
    \EX_Op1_reg[4]_0\ : in STD_LOGIC;
    \EX_Op1_reg[5]_0\ : in STD_LOGIC;
    \EX_Op1_reg[6]_0\ : in STD_LOGIC;
    \EX_Op1_reg[7]_0\ : in STD_LOGIC;
    \EX_Op1_reg[8]_0\ : in STD_LOGIC;
    \EX_Op1_reg[9]_0\ : in STD_LOGIC;
    \EX_Op1_reg[10]_0\ : in STD_LOGIC;
    \EX_Op1_reg[11]_0\ : in STD_LOGIC;
    \EX_Op1_reg[12]_0\ : in STD_LOGIC;
    \EX_Op1_reg[13]_0\ : in STD_LOGIC;
    \EX_Op1_reg[14]_0\ : in STD_LOGIC;
    \EX_Op1_reg[15]_0\ : in STD_LOGIC;
    \EX_Op1_reg[16]_0\ : in STD_LOGIC;
    \EX_Op1_reg[17]_0\ : in STD_LOGIC;
    \EX_Op1_reg[18]_0\ : in STD_LOGIC;
    \EX_Op1_reg[19]_0\ : in STD_LOGIC;
    \EX_Op1_reg[20]_0\ : in STD_LOGIC;
    \EX_Op1_reg[21]_0\ : in STD_LOGIC;
    \EX_Op1_reg[22]_0\ : in STD_LOGIC;
    \EX_Op1_reg[23]_0\ : in STD_LOGIC;
    \EX_Op1_reg[24]_0\ : in STD_LOGIC;
    \EX_Op1_reg[25]_0\ : in STD_LOGIC;
    \EX_Op1_reg[26]_0\ : in STD_LOGIC;
    \EX_Op1_reg[27]_0\ : in STD_LOGIC;
    \EX_Op1_reg[28]_1\ : in STD_LOGIC;
    \EX_Op1_reg[29]_0\ : in STD_LOGIC;
    \EX_Op1_reg[30]_1\ : in STD_LOGIC;
    \EX_Op1_reg[31]_0\ : in STD_LOGIC;
    p_231_in : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    LO : in STD_LOGIC;
    \Using_FPGA.Native_3\ : in STD_LOGIC;
    \Using_FPGA.Native_4\ : in STD_LOGIC;
    ex_MSR_Load_ALU_C : in STD_LOGIC;
    \ex_swx_access__0\ : in STD_LOGIC;
    ex_MSR_Load_Shift_C : in STD_LOGIC;
    ex_MSR_Load_LWX_SWX_C : in STD_LOGIC;
    ex_move_to_MSR_instr : in STD_LOGIC;
    ex_MSR : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_5\ : in STD_LOGIC;
    \Using_FPGA.Native_6\ : in STD_LOGIC;
    ex_valid : in STD_LOGIC;
    ex_cmp_op : in STD_LOGIC;
    EX_ALU_Sel_Logic : in STD_LOGIC;
    ex_reverse_mem_access : in STD_LOGIC;
    ex_byte_access : in STD_LOGIC;
    ex_doublet_access : in STD_LOGIC;
    \Using_FPGA.Native_i_3__31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    of_imm_data : in STD_LOGIC_VECTOR ( 0 to 15 );
    Clk : in STD_LOGIC;
    \EX_Op3_reg[31]_0\ : in STD_LOGIC;
    \EX_Op2_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \EX_Op3_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Operand_Select_gti : entity is "Operand_Select_gti";
end design_1_microblaze_0_0_Operand_Select_gti;

architecture STRUCTURE of design_1_microblaze_0_0_Operand_Select_gti is
  signal \^ex_op2_reg[0]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^ex_op3_reg[0]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \Gen_Bit[31].MUXF7_I1_n_0\ : STD_LOGIC;
  signal O : STD_LOGIC;
  signal O0_out : STD_LOGIC;
  signal O10_out : STD_LOGIC;
  signal O11_out : STD_LOGIC;
  signal O12_out : STD_LOGIC;
  signal O13_out : STD_LOGIC;
  signal O14_out : STD_LOGIC;
  signal O15_out : STD_LOGIC;
  signal O16_out : STD_LOGIC;
  signal O17_out : STD_LOGIC;
  signal O18_out : STD_LOGIC;
  signal O19_out : STD_LOGIC;
  signal O1_out : STD_LOGIC;
  signal O20_out : STD_LOGIC;
  signal O21_out : STD_LOGIC;
  signal O22_out : STD_LOGIC;
  signal O23_out : STD_LOGIC;
  signal O24_out : STD_LOGIC;
  signal O25_out : STD_LOGIC;
  signal O26_out : STD_LOGIC;
  signal O27_out : STD_LOGIC;
  signal O28_out : STD_LOGIC;
  signal O29_out : STD_LOGIC;
  signal O2_out : STD_LOGIC;
  signal O3_out : STD_LOGIC;
  signal O4_out : STD_LOGIC;
  signal O5_out : STD_LOGIC;
  signal O6_out : STD_LOGIC;
  signal O7_out : STD_LOGIC;
  signal O8_out : STD_LOGIC;
  signal O9_out : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \Using_FPGA.Native_i_2__21_n_0\ : STD_LOGIC;
  signal \Using_FPGA.Native_i_3_n_0\ : STD_LOGIC;
  signal ex_branch_cmp_op1 : STD_LOGIC_VECTOR ( 30 to 31 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \Byte_Enable[0]_INST_0_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__51\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__54\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \mem_byte_selects[1]_i_1\ : label is "soft_lutpair1";
begin
  \EX_Op2_reg[0]_0\(31 downto 0) <= \^ex_op2_reg[0]_0\(31 downto 0);
  \EX_Op3_reg[0]_0\(31 downto 0) <= \^ex_op3_reg[0]_0\(31 downto 0);
  Q(31 downto 0) <= \^q\(31 downto 0);
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
\Byte_Enable[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000969600FFFFFF"
    )
        port map (
      I0 => \^ex_op2_reg[0]_0\(0),
      I1 => \^q\(0),
      I2 => ex_reverse_mem_access,
      I3 => ex_doublet_access,
      I4 => \^using_fpga.native_0\,
      I5 => ex_byte_access,
      O => \Using_FPGA.Native\(3)
    );
\Byte_Enable[0]_INST_0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696969"
    )
        port map (
      I0 => ex_reverse_mem_access,
      I1 => \^ex_op2_reg[0]_0\(1),
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => \^ex_op2_reg[0]_0\(0),
      O => \^using_fpga.native_0\
    );
\Byte_Enable[1]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000696900FFFFFF"
    )
        port map (
      I0 => \^ex_op2_reg[0]_0\(0),
      I1 => \^q\(0),
      I2 => ex_reverse_mem_access,
      I3 => ex_doublet_access,
      I4 => \^using_fpga.native_0\,
      I5 => ex_byte_access,
      O => \Using_FPGA.Native\(2)
    );
\Byte_Enable[2]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"96FF000096FF00FF"
    )
        port map (
      I0 => \^ex_op2_reg[0]_0\(0),
      I1 => \^q\(0),
      I2 => ex_reverse_mem_access,
      I3 => ex_byte_access,
      I4 => \^using_fpga.native_0\,
      I5 => ex_doublet_access,
      O => \Using_FPGA.Native\(1)
    );
\Byte_Enable[3]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69FF000069FF00FF"
    )
        port map (
      I0 => \^ex_op2_reg[0]_0\(0),
      I1 => \^q\(0),
      I2 => ex_reverse_mem_access,
      I3 => ex_byte_access,
      I4 => \^using_fpga.native_0\,
      I5 => ex_doublet_access,
      O => \Using_FPGA.Native\(0)
    );
\Data_Addr[30]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"E00E0EE00EE00EE0"
    )
        port map (
      I0 => ex_byte_access,
      I1 => ex_doublet_access,
      I2 => \^ex_op2_reg[0]_0\(1),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \^ex_op2_reg[0]_0\(0),
      O => \Using_FPGA.Native\(13)
    );
\Data_Addr[31]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"28"
    )
        port map (
      I0 => ex_byte_access,
      I1 => \^q\(0),
      I2 => \^ex_op2_reg[0]_0\(0),
      O => \Using_FPGA.Native\(12)
    );
\Data_Write[16]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(7),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(23),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(15),
      O => \Using_FPGA.Native\(11)
    );
\Data_Write[17]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(6),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(22),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(14),
      O => \Using_FPGA.Native\(10)
    );
\Data_Write[18]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(5),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(21),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(13),
      O => \Using_FPGA.Native\(9)
    );
\Data_Write[19]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(4),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(20),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(12),
      O => \Using_FPGA.Native\(8)
    );
\Data_Write[20]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(3),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(19),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(11),
      O => \Using_FPGA.Native\(7)
    );
\Data_Write[21]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(2),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(18),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(10),
      O => \Using_FPGA.Native\(6)
    );
\Data_Write[22]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(1),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(17),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(9),
      O => \Using_FPGA.Native\(5)
    );
\Data_Write[23]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \^ex_op3_reg[0]_0\(0),
      I1 => ex_byte_access,
      I2 => \^ex_op3_reg[0]_0\(16),
      I3 => ex_reverse_mem_access,
      I4 => \^ex_op3_reg[0]_0\(8),
      O => \Using_FPGA.Native\(4)
    );
\EX_Branch_CMP_Op1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(31),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(29),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(21),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(19),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(20),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(18),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(19),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(17),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(18),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(16),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(17),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(15),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(16),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(14),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(15),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(13),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(14),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(12),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(13),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(11),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(12),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(10),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(30),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(28),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(11),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(9),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(10),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(8),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(9),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(7),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(8),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(6),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(7),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(5),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(6),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(4),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(5),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(3),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(4),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(2),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(3),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(1),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(2),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(0),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(29),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(27),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(1),
      Q => ex_branch_cmp_op1(30),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(0),
      Q => ex_branch_cmp_op1(31),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(28),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(26),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(27),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(25),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(26),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(24),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(25),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(23),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(24),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(22),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(23),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(21),
      R => sync_reset
    );
\EX_Branch_CMP_Op1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => D(22),
      Q => \EX_Branch_CMP_Op1_reg[0]_0\(20),
      R => sync_reset
    );
\EX_Op1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O,
      Q => \^q\(31),
      R => sync_reset
    );
\EX_Op1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O20_out,
      Q => \^q\(21),
      R => sync_reset
    );
\EX_Op1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O19_out,
      Q => \^q\(20),
      R => sync_reset
    );
\EX_Op1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O18_out,
      Q => \^q\(19),
      R => sync_reset
    );
\EX_Op1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O17_out,
      Q => \^q\(18),
      R => sync_reset
    );
\EX_Op1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O16_out,
      Q => \^q\(17),
      R => sync_reset
    );
\EX_Op1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O15_out,
      Q => \^q\(16),
      R => sync_reset
    );
\EX_Op1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O14_out,
      Q => \^q\(15),
      R => sync_reset
    );
\EX_Op1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O13_out,
      Q => \^q\(14),
      R => sync_reset
    );
\EX_Op1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O12_out,
      Q => \^q\(13),
      R => sync_reset
    );
\EX_Op1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O11_out,
      Q => \^q\(12),
      R => sync_reset
    );
\EX_Op1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O29_out,
      Q => \^q\(30),
      R => sync_reset
    );
\EX_Op1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O10_out,
      Q => \^q\(11),
      R => sync_reset
    );
\EX_Op1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O9_out,
      Q => \^q\(10),
      R => sync_reset
    );
\EX_Op1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O8_out,
      Q => \^q\(9),
      R => sync_reset
    );
\EX_Op1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O7_out,
      Q => \^q\(8),
      R => sync_reset
    );
\EX_Op1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O6_out,
      Q => \^q\(7),
      R => sync_reset
    );
\EX_Op1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O5_out,
      Q => \^q\(6),
      R => sync_reset
    );
\EX_Op1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O4_out,
      Q => \^q\(5),
      R => sync_reset
    );
\EX_Op1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O3_out,
      Q => \^q\(4),
      R => sync_reset
    );
\EX_Op1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O2_out,
      Q => \^q\(3),
      R => sync_reset
    );
\EX_Op1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O1_out,
      Q => \^q\(2),
      R => sync_reset
    );
\EX_Op1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O28_out,
      Q => \^q\(29),
      R => sync_reset
    );
\EX_Op1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O0_out,
      Q => \^q\(1),
      R => sync_reset
    );
\EX_Op1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \Gen_Bit[31].MUXF7_I1_n_0\,
      Q => \^q\(0),
      R => sync_reset
    );
\EX_Op1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O27_out,
      Q => \^q\(28),
      R => sync_reset
    );
\EX_Op1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O26_out,
      Q => \^q\(27),
      R => sync_reset
    );
\EX_Op1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O25_out,
      Q => \^q\(26),
      R => sync_reset
    );
\EX_Op1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O24_out,
      Q => \^q\(25),
      R => sync_reset
    );
\EX_Op1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O23_out,
      Q => \^q\(24),
      R => sync_reset
    );
\EX_Op1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O22_out,
      Q => \^q\(23),
      R => sync_reset
    );
\EX_Op1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => O21_out,
      Q => \^q\(22),
      R => sync_reset
    );
\EX_Op2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(31),
      Q => \^ex_op2_reg[0]_0\(31),
      R => sync_reset
    );
\EX_Op2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(21),
      Q => \^ex_op2_reg[0]_0\(21),
      R => sync_reset
    );
\EX_Op2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(20),
      Q => \^ex_op2_reg[0]_0\(20),
      R => sync_reset
    );
\EX_Op2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(19),
      Q => \^ex_op2_reg[0]_0\(19),
      R => sync_reset
    );
\EX_Op2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(18),
      Q => \^ex_op2_reg[0]_0\(18),
      R => sync_reset
    );
\EX_Op2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(17),
      Q => \^ex_op2_reg[0]_0\(17),
      R => sync_reset
    );
\EX_Op2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(16),
      Q => \^ex_op2_reg[0]_0\(16),
      R => sync_reset
    );
\EX_Op2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(15),
      Q => \^ex_op2_reg[0]_0\(15),
      R => sync_reset
    );
\EX_Op2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(14),
      Q => \^ex_op2_reg[0]_0\(14),
      R => sync_reset
    );
\EX_Op2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(13),
      Q => \^ex_op2_reg[0]_0\(13),
      R => sync_reset
    );
\EX_Op2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(12),
      Q => \^ex_op2_reg[0]_0\(12),
      R => sync_reset
    );
\EX_Op2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(30),
      Q => \^ex_op2_reg[0]_0\(30),
      R => sync_reset
    );
\EX_Op2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(11),
      Q => \^ex_op2_reg[0]_0\(11),
      R => sync_reset
    );
\EX_Op2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(10),
      Q => \^ex_op2_reg[0]_0\(10),
      R => sync_reset
    );
\EX_Op2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(9),
      Q => \^ex_op2_reg[0]_0\(9),
      R => sync_reset
    );
\EX_Op2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(8),
      Q => \^ex_op2_reg[0]_0\(8),
      R => sync_reset
    );
\EX_Op2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(7),
      Q => \^ex_op2_reg[0]_0\(7),
      R => sync_reset
    );
\EX_Op2_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(6),
      Q => \^ex_op2_reg[0]_0\(6),
      R => sync_reset
    );
\EX_Op2_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(5),
      Q => \^ex_op2_reg[0]_0\(5),
      R => sync_reset
    );
\EX_Op2_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(4),
      Q => \^ex_op2_reg[0]_0\(4),
      R => sync_reset
    );
\EX_Op2_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(3),
      Q => \^ex_op2_reg[0]_0\(3),
      R => sync_reset
    );
\EX_Op2_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(2),
      Q => \^ex_op2_reg[0]_0\(2),
      R => sync_reset
    );
\EX_Op2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(29),
      Q => \^ex_op2_reg[0]_0\(29),
      R => sync_reset
    );
\EX_Op2_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(1),
      Q => \^ex_op2_reg[0]_0\(1),
      R => sync_reset
    );
\EX_Op2_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(0),
      Q => \^ex_op2_reg[0]_0\(0),
      R => sync_reset
    );
\EX_Op2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(28),
      Q => \^ex_op2_reg[0]_0\(28),
      R => sync_reset
    );
\EX_Op2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(27),
      Q => \^ex_op2_reg[0]_0\(27),
      R => sync_reset
    );
\EX_Op2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(26),
      Q => \^ex_op2_reg[0]_0\(26),
      R => sync_reset
    );
\EX_Op2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(25),
      Q => \^ex_op2_reg[0]_0\(25),
      R => sync_reset
    );
\EX_Op2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(24),
      Q => \^ex_op2_reg[0]_0\(24),
      R => sync_reset
    );
\EX_Op2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(23),
      Q => \^ex_op2_reg[0]_0\(23),
      R => sync_reset
    );
\EX_Op2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op2_reg[0]_1\(22),
      Q => \^ex_op2_reg[0]_0\(22),
      R => sync_reset
    );
\EX_Op3_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(31),
      Q => \^ex_op3_reg[0]_0\(31),
      R => sync_reset
    );
\EX_Op3_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(21),
      Q => \^ex_op3_reg[0]_0\(21),
      R => sync_reset
    );
\EX_Op3_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(20),
      Q => \^ex_op3_reg[0]_0\(20),
      R => sync_reset
    );
\EX_Op3_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(19),
      Q => \^ex_op3_reg[0]_0\(19),
      R => sync_reset
    );
\EX_Op3_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(18),
      Q => \^ex_op3_reg[0]_0\(18),
      R => sync_reset
    );
\EX_Op3_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(17),
      Q => \^ex_op3_reg[0]_0\(17),
      R => sync_reset
    );
\EX_Op3_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(16),
      Q => \^ex_op3_reg[0]_0\(16),
      R => sync_reset
    );
\EX_Op3_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(15),
      Q => \^ex_op3_reg[0]_0\(15),
      R => sync_reset
    );
\EX_Op3_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(14),
      Q => \^ex_op3_reg[0]_0\(14),
      R => sync_reset
    );
\EX_Op3_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(13),
      Q => \^ex_op3_reg[0]_0\(13),
      R => sync_reset
    );
\EX_Op3_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(12),
      Q => \^ex_op3_reg[0]_0\(12),
      R => sync_reset
    );
\EX_Op3_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(30),
      Q => \^ex_op3_reg[0]_0\(30),
      R => sync_reset
    );
\EX_Op3_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(11),
      Q => \^ex_op3_reg[0]_0\(11),
      R => sync_reset
    );
\EX_Op3_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(10),
      Q => \^ex_op3_reg[0]_0\(10),
      R => sync_reset
    );
\EX_Op3_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(9),
      Q => \^ex_op3_reg[0]_0\(9),
      R => sync_reset
    );
\EX_Op3_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(8),
      Q => \^ex_op3_reg[0]_0\(8),
      R => sync_reset
    );
\EX_Op3_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(7),
      Q => \^ex_op3_reg[0]_0\(7),
      R => sync_reset
    );
\EX_Op3_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(6),
      Q => \^ex_op3_reg[0]_0\(6),
      R => sync_reset
    );
\EX_Op3_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(5),
      Q => \^ex_op3_reg[0]_0\(5),
      R => sync_reset
    );
\EX_Op3_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(4),
      Q => \^ex_op3_reg[0]_0\(4),
      R => sync_reset
    );
\EX_Op3_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(3),
      Q => \^ex_op3_reg[0]_0\(3),
      R => sync_reset
    );
\EX_Op3_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(2),
      Q => \^ex_op3_reg[0]_0\(2),
      R => sync_reset
    );
\EX_Op3_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(29),
      Q => \^ex_op3_reg[0]_0\(29),
      R => sync_reset
    );
\EX_Op3_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(1),
      Q => \^ex_op3_reg[0]_0\(1),
      R => sync_reset
    );
\EX_Op3_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(0),
      Q => \^ex_op3_reg[0]_0\(0),
      R => sync_reset
    );
\EX_Op3_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(28),
      Q => \^ex_op3_reg[0]_0\(28),
      R => sync_reset
    );
\EX_Op3_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(27),
      Q => \^ex_op3_reg[0]_0\(27),
      R => sync_reset
    );
\EX_Op3_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(26),
      Q => \^ex_op3_reg[0]_0\(26),
      R => sync_reset
    );
\EX_Op3_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(25),
      Q => \^ex_op3_reg[0]_0\(25),
      R => sync_reset
    );
\EX_Op3_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(24),
      Q => \^ex_op3_reg[0]_0\(24),
      R => sync_reset
    );
\EX_Op3_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(23),
      Q => \^ex_op3_reg[0]_0\(23),
      R => sync_reset
    );
\EX_Op3_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \EX_Op3_reg[31]_0\,
      D => \EX_Op3_reg[0]_1\(22),
      Q => \^ex_op3_reg[0]_0\(22),
      R => sync_reset
    );
\Gen_Bit[0].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_424
     port map (
      D(0) => O,
      \EX_Op1_reg[0]\(0) => D(31),
      I1 => I1,
      Q(1) => \^q\(15),
      Q(0) => \^q\(7),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(0)
    );
\Gen_Bit[10].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_425
     port map (
      D(0) => O20_out,
      \EX_Op1_reg[10]\(0) => D(21),
      \EX_Op1_reg[10]_0\ => \EX_Op1_reg[10]_0\,
      Q(1) => \^q\(13),
      Q(0) => \^q\(5),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(21)
    );
\Gen_Bit[11].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_426
     port map (
      D(0) => O19_out,
      \EX_Op1_reg[11]\(0) => D(20),
      \EX_Op1_reg[11]_0\ => \EX_Op1_reg[11]_0\,
      Q(1) => \^q\(12),
      Q(0) => \^q\(4),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(20)
    );
\Gen_Bit[12].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_427
     port map (
      D(0) => O18_out,
      \EX_Op1_reg[12]\(0) => D(19),
      \EX_Op1_reg[12]_0\ => \EX_Op1_reg[12]_0\,
      Q(1) => \^q\(11),
      Q(0) => \^q\(3),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(19)
    );
\Gen_Bit[13].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_428
     port map (
      D(0) => O17_out,
      \EX_Op1_reg[13]\(0) => D(18),
      \EX_Op1_reg[13]_0\ => \EX_Op1_reg[13]_0\,
      Q(1) => \^q\(10),
      Q(0) => \^q\(2),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(18)
    );
\Gen_Bit[14].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_429
     port map (
      D(0) => O16_out,
      \EX_Op1_reg[14]\(0) => D(17),
      \EX_Op1_reg[14]_0\ => \EX_Op1_reg[14]_0\,
      Q(1) => \^q\(9),
      Q(0) => \^q\(1),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(17)
    );
\Gen_Bit[15].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_430
     port map (
      D(0) => O15_out,
      \EX_Op1_reg[15]\(0) => D(16),
      \EX_Op1_reg[15]_0\ => \EX_Op1_reg[15]_0\,
      Q(1) => \^q\(8),
      Q(0) => \^q\(0),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(16)
    );
\Gen_Bit[16].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_431
     port map (
      D(0) => O14_out,
      \EX_Op1_reg[16]\(0) => D(15),
      \EX_Op1_reg[16]_0\ => \EX_Op1_reg[16]_0\,
      Q(1) => \^q\(31),
      Q(0) => \^q\(23),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(15)
    );
\Gen_Bit[17].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_432
     port map (
      D(0) => O13_out,
      \EX_Op1_reg[17]\(0) => D(14),
      \EX_Op1_reg[17]_0\ => \EX_Op1_reg[17]_0\,
      Q(1) => \^q\(30),
      Q(0) => \^q\(22),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(14)
    );
\Gen_Bit[18].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_433
     port map (
      D(0) => O12_out,
      \EX_Op1_reg[18]\(0) => D(13),
      \EX_Op1_reg[18]_0\ => \EX_Op1_reg[18]_0\,
      Q(1) => \^q\(29),
      Q(0) => \^q\(21),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(13)
    );
\Gen_Bit[19].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_434
     port map (
      D(0) => O11_out,
      \EX_Op1_reg[19]\(0) => D(12),
      \EX_Op1_reg[19]_0\ => \EX_Op1_reg[19]_0\,
      Q(1) => \^q\(28),
      Q(0) => \^q\(20),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(12)
    );
\Gen_Bit[1].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_435
     port map (
      D(0) => O29_out,
      \EX_Op1_reg[1]\(0) => D(30),
      \EX_Op1_reg[1]_0\ => \EX_Op1_reg[1]_0\,
      Q(1) => \^q\(14),
      Q(0) => \^q\(6),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(1)
    );
\Gen_Bit[20].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_436
     port map (
      D(0) => O10_out,
      \EX_Op1_reg[20]\(0) => D(11),
      \EX_Op1_reg[20]_0\ => \EX_Op1_reg[20]_0\,
      Q(1) => \^q\(27),
      Q(0) => \^q\(19),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(11)
    );
\Gen_Bit[21].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_437
     port map (
      D(0) => O9_out,
      \EX_Op1_reg[21]\(0) => D(10),
      \EX_Op1_reg[21]_0\ => \EX_Op1_reg[21]_0\,
      Q(1) => \^q\(26),
      Q(0) => \^q\(18),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(10)
    );
\Gen_Bit[22].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_438
     port map (
      D(0) => O8_out,
      \EX_Op1_reg[22]\(0) => D(9),
      \EX_Op1_reg[22]_0\ => \EX_Op1_reg[22]_0\,
      Q(1) => \^q\(25),
      Q(0) => \^q\(17),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(9)
    );
\Gen_Bit[23].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_439
     port map (
      D(0) => O7_out,
      \EX_Op1_reg[23]\(0) => D(8),
      \EX_Op1_reg[23]_0\ => \EX_Op1_reg[23]_0\,
      Q(1) => \^q\(24),
      Q(0) => \^q\(16),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(8)
    );
\Gen_Bit[24].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_440
     port map (
      D(0) => O6_out,
      \EX_Op1_reg[24]\(0) => D(7),
      \EX_Op1_reg[24]_0\ => \EX_Op1_reg[24]_0\,
      Q(1) => \^q\(31),
      Q(0) => \^q\(23),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(7)
    );
\Gen_Bit[25].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_441
     port map (
      D(0) => O5_out,
      \EX_Op1_reg[25]\(0) => D(6),
      \EX_Op1_reg[25]_0\ => \EX_Op1_reg[25]_0\,
      Q(1) => \^q\(30),
      Q(0) => \^q\(22),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(6)
    );
\Gen_Bit[26].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_442
     port map (
      D(0) => O4_out,
      \EX_Op1_reg[26]\(0) => D(5),
      \EX_Op1_reg[26]_0\ => \EX_Op1_reg[26]_0\,
      Q(1) => \^q\(29),
      Q(0) => \^q\(21),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(5)
    );
\Gen_Bit[27].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_443
     port map (
      D(0) => O3_out,
      \EX_Op1_reg[27]\(0) => D(4),
      \EX_Op1_reg[27]_0\ => \EX_Op1_reg[27]_0\,
      Q(1) => \^q\(28),
      Q(0) => \^q\(20),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(4)
    );
\Gen_Bit[28].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_444
     port map (
      D(0) => O2_out,
      \EX_Op1_reg[28]\(0) => D(3),
      \EX_Op1_reg[28]_0\ => \EX_Op1_reg[28]_1\,
      Q(1) => \^q\(27),
      Q(0) => \^q\(19),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(3)
    );
\Gen_Bit[29].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_445
     port map (
      D(0) => O1_out,
      \EX_Op1_reg[29]\(0) => D(2),
      \EX_Op1_reg[29]_0\ => \EX_Op1_reg[29]_0\,
      Q(1) => \^q\(26),
      Q(0) => \^q\(18),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(2)
    );
\Gen_Bit[2].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_446
     port map (
      D(0) => O28_out,
      \EX_Op1_reg[2]\(0) => D(29),
      \EX_Op1_reg[2]_0\ => \EX_Op1_reg[2]_0\,
      Q(1) => \^q\(13),
      Q(0) => \^q\(5),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(2)
    );
\Gen_Bit[30].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_447
     port map (
      D(0) => O0_out,
      \EX_Op1_reg[30]\(0) => D(1),
      \EX_Op1_reg[30]_0\ => \EX_Op1_reg[30]_1\,
      Q(1) => \^q\(25),
      Q(0) => \^q\(17),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(1)
    );
\Gen_Bit[31].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_448
     port map (
      D(0) => \Gen_Bit[31].MUXF7_I1_n_0\,
      \EX_Op1_reg[31]\(0) => D(0),
      \EX_Op1_reg[31]_0\ => \EX_Op1_reg[31]_0\,
      Q(1) => \^q\(24),
      Q(0) => \^q\(16),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(0)
    );
\Gen_Bit[3].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_449
     port map (
      D(0) => O27_out,
      \EX_Op1_reg[3]\(0) => D(28),
      \EX_Op1_reg[3]_0\ => \EX_Op1_reg[3]_0\,
      Q(1) => \^q\(12),
      Q(0) => \^q\(4),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(3)
    );
\Gen_Bit[4].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_450
     port map (
      D(0) => O26_out,
      \EX_Op1_reg[4]\(0) => D(27),
      \EX_Op1_reg[4]_0\ => \EX_Op1_reg[4]_0\,
      Q(1) => \^q\(11),
      Q(0) => \^q\(3),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(4)
    );
\Gen_Bit[5].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_451
     port map (
      D(0) => O25_out,
      \EX_Op1_reg[5]\(0) => D(26),
      \EX_Op1_reg[5]_0\ => \EX_Op1_reg[5]_0\,
      Q(1) => \^q\(10),
      Q(0) => \^q\(2),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(5)
    );
\Gen_Bit[6].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_452
     port map (
      D(0) => O24_out,
      \EX_Op1_reg[6]\(0) => D(25),
      \EX_Op1_reg[6]_0\ => \EX_Op1_reg[6]_0\,
      Q(1) => \^q\(9),
      Q(0) => \^q\(1),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(6)
    );
\Gen_Bit[7].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_453
     port map (
      D(0) => O23_out,
      \EX_Op1_reg[7]\(0) => D(24),
      \EX_Op1_reg[7]_0\ => \EX_Op1_reg[7]_0\,
      Q(1) => \^q\(8),
      Q(0) => \^q\(0),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result_reg(0) => swap_result_reg(7)
    );
\Gen_Bit[8].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_454
     port map (
      D(0) => O22_out,
      \EX_Op1_reg[8]\(0) => D(23),
      \EX_Op1_reg[8]_0\ => \EX_Op1_reg[8]_0\,
      Q(1) => \^q\(15),
      Q(0) => \^q\(7),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(23)
    );
\Gen_Bit[9].MUXF7_I1\: entity work.design_1_microblaze_0_0_MB_MUXF7_455
     port map (
      D(0) => O21_out,
      \EX_Op1_reg[9]\(0) => D(22),
      \EX_Op1_reg[9]_0\ => \EX_Op1_reg[9]_0\,
      Q(1) => \^q\(14),
      Q(0) => \^q\(6),
      ex_swap_byte_instr => ex_swap_byte_instr,
      of_op1_sel_spr => of_op1_sel_spr,
      swap_result(0) => swap_result(22)
    );
\Using_FPGA.Native_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAAAFFFFEAAA0000"
    )
        port map (
      I0 => \Using_FPGA.Native_i_2__21_n_0\,
      I1 => p_231_in,
      I2 => \Using_FPGA.Native_2\,
      I3 => LO,
      I4 => \Using_FPGA.Native_3\,
      I5 => \Using_FPGA.Native_4\,
      O => ex_load_alu_carry_reg
    );
\Using_FPGA.Native_i_1__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BFFF8000"
    )
        port map (
      I0 => \^q\(1),
      I1 => p_231_in,
      I2 => ex_move_to_MSR_instr,
      I3 => \Using_FPGA.Native_3\,
      I4 => ex_MSR(0),
      O => \EX_Op1_reg[30]_0\
    );
\Using_FPGA.Native_i_1__50\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"009F"
    )
        port map (
      I0 => \^ex_op2_reg[0]_0\(31),
      I1 => \^q\(31),
      I2 => ex_cmp_op,
      I3 => EX_ALU_Sel_Logic,
      O => S
    );
\Using_FPGA.Native_i_1__51\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^ex_op2_reg[0]_0\(31),
      I1 => EX_ALU_Sel_Logic,
      O => I0
    );
\Using_FPGA.Native_i_1__54\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"9F"
    )
        port map (
      I0 => \^ex_op2_reg[0]_0\(31),
      I1 => \^q\(31),
      I2 => ex_cmp_op,
      O => I2
    );
\Using_FPGA.Native_i_1__94\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ex_branch_cmp_op1(30),
      I1 => ex_branch_cmp_op1(31),
      O => \EX_Branch_CMP_Op1_reg[30]_0\
    );
\Using_FPGA.Native_i_2__21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3030003330302222"
    )
        port map (
      I0 => \Using_FPGA.Native_i_3_n_0\,
      I1 => ex_MSR_Load_ALU_C,
      I2 => \^q\(0),
      I3 => \ex_swx_access__0\,
      I4 => ex_MSR_Load_Shift_C,
      I5 => ex_MSR_Load_LWX_SWX_C,
      O => \Using_FPGA.Native_i_2__21_n_0\
    );
\Using_FPGA.Native_i_2__22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEFFFFFFA2000000"
    )
        port map (
      I0 => \^q\(3),
      I1 => \Using_FPGA.Native_5\,
      I2 => \Using_FPGA.Native_6\,
      I3 => ex_valid,
      I4 => ex_move_to_MSR_instr,
      I5 => ex_MSR(1),
      O => \EX_Op1_reg[28]_0\
    );
\Using_FPGA.Native_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AEFFFFFFA2000000"
    )
        port map (
      I0 => \^q\(2),
      I1 => \Using_FPGA.Native_5\,
      I2 => \Using_FPGA.Native_6\,
      I3 => ex_valid,
      I4 => ex_move_to_MSR_instr,
      I5 => \Using_FPGA.Native_4\,
      O => \Using_FPGA.Native_i_3_n_0\
    );
\imm_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(0),
      Q => \imm_reg_reg[0]_0\(15),
      R => sync_reset
    );
\imm_reg_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(10),
      Q => \imm_reg_reg[0]_0\(5),
      R => sync_reset
    );
\imm_reg_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(11),
      Q => \imm_reg_reg[0]_0\(4),
      R => sync_reset
    );
\imm_reg_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(12),
      Q => \imm_reg_reg[0]_0\(3),
      R => sync_reset
    );
\imm_reg_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(13),
      Q => \imm_reg_reg[0]_0\(2),
      R => sync_reset
    );
\imm_reg_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(14),
      Q => \imm_reg_reg[0]_0\(1),
      R => sync_reset
    );
\imm_reg_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(15),
      Q => \imm_reg_reg[0]_0\(0),
      R => sync_reset
    );
\imm_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(1),
      Q => \imm_reg_reg[0]_0\(14),
      R => sync_reset
    );
\imm_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(2),
      Q => \imm_reg_reg[0]_0\(13),
      R => sync_reset
    );
\imm_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(3),
      Q => \imm_reg_reg[0]_0\(12),
      R => sync_reset
    );
\imm_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(4),
      Q => \imm_reg_reg[0]_0\(11),
      R => sync_reset
    );
\imm_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(5),
      Q => \imm_reg_reg[0]_0\(10),
      R => sync_reset
    );
\imm_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(6),
      Q => \imm_reg_reg[0]_0\(9),
      R => sync_reset
    );
\imm_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(7),
      Q => \imm_reg_reg[0]_0\(8),
      R => sync_reset
    );
\imm_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(8),
      Q => \imm_reg_reg[0]_0\(7),
      R => sync_reset
    );
\imm_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => E(0),
      D => of_imm_data(9),
      Q => \imm_reg_reg[0]_0\(6),
      R => sync_reset
    );
\mem_byte_selects[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => ex_reverse_mem_access,
      I1 => \^q\(0),
      I2 => \^ex_op2_reg[0]_0\(0),
      O => \Using_FPGA.Native_1\(0)
    );
sign_doublet_inferred_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => \^q\(7),
      I1 => \Using_FPGA.Native_i_3__31\(0),
      I2 => \^q\(15),
      I3 => \Using_FPGA.Native_i_3__31\(1),
      O => in0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_PC_Module_gti is
  port (
    D : out STD_LOGIC_VECTOR ( 31 downto 0 );
    O56_out : out STD_LOGIC;
    IB_Ready : out STD_LOGIC;
    \if_pc_reg[30]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    O : out STD_LOGIC;
    \if_pc_reg[28]_0\ : out STD_LOGIC;
    \if_pc_reg[27]_0\ : out STD_LOGIC;
    \if_pc_reg[26]_0\ : out STD_LOGIC;
    \if_pc_reg[25]_0\ : out STD_LOGIC;
    \if_pc_reg[24]_0\ : out STD_LOGIC;
    \if_pc_reg[23]_0\ : out STD_LOGIC;
    \if_pc_reg[22]_0\ : out STD_LOGIC;
    \if_pc_reg[21]_0\ : out STD_LOGIC;
    \if_pc_reg[20]_0\ : out STD_LOGIC;
    \if_pc_reg[19]_0\ : out STD_LOGIC;
    \if_pc_reg[18]_0\ : out STD_LOGIC;
    \if_pc_reg[17]_0\ : out STD_LOGIC;
    \if_pc_reg[16]_0\ : out STD_LOGIC;
    \if_pc_reg[15]_0\ : out STD_LOGIC;
    \if_pc_reg[14]_0\ : out STD_LOGIC;
    \if_pc_reg[13]_0\ : out STD_LOGIC;
    \if_pc_reg[12]_0\ : out STD_LOGIC;
    \if_pc_reg[11]_0\ : out STD_LOGIC;
    \if_pc_reg[10]_0\ : out STD_LOGIC;
    \if_pc_reg[9]_0\ : out STD_LOGIC;
    \if_pc_reg[8]_0\ : out STD_LOGIC;
    \if_pc_reg[7]_0\ : out STD_LOGIC;
    \if_pc_reg[6]_0\ : out STD_LOGIC;
    \if_pc_reg[5]_0\ : out STD_LOGIC;
    \if_pc_reg[4]_0\ : out STD_LOGIC;
    \if_pc_reg[3]_0\ : out STD_LOGIC;
    \if_pc_reg[2]_0\ : out STD_LOGIC;
    \if_pc_reg[1]_0\ : out STD_LOGIC;
    \mem_pc_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \ex_pc_i_reg[31]_0\ : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_jump_nodelay_reg : in STD_LOGIC;
    ex_jump_nodelay_reg_0 : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    IReady : in STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    if_sel_input : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    CI : in STD_LOGIC;
    if_pre_buffer_addr : in STD_LOGIC_VECTOR ( 0 to 0 );
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \if_pc_reg[0]_1\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : in STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : in STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : in STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_PC_Module_gti : entity is "PC_Module_gti";
end design_1_microblaze_0_0_PC_Module_gti;

architecture STRUCTURE of design_1_microblaze_0_0_PC_Module_gti is
  signal \^d\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal I0 : STD_LOGIC;
  signal I0101_out : STD_LOGIC;
  signal I0105_out : STD_LOGIC;
  signal I0109_out : STD_LOGIC;
  signal I0113_out : STD_LOGIC;
  signal I0117_out : STD_LOGIC;
  signal I0121_out : STD_LOGIC;
  signal I0125_out : STD_LOGIC;
  signal I013_out : STD_LOGIC;
  signal I017_out : STD_LOGIC;
  signal I021_out : STD_LOGIC;
  signal I025_out : STD_LOGIC;
  signal I029_out : STD_LOGIC;
  signal I033_out : STD_LOGIC;
  signal I037_out : STD_LOGIC;
  signal I041_out : STD_LOGIC;
  signal I045_out : STD_LOGIC;
  signal I049_out : STD_LOGIC;
  signal I053_out : STD_LOGIC;
  signal I057_out : STD_LOGIC;
  signal I05_out : STD_LOGIC;
  signal I061_out : STD_LOGIC;
  signal I065_out : STD_LOGIC;
  signal I069_out : STD_LOGIC;
  signal I073_out : STD_LOGIC;
  signal I077_out : STD_LOGIC;
  signal I081_out : STD_LOGIC;
  signal I085_out : STD_LOGIC;
  signal I089_out : STD_LOGIC;
  signal I093_out : STD_LOGIC;
  signal I097_out : STD_LOGIC;
  signal I09_out : STD_LOGIC;
  signal \PC_Buffer_reg[3][31]_srl4_n_0\ : STD_LOGIC;
  signal S : STD_LOGIC;
  signal S102_in : STD_LOGIC;
  signal S107_in : STD_LOGIC;
  signal S112_in : STD_LOGIC;
  signal S117_in : STD_LOGIC;
  signal S122_in : STD_LOGIC;
  signal S127_in : STD_LOGIC;
  signal S12_in : STD_LOGIC;
  signal S132_in : STD_LOGIC;
  signal S137_in : STD_LOGIC;
  signal S142_in : STD_LOGIC;
  signal S147_in : STD_LOGIC;
  signal S152_in : STD_LOGIC;
  signal S17_in : STD_LOGIC;
  signal S22_in : STD_LOGIC;
  signal S27_in : STD_LOGIC;
  signal S32_in : STD_LOGIC;
  signal S37_in : STD_LOGIC;
  signal S42_in : STD_LOGIC;
  signal S47_in : STD_LOGIC;
  signal S52_in : STD_LOGIC;
  signal S57_in : STD_LOGIC;
  signal S62_in : STD_LOGIC;
  signal S67_in : STD_LOGIC;
  signal S72_in : STD_LOGIC;
  signal S77_in : STD_LOGIC;
  signal S82_in : STD_LOGIC;
  signal S87_in : STD_LOGIC;
  signal S92_in : STD_LOGIC;
  signal S97_in : STD_LOGIC;
  signal ex_pc : STD_LOGIC_VECTOR ( 0 to 31 );
  signal if_pc_carry : STD_LOGIC_VECTOR ( 29 downto 1 );
  signal \^if_pc_reg[30]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^lopt_10\ : STD_LOGIC;
  signal lopt_100 : STD_LOGIC;
  signal lopt_101 : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal lopt_20 : STD_LOGIC;
  signal lopt_21 : STD_LOGIC;
  signal lopt_22 : STD_LOGIC;
  signal lopt_23 : STD_LOGIC;
  signal lopt_24 : STD_LOGIC;
  signal lopt_25 : STD_LOGIC;
  signal lopt_26 : STD_LOGIC;
  signal lopt_27 : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal lopt_29 : STD_LOGIC;
  signal \^lopt_3\ : STD_LOGIC;
  signal lopt_30 : STD_LOGIC;
  signal lopt_31 : STD_LOGIC;
  signal lopt_32 : STD_LOGIC;
  signal lopt_33 : STD_LOGIC;
  signal lopt_34 : STD_LOGIC;
  signal lopt_35 : STD_LOGIC;
  signal lopt_36 : STD_LOGIC;
  signal lopt_37 : STD_LOGIC;
  signal lopt_38 : STD_LOGIC;
  signal lopt_39 : STD_LOGIC;
  signal \^lopt_4\ : STD_LOGIC;
  signal lopt_40 : STD_LOGIC;
  signal lopt_41 : STD_LOGIC;
  signal lopt_42 : STD_LOGIC;
  signal lopt_43 : STD_LOGIC;
  signal lopt_44 : STD_LOGIC;
  signal lopt_45 : STD_LOGIC;
  signal lopt_46 : STD_LOGIC;
  signal lopt_47 : STD_LOGIC;
  signal lopt_48 : STD_LOGIC;
  signal lopt_49 : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal lopt_50 : STD_LOGIC;
  signal lopt_51 : STD_LOGIC;
  signal lopt_52 : STD_LOGIC;
  signal lopt_53 : STD_LOGIC;
  signal lopt_54 : STD_LOGIC;
  signal lopt_55 : STD_LOGIC;
  signal lopt_56 : STD_LOGIC;
  signal lopt_57 : STD_LOGIC;
  signal lopt_58 : STD_LOGIC;
  signal lopt_59 : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal lopt_60 : STD_LOGIC;
  signal lopt_61 : STD_LOGIC;
  signal lopt_62 : STD_LOGIC;
  signal lopt_63 : STD_LOGIC;
  signal lopt_64 : STD_LOGIC;
  signal lopt_65 : STD_LOGIC;
  signal lopt_66 : STD_LOGIC;
  signal lopt_67 : STD_LOGIC;
  signal lopt_68 : STD_LOGIC;
  signal lopt_69 : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal lopt_70 : STD_LOGIC;
  signal lopt_71 : STD_LOGIC;
  signal lopt_72 : STD_LOGIC;
  signal lopt_73 : STD_LOGIC;
  signal lopt_74 : STD_LOGIC;
  signal lopt_75 : STD_LOGIC;
  signal lopt_76 : STD_LOGIC;
  signal lopt_77 : STD_LOGIC;
  signal lopt_78 : STD_LOGIC;
  signal lopt_79 : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal lopt_80 : STD_LOGIC;
  signal lopt_81 : STD_LOGIC;
  signal lopt_82 : STD_LOGIC;
  signal lopt_83 : STD_LOGIC;
  signal lopt_84 : STD_LOGIC;
  signal lopt_85 : STD_LOGIC;
  signal lopt_86 : STD_LOGIC;
  signal lopt_87 : STD_LOGIC;
  signal lopt_88 : STD_LOGIC;
  signal lopt_89 : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal lopt_90 : STD_LOGIC;
  signal lopt_91 : STD_LOGIC;
  signal lopt_92 : STD_LOGIC;
  signal lopt_93 : STD_LOGIC;
  signal lopt_94 : STD_LOGIC;
  signal lopt_95 : STD_LOGIC;
  signal lopt_96 : STD_LOGIC;
  signal lopt_97 : STD_LOGIC;
  signal lopt_98 : STD_LOGIC;
  signal lopt_99 : STD_LOGIC;
  signal of_pc_ii_0 : STD_LOGIC;
  signal of_pc_ii_1 : STD_LOGIC;
  signal of_pc_ii_10 : STD_LOGIC;
  signal of_pc_ii_11 : STD_LOGIC;
  signal of_pc_ii_12 : STD_LOGIC;
  signal of_pc_ii_13 : STD_LOGIC;
  signal of_pc_ii_14 : STD_LOGIC;
  signal of_pc_ii_15 : STD_LOGIC;
  signal of_pc_ii_16 : STD_LOGIC;
  signal of_pc_ii_17 : STD_LOGIC;
  signal of_pc_ii_18 : STD_LOGIC;
  signal of_pc_ii_19 : STD_LOGIC;
  signal of_pc_ii_2 : STD_LOGIC;
  signal of_pc_ii_20 : STD_LOGIC;
  signal of_pc_ii_21 : STD_LOGIC;
  signal of_pc_ii_22 : STD_LOGIC;
  signal of_pc_ii_23 : STD_LOGIC;
  signal of_pc_ii_24 : STD_LOGIC;
  signal of_pc_ii_25 : STD_LOGIC;
  signal of_pc_ii_26 : STD_LOGIC;
  signal of_pc_ii_27 : STD_LOGIC;
  signal of_pc_ii_28 : STD_LOGIC;
  signal of_pc_ii_29 : STD_LOGIC;
  signal of_pc_ii_3 : STD_LOGIC;
  signal of_pc_ii_30 : STD_LOGIC;
  signal of_pc_ii_31 : STD_LOGIC;
  signal of_pc_ii_4 : STD_LOGIC;
  signal of_pc_ii_5 : STD_LOGIC;
  signal of_pc_ii_6 : STD_LOGIC;
  signal of_pc_ii_7 : STD_LOGIC;
  signal of_pc_ii_8 : STD_LOGIC;
  signal of_pc_ii_9 : STD_LOGIC;
  signal p_1_in103_in : STD_LOGIC;
  signal p_1_in108_in : STD_LOGIC;
  signal p_1_in113_in : STD_LOGIC;
  signal p_1_in118_in : STD_LOGIC;
  signal p_1_in123_in : STD_LOGIC;
  signal p_1_in128_in : STD_LOGIC;
  signal p_1_in133_in : STD_LOGIC;
  signal p_1_in138_in : STD_LOGIC;
  signal p_1_in13_in : STD_LOGIC;
  signal p_1_in143_in : STD_LOGIC;
  signal p_1_in148_in : STD_LOGIC;
  signal p_1_in153_in : STD_LOGIC;
  signal p_1_in18_in : STD_LOGIC;
  signal p_1_in23_in : STD_LOGIC;
  signal p_1_in28_in : STD_LOGIC;
  signal p_1_in33_in : STD_LOGIC;
  signal p_1_in38_in : STD_LOGIC;
  signal p_1_in43_in : STD_LOGIC;
  signal p_1_in48_in : STD_LOGIC;
  signal p_1_in53_in : STD_LOGIC;
  signal p_1_in58_in : STD_LOGIC;
  signal p_1_in63_in : STD_LOGIC;
  signal p_1_in68_in : STD_LOGIC;
  signal p_1_in73_in : STD_LOGIC;
  signal p_1_in78_in : STD_LOGIC;
  signal p_1_in83_in : STD_LOGIC;
  signal p_1_in88_in : STD_LOGIC;
  signal p_1_in8_in : STD_LOGIC;
  signal p_1_in93_in : STD_LOGIC;
  signal p_1_in98_in : STD_LOGIC;
  signal p_2_in4_in : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \PC_Buffer_reg[3][0]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name : string;
  attribute srl_name of \PC_Buffer_reg[3][0]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][0]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][10]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][10]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][10]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][11]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][11]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][11]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][12]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][12]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][12]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][13]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][13]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][13]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][14]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][14]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][14]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][15]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][15]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][15]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][16]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][16]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][16]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][17]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][17]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][17]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][18]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][18]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][18]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][19]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][19]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][19]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][1]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][1]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][1]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][20]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][20]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][20]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][21]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][21]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][21]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][22]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][22]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][22]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][23]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][23]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][23]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][24]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][24]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][24]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][25]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][25]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][25]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][26]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][26]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][26]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][27]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][27]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][27]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][28]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][28]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][28]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][29]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][29]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][29]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][2]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][2]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][2]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][30]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][30]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][30]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][31]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][31]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][31]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][3]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][3]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][3]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][4]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][4]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][4]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][5]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][5]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][5]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][6]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][6]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][6]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][7]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][7]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][7]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][8]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][8]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][8]_srl4 ";
  attribute srl_bus_name of \PC_Buffer_reg[3][9]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] ";
  attribute srl_name of \PC_Buffer_reg[3][9]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][9]_srl4 ";
begin
  D(31 downto 0) <= \^d\(31 downto 0);
  \^lopt_2\ <= lopt_3;
  \if_pc_reg[30]_0\(1 downto 0) <= \^if_pc_reg[30]_0\(1 downto 0);
  lopt_12 <= \^lopt_8\;
  lopt_13 <= \^lopt_6\;
  lopt_14 <= \^lopt_4\;
  lopt_15 <= lopt_74;
  lopt_16 <= S27_in;
  lopt_17 <= S22_in;
  lopt_18 <= S17_in;
  lopt_19 <= S12_in;
  lopt_2 <= S;
  lopt_66 <= lopt_4;
  lopt_67 <= lopt_5;
  lopt_68 <= lopt_6;
  lopt_69 <= lopt_7;
  lopt_70 <= lopt_8;
  lopt_71 <= lopt_9;
  lopt_72 <= lopt_10;
  lopt_73 <= lopt_11;
I_AS_INST_0_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABBBBBBBAAAAAAAA"
    )
        port map (
      I0 => ex_jump_nodelay_reg,
      I1 => ex_jump_nodelay_reg_0,
      I2 => wb_exception,
      I3 => Q(0),
      I4 => Q(1),
      I5 => IReady,
      O => IB_Ready
    );
\Instruction_Prefetch_Mux[0].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_206
     port map (
      Clk => Clk,
      D(0) => \^d\(31),
      I0125_out => I0125_out,
      Q(0) => S152_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_31 => of_pc_ii_31,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[0].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_207
     port map (
      I0125_out => I0125_out,
      Q(0) => S152_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_31 => of_pc_ii_31,
      \out\(0) => p_1_in153_in
    );
\Instruction_Prefetch_Mux[10].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_208
     port map (
      Clk => Clk,
      D(0) => \^d\(21),
      I085_out => I085_out,
      Q(0) => S102_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_21 => of_pc_ii_21,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[10].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_209
     port map (
      I085_out => I085_out,
      Q(0) => S102_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_21 => of_pc_ii_21,
      \out\(0) => p_1_in103_in
    );
\Instruction_Prefetch_Mux[11].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_210
     port map (
      Clk => Clk,
      D(0) => \^d\(20),
      I081_out => I081_out,
      Q(0) => S97_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_20 => of_pc_ii_20,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[11].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_211
     port map (
      I081_out => I081_out,
      Q(0) => S97_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_20 => of_pc_ii_20,
      \out\(0) => p_1_in98_in
    );
\Instruction_Prefetch_Mux[12].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_212
     port map (
      Clk => Clk,
      D(0) => \^d\(19),
      I077_out => I077_out,
      Q(0) => S92_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_19 => of_pc_ii_19,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[12].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_213
     port map (
      I077_out => I077_out,
      Q(0) => S92_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_19 => of_pc_ii_19,
      \out\(0) => p_1_in93_in
    );
\Instruction_Prefetch_Mux[13].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_214
     port map (
      Clk => Clk,
      D(0) => \^d\(18),
      I073_out => I073_out,
      Q(0) => S87_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_18 => of_pc_ii_18,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[13].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_215
     port map (
      I073_out => I073_out,
      Q(0) => S87_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_18 => of_pc_ii_18,
      \out\(0) => p_1_in88_in
    );
\Instruction_Prefetch_Mux[14].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_216
     port map (
      Clk => Clk,
      D(0) => \^d\(17),
      I069_out => I069_out,
      Q(0) => S82_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_17 => of_pc_ii_17,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[14].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_217
     port map (
      I069_out => I069_out,
      Q(0) => S82_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_17 => of_pc_ii_17,
      \out\(0) => p_1_in83_in
    );
\Instruction_Prefetch_Mux[15].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_218
     port map (
      Clk => Clk,
      D(0) => \^d\(16),
      I065_out => I065_out,
      Q(0) => S77_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_16 => of_pc_ii_16,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[15].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_219
     port map (
      I065_out => I065_out,
      Q(0) => S77_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_16 => of_pc_ii_16,
      \out\(0) => p_1_in78_in
    );
\Instruction_Prefetch_Mux[16].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_220
     port map (
      Clk => Clk,
      D(0) => \^d\(15),
      I061_out => I061_out,
      Q(0) => S72_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_15 => of_pc_ii_15,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[16].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_221
     port map (
      I061_out => I061_out,
      Q(0) => S72_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_15 => of_pc_ii_15,
      \out\(0) => p_1_in73_in
    );
\Instruction_Prefetch_Mux[17].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_222
     port map (
      Clk => Clk,
      D(0) => \^d\(14),
      I057_out => I057_out,
      Q(0) => S67_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_14 => of_pc_ii_14,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[17].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_223
     port map (
      I057_out => I057_out,
      Q(0) => S67_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_14 => of_pc_ii_14,
      \out\(0) => p_1_in68_in
    );
\Instruction_Prefetch_Mux[18].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_224
     port map (
      Clk => Clk,
      D(0) => \^d\(13),
      I053_out => I053_out,
      Q(0) => S62_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_13 => of_pc_ii_13,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[18].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_225
     port map (
      I053_out => I053_out,
      Q(0) => S62_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_13 => of_pc_ii_13,
      \out\(0) => p_1_in63_in
    );
\Instruction_Prefetch_Mux[19].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_226
     port map (
      Clk => Clk,
      D(0) => \^d\(12),
      I049_out => I049_out,
      Q(0) => S57_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_12 => of_pc_ii_12,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[19].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_227
     port map (
      I049_out => I049_out,
      Q(0) => S57_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_12 => of_pc_ii_12,
      \out\(0) => p_1_in58_in
    );
\Instruction_Prefetch_Mux[1].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_228
     port map (
      Clk => Clk,
      D(0) => \^d\(30),
      I0121_out => I0121_out,
      Q(0) => S147_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_30 => of_pc_ii_30,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[1].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_229
     port map (
      I0121_out => I0121_out,
      Q(0) => S147_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_30 => of_pc_ii_30,
      \out\(0) => p_1_in148_in
    );
\Instruction_Prefetch_Mux[20].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_230
     port map (
      Clk => Clk,
      D(0) => \^d\(11),
      I045_out => I045_out,
      Q(0) => S52_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_11 => of_pc_ii_11,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[20].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_231
     port map (
      I045_out => I045_out,
      Q(0) => S52_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_11 => of_pc_ii_11,
      \out\(0) => p_1_in53_in
    );
\Instruction_Prefetch_Mux[21].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_232
     port map (
      Clk => Clk,
      D(0) => \^d\(10),
      I041_out => I041_out,
      Q(0) => S47_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_10 => of_pc_ii_10,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[21].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_233
     port map (
      I041_out => I041_out,
      Q(0) => S47_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_10 => of_pc_ii_10,
      \out\(0) => p_1_in48_in
    );
\Instruction_Prefetch_Mux[22].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_234
     port map (
      Clk => Clk,
      D(0) => \^d\(9),
      I037_out => I037_out,
      Q(0) => S42_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_9 => of_pc_ii_9,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[22].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_235
     port map (
      I037_out => I037_out,
      Q(0) => S42_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_9 => of_pc_ii_9,
      \out\(0) => p_1_in43_in
    );
\Instruction_Prefetch_Mux[23].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_236
     port map (
      Clk => Clk,
      D(0) => \^d\(8),
      I033_out => I033_out,
      Q(0) => S37_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_8 => of_pc_ii_8,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[23].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_237
     port map (
      I033_out => I033_out,
      Q(0) => S37_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_8 => of_pc_ii_8,
      \out\(0) => p_1_in38_in
    );
\Instruction_Prefetch_Mux[24].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_238
     port map (
      Clk => Clk,
      D(0) => \^d\(7),
      I029_out => I029_out,
      Q(0) => S32_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_7 => of_pc_ii_7,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[24].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_239
     port map (
      I029_out => I029_out,
      Q(0) => S32_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_7 => of_pc_ii_7,
      \out\(0) => p_1_in33_in
    );
\Instruction_Prefetch_Mux[25].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_240
     port map (
      Clk => Clk,
      D(0) => \^d\(6),
      I025_out => I025_out,
      Q(0) => S27_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_6 => of_pc_ii_6,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[25].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_241
     port map (
      I025_out => I025_out,
      Q(0) => S27_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_6 => of_pc_ii_6,
      \out\(0) => p_1_in28_in
    );
\Instruction_Prefetch_Mux[26].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_242
     port map (
      Clk => Clk,
      D(0) => \^d\(5),
      I021_out => I021_out,
      Q(0) => S22_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_5 => of_pc_ii_5,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[26].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_243
     port map (
      I021_out => I021_out,
      Q(0) => S22_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_5 => of_pc_ii_5,
      \out\(0) => p_1_in23_in
    );
\Instruction_Prefetch_Mux[27].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_244
     port map (
      Clk => Clk,
      D(0) => \^d\(4),
      I017_out => I017_out,
      Q(0) => S17_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_4 => of_pc_ii_4,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[27].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_245
     port map (
      I017_out => I017_out,
      Q(0) => S17_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_4 => of_pc_ii_4,
      \out\(0) => p_1_in18_in
    );
\Instruction_Prefetch_Mux[28].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_246
     port map (
      Clk => Clk,
      D(0) => \^d\(3),
      I013_out => I013_out,
      Q(0) => S12_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_3 => of_pc_ii_3,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[28].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_247
     port map (
      I013_out => I013_out,
      Q(0) => S12_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_3 => of_pc_ii_3,
      \out\(0) => p_1_in13_in
    );
\Instruction_Prefetch_Mux[29].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_248
     port map (
      Clk => Clk,
      D(0) => \^d\(2),
      I09_out => I09_out,
      Q(0) => S,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_2 => of_pc_ii_2,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[29].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_249
     port map (
      I09_out => I09_out,
      Q(0) => S,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_2 => of_pc_ii_2,
      \out\(0) => p_1_in8_in
    );
\Instruction_Prefetch_Mux[2].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_250
     port map (
      Clk => Clk,
      D(0) => \^d\(29),
      I0117_out => I0117_out,
      Q(0) => S142_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_29 => of_pc_ii_29,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[2].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_251
     port map (
      I0117_out => I0117_out,
      Q(0) => S142_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_29 => of_pc_ii_29,
      \out\(0) => p_1_in143_in
    );
\Instruction_Prefetch_Mux[30].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_252
     port map (
      Clk => Clk,
      D(0) => \^d\(1),
      I05_out => I05_out,
      Q(0) => \^if_pc_reg[30]_0\(1),
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_1 => of_pc_ii_1,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[30].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_253
     port map (
      I05_out => I05_out,
      Q(0) => \^if_pc_reg[30]_0\(1),
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_1 => of_pc_ii_1,
      \out\(0) => p_2_in4_in
    );
\Instruction_Prefetch_Mux[31].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_254
     port map (
      Clk => Clk,
      D(0) => \^d\(0),
      I0 => I0,
      Q(0) => \^if_pc_reg[30]_0\(0),
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_0 => of_pc_ii_0,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[31].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_255
     port map (
      I0 => I0,
      Q(0) => \^if_pc_reg[30]_0\(0),
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_0 => of_pc_ii_0,
      \out\(0) => \PC_Buffer_reg[3][31]_srl4_n_0\
    );
\Instruction_Prefetch_Mux[3].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_256
     port map (
      Clk => Clk,
      D(0) => \^d\(28),
      I0113_out => I0113_out,
      Q(0) => S137_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_28 => of_pc_ii_28,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[3].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_257
     port map (
      I0113_out => I0113_out,
      Q(0) => S137_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_28 => of_pc_ii_28,
      \out\(0) => p_1_in138_in
    );
\Instruction_Prefetch_Mux[4].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_258
     port map (
      Clk => Clk,
      D(0) => \^d\(27),
      I0109_out => I0109_out,
      Q(0) => S132_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_27 => of_pc_ii_27,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[4].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_259
     port map (
      I0109_out => I0109_out,
      Q(0) => S132_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_27 => of_pc_ii_27,
      \out\(0) => p_1_in133_in
    );
\Instruction_Prefetch_Mux[5].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_260
     port map (
      Clk => Clk,
      D(0) => \^d\(26),
      I0105_out => I0105_out,
      Q(0) => S127_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_26 => of_pc_ii_26,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[5].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_261
     port map (
      I0105_out => I0105_out,
      Q(0) => S127_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_26 => of_pc_ii_26,
      \out\(0) => p_1_in128_in
    );
\Instruction_Prefetch_Mux[6].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_262
     port map (
      Clk => Clk,
      D(0) => \^d\(25),
      I0101_out => I0101_out,
      Q(0) => S122_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_25 => of_pc_ii_25,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[6].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_263
     port map (
      I0101_out => I0101_out,
      Q(0) => S122_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_25 => of_pc_ii_25,
      \out\(0) => p_1_in123_in
    );
\Instruction_Prefetch_Mux[7].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_264
     port map (
      Clk => Clk,
      D(0) => \^d\(24),
      I097_out => I097_out,
      Q(0) => S117_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_24 => of_pc_ii_24,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[7].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_265
     port map (
      I097_out => I097_out,
      Q(0) => S117_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_24 => of_pc_ii_24,
      \out\(0) => p_1_in118_in
    );
\Instruction_Prefetch_Mux[8].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_266
     port map (
      Clk => Clk,
      D(0) => \^d\(23),
      I093_out => I093_out,
      Q(0) => S112_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_23 => of_pc_ii_23,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[8].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_267
     port map (
      I093_out => I093_out,
      Q(0) => S112_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_23 => of_pc_ii_23,
      \out\(0) => p_1_in113_in
    );
\Instruction_Prefetch_Mux[9].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_268
     port map (
      Clk => Clk,
      D(0) => \^d\(22),
      I089_out => I089_out,
      Q(0) => S107_in,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      if_sel_input(0) => if_sel_input(0),
      of_pc_ii_22 => of_pc_ii_22,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[9].PC_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_269
     port map (
      I089_out => I089_out,
      Q(0) => S107_in,
      \Using_FPGA.Native_0\ => \ex_pc_i_reg[31]_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      of_pc_ii_22 => of_pc_ii_22,
      \out\(0) => p_1_in108_in
    );
\PC_Buffer_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S152_in,
      Q => p_1_in153_in
    );
\PC_Buffer_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S102_in,
      Q => p_1_in103_in
    );
\PC_Buffer_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S97_in,
      Q => p_1_in98_in
    );
\PC_Buffer_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S92_in,
      Q => p_1_in93_in
    );
\PC_Buffer_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S87_in,
      Q => p_1_in88_in
    );
\PC_Buffer_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S82_in,
      Q => p_1_in83_in
    );
\PC_Buffer_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S77_in,
      Q => p_1_in78_in
    );
\PC_Buffer_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S72_in,
      Q => p_1_in73_in
    );
\PC_Buffer_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S67_in,
      Q => p_1_in68_in
    );
\PC_Buffer_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S62_in,
      Q => p_1_in63_in
    );
\PC_Buffer_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S57_in,
      Q => p_1_in58_in
    );
\PC_Buffer_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S147_in,
      Q => p_1_in148_in
    );
\PC_Buffer_reg[3][20]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S52_in,
      Q => p_1_in53_in
    );
\PC_Buffer_reg[3][21]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S47_in,
      Q => p_1_in48_in
    );
\PC_Buffer_reg[3][22]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S42_in,
      Q => p_1_in43_in
    );
\PC_Buffer_reg[3][23]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S37_in,
      Q => p_1_in38_in
    );
\PC_Buffer_reg[3][24]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S32_in,
      Q => p_1_in33_in
    );
\PC_Buffer_reg[3][25]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S27_in,
      Q => p_1_in28_in
    );
\PC_Buffer_reg[3][26]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S22_in,
      Q => p_1_in23_in
    );
\PC_Buffer_reg[3][27]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S17_in,
      Q => p_1_in18_in
    );
\PC_Buffer_reg[3][28]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S12_in,
      Q => p_1_in13_in
    );
\PC_Buffer_reg[3][29]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S,
      Q => p_1_in8_in
    );
\PC_Buffer_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S142_in,
      Q => p_1_in143_in
    );
\PC_Buffer_reg[3][30]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => \^if_pc_reg[30]_0\(1),
      Q => p_2_in4_in
    );
\PC_Buffer_reg[3][31]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => \^if_pc_reg[30]_0\(0),
      Q => \PC_Buffer_reg[3][31]_srl4_n_0\
    );
\PC_Buffer_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S137_in,
      Q => p_1_in138_in
    );
\PC_Buffer_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S132_in,
      Q => p_1_in133_in
    );
\PC_Buffer_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S127_in,
      Q => p_1_in128_in
    );
\PC_Buffer_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S122_in,
      Q => p_1_in123_in
    );
\PC_Buffer_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S117_in,
      Q => p_1_in118_in
    );
\PC_Buffer_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S112_in,
      Q => p_1_in113_in
    );
\PC_Buffer_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => if_pre_buffer_addr(0),
      A1 => if_sel_input(1),
      A2 => '0',
      A3 => '0',
      CE => \Using_FPGA.Native_0\,
      CLK => Clk,
      D => S107_in,
      Q => p_1_in108_in
    );
\Using_FPGA.Incr_PC[0].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY
     port map (
      LO => if_pc_carry(29),
      O56_out => O56_out,
      Q(0) => S152_in
    );
\Using_FPGA.Incr_PC[10].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_270
     port map (
      LO => if_pc_carry(20),
      Q(0) => S102_in,
      \if_pc_reg[10]\ => \if_pc_reg[10]_0\,
      \if_pc_reg[10]_0\ => if_pc_carry(19),
      lopt => lopt_41,
      lopt_1 => lopt_42,
      lopt_2 => lopt_46
    );
\Using_FPGA.Incr_PC[11].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_271
     port map (
      LO => if_pc_carry(19),
      Q(0) => S97_in,
      \if_pc_reg[11]\ => \if_pc_reg[11]_0\,
      \if_pc_reg[11]_0\ => if_pc_carry(18),
      lopt => lopt_39,
      lopt_1 => lopt_40,
      lopt_2 => lopt_45
    );
\Using_FPGA.Incr_PC[12].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_272
     port map (
      LO => if_pc_carry(18),
      Q(0) => S92_in,
      \if_pc_reg[12]\ => \if_pc_reg[12]_0\,
      \if_pc_reg[12]_0\ => if_pc_carry(17),
      lopt => lopt_39,
      lopt_1 => lopt_40,
      lopt_10 => lopt_46,
      lopt_11 => lopt_47,
      lopt_12 => lopt_84,
      lopt_13 => lopt_85,
      lopt_14 => lopt_86,
      lopt_15 => lopt_87,
      lopt_16 => lopt_88,
      lopt_17 => lopt_89,
      lopt_18 => lopt_90,
      lopt_19 => lopt_91,
      lopt_2 => S97_in,
      lopt_20 => lopt_92,
      lopt_3 => lopt_41,
      lopt_4 => lopt_42,
      lopt_5 => S102_in,
      lopt_6 => lopt_43,
      lopt_7 => lopt_44,
      lopt_8 => S107_in,
      lopt_9 => lopt_45
    );
\Using_FPGA.Incr_PC[13].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_273
     port map (
      LO => if_pc_carry(17),
      Q(0) => S87_in,
      \if_pc_reg[13]\ => \if_pc_reg[13]_0\,
      \if_pc_reg[13]_0\ => if_pc_carry(16),
      lopt => lopt_34,
      lopt_1 => lopt_35,
      lopt_2 => lopt_38
    );
\Using_FPGA.Incr_PC[14].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_274
     port map (
      LO => if_pc_carry(16),
      Q(0) => S82_in,
      \if_pc_reg[14]\ => \if_pc_reg[14]_0\,
      \if_pc_reg[14]_0\ => if_pc_carry(15),
      lopt => lopt_32,
      lopt_1 => lopt_33,
      lopt_2 => lopt_37
    );
\Using_FPGA.Incr_PC[15].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_275
     port map (
      LO => if_pc_carry(15),
      Q(0) => S77_in,
      \if_pc_reg[15]\ => \if_pc_reg[15]_0\,
      \if_pc_reg[15]_0\ => if_pc_carry(14),
      lopt => lopt_30,
      lopt_1 => lopt_31,
      lopt_2 => lopt_36
    );
\Using_FPGA.Incr_PC[16].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_276
     port map (
      LO => if_pc_carry(14),
      Q(0) => S72_in,
      \if_pc_reg[16]\ => \if_pc_reg[16]_0\,
      \if_pc_reg[16]_0\ => if_pc_carry(13),
      lopt => lopt_30,
      lopt_1 => lopt_31,
      lopt_10 => lopt_37,
      lopt_11 => lopt_38,
      lopt_12 => lopt_84,
      lopt_13 => lopt_85,
      lopt_14 => lopt_86,
      lopt_15 => lopt_87,
      lopt_16 => lopt_88,
      lopt_17 => lopt_89,
      lopt_18 => lopt_90,
      lopt_19 => lopt_91,
      lopt_2 => S77_in,
      lopt_20 => lopt_44,
      lopt_21 => lopt_42,
      lopt_22 => lopt_40,
      lopt_23 => lopt_92,
      lopt_24 => S107_in,
      lopt_25 => S102_in,
      lopt_26 => S97_in,
      lopt_27 => S92_in,
      lopt_3 => lopt_32,
      lopt_4 => lopt_33,
      lopt_5 => S82_in,
      lopt_6 => lopt_34,
      lopt_7 => lopt_35,
      lopt_8 => S87_in,
      lopt_9 => lopt_36
    );
\Using_FPGA.Incr_PC[17].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_277
     port map (
      LO => if_pc_carry(13),
      Q(0) => S67_in,
      \if_pc_reg[17]\ => \if_pc_reg[17]_0\,
      \if_pc_reg[17]_0\ => if_pc_carry(12),
      lopt => lopt_25,
      lopt_1 => lopt_26,
      lopt_2 => lopt_29
    );
\Using_FPGA.Incr_PC[18].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_278
     port map (
      LO => if_pc_carry(12),
      Q(0) => S62_in,
      \if_pc_reg[18]\ => \if_pc_reg[18]_0\,
      \if_pc_reg[18]_0\ => if_pc_carry(11),
      lopt => lopt_23,
      lopt_1 => lopt_24,
      lopt_2 => lopt_28
    );
\Using_FPGA.Incr_PC[19].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_279
     port map (
      LO => if_pc_carry(11),
      Q(0) => S57_in,
      \if_pc_reg[19]\ => \if_pc_reg[19]_0\,
      \if_pc_reg[19]_0\ => if_pc_carry(10),
      lopt => lopt_21,
      lopt_1 => lopt_22,
      lopt_2 => lopt_27
    );
\Using_FPGA.Incr_PC[1].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_280
     port map (
      LO => if_pc_carry(29),
      Q(0) => S147_in,
      \if_pc_reg[1]\ => \if_pc_reg[1]_0\,
      \if_pc_reg[1]_0\ => if_pc_carry(28),
      lopt => lopt_61,
      lopt_1 => lopt_62,
      lopt_2 => lopt_65
    );
\Using_FPGA.Incr_PC[20].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_281
     port map (
      LO => if_pc_carry(10),
      Q(0) => S52_in,
      \if_pc_reg[20]\ => \if_pc_reg[20]_0\,
      \if_pc_reg[20]_0\ => if_pc_carry(9),
      lopt => lopt_21,
      lopt_1 => lopt_22,
      lopt_10 => lopt_28,
      lopt_11 => lopt_29,
      lopt_12 => lopt_75,
      lopt_13 => lopt_76,
      lopt_14 => lopt_77,
      lopt_15 => lopt_78,
      lopt_16 => lopt_79,
      lopt_17 => lopt_80,
      lopt_18 => lopt_81,
      lopt_19 => lopt_82,
      lopt_2 => S57_in,
      lopt_20 => lopt_83,
      lopt_3 => lopt_23,
      lopt_4 => lopt_24,
      lopt_5 => S62_in,
      lopt_6 => lopt_25,
      lopt_7 => lopt_26,
      lopt_8 => S67_in,
      lopt_9 => lopt_27
    );
\Using_FPGA.Incr_PC[21].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_282
     port map (
      LO => if_pc_carry(9),
      Q(0) => S47_in,
      \if_pc_reg[21]\ => \if_pc_reg[21]_0\,
      \if_pc_reg[21]_0\ => if_pc_carry(8),
      lopt => \^lopt_16\,
      lopt_1 => \^lopt_17\,
      lopt_2 => lopt_20
    );
\Using_FPGA.Incr_PC[22].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_283
     port map (
      LO => if_pc_carry(8),
      Q(0) => S42_in,
      \if_pc_reg[22]\ => \if_pc_reg[22]_0\,
      \if_pc_reg[22]_0\ => if_pc_carry(7),
      lopt => \^lopt_14\,
      lopt_1 => \^lopt_15\,
      lopt_2 => \^lopt_19\
    );
\Using_FPGA.Incr_PC[23].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_284
     port map (
      LO => if_pc_carry(7),
      Q(0) => S37_in,
      \if_pc_reg[23]\ => \if_pc_reg[23]_0\,
      \if_pc_reg[23]_0\ => if_pc_carry(6),
      lopt => \^lopt_12\,
      lopt_1 => \^lopt_13\,
      lopt_2 => \^lopt_18\
    );
\Using_FPGA.Incr_PC[24].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_285
     port map (
      LO => if_pc_carry(6),
      Q(0) => S32_in,
      \if_pc_reg[24]\ => \if_pc_reg[24]_0\,
      \if_pc_reg[24]_0\ => if_pc_carry(5),
      lopt => \^lopt_12\,
      lopt_1 => \^lopt_13\,
      lopt_10 => \^lopt_19\,
      lopt_11 => lopt_20,
      lopt_12 => lopt_75,
      lopt_13 => lopt_76,
      lopt_14 => lopt_77,
      lopt_15 => lopt_78,
      lopt_16 => lopt_79,
      lopt_17 => lopt_80,
      lopt_18 => lopt_81,
      lopt_19 => lopt_82,
      lopt_2 => S37_in,
      lopt_20 => lopt_26,
      lopt_21 => lopt_24,
      lopt_22 => lopt_22,
      lopt_23 => lopt_83,
      lopt_24 => S67_in,
      lopt_25 => S62_in,
      lopt_26 => S57_in,
      lopt_27 => S52_in,
      lopt_3 => \^lopt_14\,
      lopt_4 => \^lopt_15\,
      lopt_5 => S42_in,
      lopt_6 => \^lopt_16\,
      lopt_7 => \^lopt_17\,
      lopt_8 => S47_in,
      lopt_9 => \^lopt_18\
    );
\Using_FPGA.Incr_PC[25].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_286
     port map (
      LO => if_pc_carry(5),
      Q(0) => S27_in,
      \if_pc_reg[25]\ => \if_pc_reg[25]_0\,
      \if_pc_reg[25]_0\ => if_pc_carry(4),
      lopt => \^lopt_7\,
      lopt_1 => \^lopt_8\,
      lopt_2 => \^lopt_11\
    );
\Using_FPGA.Incr_PC[26].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_287
     port map (
      LO => if_pc_carry(4),
      Q(0) => S22_in,
      \if_pc_reg[26]\ => \if_pc_reg[26]_0\,
      \if_pc_reg[26]_0\ => if_pc_carry(3),
      lopt => \^lopt_5\,
      lopt_1 => \^lopt_6\,
      lopt_2 => \^lopt_10\
    );
\Using_FPGA.Incr_PC[27].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_288
     port map (
      LO => if_pc_carry(3),
      Q(0) => S17_in,
      \if_pc_reg[27]\ => \if_pc_reg[27]_0\,
      \if_pc_reg[27]_0\ => if_pc_carry(2),
      lopt => \^lopt_3\,
      lopt_1 => \^lopt_4\,
      lopt_2 => \^lopt_9\
    );
\Using_FPGA.Incr_PC[28].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_289
     port map (
      LO => if_pc_carry(2),
      Q(0) => S12_in,
      \if_pc_reg[28]\ => \if_pc_reg[28]_0\,
      \if_pc_reg[28]_0\ => if_pc_carry(1),
      lopt => \^lopt_3\,
      lopt_1 => \^lopt_4\,
      lopt_10 => \^lopt_10\,
      lopt_11 => \^lopt_11\,
      lopt_12 => lopt_66,
      lopt_13 => lopt_67,
      lopt_14 => lopt_68,
      lopt_15 => lopt_69,
      lopt_16 => lopt_70,
      lopt_17 => lopt_71,
      lopt_18 => lopt_72,
      lopt_19 => lopt_73,
      lopt_2 => S17_in,
      lopt_20 => lopt_74,
      lopt_3 => \^lopt_5\,
      lopt_4 => \^lopt_6\,
      lopt_5 => S22_in,
      lopt_6 => \^lopt_7\,
      lopt_7 => \^lopt_8\,
      lopt_8 => S27_in,
      lopt_9 => \^lopt_9\
    );
\Using_FPGA.Incr_PC[29].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_290
     port map (
      CI => CI,
      LO => if_pc_carry(1),
      O => O,
      Q(0) => S,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_2 => \^lopt_2\
    );
\Using_FPGA.Incr_PC[2].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_291
     port map (
      LO => if_pc_carry(28),
      Q(0) => S142_in,
      \if_pc_reg[2]\ => \if_pc_reg[2]_0\,
      \if_pc_reg[2]_0\ => if_pc_carry(27),
      lopt => lopt_59,
      lopt_1 => lopt_60,
      lopt_2 => lopt_64
    );
\Using_FPGA.Incr_PC[3].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_292
     port map (
      LO => if_pc_carry(27),
      Q(0) => S137_in,
      \if_pc_reg[3]\ => \if_pc_reg[3]_0\,
      \if_pc_reg[3]_0\ => if_pc_carry(26),
      lopt => lopt_57,
      lopt_1 => lopt_58,
      lopt_2 => lopt_63
    );
\Using_FPGA.Incr_PC[4].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_293
     port map (
      LO => if_pc_carry(26),
      Q(0) => S132_in,
      \if_pc_reg[4]\ => \if_pc_reg[4]_0\,
      \if_pc_reg[4]_0\ => if_pc_carry(25),
      lopt => lopt_57,
      lopt_1 => lopt_58,
      lopt_10 => lopt_64,
      lopt_11 => lopt_65,
      lopt_12 => lopt_93,
      lopt_13 => lopt_94,
      lopt_14 => lopt_95,
      lopt_15 => lopt_96,
      lopt_16 => lopt_97,
      lopt_17 => lopt_98,
      lopt_18 => lopt_99,
      lopt_19 => lopt_100,
      lopt_2 => S137_in,
      lopt_20 => lopt_101,
      lopt_3 => lopt_59,
      lopt_4 => lopt_60,
      lopt_5 => S142_in,
      lopt_6 => lopt_61,
      lopt_7 => lopt_62,
      lopt_8 => S147_in,
      lopt_9 => lopt_63
    );
\Using_FPGA.Incr_PC[5].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_294
     port map (
      LO => if_pc_carry(25),
      Q(0) => S127_in,
      \if_pc_reg[5]\ => \if_pc_reg[5]_0\,
      \if_pc_reg[5]_0\ => if_pc_carry(24),
      lopt => lopt_52,
      lopt_1 => lopt_53,
      lopt_2 => lopt_56
    );
\Using_FPGA.Incr_PC[6].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_295
     port map (
      LO => if_pc_carry(24),
      Q(0) => S122_in,
      \if_pc_reg[6]\ => \if_pc_reg[6]_0\,
      \if_pc_reg[6]_0\ => if_pc_carry(23),
      lopt => lopt_50,
      lopt_1 => lopt_51,
      lopt_2 => lopt_55
    );
\Using_FPGA.Incr_PC[7].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_296
     port map (
      LO => if_pc_carry(23),
      Q(0) => S117_in,
      \if_pc_reg[7]\ => \if_pc_reg[7]_0\,
      \if_pc_reg[7]_0\ => if_pc_carry(22),
      lopt => lopt_48,
      lopt_1 => lopt_49,
      lopt_2 => lopt_54
    );
\Using_FPGA.Incr_PC[8].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_297
     port map (
      LO => if_pc_carry(22),
      Q(0) => S112_in,
      \if_pc_reg[8]\ => \if_pc_reg[8]_0\,
      \if_pc_reg[8]_0\ => if_pc_carry(21),
      lopt => lopt_48,
      lopt_1 => lopt_49,
      lopt_10 => lopt_55,
      lopt_11 => lopt_56,
      lopt_12 => lopt_93,
      lopt_13 => lopt_94,
      lopt_14 => lopt_95,
      lopt_15 => lopt_96,
      lopt_16 => lopt_97,
      lopt_17 => lopt_98,
      lopt_18 => lopt_99,
      lopt_19 => lopt_100,
      lopt_2 => S117_in,
      lopt_20 => lopt_62,
      lopt_21 => lopt_60,
      lopt_22 => lopt_58,
      lopt_23 => lopt_101,
      lopt_24 => S147_in,
      lopt_25 => S142_in,
      lopt_26 => S137_in,
      lopt_27 => S132_in,
      lopt_3 => lopt_50,
      lopt_4 => lopt_51,
      lopt_5 => S122_in,
      lopt_6 => lopt_52,
      lopt_7 => lopt_53,
      lopt_8 => S127_in,
      lopt_9 => lopt_54
    );
\Using_FPGA.Incr_PC[9].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_298
     port map (
      CI => if_pc_carry(20),
      LO => if_pc_carry(21),
      Q(0) => S107_in,
      \if_pc_reg[9]\ => \if_pc_reg[9]_0\,
      lopt => lopt_43,
      lopt_1 => lopt_44,
      lopt_2 => lopt_47
    );
\ex_pc_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(31),
      Q => ex_pc(0),
      R => sync_reset
    );
\ex_pc_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(21),
      Q => ex_pc(10),
      R => sync_reset
    );
\ex_pc_i_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(20),
      Q => ex_pc(11),
      R => sync_reset
    );
\ex_pc_i_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(19),
      Q => ex_pc(12),
      R => sync_reset
    );
\ex_pc_i_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(18),
      Q => ex_pc(13),
      R => sync_reset
    );
\ex_pc_i_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(17),
      Q => ex_pc(14),
      R => sync_reset
    );
\ex_pc_i_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(16),
      Q => ex_pc(15),
      R => sync_reset
    );
\ex_pc_i_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(15),
      Q => ex_pc(16),
      R => sync_reset
    );
\ex_pc_i_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(14),
      Q => ex_pc(17),
      R => sync_reset
    );
\ex_pc_i_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(13),
      Q => ex_pc(18),
      R => sync_reset
    );
\ex_pc_i_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(12),
      Q => ex_pc(19),
      R => sync_reset
    );
\ex_pc_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(30),
      Q => ex_pc(1),
      R => sync_reset
    );
\ex_pc_i_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(11),
      Q => ex_pc(20),
      R => sync_reset
    );
\ex_pc_i_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(10),
      Q => ex_pc(21),
      R => sync_reset
    );
\ex_pc_i_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(9),
      Q => ex_pc(22),
      R => sync_reset
    );
\ex_pc_i_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(8),
      Q => ex_pc(23),
      R => sync_reset
    );
\ex_pc_i_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(7),
      Q => ex_pc(24),
      R => sync_reset
    );
\ex_pc_i_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(6),
      Q => ex_pc(25),
      R => sync_reset
    );
\ex_pc_i_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(5),
      Q => ex_pc(26),
      R => sync_reset
    );
\ex_pc_i_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(4),
      Q => ex_pc(27),
      R => sync_reset
    );
\ex_pc_i_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(3),
      Q => ex_pc(28),
      R => sync_reset
    );
\ex_pc_i_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(2),
      Q => ex_pc(29),
      R => sync_reset
    );
\ex_pc_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(29),
      Q => ex_pc(2),
      R => sync_reset
    );
\ex_pc_i_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(1),
      Q => ex_pc(30),
      R => sync_reset
    );
\ex_pc_i_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(0),
      Q => ex_pc(31),
      R => sync_reset
    );
\ex_pc_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(28),
      Q => ex_pc(3),
      R => sync_reset
    );
\ex_pc_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(27),
      Q => ex_pc(4),
      R => sync_reset
    );
\ex_pc_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(26),
      Q => ex_pc(5),
      R => sync_reset
    );
\ex_pc_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(25),
      Q => ex_pc(6),
      R => sync_reset
    );
\ex_pc_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(24),
      Q => ex_pc(7),
      R => sync_reset
    );
\ex_pc_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(23),
      Q => ex_pc(8),
      R => sync_reset
    );
\ex_pc_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \ex_pc_i_reg[31]_0\,
      D => \^d\(22),
      Q => ex_pc(9),
      R => sync_reset
    );
\if_pc_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(31),
      Q => S152_in,
      S => sync_reset
    );
\if_pc_reg[10]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(21),
      Q => S102_in,
      S => sync_reset
    );
\if_pc_reg[11]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(20),
      Q => S97_in,
      S => sync_reset
    );
\if_pc_reg[12]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(19),
      Q => S92_in,
      S => sync_reset
    );
\if_pc_reg[13]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(18),
      Q => S87_in,
      S => sync_reset
    );
\if_pc_reg[14]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(17),
      Q => S82_in,
      S => sync_reset
    );
\if_pc_reg[15]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(16),
      Q => S77_in,
      S => sync_reset
    );
\if_pc_reg[16]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(15),
      Q => S72_in,
      S => sync_reset
    );
\if_pc_reg[17]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(14),
      Q => S67_in,
      S => sync_reset
    );
\if_pc_reg[18]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(13),
      Q => S62_in,
      S => sync_reset
    );
\if_pc_reg[19]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(12),
      Q => S57_in,
      S => sync_reset
    );
\if_pc_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(30),
      Q => S147_in,
      S => sync_reset
    );
\if_pc_reg[20]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(11),
      Q => S52_in,
      S => sync_reset
    );
\if_pc_reg[21]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(10),
      Q => S47_in,
      S => sync_reset
    );
\if_pc_reg[22]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(9),
      Q => S42_in,
      S => sync_reset
    );
\if_pc_reg[23]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(8),
      Q => S37_in,
      S => sync_reset
    );
\if_pc_reg[24]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(7),
      Q => S32_in,
      S => sync_reset
    );
\if_pc_reg[25]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(6),
      Q => S27_in,
      S => sync_reset
    );
\if_pc_reg[26]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(5),
      Q => S22_in,
      S => sync_reset
    );
\if_pc_reg[27]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(4),
      Q => S17_in,
      S => sync_reset
    );
\if_pc_reg[28]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(3),
      Q => S12_in,
      S => sync_reset
    );
\if_pc_reg[29]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(2),
      Q => S,
      S => sync_reset
    );
\if_pc_reg[2]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(29),
      Q => S142_in,
      S => sync_reset
    );
\if_pc_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(1),
      Q => \^if_pc_reg[30]_0\(1),
      R => sync_reset
    );
\if_pc_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(0),
      Q => \^if_pc_reg[30]_0\(0),
      R => sync_reset
    );
\if_pc_reg[3]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(28),
      Q => S137_in,
      S => sync_reset
    );
\if_pc_reg[4]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(27),
      Q => S132_in,
      S => sync_reset
    );
\if_pc_reg[5]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(26),
      Q => S127_in,
      S => sync_reset
    );
\if_pc_reg[6]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(25),
      Q => S122_in,
      S => sync_reset
    );
\if_pc_reg[7]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(24),
      Q => S117_in,
      S => sync_reset
    );
\if_pc_reg[8]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(23),
      Q => S112_in,
      S => sync_reset
    );
\if_pc_reg[9]\: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \if_pc_reg[0]_0\(0),
      D => \if_pc_reg[0]_1\(22),
      Q => S107_in,
      S => sync_reset
    );
\mem_pc_i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(0),
      Q => \mem_pc_i_reg[0]_0\(31),
      R => sync_reset
    );
\mem_pc_i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(10),
      Q => \mem_pc_i_reg[0]_0\(21),
      R => sync_reset
    );
\mem_pc_i_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(11),
      Q => \mem_pc_i_reg[0]_0\(20),
      R => sync_reset
    );
\mem_pc_i_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(12),
      Q => \mem_pc_i_reg[0]_0\(19),
      R => sync_reset
    );
\mem_pc_i_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(13),
      Q => \mem_pc_i_reg[0]_0\(18),
      R => sync_reset
    );
\mem_pc_i_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(14),
      Q => \mem_pc_i_reg[0]_0\(17),
      R => sync_reset
    );
\mem_pc_i_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(15),
      Q => \mem_pc_i_reg[0]_0\(16),
      R => sync_reset
    );
\mem_pc_i_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(16),
      Q => \mem_pc_i_reg[0]_0\(15),
      R => sync_reset
    );
\mem_pc_i_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(17),
      Q => \mem_pc_i_reg[0]_0\(14),
      R => sync_reset
    );
\mem_pc_i_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(18),
      Q => \mem_pc_i_reg[0]_0\(13),
      R => sync_reset
    );
\mem_pc_i_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(19),
      Q => \mem_pc_i_reg[0]_0\(12),
      R => sync_reset
    );
\mem_pc_i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(1),
      Q => \mem_pc_i_reg[0]_0\(30),
      R => sync_reset
    );
\mem_pc_i_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(20),
      Q => \mem_pc_i_reg[0]_0\(11),
      R => sync_reset
    );
\mem_pc_i_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(21),
      Q => \mem_pc_i_reg[0]_0\(10),
      R => sync_reset
    );
\mem_pc_i_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(22),
      Q => \mem_pc_i_reg[0]_0\(9),
      R => sync_reset
    );
\mem_pc_i_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(23),
      Q => \mem_pc_i_reg[0]_0\(8),
      R => sync_reset
    );
\mem_pc_i_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(24),
      Q => \mem_pc_i_reg[0]_0\(7),
      R => sync_reset
    );
\mem_pc_i_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(25),
      Q => \mem_pc_i_reg[0]_0\(6),
      R => sync_reset
    );
\mem_pc_i_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(26),
      Q => \mem_pc_i_reg[0]_0\(5),
      R => sync_reset
    );
\mem_pc_i_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(27),
      Q => \mem_pc_i_reg[0]_0\(4),
      R => sync_reset
    );
\mem_pc_i_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(28),
      Q => \mem_pc_i_reg[0]_0\(3),
      R => sync_reset
    );
\mem_pc_i_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(29),
      Q => \mem_pc_i_reg[0]_0\(2),
      R => sync_reset
    );
\mem_pc_i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(2),
      Q => \mem_pc_i_reg[0]_0\(29),
      R => sync_reset
    );
\mem_pc_i_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(30),
      Q => \mem_pc_i_reg[0]_0\(1),
      R => sync_reset
    );
\mem_pc_i_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(31),
      Q => \mem_pc_i_reg[0]_0\(0),
      R => sync_reset
    );
\mem_pc_i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(3),
      Q => \mem_pc_i_reg[0]_0\(28),
      R => sync_reset
    );
\mem_pc_i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(4),
      Q => \mem_pc_i_reg[0]_0\(27),
      R => sync_reset
    );
\mem_pc_i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(5),
      Q => \mem_pc_i_reg[0]_0\(26),
      R => sync_reset
    );
\mem_pc_i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(6),
      Q => \mem_pc_i_reg[0]_0\(25),
      R => sync_reset
    );
\mem_pc_i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(7),
      Q => \mem_pc_i_reg[0]_0\(24),
      R => sync_reset
    );
\mem_pc_i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(8),
      Q => \mem_pc_i_reg[0]_0\(23),
      R => sync_reset
    );
\mem_pc_i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => E(0),
      D => ex_pc(9),
      Q => \mem_pc_i_reg[0]_0\(22),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_PreFetch_Buffer_gti is
  port (
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    IReady_0 : out STD_LOGIC;
    of_valid : out STD_LOGIC;
    of_instr : out STD_LOGIC_VECTOR ( 5 downto 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC_VECTOR ( 20 downto 0 );
    of_predecode : out STD_LOGIC_VECTOR ( 0 to 10 );
    \Using_FPGA.Native_5\ : out STD_LOGIC;
    ex_gpr_write_reg : out STD_LOGIC;
    ex_is_div_instr_I_reg : out STD_LOGIC;
    if_pre_buffer_addr : out STD_LOGIC_VECTOR ( 0 to 0 );
    if_fetch_in_progress_reg : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_6\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    if_fetch_for_timing_optimization1 : out STD_LOGIC;
    \Using_FPGA.Native_7\ : out STD_LOGIC;
    ex_op1_cmp_eq1 : out STD_LOGIC;
    ex_op1_cmp_eq_n5_out : out STD_LOGIC;
    \Using_FPGA.Native_8\ : out STD_LOGIC;
    use_Reg_Neg_DI1_out : out STD_LOGIC;
    force_Val10_out : out STD_LOGIC;
    use_Reg_Neg_S3_out : out STD_LOGIC;
    force12_out : out STD_LOGIC;
    \Using_FPGA.Native_9\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_10\ : out STD_LOGIC;
    ex_move_to_MSR_instr93_out : out STD_LOGIC;
    of_Sel_SPR_MSR1 : out STD_LOGIC;
    ex_sel_alu_i_reg : out STD_LOGIC_VECTOR ( 31 downto 0 );
    of_use_op2_s : out STD_LOGIC;
    ex_sel_alu_i_reg_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ex_sel_alu_i_reg_1 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \Using_FPGA.Native_11\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    p_9_in : out STD_LOGIC;
    ex_sel_alu_i0 : out STD_LOGIC;
    \Using_FPGA.Native_12\ : out STD_LOGIC;
    ex_load_shift_carry0 : out STD_LOGIC;
    ex_mbar_is_sleep_cmb : out STD_LOGIC;
    ex_mbar_decode_cmb : out STD_LOGIC;
    \Using_FPGA.Native_13\ : out STD_LOGIC;
    D224_out : out STD_LOGIC;
    p_2_in : out STD_LOGIC;
    \Using_FPGA.Native_14\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native_15\ : out STD_LOGIC;
    \Using_FPGA.Native_16\ : out STD_LOGIC;
    \Serial_Dbg_Intf.control_reg_reg[8]\ : out STD_LOGIC;
    ex_enable_sext_shift_i0 : out STD_LOGIC;
    \Using_FPGA.Native_17\ : out STD_LOGIC;
    if_missed_fetch_reg : out STD_LOGIC;
    wb_exception_i_reg : out STD_LOGIC;
    \Using_FPGA.Native_18\ : out STD_LOGIC;
    \Using_FPGA.Native_19\ : out STD_LOGIC;
    \Using_FPGA.Native_20\ : out STD_LOGIC;
    \Using_FPGA.Native_21\ : out STD_LOGIC;
    \Using_FPGA.Native_22\ : out STD_LOGIC;
    ex_branch_with_delayslot_reg : out STD_LOGIC;
    \Using_FPGA.Native_23\ : out STD_LOGIC;
    \Using_FPGA.Native_24\ : out STD_LOGIC;
    \Using_FPGA.Native_25\ : out STD_LOGIC;
    \Using_FPGA.Native_26\ : out STD_LOGIC;
    \Using_FPGA.Native_27\ : out STD_LOGIC;
    \Using_FPGA.Native_28\ : out STD_LOGIC;
    \Using_FPGA.Native_29\ : out STD_LOGIC;
    \Using_FPGA.Native_30\ : out STD_LOGIC;
    \Using_FPGA.Native_31\ : out STD_LOGIC;
    \Using_FPGA.Native_32\ : out STD_LOGIC;
    \Using_FPGA.Native_33\ : out STD_LOGIC;
    \Using_FPGA.Native_34\ : out STD_LOGIC;
    \Using_FPGA.Native_35\ : out STD_LOGIC;
    \Using_FPGA.Native_36\ : out STD_LOGIC;
    \Using_FPGA.Native_37\ : out STD_LOGIC;
    \Using_FPGA.Native_38\ : out STD_LOGIC;
    \Using_FPGA.Native_39\ : out STD_LOGIC;
    \Using_FPGA.Native_40\ : out STD_LOGIC;
    \Using_FPGA.Native_41\ : out STD_LOGIC;
    \Using_FPGA.Native_42\ : out STD_LOGIC;
    \Using_FPGA.Native_43\ : out STD_LOGIC;
    \Using_FPGA.Native_44\ : out STD_LOGIC;
    \Using_FPGA.Native_45\ : out STD_LOGIC;
    \Using_FPGA.Native_46\ : out STD_LOGIC;
    \Using_FPGA.Native_47\ : out STD_LOGIC;
    \Using_FPGA.Native_48\ : out STD_LOGIC;
    \Using_FPGA.Native_49\ : out STD_LOGIC;
    \Using_FPGA.Native_50\ : out STD_LOGIC;
    \Using_FPGA.Native_51\ : out STD_LOGIC;
    \Using_FPGA.Native_52\ : out STD_LOGIC;
    \Using_FPGA.Native_53\ : out STD_LOGIC;
    \Using_FPGA.Native_54\ : out STD_LOGIC;
    \Using_FPGA.Native_55\ : out STD_LOGIC;
    \Using_FPGA.Native_56\ : out STD_LOGIC;
    \Using_FPGA.Native_57\ : out STD_LOGIC;
    \Using_FPGA.Native_58\ : out STD_LOGIC;
    I1_0 : out STD_LOGIC;
    of_Sel_SPR_MSR88_out : out STD_LOGIC;
    ex_is_multi_or_load_instr0 : out STD_LOGIC;
    of_op1_sel_spr : out STD_LOGIC;
    Dbg_Clean_Stop0 : out STD_LOGIC;
    ex_set_bip : out STD_LOGIC;
    \Using_FPGA.Native_59\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_60\ : in STD_LOGIC;
    I5 : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Clk : in STD_LOGIC;
    I139_out : in STD_LOGIC;
    ex_branch_with_delayslot_i_reg_0 : in STD_LOGIC;
    ex_gpr_write_reg_0 : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    EX_Is_Div_Instr : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    ex_jump : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    if_fetch_in_progress : in STD_LOGIC;
    IB_Ready : in STD_LOGIC;
    in0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \in\ : in STD_LOGIC_VECTOR ( 32 downto 0 );
    \EX_Op2_reg[31]\ : in STD_LOGIC;
    \EX_Op2_reg[31]_0\ : in STD_LOGIC;
    MEM_Fwd : in STD_LOGIC_VECTOR ( 0 to 31 );
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Op2_reg[30]\ : in STD_LOGIC;
    \EX_Op2_reg[30]_0\ : in STD_LOGIC;
    \EX_Op2_reg[29]\ : in STD_LOGIC;
    \EX_Op2_reg[29]_0\ : in STD_LOGIC;
    \EX_Op2_reg[28]\ : in STD_LOGIC;
    \EX_Op2_reg[28]_0\ : in STD_LOGIC;
    \EX_Op2_reg[27]\ : in STD_LOGIC;
    \EX_Op2_reg[27]_0\ : in STD_LOGIC;
    \EX_Op2_reg[26]\ : in STD_LOGIC;
    \EX_Op2_reg[26]_0\ : in STD_LOGIC;
    \EX_Op2_reg[25]\ : in STD_LOGIC;
    \EX_Op2_reg[25]_0\ : in STD_LOGIC;
    \EX_Op2_reg[24]\ : in STD_LOGIC;
    \EX_Op2_reg[24]_0\ : in STD_LOGIC;
    \EX_Op2_reg[23]\ : in STD_LOGIC;
    \EX_Op2_reg[16]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \EX_Op2_reg[22]\ : in STD_LOGIC;
    \EX_Op2_reg[21]\ : in STD_LOGIC;
    \EX_Op2_reg[20]\ : in STD_LOGIC;
    \EX_Op2_reg[19]\ : in STD_LOGIC;
    \EX_Op2_reg[18]\ : in STD_LOGIC;
    \EX_Op2_reg[17]\ : in STD_LOGIC;
    \EX_Op2_reg[16]_0\ : in STD_LOGIC;
    \EX_Op2_reg[15]\ : in STD_LOGIC;
    \EX_Op2_reg[15]_0\ : in STD_LOGIC;
    \EX_Op2_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \EX_Op2_reg[0]_0\ : in STD_LOGIC;
    \EX_Op2_reg[14]\ : in STD_LOGIC;
    \EX_Op2_reg[14]_0\ : in STD_LOGIC;
    \EX_Op2_reg[13]\ : in STD_LOGIC;
    \EX_Op2_reg[13]_0\ : in STD_LOGIC;
    \EX_Op2_reg[12]\ : in STD_LOGIC;
    \EX_Op2_reg[12]_0\ : in STD_LOGIC;
    \EX_Op2_reg[11]\ : in STD_LOGIC;
    \EX_Op2_reg[11]_0\ : in STD_LOGIC;
    \EX_Op2_reg[10]\ : in STD_LOGIC;
    \EX_Op2_reg[10]_0\ : in STD_LOGIC;
    \EX_Op2_reg[9]\ : in STD_LOGIC;
    \EX_Op2_reg[9]_0\ : in STD_LOGIC;
    \EX_Op2_reg[8]\ : in STD_LOGIC;
    \EX_Op2_reg[8]_0\ : in STD_LOGIC;
    \EX_Op2_reg[7]\ : in STD_LOGIC;
    \EX_Op2_reg[7]_0\ : in STD_LOGIC;
    \EX_Op2_reg[6]\ : in STD_LOGIC;
    \EX_Op2_reg[6]_0\ : in STD_LOGIC;
    \EX_Op2_reg[5]\ : in STD_LOGIC;
    \EX_Op2_reg[5]_0\ : in STD_LOGIC;
    \EX_Op2_reg[4]\ : in STD_LOGIC;
    \EX_Op2_reg[4]_0\ : in STD_LOGIC;
    \EX_Op2_reg[3]\ : in STD_LOGIC;
    \EX_Op2_reg[3]_0\ : in STD_LOGIC;
    \EX_Op2_reg[2]\ : in STD_LOGIC;
    \EX_Op2_reg[2]_0\ : in STD_LOGIC;
    \EX_Op2_reg[1]\ : in STD_LOGIC;
    \EX_Op2_reg[1]_0\ : in STD_LOGIC;
    \EX_Op2_reg[0]_1\ : in STD_LOGIC;
    \EX_Op2_reg[0]_2\ : in STD_LOGIC;
    GPR_Op3 : in STD_LOGIC_VECTOR ( 0 to 31 );
    \Using_FPGA.Native_i_5__0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    mem_valid_instr : in STD_LOGIC;
    mem_gpr_write : in STD_LOGIC;
    p_213_in : in STD_LOGIC;
    GPR_Op1 : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Op3[0]_i_2\ : in STD_LOGIC;
    \Using_FPGA.Native_i_5__0_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    p_216_in : in STD_LOGIC;
    \Using_FPGA.Native_i_5__0_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_mbar_is_sleep : in STD_LOGIC;
    ex_mbar_decode : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op3[0]_i_6\ : in STD_LOGIC;
    I4 : in STD_LOGIC;
    I0 : in STD_LOGIC;
    if_missed_fetch : in STD_LOGIC;
    \ex_gpr_write_dbg__0\ : in STD_LOGIC;
    ex_jump_nodelay : in STD_LOGIC;
    IReady : in STD_LOGIC;
    \Using_FPGA.Native_61\ : in STD_LOGIC;
    \Using_FPGA.Native_62\ : in STD_LOGIC;
    ex_branch_with_delayslot : in STD_LOGIC;
    ex_jump_q : in STD_LOGIC;
    \EX_Op1_reg[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ex_MSR : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_PreFetch_Buffer_gti : entity is "PreFetch_Buffer_gti";
end design_1_microblaze_0_0_PreFetch_Buffer_gti;

architecture STRUCTURE of design_1_microblaze_0_0_PreFetch_Buffer_gti is
  signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \EX_ALU_Op1142_out__0\ : STD_LOGIC;
  signal I0101_out : STD_LOGIC;
  signal I0105_out : STD_LOGIC;
  signal I0109_out : STD_LOGIC;
  signal I0113_out : STD_LOGIC;
  signal I0117_out : STD_LOGIC;
  signal I0121_out : STD_LOGIC;
  signal I0125_out : STD_LOGIC;
  signal I0129_out : STD_LOGIC;
  signal I0133_out : STD_LOGIC;
  signal I0137_out : STD_LOGIC;
  signal I013_out : STD_LOGIC;
  signal I0141_out : STD_LOGIC;
  signal I0145_out : STD_LOGIC;
  signal I0149_out : STD_LOGIC;
  signal I0153_out : STD_LOGIC;
  signal I0157_out : STD_LOGIC;
  signal I0161_out : STD_LOGIC;
  signal I0165_out : STD_LOGIC;
  signal I0169_out : STD_LOGIC;
  signal I017_out : STD_LOGIC;
  signal I021_out : STD_LOGIC;
  signal I025_out : STD_LOGIC;
  signal I029_out : STD_LOGIC;
  signal I033_out : STD_LOGIC;
  signal I037_out : STD_LOGIC;
  signal I041_out : STD_LOGIC;
  signal I045_out : STD_LOGIC;
  signal I049_out : STD_LOGIC;
  signal I053_out : STD_LOGIC;
  signal I057_out : STD_LOGIC;
  signal I05_out : STD_LOGIC;
  signal I061_out : STD_LOGIC;
  signal I065_out : STD_LOGIC;
  signal I069_out : STD_LOGIC;
  signal I073_out : STD_LOGIC;
  signal I077_out : STD_LOGIC;
  signal I081_out : STD_LOGIC;
  signal I085_out : STD_LOGIC;
  signal I089_out : STD_LOGIC;
  signal I093_out : STD_LOGIC;
  signal I097_out : STD_LOGIC;
  signal I09_out : STD_LOGIC;
  signal I0_1 : STD_LOGIC;
  signal I1 : STD_LOGIC;
  signal I1103_out : STD_LOGIC;
  signal I1107_out : STD_LOGIC;
  signal I1111_out : STD_LOGIC;
  signal I1115_out : STD_LOGIC;
  signal I1119_out : STD_LOGIC;
  signal I111_out : STD_LOGIC;
  signal I1123_out : STD_LOGIC;
  signal I1127_out : STD_LOGIC;
  signal I1131_out : STD_LOGIC;
  signal I1135_out : STD_LOGIC;
  signal I1139_out : STD_LOGIC;
  signal I1143_out : STD_LOGIC;
  signal I1147_out : STD_LOGIC;
  signal I1151_out : STD_LOGIC;
  signal I1155_out : STD_LOGIC;
  signal I1159_out : STD_LOGIC;
  signal I115_out : STD_LOGIC;
  signal I1163_out : STD_LOGIC;
  signal I1167_out : STD_LOGIC;
  signal I119_out : STD_LOGIC;
  signal I123_out : STD_LOGIC;
  signal I127_out : STD_LOGIC;
  signal I131_out : STD_LOGIC;
  signal I135_out : STD_LOGIC;
  signal I13_out : STD_LOGIC;
  signal I143_out : STD_LOGIC;
  signal I147_out : STD_LOGIC;
  signal I151_out : STD_LOGIC;
  signal I155_out : STD_LOGIC;
  signal I159_out : STD_LOGIC;
  signal I163_out : STD_LOGIC;
  signal I167_out : STD_LOGIC;
  signal I171_out : STD_LOGIC;
  signal I175_out : STD_LOGIC;
  signal I179_out : STD_LOGIC;
  signal I17_out : STD_LOGIC;
  signal I183_out : STD_LOGIC;
  signal I187_out : STD_LOGIC;
  signal I191_out : STD_LOGIC;
  signal I195_out : STD_LOGIC;
  signal I199_out : STD_LOGIC;
  signal I4_0 : STD_LOGIC;
  signal \^iready_0\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_3\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_10\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_11\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_12\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_13\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_14\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_15\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_16\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_17\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_3\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_4\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_5\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_6\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_7\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_8\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_9\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[18].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[19].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[20].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[22].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[23].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[25].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[27].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[28].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[29].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_3\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_5\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[30].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[31].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[32].Gen_Instr_DFF_n_33\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_3\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_13\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_1\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_3\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_2\ : STD_LOGIC;
  signal \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_3\ : STD_LOGIC;
  signal \OF_Op1_Sel_SPR_PC0__0\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \^using_fpga.native_1\ : STD_LOGIC;
  signal \^using_fpga.native_15\ : STD_LOGIC;
  signal \^using_fpga.native_2\ : STD_LOGIC;
  signal \^using_fpga.native_3\ : STD_LOGIC;
  signal \^using_fpga.native_4\ : STD_LOGIC_VECTOR ( 20 downto 0 );
  signal \^using_fpga.native_5\ : STD_LOGIC;
  signal ex_branch_with_delayslot_i : STD_LOGIC;
  signal \ex_gpr_write111_out__0\ : STD_LOGIC;
  signal \^ex_op1_cmp_eq1\ : STD_LOGIC;
  signal \ex_set_bip0__1\ : STD_LOGIC;
  signal \ibuffer_reg[3][42]_srl4_n_0\ : STD_LOGIC;
  signal \^if_pre_buffer_addr\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal if_sel_input : STD_LOGIC_VECTOR ( 1 to 2 );
  signal of_Imm180 : STD_LOGIC;
  signal of_Valid_II : STD_LOGIC;
  signal \^of_instr\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal of_instr_ii_0 : STD_LOGIC;
  signal of_instr_ii_1 : STD_LOGIC;
  signal of_instr_ii_10 : STD_LOGIC;
  signal of_instr_ii_11 : STD_LOGIC;
  signal of_instr_ii_12 : STD_LOGIC;
  signal of_instr_ii_13 : STD_LOGIC;
  signal of_instr_ii_14 : STD_LOGIC;
  signal of_instr_ii_15 : STD_LOGIC;
  signal of_instr_ii_16 : STD_LOGIC;
  signal of_instr_ii_17 : STD_LOGIC;
  signal of_instr_ii_18 : STD_LOGIC;
  signal of_instr_ii_19 : STD_LOGIC;
  signal of_instr_ii_2 : STD_LOGIC;
  signal of_instr_ii_20 : STD_LOGIC;
  signal of_instr_ii_21 : STD_LOGIC;
  signal of_instr_ii_22 : STD_LOGIC;
  signal of_instr_ii_23 : STD_LOGIC;
  signal of_instr_ii_24 : STD_LOGIC;
  signal of_instr_ii_25 : STD_LOGIC;
  signal of_instr_ii_26 : STD_LOGIC;
  signal of_instr_ii_27 : STD_LOGIC;
  signal of_instr_ii_28 : STD_LOGIC;
  signal of_instr_ii_29 : STD_LOGIC;
  signal of_instr_ii_3 : STD_LOGIC;
  signal of_instr_ii_30 : STD_LOGIC;
  signal of_instr_ii_31 : STD_LOGIC;
  signal of_instr_ii_32 : STD_LOGIC;
  signal of_instr_ii_33 : STD_LOGIC;
  signal of_instr_ii_34 : STD_LOGIC;
  signal of_instr_ii_35 : STD_LOGIC;
  signal of_instr_ii_36 : STD_LOGIC;
  signal of_instr_ii_37 : STD_LOGIC;
  signal of_instr_ii_38 : STD_LOGIC;
  signal of_instr_ii_39 : STD_LOGIC;
  signal of_instr_ii_4 : STD_LOGIC;
  signal of_instr_ii_40 : STD_LOGIC;
  signal of_instr_ii_41 : STD_LOGIC;
  signal of_instr_ii_42 : STD_LOGIC;
  signal of_instr_ii_5 : STD_LOGIC;
  signal of_instr_ii_6 : STD_LOGIC;
  signal of_instr_ii_7 : STD_LOGIC;
  signal of_instr_ii_8 : STD_LOGIC;
  signal of_instr_ii_9 : STD_LOGIC;
  signal of_op2_sel_imm : STD_LOGIC;
  signal \^of_predecode\ : STD_LOGIC_VECTOR ( 0 to 10 );
  signal \of_read_mem_write_op3_conflict__1\ : STD_LOGIC;
  signal \^of_use_op2_s\ : STD_LOGIC;
  signal p_0_in30_in : STD_LOGIC;
  signal p_1_in104_in : STD_LOGIC;
  signal p_1_in109_in : STD_LOGIC;
  signal p_1_in114_in : STD_LOGIC;
  signal p_1_in119_in : STD_LOGIC;
  signal p_1_in124_in : STD_LOGIC;
  signal p_1_in129_in : STD_LOGIC;
  signal p_1_in134_in : STD_LOGIC;
  signal p_1_in139_in : STD_LOGIC;
  signal p_1_in144_in : STD_LOGIC;
  signal p_1_in149_in : STD_LOGIC;
  signal p_1_in14_in : STD_LOGIC;
  signal p_1_in154_in : STD_LOGIC;
  signal p_1_in159_in : STD_LOGIC;
  signal p_1_in164_in : STD_LOGIC;
  signal p_1_in169_in : STD_LOGIC;
  signal p_1_in174_in : STD_LOGIC;
  signal p_1_in179_in : STD_LOGIC;
  signal p_1_in184_in : STD_LOGIC;
  signal p_1_in189_in : STD_LOGIC;
  signal p_1_in194_in : STD_LOGIC;
  signal p_1_in199_in : STD_LOGIC;
  signal p_1_in19_in : STD_LOGIC;
  signal p_1_in204_in : STD_LOGIC;
  signal p_1_in209_in : STD_LOGIC;
  signal p_1_in24_in : STD_LOGIC;
  signal p_1_in26_in : STD_LOGIC;
  signal p_1_in29_in : STD_LOGIC;
  signal p_1_in34_in : STD_LOGIC;
  signal p_1_in39_in : STD_LOGIC;
  signal p_1_in44_in : STD_LOGIC;
  signal p_1_in4_in : STD_LOGIC;
  signal p_1_in54_in : STD_LOGIC;
  signal p_1_in59_in : STD_LOGIC;
  signal p_1_in64_in : STD_LOGIC;
  signal p_1_in69_in : STD_LOGIC;
  signal p_1_in74_in : STD_LOGIC;
  signal p_1_in79_in : STD_LOGIC;
  signal p_1_in84_in : STD_LOGIC;
  signal p_1_in89_in : STD_LOGIC;
  signal p_1_in94_in : STD_LOGIC;
  signal p_1_in99_in : STD_LOGIC;
  signal p_1_in9_in : STD_LOGIC;
  signal p_28_in : STD_LOGIC;
  signal \^p_9_in\ : STD_LOGIC;
  signal sel_input_delayslot : STD_LOGIC;
  signal sel_input_i_0 : STD_LOGIC;
  signal sel_input_i_1 : STD_LOGIC;
  signal sel_input_iii_0 : STD_LOGIC;
  signal sel_input_iii_1 : STD_LOGIC;
  signal sel_input_iii_2 : STD_LOGIC;
  signal sel_input_iii_3 : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \ibuffer_reg[3][0]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name : string;
  attribute srl_name of \ibuffer_reg[3][0]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][0]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][10]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][10]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][10]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][11]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][11]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][11]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][12]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][12]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][12]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][13]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][13]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][13]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][14]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][14]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][14]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][15]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][15]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][15]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][16]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][16]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][16]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][17]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][17]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][17]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][18]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][18]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][18]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][19]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][19]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][19]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][1]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][1]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][1]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][20]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][20]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][20]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][21]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][21]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][21]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][22]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][22]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][22]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][23]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][23]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][23]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][24]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][24]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][24]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][25]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][25]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][25]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][26]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][26]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][26]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][27]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][27]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][27]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][28]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][28]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][28]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][29]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][29]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][29]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][2]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][2]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][2]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][30]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][30]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][30]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][31]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][31]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][31]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][32]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][32]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][32]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][33]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][33]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][33]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][34]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][34]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][34]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][35]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][35]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][35]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][36]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][36]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][36]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][37]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][37]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][37]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][38]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][38]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][38]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][39]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][39]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][39]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][3]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][3]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][3]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][40]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][40]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][40]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][41]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][41]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][41]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][42]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][42]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][42]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][4]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][4]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][4]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][5]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][5]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][5]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][6]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][6]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][6]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][7]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][7]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][7]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][8]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][8]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][8]_srl4 ";
  attribute srl_bus_name of \ibuffer_reg[3][9]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] ";
  attribute srl_name of \ibuffer_reg[3][9]_srl4\ : label is "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][9]_srl4 ";
begin
  D(1 downto 0) <= \^d\(1 downto 0);
  IReady_0 <= \^iready_0\;
  \Using_FPGA.Native\(1 downto 0) <= \^using_fpga.native\(1 downto 0);
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  \Using_FPGA.Native_1\ <= \^using_fpga.native_1\;
  \Using_FPGA.Native_15\ <= \^using_fpga.native_15\;
  \Using_FPGA.Native_2\ <= \^using_fpga.native_2\;
  \Using_FPGA.Native_3\ <= \^using_fpga.native_3\;
  \Using_FPGA.Native_4\(20 downto 0) <= \^using_fpga.native_4\(20 downto 0);
  \Using_FPGA.Native_5\ <= \^using_fpga.native_5\;
  ex_op1_cmp_eq1 <= \^ex_op1_cmp_eq1\;
  if_pre_buffer_addr(0) <= \^if_pre_buffer_addr\(0);
  of_instr(5 downto 0) <= \^of_instr\(5 downto 0);
  of_predecode(0 to 10) <= \^of_predecode\(0 to 10);
  of_use_op2_s <= \^of_use_op2_s\;
  p_9_in <= \^p_9_in\;
\Gen_Mux_Select_LUT6[1].Gen_Sel_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_112
     port map (
      Clk => Clk,
      IB_Ready => IB_Ready,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_17\,
      addr(0) => \^using_fpga.native\(1),
      ex_jump => ex_jump,
      if_fetch_in_progress => if_fetch_in_progress,
      if_sel_input(0) => if_sel_input(1),
      \out\ => \out\,
      sel_input_iii_3 => sel_input_iii_3,
      sync_reset => sync_reset
    );
\Gen_Mux_Select_LUT6[1].Mux_Select_LUT6\: entity work.design_1_microblaze_0_0_MB_LUT6
     port map (
      I5 => I5,
      \Using_FPGA.Native_0\ => \^iready_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_60\,
      addr(0) => \^using_fpga.native\(1),
      if_sel_input(0) => if_sel_input(1),
      sel_input_iii_3 => sel_input_iii_3
    );
\Gen_Mux_Select_LUT6[2].Gen_Sel_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_113
     port map (
      Clk => Clk,
      IB_Ready => IB_Ready,
      \Serial_Dbg_Intf.status_reg_reg[25]\(0) => \^using_fpga.native\(1),
      \Using_FPGA.Native_0\(1 downto 0) => \Using_FPGA.Native_6\(1 downto 0),
      addr(0) => \^if_pre_buffer_addr\(0),
      ex_jump => ex_jump,
      if_fetch_for_timing_optimization1 => if_fetch_for_timing_optimization1,
      if_fetch_in_progress => if_fetch_in_progress,
      if_fetch_in_progress_reg(0) => if_fetch_in_progress_reg(0),
      if_missed_fetch => if_missed_fetch,
      if_missed_fetch_reg => if_missed_fetch_reg,
      if_sel_input(0) => if_sel_input(1),
      in0 => in0,
      \out\ => \out\,
      sel_input_iii_2 => sel_input_iii_2,
      sync_reset => sync_reset
    );
\Gen_Mux_Select_LUT6[2].Mux_Select_LUT6\: entity work.design_1_microblaze_0_0_MB_LUT6_114
     port map (
      I5 => I5,
      \Using_FPGA.Native_0\ => \^iready_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_60\,
      addr(0) => \^using_fpga.native\(1),
      if_sel_input(1) => if_sel_input(1),
      if_sel_input(0) => if_sel_input(2),
      sel_input_iii_2 => sel_input_iii_2
    );
\Gen_Mux_Select_LUT6[3].Gen_Sel_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_115
     port map (
      Clk => Clk,
      if_sel_input(0) => if_sel_input(2),
      sel_input_iii_1 => sel_input_iii_1,
      sync_reset => sync_reset
    );
\Gen_Mux_Select_LUT6[3].Mux_Select_LUT6\: entity work.design_1_microblaze_0_0_MB_LUT6_116
     port map (
      I5 => I5,
      \Using_FPGA.Native_0\ => \^using_fpga.native_0\,
      \Using_FPGA.Native_1\ => \^iready_0\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_60\,
      if_sel_input(1) => if_sel_input(1),
      if_sel_input(0) => if_sel_input(2),
      sel_input_iii_1 => sel_input_iii_1
    );
\Gen_Mux_Select_LUT6[4].Gen_Sel_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_117
     port map (
      Clk => Clk,
      I1 => I1,
      I1103_out => I1103_out,
      I1107_out => I1107_out,
      I1111_out => I1111_out,
      I1115_out => I1115_out,
      I1119_out => I1119_out,
      I111_out => I111_out,
      I1123_out => I1123_out,
      I1127_out => I1127_out,
      I1131_out => I1131_out,
      I1135_out => I1135_out,
      I1139_out => I1139_out,
      I1143_out => I1143_out,
      I1147_out => I1147_out,
      I1151_out => I1151_out,
      I1155_out => I1155_out,
      I1159_out => I1159_out,
      I115_out => I115_out,
      I1163_out => I1163_out,
      I1167_out => I1167_out,
      I119_out => I119_out,
      I123_out => I123_out,
      I127_out => I127_out,
      I131_out => I131_out,
      I135_out => I135_out,
      I13_out => I13_out,
      I143_out => I143_out,
      I147_out => I147_out,
      I151_out => I151_out,
      I155_out => I155_out,
      I159_out => I159_out,
      I163_out => I163_out,
      I167_out => I167_out,
      I171_out => I171_out,
      I175_out => I175_out,
      I179_out => I179_out,
      I17_out => I17_out,
      I183_out => I183_out,
      I187_out => I187_out,
      I191_out => I191_out,
      I195_out => I195_out,
      I199_out => I199_out,
      \Using_FPGA.Native_0\ => \^using_fpga.native_0\,
      \in\(31 downto 10) => \in\(32 downto 11),
      \in\(9 downto 0) => \in\(9 downto 0),
      \out\(41) => p_1_in209_in,
      \out\(40) => p_1_in204_in,
      \out\(39) => p_1_in199_in,
      \out\(38) => p_1_in194_in,
      \out\(37) => p_1_in189_in,
      \out\(36) => p_1_in184_in,
      \out\(35) => p_1_in179_in,
      \out\(34) => p_1_in174_in,
      \out\(33) => p_1_in169_in,
      \out\(32) => p_1_in164_in,
      \out\(31) => p_1_in159_in,
      \out\(30) => p_1_in154_in,
      \out\(29) => p_1_in149_in,
      \out\(28) => p_1_in144_in,
      \out\(27) => p_1_in139_in,
      \out\(26) => p_1_in134_in,
      \out\(25) => p_1_in129_in,
      \out\(24) => p_1_in124_in,
      \out\(23) => p_1_in119_in,
      \out\(22) => p_1_in114_in,
      \out\(21) => p_1_in109_in,
      \out\(20) => p_1_in104_in,
      \out\(19) => p_1_in99_in,
      \out\(18) => p_1_in94_in,
      \out\(17) => p_1_in89_in,
      \out\(16) => p_1_in84_in,
      \out\(15) => p_1_in79_in,
      \out\(14) => p_1_in74_in,
      \out\(13) => p_1_in69_in,
      \out\(12) => p_1_in64_in,
      \out\(11) => p_1_in59_in,
      \out\(10) => p_1_in54_in,
      \out\(9) => p_1_in44_in,
      \out\(8) => p_1_in39_in,
      \out\(7) => p_1_in34_in,
      \out\(6) => p_1_in29_in,
      \out\(5) => p_1_in24_in,
      \out\(4) => p_1_in19_in,
      \out\(3) => p_1_in14_in,
      \out\(2) => p_1_in9_in,
      \out\(1) => p_1_in4_in,
      \out\(0) => \ibuffer_reg[3][42]_srl4_n_0\,
      sel_input_i_1 => sel_input_i_1,
      sync_reset => sync_reset
    );
\Gen_Mux_Select_LUT6[4].Mux_Select_LUT6\: entity work.design_1_microblaze_0_0_MB_LUT6_118
     port map (
      I5 => I5,
      \Using_FPGA.Native_0\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_1\ => \^using_fpga.native_0\,
      \Using_FPGA.Native_2\ => \^iready_0\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_60\,
      if_sel_input(0) => if_sel_input(2),
      sel_input_iii_0 => sel_input_iii_0
    );
\Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Mux_Select_Delayslot_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized2\
     port map (
      I5 => I5,
      \Using_FPGA.Native_0\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_1\ => \^using_fpga.native_0\,
      \Using_FPGA.Native_2\ => \^iready_0\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_60\,
      if_sel_input(0) => if_sel_input(2),
      sel_input_delayslot => sel_input_delayslot
    );
\Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Sel_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7
     port map (
      I4_0 => I4_0,
      Q(1 downto 0) => Q(1 downto 0),
      ex_branch_with_delayslot_i => ex_branch_with_delayslot_i,
      sel_input_delayslot => sel_input_delayslot,
      sel_input_i_1 => sel_input_i_1,
      sel_input_iii_0 => sel_input_iii_0,
      wb_exception => wb_exception
    );
\Instruction_Prefetch_Mux[0].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_119
     port map (
      Clk => Clk,
      \EX_ALU_Op1142_out__0\ => \EX_ALU_Op1142_out__0\,
      EX_CMP_Op_reg => \^using_fpga.native_4\(0),
      EX_Unsigned_Op_reg => \^of_instr\(3),
      EX_Unsigned_Op_reg_0 => \^using_fpga.native_4\(1),
      EX_Use_Carry_reg => \^of_instr\(1),
      \OF_Op1_Sel_SPR_PC0__0\ => \OF_Op1_Sel_SPR_PC0__0\,
      \Using_FPGA.Native_0\ => \^of_instr\(5),
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_18\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_19\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_20\,
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_21\,
      \Using_FPGA.Native_5\ => \Using_FPGA.Native_25\,
      \Using_FPGA.Native_6\ => \^of_instr\(2),
      \Using_FPGA.Native_7\ => \^of_instr\(4),
      ex_jump => ex_jump,
      ex_jump_nodelay => ex_jump_nodelay,
      of_instr_ii_42 => of_instr_ii_42,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[0].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_120
     port map (
      I0169_out => I0169_out,
      I1167_out => I1167_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_42 => of_instr_ii_42
    );
\Instruction_Prefetch_Mux[10].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_121
     port map (
      Clk => Clk,
      \EX_Op3[0]_i_4\(2 downto 0) => \Using_FPGA.Native_i_5__0\(2 downto 0),
      \EX_Op3[0]_i_5\(2 downto 0) => \Using_FPGA.Native_i_5__0_0\(2 downto 0),
      \EX_Op3[0]_i_6\ => \^using_fpga.native_1\,
      \EX_Op3[0]_i_6_0\ => \^using_fpga.native_2\,
      \EX_Op3[0]_i_6_1\ => \EX_Op3[0]_i_6\,
      I0 => I0,
      I4 => I4,
      \Using_FPGA.Native_0\ => \^using_fpga.native_3\,
      \ex_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_3\,
      \mem_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_1\,
      of_instr_ii_32 => of_instr_ii_32,
      sync_reset => sync_reset,
      \wb_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_2\
    );
\Instruction_Prefetch_Mux[10].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_122
     port map (
      I0129_out => I0129_out,
      I1127_out => I1127_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_32 => of_instr_ii_32
    );
\Instruction_Prefetch_Mux[11].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_123
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(20),
      \ex_set_bip0__1\ => \ex_set_bip0__1\,
      ex_set_bip_reg => \^using_fpga.native_4\(18),
      ex_set_bip_reg_0 => \^using_fpga.native_4\(19),
      of_instr_ii_31 => of_instr_ii_31,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[11].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_124
     port map (
      I0125_out => I0125_out,
      I1123_out => I1123_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_31 => of_instr_ii_31
    );
\Instruction_Prefetch_Mux[12].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_125
     port map (
      Clk => Clk,
      \EX_ALU_Op1142_out__0\ => \EX_ALU_Op1142_out__0\,
      \EX_ALU_Op_reg[1]\ => \^of_instr\(0),
      \EX_ALU_Op_reg[1]_0\ => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4\,
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(19),
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_9\(0),
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_10\,
      ex_enable_alu_i_reg => \^of_instr\(5),
      ex_enable_alu_i_reg_0 => \^of_instr\(2),
      ex_enable_alu_i_reg_1 => \^of_instr\(4),
      ex_enable_alu_i_reg_2 => \^of_instr\(3),
      ex_enable_alu_i_reg_3 => \^using_fpga.native_4\(10),
      of_instr_ii_30 => of_instr_ii_30,
      p_28_in => p_28_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[12].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_126
     port map (
      I0121_out => I0121_out,
      I1119_out => I1119_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_30 => of_instr_ii_30
    );
\Instruction_Prefetch_Mux[13].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_127
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(18),
      of_instr_ii_29 => of_instr_ii_29,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[13].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_128
     port map (
      I0117_out => I0117_out,
      I1115_out => I1115_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_29 => of_instr_ii_29
    );
\Instruction_Prefetch_Mux[14].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_129
     port map (
      Clk => Clk,
      E(0) => E(0),
      \Using_FPGA.Native_0\(0) => \^using_fpga.native_4\(17),
      \Using_FPGA.Native_1\ => ex_mbar_decode_cmb,
      ex_mbar_decode => ex_mbar_decode,
      ex_mbar_decode_reg => \Using_FPGA.Native_60\,
      of_instr_ii_28 => of_instr_ii_28,
      p_1_in26_in => p_1_in26_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[14].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_130
     port map (
      I0113_out => I0113_out,
      I1111_out => I1111_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_28 => of_instr_ii_28
    );
\Instruction_Prefetch_Mux[15].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_131
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\(0) => \^using_fpga.native_4\(16),
      of_instr_ii_27 => of_instr_ii_27,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[15].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_132
     port map (
      I0109_out => I0109_out,
      I1107_out => I1107_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_27 => of_instr_ii_27
    );
\Instruction_Prefetch_Mux[16].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_133
     port map (
      Clk => Clk,
      \EX_Op2_reg[0]\(15 downto 0) => \EX_Op2_reg[0]\(15 downto 0),
      \EX_Op2_reg[0]_0\ => \EX_Op2_reg[0]_0\,
      GPR_Op2(16) => GPR_Op2(0),
      GPR_Op2(15) => GPR_Op2(1),
      GPR_Op2(14) => GPR_Op2(2),
      GPR_Op2(13) => GPR_Op2(3),
      GPR_Op2(12) => GPR_Op2(4),
      GPR_Op2(11) => GPR_Op2(5),
      GPR_Op2(10) => GPR_Op2(6),
      GPR_Op2(9) => GPR_Op2(7),
      GPR_Op2(8) => GPR_Op2(8),
      GPR_Op2(7) => GPR_Op2(9),
      GPR_Op2(6) => GPR_Op2(10),
      GPR_Op2(5) => GPR_Op2(11),
      GPR_Op2(4) => GPR_Op2(12),
      GPR_Op2(3) => GPR_Op2(13),
      GPR_Op2(2) => GPR_Op2(14),
      GPR_Op2(1) => GPR_Op2(15),
      GPR_Op2(0) => GPR_Op2(16),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(15),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_1\,
      \imm_reg_reg[0]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_17\,
      \imm_reg_reg[10]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_7\,
      \imm_reg_reg[11]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_6\,
      \imm_reg_reg[12]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_5\,
      \imm_reg_reg[13]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_4\,
      \imm_reg_reg[14]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_3\,
      \imm_reg_reg[15]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_2\,
      \imm_reg_reg[1]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_16\,
      \imm_reg_reg[2]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_15\,
      \imm_reg_reg[3]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_14\,
      \imm_reg_reg[4]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_13\,
      \imm_reg_reg[5]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_12\,
      \imm_reg_reg[6]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_11\,
      \imm_reg_reg[7]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_10\,
      \imm_reg_reg[8]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_9\,
      \imm_reg_reg[9]\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_8\,
      of_instr_ii_26 => of_instr_ii_26,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[16].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_134
     port map (
      I0105_out => I0105_out,
      I1103_out => I1103_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_26 => of_instr_ii_26
    );
\Instruction_Prefetch_Mux[17].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_135
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(17),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\ => \^using_fpga.native_4\(13),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ => \^using_fpga.native_4\(15),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(14),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_2\ => \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_2\,
      of_instr_ii_25 => of_instr_ii_25,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[17].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_136
     port map (
      I0101_out => I0101_out,
      I199_out => I199_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_25 => of_instr_ii_25
    );
\Instruction_Prefetch_Mux[18].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_137
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(18),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(13),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[18].Gen_Instr_DFF_n_1\,
      of_instr_ii_24 => of_instr_ii_24,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[18].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_138
     port map (
      I097_out => I097_out,
      I195_out => I195_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_24 => of_instr_ii_24
    );
\Instruction_Prefetch_Mux[19].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_139
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(19),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(12),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[19].Gen_Instr_DFF_n_1\,
      of_instr_ii_23 => of_instr_ii_23,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[19].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_140
     port map (
      I093_out => I093_out,
      I191_out => I191_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_23 => of_instr_ii_23
    );
\Instruction_Prefetch_Mux[1].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_141
     port map (
      Clk => Clk,
      E(0) => E(0),
      \EX_ALU_Op1142_out__0\ => \EX_ALU_Op1142_out__0\,
      \EX_ALU_Op_reg[0]\ => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4\,
      \EX_Op2[0]_i_2\ => \^of_instr\(3),
      \Using_FPGA.Native_0\ => \^of_instr\(4),
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_9\(1),
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_27\,
      \ex_gpr_write111_out__0\ => \ex_gpr_write111_out__0\,
      \ex_gpr_write_dbg__0\ => \ex_gpr_write_dbg__0\,
      ex_gpr_write_dbg_reg => \^using_fpga.native_4\(3),
      ex_gpr_write_dbg_reg_0 => \^using_fpga.native_4\(2),
      ex_gpr_write_i_2_0 => \^using_fpga.native_4\(18),
      ex_gpr_write_i_2_1 => \Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2\,
      ex_gpr_write_i_2_2 => \^using_fpga.native_4\(14),
      ex_gpr_write_i_2_3 => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_1\,
      ex_gpr_write_reg => ex_gpr_write_reg,
      ex_gpr_write_reg_0 => ex_gpr_write_reg_0,
      ex_gpr_write_reg_1 => \Using_FPGA.Native_60\,
      ex_set_bip => ex_set_bip,
      \ex_set_bip0__1\ => \ex_set_bip0__1\,
      ex_set_bip_reg => \^of_instr\(5),
      ex_set_bip_reg_0 => \^of_instr\(1),
      ex_set_bip_reg_1 => \^of_instr\(2),
      ex_set_bip_reg_2 => \^of_instr\(0),
      of_instr_ii_41 => of_instr_ii_41,
      of_op2_sel_imm => of_op2_sel_imm,
      of_use_op2_s => \^of_use_op2_s\,
      p_0_in30_in => p_0_in30_in,
      p_28_in => p_28_in,
      sync_reset => sync_reset,
      wb_exception => wb_exception,
      wb_exception_i_reg => wb_exception_i_reg
    );
\Instruction_Prefetch_Mux[1].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_142
     port map (
      I0165_out => I0165_out,
      I1163_out => I1163_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_41 => of_instr_ii_41
    );
\Instruction_Prefetch_Mux[20].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_143
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(20),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2\ => \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0\ => \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_2\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ => \^using_fpga.native_4\(12),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\ => \^using_fpga.native_4\(9),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2\ => \^using_fpga.native_4\(10),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(11),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[20].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_24\,
      \ex_set_bip0__1\ => \ex_set_bip0__1\,
      of_Imm180 => of_Imm180,
      of_instr_ii_22 => of_instr_ii_22,
      of_op2_sel_imm => of_op2_sel_imm,
      p_1_in26_in => p_1_in26_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[20].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_144
     port map (
      I089_out => I089_out,
      I187_out => I187_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_22 => of_instr_ii_22
    );
\Instruction_Prefetch_Mux[21].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_145
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(21),
      \Performance_Debug_Control.ex_brki_hit_reg\ => \^using_fpga.native_4\(9),
      \Performance_Debug_Control.ex_brki_hit_reg_0\ => \^using_fpga.native_4\(12),
      \Performance_Debug_Control.ex_brki_hit_reg_1\(0) => \^using_fpga.native_4\(11),
      \Performance_Debug_Control.ex_brki_hit_reg_2\ => \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2\,
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(10),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_2\ => \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_2\,
      of_instr_ii_21 => of_instr_ii_21,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[21].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_146
     port map (
      I085_out => I085_out,
      I183_out => I183_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_21 => of_instr_ii_21
    );
\Instruction_Prefetch_Mux[22].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_147
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(22),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(9),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[22].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_26\,
      \Using_FPGA.Native_3\ => \^of_instr\(3),
      of_instr_ii_20 => of_instr_ii_20,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[22].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_148
     port map (
      I081_out => I081_out,
      I179_out => I179_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_20 => of_instr_ii_20
    );
\Instruction_Prefetch_Mux[23].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_149
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(23),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(8),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[23].Gen_Instr_DFF_n_1\,
      of_instr_ii_19 => of_instr_ii_19,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[23].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_150
     port map (
      I077_out => I077_out,
      I175_out => I175_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_19 => of_instr_ii_19
    );
\Instruction_Prefetch_Mux[24].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_151
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(24),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\ => \^using_fpga.native_4\(8),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ => \^using_fpga.native_4\(5),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\ => \^using_fpga.native_4\(6),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(7),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_2\ => \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2\,
      of_instr_ii_18 => of_instr_ii_18,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[24].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_152
     port map (
      I073_out => I073_out,
      I171_out => I171_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_18 => of_instr_ii_18
    );
\Instruction_Prefetch_Mux[25].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_153
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(25),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(6),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[25].Gen_Instr_DFF_n_1\,
      of_instr_ii_17 => of_instr_ii_17,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[25].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_154
     port map (
      I069_out => I069_out,
      I167_out => I167_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_17 => of_instr_ii_17
    );
\Instruction_Prefetch_Mux[26].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_155
     port map (
      Clk => Clk,
      \EX_Sext_Op_reg[0]\ => \^using_fpga.native_4\(6),
      GPR_Op2(0) => GPR_Op2(26),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(5),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_2\ => \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_2\,
      of_instr_ii_16 => of_instr_ii_16,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[26].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_156
     port map (
      I065_out => I065_out,
      I163_out => I163_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_16 => of_instr_ii_16
    );
\Instruction_Prefetch_Mux[27].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_157
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(27),
      \Performance_Debug_Control.ex_brki_hit_reg\(0) => \Performance_Debug_Control.ex_brki_hit_reg\(0),
      \Performance_Debug_Control.ex_brki_hit_reg_0\ => \^using_fpga.native_4\(15),
      \Performance_Debug_Control.ex_brki_hit_reg_1\ => \^using_fpga.native_4\(13),
      \Performance_Debug_Control.ex_brki_hit_reg_2\ => \^using_fpga.native_4\(14),
      \Performance_Debug_Control.ex_brki_hit_reg_3\ => \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_2\,
      \Performance_Debug_Control.ex_brki_hit_reg_4\ => \^using_fpga.native_4\(20),
      \Performance_Debug_Control.ex_brki_hit_reg_5\ => \^using_fpga.native_4\(18),
      \Performance_Debug_Control.ex_brki_hit_reg_6\ => \^using_fpga.native_4\(19),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3\ => \^using_fpga.native_4\(2),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0\ => \^using_fpga.native_4\(3),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1\ => \^using_fpga.native_4\(1),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2\ => \^using_fpga.native_4\(0),
      \Serial_Dbg_Intf.control_reg_reg[8]\ => \Serial_Dbg_Intf.control_reg_reg[8]\,
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(4),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[27].Gen_Instr_DFF_n_1\,
      of_Imm180 => of_Imm180,
      of_instr_ii_15 => of_instr_ii_15,
      of_op2_sel_imm => of_op2_sel_imm,
      p_1_in26_in => p_1_in26_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[27].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_158
     port map (
      I061_out => I061_out,
      I159_out => I159_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_15 => of_instr_ii_15
    );
\Instruction_Prefetch_Mux[28].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_159
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(28),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(3),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[28].Gen_Instr_DFF_n_2\,
      ex_move_to_MSR_instr93_out => ex_move_to_MSR_instr93_out,
      ex_move_to_MSR_instr_reg => \^using_fpga.native_4\(1),
      ex_move_to_MSR_instr_reg_0 => \^using_fpga.native_4\(2),
      ex_move_to_MSR_instr_reg_1 => \^using_fpga.native_4\(0),
      ex_move_to_MSR_instr_reg_2 => \Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2\,
      ex_move_to_MSR_instr_reg_3 => \^using_fpga.native_4\(14),
      of_instr_ii_14 => of_instr_ii_14,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[28].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_160
     port map (
      I057_out => I057_out,
      I155_out => I155_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_14 => of_instr_ii_14
    );
\Instruction_Prefetch_Mux[29].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_161
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(29),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(2),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[29].Gen_Instr_DFF_n_1\,
      of_instr_ii_13 => of_instr_ii_13,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[29].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_162
     port map (
      I053_out => I053_out,
      I151_out => I151_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_13 => of_instr_ii_13
    );
\Instruction_Prefetch_Mux[2].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_163
     port map (
      Clk => Clk,
      \EX_ALU_Op_reg[0]\ => \^using_fpga.native_4\(10),
      \Using_FPGA.Native_0\ => \^of_instr\(3),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_2\ => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_3\,
      \Using_FPGA.Native_3\ => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4\,
      \Using_FPGA.Native_4\ => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_5\,
      \Using_FPGA.Native_5\ => \^of_instr\(0),
      \Using_FPGA.Native_6\ => \^of_instr\(5),
      ex_mbar_decode_reg => \^of_instr\(2),
      ex_mbar_decode_reg_0 => \^of_instr\(1),
      ex_mbar_decode_reg_1 => \^of_instr\(4),
      of_instr_ii_40 => of_instr_ii_40,
      p_1_in26_in => p_1_in26_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[2].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_164
     port map (
      I0161_out => I0161_out,
      I1159_out => I1159_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_40 => of_instr_ii_40
    );
\Instruction_Prefetch_Mux[30].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_165
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(30),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(1),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[30].Gen_Instr_DFF_n_1\,
      of_instr_ii_12 => of_instr_ii_12,
      of_op2_sel_imm => of_op2_sel_imm,
      p_2_in => p_2_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[30].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_166
     port map (
      I049_out => I049_out,
      I147_out => I147_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_12 => of_instr_ii_12
    );
\Instruction_Prefetch_Mux[31].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_167
     port map (
      Clk => Clk,
      GPR_Op2(0) => GPR_Op2(31),
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\(0),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[31].Gen_Instr_DFF_n_1\,
      of_instr_ii_11 => of_instr_ii_11,
      of_op2_sel_imm => of_op2_sel_imm,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[31].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_168
     port map (
      I045_out => I045_out,
      I143_out => I143_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_11 => of_instr_ii_11
    );
\Instruction_Prefetch_Mux[32].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_169
     port map (
      Clk => Clk,
      \EX_Op3[0]_i_2_0\(0) => \Using_FPGA.Native_i_5__0_1\(0),
      \EX_Op3[0]_i_2_1\ => \^d\(0),
      \EX_Op3[0]_i_2_2\ => \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_3\,
      \EX_Op3[0]_i_2_3\ => \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_3\,
      \EX_Op3[0]_i_2_4\ => \EX_Op3[0]_i_2\,
      \EX_Op3[0]_i_2_5\(0) => \Using_FPGA.Native_i_5__0_0\(3),
      \EX_Op3[0]_i_2_6\ => \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_2\,
      \EX_Op3[0]_i_2_7\ => \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_2\,
      \EX_Op3_reg[0]\ => \EX_Op2_reg[0]_1\,
      \EX_Op3_reg[0]_0\ => \EX_Op2_reg[0]_2\,
      \EX_Op3_reg[10]\ => \EX_Op2_reg[10]\,
      \EX_Op3_reg[10]_0\ => \EX_Op2_reg[10]_0\,
      \EX_Op3_reg[11]\ => \EX_Op2_reg[11]\,
      \EX_Op3_reg[11]_0\ => \EX_Op2_reg[11]_0\,
      \EX_Op3_reg[12]\ => \EX_Op2_reg[12]\,
      \EX_Op3_reg[12]_0\ => \EX_Op2_reg[12]_0\,
      \EX_Op3_reg[13]\ => \EX_Op2_reg[13]\,
      \EX_Op3_reg[13]_0\ => \EX_Op2_reg[13]_0\,
      \EX_Op3_reg[14]\ => \EX_Op2_reg[14]\,
      \EX_Op3_reg[14]_0\ => \EX_Op2_reg[14]_0\,
      \EX_Op3_reg[15]\ => \EX_Op2_reg[15]\,
      \EX_Op3_reg[15]_0\ => \EX_Op2_reg[15]_0\,
      \EX_Op3_reg[16]\ => \EX_Op2_reg[16]_0\,
      \EX_Op3_reg[16]_0\(7 downto 0) => \EX_Op2_reg[16]\(7 downto 0),
      \EX_Op3_reg[17]\ => \EX_Op2_reg[17]\,
      \EX_Op3_reg[18]\ => \EX_Op2_reg[18]\,
      \EX_Op3_reg[19]\ => \EX_Op2_reg[19]\,
      \EX_Op3_reg[1]\ => \EX_Op2_reg[1]\,
      \EX_Op3_reg[1]_0\ => \EX_Op2_reg[1]_0\,
      \EX_Op3_reg[20]\ => \EX_Op2_reg[20]\,
      \EX_Op3_reg[21]\ => \EX_Op2_reg[21]\,
      \EX_Op3_reg[22]\ => \EX_Op2_reg[22]\,
      \EX_Op3_reg[23]\ => \EX_Op2_reg[23]\,
      \EX_Op3_reg[24]\ => \EX_Op2_reg[24]\,
      \EX_Op3_reg[24]_0\ => \EX_Op2_reg[24]_0\,
      \EX_Op3_reg[25]\ => \EX_Op2_reg[25]\,
      \EX_Op3_reg[25]_0\ => \EX_Op2_reg[25]_0\,
      \EX_Op3_reg[26]\ => \EX_Op2_reg[26]\,
      \EX_Op3_reg[26]_0\ => \EX_Op2_reg[26]_0\,
      \EX_Op3_reg[27]\ => \EX_Op2_reg[27]\,
      \EX_Op3_reg[27]_0\ => \EX_Op2_reg[27]_0\,
      \EX_Op3_reg[28]\ => \EX_Op2_reg[28]\,
      \EX_Op3_reg[28]_0\ => \EX_Op2_reg[28]_0\,
      \EX_Op3_reg[29]\ => \EX_Op2_reg[29]\,
      \EX_Op3_reg[29]_0\ => \EX_Op2_reg[29]_0\,
      \EX_Op3_reg[2]\ => \EX_Op2_reg[2]\,
      \EX_Op3_reg[2]_0\ => \EX_Op2_reg[2]_0\,
      \EX_Op3_reg[30]\ => \EX_Op2_reg[30]\,
      \EX_Op3_reg[30]_0\ => \EX_Op2_reg[30]_0\,
      \EX_Op3_reg[31]\ => \EX_Op2_reg[31]\,
      \EX_Op3_reg[31]_0\ => \EX_Op2_reg[31]_0\,
      \EX_Op3_reg[3]\ => \EX_Op2_reg[3]\,
      \EX_Op3_reg[3]_0\ => \EX_Op2_reg[3]_0\,
      \EX_Op3_reg[4]\ => \EX_Op2_reg[4]\,
      \EX_Op3_reg[4]_0\ => \EX_Op2_reg[4]_0\,
      \EX_Op3_reg[5]\ => \EX_Op2_reg[5]\,
      \EX_Op3_reg[5]_0\ => \EX_Op2_reg[5]_0\,
      \EX_Op3_reg[6]\ => \EX_Op2_reg[6]\,
      \EX_Op3_reg[6]_0\ => \EX_Op2_reg[6]_0\,
      \EX_Op3_reg[7]\ => \EX_Op2_reg[7]\,
      \EX_Op3_reg[7]_0\ => \EX_Op2_reg[7]_0\,
      \EX_Op3_reg[8]\ => \EX_Op2_reg[8]\,
      \EX_Op3_reg[8]_0\ => \EX_Op2_reg[8]_0\,
      \EX_Op3_reg[9]\ => \EX_Op2_reg[9]\,
      \EX_Op3_reg[9]_0\ => \EX_Op2_reg[9]_0\,
      GPR_Op3(0 to 31) => GPR_Op3(0 to 31),
      MEM_Fwd(0 to 31) => MEM_Fwd(0 to 31),
      \Using_FPGA.Native_0\ => \^of_predecode\(0),
      ex_sel_alu_i_reg(31 downto 0) => ex_sel_alu_i_reg_0(31 downto 0),
      mem_gpr_write => mem_gpr_write,
      mem_valid_instr => mem_valid_instr,
      mem_valid_reg => \Instruction_Prefetch_Mux[32].Gen_Instr_DFF_n_33\,
      of_instr_ii_10 => of_instr_ii_10,
      \of_read_mem_write_op3_conflict__1\ => \of_read_mem_write_op3_conflict__1\,
      p_216_in => p_216_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[32].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_170
     port map (
      I041_out => I041_out,
      I139_out => I139_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_10 => of_instr_ii_10
    );
\Instruction_Prefetch_Mux[33].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_171
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[0]\ => \EX_Op2_reg[0]_1\,
      \EX_Branch_CMP_Op1_reg[0]_0\ => \EX_Op2_reg[0]_2\,
      \EX_Branch_CMP_Op1_reg[10]\ => \EX_Op2_reg[10]\,
      \EX_Branch_CMP_Op1_reg[10]_0\ => \EX_Op2_reg[10]_0\,
      \EX_Branch_CMP_Op1_reg[11]\ => \EX_Op2_reg[11]\,
      \EX_Branch_CMP_Op1_reg[11]_0\ => \EX_Op2_reg[11]_0\,
      \EX_Branch_CMP_Op1_reg[12]\ => \EX_Op2_reg[12]\,
      \EX_Branch_CMP_Op1_reg[12]_0\ => \EX_Op2_reg[12]_0\,
      \EX_Branch_CMP_Op1_reg[13]\ => \EX_Op2_reg[13]\,
      \EX_Branch_CMP_Op1_reg[13]_0\ => \EX_Op2_reg[13]_0\,
      \EX_Branch_CMP_Op1_reg[14]\ => \EX_Op2_reg[14]\,
      \EX_Branch_CMP_Op1_reg[14]_0\ => \EX_Op2_reg[14]_0\,
      \EX_Branch_CMP_Op1_reg[15]\ => \EX_Op2_reg[15]\,
      \EX_Branch_CMP_Op1_reg[15]_0\ => \EX_Op2_reg[15]_0\,
      \EX_Branch_CMP_Op1_reg[16]\ => \EX_Op2_reg[16]_0\,
      \EX_Branch_CMP_Op1_reg[16]_0\(7 downto 0) => \EX_Op2_reg[16]\(7 downto 0),
      \EX_Branch_CMP_Op1_reg[17]\ => \EX_Op2_reg[17]\,
      \EX_Branch_CMP_Op1_reg[18]\ => \EX_Op2_reg[18]\,
      \EX_Branch_CMP_Op1_reg[19]\ => \EX_Op2_reg[19]\,
      \EX_Branch_CMP_Op1_reg[1]\ => \EX_Op2_reg[1]\,
      \EX_Branch_CMP_Op1_reg[1]_0\ => \EX_Op2_reg[1]_0\,
      \EX_Branch_CMP_Op1_reg[20]\ => \EX_Op2_reg[20]\,
      \EX_Branch_CMP_Op1_reg[21]\ => \EX_Op2_reg[21]\,
      \EX_Branch_CMP_Op1_reg[22]\ => \EX_Op2_reg[22]\,
      \EX_Branch_CMP_Op1_reg[23]\ => \EX_Op2_reg[23]\,
      \EX_Branch_CMP_Op1_reg[24]\ => \EX_Op2_reg[24]\,
      \EX_Branch_CMP_Op1_reg[24]_0\ => \EX_Op2_reg[24]_0\,
      \EX_Branch_CMP_Op1_reg[25]\ => \EX_Op2_reg[25]\,
      \EX_Branch_CMP_Op1_reg[25]_0\ => \EX_Op2_reg[25]_0\,
      \EX_Branch_CMP_Op1_reg[26]\ => \EX_Op2_reg[26]\,
      \EX_Branch_CMP_Op1_reg[26]_0\ => \EX_Op2_reg[26]_0\,
      \EX_Branch_CMP_Op1_reg[27]\ => \EX_Op2_reg[27]\,
      \EX_Branch_CMP_Op1_reg[27]_0\ => \EX_Op2_reg[27]_0\,
      \EX_Branch_CMP_Op1_reg[28]\ => \EX_Op2_reg[28]\,
      \EX_Branch_CMP_Op1_reg[28]_0\ => \EX_Op2_reg[28]_0\,
      \EX_Branch_CMP_Op1_reg[29]\ => \EX_Op2_reg[29]\,
      \EX_Branch_CMP_Op1_reg[29]_0\ => \EX_Op2_reg[29]_0\,
      \EX_Branch_CMP_Op1_reg[2]\ => \EX_Op2_reg[2]\,
      \EX_Branch_CMP_Op1_reg[2]_0\ => \EX_Op2_reg[2]_0\,
      \EX_Branch_CMP_Op1_reg[30]\ => \EX_Op2_reg[30]\,
      \EX_Branch_CMP_Op1_reg[30]_0\ => \EX_Op2_reg[30]_0\,
      \EX_Branch_CMP_Op1_reg[31]\ => \EX_Op2_reg[31]\,
      \EX_Branch_CMP_Op1_reg[31]_0\ => \EX_Op2_reg[31]_0\,
      \EX_Branch_CMP_Op1_reg[3]\ => \EX_Op2_reg[3]\,
      \EX_Branch_CMP_Op1_reg[3]_0\ => \EX_Op2_reg[3]_0\,
      \EX_Branch_CMP_Op1_reg[4]\ => \EX_Op2_reg[4]\,
      \EX_Branch_CMP_Op1_reg[4]_0\ => \EX_Op2_reg[4]_0\,
      \EX_Branch_CMP_Op1_reg[5]\ => \EX_Op2_reg[5]\,
      \EX_Branch_CMP_Op1_reg[5]_0\ => \EX_Op2_reg[5]_0\,
      \EX_Branch_CMP_Op1_reg[6]\ => \EX_Op2_reg[6]\,
      \EX_Branch_CMP_Op1_reg[6]_0\ => \EX_Op2_reg[6]_0\,
      \EX_Branch_CMP_Op1_reg[7]\ => \EX_Op2_reg[7]\,
      \EX_Branch_CMP_Op1_reg[7]_0\ => \EX_Op2_reg[7]_0\,
      \EX_Branch_CMP_Op1_reg[8]\ => \EX_Op2_reg[8]\,
      \EX_Branch_CMP_Op1_reg[8]_0\ => \EX_Op2_reg[8]_0\,
      \EX_Branch_CMP_Op1_reg[9]\ => \EX_Op2_reg[9]\,
      \EX_Branch_CMP_Op1_reg[9]_0\ => \EX_Op2_reg[9]_0\,
      GPR_Op1(0 to 31) => GPR_Op1(0 to 31),
      MEM_Fwd(0 to 31) => MEM_Fwd(0 to 31),
      \Using_FPGA.Native_0\ => \^of_predecode\(1),
      \Using_FPGA.Native_i_5__0_0\(1 downto 0) => \Using_FPGA.Native_i_5__0\(4 downto 3),
      \Using_FPGA.Native_i_5__0_1\ => \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_1\,
      \Using_FPGA.Native_i_5__0_2\ => \^of_predecode\(2),
      \Using_FPGA.Native_i_5__0_3\ => \EX_Op3[0]_i_2\,
      \Using_FPGA.Native_i_5__0_4\(1 downto 0) => \Using_FPGA.Native_i_5__0_0\(4 downto 3),
      \Using_FPGA.Native_i_5__0_5\ => \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_2\,
      \Using_FPGA.Native_i_5__0_6\(1 downto 0) => \Using_FPGA.Native_i_5__0_1\(1 downto 0),
      \Using_FPGA.Native_i_5__0_7\ => \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_3\,
      ex_sel_alu_i_reg(31 downto 0) => ex_sel_alu_i_reg_1(31 downto 0),
      of_instr_ii_9 => of_instr_ii_9,
      p_213_in => p_213_in,
      p_216_in => p_216_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[33].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_172
     port map (
      I037_out => I037_out,
      I135_out => I135_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_9 => of_instr_ii_9
    );
\Instruction_Prefetch_Mux[34].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_173
     port map (
      Clk => Clk,
      of_instr_ii_8 => of_instr_ii_8,
      of_predecode(0) => \^of_predecode\(2),
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[34].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_174
     port map (
      I033_out => I033_out,
      I131_out => I131_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_8 => of_instr_ii_8
    );
\Instruction_Prefetch_Mux[35].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_175
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^of_predecode\(3),
      of_instr_ii_7 => of_instr_ii_7,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[35].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_176
     port map (
      I029_out => I029_out,
      I127_out => I127_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_7 => of_instr_ii_7
    );
\Instruction_Prefetch_Mux[36].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_177
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^of_predecode\(4),
      of_instr_ii_6 => of_instr_ii_6,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[36].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_178
     port map (
      I025_out => I025_out,
      I123_out => I123_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_6 => of_instr_ii_6
    );
\Instruction_Prefetch_Mux[37].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_179
     port map (
      Clk => Clk,
      I0 => I0,
      I4 => I4,
      \Using_FPGA.Native_0\ => \^of_predecode\(5),
      \Using_FPGA.Native_i_7\(2 downto 0) => \Using_FPGA.Native_i_5__0\(2 downto 0),
      \Using_FPGA.Native_i_7_0\ => \^of_predecode\(3),
      \Using_FPGA.Native_i_7_1\ => \^of_predecode\(4),
      \Using_FPGA.Native_i_8\(2 downto 0) => \Using_FPGA.Native_i_5__0_0\(2 downto 0),
      \Using_FPGA.Native_i_9\ => \EX_Op3[0]_i_6\,
      \ex_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_3\,
      \mem_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_1\,
      of_instr_ii_5 => of_instr_ii_5,
      sync_reset => sync_reset,
      \wb_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_2\
    );
\Instruction_Prefetch_Mux[37].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_180
     port map (
      I021_out => I021_out,
      I119_out => I119_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_5 => of_instr_ii_5
    );
\Instruction_Prefetch_Mux[38].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_181
     port map (
      Clk => Clk,
      \EX_Op2[0]_i_3_0\(1 downto 0) => \Using_FPGA.Native_i_5__0\(4 downto 3),
      \EX_Op2[0]_i_3_1\ => \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_1\,
      \EX_Op2[0]_i_3_2\ => \^of_predecode\(7),
      \EX_Op2[0]_i_3_3\(1 downto 0) => \Using_FPGA.Native_i_5__0_1\(1 downto 0),
      \EX_Op2[0]_i_3_4\ => \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_3\,
      \EX_Op2[0]_i_3_5\ => \EX_Op3[0]_i_2\,
      \EX_Op2[0]_i_3_6\(1 downto 0) => \Using_FPGA.Native_i_5__0_0\(4 downto 3),
      \EX_Op2[0]_i_3_7\ => \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_2\,
      \EX_Op2_reg[0]\ => \EX_Op2_reg[0]_1\,
      \EX_Op2_reg[0]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_17\,
      \EX_Op2_reg[0]_1\ => \EX_Op2_reg[0]_2\,
      \EX_Op2_reg[10]\ => \EX_Op2_reg[10]\,
      \EX_Op2_reg[10]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_7\,
      \EX_Op2_reg[10]_1\ => \EX_Op2_reg[10]_0\,
      \EX_Op2_reg[11]\ => \EX_Op2_reg[11]\,
      \EX_Op2_reg[11]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_6\,
      \EX_Op2_reg[11]_1\ => \EX_Op2_reg[11]_0\,
      \EX_Op2_reg[12]\ => \EX_Op2_reg[12]\,
      \EX_Op2_reg[12]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_5\,
      \EX_Op2_reg[12]_1\ => \EX_Op2_reg[12]_0\,
      \EX_Op2_reg[13]\ => \EX_Op2_reg[13]\,
      \EX_Op2_reg[13]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_4\,
      \EX_Op2_reg[13]_1\ => \EX_Op2_reg[13]_0\,
      \EX_Op2_reg[14]\ => \EX_Op2_reg[14]\,
      \EX_Op2_reg[14]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_3\,
      \EX_Op2_reg[14]_1\ => \EX_Op2_reg[14]_0\,
      \EX_Op2_reg[15]\ => \EX_Op2_reg[15]\,
      \EX_Op2_reg[15]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_2\,
      \EX_Op2_reg[15]_1\ => \EX_Op2_reg[15]_0\,
      \EX_Op2_reg[16]\(7 downto 0) => \EX_Op2_reg[16]\(7 downto 0),
      \EX_Op2_reg[16]_0\ => \EX_Op2_reg[16]_0\,
      \EX_Op2_reg[16]_1\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[17]\ => \EX_Op2_reg[17]\,
      \EX_Op2_reg[17]_0\ => \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[18]\ => \EX_Op2_reg[18]\,
      \EX_Op2_reg[18]_0\ => \Instruction_Prefetch_Mux[18].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[19]\ => \EX_Op2_reg[19]\,
      \EX_Op2_reg[19]_0\ => \Instruction_Prefetch_Mux[19].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[1]\ => \EX_Op2_reg[1]\,
      \EX_Op2_reg[1]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_16\,
      \EX_Op2_reg[1]_1\ => \EX_Op2_reg[1]_0\,
      \EX_Op2_reg[20]\ => \EX_Op2_reg[20]\,
      \EX_Op2_reg[20]_0\ => \Instruction_Prefetch_Mux[20].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[21]\ => \EX_Op2_reg[21]\,
      \EX_Op2_reg[21]_0\ => \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[22]\ => \EX_Op2_reg[22]\,
      \EX_Op2_reg[22]_0\ => \Instruction_Prefetch_Mux[22].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[23]\ => \EX_Op2_reg[23]\,
      \EX_Op2_reg[23]_0\ => \Instruction_Prefetch_Mux[23].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[24]\ => \EX_Op2_reg[24]\,
      \EX_Op2_reg[24]_0\ => \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[24]_1\ => \EX_Op2_reg[24]_0\,
      \EX_Op2_reg[25]\ => \EX_Op2_reg[25]\,
      \EX_Op2_reg[25]_0\ => \Instruction_Prefetch_Mux[25].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[25]_1\ => \EX_Op2_reg[25]_0\,
      \EX_Op2_reg[26]\ => \EX_Op2_reg[26]\,
      \EX_Op2_reg[26]_0\ => \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[26]_1\ => \EX_Op2_reg[26]_0\,
      \EX_Op2_reg[27]\ => \EX_Op2_reg[27]\,
      \EX_Op2_reg[27]_0\ => \Instruction_Prefetch_Mux[27].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[27]_1\ => \EX_Op2_reg[27]_0\,
      \EX_Op2_reg[28]\ => \EX_Op2_reg[28]\,
      \EX_Op2_reg[28]_0\ => \Instruction_Prefetch_Mux[28].Gen_Instr_DFF_n_2\,
      \EX_Op2_reg[28]_1\ => \EX_Op2_reg[28]_0\,
      \EX_Op2_reg[29]\ => \EX_Op2_reg[29]\,
      \EX_Op2_reg[29]_0\ => \Instruction_Prefetch_Mux[29].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[29]_1\ => \EX_Op2_reg[29]_0\,
      \EX_Op2_reg[2]\ => \EX_Op2_reg[2]\,
      \EX_Op2_reg[2]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_15\,
      \EX_Op2_reg[2]_1\ => \EX_Op2_reg[2]_0\,
      \EX_Op2_reg[30]\ => \EX_Op2_reg[30]\,
      \EX_Op2_reg[30]_0\ => \Instruction_Prefetch_Mux[30].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[30]_1\ => \EX_Op2_reg[30]_0\,
      \EX_Op2_reg[31]\ => \EX_Op2_reg[31]\,
      \EX_Op2_reg[31]_0\ => \Instruction_Prefetch_Mux[31].Gen_Instr_DFF_n_1\,
      \EX_Op2_reg[31]_1\ => \EX_Op2_reg[31]_0\,
      \EX_Op2_reg[3]\ => \EX_Op2_reg[3]\,
      \EX_Op2_reg[3]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_14\,
      \EX_Op2_reg[3]_1\ => \EX_Op2_reg[3]_0\,
      \EX_Op2_reg[4]\ => \EX_Op2_reg[4]\,
      \EX_Op2_reg[4]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_13\,
      \EX_Op2_reg[4]_1\ => \EX_Op2_reg[4]_0\,
      \EX_Op2_reg[5]\ => \EX_Op2_reg[5]\,
      \EX_Op2_reg[5]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_12\,
      \EX_Op2_reg[5]_1\ => \EX_Op2_reg[5]_0\,
      \EX_Op2_reg[6]\ => \EX_Op2_reg[6]\,
      \EX_Op2_reg[6]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_11\,
      \EX_Op2_reg[6]_1\ => \EX_Op2_reg[6]_0\,
      \EX_Op2_reg[7]\ => \EX_Op2_reg[7]\,
      \EX_Op2_reg[7]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_10\,
      \EX_Op2_reg[7]_1\ => \EX_Op2_reg[7]_0\,
      \EX_Op2_reg[8]\ => \EX_Op2_reg[8]\,
      \EX_Op2_reg[8]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_9\,
      \EX_Op2_reg[8]_1\ => \EX_Op2_reg[8]_0\,
      \EX_Op2_reg[9]\ => \EX_Op2_reg[9]\,
      \EX_Op2_reg[9]_0\ => \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_8\,
      \EX_Op2_reg[9]_1\ => \EX_Op2_reg[9]_0\,
      MEM_Fwd(0 to 31) => MEM_Fwd(0 to 31),
      \Using_FPGA.Native_0\ => \^of_predecode\(6),
      ex_sel_alu_i_reg(31 downto 0) => ex_sel_alu_i_reg(31 downto 0),
      of_instr_ii_4 => of_instr_ii_4,
      of_use_op2_s => \^of_use_op2_s\,
      p_213_in => p_213_in,
      p_216_in => p_216_in,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[38].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_182
     port map (
      I017_out => I017_out,
      I115_out => I115_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_4 => of_instr_ii_4
    );
\Instruction_Prefetch_Mux[39].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_183
     port map (
      Clk => Clk,
      of_instr_ii_3 => of_instr_ii_3,
      of_predecode(0) => \^of_predecode\(7),
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[39].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_184
     port map (
      I013_out => I013_out,
      I111_out => I111_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_3 => of_instr_ii_3
    );
\Instruction_Prefetch_Mux[3].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_185
     port map (
      Clk => Clk,
      \EX_ALU_Op1142_out__0\ => \EX_ALU_Op1142_out__0\,
      \EX_Sext_Op_reg[0]\ => \^of_instr\(3),
      \EX_Sext_Op_reg[0]_0\ => \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_2\,
      \EX_Sext_Op_reg[0]_1\ => \^using_fpga.native_15\,
      \Using_FPGA.Native_0\ => \^of_instr\(2),
      \Using_FPGA.Native_1\ => \^using_fpga.native_5\,
      \Using_FPGA.Native_2\ => \^ex_op1_cmp_eq1\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_8\,
      \Using_FPGA.Native_4\(0) => \Using_FPGA.Native_14\(1),
      \Using_FPGA.Native_5\ => \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_13\,
      \Using_FPGA.Native_6\ => \Using_FPGA.Native_22\,
      ex_branch_with_delayslot_i => ex_branch_with_delayslot_i,
      ex_branch_with_delayslot_i_reg => \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_1\,
      ex_branch_with_delayslot_i_reg_0 => \Using_FPGA.Native_60\,
      ex_branch_with_delayslot_i_reg_1 => ex_branch_with_delayslot_i_reg_0,
      ex_branch_with_delayslot_reg => \^using_fpga.native_4\(20),
      ex_branch_with_delayslot_reg_0 => \^d\(1),
      ex_enable_sext_shift_i0 => ex_enable_sext_shift_i0,
      ex_op1_cmp_eq_n5_out => ex_op1_cmp_eq_n5_out,
      ex_op1_cmp_eq_n_reg => \^using_fpga.native_2\,
      ex_op1_cmp_eq_n_reg_0 => \^using_fpga.native_3\,
      ex_op1_cmp_eq_n_reg_1 => \^using_fpga.native_1\,
      ex_sel_alu_i0 => ex_sel_alu_i0,
      ex_sel_alu_i_reg => \^using_fpga.native_4\(10),
      force12_out => force12_out,
      force2_reg => \^of_instr\(5),
      force2_reg_0 => \^of_instr\(0),
      force2_reg_1 => \^of_instr\(4),
      force2_reg_2 => \^of_instr\(1),
      force_Val10_out => force_Val10_out,
      of_instr_ii_39 => of_instr_ii_39,
      sync_reset => sync_reset,
      use_Reg_Neg_DI1_out => use_Reg_Neg_DI1_out,
      use_Reg_Neg_S3_out => use_Reg_Neg_S3_out
    );
\Instruction_Prefetch_Mux[3].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_186
     port map (
      I0157_out => I0157_out,
      I1155_out => I1155_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_39 => of_instr_ii_39
    );
\Instruction_Prefetch_Mux[40].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_187
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^of_predecode\(8),
      of_instr_ii_2 => of_instr_ii_2,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[40].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_188
     port map (
      I09_out => I09_out,
      I17_out => I17_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_2 => of_instr_ii_2
    );
\Instruction_Prefetch_Mux[41].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_189
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^of_predecode\(9),
      of_instr_ii_1 => of_instr_ii_1,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[41].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_190
     port map (
      I05_out => I05_out,
      I13_out => I13_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_1 => of_instr_ii_1
    );
\Instruction_Prefetch_Mux[42].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_191
     port map (
      Clk => Clk,
      \EX_Op2[0]_i_6\ => \EX_Op3[0]_i_6\,
      \EX_Op2[0]_i_7\(2 downto 0) => \Using_FPGA.Native_i_5__0_0\(2 downto 0),
      \EX_Op2[0]_i_8\(2 downto 0) => \Using_FPGA.Native_i_5__0\(2 downto 0),
      \EX_Op2[0]_i_8_0\ => \^of_predecode\(8),
      \EX_Op2[0]_i_8_1\ => \^of_predecode\(9),
      I0 => I0,
      I4 => I4,
      \Using_FPGA.Native_0\ => \^of_predecode\(10),
      \ex_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_3\,
      \mem_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_1\,
      of_instr_ii_0 => of_instr_ii_0,
      sync_reset => sync_reset,
      \wb_gpr_write_addr_reg[4]\ => \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_2\
    );
\Instruction_Prefetch_Mux[42].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_192
     port map (
      I0_1 => I0_1,
      I1 => I1,
      IReady => IReady,
      IReady_0 => \^iready_0\,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      \Using_FPGA.Native_1\ => ex_branch_with_delayslot_i_reg_0,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_61\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_62\,
      if_missed_fetch => if_missed_fetch,
      of_instr_ii_0 => of_instr_ii_0
    );
\Instruction_Prefetch_Mux[4].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_193
     port map (
      Clk => Clk,
      D224_out => D224_out,
      \EX_Op1_reg[0]\(31 downto 0) => \EX_Op1_reg[0]\(31 downto 0),
      EX_SWAP_Instr_reg => \^using_fpga.native_4\(8),
      EX_SWAP_Instr_reg_0 => \^using_fpga.native_4\(6),
      EX_SWAP_Instr_reg_1 => \^using_fpga.native_4\(5),
      EX_SWAP_Instr_reg_2 => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_5\,
      \EX_Sext_Op_reg[1]\ => \^using_fpga.native_4\(0),
      I1_0 => I1_0,
      \OF_Op1_Sel_SPR_PC0__0\ => \OF_Op1_Sel_SPR_PC0__0\,
      \Using_FPGA.Native_0\ => \^of_instr\(1),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2\,
      \Using_FPGA.Native_10\ => \Using_FPGA.Native_32\,
      \Using_FPGA.Native_11\ => \Using_FPGA.Native_33\,
      \Using_FPGA.Native_12\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_13\ => \Using_FPGA.Native_35\,
      \Using_FPGA.Native_14\ => \Using_FPGA.Native_36\,
      \Using_FPGA.Native_15\ => \Using_FPGA.Native_37\,
      \Using_FPGA.Native_16\ => \Using_FPGA.Native_38\,
      \Using_FPGA.Native_17\ => \Using_FPGA.Native_39\,
      \Using_FPGA.Native_18\ => \Using_FPGA.Native_40\,
      \Using_FPGA.Native_19\ => \Using_FPGA.Native_41\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_12\,
      \Using_FPGA.Native_20\ => \Using_FPGA.Native_42\,
      \Using_FPGA.Native_21\ => \Using_FPGA.Native_43\,
      \Using_FPGA.Native_22\ => \Using_FPGA.Native_44\,
      \Using_FPGA.Native_23\ => \Using_FPGA.Native_45\,
      \Using_FPGA.Native_24\ => \Using_FPGA.Native_46\,
      \Using_FPGA.Native_25\ => \Using_FPGA.Native_47\,
      \Using_FPGA.Native_26\ => \Using_FPGA.Native_48\,
      \Using_FPGA.Native_27\ => \Using_FPGA.Native_49\,
      \Using_FPGA.Native_28\ => \Using_FPGA.Native_50\,
      \Using_FPGA.Native_29\ => \Using_FPGA.Native_51\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_13\,
      \Using_FPGA.Native_30\ => \Using_FPGA.Native_52\,
      \Using_FPGA.Native_31\ => \Using_FPGA.Native_53\,
      \Using_FPGA.Native_32\ => \Using_FPGA.Native_54\,
      \Using_FPGA.Native_33\ => \Using_FPGA.Native_55\,
      \Using_FPGA.Native_34\ => \Using_FPGA.Native_56\,
      \Using_FPGA.Native_35\ => \Using_FPGA.Native_57\,
      \Using_FPGA.Native_36\ => \Using_FPGA.Native_58\,
      \Using_FPGA.Native_37\ => \^of_instr\(0),
      \Using_FPGA.Native_38\ => \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_3\,
      \Using_FPGA.Native_39\ => \^using_fpga.native_4\(10),
      \Using_FPGA.Native_4\(0) => \Using_FPGA.Native_14\(0),
      \Using_FPGA.Native_40\ => \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_13\,
      \Using_FPGA.Native_5\ => \^using_fpga.native_15\,
      \Using_FPGA.Native_6\ => \Using_FPGA.Native_28\,
      \Using_FPGA.Native_7\ => \Using_FPGA.Native_29\,
      \Using_FPGA.Native_8\ => \Using_FPGA.Native_30\,
      \Using_FPGA.Native_9\ => \Using_FPGA.Native_31\,
      ex_MSR(2 downto 0) => ex_MSR(2 downto 0),
      ex_is_multi_instr2_reg => \^using_fpga.native_4\(14),
      ex_is_multi_or_load_instr0 => ex_is_multi_or_load_instr0,
      ex_is_multi_or_load_instr_reg => \^of_instr\(4),
      ex_is_multi_or_load_instr_reg_0 => \^of_instr\(2),
      ex_is_multi_or_load_instr_reg_1 => \^of_instr\(5),
      ex_load_shift_carry0 => ex_load_shift_carry0,
      ex_load_shift_carry_reg => \^of_instr\(3),
      ex_mfsmsr_i_reg => \^using_fpga.native_4\(2),
      ex_mfsmsr_i_reg_0 => \^using_fpga.native_4\(1),
      ex_mfsmsr_i_reg_1 => \^using_fpga.native_4\(3),
      of_Sel_SPR_MSR1 => of_Sel_SPR_MSR1,
      of_Sel_SPR_MSR88_out => of_Sel_SPR_MSR88_out,
      of_instr_ii_38 => of_instr_ii_38,
      of_op1_sel_spr => of_op1_sel_spr,
      p_0_in30_in => p_0_in30_in,
      p_9_in => \^p_9_in\,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[4].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_194
     port map (
      I0153_out => I0153_out,
      I1151_out => I1151_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_38 => of_instr_ii_38
    );
\Instruction_Prefetch_Mux[5].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_195
     port map (
      Clk => Clk,
      E(0) => E(0),
      EX_Is_Div_Instr => EX_Is_Div_Instr,
      \Using_FPGA.Native_0\ => \^of_instr\(0),
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_16\,
      \Using_FPGA.Native_2\ => \^of_instr\(1),
      ex_is_div_instr_I_reg => ex_is_div_instr_I_reg,
      ex_is_div_instr_I_reg_0 => \Using_FPGA.Native_60\,
      ex_is_div_instr_I_reg_1 => \^of_instr\(2),
      ex_is_div_instr_I_reg_2 => \^of_instr\(5),
      ex_is_div_instr_I_reg_3 => \^of_instr\(4),
      of_instr_ii_37 => of_instr_ii_37,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[5].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_196
     port map (
      I0149_out => I0149_out,
      I1147_out => I1147_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_37 => of_instr_ii_37
    );
\Instruction_Prefetch_Mux[6].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_197
     port map (
      Clk => Clk,
      \EX_Op3[0]_i_3\(1 downto 0) => \Using_FPGA.Native_i_5__0\(4 downto 3),
      \EX_Op3[0]_i_3_0\ => \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_1\,
      \EX_Op3[0]_i_3_1\ => \^d\(0),
      \EX_Op3[0]_i_3_2\ => \Instruction_Prefetch_Mux[32].Gen_Instr_DFF_n_33\,
      \EX_Op3[0]_i_5\(0) => \Using_FPGA.Native_i_5__0_0\(4),
      \EX_Op3[0]_i_6\(0) => \Using_FPGA.Native_i_5__0_1\(1),
      \Using_FPGA.Native_0\ => \^d\(1),
      \Using_FPGA.Native_1\ => \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_2\,
      \Using_FPGA.Native_2\ => \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_3\,
      of_instr_ii_36 => of_instr_ii_36,
      \of_read_mem_write_op3_conflict__1\ => \of_read_mem_write_op3_conflict__1\,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[6].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_198
     port map (
      I0145_out => I0145_out,
      I1143_out => I1143_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_36 => of_instr_ii_36
    );
\Instruction_Prefetch_Mux[7].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_199
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^d\(0),
      \Using_FPGA.Native_1\ => ex_mbar_is_sleep_cmb,
      ex_mbar_is_sleep => ex_mbar_is_sleep,
      ex_mbar_is_sleep_reg => \^d\(1),
      ex_mbar_is_sleep_reg_0 => \Using_FPGA.Native_60\,
      of_instr_ii_35 => of_instr_ii_35,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[7].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_200
     port map (
      I0141_out => I0141_out,
      I1139_out => I1139_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_35 => of_instr_ii_35
    );
\Instruction_Prefetch_Mux[8].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_201
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_1\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_7\,
      \ex_gpr_write111_out__0\ => \ex_gpr_write111_out__0\,
      ex_gpr_write_reg => \Using_FPGA.Native_60\,
      ex_gpr_write_reg_0 => \^d\(1),
      ex_gpr_write_reg_1 => \^d\(0),
      ex_op1_cmp_eq1 => \^ex_op1_cmp_eq1\,
      ex_op1_cmp_eq_reg => \^using_fpga.native_3\,
      ex_op1_cmp_eq_reg_0 => \^using_fpga.native_2\,
      of_instr_ii_34 => of_instr_ii_34,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[8].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_202
     port map (
      I0137_out => I0137_out,
      I1135_out => I1135_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_34 => of_instr_ii_34
    );
\Instruction_Prefetch_Mux[9].Gen_Instr_DFF\: entity work.design_1_microblaze_0_0_MB_FDR_203
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_2\,
      of_instr_ii_33 => of_instr_ii_33,
      sync_reset => sync_reset
    );
\Instruction_Prefetch_Mux[9].Instr_Mux_MUXF7\: entity work.design_1_microblaze_0_0_MB_MUXF7_204
     port map (
      I0133_out => I0133_out,
      I1131_out => I1131_out,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_60\,
      of_instr_ii_33 => of_instr_ii_33
    );
Last_Sel_DFF: entity work.design_1_microblaze_0_0_MB_FDS
     port map (
      Clk => Clk,
      I0101_out => I0101_out,
      I0105_out => I0105_out,
      I0109_out => I0109_out,
      I0113_out => I0113_out,
      I0117_out => I0117_out,
      I0121_out => I0121_out,
      I0125_out => I0125_out,
      I0129_out => I0129_out,
      I0133_out => I0133_out,
      I0137_out => I0137_out,
      I013_out => I013_out,
      I0141_out => I0141_out,
      I0145_out => I0145_out,
      I0149_out => I0149_out,
      I0153_out => I0153_out,
      I0157_out => I0157_out,
      I0161_out => I0161_out,
      I0165_out => I0165_out,
      I0169_out => I0169_out,
      I017_out => I017_out,
      I021_out => I021_out,
      I025_out => I025_out,
      I029_out => I029_out,
      I033_out => I033_out,
      I037_out => I037_out,
      I041_out => I041_out,
      I045_out => I045_out,
      I049_out => I049_out,
      I053_out => I053_out,
      I057_out => I057_out,
      I05_out => I05_out,
      I061_out => I061_out,
      I065_out => I065_out,
      I069_out => I069_out,
      I073_out => I073_out,
      I077_out => I077_out,
      I081_out => I081_out,
      I085_out => I085_out,
      I089_out => I089_out,
      I093_out => I093_out,
      I097_out => I097_out,
      I09_out => I09_out,
      I0_1 => I0_1,
      \Using_FPGA.Native_0\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_1\ => \^iready_0\,
      \Using_FPGA.Native_10\ => \^d\(0),
      \Using_FPGA.Native_11\ => \^d\(1),
      \Using_FPGA.Native_12\ => \^of_instr\(0),
      \Using_FPGA.Native_13\ => \^of_instr\(1),
      \Using_FPGA.Native_14\ => \^of_instr\(2),
      \Using_FPGA.Native_15\ => \^of_instr\(3),
      \Using_FPGA.Native_16\ => \^of_instr\(4),
      \Using_FPGA.Native_17\ => \^of_instr\(5),
      \Using_FPGA.Native_2\ => \^using_fpga.native_4\(0),
      \Using_FPGA.Native_3\ => \^using_fpga.native_4\(1),
      \Using_FPGA.Native_4\ => \^using_fpga.native_4\(2),
      \Using_FPGA.Native_5\ => \^using_fpga.native_4\(3),
      \Using_FPGA.Native_6\(16 downto 0) => \^using_fpga.native_4\(20 downto 4),
      \Using_FPGA.Native_7\ => \^using_fpga.native_3\,
      \Using_FPGA.Native_8\ => \^using_fpga.native_2\,
      \Using_FPGA.Native_9\ => \^using_fpga.native_1\,
      \in\(31 downto 10) => \in\(32 downto 11),
      \in\(9 downto 0) => \in\(9 downto 0),
      of_predecode(0 to 10) => \^of_predecode\(0 to 10),
      sel_input_i_0 => sel_input_i_0,
      sync_reset => sync_reset
    );
Mux_Select_Empty_LUT6: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized4\
     port map (
      I4_0 => I4_0,
      I5 => I5,
      \Using_FPGA.Native_0\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_1\ => \^using_fpga.native_0\,
      \Using_FPGA.Native_2\ => \^iready_0\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_60\,
      sel_input_i_0 => sel_input_i_0
    );
Mux_Select_OF_Valid_LUT6: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized6\
     port map (
      I4_0 => I4_0,
      I5 => I5,
      \Using_FPGA.Native_0\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_1\ => \^using_fpga.native_0\,
      \Using_FPGA.Native_2\ => \^iready_0\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_60\,
      of_Valid_II => of_Valid_II
    );
OF_Valid_DFF: entity work.design_1_microblaze_0_0_MB_FDR_205
     port map (
      Clk => Clk,
      Dbg_Clean_Stop0 => Dbg_Clean_Stop0,
      Dbg_Clean_Stop_reg => \^using_fpga.native_5\,
      Q(1 downto 0) => Q(1 downto 0),
      \Using_FPGA.Native_0\ => of_valid,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_11\(0),
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_23\,
      ex_branch_with_delayslot => ex_branch_with_delayslot,
      ex_branch_with_delayslot_reg => ex_branch_with_delayslot_reg,
      ex_jump => ex_jump,
      ex_jump_nodelay => ex_jump_nodelay,
      ex_jump_q => ex_jump_q,
      of_Valid_II => of_Valid_II,
      p_9_in => \^p_9_in\,
      sync_reset => sync_reset,
      wb_exception => wb_exception
    );
ex_branch_with_delayslot_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_1\,
      Q => ex_branch_with_delayslot_i,
      R => '0'
    );
\ibuffer_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(32),
      Q => p_1_in209_in
    );
\ibuffer_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(22),
      Q => p_1_in159_in
    );
\ibuffer_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(9),
      Q => p_1_in154_in
    );
\ibuffer_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(8),
      Q => p_1_in149_in
    );
\ibuffer_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(7),
      Q => p_1_in144_in
    );
\ibuffer_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(6),
      Q => p_1_in139_in
    );
\ibuffer_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(5),
      Q => p_1_in134_in
    );
\ibuffer_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(4),
      Q => p_1_in129_in
    );
\ibuffer_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(3),
      Q => p_1_in124_in
    );
\ibuffer_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(2),
      Q => p_1_in119_in
    );
\ibuffer_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(1),
      Q => p_1_in114_in
    );
\ibuffer_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(31),
      Q => p_1_in204_in
    );
\ibuffer_reg[3][20]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(0),
      Q => p_1_in109_in
    );
\ibuffer_reg[3][21]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(21),
      Q => p_1_in104_in
    );
\ibuffer_reg[3][22]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(20),
      Q => p_1_in99_in
    );
\ibuffer_reg[3][23]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(19),
      Q => p_1_in94_in
    );
\ibuffer_reg[3][24]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(18),
      Q => p_1_in89_in
    );
\ibuffer_reg[3][25]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(17),
      Q => p_1_in84_in
    );
\ibuffer_reg[3][26]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(16),
      Q => p_1_in79_in
    );
\ibuffer_reg[3][27]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(15),
      Q => p_1_in74_in
    );
\ibuffer_reg[3][28]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(14),
      Q => p_1_in69_in
    );
\ibuffer_reg[3][29]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(13),
      Q => p_1_in64_in
    );
\ibuffer_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(30),
      Q => p_1_in199_in
    );
\ibuffer_reg[3][30]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(12),
      Q => p_1_in59_in
    );
\ibuffer_reg[3][31]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(11),
      Q => p_1_in54_in
    );
\ibuffer_reg[3][32]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(10),
      Q => \Using_FPGA.Native_59\(0)
    );
\ibuffer_reg[3][33]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(9),
      Q => p_1_in44_in
    );
\ibuffer_reg[3][34]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(8),
      Q => p_1_in39_in
    );
\ibuffer_reg[3][35]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(7),
      Q => p_1_in34_in
    );
\ibuffer_reg[3][36]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(6),
      Q => p_1_in29_in
    );
\ibuffer_reg[3][37]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(5),
      Q => p_1_in24_in
    );
\ibuffer_reg[3][38]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(4),
      Q => p_1_in19_in
    );
\ibuffer_reg[3][39]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(3),
      Q => p_1_in14_in
    );
\ibuffer_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(29),
      Q => p_1_in194_in
    );
\ibuffer_reg[3][40]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(2),
      Q => p_1_in9_in
    );
\ibuffer_reg[3][41]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(1),
      Q => p_1_in4_in
    );
\ibuffer_reg[3][42]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(0),
      Q => \ibuffer_reg[3][42]_srl4_n_0\
    );
\ibuffer_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(28),
      Q => p_1_in189_in
    );
\ibuffer_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(27),
      Q => p_1_in184_in
    );
\ibuffer_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(26),
      Q => p_1_in179_in
    );
\ibuffer_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(25),
      Q => p_1_in174_in
    );
\ibuffer_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(24),
      Q => p_1_in169_in
    );
\ibuffer_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => \^if_pre_buffer_addr\(0),
      A1 => \^using_fpga.native\(1),
      A2 => '0',
      A3 => '0',
      CE => \^iready_0\,
      CLK => Clk,
      D => \in\(23),
      Q => p_1_in164_in
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Register_File_gti is
  port (
    GPR_Op1 : out STD_LOGIC_VECTOR ( 0 to 31 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 0 to 31 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 0 to 31 );
    Clk : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[18]\ : in STD_LOGIC;
    DID : in STD_LOGIC_VECTOR ( 1 downto 0 );
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 4 downto 0 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[18]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \EX_Branch_CMP_Op1_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[4]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[6]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[10]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[12]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[14]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[16]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[18]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[20]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[22]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[24]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[26]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[28]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Branch_CMP_Op1_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Register_File_gti : entity is "Register_File_gti";
end design_1_microblaze_0_0_Register_File_gti;

architecture STRUCTURE of design_1_microblaze_0_0_Register_File_gti is
begin
\Using_LUT6.All_RAM32M[0].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M
     port map (
      Clk => Clk,
      DID(1 downto 0) => DID(1 downto 0),
      \EX_Branch_CMP_Op1_reg[0]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[0]_0\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(0),
      GPR_Op1(0) => GPR_Op1(1),
      GPR_Op2(1) => GPR_Op2(0),
      GPR_Op2(0) => GPR_Op2(1),
      GPR_Op3(1) => GPR_Op3(0),
      GPR_Op3(0) => GPR_Op3(1),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[10].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_409
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[20]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[20]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[20]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[20]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(20),
      GPR_Op1(0) => GPR_Op1(21),
      GPR_Op2(1) => GPR_Op2(20),
      GPR_Op2(0) => GPR_Op2(21),
      GPR_Op3(1) => GPR_Op3(20),
      GPR_Op3(0) => GPR_Op3(21),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[11].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_410
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[22]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[22]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[22]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[22]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(22),
      GPR_Op1(0) => GPR_Op1(23),
      GPR_Op2(1) => GPR_Op2(22),
      GPR_Op2(0) => GPR_Op2(23),
      GPR_Op3(1) => GPR_Op3(22),
      GPR_Op3(0) => GPR_Op3(23),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[12].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_411
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[24]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[24]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[24]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[24]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(24),
      GPR_Op1(0) => GPR_Op1(25),
      GPR_Op2(1) => GPR_Op2(24),
      GPR_Op2(0) => GPR_Op2(25),
      GPR_Op3(1) => GPR_Op3(24),
      GPR_Op3(0) => GPR_Op3(25),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[13].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_412
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[26]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[26]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[26]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[26]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(26),
      GPR_Op1(0) => GPR_Op1(27),
      GPR_Op2(1) => GPR_Op2(26),
      GPR_Op2(0) => GPR_Op2(27),
      GPR_Op3(1) => GPR_Op3(26),
      GPR_Op3(0) => GPR_Op3(27),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[14].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_413
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[28]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[28]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[28]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[28]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(28),
      GPR_Op1(0) => GPR_Op1(29),
      GPR_Op2(1) => GPR_Op2(28),
      GPR_Op2(0) => GPR_Op2(29),
      GPR_Op3(1) => GPR_Op3(28),
      GPR_Op3(0) => GPR_Op3(29),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[15].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_414
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[30]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[30]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[30]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[30]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(30),
      GPR_Op1(0) => GPR_Op1(31),
      GPR_Op2(1) => GPR_Op2(30),
      GPR_Op2(0) => GPR_Op2(31),
      GPR_Op3(1) => GPR_Op3(30),
      GPR_Op3(0) => GPR_Op3(31),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[1].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_415
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[2]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[2]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[2]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[2]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(2),
      GPR_Op1(0) => GPR_Op1(3),
      GPR_Op2(1) => GPR_Op2(2),
      GPR_Op2(0) => GPR_Op2(3),
      GPR_Op3(1) => GPR_Op3(2),
      GPR_Op3(0) => GPR_Op3(3),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[2].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_416
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[4]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[4]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[4]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[4]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(4),
      GPR_Op1(0) => GPR_Op1(5),
      GPR_Op2(1) => GPR_Op2(4),
      GPR_Op2(0) => GPR_Op2(5),
      GPR_Op3(1) => GPR_Op3(4),
      GPR_Op3(0) => GPR_Op3(5),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[3].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_417
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[6]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[6]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[6]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[6]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(6),
      GPR_Op1(0) => GPR_Op1(7),
      GPR_Op2(1) => GPR_Op2(6),
      GPR_Op2(0) => GPR_Op2(7),
      GPR_Op3(1) => GPR_Op3(6),
      GPR_Op3(0) => GPR_Op3(7),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[4].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_418
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[8]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[8]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[8]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[8]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(8),
      GPR_Op1(0) => GPR_Op1(9),
      GPR_Op2(1) => GPR_Op2(8),
      GPR_Op2(0) => GPR_Op2(9),
      GPR_Op3(1) => GPR_Op3(8),
      GPR_Op3(0) => GPR_Op3(9),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[5].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_419
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[10]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[10]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[10]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[10]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(10),
      GPR_Op1(0) => GPR_Op1(11),
      GPR_Op2(1) => GPR_Op2(10),
      GPR_Op2(0) => GPR_Op2(11),
      GPR_Op3(1) => GPR_Op3(10),
      GPR_Op3(0) => GPR_Op3(11),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[6].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_420
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[12]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[12]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[12]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[12]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(12),
      GPR_Op1(0) => GPR_Op1(13),
      GPR_Op2(1) => GPR_Op2(12),
      GPR_Op2(0) => GPR_Op2(13),
      GPR_Op3(1) => GPR_Op3(12),
      GPR_Op3(0) => GPR_Op3(13),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[7].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_421
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[14]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[14]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[14]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[14]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(14),
      GPR_Op1(0) => GPR_Op1(15),
      GPR_Op2(1) => GPR_Op2(14),
      GPR_Op2(0) => GPR_Op2(15),
      GPR_Op3(1) => GPR_Op3(14),
      GPR_Op3(0) => GPR_Op3(15),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[8].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_422
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[16]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[16]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[16]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[16]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(16),
      GPR_Op1(0) => GPR_Op1(17),
      GPR_Op2(1) => GPR_Op2(16),
      GPR_Op2(0) => GPR_Op2(17),
      GPR_Op3(1) => GPR_Op3(16),
      GPR_Op3(0) => GPR_Op3(17),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
\Using_LUT6.All_RAM32M[9].ram32m_i\: entity work.design_1_microblaze_0_0_MB_RAM32M_423
     port map (
      Clk => Clk,
      \EX_Branch_CMP_Op1_reg[18]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[18]_0\(1 downto 0) => \EX_Branch_CMP_Op1_reg[18]_1\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[18]_1\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      GPR_Op1(1) => GPR_Op1(18),
      GPR_Op1(0) => GPR_Op1(19),
      GPR_Op2(1) => GPR_Op2(18),
      GPR_Op2(0) => GPR_Op2(19),
      GPR_Op3(1) => GPR_Op3(18),
      GPR_Op3(0) => GPR_Op3(19),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4 downto 0) => of_imm_data(4 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Zero_Detect_gti is
  port (
    ex_op1_zero : out STD_LOGIC;
    ex_op1_cmp_equal : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC_VECTOR ( 29 downto 0 );
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Zero_Detect_gti : entity is "Zero_Detect_gti";
end design_1_microblaze_0_0_Zero_Detect_gti;

architecture STRUCTURE of design_1_microblaze_0_0_Zero_Detect_gti is
  signal S : STD_LOGIC;
  signal \S0_inferred__0/i__n_0\ : STD_LOGIC;
  signal \S0_inferred__1/i__n_0\ : STD_LOGIC;
  signal \S0_inferred__2/i__n_0\ : STD_LOGIC;
  signal \S0_inferred__3/i__n_0\ : STD_LOGIC;
  signal \^lopt\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal lopt_10 : STD_LOGIC;
  signal lopt_11 : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal lopt_3 : STD_LOGIC;
  signal lopt_4 : STD_LOGIC;
  signal lopt_5 : STD_LOGIC;
  signal lopt_6 : STD_LOGIC;
  signal lopt_7 : STD_LOGIC;
  signal lopt_8 : STD_LOGIC;
  signal lopt_9 : STD_LOGIC;
  signal zero_CI_1 : STD_LOGIC;
  signal zero_CI_2 : STD_LOGIC;
  signal zero_CI_3 : STD_LOGIC;
  signal zero_CI_4 : STD_LOGIC;
  signal zero_CI_5 : STD_LOGIC;
  signal zero_CI_6 : STD_LOGIC;
begin
  lopt <= lopt_5;
  lopt_6 <= lopt_1;
  lopt_7 <= lopt_2;
Part_Of_Zero_Carry_Start: entity work.design_1_microblaze_0_0_MB_MUXCY_402
     port map (
      ex_op1_cmp_equal => ex_op1_cmp_equal,
      lopt => \^lopt\,
      lopt_1 => ex_op1_cmp_equal_n,
      lopt_10 => lopt_11,
      lopt_11 => lopt_6,
      lopt_12 => lopt_7,
      lopt_13 => \Using_FPGA.Native\,
      lopt_14 => \S0_inferred__0/i__n_0\,
      lopt_15 => \S0_inferred__1/i__n_0\,
      lopt_2 => S,
      lopt_3 => \^lopt_1\,
      lopt_4 => \S0_inferred__3/i__n_0\,
      lopt_5 => \^lopt_2\,
      lopt_6 => \S0_inferred__2/i__n_0\,
      lopt_7 => lopt_8,
      lopt_8 => lopt_9,
      lopt_9 => lopt_10,
      zero_CI_6 => zero_CI_6
    );
\S0_inferred__0/i_\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \Using_FPGA.Native_0\(0),
      I1 => \Using_FPGA.Native_0\(5),
      I2 => \Using_FPGA.Native_0\(3),
      I3 => \Using_FPGA.Native_0\(4),
      I4 => \Using_FPGA.Native_0\(1),
      I5 => \Using_FPGA.Native_0\(2),
      O => \S0_inferred__0/i__n_0\
    );
\S0_inferred__1/i_\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \Using_FPGA.Native_0\(6),
      I1 => \Using_FPGA.Native_0\(11),
      I2 => \Using_FPGA.Native_0\(9),
      I3 => \Using_FPGA.Native_0\(10),
      I4 => \Using_FPGA.Native_0\(7),
      I5 => \Using_FPGA.Native_0\(8),
      O => \S0_inferred__1/i__n_0\
    );
\S0_inferred__2/i_\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \Using_FPGA.Native_0\(12),
      I1 => \Using_FPGA.Native_0\(17),
      I2 => \Using_FPGA.Native_0\(15),
      I3 => \Using_FPGA.Native_0\(16),
      I4 => \Using_FPGA.Native_0\(13),
      I5 => \Using_FPGA.Native_0\(14),
      O => \S0_inferred__2/i__n_0\
    );
\S0_inferred__3/i_\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \Using_FPGA.Native_0\(18),
      I1 => \Using_FPGA.Native_0\(23),
      I2 => \Using_FPGA.Native_0\(21),
      I3 => \Using_FPGA.Native_0\(22),
      I4 => \Using_FPGA.Native_0\(19),
      I5 => \Using_FPGA.Native_0\(20),
      O => \S0_inferred__3/i__n_0\
    );
\S0_inferred__4/i_\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \Using_FPGA.Native_0\(24),
      I1 => \Using_FPGA.Native_0\(29),
      I2 => \Using_FPGA.Native_0\(27),
      I3 => \Using_FPGA.Native_0\(28),
      I4 => \Using_FPGA.Native_0\(25),
      I5 => \Using_FPGA.Native_0\(26),
      O => S
    );
\Zero_Detecting[1].I_Part_Of_Zero_Detect\: entity work.design_1_microblaze_0_0_MB_MUXCY_403
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      ex_op1_zero => ex_op1_zero,
      lopt => lopt_4,
      zero_CI_1 => zero_CI_1
    );
\Zero_Detecting[2].I_Part_Of_Zero_Detect\: entity work.design_1_microblaze_0_0_MB_MUXCY_404
     port map (
      \Using_FPGA.Native_0\ => \S0_inferred__0/i__n_0\,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      lopt => lopt_3,
      zero_CI_1 => zero_CI_1,
      zero_CI_2 => zero_CI_2
    );
\Zero_Detecting[3].I_Part_Of_Zero_Detect\: entity work.design_1_microblaze_0_0_MB_MUXCY_405
     port map (
      \Using_FPGA.Native_0\ => \S0_inferred__1/i__n_0\,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      lopt => lopt_3,
      lopt_1 => \S0_inferred__0/i__n_0\,
      lopt_10 => lopt_11,
      lopt_2 => lopt_4,
      lopt_3 => \Using_FPGA.Native\,
      lopt_4 => lopt_5,
      lopt_5 => lopt_6,
      lopt_6 => lopt_7,
      lopt_7 => lopt_8,
      lopt_8 => lopt_9,
      lopt_9 => lopt_10,
      zero_CI_2 => zero_CI_2,
      zero_CI_3 => zero_CI_3
    );
\Zero_Detecting[4].I_Part_Of_Zero_Detect\: entity work.design_1_microblaze_0_0_MB_MUXCY_406
     port map (
      \Using_FPGA.Native_0\ => \S0_inferred__2/i__n_0\,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      lopt => \^lopt_2\,
      zero_CI_3 => zero_CI_3,
      zero_CI_4 => zero_CI_4
    );
\Zero_Detecting[5].I_Part_Of_Zero_Detect\: entity work.design_1_microblaze_0_0_MB_MUXCY_407
     port map (
      \Using_FPGA.Native_0\ => \S0_inferred__3/i__n_0\,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      lopt => \^lopt_1\,
      zero_CI_4 => zero_CI_4,
      zero_CI_5 => zero_CI_5
    );
\Zero_Detecting[6].I_Part_Of_Zero_Detect\: entity work.design_1_microblaze_0_0_MB_MUXCY_408
     port map (
      S => S,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      lopt => \^lopt\,
      zero_CI_5 => zero_CI_5,
      zero_CI_6 => zero_CI_6
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_address_hit is
  port (
    Hit : out STD_LOGIC;
    single_Step_N_reg : out STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg\ : out STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2\ : in STD_LOGIC;
    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2\ : in STD_LOGIC;
    force_stop_i : in STD_LOGIC;
    single_Step_N : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3\ : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0\ : in STD_LOGIC;
    ex_Exception_Taken : in STD_LOGIC;
    mem_Exception_Taken : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4\ : in STD_LOGIC;
    Dbg_TDI : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 0 to 31 );
    Dbg_Clk : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_address_hit : entity is "address_hit";
end design_1_microblaze_0_0_address_hit;

architecture STRUCTURE of design_1_microblaze_0_0_address_hit is
  signal SRL16_MC15_1 : STD_LOGIC;
  signal SRL16_MC15_2 : STD_LOGIC;
  signal SRL16_MC15_3 : STD_LOGIC;
  signal SRL16_MC15_4 : STD_LOGIC;
  signal SRL16_MC15_5 : STD_LOGIC;
  signal SRL16_MC15_6 : STD_LOGIC;
  signal SRL16_MC15_7 : STD_LOGIC;
  signal SRL16_Sel_0 : STD_LOGIC;
  signal SRL16_Sel_1 : STD_LOGIC;
  signal SRL16_Sel_2 : STD_LOGIC;
  signal SRL16_Sel_3 : STD_LOGIC;
  signal SRL16_Sel_4 : STD_LOGIC;
  signal SRL16_Sel_5 : STD_LOGIC;
  signal SRL16_Sel_6 : STD_LOGIC;
  signal SRL16_Sel_7 : STD_LOGIC;
  signal carry_0 : STD_LOGIC;
  signal carry_1 : STD_LOGIC;
  signal carry_2 : STD_LOGIC;
  signal carry_3 : STD_LOGIC;
  signal carry_4 : STD_LOGIC;
  signal carry_5 : STD_LOGIC;
  signal carry_6 : STD_LOGIC;
  signal carry_7 : STD_LOGIC;
  signal lopt : STD_LOGIC;
  signal lopt_1 : STD_LOGIC;
  signal lopt_10 : STD_LOGIC;
  signal lopt_11 : STD_LOGIC;
  signal lopt_12 : STD_LOGIC;
  signal lopt_13 : STD_LOGIC;
  signal lopt_14 : STD_LOGIC;
  signal lopt_15 : STD_LOGIC;
  signal lopt_16 : STD_LOGIC;
  signal lopt_2 : STD_LOGIC;
  signal lopt_3 : STD_LOGIC;
  signal lopt_4 : STD_LOGIC;
  signal lopt_5 : STD_LOGIC;
  signal lopt_6 : STD_LOGIC;
  signal lopt_7 : STD_LOGIC;
  signal lopt_8 : STD_LOGIC;
  signal lopt_9 : STD_LOGIC;
  signal \which_pc__0\ : STD_LOGIC;
begin
\Compare[0].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY
     port map (
      Q(0) => Q(1),
      SRL16_Sel_7 => SRL16_Sel_7,
      carry_7 => carry_7,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_13,
      lopt_11 => lopt_14,
      lopt_12 => lopt_15,
      lopt_13 => lopt_11,
      lopt_14 => lopt_9,
      lopt_15 => lopt_7,
      lopt_16 => lopt_16,
      lopt_17 => SRL16_Sel_0,
      lopt_18 => SRL16_Sel_1,
      lopt_19 => SRL16_Sel_2,
      lopt_2 => SRL16_Sel_6,
      lopt_20 => SRL16_Sel_3,
      lopt_3 => lopt_2,
      lopt_4 => lopt_3,
      lopt_5 => SRL16_Sel_5,
      lopt_6 => lopt_4,
      lopt_7 => lopt_5,
      lopt_8 => SRL16_Sel_4,
      lopt_9 => lopt_12
    );
\Compare[0].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E
     port map (
      Address(3) => Address(28),
      Address(2) => Address(29),
      Address(1) => Address(30),
      Address(0) => Address(31),
      Dbg_Clk => Dbg_Clk,
      Dbg_Reg_En(0 to 7) => Dbg_Reg_En(0 to 7),
      SRL16_MC15_7 => SRL16_MC15_7,
      SRL16_Sel_7 => SRL16_Sel_7,
      \which_pc__0\ => \which_pc__0\
    );
\Compare[1].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_31
     port map (
      SRL16_Sel_6 => SRL16_Sel_6,
      carry_6 => carry_6,
      carry_7 => carry_7,
      lopt => lopt,
      lopt_1 => lopt_1
    );
\Compare[1].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E_32
     port map (
      Address(3) => Address(24),
      Address(2) => Address(25),
      Address(1) => Address(26),
      Address(0) => Address(27),
      Dbg_Clk => Dbg_Clk,
      SRL16_MC15_6 => SRL16_MC15_6,
      SRL16_MC15_7 => SRL16_MC15_7,
      SRL16_Sel_6 => SRL16_Sel_6,
      \which_pc__0\ => \which_pc__0\
    );
\Compare[2].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_33
     port map (
      SRL16_Sel_5 => SRL16_Sel_5,
      carry_5 => carry_5,
      carry_6 => carry_6,
      lopt => lopt_2,
      lopt_1 => lopt_3
    );
\Compare[2].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E_34
     port map (
      Address(3) => Address(20),
      Address(2) => Address(21),
      Address(1) => Address(22),
      Address(0) => Address(23),
      Dbg_Clk => Dbg_Clk,
      SRL16_MC15_5 => SRL16_MC15_5,
      SRL16_MC15_6 => SRL16_MC15_6,
      SRL16_Sel_5 => SRL16_Sel_5,
      \which_pc__0\ => \which_pc__0\
    );
\Compare[3].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_35
     port map (
      SRL16_Sel_4 => SRL16_Sel_4,
      carry_4 => carry_4,
      carry_5 => carry_5,
      lopt => lopt_4,
      lopt_1 => lopt_5
    );
\Compare[3].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E_36
     port map (
      Address(3) => Address(16),
      Address(2) => Address(17),
      Address(1) => Address(18),
      Address(0) => Address(19),
      Dbg_Clk => Dbg_Clk,
      SRL16_MC15_4 => SRL16_MC15_4,
      SRL16_MC15_5 => SRL16_MC15_5,
      SRL16_Sel_4 => SRL16_Sel_4,
      \which_pc__0\ => \which_pc__0\
    );
\Compare[4].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_37
     port map (
      SRL16_Sel_3 => SRL16_Sel_3,
      carry_3 => carry_3,
      carry_4 => carry_4,
      lopt => lopt_6,
      lopt_1 => lopt_7,
      lopt_10 => lopt_13,
      lopt_11 => lopt_14,
      lopt_12 => lopt_15,
      lopt_13 => lopt_16,
      lopt_2 => SRL16_Sel_2,
      lopt_3 => lopt_8,
      lopt_4 => lopt_9,
      lopt_5 => SRL16_Sel_1,
      lopt_6 => lopt_10,
      lopt_7 => lopt_11,
      lopt_8 => SRL16_Sel_0,
      lopt_9 => lopt_12
    );
\Compare[4].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E_38
     port map (
      Address(3) => Address(12),
      Address(2) => Address(13),
      Address(1) => Address(14),
      Address(0) => Address(15),
      Dbg_Clk => Dbg_Clk,
      SRL16_MC15_3 => SRL16_MC15_3,
      SRL16_MC15_4 => SRL16_MC15_4,
      SRL16_Sel_3 => SRL16_Sel_3,
      \which_pc__0\ => \which_pc__0\
    );
\Compare[5].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_39
     port map (
      SRL16_Sel_2 => SRL16_Sel_2,
      carry_2 => carry_2,
      carry_3 => carry_3,
      lopt => lopt_6,
      lopt_1 => lopt_7
    );
\Compare[5].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E_40
     port map (
      Address(3) => Address(8),
      Address(2) => Address(9),
      Address(1) => Address(10),
      Address(0) => Address(11),
      Dbg_Clk => Dbg_Clk,
      SRL16_MC15_2 => SRL16_MC15_2,
      SRL16_MC15_3 => SRL16_MC15_3,
      SRL16_Sel_2 => SRL16_Sel_2,
      \which_pc__0\ => \which_pc__0\
    );
\Compare[6].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_41
     port map (
      SRL16_Sel_1 => SRL16_Sel_1,
      carry_1 => carry_1,
      carry_2 => carry_2,
      lopt => lopt_8,
      lopt_1 => lopt_9
    );
\Compare[6].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E_42
     port map (
      Address(3) => Address(4),
      Address(2) => Address(5),
      Address(1) => Address(6),
      Address(0) => Address(7),
      Dbg_Clk => Dbg_Clk,
      SRL16_MC15_1 => SRL16_MC15_1,
      SRL16_MC15_2 => SRL16_MC15_2,
      SRL16_Sel_1 => SRL16_Sel_1,
      \which_pc__0\ => \which_pc__0\
    );
\Compare[7].MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_43
     port map (
      SRL16_Sel_0 => SRL16_Sel_0,
      carry_0 => carry_0,
      carry_1 => carry_1,
      lopt => lopt_10,
      lopt_1 => lopt_11
    );
\Compare[7].SRLC16E_I\: entity work.design_1_microblaze_0_0_MB_SRLC16E_44
     port map (
      Address(3) => Address(0),
      Address(2) => Address(1),
      Address(1) => Address(2),
      Address(0) => Address(3),
      Dbg_Clk => Dbg_Clk,
      Dbg_TDI => Dbg_TDI,
      SRL16_MC15_1 => SRL16_MC15_1,
      SRL16_Sel_0 => SRL16_Sel_0,
      \which_pc__0\ => \which_pc__0\
    );
\The_First_BreakPoints.MUXCY_Post\: entity work.design_1_microblaze_0_0_MB_MUXCY_45
     port map (
      Hit => Hit,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4\,
      \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg\ => \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg\,
      \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0\ => \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0\,
      Q(0) => Q(0),
      carry_0 => carry_0,
      ex_Exception_Taken => ex_Exception_Taken,
      force_stop_i => force_stop_i,
      mem_Exception_Taken => mem_Exception_Taken,
      single_Step_N => single_Step_N,
      single_Step_N_reg => single_Step_N_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and is
  port (
    of_PipeRun_carry_1 : out STD_LOGIC;
    use_Reg_Neg_S_reg : in STD_LOGIC;
    of_PipeRun_carry_2 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and : entity is "carry_and";
end design_1_microblaze_0_0_carry_and;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_111
     port map (
      lopt => lopt,
      lopt_1 => lopt_1,
      of_PipeRun_carry_1 => of_PipeRun_carry_1,
      of_PipeRun_carry_2 => of_PipeRun_carry_2,
      use_Reg_Neg_S_reg => use_Reg_Neg_S_reg
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_57 is
  port (
    of_PipeRun_for_ce : out STD_LOGIC;
    ex_jump_nodelay_reg : out STD_LOGIC;
    of_read_imm_reg_ii_reg : out STD_LOGIC;
    wb_exception_i_reg : out STD_LOGIC;
    wb_exception_i_reg_0 : out STD_LOGIC;
    of_PipeRun_carry_1 : in STD_LOGIC;
    ex_jump_nodelay : in STD_LOGIC;
    ex_jump : in STD_LOGIC;
    ex_jump_nodelay_reg_0 : in STD_LOGIC;
    IB_Ready : in STD_LOGIC;
    if_missed_fetch : in STD_LOGIC;
    of_read_imm_reg_ii : in STD_LOGIC;
    p_9_in : in STD_LOGIC;
    of_read_imm_reg_ii_reg_0 : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    of_pause : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_57 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_57;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_57 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_110
     port map (
      E(0) => E(0),
      IB_Ready => IB_Ready,
      ex_jump => ex_jump,
      ex_jump_nodelay => ex_jump_nodelay,
      ex_jump_nodelay_reg => ex_jump_nodelay_reg,
      ex_jump_nodelay_reg_0 => ex_jump_nodelay_reg_0,
      if_missed_fetch => if_missed_fetch,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_2 => lopt_2,
      of_PipeRun_carry_1 => of_PipeRun_carry_1,
      of_pause => of_pause,
      of_pause_reg => of_PipeRun_for_ce,
      of_read_imm_reg_ii => of_read_imm_reg_ii,
      of_read_imm_reg_ii_reg => of_read_imm_reg_ii_reg,
      of_read_imm_reg_ii_reg_0 => of_read_imm_reg_ii_reg_0,
      p_9_in => p_9_in,
      sync_reset => sync_reset,
      wb_exception => wb_exception,
      wb_exception_i_reg => wb_exception_i_reg,
      wb_exception_i_reg_0 => wb_exception_i_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_58 is
  port (
    of_PipeRun_carry_10 : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_58 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_58;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_58 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_109
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_2 => lopt_2,
      of_PipeRun_carry_10 => of_PipeRun_carry_10
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_59 is
  port (
    of_PipeRun_carry_9 : out STD_LOGIC;
    \EX_MBAR_Stall__1\ : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    of_PipeRun_carry_10 : in STD_LOGIC;
    ex_mbar_sleep : in STD_LOGIC;
    ex_mbar_decode : in STD_LOGIC;
    ex_first_cycle : in STD_LOGIC;
    ex_mbar_stall_no_sleep_1 : in STD_LOGIC;
    ex_jump_hold : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_59 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_59;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_59 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_108
     port map (
      \EX_MBAR_Stall__1\ => \EX_MBAR_Stall__1\,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      ex_first_cycle => ex_first_cycle,
      ex_jump_hold => ex_jump_hold,
      ex_mbar_decode => ex_mbar_decode,
      ex_mbar_sleep => ex_mbar_sleep,
      ex_mbar_stall_no_sleep_1 => ex_mbar_stall_no_sleep_1,
      lopt => lopt,
      lopt_1 => lopt_1,
      of_PipeRun_carry_10 => of_PipeRun_carry_10,
      of_PipeRun_carry_9 => of_PipeRun_carry_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_60 is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \wb_exception_kind_i_reg[28]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    in0 : out STD_LOGIC;
    ex_Write_ICache_i_cmb : out STD_LOGIC;
    of_PipeRun_carry_9 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    wb_exception : in STD_LOGIC;
    \mem_pc_i_reg[0]\ : in STD_LOGIC;
    ex_Write_DCache_decode_reg : in STD_LOGIC;
    ex_write_dcache_instr : in STD_LOGIC;
    ex_Write_ICache_i : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : in STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_60 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_60;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_60 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_107
     port map (
      Q(1 downto 0) => Q(1 downto 0),
      \Using_FPGA.Native_0\ => E(0),
      ex_Write_DCache_decode_reg => ex_Write_DCache_decode_reg,
      ex_Write_ICache_i => ex_Write_ICache_i,
      ex_Write_ICache_i_reg => ex_Write_ICache_i_cmb,
      ex_write_dcache_instr => ex_write_dcache_instr,
      in0 => in0,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_2 => lopt_2,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9,
      \mem_pc_i_reg[0]\ => \mem_pc_i_reg[0]\,
      of_PipeRun_carry_9 => of_PipeRun_carry_9,
      wb_exception => wb_exception,
      \wb_exception_kind_i_reg[28]\(0) => \wb_exception_kind_i_reg[28]\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_61 is
  port (
    of_PipeRun_carry_7 : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_61 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_61;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_61 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_106
     port map (
      E(0) => E(0),
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      lopt => lopt,
      lopt_1 => lopt_1,
      of_PipeRun_carry_7 => of_PipeRun_carry_7
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_62 is
  port (
    of_PipeRun_carry_6 : out STD_LOGIC;
    A : in STD_LOGIC;
    of_PipeRun_carry_7 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_62 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_62;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_62 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_105
     port map (
      A => A,
      lopt => lopt,
      lopt_1 => lopt_1,
      of_PipeRun_carry_6 => of_PipeRun_carry_6,
      of_PipeRun_carry_7 => of_PipeRun_carry_7
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_63 is
  port (
    of_PipeRun_carry_5 : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    of_PipeRun_carry_6 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_63 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_63;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_63 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_104
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      lopt => lopt,
      lopt_1 => lopt_1,
      of_PipeRun_carry_5 => of_PipeRun_carry_5,
      of_PipeRun_carry_6 => of_PipeRun_carry_6
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_64 is
  port (
    of_PipeRun_carry_4 : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    of_PipeRun_carry_5 : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_64 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_64;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_64 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_103
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_2 => lopt_2,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9,
      of_PipeRun_carry_4 => of_PipeRun_carry_4,
      of_PipeRun_carry_5 => of_PipeRun_carry_5
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_65 is
  port (
    of_PipeRun_carry_3 : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    of_PipeRun_carry_4 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_65 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_65;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_65 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_102
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      lopt => lopt,
      lopt_1 => lopt_1,
      of_PipeRun_carry_3 => of_PipeRun_carry_3,
      of_PipeRun_carry_4 => of_PipeRun_carry_4
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_66 is
  port (
    of_PipeRun_carry_2 : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    of_PipeRun_carry_3 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_66 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_66;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_66 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_101
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      lopt => lopt,
      lopt_1 => lopt_1,
      of_PipeRun_carry_2 => of_PipeRun_carry_2,
      of_PipeRun_carry_3 => of_PipeRun_carry_3
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_86 is
  port (
    if_pc_incr_carry1 : out STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    if_pc_incr_carry0 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_86 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_86;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_86 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_100
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      if_pc_incr_carry0 => if_pc_incr_carry0,
      if_pc_incr_carry1 => if_pc_incr_carry1,
      lopt => lopt,
      lopt_1 => lopt_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_87 is
  port (
    if_pc_incr_carry0 : out STD_LOGIC;
    if_missed_fetch : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : in STD_LOGIC;
    lopt_21 : in STD_LOGIC;
    lopt_22 : in STD_LOGIC;
    lopt_23 : in STD_LOGIC;
    lopt_24 : in STD_LOGIC;
    lopt_25 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_87 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_87;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_87 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_99
     port map (
      if_missed_fetch => if_missed_fetch,
      if_pc_incr_carry0 => if_pc_incr_carry0,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_20 => lopt_20,
      lopt_21 => lopt_21,
      lopt_22 => lopt_22,
      lopt_23 => lopt_23,
      lopt_24 => lopt_24,
      lopt_25 => lopt_25,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_88 is
  port (
    CI : out STD_LOGIC;
    if_fetch_for_timing_optimization1 : in STD_LOGIC;
    if_pc_incr_carry1 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_88 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_88;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_88 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_98
     port map (
      CI => CI,
      if_fetch_for_timing_optimization1 => if_fetch_for_timing_optimization1,
      if_pc_incr_carry1 => if_pc_incr_carry1,
      lopt => lopt,
      lopt_1 => lopt_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_and_89 is
  port (
    \Using_FPGA.Native\ : out STD_LOGIC;
    mem_valid_reg : out STD_LOGIC;
    wb_valid_reg : out STD_LOGIC;
    wb_gpr_write_dbg0 : out STD_LOGIC;
    wb_gpr_write_i0 : out STD_LOGIC;
    mem_wait_on_ready_N : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    mem_exception_from_ex : in STD_LOGIC;
    mem_valid_reg_0 : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    flush_pipe : in STD_LOGIC;
    wb_valid_reg_0 : in STD_LOGIC;
    wb_valid_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    sync_reset : in STD_LOGIC;
    wb_exception : in STD_LOGIC;
    mem_gpr_write_dbg : in STD_LOGIC;
    mem_gpr_write : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_and_89 : entity is "carry_and";
end design_1_microblaze_0_0_carry_and_89;

architecture STRUCTURE of design_1_microblaze_0_0_carry_and_89 is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_91
     port map (
      E(0) => E(0),
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      flush_pipe => flush_pipe,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_2 => lopt_2,
      mem_exception_from_ex => mem_exception_from_ex,
      mem_gpr_write => mem_gpr_write,
      mem_gpr_write_dbg => mem_gpr_write_dbg,
      mem_valid_instr => mem_valid_instr,
      mem_valid_reg => mem_valid_reg,
      mem_valid_reg_0 => mem_valid_reg_0,
      mem_wait_on_ready_N => mem_wait_on_ready_N,
      sync_reset => sync_reset,
      wb_exception => wb_exception,
      wb_gpr_write_dbg0 => wb_gpr_write_dbg0,
      wb_gpr_write_i0 => wb_gpr_write_i0,
      wb_valid_reg => wb_valid_reg,
      wb_valid_reg_0 => wb_valid_reg_0,
      wb_valid_reg_1(0) => wb_valid_reg_1(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_carry_or is
  port (
    mem_wait_on_ready_N : out STD_LOGIC;
    MEM_DataBus_Ready : in STD_LOGIC;
    mem_load_store_access : in STD_LOGIC;
    mem_Write_DCache : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : out STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : out STD_LOGIC;
    lopt_10 : out STD_LOGIC;
    lopt_11 : out STD_LOGIC;
    lopt_12 : out STD_LOGIC;
    lopt_13 : in STD_LOGIC;
    lopt_14 : in STD_LOGIC;
    lopt_15 : in STD_LOGIC;
    lopt_16 : in STD_LOGIC;
    lopt_17 : in STD_LOGIC;
    lopt_18 : in STD_LOGIC;
    lopt_19 : in STD_LOGIC;
    lopt_20 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_carry_or : entity is "carry_or";
end design_1_microblaze_0_0_carry_or;

architecture STRUCTURE of design_1_microblaze_0_0_carry_or is
begin
MUXCY_I: entity work.design_1_microblaze_0_0_MB_MUXCY_90
     port map (
      MEM_DataBus_Ready => MEM_DataBus_Ready,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_12,
      lopt_13 => lopt_13,
      lopt_14 => lopt_14,
      lopt_15 => lopt_15,
      lopt_16 => lopt_16,
      lopt_17 => lopt_17,
      lopt_18 => lopt_18,
      lopt_19 => lopt_19,
      lopt_2 => lopt_2,
      lopt_20 => lopt_20,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => lopt_5,
      lopt_6 => lopt_6,
      lopt_7 => lopt_7,
      lopt_8 => lopt_8,
      lopt_9 => lopt_9,
      mem_Write_DCache => mem_Write_DCache,
      mem_load_store_access => mem_load_store_access,
      mem_valid_instr => mem_valid_instr,
      mem_wait_on_ready_N => mem_wait_on_ready_N
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_exception_registers_gti is
  port (
    DI : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC;
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC;
    \Using_FPGA.Native_5\ : out STD_LOGIC;
    \Using_FPGA.Native_6\ : out STD_LOGIC;
    \Using_FPGA.Native_7\ : out STD_LOGIC;
    \Using_FPGA.Native_8\ : out STD_LOGIC;
    \Using_FPGA.Native_9\ : out STD_LOGIC;
    \Using_FPGA.Native_10\ : out STD_LOGIC;
    \Using_FPGA.Native_11\ : out STD_LOGIC;
    \Using_FPGA.Native_12\ : out STD_LOGIC;
    \Using_FPGA.Native_13\ : out STD_LOGIC;
    \Using_FPGA.Native_14\ : out STD_LOGIC;
    \Using_FPGA.Native_15\ : out STD_LOGIC;
    \Using_FPGA.Native_16\ : out STD_LOGIC;
    \Using_FPGA.Native_17\ : out STD_LOGIC;
    \Using_FPGA.Native_18\ : out STD_LOGIC;
    \Using_FPGA.Native_19\ : out STD_LOGIC;
    \Using_FPGA.Native_20\ : out STD_LOGIC;
    \Using_FPGA.Native_21\ : out STD_LOGIC;
    \Using_FPGA.Native_22\ : out STD_LOGIC;
    \Using_FPGA.Native_23\ : out STD_LOGIC;
    \Using_FPGA.Native_24\ : out STD_LOGIC;
    \Using_FPGA.Native_25\ : out STD_LOGIC;
    \Using_FPGA.Native_26\ : out STD_LOGIC;
    \Using_FPGA.Native_27\ : out STD_LOGIC;
    \Using_FPGA.Native_28\ : out STD_LOGIC;
    \Using_FPGA.Native_29\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
    \Using_FPGA.Native_30\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \Using_FPGA.Native_31\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_32\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \Using_FPGA.Native_33\ : in STD_LOGIC;
    \Using_FPGA.Native_34\ : in STD_LOGIC;
    Clk : in STD_LOGIC;
    I1_1 : in STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[23]\ : in STD_LOGIC;
    \data_rd_reg_reg[23]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3030]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3024]\ : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \LOCKSTEP_Out_reg[3026]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3028]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3030]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3029]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3027]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3025]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3023]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_exception_registers_gti : entity is "exception_registers_gti";
end design_1_microblaze_0_0_exception_registers_gti;

architecture STRUCTURE of design_1_microblaze_0_0_exception_registers_gti is
  signal \^di\ : STD_LOGIC;
  signal O5 : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC;
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \^using_fpga.native_1\ : STD_LOGIC;
  signal \^using_fpga.native_10\ : STD_LOGIC;
  signal \^using_fpga.native_11\ : STD_LOGIC;
  signal \^using_fpga.native_12\ : STD_LOGIC;
  signal \^using_fpga.native_13\ : STD_LOGIC;
  signal \^using_fpga.native_14\ : STD_LOGIC;
  signal \^using_fpga.native_15\ : STD_LOGIC;
  signal \^using_fpga.native_16\ : STD_LOGIC;
  signal \^using_fpga.native_17\ : STD_LOGIC;
  signal \^using_fpga.native_18\ : STD_LOGIC;
  signal \^using_fpga.native_19\ : STD_LOGIC;
  signal \^using_fpga.native_2\ : STD_LOGIC;
  signal \^using_fpga.native_20\ : STD_LOGIC;
  signal \^using_fpga.native_21\ : STD_LOGIC;
  signal \^using_fpga.native_22\ : STD_LOGIC;
  signal \^using_fpga.native_23\ : STD_LOGIC;
  signal \^using_fpga.native_24\ : STD_LOGIC;
  signal \^using_fpga.native_25\ : STD_LOGIC;
  signal \^using_fpga.native_26\ : STD_LOGIC;
  signal \^using_fpga.native_27\ : STD_LOGIC;
  signal \^using_fpga.native_28\ : STD_LOGIC;
  signal \^using_fpga.native_29\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal \^using_fpga.native_3\ : STD_LOGIC;
  signal \^using_fpga.native_4\ : STD_LOGIC;
  signal \^using_fpga.native_5\ : STD_LOGIC;
  signal \^using_fpga.native_6\ : STD_LOGIC;
  signal \^using_fpga.native_7\ : STD_LOGIC;
  signal \^using_fpga.native_8\ : STD_LOGIC;
  signal \^using_fpga.native_9\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal \Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0\ : STD_LOGIC;
  signal addr_AddSub_0 : STD_LOGIC;
  signal addr_AddSub_1 : STD_LOGIC;
  signal addr_AddSub_10 : STD_LOGIC;
  signal addr_AddSub_11 : STD_LOGIC;
  signal addr_AddSub_12 : STD_LOGIC;
  signal addr_AddSub_13 : STD_LOGIC;
  signal addr_AddSub_14 : STD_LOGIC;
  signal addr_AddSub_15 : STD_LOGIC;
  signal addr_AddSub_16 : STD_LOGIC;
  signal addr_AddSub_17 : STD_LOGIC;
  signal addr_AddSub_18 : STD_LOGIC;
  signal addr_AddSub_19 : STD_LOGIC;
  signal addr_AddSub_2 : STD_LOGIC;
  signal addr_AddSub_20 : STD_LOGIC;
  signal addr_AddSub_21 : STD_LOGIC;
  signal addr_AddSub_22 : STD_LOGIC;
  signal addr_AddSub_23 : STD_LOGIC;
  signal addr_AddSub_24 : STD_LOGIC;
  signal addr_AddSub_25 : STD_LOGIC;
  signal addr_AddSub_26 : STD_LOGIC;
  signal addr_AddSub_27 : STD_LOGIC;
  signal addr_AddSub_28 : STD_LOGIC;
  signal addr_AddSub_29 : STD_LOGIC;
  signal addr_AddSub_3 : STD_LOGIC;
  signal addr_AddSub_30 : STD_LOGIC;
  signal addr_AddSub_31 : STD_LOGIC;
  signal addr_AddSub_4 : STD_LOGIC;
  signal addr_AddSub_5 : STD_LOGIC;
  signal addr_AddSub_6 : STD_LOGIC;
  signal addr_AddSub_7 : STD_LOGIC;
  signal addr_AddSub_8 : STD_LOGIC;
  signal addr_AddSub_9 : STD_LOGIC;
  signal carry_0 : STD_LOGIC;
  signal carry_1 : STD_LOGIC;
  signal carry_10 : STD_LOGIC;
  signal carry_11 : STD_LOGIC;
  signal carry_12 : STD_LOGIC;
  signal carry_13 : STD_LOGIC;
  signal carry_14 : STD_LOGIC;
  signal carry_15 : STD_LOGIC;
  signal carry_16 : STD_LOGIC;
  signal carry_17 : STD_LOGIC;
  signal carry_18 : STD_LOGIC;
  signal carry_19 : STD_LOGIC;
  signal carry_2 : STD_LOGIC;
  signal carry_20 : STD_LOGIC;
  signal carry_21 : STD_LOGIC;
  signal carry_22 : STD_LOGIC;
  signal carry_23 : STD_LOGIC;
  signal carry_24 : STD_LOGIC;
  signal carry_25 : STD_LOGIC;
  signal carry_26 : STD_LOGIC;
  signal carry_27 : STD_LOGIC;
  signal carry_28 : STD_LOGIC;
  signal carry_29 : STD_LOGIC;
  signal carry_3 : STD_LOGIC;
  signal carry_30 : STD_LOGIC;
  signal carry_31 : STD_LOGIC;
  signal carry_4 : STD_LOGIC;
  signal carry_5 : STD_LOGIC;
  signal carry_6 : STD_LOGIC;
  signal carry_7 : STD_LOGIC;
  signal carry_8 : STD_LOGIC;
  signal carry_9 : STD_LOGIC;
  signal lopt : STD_LOGIC;
  signal lopt_1 : STD_LOGIC;
  signal lopt_10 : STD_LOGIC;
  signal lopt_11 : STD_LOGIC;
  signal lopt_12 : STD_LOGIC;
  signal lopt_13 : STD_LOGIC;
  signal lopt_14 : STD_LOGIC;
  signal lopt_15 : STD_LOGIC;
  signal lopt_16 : STD_LOGIC;
  signal lopt_17 : STD_LOGIC;
  signal lopt_18 : STD_LOGIC;
  signal lopt_19 : STD_LOGIC;
  signal lopt_2 : STD_LOGIC;
  signal lopt_20 : STD_LOGIC;
  signal lopt_21 : STD_LOGIC;
  signal lopt_22 : STD_LOGIC;
  signal lopt_23 : STD_LOGIC;
  signal lopt_24 : STD_LOGIC;
  signal lopt_25 : STD_LOGIC;
  signal lopt_26 : STD_LOGIC;
  signal lopt_27 : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal lopt_29 : STD_LOGIC;
  signal lopt_3 : STD_LOGIC;
  signal lopt_30 : STD_LOGIC;
  signal lopt_31 : STD_LOGIC;
  signal lopt_32 : STD_LOGIC;
  signal lopt_33 : STD_LOGIC;
  signal lopt_34 : STD_LOGIC;
  signal lopt_35 : STD_LOGIC;
  signal lopt_36 : STD_LOGIC;
  signal lopt_37 : STD_LOGIC;
  signal lopt_38 : STD_LOGIC;
  signal lopt_39 : STD_LOGIC;
  signal lopt_4 : STD_LOGIC;
  signal lopt_40 : STD_LOGIC;
  signal lopt_41 : STD_LOGIC;
  signal lopt_42 : STD_LOGIC;
  signal lopt_43 : STD_LOGIC;
  signal lopt_44 : STD_LOGIC;
  signal lopt_45 : STD_LOGIC;
  signal lopt_46 : STD_LOGIC;
  signal lopt_47 : STD_LOGIC;
  signal lopt_48 : STD_LOGIC;
  signal lopt_49 : STD_LOGIC;
  signal lopt_5 : STD_LOGIC;
  signal lopt_50 : STD_LOGIC;
  signal lopt_51 : STD_LOGIC;
  signal lopt_52 : STD_LOGIC;
  signal lopt_53 : STD_LOGIC;
  signal lopt_54 : STD_LOGIC;
  signal lopt_55 : STD_LOGIC;
  signal lopt_56 : STD_LOGIC;
  signal lopt_57 : STD_LOGIC;
  signal lopt_58 : STD_LOGIC;
  signal lopt_59 : STD_LOGIC;
  signal lopt_6 : STD_LOGIC;
  signal lopt_60 : STD_LOGIC;
  signal lopt_61 : STD_LOGIC;
  signal lopt_62 : STD_LOGIC;
  signal lopt_63 : STD_LOGIC;
  signal lopt_64 : STD_LOGIC;
  signal lopt_65 : STD_LOGIC;
  signal lopt_66 : STD_LOGIC;
  signal lopt_67 : STD_LOGIC;
  signal lopt_68 : STD_LOGIC;
  signal lopt_69 : STD_LOGIC;
  signal lopt_7 : STD_LOGIC;
  signal lopt_70 : STD_LOGIC;
  signal lopt_71 : STD_LOGIC;
  signal lopt_72 : STD_LOGIC;
  signal lopt_73 : STD_LOGIC;
  signal lopt_74 : STD_LOGIC;
  signal lopt_75 : STD_LOGIC;
  signal lopt_76 : STD_LOGIC;
  signal lopt_77 : STD_LOGIC;
  signal lopt_78 : STD_LOGIC;
  signal lopt_79 : STD_LOGIC;
  signal lopt_8 : STD_LOGIC;
  signal lopt_9 : STD_LOGIC;
begin
  DI <= \^di\;
  \Using_FPGA.Native\ <= \^using_fpga.native\;
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  \Using_FPGA.Native_1\ <= \^using_fpga.native_1\;
  \Using_FPGA.Native_10\ <= \^using_fpga.native_10\;
  \Using_FPGA.Native_11\ <= \^using_fpga.native_11\;
  \Using_FPGA.Native_12\ <= \^using_fpga.native_12\;
  \Using_FPGA.Native_13\ <= \^using_fpga.native_13\;
  \Using_FPGA.Native_14\ <= \^using_fpga.native_14\;
  \Using_FPGA.Native_15\ <= \^using_fpga.native_15\;
  \Using_FPGA.Native_16\ <= \^using_fpga.native_16\;
  \Using_FPGA.Native_17\ <= \^using_fpga.native_17\;
  \Using_FPGA.Native_18\ <= \^using_fpga.native_18\;
  \Using_FPGA.Native_19\ <= \^using_fpga.native_19\;
  \Using_FPGA.Native_2\ <= \^using_fpga.native_2\;
  \Using_FPGA.Native_20\ <= \^using_fpga.native_20\;
  \Using_FPGA.Native_21\ <= \^using_fpga.native_21\;
  \Using_FPGA.Native_22\ <= \^using_fpga.native_22\;
  \Using_FPGA.Native_23\ <= \^using_fpga.native_23\;
  \Using_FPGA.Native_24\ <= \^using_fpga.native_24\;
  \Using_FPGA.Native_25\ <= \^using_fpga.native_25\;
  \Using_FPGA.Native_26\ <= \^using_fpga.native_26\;
  \Using_FPGA.Native_27\ <= \^using_fpga.native_27\;
  \Using_FPGA.Native_28\ <= \^using_fpga.native_28\;
  \Using_FPGA.Native_29\(8 downto 0) <= \^using_fpga.native_29\(8 downto 0);
  \Using_FPGA.Native_3\ <= \^using_fpga.native_3\;
  \Using_FPGA.Native_4\ <= \^using_fpga.native_4\;
  \Using_FPGA.Native_5\ <= \^using_fpga.native_5\;
  \Using_FPGA.Native_6\ <= \^using_fpga.native_6\;
  \Using_FPGA.Native_7\ <= \^using_fpga.native_7\;
  \Using_FPGA.Native_8\ <= \^using_fpga.native_8\;
  \Using_FPGA.Native_9\ <= \^using_fpga.native_9\;
CarryIn_MUXCY: entity work.design_1_microblaze_0_0_MB_MUXCY_307
     port map (
      CI => carry_0,
      \Using_FPGA.Native_I2\(0) => \Using_FPGA.Native_31\(0),
      lopt => lopt,
      lopt_1 => \^di\,
      lopt_10 => lopt_4,
      lopt_11 => lopt_5,
      lopt_12 => lopt_48,
      lopt_13 => lopt_49,
      lopt_14 => lopt_50,
      lopt_15 => lopt_51,
      lopt_16 => lopt_52,
      lopt_17 => lopt_53,
      lopt_18 => lopt_54,
      lopt_19 => lopt_55,
      lopt_2 => addr_AddSub_0,
      lopt_20 => \^using_fpga.native_4\,
      lopt_21 => \^using_fpga.native_3\,
      lopt_22 => \^using_fpga.native_2\,
      lopt_23 => \^using_fpga.native_1\,
      lopt_24 => addr_AddSub_6,
      lopt_25 => addr_AddSub_5,
      lopt_26 => addr_AddSub_4,
      lopt_27 => addr_AddSub_3,
      lopt_3 => lopt_1,
      lopt_4 => \^using_fpga.native\,
      lopt_5 => addr_AddSub_1,
      lopt_6 => lopt_2,
      lopt_7 => \^using_fpga.native_0\,
      lopt_8 => addr_AddSub_2,
      lopt_9 => lopt_3
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5\
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \^using_fpga.native_29\(8),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(31),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\,
      addr_AddSub_31 => addr_AddSub_31
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[0].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_308
     port map (
      LO => carry_31,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(23),
      addr_AddSub_31 => addr_AddSub_31
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[0].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\(0) => \^using_fpga.native_29\(8),
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_309\
     port map (
      S => addr_AddSub_21,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_19\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(21),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[10].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_310
     port map (
      LO => carry_22,
      \LOCKSTEP_Out_reg[3017]\ => carry_21,
      S => addr_AddSub_21,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(13),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_19\,
      lopt => lopt_31,
      lopt_1 => lopt_34
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[10].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_311
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_19\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_312\
     port map (
      S => addr_AddSub_20,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_18\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(20),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[11].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_313
     port map (
      LO => carry_21,
      \LOCKSTEP_Out_reg[3018]\ => carry_20,
      S => addr_AddSub_20,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(12),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_18\,
      lopt => lopt_30,
      lopt_1 => lopt_33
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[11].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_314
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_18\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_315\
     port map (
      S => addr_AddSub_19,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_17\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(19),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[12].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_316
     port map (
      LO => carry_20,
      \LOCKSTEP_Out_reg[3019]\ => carry_19,
      S => addr_AddSub_19,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(11),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_17\,
      lopt => lopt_30,
      lopt_1 => \^using_fpga.native_18\,
      lopt_10 => lopt_34,
      lopt_11 => lopt_35,
      lopt_12 => lopt_64,
      lopt_13 => lopt_65,
      lopt_14 => lopt_66,
      lopt_15 => lopt_67,
      lopt_16 => lopt_68,
      lopt_17 => lopt_69,
      lopt_18 => lopt_70,
      lopt_19 => lopt_71,
      lopt_2 => addr_AddSub_20,
      lopt_3 => lopt_31,
      lopt_4 => \^using_fpga.native_19\,
      lopt_5 => addr_AddSub_21,
      lopt_6 => lopt_32,
      lopt_7 => \^using_fpga.native_20\,
      lopt_8 => addr_AddSub_22,
      lopt_9 => lopt_33
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[12].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_317
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_17\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_318\
     port map (
      S => addr_AddSub_18,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_16\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(18),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[13].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_319
     port map (
      LO => carry_19,
      \LOCKSTEP_Out_reg[3020]\ => carry_18,
      S => addr_AddSub_18,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(10),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_16\,
      lopt => lopt_26,
      lopt_1 => lopt_29
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[13].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_320
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_16\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_321\
     port map (
      S => addr_AddSub_17,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_15\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(17),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[14].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_322
     port map (
      LO => carry_18,
      \LOCKSTEP_Out_reg[3021]\ => carry_17,
      S => addr_AddSub_17,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(9),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_15\,
      lopt => lopt_25,
      lopt_1 => lopt_28
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[14].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_323
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_15\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_324\
     port map (
      S => addr_AddSub_16,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_14\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(16),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[15].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_325
     port map (
      LO => carry_17,
      \LOCKSTEP_Out_reg[3022]\ => carry_16,
      S => addr_AddSub_16,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(8),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_14\,
      lopt => lopt_24,
      lopt_1 => lopt_27
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[15].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_326
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_14\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_327\
     port map (
      DI => \^using_fpga.native_13\,
      S => addr_AddSub_15,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(15),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[16].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_328
     port map (
      DI => \^using_fpga.native_13\,
      LO => carry_16,
      \LOCKSTEP_Out_reg[3023]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3023]_0\ => \LOCKSTEP_Out_reg[3023]\,
      \LOCKSTEP_Out_reg[3023]_1\ => carry_15,
      Q(0) => Q(7),
      S => addr_AddSub_15,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(7),
      \data_rd_reg_reg[16]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[16]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_24,
      lopt_1 => \^using_fpga.native_14\,
      lopt_10 => lopt_28,
      lopt_11 => lopt_29,
      lopt_12 => lopt_64,
      lopt_13 => lopt_65,
      lopt_14 => lopt_66,
      lopt_15 => lopt_67,
      lopt_16 => lopt_68,
      lopt_17 => lopt_69,
      lopt_18 => lopt_70,
      lopt_19 => lopt_71,
      lopt_2 => addr_AddSub_16,
      lopt_20 => \^using_fpga.native_20\,
      lopt_21 => \^using_fpga.native_19\,
      lopt_22 => \^using_fpga.native_18\,
      lopt_23 => \^using_fpga.native_17\,
      lopt_24 => addr_AddSub_22,
      lopt_25 => addr_AddSub_21,
      lopt_26 => addr_AddSub_20,
      lopt_27 => addr_AddSub_19,
      lopt_3 => lopt_25,
      lopt_4 => \^using_fpga.native_15\,
      lopt_5 => addr_AddSub_17,
      lopt_6 => lopt_26,
      lopt_7 => \^using_fpga.native_16\,
      lopt_8 => addr_AddSub_18,
      lopt_9 => lopt_27,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(7)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[16].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_329
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_13\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_330\
     port map (
      DI => \^using_fpga.native_12\,
      S => addr_AddSub_14,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(14),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[17].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_331
     port map (
      DI => \^using_fpga.native_12\,
      LO => carry_15,
      \LOCKSTEP_Out_reg[3024]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3024]_0\ => \LOCKSTEP_Out_reg[3024]\,
      \LOCKSTEP_Out_reg[3024]_1\ => carry_14,
      Q(0) => Q(6),
      S => addr_AddSub_14,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(6),
      \data_rd_reg_reg[17]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[17]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_20,
      lopt_1 => lopt_23,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(6)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[17].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_332
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_12\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_333\
     port map (
      DI => \^using_fpga.native_11\,
      S => addr_AddSub_13,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(13),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[18].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_334
     port map (
      DI => \^using_fpga.native_11\,
      LO => carry_14,
      \LOCKSTEP_Out_reg[3025]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3025]_0\ => \LOCKSTEP_Out_reg[3025]\,
      \LOCKSTEP_Out_reg[3025]_1\ => carry_13,
      Q(0) => Q(5),
      S => addr_AddSub_13,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(5),
      \data_rd_reg_reg[18]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[18]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_19,
      lopt_1 => lopt_22,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(5)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[18].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_335
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_11\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_336\
     port map (
      DI => \^using_fpga.native_10\,
      S => addr_AddSub_12,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(12),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[19].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_337
     port map (
      DI => \^using_fpga.native_10\,
      LO => carry_13,
      \LOCKSTEP_Out_reg[3026]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3026]_0\ => \LOCKSTEP_Out_reg[3026]\,
      \LOCKSTEP_Out_reg[3026]_1\ => carry_12,
      Q(0) => Q(4),
      S => addr_AddSub_12,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(4),
      \data_rd_reg_reg[19]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[19]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_18,
      lopt_1 => lopt_21,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(4)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[19].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_338
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_10\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_339\
     port map (
      S => addr_AddSub_30,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_28\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(30),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[1].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_340
     port map (
      LO => carry_31,
      \LOCKSTEP_Out_reg[3008]\ => carry_30,
      S => addr_AddSub_30,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(22),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_28\,
      lopt => lopt_44,
      lopt_1 => lopt_47
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[1].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_341
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_28\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_342\
     port map (
      DI => \^using_fpga.native_9\,
      S => addr_AddSub_11,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(11),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[20].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_343
     port map (
      DI => \^using_fpga.native_9\,
      LO => carry_12,
      \LOCKSTEP_Out_reg[3027]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3027]_0\ => \LOCKSTEP_Out_reg[3027]\,
      \LOCKSTEP_Out_reg[3027]_1\ => carry_11,
      Q(0) => Q(3),
      S => addr_AddSub_11,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(3),
      \data_rd_reg_reg[20]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[20]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_18,
      lopt_1 => \^using_fpga.native_10\,
      lopt_10 => lopt_22,
      lopt_11 => lopt_23,
      lopt_12 => lopt_56,
      lopt_13 => lopt_57,
      lopt_14 => lopt_58,
      lopt_15 => lopt_59,
      lopt_16 => lopt_60,
      lopt_17 => lopt_61,
      lopt_18 => lopt_62,
      lopt_19 => lopt_63,
      lopt_2 => addr_AddSub_12,
      lopt_3 => lopt_19,
      lopt_4 => \^using_fpga.native_11\,
      lopt_5 => addr_AddSub_13,
      lopt_6 => lopt_20,
      lopt_7 => \^using_fpga.native_12\,
      lopt_8 => addr_AddSub_14,
      lopt_9 => lopt_21,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(3)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[20].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_344
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_9\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_345\
     port map (
      DI => \^using_fpga.native_8\,
      S => addr_AddSub_10,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(10),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[21].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_346
     port map (
      DI => \^using_fpga.native_8\,
      LO => carry_11,
      \LOCKSTEP_Out_reg[3028]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3028]_0\ => \LOCKSTEP_Out_reg[3028]\,
      \LOCKSTEP_Out_reg[3028]_1\ => carry_10,
      Q(0) => Q(2),
      S => addr_AddSub_10,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(2),
      \data_rd_reg_reg[21]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[21]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_14,
      lopt_1 => lopt_17,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(2)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[21].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_347
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_8\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_348\
     port map (
      DI => \^using_fpga.native_7\,
      S => addr_AddSub_9,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(9),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[22].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_349
     port map (
      DI => \^using_fpga.native_7\,
      LO => carry_10,
      \LOCKSTEP_Out_reg[3029]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3029]_0\ => \LOCKSTEP_Out_reg[3029]\,
      \LOCKSTEP_Out_reg[3029]_1\ => carry_9,
      Q(0) => Q(1),
      S => addr_AddSub_9,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(1),
      \data_rd_reg_reg[22]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[22]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_13,
      lopt_1 => lopt_16,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(1)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[22].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_350
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_7\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_351\
     port map (
      DI => \^using_fpga.native_6\,
      S => addr_AddSub_8,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_32\(8),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[23].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_352
     port map (
      DI => \^using_fpga.native_6\,
      LO => carry_9,
      \LOCKSTEP_Out_reg[3030]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3030]_0\ => \LOCKSTEP_Out_reg[3030]_0\,
      \LOCKSTEP_Out_reg[3030]_1\ => carry_8,
      Q(0) => Q(0),
      S => addr_AddSub_8,
      WB_Byte_Access_reg(0) => \^using_fpga.native_29\(0),
      \data_rd_reg_reg[23]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[23]_0\ => \data_rd_reg_reg[23]_0\,
      lopt => lopt_12,
      lopt_1 => lopt_15,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(0) => wb_gpr_write_dbg_reg(0)
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[23].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_353
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_6\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_354\
     port map (
      S => addr_AddSub_7,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_5\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(7),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[24].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_355
     port map (
      LO => carry_8,
      \LOCKSTEP_Out_reg[3031]\ => carry_7,
      S => addr_AddSub_7,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(7),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_5\,
      lopt => lopt_12,
      lopt_1 => \^using_fpga.native_6\,
      lopt_10 => lopt_16,
      lopt_11 => lopt_17,
      lopt_12 => lopt_56,
      lopt_13 => lopt_57,
      lopt_14 => lopt_58,
      lopt_15 => lopt_59,
      lopt_16 => lopt_60,
      lopt_17 => lopt_61,
      lopt_18 => lopt_62,
      lopt_19 => lopt_63,
      lopt_2 => addr_AddSub_8,
      lopt_20 => \^using_fpga.native_12\,
      lopt_21 => \^using_fpga.native_11\,
      lopt_22 => \^using_fpga.native_10\,
      lopt_23 => \^using_fpga.native_9\,
      lopt_24 => addr_AddSub_14,
      lopt_25 => addr_AddSub_13,
      lopt_26 => addr_AddSub_12,
      lopt_27 => addr_AddSub_11,
      lopt_3 => lopt_13,
      lopt_4 => \^using_fpga.native_7\,
      lopt_5 => addr_AddSub_9,
      lopt_6 => lopt_14,
      lopt_7 => \^using_fpga.native_8\,
      lopt_8 => addr_AddSub_10,
      lopt_9 => lopt_15
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[24].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_356
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_5\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_357\
     port map (
      S => addr_AddSub_6,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_4\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(6),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[25].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_358
     port map (
      LO => carry_7,
      \LOCKSTEP_Out_reg[3032]\ => carry_6,
      S => addr_AddSub_6,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(6),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_4\,
      lopt => lopt_8,
      lopt_1 => lopt_11
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[25].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_359
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_4\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_360\
     port map (
      S => addr_AddSub_5,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_3\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(5),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[26].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_361
     port map (
      LO => carry_6,
      \LOCKSTEP_Out_reg[3033]\ => carry_5,
      S => addr_AddSub_5,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(5),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_3\,
      lopt => lopt_7,
      lopt_1 => lopt_10
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[26].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_362
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_3\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_363\
     port map (
      S => addr_AddSub_4,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_2\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(4),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[27].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_364
     port map (
      LO => carry_5,
      \LOCKSTEP_Out_reg[3034]\ => carry_4,
      S => addr_AddSub_4,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(4),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_2\,
      lopt => lopt_6,
      lopt_1 => lopt_9
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[27].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_365
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_2\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_366\
     port map (
      S => addr_AddSub_3,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_1\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(3),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[28].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_367
     port map (
      LO => carry_4,
      \LOCKSTEP_Out_reg[3035]\ => carry_3,
      S => addr_AddSub_3,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(3),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_1\,
      lopt => lopt_6,
      lopt_1 => \^using_fpga.native_2\,
      lopt_10 => lopt_10,
      lopt_11 => lopt_11,
      lopt_12 => lopt_48,
      lopt_13 => lopt_49,
      lopt_14 => lopt_50,
      lopt_15 => lopt_51,
      lopt_16 => lopt_52,
      lopt_17 => lopt_53,
      lopt_18 => lopt_54,
      lopt_19 => lopt_55,
      lopt_2 => addr_AddSub_4,
      lopt_3 => lopt_7,
      lopt_4 => \^using_fpga.native_3\,
      lopt_5 => addr_AddSub_5,
      lopt_6 => lopt_8,
      lopt_7 => \^using_fpga.native_4\,
      lopt_8 => addr_AddSub_6,
      lopt_9 => lopt_9
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[28].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_368
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_1\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_369\
     port map (
      I1_1 => I1_1,
      S => addr_AddSub_2,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_0\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(2),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[29].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_370
     port map (
      LO => carry_3,
      \LOCKSTEP_Out_reg[3036]\ => carry_2,
      S => addr_AddSub_2,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(2),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_0\,
      lopt => lopt_2,
      lopt_1 => lopt_5
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[29].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_371
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_372\
     port map (
      S => addr_AddSub_29,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_27\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(29),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[2].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_373
     port map (
      LO => carry_30,
      \LOCKSTEP_Out_reg[3009]\ => carry_29,
      S => addr_AddSub_29,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(21),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_27\,
      lopt => lopt_43,
      lopt_1 => lopt_46
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[2].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_374
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_27\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_375\
     port map (
      S => addr_AddSub_1,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(1),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[30].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_376
     port map (
      LO => carry_2,
      \LOCKSTEP_Out_reg[3037]\ => carry_1,
      S => addr_AddSub_1,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(1),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native\,
      lopt => lopt_1,
      lopt_1 => lopt_4
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[30].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_377
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[31].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_378\
     port map (
      DI => \^di\,
      O5 => O5,
      S => addr_AddSub_0,
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_32\(0),
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[31].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_379
     port map (
      CI => carry_0,
      DI => \^di\,
      LO => carry_1,
      S => addr_AddSub_0,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(0),
      lopt => lopt,
      lopt_1 => lopt_3
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[31].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_380
     port map (
      Clk => Clk,
      DI => \^di\,
      O5 => O5,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_34\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_381\
     port map (
      S => addr_AddSub_28,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_26\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(28),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[3].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_382
     port map (
      LO => carry_29,
      \LOCKSTEP_Out_reg[3010]\ => carry_28,
      S => addr_AddSub_28,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(20),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_26\,
      lopt => lopt_42,
      lopt_1 => lopt_45
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[3].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_383
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_26\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_384\
     port map (
      S => addr_AddSub_27,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_25\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(27),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[4].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_385
     port map (
      LO => carry_28,
      \LOCKSTEP_Out_reg[3011]\ => carry_27,
      S => addr_AddSub_27,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(19),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_25\,
      lopt => lopt_42,
      lopt_1 => \^using_fpga.native_26\,
      lopt_10 => lopt_46,
      lopt_11 => lopt_47,
      lopt_12 => lopt_72,
      lopt_13 => lopt_73,
      lopt_14 => lopt_74,
      lopt_15 => lopt_75,
      lopt_16 => lopt_76,
      lopt_17 => lopt_77,
      lopt_18 => lopt_78,
      lopt_19 => lopt_79,
      lopt_2 => addr_AddSub_28,
      lopt_3 => lopt_43,
      lopt_4 => \^using_fpga.native_27\,
      lopt_5 => addr_AddSub_29,
      lopt_6 => lopt_44,
      lopt_7 => \^using_fpga.native_28\,
      lopt_8 => addr_AddSub_30,
      lopt_9 => lopt_45
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[4].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_386
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_25\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_387\
     port map (
      S => addr_AddSub_26,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_24\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(26),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[5].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_388
     port map (
      LO => carry_27,
      \LOCKSTEP_Out_reg[3012]\ => carry_26,
      S => addr_AddSub_26,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(18),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_24\,
      lopt => lopt_38,
      lopt_1 => lopt_41
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[5].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_389
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_24\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_390\
     port map (
      S => addr_AddSub_25,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_23\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(25),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[6].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_391
     port map (
      LO => carry_26,
      \LOCKSTEP_Out_reg[3013]\ => carry_25,
      S => addr_AddSub_25,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(17),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_23\,
      lopt => lopt_37,
      lopt_1 => lopt_40
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[6].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_392
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_23\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_393\
     port map (
      S => addr_AddSub_24,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_22\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(24),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[7].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_394
     port map (
      LO => carry_25,
      \LOCKSTEP_Out_reg[3014]\ => carry_24,
      S => addr_AddSub_24,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(16),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_22\,
      lopt => lopt_36,
      lopt_1 => lopt_39
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[7].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_395
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_22\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_396\
     port map (
      S => addr_AddSub_23,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_21\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(23),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[8].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_397
     port map (
      LO => carry_24,
      \LOCKSTEP_Out_reg[3015]\ => carry_23,
      S => addr_AddSub_23,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(15),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_21\,
      lopt => lopt_36,
      lopt_1 => \^using_fpga.native_22\,
      lopt_10 => lopt_40,
      lopt_11 => lopt_41,
      lopt_12 => lopt_72,
      lopt_13 => lopt_73,
      lopt_14 => lopt_74,
      lopt_15 => lopt_75,
      lopt_16 => lopt_76,
      lopt_17 => lopt_77,
      lopt_18 => lopt_78,
      lopt_19 => lopt_79,
      lopt_2 => addr_AddSub_24,
      lopt_20 => \^using_fpga.native_28\,
      lopt_21 => \^using_fpga.native_27\,
      lopt_22 => \^using_fpga.native_26\,
      lopt_23 => \^using_fpga.native_25\,
      lopt_24 => addr_AddSub_30,
      lopt_25 => addr_AddSub_29,
      lopt_26 => addr_AddSub_28,
      lopt_27 => addr_AddSub_27,
      lopt_3 => lopt_37,
      lopt_4 => \^using_fpga.native_23\,
      lopt_5 => addr_AddSub_25,
      lopt_6 => lopt_38,
      lopt_7 => \^using_fpga.native_24\,
      lopt_8 => addr_AddSub_26,
      lopt_9 => lopt_39
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[8].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_398
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_21\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB_n_0\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized5_399\
     port map (
      S => addr_AddSub_22,
      \Using_FPGA.Native_0\ => \Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0\,
      \Using_FPGA.Native_1\ => \^using_fpga.native_20\,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_31\(0),
      \Using_FPGA.Native_3\(0) => \Using_FPGA.Native_32\(22),
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_33\
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[9].MUXCY_XOR_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_XORCY_400
     port map (
      CI => carry_22,
      LO => carry_23,
      S => addr_AddSub_22,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native_30\(14),
      \Using_FPGA.Native_I2_0\ => \^using_fpga.native_20\,
      lopt => lopt_32,
      lopt_1 => lopt_35
    );
\Using_FPGA_LUT6.Gen_Ret_Addr[9].WB_PC_FDE\: entity work.design_1_microblaze_0_0_MB_FDE_401
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => \^using_fpga.native_20\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_2\ => \Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_jump_logic is
  port (
    ex_jump : out STD_LOGIC;
    ex_op1_cmp_equal : out STD_LOGIC;
    ex_op1_cmp_equal_n : out STD_LOGIC;
    ex_jump_q : out STD_LOGIC;
    I5 : out STD_LOGIC;
    of_next_ex_valid : out STD_LOGIC;
    ex_jump_hold_reg : out STD_LOGIC;
    ex_delayslot_Instr0 : out STD_LOGIC;
    keep_jump_taken_with_ds_reg : out STD_LOGIC;
    mem_jump_taken0 : out STD_LOGIC;
    \if_pc_reg[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \Using_FPGA.Native\ : out STD_LOGIC;
    ex_op1_zero : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    use_Reg_Neg_S_reg_0 : in STD_LOGIC;
    ex_op1_cmp_eq_reg_0 : in STD_LOGIC;
    Clk : in STD_LOGIC;
    ex_op1_cmp_eq_n5_out : in STD_LOGIC;
    force_Val2_N_reg_0 : in STD_LOGIC;
    ex_op1_cmp_eq1 : in STD_LOGIC;
    use_Reg_Neg_DI1_out : in STD_LOGIC;
    force_Val10_out : in STD_LOGIC;
    use_Reg_Neg_S3_out : in STD_LOGIC;
    force12_out : in STD_LOGIC;
    \Using_FPGA.Native_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    wb_exception : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \out\ : in STD_LOGIC;
    ex_Exception_Taken : in STD_LOGIC;
    ex_jump_nodelay : in STD_LOGIC;
    of_valid : in STD_LOGIC;
    mem_exception_from_ex : in STD_LOGIC;
    mem_valid_instr : in STD_LOGIC;
    ex_jump_hold : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    keep_jump_taken_with_ds : in STD_LOGIC;
    ex_branch_with_delayslot : in STD_LOGIC;
    ex_mbar_stall_no_sleep_1 : in STD_LOGIC;
    ex_first_cycle : in STD_LOGIC;
    ex_mbar_decode : in STD_LOGIC;
    ex_mbar_sleep : in STD_LOGIC;
    ex_databus_addr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \if_pc_reg[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \if_pc_reg[0]_0\ : in STD_LOGIC_VECTOR ( 29 downto 0 );
    O : in STD_LOGIC;
    \if_pc_reg[28]\ : in STD_LOGIC;
    \if_pc_reg[27]\ : in STD_LOGIC;
    \if_pc_reg[26]\ : in STD_LOGIC;
    \if_pc_reg[25]\ : in STD_LOGIC;
    \if_pc_reg[24]\ : in STD_LOGIC;
    \if_pc_reg[23]\ : in STD_LOGIC;
    \if_pc_reg[22]\ : in STD_LOGIC;
    \if_pc_reg[21]\ : in STD_LOGIC;
    \if_pc_reg[20]\ : in STD_LOGIC;
    \if_pc_reg[19]\ : in STD_LOGIC;
    \if_pc_reg[18]\ : in STD_LOGIC;
    \if_pc_reg[17]\ : in STD_LOGIC;
    \if_pc_reg[16]\ : in STD_LOGIC;
    \if_pc_reg[15]\ : in STD_LOGIC;
    \if_pc_reg[14]\ : in STD_LOGIC;
    \if_pc_reg[13]\ : in STD_LOGIC;
    \if_pc_reg[12]\ : in STD_LOGIC;
    \if_pc_reg[11]\ : in STD_LOGIC;
    \if_pc_reg[10]\ : in STD_LOGIC;
    \if_pc_reg[9]\ : in STD_LOGIC;
    \if_pc_reg[8]\ : in STD_LOGIC;
    \if_pc_reg[7]\ : in STD_LOGIC;
    \if_pc_reg[6]\ : in STD_LOGIC;
    \if_pc_reg[5]\ : in STD_LOGIC;
    \if_pc_reg[4]\ : in STD_LOGIC;
    \if_pc_reg[3]\ : in STD_LOGIC;
    \if_pc_reg[2]\ : in STD_LOGIC;
    \if_pc_reg[1]\ : in STD_LOGIC;
    O56_out : in STD_LOGIC;
    \EX_MBAR_Stall__1\ : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_jump_logic : entity is "jump_logic";
end design_1_microblaze_0_0_jump_logic;

architecture STRUCTURE of design_1_microblaze_0_0_jump_logic is
  signal DI : STD_LOGIC;
  signal MUXCY_JUMP_CARRY6_n_39 : STD_LOGIC;
  signal S : STD_LOGIC;
  signal \^ex_jump_q\ : STD_LOGIC;
  signal ex_jump_wanted : STD_LOGIC;
  signal force1_reg_n_0 : STD_LOGIC;
  signal force2 : STD_LOGIC;
  signal force_Val1_reg_n_0 : STD_LOGIC;
  signal force_Val2_N : STD_LOGIC;
  signal jump_carry1 : STD_LOGIC;
  signal jump_carry2 : STD_LOGIC;
  signal jump_carry4 : STD_LOGIC;
  signal jump_carry5 : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal lopt_10 : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal lopt_3 : STD_LOGIC;
  signal lopt_4 : STD_LOGIC;
  signal lopt_5 : STD_LOGIC;
  signal lopt_6 : STD_LOGIC;
  signal lopt_7 : STD_LOGIC;
  signal lopt_8 : STD_LOGIC;
  signal lopt_9 : STD_LOGIC;
  signal of_PipeRun_for_ce : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of of_PipeRun_for_ce : signal is std.standard.true;
  signal reset_bool_for_rst : STD_LOGIC;
  attribute DIRECT_RESET : boolean;
  attribute DIRECT_RESET of reset_bool_for_rst : signal is std.standard.true;
  signal use_Reg_Neg_DI_reg_n_0 : STD_LOGIC;
  signal use_Reg_Neg_S_reg_n_0 : STD_LOGIC;
begin
  ex_jump_q <= \^ex_jump_q\;
  lopt_1 <= DI;
  lopt_2 <= S;
  of_PipeRun_for_ce <= use_Reg_Neg_S_reg_0;
  reset_bool_for_rst <= sync_reset;
MUXCY_JUMP_CARRY: entity work.design_1_microblaze_0_0_MB_MUXCY_92
     port map (
      DI => DI,
      S => S,
      ex_op1_zero => ex_op1_zero,
      jump_carry1 => jump_carry1,
      lopt => lopt
    );
MUXCY_JUMP_CARRY2: entity work.design_1_microblaze_0_0_MB_MUXCY_93
     port map (
      force2 => force2,
      force_Val2_N => force_Val2_N,
      jump_carry1 => jump_carry1,
      jump_carry2 => jump_carry2,
      lopt => \^lopt_1\,
      lopt_1 => \^lopt_2\,
      lopt_10 => lopt_9,
      lopt_11 => lopt_10,
      lopt_2 => \Using_FPGA.Native_0\,
      lopt_3 => lopt_3,
      lopt_4 => lopt_4,
      lopt_5 => \Using_FPGA.Native_1\,
      lopt_6 => lopt_5,
      lopt_7 => lopt_6,
      lopt_8 => lopt_7,
      lopt_9 => lopt_8,
      \out\ => \out\
    );
MUXCY_JUMP_CARRY3: entity work.design_1_microblaze_0_0_MB_MUXCY_94
     port map (
      \EX_MBAR_Stall__1\ => \EX_MBAR_Stall__1\,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_0\,
      ex_branch_with_delayslot => ex_branch_with_delayslot,
      ex_jump_wanted => ex_jump_wanted,
      jump_carry2 => jump_carry2,
      lopt => \^lopt_1\,
      lopt_1 => \^lopt_2\,
      of_valid => of_valid
    );
MUXCY_JUMP_CARRY4: entity work.design_1_microblaze_0_0_MB_MUXCY_95
     port map (
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_1\,
      ex_jump_wanted => ex_jump_wanted,
      jump_carry4 => jump_carry4,
      lopt => lopt_3,
      lopt_1 => lopt_4
    );
MUXCY_JUMP_CARRY5: entity work.design_1_microblaze_0_0_MB_MUXCY_96
     port map (
      jump_carry4 => jump_carry4,
      jump_carry5 => jump_carry5,
      lopt => lopt_5,
      lopt_1 => lopt_6,
      lopt_2 => lopt_7
    );
MUXCY_JUMP_CARRY6: entity work.design_1_microblaze_0_0_MB_MUXCY_97
     port map (
      E(0) => E(0),
      I5 => I5,
      O => O,
      O56_out => O56_out,
      Q(1 downto 0) => Q(1 downto 0),
      ex_Exception_Taken => ex_Exception_Taken,
      ex_branch_with_delayslot => ex_branch_with_delayslot,
      ex_databus_addr(1 downto 0) => ex_databus_addr(1 downto 0),
      ex_delayslot_Instr0 => ex_delayslot_Instr0,
      ex_first_cycle => ex_first_cycle,
      ex_jump_hold => ex_jump_hold,
      ex_jump_hold_reg => ex_jump,
      ex_jump_hold_reg_0 => ex_jump_hold_reg,
      ex_jump_nodelay => ex_jump_nodelay,
      ex_jump_q => \^ex_jump_q\,
      ex_jump_q_reg => MUXCY_JUMP_CARRY6_n_39,
      ex_mbar_decode => ex_mbar_decode,
      ex_mbar_sleep => ex_mbar_sleep,
      ex_mbar_stall_no_sleep_1 => ex_mbar_stall_no_sleep_1,
      \if_pc_reg[0]\(31 downto 0) => \if_pc_reg[0]\(31 downto 0),
      \if_pc_reg[0]_0\(29 downto 0) => \if_pc_reg[0]_0\(29 downto 0),
      \if_pc_reg[10]\ => \if_pc_reg[10]\,
      \if_pc_reg[11]\ => \if_pc_reg[11]\,
      \if_pc_reg[12]\ => \if_pc_reg[12]\,
      \if_pc_reg[13]\ => \if_pc_reg[13]\,
      \if_pc_reg[14]\ => \if_pc_reg[14]\,
      \if_pc_reg[15]\ => \if_pc_reg[15]\,
      \if_pc_reg[16]\ => \if_pc_reg[16]\,
      \if_pc_reg[17]\ => \if_pc_reg[17]\,
      \if_pc_reg[18]\ => \if_pc_reg[18]\,
      \if_pc_reg[19]\ => \if_pc_reg[19]\,
      \if_pc_reg[1]\ => \if_pc_reg[1]\,
      \if_pc_reg[20]\ => \if_pc_reg[20]\,
      \if_pc_reg[21]\ => \if_pc_reg[21]\,
      \if_pc_reg[22]\ => \if_pc_reg[22]\,
      \if_pc_reg[23]\ => \if_pc_reg[23]\,
      \if_pc_reg[24]\ => \if_pc_reg[24]\,
      \if_pc_reg[25]\ => \if_pc_reg[25]\,
      \if_pc_reg[26]\ => \if_pc_reg[26]\,
      \if_pc_reg[27]\ => \if_pc_reg[27]\,
      \if_pc_reg[28]\ => \if_pc_reg[28]\,
      \if_pc_reg[2]\ => \if_pc_reg[2]\,
      \if_pc_reg[30]\(1 downto 0) => \if_pc_reg[30]\(1 downto 0),
      \if_pc_reg[3]\ => \if_pc_reg[3]\,
      \if_pc_reg[4]\ => \if_pc_reg[4]\,
      \if_pc_reg[5]\ => \if_pc_reg[5]\,
      \if_pc_reg[6]\ => \if_pc_reg[6]\,
      \if_pc_reg[7]\ => \if_pc_reg[7]\,
      \if_pc_reg[8]\ => \if_pc_reg[8]\,
      \if_pc_reg[9]\ => \if_pc_reg[9]\,
      jump_carry5 => jump_carry5,
      keep_jump_taken_with_ds => keep_jump_taken_with_ds,
      keep_jump_taken_with_ds_reg => keep_jump_taken_with_ds_reg,
      keep_jump_taken_with_ds_reg_0 => of_PipeRun_for_ce,
      lopt => lopt_8,
      lopt_1 => lopt_9,
      lopt_2 => lopt_10,
      mem_exception_from_ex => mem_exception_from_ex,
      mem_jump_taken0 => mem_jump_taken0,
      mem_valid_instr => mem_valid_instr,
      of_next_ex_valid => of_next_ex_valid,
      of_valid => of_valid,
      sync_reset => reset_bool_for_rst,
      wb_exception => wb_exception
    );
ex_jump_q_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => MUXCY_JUMP_CARRY6_n_39,
      Q => \^ex_jump_q\,
      R => '0'
    );
ex_op1_cmp_eq_n_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_op1_cmp_eq_n5_out,
      Q => ex_op1_cmp_equal_n,
      R => reset_bool_for_rst
    );
ex_op1_cmp_eq_reg: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_op1_cmp_eq_reg_0,
      Q => ex_op1_cmp_equal,
      S => reset_bool_for_rst
    );
force1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => force12_out,
      Q => force1_reg_n_0,
      R => reset_bool_for_rst
    );
force2_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_op1_cmp_eq1,
      Q => force2,
      R => reset_bool_for_rst
    );
force_DI1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A6"
    )
        port map (
      I0 => force_Val1_reg_n_0,
      I1 => use_Reg_Neg_DI_reg_n_0,
      I2 => \Using_FPGA.Native_2\(0),
      O => DI
    );
force_Val1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => force_Val10_out,
      Q => force_Val1_reg_n_0,
      R => reset_bool_for_rst
    );
force_Val2_N_reg: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => force_Val2_N_reg_0,
      Q => force_Val2_N,
      S => reset_bool_for_rst
    );
force_jump1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A6"
    )
        port map (
      I0 => force1_reg_n_0,
      I1 => use_Reg_Neg_S_reg_n_0,
      I2 => \Using_FPGA.Native_2\(0),
      O => S
    );
use_Reg_Neg_DI_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => use_Reg_Neg_DI1_out,
      Q => use_Reg_Neg_DI_reg_n_0,
      R => reset_bool_for_rst
    );
use_Reg_Neg_S_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => use_Reg_Neg_S3_out,
      Q => use_Reg_Neg_S_reg_n_0,
      R => reset_bool_for_rst
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mb_sync_vec is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    dbg_hit : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Clk : in STD_LOGIC;
    \Single_Synchronize.use_async_reset.sync_reg\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mb_sync_vec : entity is "mb_sync_vec";
end design_1_microblaze_0_0_mb_sync_vec;

architecture STRUCTURE of design_1_microblaze_0_0_mb_sync_vec is
begin
\sync_bits[0].sync_bit\: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized2_56\
     port map (
      D(0) => D(0),
      Dbg_Clk => Dbg_Clk,
      \Single_Synchronize.use_async_reset.sync_reg_0\ => \Single_Synchronize.use_async_reset.sync_reg\,
      dbg_hit(0) => dbg_hit(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \design_1_microblaze_0_0_mb_sync_vec__parameterized1\ is
  port (
    sample_synced : out STD_LOGIC_VECTOR ( 0 to 9 );
    \Use_Async_Reset.sync_reset_reg\ : out STD_LOGIC;
    p_11_out : out STD_LOGIC;
    \Serial_Dbg_Intf.trig_ack_out_1_reg\ : out STD_LOGIC;
    p_88_out : out STD_LOGIC;
    p_91_out : out STD_LOGIC;
    p_76_out : out STD_LOGIC;
    p_86_out : out STD_LOGIC;
    p_83_out : out STD_LOGIC;
    p_94_out : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
    Dbg_Trig_Ack_Out : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Trig_In : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    Clk : in STD_LOGIC;
    \Synchronize.use_sync_reset.sync_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Synchronize.use_sync_reset.sync_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Synchronize.use_sync_reset.sync_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Synchronize.use_sync_reset.sync_reg[1]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Synchronize.use_sync_reset.sync_reg[1]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Trig_Out : in STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Trig_Ack_In : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Synchronize.use_sync_reset.sync_reg[1]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \design_1_microblaze_0_0_mb_sync_vec__parameterized1\ : entity is "mb_sync_vec";
end \design_1_microblaze_0_0_mb_sync_vec__parameterized1\;

architecture STRUCTURE of \design_1_microblaze_0_0_mb_sync_vec__parameterized1\ is
  signal \^sample_synced\ : STD_LOGIC_VECTOR ( 0 to 9 );
begin
  sample_synced(0 to 9) <= \^sample_synced\(0 to 9);
\sync_bits[0].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_46
     port map (
      Clk => Clk,
      D(0) => D(0),
      Q(0) => Q(8),
      p_94_out => p_94_out,
      sample_synced(0) => \^sample_synced\(0),
      sync_reset => sync_reset
    );
\sync_bits[1].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_47
     port map (
      Clk => Clk,
      Q(0) => Q(7),
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \Synchronize.use_sync_reset.sync_reg[1]\(0),
      p_91_out => p_91_out,
      sample_synced(0) => \^sample_synced\(1),
      sync_reset => sync_reset
    );
\sync_bits[2].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_48
     port map (
      Clk => Clk,
      Q(0) => Q(6),
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \Synchronize.use_sync_reset.sync_reg[1]_0\(0),
      p_88_out => p_88_out,
      sample_synced(0) => \^sample_synced\(2),
      sync_reset => sync_reset
    );
\sync_bits[3].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_49
     port map (
      Clk => Clk,
      Q(0) => Q(5),
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \Synchronize.use_sync_reset.sync_reg[1]_1\(1),
      p_86_out => p_86_out,
      sample_synced(0) => \^sample_synced\(3),
      sync_reset => sync_reset
    );
\sync_bits[4].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_50
     port map (
      Clk => Clk,
      Q(0) => Q(4),
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \Synchronize.use_sync_reset.sync_reg[1]_1\(0),
      p_83_out => p_83_out,
      sample_synced(0) => \^sample_synced\(4),
      sync_reset => sync_reset
    );
\sync_bits[5].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_51
     port map (
      Clk => Clk,
      Dbg_Trig_In(0) => Dbg_Trig_In(0),
      Q(3) => Q(6),
      Q(2) => Q(3),
      Q(1 downto 0) => Q(1 downto 0),
      \Serial_Dbg_Intf.trig_in_1_reg\(2) => \^sample_synced\(2),
      \Serial_Dbg_Intf.trig_in_1_reg\(1) => \^sample_synced\(7),
      \Serial_Dbg_Intf.trig_in_1_reg\(0) => \^sample_synced\(8),
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \Synchronize.use_sync_reset.sync_reg[1]_2\(0),
      \Use_Async_Reset.sync_reset_reg\ => \Use_Async_Reset.sync_reset_reg\,
      p_11_out => p_11_out,
      sample_synced(0) => \^sample_synced\(5),
      sync_reset => sync_reset
    );
\sync_bits[6].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_52
     port map (
      Clk => Clk,
      Q(0) => Q(2),
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \Synchronize.use_sync_reset.sync_reg[1]_3\(0),
      p_76_out => p_76_out,
      sample_synced(0) => \^sample_synced\(6),
      sync_reset => sync_reset
    );
\sync_bits[7].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_53
     port map (
      Clk => Clk,
      Dbg_Trig_Ack_Out(0) => Dbg_Trig_Ack_Out(0),
      Dbg_Trig_Out(0) => Dbg_Trig_Out(0),
      Q(0) => Q(1),
      \Serial_Dbg_Intf.trig_ack_out_1_reg\ => \Serial_Dbg_Intf.trig_ack_out_1_reg\,
      sample_synced(0) => \^sample_synced\(7),
      sync_reset => sync_reset
    );
\sync_bits[8].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_54
     port map (
      Clk => Clk,
      Dbg_Trig_Ack_In(0) => Dbg_Trig_Ack_In(0),
      sample_synced(0) => \^sample_synced\(8),
      sync_reset => sync_reset
    );
\sync_bits[9].sync_bit\: entity work.design_1_microblaze_0_0_mb_sync_bit_55
     port map (
      Clk => Clk,
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \Synchronize.use_sync_reset.sync_reg[1]_4\(0),
      sample_synced(0) => \^sample_synced\(9),
      sync_reset => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_msr_reg_gti is
  port (
    ex_MSR : out STD_LOGIC_VECTOR ( 2 downto 0 );
    MEM_Fwd : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \wb_MSR_i_reg[28]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    sync_reset : in STD_LOGIC;
    Clk : in STD_LOGIC;
    \Using_FPGA.Native\ : in STD_LOGIC;
    \Using_FPGA.Native_0\ : in STD_LOGIC;
    \Using_FPGA.Native_1\ : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC;
    \WB_MEM_Result_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \Using_FPGA.Native_2\ : in STD_LOGIC;
    \wb_MSR_i_reg[30]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_msr_reg_gti : entity is "msr_reg_gti";
end design_1_microblaze_0_0_msr_reg_gti;

architecture STRUCTURE of design_1_microblaze_0_0_msr_reg_gti is
  signal \OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I_n_1\ : STD_LOGIC;
  signal \OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I_n_1\ : STD_LOGIC;
  signal \OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I_n_1\ : STD_LOGIC;
  signal mem_MSR : STD_LOGIC_VECTOR ( 28 to 30 );
begin
\MEM_MSR_Bits[28].Using_FDR.MSR_I\: entity work.design_1_microblaze_0_0_MB_FDR_301
     port map (
      Clk => Clk,
      D(0) => mem_MSR(28),
      MEM_Fwd(0) => MEM_Fwd(2),
      \Using_FPGA.Native_0\ => \OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I_n_1\,
      \WB_MEM_Result_reg[28]\(0) => \WB_MEM_Result_reg[0]\(2),
      mem_sel_msr => mem_sel_msr,
      sync_reset => sync_reset
    );
\MEM_MSR_Bits[29].Using_FDR.MSR_I\: entity work.design_1_microblaze_0_0_MB_FDR_302
     port map (
      Clk => Clk,
      MEM_Fwd(1) => MEM_Fwd(3),
      MEM_Fwd(0) => MEM_Fwd(1),
      \Using_FPGA.Native_0\ => \OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I_n_1\,
      \WB_MEM_Result_reg[0]\(1) => \WB_MEM_Result_reg[0]\(3),
      \WB_MEM_Result_reg[0]\(0) => \WB_MEM_Result_reg[0]\(1),
      mem_MSR(0) => mem_MSR(29),
      mem_sel_msr => mem_sel_msr,
      sync_reset => sync_reset
    );
\MEM_MSR_Bits[30].Using_FDR.MSR_I\: entity work.design_1_microblaze_0_0_MB_FDR_303
     port map (
      Clk => Clk,
      D(0) => mem_MSR(30),
      MEM_Fwd(0) => MEM_Fwd(0),
      \Using_FPGA.Native_0\ => \OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I_n_1\,
      \WB_MEM_Result_reg[30]\(0) => \WB_MEM_Result_reg[0]\(0),
      mem_sel_msr => mem_sel_msr,
      sync_reset => sync_reset
    );
\OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I\: entity work.design_1_microblaze_0_0_MB_FDR_304
     port map (
      Clk => Clk,
      D(0) => mem_MSR(28),
      \Using_FPGA.Native_0\ => \OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I_n_1\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_2\,
      ex_MSR(0) => ex_MSR(2),
      sync_reset => sync_reset
    );
\OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I\: entity work.design_1_microblaze_0_0_MB_FDR_305
     port map (
      Clk => Clk,
      D(0) => mem_MSR(29),
      \Using_FPGA.Native_0\ => \OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I_n_1\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_0\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_2\,
      ex_MSR(0) => ex_MSR(1),
      sync_reset => sync_reset
    );
\OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I\: entity work.design_1_microblaze_0_0_MB_FDR_306
     port map (
      Clk => Clk,
      D(0) => mem_MSR(30),
      \Using_FPGA.Native_0\ => \OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I_n_1\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_1\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_2\,
      ex_MSR(0) => ex_MSR(0),
      sync_reset => sync_reset
    );
\wb_MSR_i_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \wb_MSR_i_reg[30]_0\(0),
      D => mem_MSR(28),
      Q => \wb_MSR_i_reg[28]_0\(2),
      R => sync_reset
    );
\wb_MSR_i_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \wb_MSR_i_reg[30]_0\(0),
      D => mem_MSR(29),
      Q => \wb_MSR_i_reg[28]_0\(1),
      R => sync_reset
    );
\wb_MSR_i_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \wb_MSR_i_reg[30]_0\(0),
      D => mem_MSR(30),
      Q => \wb_MSR_i_reg[28]_0\(0),
      R => sync_reset
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_mux_bus is
  port (
    I139_out : out STD_LOGIC;
    Y : out STD_LOGIC_VECTOR ( 0 to 31 );
    \in\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 32 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_mux_bus : entity is "mux_bus";
end design_1_microblaze_0_0_mux_bus;

architecture STRUCTURE of design_1_microblaze_0_0_mux_bus is
  signal \^y\ : STD_LOGIC_VECTOR ( 0 to 31 );
begin
  Y(0 to 31) <= \^y\(0 to 31);
\Mux_Loop[0].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3\
     port map (
      I139_out => I139_out,
      Instr(1) => Instr(0),
      Instr(0) => Instr(16),
      LOCKSTEP_Master_Out(2 downto 1) => LOCKSTEP_Master_Out(32 downto 31),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(15),
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native\(0),
      \Using_FPGA.Native_1\(0) => \Using_FPGA.Native_0\(0),
      \Using_FPGA.Native_2\(1) => \^y\(1),
      \Using_FPGA.Native_2\(0) => \^y\(3),
      Y(1) => \^y\(0),
      Y(0) => \^y\(16),
      \in\(0) => \in\(0)
    );
\Mux_Loop[10].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_2\
     port map (
      Instr(1) => Instr(10),
      Instr(0) => Instr(26),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(21),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(5),
      Y(1) => \^y\(10),
      Y(0) => \^y\(26)
    );
\Mux_Loop[11].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_3\
     port map (
      Instr(1) => Instr(11),
      Instr(0) => Instr(27),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(20),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(4),
      Y(1) => \^y\(11),
      Y(0) => \^y\(27)
    );
\Mux_Loop[12].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_4\
     port map (
      Instr(1) => Instr(12),
      Instr(0) => Instr(28),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(19),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(3),
      Y(1) => \^y\(12),
      Y(0) => \^y\(28)
    );
\Mux_Loop[13].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_5\
     port map (
      Instr(1) => Instr(13),
      Instr(0) => Instr(29),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(18),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(2),
      Y(1) => \^y\(13),
      Y(0) => \^y\(29)
    );
\Mux_Loop[14].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_6\
     port map (
      Instr(1) => Instr(14),
      Instr(0) => Instr(30),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(17),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(1),
      Y(1) => \^y\(14),
      Y(0) => \^y\(30)
    );
\Mux_Loop[15].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_7\
     port map (
      Instr(1) => Instr(15),
      Instr(0) => Instr(31),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(16),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(0),
      Y(1) => \^y\(15),
      Y(0) => \^y\(31)
    );
\Mux_Loop[1].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_8\
     port map (
      Instr(1) => Instr(1),
      Instr(0) => Instr(17),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(30),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(14),
      Y(1) => \^y\(1),
      Y(0) => \^y\(17)
    );
\Mux_Loop[2].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_9\
     port map (
      Instr(1) => Instr(2),
      Instr(0) => Instr(18),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(29),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(13),
      Y(1) => \^y\(2),
      Y(0) => \^y\(18)
    );
\Mux_Loop[3].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_10\
     port map (
      Instr(1) => Instr(3),
      Instr(0) => Instr(19),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(28),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(12),
      Y(1) => \^y\(3),
      Y(0) => \^y\(19)
    );
\Mux_Loop[4].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_11\
     port map (
      Instr(1) => Instr(4),
      Instr(0) => Instr(20),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(27),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(11),
      Y(1) => \^y\(4),
      Y(0) => \^y\(20)
    );
\Mux_Loop[5].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_12\
     port map (
      Instr(1) => Instr(5),
      Instr(0) => Instr(21),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(26),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(10),
      Y(1) => \^y\(5),
      Y(0) => \^y\(21)
    );
\Mux_Loop[6].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_13\
     port map (
      Instr(1) => Instr(6),
      Instr(0) => Instr(22),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(25),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(9),
      Y(1) => \^y\(6),
      Y(0) => \^y\(22)
    );
\Mux_Loop[7].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_14\
     port map (
      Instr(1) => Instr(7),
      Instr(0) => Instr(23),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(24),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(8),
      Y(1) => \^y\(7),
      Y(0) => \^y\(23)
    );
\Mux_Loop[8].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_15\
     port map (
      Instr(1) => Instr(8),
      Instr(0) => Instr(24),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(23),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(7),
      Y(1) => \^y\(8),
      Y(0) => \^y\(24)
    );
\Mux_Loop[9].I_MUX_LUT6\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized3_16\
     port map (
      Instr(1) => Instr(9),
      Instr(0) => Instr(25),
      LOCKSTEP_Master_Out(2) => LOCKSTEP_Master_Out(32),
      LOCKSTEP_Master_Out(1) => LOCKSTEP_Master_Out(22),
      LOCKSTEP_Master_Out(0) => LOCKSTEP_Master_Out(6),
      Y(1) => \^y\(9),
      Y(0) => \^y\(25)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_ALU is
  port (
    LO : out STD_LOGIC;
    \EX_Op2_reg[0]\ : out STD_LOGIC_VECTOR ( 29 downto 0 );
    ex_databus_addr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_use_carry : in STD_LOGIC;
    DI_0 : in STD_LOGIC;
    ex_alu_carryin : in STD_LOGIC;
    S : in STD_LOGIC;
    ex_unsigned_op : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \MEM_DataBus_Addr_reg[9]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \Using_FPGA.Native\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    I2 : in STD_LOGIC;
    I0 : in STD_LOGIC;
    lopt : in STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : out STD_LOGIC;
    lopt_3 : out STD_LOGIC;
    lopt_4 : in STD_LOGIC;
    lopt_5 : in STD_LOGIC;
    lopt_6 : in STD_LOGIC;
    lopt_7 : in STD_LOGIC;
    lopt_8 : in STD_LOGIC;
    lopt_9 : in STD_LOGIC;
    lopt_10 : in STD_LOGIC;
    lopt_11 : in STD_LOGIC;
    lopt_12 : in STD_LOGIC;
    lopt_13 : out STD_LOGIC;
    lopt_14 : out STD_LOGIC;
    lopt_15 : out STD_LOGIC;
    lopt_16 : out STD_LOGIC;
    lopt_17 : out STD_LOGIC;
    lopt_18 : out STD_LOGIC;
    lopt_19 : out STD_LOGIC;
    lopt_20 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_ALU : entity is "ALU";
end design_1_microblaze_0_0_ALU;

architecture STRUCTURE of design_1_microblaze_0_0_ALU is
  signal alu_carry_1 : STD_LOGIC;
  signal alu_carry_10 : STD_LOGIC;
  signal alu_carry_11 : STD_LOGIC;
  signal alu_carry_12 : STD_LOGIC;
  signal alu_carry_13 : STD_LOGIC;
  signal alu_carry_14 : STD_LOGIC;
  signal alu_carry_15 : STD_LOGIC;
  signal alu_carry_16 : STD_LOGIC;
  signal alu_carry_17 : STD_LOGIC;
  signal alu_carry_18 : STD_LOGIC;
  signal alu_carry_19 : STD_LOGIC;
  signal alu_carry_2 : STD_LOGIC;
  signal alu_carry_20 : STD_LOGIC;
  signal alu_carry_21 : STD_LOGIC;
  signal alu_carry_22 : STD_LOGIC;
  signal alu_carry_23 : STD_LOGIC;
  signal alu_carry_24 : STD_LOGIC;
  signal alu_carry_25 : STD_LOGIC;
  signal alu_carry_26 : STD_LOGIC;
  signal alu_carry_27 : STD_LOGIC;
  signal alu_carry_28 : STD_LOGIC;
  signal alu_carry_29 : STD_LOGIC;
  signal alu_carry_3 : STD_LOGIC;
  signal alu_carry_30 : STD_LOGIC;
  signal alu_carry_31 : STD_LOGIC;
  signal alu_carry_4 : STD_LOGIC;
  signal alu_carry_5 : STD_LOGIC;
  signal alu_carry_6 : STD_LOGIC;
  signal alu_carry_7 : STD_LOGIC;
  signal alu_carry_8 : STD_LOGIC;
  signal alu_carry_9 : STD_LOGIC;
  signal alu_carry_in : STD_LOGIC;
  signal \^lopt_10\ : STD_LOGIC;
  signal lopt_100 : STD_LOGIC;
  signal lopt_101 : STD_LOGIC;
  signal lopt_102 : STD_LOGIC;
  signal lopt_103 : STD_LOGIC;
  signal lopt_104 : STD_LOGIC;
  signal lopt_105 : STD_LOGIC;
  signal lopt_106 : STD_LOGIC;
  signal lopt_107 : STD_LOGIC;
  signal lopt_108 : STD_LOGIC;
  signal lopt_109 : STD_LOGIC;
  signal \^lopt_11\ : STD_LOGIC;
  signal lopt_110 : STD_LOGIC;
  signal lopt_111 : STD_LOGIC;
  signal lopt_112 : STD_LOGIC;
  signal lopt_113 : STD_LOGIC;
  signal lopt_114 : STD_LOGIC;
  signal lopt_115 : STD_LOGIC;
  signal lopt_116 : STD_LOGIC;
  signal lopt_117 : STD_LOGIC;
  signal lopt_118 : STD_LOGIC;
  signal lopt_119 : STD_LOGIC;
  signal \^lopt_12\ : STD_LOGIC;
  signal lopt_120 : STD_LOGIC;
  signal lopt_121 : STD_LOGIC;
  signal lopt_122 : STD_LOGIC;
  signal lopt_123 : STD_LOGIC;
  signal lopt_124 : STD_LOGIC;
  signal lopt_125 : STD_LOGIC;
  signal lopt_126 : STD_LOGIC;
  signal lopt_127 : STD_LOGIC;
  signal lopt_128 : STD_LOGIC;
  signal lopt_129 : STD_LOGIC;
  signal \^lopt_13\ : STD_LOGIC;
  signal lopt_130 : STD_LOGIC;
  signal lopt_131 : STD_LOGIC;
  signal lopt_132 : STD_LOGIC;
  signal lopt_133 : STD_LOGIC;
  signal lopt_134 : STD_LOGIC;
  signal lopt_135 : STD_LOGIC;
  signal lopt_136 : STD_LOGIC;
  signal lopt_137 : STD_LOGIC;
  signal \^lopt_14\ : STD_LOGIC;
  signal \^lopt_15\ : STD_LOGIC;
  signal \^lopt_16\ : STD_LOGIC;
  signal \^lopt_17\ : STD_LOGIC;
  signal \^lopt_18\ : STD_LOGIC;
  signal \^lopt_19\ : STD_LOGIC;
  signal \^lopt_20\ : STD_LOGIC;
  signal lopt_21 : STD_LOGIC;
  signal lopt_22 : STD_LOGIC;
  signal lopt_23 : STD_LOGIC;
  signal lopt_24 : STD_LOGIC;
  signal lopt_25 : STD_LOGIC;
  signal lopt_26 : STD_LOGIC;
  signal lopt_27 : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal lopt_29 : STD_LOGIC;
  signal lopt_30 : STD_LOGIC;
  signal lopt_31 : STD_LOGIC;
  signal lopt_32 : STD_LOGIC;
  signal lopt_33 : STD_LOGIC;
  signal lopt_34 : STD_LOGIC;
  signal lopt_35 : STD_LOGIC;
  signal lopt_36 : STD_LOGIC;
  signal lopt_37 : STD_LOGIC;
  signal lopt_38 : STD_LOGIC;
  signal lopt_39 : STD_LOGIC;
  signal lopt_40 : STD_LOGIC;
  signal lopt_41 : STD_LOGIC;
  signal lopt_42 : STD_LOGIC;
  signal lopt_43 : STD_LOGIC;
  signal lopt_44 : STD_LOGIC;
  signal lopt_45 : STD_LOGIC;
  signal lopt_46 : STD_LOGIC;
  signal lopt_47 : STD_LOGIC;
  signal lopt_48 : STD_LOGIC;
  signal lopt_49 : STD_LOGIC;
  signal \^lopt_5\ : STD_LOGIC;
  signal lopt_50 : STD_LOGIC;
  signal lopt_51 : STD_LOGIC;
  signal lopt_52 : STD_LOGIC;
  signal lopt_53 : STD_LOGIC;
  signal lopt_54 : STD_LOGIC;
  signal lopt_55 : STD_LOGIC;
  signal lopt_56 : STD_LOGIC;
  signal lopt_57 : STD_LOGIC;
  signal lopt_58 : STD_LOGIC;
  signal lopt_59 : STD_LOGIC;
  signal \^lopt_6\ : STD_LOGIC;
  signal lopt_60 : STD_LOGIC;
  signal lopt_61 : STD_LOGIC;
  signal lopt_62 : STD_LOGIC;
  signal lopt_63 : STD_LOGIC;
  signal lopt_64 : STD_LOGIC;
  signal lopt_65 : STD_LOGIC;
  signal lopt_66 : STD_LOGIC;
  signal lopt_67 : STD_LOGIC;
  signal lopt_68 : STD_LOGIC;
  signal lopt_69 : STD_LOGIC;
  signal \^lopt_7\ : STD_LOGIC;
  signal lopt_70 : STD_LOGIC;
  signal lopt_71 : STD_LOGIC;
  signal lopt_72 : STD_LOGIC;
  signal lopt_73 : STD_LOGIC;
  signal lopt_74 : STD_LOGIC;
  signal lopt_75 : STD_LOGIC;
  signal lopt_76 : STD_LOGIC;
  signal lopt_77 : STD_LOGIC;
  signal lopt_78 : STD_LOGIC;
  signal lopt_79 : STD_LOGIC;
  signal \^lopt_8\ : STD_LOGIC;
  signal lopt_80 : STD_LOGIC;
  signal lopt_81 : STD_LOGIC;
  signal lopt_82 : STD_LOGIC;
  signal lopt_83 : STD_LOGIC;
  signal lopt_84 : STD_LOGIC;
  signal lopt_85 : STD_LOGIC;
  signal lopt_86 : STD_LOGIC;
  signal lopt_87 : STD_LOGIC;
  signal lopt_88 : STD_LOGIC;
  signal lopt_89 : STD_LOGIC;
  signal \^lopt_9\ : STD_LOGIC;
  signal lopt_90 : STD_LOGIC;
  signal lopt_91 : STD_LOGIC;
  signal lopt_92 : STD_LOGIC;
  signal lopt_93 : STD_LOGIC;
  signal lopt_94 : STD_LOGIC;
  signal lopt_95 : STD_LOGIC;
  signal lopt_96 : STD_LOGIC;
  signal lopt_97 : STD_LOGIC;
  signal lopt_98 : STD_LOGIC;
  signal lopt_99 : STD_LOGIC;
begin
  lopt_100 <= lopt_7;
  lopt_101 <= lopt_8;
  lopt_102 <= lopt_9;
  lopt_103 <= lopt_10;
  lopt_104 <= lopt_11;
  lopt_105 <= lopt_12;
  lopt_13 <= \^lopt_12\;
  lopt_14 <= \^lopt_9\;
  lopt_15 <= \^lopt_6\;
  lopt_16 <= lopt_106;
  lopt_17 <= \^lopt_13\;
  lopt_18 <= \^lopt_10\;
  lopt_19 <= \^lopt_7\;
  lopt_20 <= lopt_107;
  lopt_98 <= lopt_5;
  lopt_99 <= lopt_6;
\Use_Carry_Decoding.CarryIn_MUXCY\: entity work.design_1_microblaze_0_0_MB_MUXCY_488
     port map (
      CI => alu_carry_in,
      DI_0 => DI_0,
      ex_alu_carryin => ex_alu_carryin,
      ex_use_carry => ex_use_carry,
      lopt => lopt
    );
\Using_FPGA.ALL_Bits[0].ALU_Bit_I1\: entity work.\design_1_microblaze_0_0_ALU_Bit__parameterized2\
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[0]\ => LO,
      \EX_Op2_reg[0]_0\(0) => \EX_Op2_reg[0]\(29),
      I0 => I0,
      I2 => I2,
      LO => alu_carry_31,
      \MEM_DataBus_Addr_reg[0]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      Q(0) => Q(31),
      S => S,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native\(31),
      ex_unsigned_op => ex_unsigned_op,
      lopt => lopt_92,
      lopt_1 => lopt_93,
      lopt_2 => lopt_94,
      lopt_3 => lopt_95,
      lopt_4 => lopt_97
    );
\Using_FPGA.ALL_Bits[10].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_22,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[10]\(0) => \EX_Op2_reg[0]\(19),
      LO => alu_carry_21,
      \MEM_DataBus_Addr_reg[10]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[10]_0\(0) => \Using_FPGA.Native\(21),
      Q(0) => Q(21),
      lopt => lopt_65,
      lopt_1 => lopt_66,
      lopt_10 => lopt_75,
      lopt_11 => lopt_76,
      lopt_12 => lopt_128,
      lopt_13 => lopt_129,
      lopt_14 => lopt_130,
      lopt_15 => lopt_131,
      lopt_16 => lopt_132,
      lopt_17 => lopt_133,
      lopt_18 => lopt_134,
      lopt_19 => lopt_135,
      lopt_2 => lopt_67,
      lopt_20 => lopt_84,
      lopt_21 => lopt_81,
      lopt_22 => lopt_78,
      lopt_23 => lopt_136,
      lopt_24 => lopt_85,
      lopt_25 => lopt_82,
      lopt_26 => lopt_79,
      lopt_27 => lopt_137,
      lopt_3 => lopt_68,
      lopt_4 => lopt_69,
      lopt_5 => lopt_70,
      lopt_6 => lopt_71,
      lopt_7 => lopt_72,
      lopt_8 => lopt_73,
      lopt_9 => lopt_74
    );
\Using_FPGA.ALL_Bits[11].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_489
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_21,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[11]\(0) => \EX_Op2_reg[0]\(18),
      LO => alu_carry_20,
      \MEM_DataBus_Addr_reg[11]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[11]_0\(0) => \Using_FPGA.Native\(20),
      Q(0) => Q(20),
      lopt => lopt_59,
      lopt_1 => lopt_60,
      lopt_2 => lopt_61,
      lopt_3 => lopt_64
    );
\Using_FPGA.ALL_Bits[12].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_490
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_20,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[12]\(0) => \EX_Op2_reg[0]\(17),
      LO => alu_carry_19,
      \MEM_DataBus_Addr_reg[12]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[12]_0\(0) => \Using_FPGA.Native\(19),
      Q(0) => Q(19),
      lopt => lopt_56,
      lopt_1 => lopt_57,
      lopt_2 => lopt_58,
      lopt_3 => lopt_63
    );
\Using_FPGA.ALL_Bits[13].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_491
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_19,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[13]\(0) => \EX_Op2_reg[0]\(16),
      LO => alu_carry_18,
      \MEM_DataBus_Addr_reg[13]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[13]_0\(0) => \Using_FPGA.Native\(18),
      Q(0) => Q(18),
      lopt => lopt_53,
      lopt_1 => lopt_54,
      lopt_2 => lopt_55,
      lopt_3 => lopt_62
    );
\Using_FPGA.ALL_Bits[14].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_492
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_18,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[14]\(0) => \EX_Op2_reg[0]\(15),
      LO => alu_carry_17,
      \MEM_DataBus_Addr_reg[14]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[14]_0\(0) => \Using_FPGA.Native\(17),
      Q(0) => Q(17),
      lopt => lopt_53,
      lopt_1 => lopt_54,
      lopt_10 => lopt_63,
      lopt_11 => lopt_64,
      lopt_12 => lopt_118,
      lopt_13 => lopt_119,
      lopt_14 => lopt_120,
      lopt_15 => lopt_121,
      lopt_16 => lopt_122,
      lopt_17 => lopt_123,
      lopt_18 => lopt_124,
      lopt_19 => lopt_125,
      lopt_2 => lopt_55,
      lopt_20 => lopt_126,
      lopt_21 => lopt_127,
      lopt_3 => lopt_56,
      lopt_4 => lopt_57,
      lopt_5 => lopt_58,
      lopt_6 => lopt_59,
      lopt_7 => lopt_60,
      lopt_8 => lopt_61,
      lopt_9 => lopt_62
    );
\Using_FPGA.ALL_Bits[15].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_493
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_17,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[15]\(0) => \EX_Op2_reg[0]\(14),
      LO => alu_carry_16,
      \MEM_DataBus_Addr_reg[15]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[15]_0\(0) => \Using_FPGA.Native\(16),
      Q(0) => Q(16),
      lopt => lopt_47,
      lopt_1 => lopt_48,
      lopt_2 => lopt_49,
      lopt_3 => lopt_52
    );
\Using_FPGA.ALL_Bits[16].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_494
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_16,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[16]\(0) => \EX_Op2_reg[0]\(13),
      LO => alu_carry_15,
      \MEM_DataBus_Addr_reg[16]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[16]_0\(0) => \Using_FPGA.Native\(15),
      Q(0) => Q(15),
      lopt => lopt_44,
      lopt_1 => lopt_45,
      lopt_2 => lopt_46,
      lopt_3 => lopt_51
    );
\Using_FPGA.ALL_Bits[17].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_495
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_15,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[17]\(0) => \EX_Op2_reg[0]\(12),
      LO => alu_carry_14,
      \MEM_DataBus_Addr_reg[17]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[17]_0\(0) => \Using_FPGA.Native\(14),
      Q(0) => Q(14),
      lopt => lopt_41,
      lopt_1 => lopt_42,
      lopt_2 => lopt_43,
      lopt_3 => lopt_50
    );
\Using_FPGA.ALL_Bits[18].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_496
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_14,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[18]\(0) => \EX_Op2_reg[0]\(11),
      LO => alu_carry_13,
      \MEM_DataBus_Addr_reg[18]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[18]_0\(0) => \Using_FPGA.Native\(13),
      Q(0) => Q(13),
      lopt => lopt_41,
      lopt_1 => lopt_42,
      lopt_10 => lopt_51,
      lopt_11 => lopt_52,
      lopt_12 => lopt_118,
      lopt_13 => lopt_119,
      lopt_14 => lopt_120,
      lopt_15 => lopt_121,
      lopt_16 => lopt_122,
      lopt_17 => lopt_123,
      lopt_18 => lopt_124,
      lopt_19 => lopt_125,
      lopt_2 => lopt_43,
      lopt_20 => lopt_60,
      lopt_21 => lopt_57,
      lopt_22 => lopt_54,
      lopt_23 => lopt_126,
      lopt_24 => lopt_61,
      lopt_25 => lopt_58,
      lopt_26 => lopt_55,
      lopt_27 => lopt_127,
      lopt_3 => lopt_44,
      lopt_4 => lopt_45,
      lopt_5 => lopt_46,
      lopt_6 => lopt_47,
      lopt_7 => lopt_48,
      lopt_8 => lopt_49,
      lopt_9 => lopt_50
    );
\Using_FPGA.ALL_Bits[19].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_497
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_13,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[19]\(0) => \EX_Op2_reg[0]\(10),
      LO => alu_carry_12,
      \MEM_DataBus_Addr_reg[19]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[19]_0\(0) => \Using_FPGA.Native\(12),
      Q(0) => Q(12),
      lopt => lopt_35,
      lopt_1 => lopt_36,
      lopt_2 => lopt_37,
      lopt_3 => lopt_40
    );
\Using_FPGA.ALL_Bits[1].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_498
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_31,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[1]\(0) => \EX_Op2_reg[0]\(28),
      LO => alu_carry_30,
      \MEM_DataBus_Addr_reg[1]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[1]_0\(0) => \Using_FPGA.Native\(30),
      Q(0) => Q(30),
      lopt => lopt_89,
      lopt_1 => lopt_90,
      lopt_2 => lopt_91,
      lopt_3 => lopt_96
    );
\Using_FPGA.ALL_Bits[20].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_499
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_12,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[20]\(0) => \EX_Op2_reg[0]\(9),
      LO => alu_carry_11,
      \MEM_DataBus_Addr_reg[20]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[20]_0\(0) => \Using_FPGA.Native\(11),
      Q(0) => Q(11),
      lopt => lopt_32,
      lopt_1 => lopt_33,
      lopt_2 => lopt_34,
      lopt_3 => lopt_39
    );
\Using_FPGA.ALL_Bits[21].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_500
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_11,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[21]\(0) => \EX_Op2_reg[0]\(8),
      LO => alu_carry_10,
      \MEM_DataBus_Addr_reg[21]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[21]_0\(0) => \Using_FPGA.Native\(10),
      Q(0) => Q(10),
      lopt => lopt_29,
      lopt_1 => lopt_30,
      lopt_2 => lopt_31,
      lopt_3 => lopt_38
    );
\Using_FPGA.ALL_Bits[22].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_501
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_10,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[22]\(0) => \EX_Op2_reg[0]\(7),
      LO => alu_carry_9,
      \MEM_DataBus_Addr_reg[22]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[22]_0\(0) => \Using_FPGA.Native\(9),
      Q(0) => Q(9),
      lopt => lopt_29,
      lopt_1 => lopt_30,
      lopt_10 => lopt_39,
      lopt_11 => lopt_40,
      lopt_12 => lopt_108,
      lopt_13 => lopt_109,
      lopt_14 => lopt_110,
      lopt_15 => lopt_111,
      lopt_16 => lopt_112,
      lopt_17 => lopt_113,
      lopt_18 => lopt_114,
      lopt_19 => lopt_115,
      lopt_2 => lopt_31,
      lopt_20 => lopt_116,
      lopt_21 => lopt_117,
      lopt_3 => lopt_32,
      lopt_4 => lopt_33,
      lopt_5 => lopt_34,
      lopt_6 => lopt_35,
      lopt_7 => lopt_36,
      lopt_8 => lopt_37,
      lopt_9 => lopt_38
    );
\Using_FPGA.ALL_Bits[23].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_502
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_9,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[23]\(0) => \EX_Op2_reg[0]\(6),
      LO => alu_carry_8,
      \MEM_DataBus_Addr_reg[23]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[23]_0\(0) => \Using_FPGA.Native\(8),
      Q(0) => Q(8),
      lopt => lopt_23,
      lopt_1 => lopt_24,
      lopt_2 => lopt_25,
      lopt_3 => lopt_28
    );
\Using_FPGA.ALL_Bits[24].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_503
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_8,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[24]\(0) => \EX_Op2_reg[0]\(5),
      LO => alu_carry_7,
      \MEM_DataBus_Addr_reg[24]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[24]_0\(0) => \Using_FPGA.Native\(7),
      Q(0) => Q(7),
      lopt => \^lopt_20\,
      lopt_1 => lopt_21,
      lopt_2 => lopt_22,
      lopt_3 => lopt_27
    );
\Using_FPGA.ALL_Bits[25].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_504
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_7,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[25]\(0) => \EX_Op2_reg[0]\(4),
      LO => alu_carry_6,
      \MEM_DataBus_Addr_reg[25]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[25]_0\(0) => \Using_FPGA.Native\(6),
      Q(0) => Q(6),
      lopt => \^lopt_17\,
      lopt_1 => \^lopt_18\,
      lopt_2 => \^lopt_19\,
      lopt_3 => lopt_26
    );
\Using_FPGA.ALL_Bits[26].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_505
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_6,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[26]\(0) => \EX_Op2_reg[0]\(3),
      LO => alu_carry_5,
      \MEM_DataBus_Addr_reg[26]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[26]_0\(0) => \Using_FPGA.Native\(5),
      Q(0) => Q(5),
      lopt => \^lopt_17\,
      lopt_1 => \^lopt_18\,
      lopt_10 => lopt_27,
      lopt_11 => lopt_28,
      lopt_12 => lopt_108,
      lopt_13 => lopt_109,
      lopt_14 => lopt_110,
      lopt_15 => lopt_111,
      lopt_16 => lopt_112,
      lopt_17 => lopt_113,
      lopt_18 => lopt_114,
      lopt_19 => lopt_115,
      lopt_2 => \^lopt_19\,
      lopt_20 => lopt_36,
      lopt_21 => lopt_33,
      lopt_22 => lopt_30,
      lopt_23 => lopt_116,
      lopt_24 => lopt_37,
      lopt_25 => lopt_34,
      lopt_26 => lopt_31,
      lopt_27 => lopt_117,
      lopt_3 => \^lopt_20\,
      lopt_4 => lopt_21,
      lopt_5 => lopt_22,
      lopt_6 => lopt_23,
      lopt_7 => lopt_24,
      lopt_8 => lopt_25,
      lopt_9 => lopt_26
    );
\Using_FPGA.ALL_Bits[27].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_506
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_5,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[27]\(0) => \EX_Op2_reg[0]\(2),
      LO => alu_carry_4,
      \MEM_DataBus_Addr_reg[27]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[27]_0\(0) => \Using_FPGA.Native\(4),
      Q(0) => Q(4),
      lopt => \^lopt_11\,
      lopt_1 => \^lopt_12\,
      lopt_2 => \^lopt_13\,
      lopt_3 => \^lopt_16\
    );
\Using_FPGA.ALL_Bits[28].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_507
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_4,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[28]\(0) => \EX_Op2_reg[0]\(1),
      LO => alu_carry_3,
      \MEM_DataBus_Addr_reg[28]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[28]_0\(0) => \Using_FPGA.Native\(3),
      Q(0) => Q(3),
      lopt => \^lopt_8\,
      lopt_1 => \^lopt_9\,
      lopt_2 => \^lopt_10\,
      lopt_3 => \^lopt_15\
    );
\Using_FPGA.ALL_Bits[29].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_508
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_3,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[29]\(0) => \EX_Op2_reg[0]\(0),
      LO => alu_carry_2,
      \MEM_DataBus_Addr_reg[29]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[29]_0\(0) => \Using_FPGA.Native\(2),
      Q(0) => Q(2),
      lopt => \^lopt_5\,
      lopt_1 => \^lopt_6\,
      lopt_2 => \^lopt_7\,
      lopt_3 => \^lopt_14\
    );
\Using_FPGA.ALL_Bits[2].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_509
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_30,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[2]\(0) => \EX_Op2_reg[0]\(27),
      LO => alu_carry_29,
      \MEM_DataBus_Addr_reg[2]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[2]_0\(0) => \Using_FPGA.Native\(29),
      Q(0) => Q(29),
      lopt => lopt_89,
      lopt_1 => lopt_90,
      lopt_10 => lopt_97,
      lopt_2 => lopt_91,
      lopt_3 => lopt_92,
      lopt_4 => ex_unsigned_op,
      lopt_5 => S,
      lopt_6 => lopt_93,
      lopt_7 => lopt_94,
      lopt_8 => lopt_95,
      lopt_9 => lopt_96
    );
\Using_FPGA.ALL_Bits[30].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_510
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_2,
      EX_Enable_ALU => EX_Enable_ALU,
      LO => alu_carry_1,
      Q(0) => Q(1),
      \Using_FPGA.Native_I2\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \Using_FPGA.Native_I2_0\(0) => \Using_FPGA.Native\(1),
      ex_databus_addr(0) => ex_databus_addr(1),
      lopt => \^lopt_5\,
      lopt_1 => \^lopt_6\,
      lopt_10 => \^lopt_15\,
      lopt_11 => \^lopt_16\,
      lopt_12 => lopt_98,
      lopt_13 => lopt_99,
      lopt_14 => lopt_100,
      lopt_15 => lopt_101,
      lopt_16 => lopt_102,
      lopt_17 => lopt_103,
      lopt_18 => lopt_104,
      lopt_19 => lopt_105,
      lopt_2 => \^lopt_7\,
      lopt_20 => lopt_106,
      lopt_21 => lopt_107,
      lopt_3 => \^lopt_8\,
      lopt_4 => \^lopt_9\,
      lopt_5 => \^lopt_10\,
      lopt_6 => \^lopt_11\,
      lopt_7 => \^lopt_12\,
      lopt_8 => \^lopt_13\,
      lopt_9 => \^lopt_14\
    );
\Using_FPGA.ALL_Bits[31].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_511
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryIn => alu_carry_in,
      EX_CarryOut => alu_carry_1,
      EX_Enable_ALU => EX_Enable_ALU,
      Q(0) => Q(0),
      \Using_FPGA.Native_I2\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \Using_FPGA.Native_I2_0\(0) => \Using_FPGA.Native\(0),
      ex_databus_addr(0) => ex_databus_addr(0),
      lopt => lopt_1,
      lopt_1 => lopt_2,
      lopt_2 => lopt_3,
      lopt_3 => lopt_4
    );
\Using_FPGA.ALL_Bits[3].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_512
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_29,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[3]\(0) => \EX_Op2_reg[0]\(26),
      LO => alu_carry_28,
      \MEM_DataBus_Addr_reg[3]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[3]_0\(0) => \Using_FPGA.Native\(28),
      Q(0) => Q(28),
      lopt => lopt_83,
      lopt_1 => lopt_84,
      lopt_2 => lopt_85,
      lopt_3 => lopt_88
    );
\Using_FPGA.ALL_Bits[4].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_513
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_28,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[4]\(0) => \EX_Op2_reg[0]\(25),
      LO => alu_carry_27,
      \MEM_DataBus_Addr_reg[4]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[4]_0\(0) => \Using_FPGA.Native\(27),
      Q(0) => Q(27),
      lopt => lopt_80,
      lopt_1 => lopt_81,
      lopt_2 => lopt_82,
      lopt_3 => lopt_87
    );
\Using_FPGA.ALL_Bits[5].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_514
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_27,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[5]\(0) => \EX_Op2_reg[0]\(24),
      LO => alu_carry_26,
      \MEM_DataBus_Addr_reg[5]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[5]_0\(0) => \Using_FPGA.Native\(26),
      Q(0) => Q(26),
      lopt => lopt_77,
      lopt_1 => lopt_78,
      lopt_2 => lopt_79,
      lopt_3 => lopt_86
    );
\Using_FPGA.ALL_Bits[6].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_515
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_26,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[6]\(0) => \EX_Op2_reg[0]\(23),
      LO => alu_carry_25,
      \MEM_DataBus_Addr_reg[6]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[6]_0\(0) => \Using_FPGA.Native\(25),
      Q(0) => Q(25),
      lopt => lopt_77,
      lopt_1 => lopt_78,
      lopt_10 => lopt_87,
      lopt_11 => lopt_88,
      lopt_12 => lopt_128,
      lopt_13 => lopt_129,
      lopt_14 => lopt_130,
      lopt_15 => lopt_131,
      lopt_16 => lopt_132,
      lopt_17 => lopt_133,
      lopt_18 => lopt_134,
      lopt_19 => lopt_135,
      lopt_2 => lopt_79,
      lopt_20 => lopt_136,
      lopt_21 => lopt_137,
      lopt_3 => lopt_80,
      lopt_4 => lopt_81,
      lopt_5 => lopt_82,
      lopt_6 => lopt_83,
      lopt_7 => lopt_84,
      lopt_8 => lopt_85,
      lopt_9 => lopt_86
    );
\Using_FPGA.ALL_Bits[7].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_516
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_25,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[7]\(0) => \EX_Op2_reg[0]\(22),
      LO => alu_carry_24,
      \MEM_DataBus_Addr_reg[7]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[7]_0\(0) => \Using_FPGA.Native\(24),
      Q(0) => Q(24),
      lopt => lopt_71,
      lopt_1 => lopt_72,
      lopt_2 => lopt_73,
      lopt_3 => lopt_76
    );
\Using_FPGA.ALL_Bits[8].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_517
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryOut => alu_carry_24,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[8]\(0) => \EX_Op2_reg[0]\(21),
      LO => alu_carry_23,
      \MEM_DataBus_Addr_reg[8]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[8]_0\(0) => \Using_FPGA.Native\(23),
      Q(0) => Q(23),
      lopt => lopt_68,
      lopt_1 => lopt_69,
      lopt_2 => lopt_70,
      lopt_3 => lopt_75
    );
\Using_FPGA.ALL_Bits[9].ALU_Bit_I1\: entity work.design_1_microblaze_0_0_ALU_Bit_518
     port map (
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_CarryIn => alu_carry_22,
      EX_CarryOut => alu_carry_23,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[9]\(0) => \EX_Op2_reg[0]\(20),
      \MEM_DataBus_Addr_reg[9]\(1 downto 0) => \MEM_DataBus_Addr_reg[9]\(1 downto 0),
      \MEM_DataBus_Addr_reg[9]_0\(0) => \Using_FPGA.Native\(22),
      Q(0) => Q(22),
      lopt => lopt_65,
      lopt_1 => lopt_66,
      lopt_2 => lopt_67,
      lopt_3 => lopt_74
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Debug is
  port (
    LOCKSTEP_Master_Out : out STD_LOGIC_VECTOR ( 37 downto 0 );
    \Serial_Dbg_Intf.force_stop_cmd_i_reg_0\ : out STD_LOGIC;
    read_register_MSR_1_reg_0 : out STD_LOGIC;
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0\ : out STD_LOGIC;
    Sleep_Out : out STD_LOGIC;
    dbg_halt_reset_mode_reg_0 : out STD_LOGIC;
    \Performance_Debug_Control.dbg_state_nohalt_reg_0\ : out STD_LOGIC;
    \Performance_Debug_Control.dbg_freeze_nohalt_reg_0\ : out STD_LOGIC;
    exception_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Trig_In : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_Trig_Ack_Out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \Performance_Debug_Control.dbg_stop_if_delay_i_reg_0\ : out STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    ex_MSR_Load_Shift_C : out STD_LOGIC;
    ex_MSR_Load_ALU_C : out STD_LOGIC;
    ex_MSR_Set_SW_BIP : out STD_LOGIC;
    p_231_in : out STD_LOGIC;
    ex_Exception_Taken : out STD_LOGIC;
    ex_exception_no_load_store_mask : out STD_LOGIC;
    \Performance_Debug_Control.dbg_stop_if_delay_i_reg_1\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    Dbg_Reg_En_0_sp_1 : out STD_LOGIC;
    Dbg_TDO : out STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Performance_Debug_Control.wb_dbg_hit_reg[0]_0\ : in STD_LOGIC;
    \Performance_Debug_Control.m0_dbg_hit_reg[0]_0\ : in STD_LOGIC;
    single_Step_N_reg_0 : in STD_LOGIC;
    Dbg_Trig_Ack_In : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Clk : in STD_LOGIC;
    Dbg_Trig_Out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Pause : in STD_LOGIC;
    Sleep : in STD_LOGIC;
    \Performance_Debug_Control.ex_brki_hit_reg_0\ : in STD_LOGIC;
    wb_Halted : in STD_LOGIC;
    Dbg_Update : in STD_LOGIC;
    wb_read_imm_reg_1 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wb_read_imm_reg : in STD_LOGIC;
    Dbg_Stop : in STD_LOGIC;
    Dbg_Capture : in STD_LOGIC;
    dbg_stop_i : in STD_LOGIC;
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1\ : in STD_LOGIC;
    exception_reg_1 : in STD_LOGIC;
    executing_reg_0 : in STD_LOGIC;
    ex_valid : in STD_LOGIC;
    ex_is_load_instr_s : in STD_LOGIC;
    ex_load_shift_carry : in STD_LOGIC;
    \Using_FPGA.Native_i_2__21\ : in STD_LOGIC;
    \Using_LWX_SWX_instr.ex_reservation_i_3\ : in STD_LOGIC;
    \p_4_out__0\ : in STD_LOGIC;
    Reset_Mode : in STD_LOGIC_VECTOR ( 0 to 1 );
    wb_pc_valid : in STD_LOGIC;
    Data_Read_Reg_En : in STD_LOGIC;
    Config_Reg_En : in STD_LOGIC;
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\ : in STD_LOGIC;
    Dbg_Shift : in STD_LOGIC;
    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
    wb_gpr_wr_dbg : in STD_LOGIC;
    Status_Reg_En : in STD_LOGIC;
    wakeup_i : in STD_LOGIC_VECTOR ( 0 to 1 );
    of_pause : in STD_LOGIC;
    mem_Exception_Taken : in STD_LOGIC;
    Scan_Reset_Sel : in STD_LOGIC;
    Sleep_Decode : in STD_LOGIC;
    Scan_Reset : in STD_LOGIC;
    Scan_En : in STD_LOGIC;
    dbg_clean_stop : in STD_LOGIC;
    Dbg_TDI : in STD_LOGIC;
    Address : in STD_LOGIC_VECTOR ( 0 to 31 );
    \data_rd_reg_reg[0]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \Serial_Dbg_Intf.status_reg_reg[22]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Debug : entity is "Debug";
end design_1_microblaze_0_0_Debug;

architecture STRUCTURE of design_1_microblaze_0_0_Debug is
  signal A1 : STD_LOGIC;
  signal A2 : STD_LOGIC;
  signal A3 : STD_LOGIC;
  signal Command_Reg_En : STD_LOGIC;
  signal Control_Reg_En : STD_LOGIC;
  signal Dbg_Reg_En_0_sn_1 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_10_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_16_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_17_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_18_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_19_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_20_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_21_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_22_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_27_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_28_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_29_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_30_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_31_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_32_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_33_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_34_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_35_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_36_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_7_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_8_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_9_n_0 : STD_LOGIC;
  signal \^dbg_trig_ack_out\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^dbg_trig_in\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal Full_32_bit : STD_LOGIC;
  signal Full_32_bit_1 : STD_LOGIC;
  signal Instr_Insert_Reg_En : STD_LOGIC;
  signal Instr_Insert_Reg_En_1 : STD_LOGIC;
  signal \^lockstep_master_out\ : STD_LOGIC_VECTOR ( 37 downto 0 );
  signal New_Dbg_Instr_TCK : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_freeze_nohalt_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_freeze_nohalt_i_3_n_0\ : STD_LOGIC;
  signal \^performance_debug_control.dbg_freeze_nohalt_reg_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_state_nohalt_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_state_nohalt_i_3_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_state_nohalt_i_4_n_0\ : STD_LOGIC;
  signal \^performance_debug_control.dbg_state_nohalt_reg_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_stop_i_reg_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_stop_if_delay_i_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2_n_0\ : STD_LOGIC;
  signal \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.ex_dbg_pc_hit_i_i_4_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.force_stop_i_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.m0_dbg_hit[0]_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0]\ : STD_LOGIC;
  signal \Performance_Debug_Control.normal_stop_i_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.step_continue_hold_i_1_n_0\ : STD_LOGIC;
  signal \Performance_Debug_Control.step_continue_hold_reg_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal Q0_out : STD_LOGIC;
  signal Q11_in : STD_LOGIC;
  signal Q2_in : STD_LOGIC;
  signal Q2_out : STD_LOGIC;
  signal Q3_in : STD_LOGIC;
  signal Q3_out : STD_LOGIC;
  signal Q4_out : STD_LOGIC;
  signal Q6_out : STD_LOGIC;
  signal Q_0 : STD_LOGIC;
  signal \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.command_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.continue_from_brk_TClk_i_1_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.continue_from_brk_reg_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.control_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.control_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.control_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.dbg_wakeup_i_i_2_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.force_stop_TClk_i_1_n_0\ : STD_LOGIC;
  signal \^serial_dbg_intf.force_stop_cmd_i_reg_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.normal_stop_TClk_i_1_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[0]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[1]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[2]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[3]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[4]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[6]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[8]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_count[5]_i_2_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_count[7]_i_2_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[10]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[11]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[12]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[13]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[14]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[15]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[16]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[17]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[18]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[19]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[1]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[20]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[21]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[22]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[23]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[24]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[25]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[26]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[27]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[28]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[29]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[2]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[30]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[31]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[3]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[4]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[5]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[6]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[7]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[8]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.shift_datain_reg_n_0_[9]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.single_Step_TClk_i_1_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[16]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[17]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[18]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[19]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[20]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[22]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[23]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[24]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[25]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[27]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[28]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.status_reg_reg_n_0_[29]\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sync_dbg_wakeup_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sync_pause_n_1\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sync_sample_n_10\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sync_sample_n_12\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.sync_stop_CPU_n_0\ : STD_LOGIC;
  signal \Serial_Dbg_Intf.unchanged_i_1_n_0\ : STD_LOGIC;
  signal \^sleep_out\ : STD_LOGIC;
  signal \TDO_Data_Reg__31\ : STD_LOGIC;
  signal \TDO_Instr_Reg__0\ : STD_LOGIC;
  signal \TDO_Status_Reg__17\ : STD_LOGIC;
  signal \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_0\ : STD_LOGIC;
  signal \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_1\ : STD_LOGIC;
  signal \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_2\ : STD_LOGIC;
  signal capture_1 : STD_LOGIC;
  signal command_reg_clear : STD_LOGIC;
  signal command_reg_clear_i_1_n_0 : STD_LOGIC;
  signal \data_rd_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \data_rd_reg[32]_i_1_n_0\ : STD_LOGIC;
  signal \data_rd_reg[32]_i_2_n_0\ : STD_LOGIC;
  signal \data_rd_reg[32]_i_3_n_0\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[0]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[10]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[11]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[12]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[13]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[14]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[15]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[16]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[17]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[18]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[19]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[1]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[20]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[21]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[22]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[23]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[24]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[25]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[26]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[27]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[28]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[29]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[2]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[30]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[31]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[32]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[3]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[4]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[5]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[6]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[7]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[8]\ : STD_LOGIC;
  signal \data_rd_reg_reg_n_0_[9]\ : STD_LOGIC;
  signal data_read_reg : STD_LOGIC_VECTOR ( 0 to 32 );
  signal dbg_brki_hit : STD_LOGIC;
  signal dbg_brki_hit_synced : STD_LOGIC;
  signal dbg_continue_i_i_2_n_0 : STD_LOGIC;
  signal dbg_freeze_nohalt0_in : STD_LOGIC;
  signal dbg_halt_reset_mode_i_1_n_0 : STD_LOGIC;
  signal \^dbg_halt_reset_mode_reg_0\ : STD_LOGIC;
  signal dbg_hit : STD_LOGIC_VECTOR ( 0 to 0 );
  signal dbg_stop_1 : STD_LOGIC;
  signal delay_slot_instr : STD_LOGIC;
  signal \^ex_exception_taken\ : STD_LOGIC;
  signal ex_brki_hit : STD_LOGIC;
  signal ex_pc_brk : STD_LOGIC;
  signal ex_piperun_for_ce : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of ex_piperun_for_ce : signal is std.standard.true;
  signal ex_step_continue_hold : STD_LOGIC;
  signal exception_i_1_n_0 : STD_LOGIC;
  signal \^exception_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal executing_i_1_n_0 : STD_LOGIC;
  signal force_stop_cmd_1 : STD_LOGIC;
  signal force_stop_i : STD_LOGIC;
  signal force_stop_overrun : STD_LOGIC;
  signal instr_rd_reg : STD_LOGIC_VECTOR ( 0 to 0 );
  signal instr_read_reg : STD_LOGIC_VECTOR ( 0 to 1 );
  signal m0_brki_hit : STD_LOGIC;
  signal m3_piperun_for_ce : STD_LOGIC;
  attribute DIRECT_ENABLE of m3_piperun_for_ce : signal is std.standard.true;
  signal mb_halted_1 : STD_LOGIC;
  signal normal_stop_cmd_1 : STD_LOGIC;
  signal normal_stop_i : STD_LOGIC;
  signal of_piperun_for_ce : STD_LOGIC;
  attribute DIRECT_ENABLE of of_piperun_for_ce : signal is std.standard.true;
  signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 1 );
  signal p_0_in71_in : STD_LOGIC;
  signal p_0_in_1 : STD_LOGIC;
  signal p_11_out : STD_LOGIC;
  signal p_1_out : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_1_out__0\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_1_out__1\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_1_out__2\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_1_out__3\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_1_out__4\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_1_out__5\ : STD_LOGIC_VECTOR ( 1 to 1 );
  signal \p_37_out__0\ : STD_LOGIC;
  signal p_56_out : STD_LOGIC;
  signal p_76_out : STD_LOGIC;
  signal p_83_out : STD_LOGIC;
  signal p_86_out : STD_LOGIC;
  signal p_88_out : STD_LOGIC;
  signal p_91_out : STD_LOGIC;
  signal p_94_out : STD_LOGIC;
  signal p_95_in : STD_LOGIC;
  signal p_97_out : STD_LOGIC;
  signal pause_synced : STD_LOGIC;
  signal read_register_MSR : STD_LOGIC;
  signal \^read_register_msr_1_reg_0\ : STD_LOGIC;
  signal read_register_PC : STD_LOGIC;
  signal read_register_PC_1_reg_n_0 : STD_LOGIC;
  signal reset_bool_for_rst : STD_LOGIC;
  attribute DIRECT_RESET : boolean;
  attribute DIRECT_RESET of reset_bool_for_rst : signal is std.standard.true;
  signal running_clock : STD_LOGIC;
  signal running_clock_i_1_n_0 : STD_LOGIC;
  signal running_clock_synced : STD_LOGIC;
  signal sample_synced : STD_LOGIC_VECTOR ( 0 to 9 );
  signal saved_reset_mode_dbg_halt : STD_LOGIC;
  signal saved_reset_mode_dbg_halt_i_1_n_0 : STD_LOGIC;
  signal saved_reset_mode_sleep : STD_LOGIC;
  signal saved_reset_mode_sleep_i_1_n_0 : STD_LOGIC;
  signal sel0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \sel0__0\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal single_Step_N : STD_LOGIC;
  signal single_Step_N_i_1_n_0 : STD_LOGIC;
  signal single_step_count : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \single_step_count[0]_i_1_n_0\ : STD_LOGIC;
  signal \single_step_count[0]_i_2_n_0\ : STD_LOGIC;
  signal \single_step_count[1]_i_1_n_0\ : STD_LOGIC;
  signal sleep_reset_mode : STD_LOGIC;
  signal sleep_reset_mode_i_1_n_0 : STD_LOGIC;
  signal sleep_synced : STD_LOGIC;
  signal start_dbg_exec_reg_n_0 : STD_LOGIC;
  signal start_single_cmd : STD_LOGIC;
  signal start_single_step_i_1_n_0 : STD_LOGIC;
  signal start_single_step_reg_n_0 : STD_LOGIC;
  signal \step_continue__0\ : STD_LOGIC;
  signal sync : STD_LOGIC;
  signal sync_trig_ack_in_0_n_1 : STD_LOGIC;
  signal sync_trig_out_0_n_1 : STD_LOGIC;
  signal sync_trig_out_0_n_2 : STD_LOGIC;
  signal tdo_config_word1_0 : STD_LOGIC;
  signal trig_ack_in_0_synced : STD_LOGIC;
  signal trig_ack_in_0_synced_1 : STD_LOGIC;
  signal trig_out_0_synced : STD_LOGIC;
  signal trig_out_0_synced_1 : STD_LOGIC;
  signal unchanged : STD_LOGIC;
  signal wb_brki_hit : STD_LOGIC;
  signal wb_dbg_hit : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of Dbg_TDO_INST_0_i_10 : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of Dbg_TDO_INST_0_i_15 : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of Dbg_TDO_INST_0_i_18 : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of Dbg_TDO_INST_0_i_29 : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of Dbg_TDO_INST_0_i_31 : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \Performance_Debug_Control.force_stop_overrun_i_1\ : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \Performance_Debug_Control.step_continue_hold_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of Read_Strobe_INST_0 : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.New_Dbg_Instr_TCK_i_1\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.New_Dbg_Instr_TCK_i_2\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.shift_count[0]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.shift_count[1]_i_1\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.shift_count[2]_i_1\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.shift_count[3]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.shift_count[5]_i_2\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.shift_count[6]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \Serial_Dbg_Intf.shift_count[7]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__8\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_4\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_5\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \Using_LWX_SWX_instr.ex_reservation_i_4\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \data_rd_reg[32]_i_2\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \data_rd_reg[32]_i_3\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of dbg_continue_i_i_2 : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of dbg_halt_reset_mode_i_2 : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of mem_exception_from_ex_i_1 : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of saved_reset_mode_sleep_i_1 : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of sleep_reset_mode_i_2 : label is "soft_lutpair78";
begin
  Dbg_Reg_En_0_sp_1 <= Dbg_Reg_En_0_sn_1;
  Dbg_Trig_Ack_Out(1 downto 0) <= \^dbg_trig_ack_out\(1 downto 0);
  Dbg_Trig_In(1 downto 0) <= \^dbg_trig_in\(1 downto 0);
  LOCKSTEP_Master_Out(37 downto 0) <= \^lockstep_master_out\(37 downto 0);
  \Performance_Debug_Control.dbg_freeze_nohalt_reg_0\ <= \^performance_debug_control.dbg_freeze_nohalt_reg_0\;
  \Performance_Debug_Control.dbg_state_nohalt_reg_0\ <= \^performance_debug_control.dbg_state_nohalt_reg_0\;
  \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0\ <= \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\;
  Q(0) <= \^q\(0);
  \Serial_Dbg_Intf.force_stop_cmd_i_reg_0\ <= \^serial_dbg_intf.force_stop_cmd_i_reg_0\;
  Sleep_Out <= \^sleep_out\;
  dbg_halt_reset_mode_reg_0 <= \^dbg_halt_reset_mode_reg_0\;
  ex_Exception_Taken <= \^ex_exception_taken\;
  ex_piperun_for_ce <= \Performance_Debug_Control.m0_dbg_hit_reg[0]_0\;
  exception_reg_0(0) <= \^exception_reg_0\(0);
  m3_piperun_for_ce <= \Performance_Debug_Control.wb_dbg_hit_reg[0]_0\;
  of_piperun_for_ce <= single_Step_N_reg_0;
  read_register_MSR_1_reg_0 <= \^read_register_msr_1_reg_0\;
  reset_bool_for_rst <= sync_reset;
Dbg_TDO_INST_0_i_10: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20000002"
    )
        port map (
      I0 => \Serial_Dbg_Intf.status_reg_reg_n_0_[0]\,
      I1 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I2 => A3,
      I3 => A1,
      I4 => A2,
      O => Dbg_TDO_INST_0_i_10_n_0
    );
Dbg_TDO_INST_0_i_15: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => instr_read_reg(1),
      I1 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I2 => instr_read_reg(0),
      O => \TDO_Instr_Reg__0\
    );
Dbg_TDO_INST_0_i_16: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => Dbg_TDO_INST_0_i_27_n_0,
      I1 => Dbg_TDO_INST_0_i_28_n_0,
      I2 => Dbg_TDO_INST_0_i_29_n_0,
      I3 => Dbg_TDO_INST_0_i_30_n_0,
      I4 => Dbg_TDO_INST_0_i_31_n_0,
      I5 => Dbg_TDO_INST_0_i_32_n_0,
      O => Dbg_TDO_INST_0_i_16_n_0
    );
Dbg_TDO_INST_0_i_17: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => Dbg_TDO_INST_0_i_33_n_0,
      I1 => Dbg_TDO_INST_0_i_34_n_0,
      I2 => Dbg_TDO_INST_0_i_29_n_0,
      I3 => Dbg_TDO_INST_0_i_35_n_0,
      I4 => Dbg_TDO_INST_0_i_31_n_0,
      I5 => Dbg_TDO_INST_0_i_36_n_0,
      O => Dbg_TDO_INST_0_i_17_n_0
    );
Dbg_TDO_INST_0_i_18: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => A2,
      I1 => A1,
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A3,
      O => Dbg_TDO_INST_0_i_18_n_0
    );
Dbg_TDO_INST_0_i_19: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => A1,
      I1 => A2,
      O => Dbg_TDO_INST_0_i_19_n_0
    );
Dbg_TDO_INST_0_i_20: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AFA0CFCFAFA0C0C0"
    )
        port map (
      I0 => \Serial_Dbg_Intf.status_reg_reg_n_0_[23]\,
      I1 => \Serial_Dbg_Intf.status_reg_reg_n_0_[22]\,
      I2 => A1,
      I3 => \Serial_Dbg_Intf.status_reg_reg_n_0_[25]\,
      I4 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I5 => \Serial_Dbg_Intf.status_reg_reg_n_0_[24]\,
      O => Dbg_TDO_INST_0_i_20_n_0
    );
Dbg_TDO_INST_0_i_21: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B833B800"
    )
        port map (
      I0 => \Serial_Dbg_Intf.status_reg_reg_n_0_[27]\,
      I1 => A1,
      I2 => \Serial_Dbg_Intf.status_reg_reg_n_0_[29]\,
      I3 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I4 => \Serial_Dbg_Intf.status_reg_reg_n_0_[28]\,
      O => Dbg_TDO_INST_0_i_21_n_0
    );
Dbg_TDO_INST_0_i_22: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A0A0CFC0"
    )
        port map (
      I0 => \Serial_Dbg_Intf.status_reg_reg_n_0_[19]\,
      I1 => \Serial_Dbg_Intf.status_reg_reg_n_0_[18]\,
      I2 => A1,
      I3 => \Serial_Dbg_Intf.status_reg_reg_n_0_[20]\,
      I4 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      O => Dbg_TDO_INST_0_i_22_n_0
    );
Dbg_TDO_INST_0_i_27: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(1),
      I1 => data_read_reg(2),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(3),
      I5 => data_read_reg(4),
      O => Dbg_TDO_INST_0_i_27_n_0
    );
Dbg_TDO_INST_0_i_28: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(5),
      I1 => data_read_reg(6),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(7),
      I5 => data_read_reg(8),
      O => Dbg_TDO_INST_0_i_28_n_0
    );
Dbg_TDO_INST_0_i_29: unisim.vcomponents.LUT4
    generic map(
      INIT => X"01FE"
    )
        port map (
      I0 => A2,
      I1 => A1,
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A3,
      O => Dbg_TDO_INST_0_i_29_n_0
    );
Dbg_TDO_INST_0_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ACFAFFCFAC0A00C0"
    )
        port map (
      I0 => Dbg_TDO_INST_0_i_7_n_0,
      I1 => Dbg_TDO_INST_0_i_8_n_0,
      I2 => A3,
      I3 => Dbg_TDO_INST_0_i_9_n_0,
      I4 => sel0(0),
      I5 => Dbg_TDO_INST_0_i_10_n_0,
      O => \TDO_Status_Reg__17\
    );
Dbg_TDO_INST_0_i_30: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(9),
      I1 => data_read_reg(10),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(11),
      I5 => data_read_reg(12),
      O => Dbg_TDO_INST_0_i_30_n_0
    );
Dbg_TDO_INST_0_i_31: unisim.vcomponents.LUT3
    generic map(
      INIT => X"1E"
    )
        port map (
      I0 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I1 => A1,
      I2 => A2,
      O => Dbg_TDO_INST_0_i_31_n_0
    );
Dbg_TDO_INST_0_i_32: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(13),
      I1 => data_read_reg(14),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(15),
      I5 => data_read_reg(16),
      O => Dbg_TDO_INST_0_i_32_n_0
    );
Dbg_TDO_INST_0_i_33: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(17),
      I1 => data_read_reg(18),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(19),
      I5 => data_read_reg(20),
      O => Dbg_TDO_INST_0_i_33_n_0
    );
Dbg_TDO_INST_0_i_34: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(21),
      I1 => data_read_reg(22),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(23),
      I5 => data_read_reg(24),
      O => Dbg_TDO_INST_0_i_34_n_0
    );
Dbg_TDO_INST_0_i_35: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(25),
      I1 => data_read_reg(26),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(27),
      I5 => data_read_reg(28),
      O => Dbg_TDO_INST_0_i_35_n_0
    );
Dbg_TDO_INST_0_i_36: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCAF0CAFFCA00CA0"
    )
        port map (
      I0 => data_read_reg(29),
      I1 => data_read_reg(30),
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => data_read_reg(31),
      I5 => data_read_reg(32),
      O => Dbg_TDO_INST_0_i_36_n_0
    );
Dbg_TDO_INST_0_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FCFFAFCA0C00A0CA"
    )
        port map (
      I0 => Dbg_TDO_INST_0_i_16_n_0,
      I1 => Dbg_TDO_INST_0_i_17_n_0,
      I2 => sel0(0),
      I3 => Dbg_TDO_INST_0_i_18_n_0,
      I4 => \sel0__0\(1),
      I5 => data_read_reg(0),
      O => \TDO_Data_Reg__31\
    );
Dbg_TDO_INST_0_i_7: unisim.vcomponents.MUXF7
     port map (
      I0 => Dbg_TDO_INST_0_i_20_n_0,
      I1 => Dbg_TDO_INST_0_i_21_n_0,
      O => Dbg_TDO_INST_0_i_7_n_0,
      S => Dbg_TDO_INST_0_i_19_n_0
    );
Dbg_TDO_INST_0_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"2B2B2B2828282B28"
    )
        port map (
      I0 => Dbg_TDO_INST_0_i_22_n_0,
      I1 => A1,
      I2 => A2,
      I3 => \Serial_Dbg_Intf.status_reg_reg_n_0_[16]\,
      I4 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I5 => \Serial_Dbg_Intf.status_reg_reg_n_0_[17]\,
      O => Dbg_TDO_INST_0_i_8_n_0
    );
Dbg_TDO_INST_0_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => A1,
      I1 => A2,
      O => Dbg_TDO_INST_0_i_9_n_0
    );
Full_32_bit_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => wb_Halted,
      D => wb_read_imm_reg_1,
      Q => Full_32_bit_1,
      R => reset_bool_for_rst
    );
Full_32_bit_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => wb_Halted,
      D => wb_read_imm_reg,
      Q => Full_32_bit,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.dbg_brki_hit_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => wb_Halted,
      D => wb_brki_hit,
      Q => dbg_brki_hit,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.dbg_freeze_nohalt_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAABAAAAAAA8"
    )
        port map (
      I0 => dbg_freeze_nohalt0_in,
      I1 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      I2 => \p_4_out__0\,
      I3 => \Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0\,
      I4 => \Performance_Debug_Control.dbg_freeze_nohalt_i_3_n_0\,
      I5 => \^performance_debug_control.dbg_freeze_nohalt_reg_0\,
      O => \Performance_Debug_Control.dbg_freeze_nohalt_i_1_n_0\
    );
\Performance_Debug_Control.dbg_freeze_nohalt_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFD00"
    )
        port map (
      I0 => \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\,
      I1 => start_single_step_reg_n_0,
      I2 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      I3 => \^performance_debug_control.dbg_state_nohalt_reg_0\,
      I4 => reset_bool_for_rst,
      O => \Performance_Debug_Control.dbg_freeze_nohalt_i_3_n_0\
    );
\Performance_Debug_Control.dbg_freeze_nohalt_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Performance_Debug_Control.dbg_freeze_nohalt_i_1_n_0\,
      Q => \^performance_debug_control.dbg_freeze_nohalt_reg_0\,
      R => '0'
    );
\Performance_Debug_Control.dbg_hit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => wb_Halted,
      D => wb_dbg_hit,
      Q => dbg_hit(0),
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.dbg_state_nohalt_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A888FFFFA8880000"
    )
        port map (
      I0 => dbg_freeze_nohalt0_in,
      I1 => \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\,
      I2 => saved_reset_mode_dbg_halt,
      I3 => \^dbg_halt_reset_mode_reg_0\,
      I4 => \Performance_Debug_Control.dbg_state_nohalt_i_3_n_0\,
      I5 => \^performance_debug_control.dbg_state_nohalt_reg_0\,
      O => \Performance_Debug_Control.dbg_state_nohalt_i_1_n_0\
    );
\Performance_Debug_Control.dbg_state_nohalt_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000054FE5454"
    )
        port map (
      I0 => reset_bool_for_rst,
      I1 => \^dbg_halt_reset_mode_reg_0\,
      I2 => wb_Halted,
      I3 => Reset_Mode(1),
      I4 => Reset_Mode(0),
      I5 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      O => dbg_freeze_nohalt0_in
    );
\Performance_Debug_Control.dbg_state_nohalt_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFEFFFEFE"
    )
        port map (
      I0 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      I1 => reset_bool_for_rst,
      I2 => \p_4_out__0\,
      I3 => \Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0\,
      I4 => \p_37_out__0\,
      I5 => \Performance_Debug_Control.dbg_state_nohalt_i_4_n_0\,
      O => \Performance_Debug_Control.dbg_state_nohalt_i_3_n_0\
    );
\Performance_Debug_Control.dbg_state_nohalt_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"07"
    )
        port map (
      I0 => \^dbg_halt_reset_mode_reg_0\,
      I1 => saved_reset_mode_dbg_halt,
      I2 => \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\,
      O => \Performance_Debug_Control.dbg_state_nohalt_i_4_n_0\
    );
\Performance_Debug_Control.dbg_state_nohalt_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Performance_Debug_Control.dbg_state_nohalt_i_1_n_0\,
      Q => \^performance_debug_control.dbg_state_nohalt_reg_0\,
      R => '0'
    );
\Performance_Debug_Control.dbg_stop_1_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Dbg_Stop,
      Q => dbg_stop_1,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.dbg_stop_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sync_trig_out_0_n_2,
      Q => \Performance_Debug_Control.dbg_stop_i_reg_n_0\,
      R => dbg_stop_i
    );
\Performance_Debug_Control.dbg_stop_if_delay_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000000000FE"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg_0\,
      I1 => wb_Halted,
      I2 => \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\,
      I3 => reset_bool_for_rst,
      I4 => saved_reset_mode_sleep,
      I5 => \^dbg_halt_reset_mode_reg_0\,
      O => \Performance_Debug_Control.dbg_stop_if_delay_i_i_1_n_0\
    );
\Performance_Debug_Control.dbg_stop_if_delay_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Performance_Debug_Control.dbg_stop_if_delay_i_i_1_n_0\,
      Q => \^lockstep_master_out\(32),
      R => '0'
    );
\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000FE02"
    )
        port map (
      I0 => \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\,
      I1 => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2_n_0\,
      I2 => reset_bool_for_rst,
      I3 => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1\,
      I4 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      O => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1_n_0\
    );
\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEFEFEFEEEFEEEE"
    )
        port map (
      I0 => \^dbg_halt_reset_mode_reg_0\,
      I1 => wb_Halted,
      I2 => \Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0\,
      I3 => \^sleep_out\,
      I4 => saved_reset_mode_sleep,
      I5 => \p_37_out__0\,
      O => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2_n_0\
    );
\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAA8AAAA"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg_0\,
      I1 => reset_bool_for_rst,
      I2 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      I3 => start_single_step_reg_n_0,
      I4 => \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\,
      O => \p_37_out__0\
    );
\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1_n_0\,
      Q => \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\,
      R => '0'
    );
\Performance_Debug_Control.ex_brki_hit_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_piperun_for_ce,
      D => \Performance_Debug_Control.ex_brki_hit_reg_0\,
      Q => ex_brki_hit,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.ex_dbg_hit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_piperun_for_ce,
      D => \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_0\,
      Q => ex_pc_brk,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.ex_dbg_pc_hit_i_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8F"
    )
        port map (
      I0 => normal_stop_i,
      I1 => dbg_clean_stop,
      I2 => single_Step_N,
      O => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_4_n_0\
    );
\Performance_Debug_Control.ex_dbg_pc_hit_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_2\,
      Q => \^lockstep_master_out\(35),
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_1\,
      Q => \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_n_0\,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.ex_step_continue_hold_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_piperun_for_ce,
      D => \Performance_Debug_Control.step_continue_hold_reg_n_0\,
      Q => ex_step_continue_hold,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.force_stop_cmd_1_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^serial_dbg_intf.force_stop_cmd_i_reg_0\,
      Q => force_stop_cmd_1,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.force_stop_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0010"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg_0\,
      I1 => wb_Halted,
      I2 => force_stop_cmd_1,
      I3 => \^serial_dbg_intf.force_stop_cmd_i_reg_0\,
      I4 => force_stop_i,
      O => \Performance_Debug_Control.force_stop_i_i_1_n_0\
    );
\Performance_Debug_Control.force_stop_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Performance_Debug_Control.force_stop_i_i_1_n_0\,
      Q => force_stop_i,
      R => dbg_stop_i
    );
\Performance_Debug_Control.force_stop_overrun_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => force_stop_cmd_1,
      I1 => \^serial_dbg_intf.force_stop_cmd_i_reg_0\,
      O => p_56_out
    );
\Performance_Debug_Control.force_stop_overrun_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => p_56_out,
      Q => force_stop_overrun,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.m0_brki_hit_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => ex_piperun_for_ce,
      D => ex_brki_hit,
      Q => m0_brki_hit,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.m0_dbg_hit[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => ex_pc_brk,
      I1 => ex_step_continue_hold,
      I2 => \Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0]\,
      O => \Performance_Debug_Control.m0_dbg_hit[0]_i_1_n_0\
    );
\Performance_Debug_Control.m0_dbg_hit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => ex_piperun_for_ce,
      D => \Performance_Debug_Control.m0_dbg_hit[0]_i_1_n_0\,
      Q => \Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0]\,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.normal_stop_cmd_1_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0\,
      Q => normal_stop_cmd_1,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.normal_stop_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF0100"
    )
        port map (
      I0 => \Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0\,
      I1 => wb_Halted,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg_0\,
      I3 => normal_stop_cmd_1,
      I4 => normal_stop_i,
      O => \Performance_Debug_Control.normal_stop_i_i_1_n_0\
    );
\Performance_Debug_Control.normal_stop_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Performance_Debug_Control.normal_stop_i_i_1_n_0\,
      Q => normal_stop_i,
      R => dbg_stop_i
    );
\Performance_Debug_Control.step_continue_hold_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F0E"
    )
        port map (
      I0 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      I1 => start_single_step_reg_n_0,
      I2 => of_piperun_for_ce,
      I3 => \Performance_Debug_Control.step_continue_hold_reg_n_0\,
      O => \Performance_Debug_Control.step_continue_hold_i_1_n_0\
    );
\Performance_Debug_Control.step_continue_hold_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Performance_Debug_Control.step_continue_hold_i_1_n_0\,
      Q => \Performance_Debug_Control.step_continue_hold_reg_n_0\,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.trig_ack_out_0_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sync_trig_out_0_n_1,
      Q => \^dbg_trig_ack_out\(1),
      R => '0'
    );
\Performance_Debug_Control.trig_out_0_synced_1_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => trig_out_0_synced,
      Q => trig_out_0_synced_1,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.wb_brki_hit_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => m3_piperun_for_ce,
      D => m0_brki_hit,
      Q => wb_brki_hit,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.wb_dbg_hit_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => m3_piperun_for_ce,
      D => \Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0]\,
      Q => wb_dbg_hit,
      R => reset_bool_for_rst
    );
Read_Strobe_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D000"
    )
        port map (
      I0 => \^lockstep_master_out\(35),
      I1 => \^lockstep_master_out\(32),
      I2 => ex_valid,
      I3 => ex_is_load_instr_s,
      O => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\(0)
    );
\Serial_Dbg_Intf.Instr_Insert_Reg_En_1_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => Dbg_Reg_En_0_sn_1,
      I1 => Dbg_Reg_En(6),
      I2 => Dbg_Reg_En(5),
      I3 => Dbg_Reg_En(4),
      I4 => Dbg_Reg_En(7),
      O => Instr_Insert_Reg_En
    );
\Serial_Dbg_Intf.Instr_Insert_Reg_En_1_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => Instr_Insert_Reg_En,
      Q => Instr_Insert_Reg_En_1
    );
\Serial_Dbg_Intf.New_Dbg_Instr2_TCK_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => New_Dbg_Instr_TCK,
      Q => \p_1_out__5\(1)
    );
\Serial_Dbg_Intf.New_Dbg_Instr_TCK_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0008"
    )
        port map (
      I0 => p_95_in,
      I1 => Instr_Insert_Reg_En,
      I2 => instr_read_reg(1),
      I3 => instr_read_reg(0),
      O => p_97_out
    );
\Serial_Dbg_Intf.New_Dbg_Instr_TCK_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40000000"
    )
        port map (
      I0 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I1 => A1,
      I2 => sel0(0),
      I3 => A3,
      I4 => A2,
      O => p_95_in
    );
\Serial_Dbg_Intf.New_Dbg_Instr_TCK_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_97_out,
      Q => New_Dbg_Instr_TCK
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => Scan_Reset,
      I2 => Scan_En,
      O => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[1]\,
      Q => \^lockstep_master_out\(31)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[11]\,
      Q => \^lockstep_master_out\(21)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[12]\,
      Q => \^lockstep_master_out\(20)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[13]\,
      Q => \^lockstep_master_out\(19)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[14]\,
      Q => \^lockstep_master_out\(18)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[15]\,
      Q => \^lockstep_master_out\(17)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[16]\,
      Q => \^lockstep_master_out\(16)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[17]\,
      Q => \^lockstep_master_out\(15)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[18]\,
      Q => \^lockstep_master_out\(14)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[19]\,
      Q => \^lockstep_master_out\(13)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[20]\,
      Q => \^lockstep_master_out\(12)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[2]\,
      Q => \^lockstep_master_out\(30)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[21]\,
      Q => \^lockstep_master_out\(11)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[22]\,
      Q => \^lockstep_master_out\(10)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[23]\,
      Q => \^lockstep_master_out\(9)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[24]\,
      Q => \^lockstep_master_out\(8)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[25]\,
      Q => \^lockstep_master_out\(7)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[26]\,
      Q => \^lockstep_master_out\(6)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[27]\,
      Q => \^lockstep_master_out\(5)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[28]\,
      Q => \^lockstep_master_out\(4)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[29]\,
      Q => \^lockstep_master_out\(3)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[30]\,
      Q => \^lockstep_master_out\(2)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[3]\,
      Q => \^lockstep_master_out\(29)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[30]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[31]\,
      Q => \^lockstep_master_out\(1)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[31]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => Dbg_TDI,
      Q => \^lockstep_master_out\(0)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[4]\,
      Q => \^lockstep_master_out\(28)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[5]\,
      Q => \^lockstep_master_out\(27)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[6]\,
      Q => \^lockstep_master_out\(26)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[7]\,
      Q => \^lockstep_master_out\(25)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[8]\,
      Q => \^lockstep_master_out\(24)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[9]\,
      Q => \^lockstep_master_out\(23)
    );
\Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => New_Dbg_Instr_TCK,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[10]\,
      Q => \^lockstep_master_out\(22)
    );
\Serial_Dbg_Intf.SRL16E_1\: entity work.design_1_microblaze_0_0_MB_SRL16E
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q_0 => Q_0
    );
\Serial_Dbg_Intf.SRL16E_2\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized1\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q11_in => Q11_in
    );
\Serial_Dbg_Intf.SRL16E_3\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized7\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q2_in => Q2_in
    );
\Serial_Dbg_Intf.SRL16E_4\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized9\
     port map (
      Config_Reg_En => Config_Reg_En,
      Data_Read_Reg_En => Data_Read_Reg_En,
      Dbg_Clk => Dbg_Clk,
      Dbg_TDO => Dbg_TDO,
      Dbg_TDO_INST_0_i_2_0 => \Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I_n_0\,
      Dbg_TDO_INST_0_i_5_0 => \Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector_n_0\,
      Instr_Insert_Reg_En => Instr_Insert_Reg_En,
      Q(7 downto 5) => \sel0__0\(3 downto 1),
      Q(4) => sel0(0),
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q0_out => Q0_out,
      Q2_in => Q2_in,
      Q3_in => Q3_in,
      Status_Reg_En => Status_Reg_En,
      \TDO_Data_Reg__31\ => \TDO_Data_Reg__31\,
      \TDO_Instr_Reg__0\ => \TDO_Instr_Reg__0\,
      \TDO_Status_Reg__17\ => \TDO_Status_Reg__17\,
      tdo_config_word1_0 => tdo_config_word1_0
    );
\Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized1_17\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      \Serial_Dbg_Intf.shift_count_reg[0]\ => \Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector_n_0\
    );
\Serial_Dbg_Intf.The_Base_Vector[2].SRL16E_Base_Vector\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized1_18\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      tdo_config_word1_0 => tdo_config_word1_0
    );
\Serial_Dbg_Intf.The_Cache_Addresses[1].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized3\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q6_out => Q6_out
    );
\Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized5\
     port map (
      Dbg_Clk => Dbg_Clk,
      Dbg_TDO_INST_0_i_5 => \Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I_n_0\,
      Q(6 downto 5) => \sel0__0\(2 downto 1),
      Q(4) => sel0(0),
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q11_in => Q11_in,
      Q6_out => Q6_out,
      Q_0 => Q_0,
      \Serial_Dbg_Intf.shift_count_reg[6]\ => \Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I_n_0\
    );
\Serial_Dbg_Intf.The_Cache_Addresses[3].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized1_19\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q4_out => Q4_out
    );
\Serial_Dbg_Intf.The_Cache_Addresses[4].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized1_20\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q3_out => Q3_out
    );
\Serial_Dbg_Intf.The_Cache_Addresses[5].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized3_21\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q2_out => Q2_out
    );
\Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized5_22\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(5) => \sel0__0\(1),
      Q(4) => sel0(0),
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q2_out => Q2_out,
      Q3_out => Q3_out,
      Q4_out => Q4_out,
      \Serial_Dbg_Intf.shift_count_reg[5]\ => \Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I_n_0\
    );
\Serial_Dbg_Intf.The_Cache_Addresses[7].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized1_23\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q0_out => Q0_out
    );
\Serial_Dbg_Intf.The_Cache_Addresses[8].SRL16E_Cache_I\: entity work.\design_1_microblaze_0_0_MB_SRL16E__parameterized1_24\
     port map (
      Dbg_Clk => Dbg_Clk,
      Q(3) => A3,
      Q(2) => A2,
      Q(1) => A1,
      Q(0) => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      Q3_in => Q3_in
    );
\Serial_Dbg_Intf.capture_1_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => Dbg_Capture,
      Q => capture_1
    );
\Serial_Dbg_Intf.command_reg[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => Dbg_Reg_En_0_sn_1,
      I1 => Dbg_Reg_En(7),
      I2 => Dbg_Reg_En(6),
      I3 => Dbg_Reg_En(4),
      I4 => Dbg_Reg_En(5),
      O => Command_Reg_En
    );
\Serial_Dbg_Intf.command_reg[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E4"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => command_reg_clear,
      I2 => Scan_Reset,
      I3 => Scan_En,
      O => \Serial_Dbg_Intf.command_reg[0]_i_2_n_0\
    );
\Serial_Dbg_Intf.command_reg_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Command_Reg_En,
      CLR => \Serial_Dbg_Intf.command_reg[0]_i_2_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[30]\,
      Q => \p_1_out__2\(1)
    );
\Serial_Dbg_Intf.command_reg_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Command_Reg_En,
      CLR => \Serial_Dbg_Intf.command_reg[0]_i_2_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[31]\,
      Q => \p_1_out__3\(1)
    );
\Serial_Dbg_Intf.continue_from_brk_TClk_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E4"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      I2 => Scan_Reset,
      I3 => Scan_En,
      O => \Serial_Dbg_Intf.continue_from_brk_TClk_i_1_n_0\
    );
\Serial_Dbg_Intf.continue_from_brk_TClk_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.continue_from_brk_TClk_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[24]\,
      Q => \p_1_out__4\(1)
    );
\Serial_Dbg_Intf.continue_from_brk_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => p_11_out,
      Q => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.control_reg_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[22]\,
      Q => \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\
    );
\Serial_Dbg_Intf.control_reg_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[25]\,
      Q => \Serial_Dbg_Intf.control_reg_reg_n_0_[3]\
    );
\Serial_Dbg_Intf.control_reg_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[26]\,
      Q => \Serial_Dbg_Intf.control_reg_reg_n_0_[4]\
    );
\Serial_Dbg_Intf.control_reg_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[27]\,
      Q => \Serial_Dbg_Intf.control_reg_reg_n_0_[5]\
    );
\Serial_Dbg_Intf.control_reg_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[30]\,
      Q => \^q\(0)
    );
\Serial_Dbg_Intf.data_read_reg_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[0]\,
      Q => data_read_reg(0)
    );
\Serial_Dbg_Intf.data_read_reg_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[10]\,
      Q => data_read_reg(10)
    );
\Serial_Dbg_Intf.data_read_reg_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[11]\,
      Q => data_read_reg(11)
    );
\Serial_Dbg_Intf.data_read_reg_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[12]\,
      Q => data_read_reg(12)
    );
\Serial_Dbg_Intf.data_read_reg_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[13]\,
      Q => data_read_reg(13)
    );
\Serial_Dbg_Intf.data_read_reg_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[14]\,
      Q => data_read_reg(14)
    );
\Serial_Dbg_Intf.data_read_reg_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[15]\,
      Q => data_read_reg(15)
    );
\Serial_Dbg_Intf.data_read_reg_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[16]\,
      Q => data_read_reg(16)
    );
\Serial_Dbg_Intf.data_read_reg_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[17]\,
      Q => data_read_reg(17)
    );
\Serial_Dbg_Intf.data_read_reg_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[18]\,
      Q => data_read_reg(18)
    );
\Serial_Dbg_Intf.data_read_reg_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[19]\,
      Q => data_read_reg(19)
    );
\Serial_Dbg_Intf.data_read_reg_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[1]\,
      Q => data_read_reg(1)
    );
\Serial_Dbg_Intf.data_read_reg_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[20]\,
      Q => data_read_reg(20)
    );
\Serial_Dbg_Intf.data_read_reg_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[21]\,
      Q => data_read_reg(21)
    );
\Serial_Dbg_Intf.data_read_reg_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[22]\,
      Q => data_read_reg(22)
    );
\Serial_Dbg_Intf.data_read_reg_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[23]\,
      Q => data_read_reg(23)
    );
\Serial_Dbg_Intf.data_read_reg_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[24]\,
      Q => data_read_reg(24)
    );
\Serial_Dbg_Intf.data_read_reg_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[25]\,
      Q => data_read_reg(25)
    );
\Serial_Dbg_Intf.data_read_reg_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[26]\,
      Q => data_read_reg(26)
    );
\Serial_Dbg_Intf.data_read_reg_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[27]\,
      Q => data_read_reg(27)
    );
\Serial_Dbg_Intf.data_read_reg_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[28]\,
      Q => data_read_reg(28)
    );
\Serial_Dbg_Intf.data_read_reg_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[29]\,
      Q => data_read_reg(29)
    );
\Serial_Dbg_Intf.data_read_reg_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[2]\,
      Q => data_read_reg(2)
    );
\Serial_Dbg_Intf.data_read_reg_reg[30]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[30]\,
      Q => data_read_reg(30)
    );
\Serial_Dbg_Intf.data_read_reg_reg[31]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[31]\,
      Q => data_read_reg(31)
    );
\Serial_Dbg_Intf.data_read_reg_reg[32]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[32]\,
      Q => data_read_reg(32)
    );
\Serial_Dbg_Intf.data_read_reg_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[3]\,
      Q => data_read_reg(3)
    );
\Serial_Dbg_Intf.data_read_reg_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[4]\,
      Q => data_read_reg(4)
    );
\Serial_Dbg_Intf.data_read_reg_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[5]\,
      Q => data_read_reg(5)
    );
\Serial_Dbg_Intf.data_read_reg_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[6]\,
      Q => data_read_reg(6)
    );
\Serial_Dbg_Intf.data_read_reg_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[7]\,
      Q => data_read_reg(7)
    );
\Serial_Dbg_Intf.data_read_reg_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[8]\,
      Q => data_read_reg(8)
    );
\Serial_Dbg_Intf.data_read_reg_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \data_rd_reg_reg_n_0_[9]\,
      Q => data_read_reg(9)
    );
\Serial_Dbg_Intf.dbg_disable_interrupt_i_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(9),
      Q => \^lockstep_master_out\(37),
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.dbg_wakeup_i_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => Dbg_Reg_En_0_sn_1,
      I1 => Dbg_Reg_En(6),
      I2 => Dbg_Reg_En(7),
      I3 => Dbg_Reg_En(4),
      I4 => Dbg_Reg_En(5),
      O => Control_Reg_En
    );
\Serial_Dbg_Intf.dbg_wakeup_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0000AB01"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => \^sleep_out\,
      I2 => Sleep_Decode,
      I3 => Scan_Reset,
      I4 => Scan_En,
      O => \Serial_Dbg_Intf.dbg_wakeup_i_i_2_n_0\
    );
\Serial_Dbg_Intf.dbg_wakeup_i_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => Dbg_Reg_En(0),
      I1 => Dbg_Reg_En(1),
      I2 => Dbg_Reg_En(3),
      I3 => Dbg_Reg_En(2),
      O => Dbg_Reg_En_0_sn_1
    );
\Serial_Dbg_Intf.dbg_wakeup_i_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.dbg_wakeup_i_i_2_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[31]\,
      Q => \^lockstep_master_out\(34)
    );
\Serial_Dbg_Intf.force_stop_TClk_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E4"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => \^serial_dbg_intf.force_stop_cmd_i_reg_0\,
      I2 => Scan_Reset,
      I3 => Scan_En,
      O => \Serial_Dbg_Intf.force_stop_TClk_i_1_n_0\
    );
\Serial_Dbg_Intf.force_stop_TClk_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.force_stop_TClk_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[29]\,
      Q => \p_1_out__0\(1)
    );
\Serial_Dbg_Intf.force_stop_cmd_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => p_91_out,
      Q => \^serial_dbg_intf.force_stop_cmd_i_reg_0\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.if_debug_ready_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => p_76_out,
      Q => \^lockstep_master_out\(36),
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.instr_read_reg_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => instr_rd_reg(0),
      Q => instr_read_reg(0)
    );
\Serial_Dbg_Intf.instr_read_reg_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \^exception_reg_0\(0),
      Q => instr_read_reg(1)
    );
\Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Instr_Insert_Reg_En_1,
      Q => \Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.normal_stop_TClk_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E4"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => \Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0\,
      I2 => Scan_Reset,
      I3 => Scan_En,
      O => \Serial_Dbg_Intf.normal_stop_TClk_i_1_n_0\
    );
\Serial_Dbg_Intf.normal_stop_TClk_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.normal_stop_TClk_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[28]\,
      Q => p_1_out(1)
    );
\Serial_Dbg_Intf.normal_stop_cmd_i_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => p_94_out,
      Q => \Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.read_register_MSR_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => p_86_out,
      Q => read_register_MSR,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.read_register_PC_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => p_83_out,
      Q => read_register_PC,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(0),
      Q => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[0]\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(1),
      Q => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[1]\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(2),
      Q => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[2]\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(3),
      Q => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[3]\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(4),
      Q => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[4]\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(5),
      Q => p_0_in_1,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(6),
      Q => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[6]\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(7),
      Q => p_0_in71_in,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sample_synced_1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sample_synced(8),
      Q => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[8]\,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.shift_count[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Dbg_Shift,
      I1 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      O => \Serial_Dbg_Intf.shift_count[0]_i_1_n_0\
    );
\Serial_Dbg_Intf.shift_count[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => A1,
      I1 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I2 => Dbg_Shift,
      O => p_0_in(1)
    );
\Serial_Dbg_Intf.shift_count[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => A2,
      I1 => A1,
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => Dbg_Shift,
      O => p_0_in(2)
    );
\Serial_Dbg_Intf.shift_count[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAA0000"
    )
        port map (
      I0 => A3,
      I1 => A2,
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => Dbg_Shift,
      O => p_0_in(3)
    );
\Serial_Dbg_Intf.shift_count[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAA00000000"
    )
        port map (
      I0 => sel0(0),
      I1 => A3,
      I2 => A1,
      I3 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I4 => A2,
      I5 => Dbg_Shift,
      O => p_0_in(4)
    );
\Serial_Dbg_Intf.shift_count[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sel0__0\(1),
      I1 => \Serial_Dbg_Intf.shift_count[5]_i_2_n_0\,
      I2 => Dbg_Shift,
      O => p_0_in(5)
    );
\Serial_Dbg_Intf.shift_count[5]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => sel0(0),
      I1 => A2,
      I2 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I3 => A1,
      I4 => A3,
      O => \Serial_Dbg_Intf.shift_count[5]_i_2_n_0\
    );
\Serial_Dbg_Intf.shift_count[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"60"
    )
        port map (
      I0 => \sel0__0\(2),
      I1 => \Serial_Dbg_Intf.shift_count[7]_i_2_n_0\,
      I2 => Dbg_Shift,
      O => p_0_in(6)
    );
\Serial_Dbg_Intf.shift_count[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6A00"
    )
        port map (
      I0 => \sel0__0\(3),
      I1 => \sel0__0\(2),
      I2 => \Serial_Dbg_Intf.shift_count[7]_i_2_n_0\,
      I3 => Dbg_Shift,
      O => p_0_in(7)
    );
\Serial_Dbg_Intf.shift_count[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => \sel0__0\(1),
      I1 => A3,
      I2 => A1,
      I3 => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\,
      I4 => A2,
      I5 => sel0(0),
      O => \Serial_Dbg_Intf.shift_count[7]_i_2_n_0\
    );
\Serial_Dbg_Intf.shift_count_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_count[0]_i_1_n_0\,
      Q => \Serial_Dbg_Intf.shift_count_reg_n_0_[0]\
    );
\Serial_Dbg_Intf.shift_count_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_0_in(1),
      Q => A1
    );
\Serial_Dbg_Intf.shift_count_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_0_in(2),
      Q => A2
    );
\Serial_Dbg_Intf.shift_count_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_0_in(3),
      Q => A3
    );
\Serial_Dbg_Intf.shift_count_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_0_in(4),
      Q => sel0(0)
    );
\Serial_Dbg_Intf.shift_count_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_0_in(5),
      Q => \sel0__0\(1)
    );
\Serial_Dbg_Intf.shift_count_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_0_in(6),
      Q => \sel0__0\(2)
    );
\Serial_Dbg_Intf.shift_count_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => p_0_in(7),
      Q => \sel0__0\(3)
    );
\Serial_Dbg_Intf.shift_datain_reg[10]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[11]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[10]\
    );
\Serial_Dbg_Intf.shift_datain_reg[11]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[12]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[11]\
    );
\Serial_Dbg_Intf.shift_datain_reg[12]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[13]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[12]\
    );
\Serial_Dbg_Intf.shift_datain_reg[13]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[14]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[13]\
    );
\Serial_Dbg_Intf.shift_datain_reg[14]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[15]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[14]\
    );
\Serial_Dbg_Intf.shift_datain_reg[15]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[16]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[15]\
    );
\Serial_Dbg_Intf.shift_datain_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[17]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[16]\
    );
\Serial_Dbg_Intf.shift_datain_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[18]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[17]\
    );
\Serial_Dbg_Intf.shift_datain_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[19]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[18]\
    );
\Serial_Dbg_Intf.shift_datain_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[20]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[19]\
    );
\Serial_Dbg_Intf.shift_datain_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[2]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[1]\
    );
\Serial_Dbg_Intf.shift_datain_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[21]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[20]\
    );
\Serial_Dbg_Intf.shift_datain_reg[21]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[22]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[21]\
    );
\Serial_Dbg_Intf.shift_datain_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[23]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[22]\
    );
\Serial_Dbg_Intf.shift_datain_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[24]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[23]\
    );
\Serial_Dbg_Intf.shift_datain_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[25]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[24]\
    );
\Serial_Dbg_Intf.shift_datain_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[26]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[25]\
    );
\Serial_Dbg_Intf.shift_datain_reg[26]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[27]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[26]\
    );
\Serial_Dbg_Intf.shift_datain_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[28]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[27]\
    );
\Serial_Dbg_Intf.shift_datain_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[29]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[28]\
    );
\Serial_Dbg_Intf.shift_datain_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[30]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[29]\
    );
\Serial_Dbg_Intf.shift_datain_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[3]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[2]\
    );
\Serial_Dbg_Intf.shift_datain_reg[30]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[31]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[30]\
    );
\Serial_Dbg_Intf.shift_datain_reg[31]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => Dbg_TDI,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[31]\
    );
\Serial_Dbg_Intf.shift_datain_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[4]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[3]\
    );
\Serial_Dbg_Intf.shift_datain_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[5]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[4]\
    );
\Serial_Dbg_Intf.shift_datain_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[6]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[5]\
    );
\Serial_Dbg_Intf.shift_datain_reg[6]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[7]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[6]\
    );
\Serial_Dbg_Intf.shift_datain_reg[7]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[8]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[7]\
    );
\Serial_Dbg_Intf.shift_datain_reg[8]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[9]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[8]\
    );
\Serial_Dbg_Intf.shift_datain_reg[9]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[10]\,
      Q => \Serial_Dbg_Intf.shift_datain_reg_n_0_[9]\
    );
\Serial_Dbg_Intf.single_Step_TClk_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E4"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => start_single_step_reg_n_0,
      I2 => Scan_Reset,
      I3 => Scan_En,
      O => \Serial_Dbg_Intf.single_Step_TClk_i_1_n_0\
    );
\Serial_Dbg_Intf.single_Step_TClk_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Update,
      CE => Control_Reg_En,
      CLR => \Serial_Dbg_Intf.single_Step_TClk_i_1_n_0\,
      D => \Serial_Dbg_Intf.shift_datain_reg_n_0_[23]\,
      Q => \p_1_out__1\(1)
    );
\Serial_Dbg_Intf.start_single_cmd_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => p_88_out,
      Q => start_single_cmd,
      R => reset_bool_for_rst
    );
\Serial_Dbg_Intf.status_reg_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => sync,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[0]\
    );
\Serial_Dbg_Intf.status_reg_reg[16]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.sync_stop_CPU_n_0\,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[16]\
    );
\Serial_Dbg_Intf.status_reg_reg[17]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => reset_bool_for_rst,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[17]\
    );
\Serial_Dbg_Intf.status_reg_reg[18]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => Full_32_bit,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[18]\
    );
\Serial_Dbg_Intf.status_reg_reg[19]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => delay_slot_instr,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[19]\
    );
\Serial_Dbg_Intf.status_reg_reg[20]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => Full_32_bit_1,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[20]\
    );
\Serial_Dbg_Intf.status_reg_reg[22]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.status_reg_reg[22]_0\(0),
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[22]\
    );
\Serial_Dbg_Intf.status_reg_reg[23]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => dbg_brki_hit_synced,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[23]\
    );
\Serial_Dbg_Intf.status_reg_reg[24]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => running_clock_synced,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[24]\
    );
\Serial_Dbg_Intf.status_reg_reg[25]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => D(1),
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[25]\
    );
\Serial_Dbg_Intf.status_reg_reg[27]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => sleep_synced,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[27]\
    );
\Serial_Dbg_Intf.status_reg_reg[28]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => pause_synced,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[28]\
    );
\Serial_Dbg_Intf.status_reg_reg[29]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => Dbg_Capture,
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => unchanged,
      Q => \Serial_Dbg_Intf.status_reg_reg_n_0_[29]\
    );
\Serial_Dbg_Intf.sync_dbg_brk_hit\: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized2\
     port map (
      D(0) => dbg_brki_hit_synced,
      Dbg_Clk => Dbg_Clk,
      \Single_Synchronize.use_async_reset.sync_reg_0\ => \Serial_Dbg_Intf.sync_pause_n_1\,
      dbg_brki_hit => dbg_brki_hit
    );
\Serial_Dbg_Intf.sync_dbg_hit\: entity work.design_1_microblaze_0_0_mb_sync_vec
     port map (
      D(0) => sync,
      Dbg_Clk => Dbg_Clk,
      \Single_Synchronize.use_async_reset.sync_reg\ => \Serial_Dbg_Intf.sync_pause_n_1\,
      dbg_hit(0) => dbg_hit(0)
    );
\Serial_Dbg_Intf.sync_dbg_wakeup\: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized4\
     port map (
      Clk => Clk,
      LOCKSTEP_Master_Out(1 downto 0) => \^lockstep_master_out\(34 downto 33),
      \Performance_Debug_Control.dbg_stop_i_reg\ => \Serial_Dbg_Intf.sync_dbg_wakeup_n_0\,
      dbg_continue_i_reg => \Performance_Debug_Control.dbg_stop_i_reg_n_0\,
      dbg_continue_i_reg_0 => \Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0\,
      dbg_continue_i_reg_1 => dbg_continue_i_i_2_n_0,
      of_pause => of_pause,
      sync_reset => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sync_pause\: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized2_25\
     port map (
      D(0) => pause_synced,
      Dbg_Clk => Dbg_Clk,
      Pause => Pause,
      Scan_En => Scan_En,
      Scan_Reset => Scan_Reset,
      Scan_Reset_Sel => Scan_Reset_Sel,
      \Single_Synchronize.use_async_reset.sync_i_1_0\ => \Serial_Dbg_Intf.sync_pause_n_1\
    );
\Serial_Dbg_Intf.sync_running_clock\: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized2_26\
     port map (
      D(0) => running_clock_synced,
      Dbg_Clk => Dbg_Clk,
      \Single_Synchronize.use_async_reset.sync_reg_0\ => \Serial_Dbg_Intf.sync_pause_n_1\,
      running_clock => running_clock
    );
\Serial_Dbg_Intf.sync_sample\: entity work.\design_1_microblaze_0_0_mb_sync_vec__parameterized1\
     port map (
      Clk => Clk,
      D(0) => p_1_out(1),
      Dbg_Trig_Ack_In(0) => Dbg_Trig_Ack_In(0),
      Dbg_Trig_Ack_Out(0) => \^dbg_trig_ack_out\(0),
      Dbg_Trig_In(0) => \^dbg_trig_in\(0),
      Dbg_Trig_Out(0) => Dbg_Trig_Out(0),
      Q(8) => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[0]\,
      Q(7) => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[1]\,
      Q(6) => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[2]\,
      Q(5) => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[3]\,
      Q(4) => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[4]\,
      Q(3) => p_0_in_1,
      Q(2) => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[6]\,
      Q(1) => p_0_in71_in,
      Q(0) => \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[8]\,
      \Serial_Dbg_Intf.trig_ack_out_1_reg\ => \Serial_Dbg_Intf.sync_sample_n_12\,
      \Synchronize.use_sync_reset.sync_reg[1]\(0) => \p_1_out__0\(1),
      \Synchronize.use_sync_reset.sync_reg[1]_0\(0) => \p_1_out__1\(1),
      \Synchronize.use_sync_reset.sync_reg[1]_1\(1) => \p_1_out__2\(1),
      \Synchronize.use_sync_reset.sync_reg[1]_1\(0) => \p_1_out__3\(1),
      \Synchronize.use_sync_reset.sync_reg[1]_2\(0) => \p_1_out__4\(1),
      \Synchronize.use_sync_reset.sync_reg[1]_3\(0) => \p_1_out__5\(1),
      \Synchronize.use_sync_reset.sync_reg[1]_4\(0) => \Serial_Dbg_Intf.control_reg_reg_n_0_[3]\,
      \Use_Async_Reset.sync_reset_reg\ => \Serial_Dbg_Intf.sync_sample_n_10\,
      p_11_out => p_11_out,
      p_76_out => p_76_out,
      p_83_out => p_83_out,
      p_86_out => p_86_out,
      p_88_out => p_88_out,
      p_91_out => p_91_out,
      p_94_out => p_94_out,
      sample_synced(0 to 9) => sample_synced(0 to 9),
      sync_reset => reset_bool_for_rst
    );
\Serial_Dbg_Intf.sync_sleep\: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized2_27\
     port map (
      D(0) => sleep_synced,
      Dbg_Clk => Dbg_Clk,
      \Single_Synchronize.use_async_reset.sync_reg_0\ => \Serial_Dbg_Intf.sync_pause_n_1\,
      Sleep => Sleep
    );
\Serial_Dbg_Intf.sync_stop_CPU\: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized2_28\
     port map (
      D(0) => \Serial_Dbg_Intf.sync_stop_CPU_n_0\,
      Dbg_Clk => Dbg_Clk,
      \Single_Synchronize.use_async_reset.sync_reg_0\ => \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\,
      \Single_Synchronize.use_async_reset.sync_reg_1\ => \Serial_Dbg_Intf.sync_pause_n_1\
    );
\Serial_Dbg_Intf.trig_ack_out_1_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Serial_Dbg_Intf.sync_sample_n_12\,
      Q => \^dbg_trig_ack_out\(0),
      R => '0'
    );
\Serial_Dbg_Intf.trig_in_1_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Serial_Dbg_Intf.sync_sample_n_10\,
      Q => \^dbg_trig_in\(0),
      R => '0'
    );
\Serial_Dbg_Intf.unchanged_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF00001000"
    )
        port map (
      I0 => Dbg_Reg_En(5),
      I1 => Dbg_Reg_En(4),
      I2 => Dbg_Reg_En(7),
      I3 => Dbg_Reg_En(6),
      I4 => Dbg_Reg_En_0_sn_1,
      I5 => unchanged,
      O => \Serial_Dbg_Intf.unchanged_i_1_n_0\
    );
\Serial_Dbg_Intf.unchanged_reg\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Dbg_Clk,
      CE => '1',
      CLR => \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0\,
      D => \Serial_Dbg_Intf.unchanged_i_1_n_0\,
      Q => unchanged
    );
\Using_FPGA.Native_i_1__2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^lockstep_master_out\(32),
      I1 => \^lockstep_master_out\(35),
      O => \Performance_Debug_Control.dbg_stop_if_delay_i_reg_0\
    );
\Using_FPGA.Native_i_1__49\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^lockstep_master_out\(32),
      O => \Performance_Debug_Control.dbg_stop_if_delay_i_reg_1\
    );
\Using_FPGA.Native_i_1__8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^lockstep_master_out\(35),
      I1 => \^lockstep_master_out\(32),
      O => ex_exception_no_load_store_mask
    );
\Using_FPGA.Native_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D000"
    )
        port map (
      I0 => \^lockstep_master_out\(35),
      I1 => \^lockstep_master_out\(32),
      I2 => ex_valid,
      I3 => \Using_FPGA.Native_i_2__21\,
      O => ex_MSR_Load_ALU_C
    );
\Using_FPGA.Native_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D000"
    )
        port map (
      I0 => \^lockstep_master_out\(35),
      I1 => \^lockstep_master_out\(32),
      I2 => ex_valid,
      I3 => ex_load_shift_carry,
      O => ex_MSR_Load_Shift_C
    );
\Using_LWX_SWX_instr.ex_reservation_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D000"
    )
        port map (
      I0 => \^lockstep_master_out\(35),
      I1 => \^lockstep_master_out\(32),
      I2 => ex_valid,
      I3 => \Using_LWX_SWX_instr.ex_reservation_i_3\,
      O => ex_MSR_Set_SW_BIP
    );
\Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I\: entity work.design_1_microblaze_0_0_address_hit
     port map (
      Address(0 to 31) => Address(0 to 31),
      Dbg_Clk => Dbg_Clk,
      Dbg_Reg_En(0 to 7) => Dbg_Reg_En(0 to 7),
      Dbg_TDI => Dbg_TDI,
      Hit => \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_0\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2\ => \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\ => \Performance_Debug_Control.dbg_stop_i_reg_n_0\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\ => \Performance_Debug_Control.ex_dbg_pc_hit_i_i_4_n_0\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2\ => of_piperun_for_ce,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3\ => \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_n_0\,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4\ => \^lockstep_master_out\(35),
      \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg\ => \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_2\,
      \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0\ => ex_piperun_for_ce,
      Q(1) => \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\,
      Q(0) => \^q\(0),
      ex_Exception_Taken => \^ex_exception_taken\,
      force_stop_i => force_stop_i,
      mem_Exception_Taken => mem_Exception_Taken,
      single_Step_N => single_Step_N,
      single_Step_N_reg => \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_1\
    );
Write_Strobe_INST_0_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => ex_valid,
      I1 => \^lockstep_master_out\(32),
      I2 => \^lockstep_master_out\(35),
      O => p_231_in
    );
command_reg_clear_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => read_register_PC_1_reg_n_0,
      I1 => \^read_register_msr_1_reg_0\,
      O => command_reg_clear_i_1_n_0
    );
command_reg_clear_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => command_reg_clear_i_1_n_0,
      Q => command_reg_clear,
      R => reset_bool_for_rst
    );
\data_rd_reg[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF8"
    )
        port map (
      I0 => wb_gpr_wr_dbg,
      I1 => \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\,
      I2 => \^read_register_msr_1_reg_0\,
      I3 => read_register_PC_1_reg_n_0,
      O => \data_rd_reg[0]_i_1_n_0\
    );
\data_rd_reg[32]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CEAACFFFCEAACC00"
    )
        port map (
      I0 => \data_rd_reg[32]_i_2_n_0\,
      I1 => wb_gpr_wr_dbg,
      I2 => \^lockstep_master_out\(36),
      I3 => \^performance_debug_control.dbg_stop_instr_fetch_nohalt_reg_0\,
      I4 => \data_rd_reg[32]_i_3_n_0\,
      I5 => \data_rd_reg_reg_n_0_[32]\,
      O => \data_rd_reg[32]_i_1_n_0\
    );
\data_rd_reg[32]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \^read_register_msr_1_reg_0\,
      I1 => \^performance_debug_control.dbg_freeze_nohalt_reg_0\,
      I2 => wb_pc_valid,
      O => \data_rd_reg[32]_i_2_n_0\
    );
\data_rd_reg[32]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^read_register_msr_1_reg_0\,
      I1 => read_register_PC_1_reg_n_0,
      O => \data_rd_reg[32]_i_3_n_0\
    );
\data_rd_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(31),
      Q => \data_rd_reg_reg_n_0_[0]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(21),
      Q => \data_rd_reg_reg_n_0_[10]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(20),
      Q => \data_rd_reg_reg_n_0_[11]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(19),
      Q => \data_rd_reg_reg_n_0_[12]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(18),
      Q => \data_rd_reg_reg_n_0_[13]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(17),
      Q => \data_rd_reg_reg_n_0_[14]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(16),
      Q => \data_rd_reg_reg_n_0_[15]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(15),
      Q => \data_rd_reg_reg_n_0_[16]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(14),
      Q => \data_rd_reg_reg_n_0_[17]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(13),
      Q => \data_rd_reg_reg_n_0_[18]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(12),
      Q => \data_rd_reg_reg_n_0_[19]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(30),
      Q => \data_rd_reg_reg_n_0_[1]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(11),
      Q => \data_rd_reg_reg_n_0_[20]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(10),
      Q => \data_rd_reg_reg_n_0_[21]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(9),
      Q => \data_rd_reg_reg_n_0_[22]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(8),
      Q => \data_rd_reg_reg_n_0_[23]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(7),
      Q => \data_rd_reg_reg_n_0_[24]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(6),
      Q => \data_rd_reg_reg_n_0_[25]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(5),
      Q => \data_rd_reg_reg_n_0_[26]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(4),
      Q => \data_rd_reg_reg_n_0_[27]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(3),
      Q => \data_rd_reg_reg_n_0_[28]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(2),
      Q => \data_rd_reg_reg_n_0_[29]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(29),
      Q => \data_rd_reg_reg_n_0_[2]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(1),
      Q => \data_rd_reg_reg_n_0_[30]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(0),
      Q => \data_rd_reg_reg_n_0_[31]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \data_rd_reg[32]_i_1_n_0\,
      Q => \data_rd_reg_reg_n_0_[32]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(28),
      Q => \data_rd_reg_reg_n_0_[3]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(27),
      Q => \data_rd_reg_reg_n_0_[4]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(26),
      Q => \data_rd_reg_reg_n_0_[5]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(25),
      Q => \data_rd_reg_reg_n_0_[6]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(24),
      Q => \data_rd_reg_reg_n_0_[7]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(23),
      Q => \data_rd_reg_reg_n_0_[8]\,
      R => reset_bool_for_rst
    );
\data_rd_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \data_rd_reg[0]_i_1_n_0\,
      D => \data_rd_reg_reg[0]_0\(22),
      Q => \data_rd_reg_reg_n_0_[9]\,
      R => reset_bool_for_rst
    );
dbg_continue_i_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^lockstep_master_out\(36),
      I1 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      I2 => \^serial_dbg_intf.force_stop_cmd_i_reg_0\,
      I3 => start_single_cmd,
      O => dbg_continue_i_i_2_n_0
    );
dbg_continue_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Serial_Dbg_Intf.sync_dbg_wakeup_n_0\,
      Q => \^lockstep_master_out\(33),
      R => reset_bool_for_rst
    );
dbg_halt_reset_mode_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22222222000000F0"
    )
        port map (
      I0 => Reset_Mode(0),
      I1 => Reset_Mode(1),
      I2 => \^dbg_halt_reset_mode_reg_0\,
      I3 => \Serial_Dbg_Intf.control_reg_reg_n_0_[0]\,
      I4 => \step_continue__0\,
      I5 => reset_bool_for_rst,
      O => dbg_halt_reset_mode_i_1_n_0
    );
dbg_halt_reset_mode_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => start_single_step_reg_n_0,
      I1 => \Serial_Dbg_Intf.continue_from_brk_reg_n_0\,
      O => \step_continue__0\
    );
dbg_halt_reset_mode_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => dbg_halt_reset_mode_i_1_n_0,
      Q => \^dbg_halt_reset_mode_reg_0\,
      R => '0'
    );
delay_slot_instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => wb_Halted,
      D => D(0),
      Q => delay_slot_instr,
      R => reset_bool_for_rst
    );
exception_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => exception_reg_1,
      I1 => force_stop_overrun,
      I2 => start_dbg_exec_reg_n_0,
      I3 => reset_bool_for_rst,
      O => exception_i_1_n_0
    );
exception_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => exception_i_1_n_0,
      Q => \^exception_reg_0\(0),
      R => '0'
    );
executing_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000EECE"
    )
        port map (
      I0 => instr_rd_reg(0),
      I1 => start_dbg_exec_reg_n_0,
      I2 => executing_reg_0,
      I3 => wb_Halted,
      I4 => reset_bool_for_rst,
      I5 => force_stop_overrun,
      O => executing_i_1_n_0
    );
executing_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => executing_i_1_n_0,
      Q => instr_rd_reg(0),
      R => '0'
    );
mb_halted_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => D(2),
      Q => mb_halted_1,
      R => reset_bool_for_rst
    );
mem_exception_from_ex_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"40"
    )
        port map (
      I0 => \^lockstep_master_out\(32),
      I1 => \^lockstep_master_out\(35),
      I2 => ex_valid,
      O => \^ex_exception_taken\
    );
read_register_MSR_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => read_register_MSR,
      Q => \^read_register_msr_1_reg_0\,
      R => reset_bool_for_rst
    );
read_register_PC_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => read_register_PC,
      Q => read_register_PC_1_reg_n_0,
      R => reset_bool_for_rst
    );
running_clock_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E4"
    )
        port map (
      I0 => Scan_Reset_Sel,
      I1 => capture_1,
      I2 => Scan_Reset,
      I3 => Scan_En,
      O => running_clock_i_1_n_0
    );
running_clock_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      CLR => running_clock_i_1_n_0,
      D => '1',
      Q => running_clock
    );
saved_reset_mode_dbg_halt_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => Reset_Mode(0),
      I1 => Reset_Mode(1),
      I2 => reset_bool_for_rst,
      I3 => saved_reset_mode_dbg_halt,
      O => saved_reset_mode_dbg_halt_i_1_n_0
    );
saved_reset_mode_dbg_halt_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => saved_reset_mode_dbg_halt_i_1_n_0,
      Q => saved_reset_mode_dbg_halt,
      R => '0'
    );
saved_reset_mode_sleep_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22F0"
    )
        port map (
      I0 => Reset_Mode(1),
      I1 => Reset_Mode(0),
      I2 => \^sleep_out\,
      I3 => reset_bool_for_rst,
      O => saved_reset_mode_sleep_i_1_n_0
    );
saved_reset_mode_sleep_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => saved_reset_mode_sleep_i_1_n_0,
      Q => saved_reset_mode_sleep,
      R => '0'
    );
single_Step_N_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => start_single_step_reg_n_0,
      I1 => single_step_count(1),
      I2 => single_step_count(0),
      O => single_Step_N_i_1_n_0
    );
single_Step_N_reg: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => of_piperun_for_ce,
      D => single_Step_N_i_1_n_0,
      Q => single_Step_N,
      S => reset_bool_for_rst
    );
\single_step_count[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => start_single_cmd,
      I1 => of_piperun_for_ce,
      O => \single_step_count[0]_i_1_n_0\
    );
\single_step_count[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9F90"
    )
        port map (
      I0 => single_step_count(1),
      I1 => single_step_count(0),
      I2 => of_piperun_for_ce,
      I3 => \Serial_Dbg_Intf.control_reg_reg_n_0_[4]\,
      O => \single_step_count[0]_i_2_n_0\
    );
\single_step_count[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"74"
    )
        port map (
      I0 => single_step_count(1),
      I1 => of_piperun_for_ce,
      I2 => \Serial_Dbg_Intf.control_reg_reg_n_0_[5]\,
      O => \single_step_count[1]_i_1_n_0\
    );
\single_step_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \single_step_count[0]_i_1_n_0\,
      D => \single_step_count[0]_i_2_n_0\,
      Q => single_step_count(0),
      R => reset_bool_for_rst
    );
\single_step_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \single_step_count[0]_i_1_n_0\,
      D => \single_step_count[1]_i_1_n_0\,
      Q => single_step_count(1),
      R => reset_bool_for_rst
    );
sleep_reset_mode_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAABBBFAAAA8880"
    )
        port map (
      I0 => sleep_reset_mode,
      I1 => saved_reset_mode_sleep,
      I2 => wakeup_i(0),
      I3 => wakeup_i(1),
      I4 => reset_bool_for_rst,
      I5 => \^sleep_out\,
      O => sleep_reset_mode_i_1_n_0
    );
sleep_reset_mode_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"20"
    )
        port map (
      I0 => reset_bool_for_rst,
      I1 => Reset_Mode(0),
      I2 => Reset_Mode(1),
      O => sleep_reset_mode
    );
sleep_reset_mode_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sleep_reset_mode_i_1_n_0,
      Q => \^sleep_out\,
      R => '0'
    );
start_dbg_exec_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^lockstep_master_out\(36),
      Q => start_dbg_exec_reg_n_0,
      R => reset_bool_for_rst
    );
start_single_step_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3232320232323232"
    )
        port map (
      I0 => start_single_cmd,
      I1 => reset_bool_for_rst,
      I2 => start_single_step_reg_n_0,
      I3 => single_step_count(1),
      I4 => single_step_count(0),
      I5 => of_piperun_for_ce,
      O => start_single_step_i_1_n_0
    );
start_single_step_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => start_single_step_i_1_n_0,
      Q => start_single_step_reg_n_0,
      R => '0'
    );
sync_trig_ack_in_0: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized4_29\
     port map (
      Clk => Clk,
      D(0) => D(2),
      Dbg_Trig_Ack_In(0) => Dbg_Trig_Ack_In(1),
      Dbg_Trig_In(0) => \^dbg_trig_in\(1),
      mb_halted_1 => mb_halted_1,
      sync_reset => reset_bool_for_rst,
      trig_ack_in_0_synced => trig_ack_in_0_synced,
      trig_ack_in_0_synced_1 => trig_ack_in_0_synced_1,
      trig_in_0_reg => sync_trig_ack_in_0_n_1
    );
sync_trig_out_0: entity work.\design_1_microblaze_0_0_mb_sync_bit__parameterized4_30\
     port map (
      Clk => Clk,
      D(0) => D(2),
      Dbg_Stop => Dbg_Stop,
      Dbg_Trig_Ack_Out(0) => \^dbg_trig_ack_out\(1),
      Dbg_Trig_Out(0) => Dbg_Trig_Out(1),
      \Performance_Debug_Control.dbg_stop_i_reg\ => \Performance_Debug_Control.dbg_stop_i_reg_n_0\,
      \Performance_Debug_Control.trig_ack_out_0_reg\ => sync_trig_out_0_n_1,
      \Performance_Debug_Control.trig_out_0_synced_1_reg\ => sync_trig_out_0_n_2,
      dbg_stop_1 => dbg_stop_1,
      sync_reset => reset_bool_for_rst,
      trig_out_0_synced => trig_out_0_synced,
      trig_out_0_synced_1 => trig_out_0_synced_1
    );
trig_ack_in_0_synced_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => trig_ack_in_0_synced,
      Q => trig_ack_in_0_synced_1,
      R => reset_bool_for_rst
    );
trig_in_0_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => sync_trig_ack_in_0_n_1,
      Q => \^dbg_trig_in\(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Decode_gti is
  port (
    of_pause_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    of_gpr_op3_rd_addr : out STD_LOGIC_VECTOR ( 0 to 4 );
    of_gpr_op1_rd_addr : out STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : out STD_LOGIC_VECTOR ( 0 to 15 );
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    ex_valid : out STD_LOGIC;
    ex_is_load_instr_s : out STD_LOGIC;
    ex_byte_access : out STD_LOGIC;
    ex_doublet_access : out STD_LOGIC;
    ex_reverse_mem_access : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    ex_op1_cmp_equal : out STD_LOGIC;
    ex_op1_cmp_equal_n : out STD_LOGIC;
    mem_Exception_Taken : out STD_LOGIC;
    Hibernate : out STD_LOGIC;
    Suspend : out STD_LOGIC;
    Sleep_Decode : out STD_LOGIC;
    Pause_Ack : out STD_LOGIC;
    ex_set_bip_reg_0 : out STD_LOGIC;
    mem_databus_read : out STD_LOGIC;
    mem_databus_write : out STD_LOGIC;
    \Performance_Debug_Control.dbg_state_nohalt_reg\ : out STD_LOGIC_VECTOR ( 159 downto 0 );
    mem_byte_access : out STD_LOGIC;
    mem_doublet_access : out STD_LOGIC;
    wb_byte_access : out STD_LOGIC;
    wb_PipeRun_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    ex_cmp_op : out STD_LOGIC;
    ex_unsigned_op : out STD_LOGIC;
    ex_use_carry : out STD_LOGIC;
    EX_Enable_ALU : out STD_LOGIC;
    EX_ALU_Sel_Logic : out STD_LOGIC;
    ex_swap_byte_instr : out STD_LOGIC;
    ex_load_alu_carry_reg_0 : out STD_LOGIC;
    ex_load_shift_carry : out STD_LOGIC;
    ex_move_to_MSR_instr : out STD_LOGIC;
    mem_sel_msr : out STD_LOGIC;
    wb_gpr_wr_dbg : out STD_LOGIC;
    wb_read_imm_reg : out STD_LOGIC;
    wb_read_imm_reg_1 : out STD_LOGIC;
    wb_pc_valid : out STD_LOGIC;
    dbg_clean_stop : out STD_LOGIC;
    of_pause : out STD_LOGIC;
    mem_databus_access : out STD_LOGIC;
    wb_valid_reg_0 : out STD_LOGIC;
    wb_Halted : out STD_LOGIC;
    \ex_swx_access__0\ : out STD_LOGIC;
    ex_MSR_Load_LWX_SWX_C : out STD_LOGIC;
    SRI : out STD_LOGIC;
    ex_set_bip_reg_1 : out STD_LOGIC;
    LOCKSTEP_Master_Out : out STD_LOGIC_VECTOR ( 2 downto 0 );
    ex_sel_alu_i_reg_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    EX_Fwd : out STD_LOGIC_VECTOR ( 0 to 31 );
    ex_sel_alu_i_reg_1 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ex_sel_alu_i_reg_2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    wb_gpr_write_dbg_reg_0 : out STD_LOGIC_VECTOR ( 23 downto 0 );
    SR : out STD_LOGIC_VECTOR ( 0 to 0 );
    R : out STD_LOGIC;
    I1 : out STD_LOGIC;
    M_AXI_DP_BVALID_0 : out STD_LOGIC;
    MEM_DataBus_Write_reg_0 : out STD_LOGIC;
    MEM_DataBus_Write_reg_1 : out STD_LOGIC;
    MEM_DataBus_Write_reg_2 : out STD_LOGIC;
    dbg_halt_reset_mode_reg : out STD_LOGIC;
    \p_4_out__0\ : out STD_LOGIC;
    dbg_stop_i : out STD_LOGIC;
    \Serial_Dbg_Intf.control_reg_reg[8]\ : out STD_LOGIC;
    Sleep : out STD_LOGIC;
    DI : out STD_LOGIC;
    \EX_ALU_Op_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \EX_Sext_Op_reg[0]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    in0 : out STD_LOGIC;
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg\ : out STD_LOGIC;
    \Performance_Debug_Control.dbg_freeze_nohalt_reg\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC;
    \Using_FPGA.Native_5\ : out STD_LOGIC;
    \Using_FPGA.Native_6\ : out STD_LOGIC;
    \Using_FPGA.Native_7\ : out STD_LOGIC;
    \Using_FPGA.Native_8\ : out STD_LOGIC;
    \Using_FPGA.Native_9\ : out STD_LOGIC;
    \Using_FPGA.Native_10\ : out STD_LOGIC;
    \Using_FPGA.Native_11\ : out STD_LOGIC;
    \Using_FPGA.Native_12\ : out STD_LOGIC;
    \Using_FPGA.Native_13\ : out STD_LOGIC;
    \Using_FPGA.Native_14\ : out STD_LOGIC;
    \Using_FPGA.Native_15\ : out STD_LOGIC;
    \Using_FPGA.Native_16\ : out STD_LOGIC;
    \Using_FPGA.Native_17\ : out STD_LOGIC;
    \Using_FPGA.Native_18\ : out STD_LOGIC;
    \Using_FPGA.Native_19\ : out STD_LOGIC;
    \Using_FPGA.Native_20\ : out STD_LOGIC;
    \Using_FPGA.Native_21\ : out STD_LOGIC;
    \Using_FPGA.Native_22\ : out STD_LOGIC;
    \Using_FPGA.Native_23\ : out STD_LOGIC;
    \Using_FPGA.Native_24\ : out STD_LOGIC;
    \Using_FPGA.Native_25\ : out STD_LOGIC;
    \Using_FPGA.Native_26\ : out STD_LOGIC;
    \Using_FPGA.Native_27\ : out STD_LOGIC;
    \Using_FPGA.Native_28\ : out STD_LOGIC;
    \Using_FPGA.Native_29\ : out STD_LOGIC;
    \Using_FPGA.Native_30\ : out STD_LOGIC;
    \Using_FPGA.Native_31\ : out STD_LOGIC;
    \Using_FPGA.Native_32\ : out STD_LOGIC;
    \Using_FPGA.Native_33\ : out STD_LOGIC;
    I1_0 : out STD_LOGIC;
    of_op1_sel_spr : out STD_LOGIC;
    \Using_FPGA.Native_34\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \mem_pc_i_reg[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    sync_reset : in STD_LOGIC;
    Clk : in STD_LOGIC;
    I139_out : in STD_LOGIC;
    ex_op1_zero : in STD_LOGIC;
    \Using_FPGA.Native_35\ : in STD_LOGIC;
    MEM_DataBus_Ready : in STD_LOGIC;
    \Using_FPGA.Native_36\ : in STD_LOGIC;
    ex_exception_no_load_store_mask : in STD_LOGIC;
    ex_Exception_Taken : in STD_LOGIC;
    \MEM_DataBus_Addr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 70 downto 0 );
    Pause : in STD_LOGIC;
    \Using_FPGA.Native_37\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Y : in STD_LOGIC_VECTOR ( 0 to 31 );
    p_231_in : in STD_LOGIC;
    ex_MSR_Set_SW_BIP : in STD_LOGIC;
    \Using_FPGA.Native_38\ : in STD_LOGIC;
    ex_MSR : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \Using_FPGA.Native_39\ : in STD_LOGIC;
    \Using_FPGA.Native_40\ : in STD_LOGIC;
    if_missed_fetch_reg_0 : in STD_LOGIC;
    if_missed_fetch_reg_1 : in STD_LOGIC;
    MEM_Fwd : in STD_LOGIC_VECTOR ( 0 to 31 );
    GPR_Op2 : in STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Op2_reg[0]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
    GPR_Op3 : in STD_LOGIC_VECTOR ( 0 to 31 );
    GPR_Op1 : in STD_LOGIC_VECTOR ( 0 to 31 );
    \mem_pc_i_reg[0]_0\ : in STD_LOGIC;
    \data_rd_reg_reg[0]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3007]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \LOCKSTEP_Out_reg[3007]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3007]_1\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \LOCKSTEP_Out_reg[3008]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3009]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3010]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3011]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3012]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3013]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3014]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3015]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3016]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3017]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3018]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3019]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3020]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3021]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3022]\ : in STD_LOGIC;
    M_AXI_DP_BVALID : in STD_LOGIC;
    active_access : in STD_LOGIC;
    M_AXI_DP_RVALID : in STD_LOGIC;
    M_AXI_DP_WREADY : in STD_LOGIC;
    M_AXI_DP_AWREADY : in STD_LOGIC;
    M_AXI_DP_ARREADY : in STD_LOGIC;
    Reset_Mode : in STD_LOGIC_VECTOR ( 0 to 1 );
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0\ : in STD_LOGIC;
    active_access_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_41\ : in STD_LOGIC;
    IReady : in STD_LOGIC;
    DReady : in STD_LOGIC;
    DWait : in STD_LOGIC;
    active_access_d1 : in STD_LOGIC;
    Sleep_Out : in STD_LOGIC;
    wakeup_i : in STD_LOGIC_VECTOR ( 0 to 1 );
    wb_databus_steered_read_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
    ex_databus_addr : in STD_LOGIC_VECTOR ( 1 downto 0 );
    swap_result : in STD_LOGIC_VECTOR ( 23 downto 0 );
    \Using_FPGA.Native_42\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \out\ : in STD_LOGIC;
    \Using_FPGA.Native_43\ : in STD_LOGIC;
    swap_result_reg : in STD_LOGIC_VECTOR ( 0 to 7 );
    \MEM_DataBus_Write_Data_reg[0]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    exception_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \in\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    lopt : in STD_LOGIC;
    lopt_1 : out STD_LOGIC;
    lopt_2 : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Decode_gti : entity is "Decode_gti";
end design_1_microblaze_0_0_Decode_gti;

architecture STRUCTURE of design_1_microblaze_0_0_Decode_gti is
  signal A : STD_LOGIC;
  signal \^d\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal D224_out : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O0_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O10_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O11_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O12_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O13_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O14_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O15_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O17_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O18_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O19_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O1_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O20_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O21_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O22_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O23_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O24_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O26_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O27_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O28_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O29_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O2_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O30_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O31_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O3_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O4_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O5_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O6_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O7_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O8_out\ : STD_LOGIC;
  signal \Data_Flow_I/Shift_Logic_Module_I/O9_out\ : STD_LOGIC;
  signal Dbg_Clean_Stop0 : STD_LOGIC;
  signal \^ex_alu_op_reg[0]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^ex_alu_sel_logic\ : STD_LOGIC;
  signal \^ex_fwd\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal EX_Is_Div_Instr : STD_LOGIC;
  signal \EX_MBAR_Stall__1\ : STD_LOGIC;
  signal \^ex_sext_op_reg[0]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^hibernate\ : STD_LOGIC;
  signal I0 : STD_LOGIC;
  signal I2 : STD_LOGIC;
  signal I4 : STD_LOGIC;
  signal I5 : STD_LOGIC;
  signal IB_Ready : STD_LOGIC;
  signal IF_PC_Write : STD_LOGIC;
  signal \^lockstep_master_out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal O : STD_LOGIC;
  signal O31_out : STD_LOGIC;
  signal O33_out : STD_LOGIC;
  signal O35_out : STD_LOGIC;
  signal O37_out : STD_LOGIC;
  signal O39_out : STD_LOGIC;
  signal O41_out : STD_LOGIC;
  signal O43_out : STD_LOGIC;
  signal O45_out : STD_LOGIC;
  signal O47_out : STD_LOGIC;
  signal O49_out : STD_LOGIC;
  signal O51_out : STD_LOGIC;
  signal O53_out : STD_LOGIC;
  signal O55_out : STD_LOGIC;
  signal O56_out : STD_LOGIC;
  signal O57_out : STD_LOGIC;
  signal O59_out : STD_LOGIC;
  signal O61_out : STD_LOGIC;
  signal O63_out : STD_LOGIC;
  signal O65_out : STD_LOGIC;
  signal O67_out : STD_LOGIC;
  signal O69_out : STD_LOGIC;
  signal O71_out : STD_LOGIC;
  signal O73_out : STD_LOGIC;
  signal O75_out : STD_LOGIC;
  signal O77_out : STD_LOGIC;
  signal O79_out : STD_LOGIC;
  signal O81_out : STD_LOGIC;
  signal O83_out : STD_LOGIC;
  signal O85_out : STD_LOGIC;
  signal O87_out : STD_LOGIC;
  signal PC_Module_I_n_35 : STD_LOGIC;
  signal Pause_Ack0 : STD_LOGIC;
  signal \^performance_debug_control.dbg_state_nohalt_reg\ : STD_LOGIC_VECTOR ( 159 downto 0 );
  signal PreFetch_Buffer_I1_n_169 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_173 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_176 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_177 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_178 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_179 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_182 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_183 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_184 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_185 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_186 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_187 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_188 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_189 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_190 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_191 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_193 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_194 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_195 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_3 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_48 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_49 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_50 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_56 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_59 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_64 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_65 : STD_LOGIC;
  signal PreFetch_Buffer_I1_n_66 : STD_LOGIC;
  signal \^sleep_decode\ : STD_LOGIC;
  signal \^suspend\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1\ : STD_LOGIC;
  signal \Use_MuxCy[11].OF_Piperun_Stage_n_1\ : STD_LOGIC;
  signal \Use_MuxCy[11].OF_Piperun_Stage_n_2\ : STD_LOGIC;
  signal \Use_MuxCy[11].OF_Piperun_Stage_n_3\ : STD_LOGIC;
  signal \Use_MuxCy[11].OF_Piperun_Stage_n_4\ : STD_LOGIC;
  signal \Use_MuxCy[3].OF_Piperun_Stage_n_1\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^using_fpga.native_0\ : STD_LOGIC;
  signal \^using_fpga.native_1\ : STD_LOGIC;
  signal \Using_FPGA.Native_i_5__1_n_0\ : STD_LOGIC;
  signal \Using_FPGA_2.ex_is_load_instr_Inst_n_3\ : STD_LOGIC;
  signal \Using_FPGA_2.ex_is_lwx_instr_Inst_n_1\ : STD_LOGIC;
  signal \Using_FPGA_2.ex_is_swx_instr_Inst_n_1\ : STD_LOGIC;
  signal \Using_FPGA_2.ex_is_swx_instr_Inst_n_4\ : STD_LOGIC;
  signal \Using_FPGA_3.of_clear_MSR_BIP_hold_Inst_n_0\ : STD_LOGIC;
  signal \Using_FPGA_4.of_read_ex_write_op2_conflict_INST2_n_0\ : STD_LOGIC;
  signal \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0\ : STD_LOGIC;
  signal \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0\ : STD_LOGIC;
  signal \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0\ : STD_LOGIC;
  signal \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0\ : STD_LOGIC;
  signal active_wakeup : STD_LOGIC;
  signal active_wakeup0 : STD_LOGIC;
  signal ex_Enable_Sext_Shift : STD_LOGIC;
  signal ex_Sel_SPR_BTR : STD_LOGIC;
  signal ex_Sel_SPR_EAR : STD_LOGIC;
  signal ex_Sel_SPR_EDR : STD_LOGIC;
  signal ex_Sel_SPR_ESR : STD_LOGIC;
  signal ex_Sel_SPR_FSR : STD_LOGIC;
  signal ex_Sel_SPR_PVR : STD_LOGIC;
  signal ex_Sel_SPR_SHR : STD_LOGIC;
  signal ex_Sel_SPR_SLR : STD_LOGIC;
  signal ex_Write_DCache_decode_cmb : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of ex_Write_DCache_decode_cmb : signal is "true";
  signal ex_Write_ICache_i : STD_LOGIC;
  signal ex_Write_ICache_i_cmb : STD_LOGIC;
  attribute RTL_KEEP of ex_Write_ICache_i_cmb : signal is "true";
  signal ex_branch_with_delayslot : STD_LOGIC;
  signal \^ex_byte_access\ : STD_LOGIC;
  signal ex_delayslot_Instr : STD_LOGIC;
  signal ex_delayslot_Instr0 : STD_LOGIC;
  signal \^ex_doublet_access\ : STD_LOGIC;
  signal ex_enable_sext_shift_i0 : STD_LOGIC;
  signal ex_first_cycle : STD_LOGIC;
  signal \ex_gpr_write_addr_reg_n_0_[0]\ : STD_LOGIC;
  signal \ex_gpr_write_addr_reg_n_0_[4]\ : STD_LOGIC;
  signal \ex_gpr_write_dbg__0\ : STD_LOGIC;
  signal ex_gpr_write_reg_n_0 : STD_LOGIC;
  signal ex_hibernate_i_i_1_n_0 : STD_LOGIC;
  signal \ex_instr_reg_n_0_[0]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[10]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[11]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[12]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[13]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[14]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[15]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[16]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[17]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[18]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[19]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[1]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[20]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[21]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[22]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[23]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[24]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[25]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[26]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[27]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[28]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[29]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[2]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[30]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[31]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[3]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[4]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[5]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[8]\ : STD_LOGIC;
  signal \ex_instr_reg_n_0_[9]\ : STD_LOGIC;
  signal ex_is_multi_instr2 : STD_LOGIC;
  signal ex_is_multi_or_load_instr : STD_LOGIC;
  signal ex_is_multi_or_load_instr0 : STD_LOGIC;
  signal ex_is_swx_instr_s : STD_LOGIC;
  signal ex_jump : STD_LOGIC;
  signal ex_jump_hold : STD_LOGIC;
  signal ex_jump_nodelay : STD_LOGIC;
  signal ex_jump_q : STD_LOGIC;
  signal ex_load_shift_carry0 : STD_LOGIC;
  signal ex_load_store_instr_s : STD_LOGIC;
  signal ex_mbar_decode : STD_LOGIC;
  signal ex_mbar_decode_cmb : STD_LOGIC;
  attribute RTL_KEEP of ex_mbar_decode_cmb : signal is "true";
  signal ex_mbar_is_sleep : STD_LOGIC;
  signal ex_mbar_is_sleep_cmb : STD_LOGIC;
  attribute RTL_KEEP of ex_mbar_is_sleep_cmb : signal is "true";
  signal ex_mbar_sleep : STD_LOGIC;
  signal ex_mbar_sleep_i_1_n_0 : STD_LOGIC;
  signal ex_mbar_stall_no_sleep_1 : STD_LOGIC;
  signal ex_mbar_stall_no_sleep_10 : STD_LOGIC;
  signal \ex_mbar_stall_no_sleep__0\ : STD_LOGIC;
  signal ex_mfsmsr_i : STD_LOGIC;
  signal ex_move_to_MSR_instr93_out : STD_LOGIC;
  signal ex_op1_cmp_eq1 : STD_LOGIC;
  signal ex_op1_cmp_eq_n5_out : STD_LOGIC;
  signal ex_opcode : STD_LOGIC_VECTOR ( 0 to 5 );
  signal ex_read_imm_reg : STD_LOGIC;
  signal ex_read_imm_reg_1 : STD_LOGIC;
  signal ex_read_imm_reg_i_1_n_0 : STD_LOGIC;
  signal ex_reservation : STD_LOGIC;
  signal \^ex_reverse_mem_access\ : STD_LOGIC;
  signal ex_sel_alu : STD_LOGIC;
  signal ex_sel_alu_i0 : STD_LOGIC;
  signal ex_set_bip : STD_LOGIC;
  signal \^ex_set_bip_reg_0\ : STD_LOGIC;
  signal ex_shift_logic_result : STD_LOGIC_VECTOR ( 0 to 0 );
  signal ex_shift_op : STD_LOGIC_VECTOR ( 0 to 1 );
  signal ex_sleep_i0 : STD_LOGIC;
  signal ex_sleep_i_i_1_n_0 : STD_LOGIC;
  signal ex_suspend_i0 : STD_LOGIC;
  signal ex_swap_instr : STD_LOGIC;
  signal \^ex_use_carry\ : STD_LOGIC;
  signal \^ex_valid\ : STD_LOGIC;
  signal ex_valid_jump : STD_LOGIC;
  attribute RTL_KEEP of ex_valid_jump : signal is "true";
  signal ex_write_dcache_instr : STD_LOGIC;
  signal flush_pipe : STD_LOGIC;
  signal force12_out : STD_LOGIC;
  signal force_Val10_out : STD_LOGIC;
  signal if_fetch_for_timing_optimization1 : STD_LOGIC;
  signal if_fetch_in_progress : STD_LOGIC;
  signal if_fetch_in_progress_i_1_n_0 : STD_LOGIC;
  signal if_fetch_without_full_or_jump : STD_LOGIC;
  attribute RTL_KEEP of if_fetch_without_full_or_jump : signal is "true";
  signal if_missed_fetch : STD_LOGIC;
  signal if_pc_incr_carry0 : STD_LOGIC;
  signal if_pc_incr_carry1 : STD_LOGIC;
  signal if_pc_incr_carry3 : STD_LOGIC;
  signal if_pre_buffer_addr : STD_LOGIC_VECTOR ( 1 to 1 );
  signal if_sel_input : STD_LOGIC_VECTOR ( 0 to 4 );
  signal jump_logic_I1_n_42 : STD_LOGIC;
  signal jump_logic_I1_n_6 : STD_LOGIC;
  signal jump_logic_I1_n_8 : STD_LOGIC;
  signal keep_jump_taken_with_ds : STD_LOGIC;
  signal lopt_10 : STD_LOGIC;
  signal lopt_11 : STD_LOGIC;
  signal lopt_12 : STD_LOGIC;
  signal lopt_13 : STD_LOGIC;
  signal lopt_14 : STD_LOGIC;
  signal lopt_15 : STD_LOGIC;
  signal lopt_16 : STD_LOGIC;
  signal lopt_17 : STD_LOGIC;
  signal lopt_18 : STD_LOGIC;
  signal lopt_19 : STD_LOGIC;
  signal lopt_20 : STD_LOGIC;
  signal lopt_21 : STD_LOGIC;
  signal lopt_22 : STD_LOGIC;
  signal lopt_23 : STD_LOGIC;
  signal lopt_24 : STD_LOGIC;
  signal lopt_25 : STD_LOGIC;
  signal lopt_26 : STD_LOGIC;
  signal lopt_27 : STD_LOGIC;
  signal lopt_28 : STD_LOGIC;
  signal lopt_29 : STD_LOGIC;
  signal lopt_3 : STD_LOGIC;
  signal lopt_30 : STD_LOGIC;
  signal lopt_31 : STD_LOGIC;
  signal lopt_32 : STD_LOGIC;
  signal lopt_33 : STD_LOGIC;
  signal lopt_34 : STD_LOGIC;
  signal lopt_35 : STD_LOGIC;
  signal lopt_36 : STD_LOGIC;
  signal lopt_37 : STD_LOGIC;
  signal lopt_38 : STD_LOGIC;
  signal lopt_39 : STD_LOGIC;
  signal lopt_4 : STD_LOGIC;
  signal lopt_40 : STD_LOGIC;
  signal lopt_41 : STD_LOGIC;
  signal lopt_42 : STD_LOGIC;
  signal lopt_43 : STD_LOGIC;
  signal lopt_44 : STD_LOGIC;
  signal lopt_45 : STD_LOGIC;
  signal lopt_46 : STD_LOGIC;
  signal lopt_47 : STD_LOGIC;
  signal lopt_48 : STD_LOGIC;
  signal lopt_49 : STD_LOGIC;
  signal lopt_5 : STD_LOGIC;
  signal lopt_50 : STD_LOGIC;
  signal lopt_51 : STD_LOGIC;
  signal lopt_52 : STD_LOGIC;
  signal lopt_53 : STD_LOGIC;
  signal lopt_54 : STD_LOGIC;
  signal lopt_55 : STD_LOGIC;
  signal lopt_6 : STD_LOGIC;
  signal lopt_7 : STD_LOGIC;
  signal lopt_8 : STD_LOGIC;
  signal lopt_9 : STD_LOGIC;
  signal \^mem_exception_taken\ : STD_LOGIC;
  signal mem_PipeRun_carry_and_n_1 : STD_LOGIC;
  signal mem_PipeRun_carry_and_n_2 : STD_LOGIC;
  signal mem_Sel_MEM_Res : STD_LOGIC;
  signal mem_Write_DCache : STD_LOGIC;
  signal mem_Write_DCache_i_1_n_0 : STD_LOGIC;
  signal \^mem_byte_access\ : STD_LOGIC;
  signal \^mem_databus_access\ : STD_LOGIC;
  signal \^mem_databus_write\ : STD_LOGIC;
  signal mem_delayslot_instr : STD_LOGIC;
  signal \^mem_doublet_access\ : STD_LOGIC;
  signal mem_exception_from_ex : STD_LOGIC;
  signal mem_exception_kind : STD_LOGIC_VECTOR ( 28 to 31 );
  signal mem_gpr_write : STD_LOGIC;
  signal mem_gpr_write_addr : STD_LOGIC_VECTOR ( 0 to 4 );
  signal mem_gpr_write_dbg : STD_LOGIC;
  signal mem_instr : STD_LOGIC_VECTOR ( 0 to 31 );
  signal mem_is_multi_or_load_instr : STD_LOGIC;
  signal mem_is_multi_or_load_instr0 : STD_LOGIC;
  signal mem_jump_taken : STD_LOGIC;
  signal mem_jump_taken0 : STD_LOGIC;
  signal mem_load_store_access : STD_LOGIC;
  signal mem_load_store_access0 : STD_LOGIC;
  signal mem_read_imm_reg : STD_LOGIC;
  signal mem_read_imm_reg_1 : STD_LOGIC;
  signal mem_valid_instr : STD_LOGIC;
  signal mem_wait_on_ready_N : STD_LOGIC;
  signal of_PVR_Select : STD_LOGIC_VECTOR ( 0 to 3 );
  attribute RTL_KEEP of of_PVR_Select : signal is "true";
  signal of_PipeRun_carry_1 : STD_LOGIC;
  signal of_PipeRun_carry_10 : STD_LOGIC;
  signal of_PipeRun_carry_2 : STD_LOGIC;
  signal of_PipeRun_carry_3 : STD_LOGIC;
  signal of_PipeRun_carry_4 : STD_LOGIC;
  signal of_PipeRun_carry_5 : STD_LOGIC;
  signal of_PipeRun_carry_6 : STD_LOGIC;
  signal of_PipeRun_carry_7 : STD_LOGIC;
  signal of_PipeRun_carry_9 : STD_LOGIC;
  signal of_PipeRun_for_ce : STD_LOGIC;
  attribute DIRECT_ENABLE : boolean;
  attribute DIRECT_ENABLE of of_PipeRun_for_ce : signal is std.standard.true;
  signal of_Sel_SPR_BTR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_BTR : signal is "true";
  signal of_Sel_SPR_EAR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_EAR : signal is "true";
  signal of_Sel_SPR_EDR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_EDR : signal is "true";
  signal of_Sel_SPR_ESR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_ESR : signal is "true";
  signal of_Sel_SPR_FSR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_FSR : signal is "true";
  signal of_Sel_SPR_MSR1 : STD_LOGIC;
  signal of_Sel_SPR_MSR88_out : STD_LOGIC;
  signal of_Sel_SPR_PVR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_PVR : signal is "true";
  signal of_Sel_SPR_SHR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_SHR : signal is "true";
  signal of_Sel_SPR_SLR : STD_LOGIC;
  attribute RTL_KEEP of of_Sel_SPR_SLR : signal is "true";
  signal \^of_gpr_op1_rd_addr\ : STD_LOGIC_VECTOR ( 0 to 4 );
  signal \^of_gpr_op3_rd_addr\ : STD_LOGIC_VECTOR ( 0 to 4 );
  signal \^of_imm_data\ : STD_LOGIC_VECTOR ( 0 to 15 );
  signal of_instr : STD_LOGIC_VECTOR ( 0 to 5 );
  signal of_next_ex_valid : STD_LOGIC;
  signal \^of_pause\ : STD_LOGIC;
  signal of_predecode : STD_LOGIC_VECTOR ( 0 to 10 );
  signal of_read_ex_write_op2_conflict_part1 : STD_LOGIC;
  signal of_read_ex_write_op3_conflict_part1 : STD_LOGIC;
  signal of_read_imm_reg_ii : STD_LOGIC;
  signal of_read_imm_reg_ii_i_2_n_0 : STD_LOGIC;
  signal of_read_mem_write_op1_conflict_part2 : STD_LOGIC;
  signal of_read_mem_write_op2_conflict_part1 : STD_LOGIC;
  signal of_read_mem_write_op3_conflict_part1 : STD_LOGIC;
  signal of_use_op2_s : STD_LOGIC;
  signal of_valid : STD_LOGIC;
  signal p_0_in123_in : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_1_in124_in : STD_LOGIC;
  signal p_1_in3_in : STD_LOGIC;
  signal p_213_in : STD_LOGIC;
  signal p_216_in : STD_LOGIC;
  signal p_227_in : STD_LOGIC;
  signal p_232_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC;
  signal p_9_in : STD_LOGIC;
  signal reset_bool_for_rst : STD_LOGIC;
  attribute DIRECT_RESET : boolean;
  attribute DIRECT_RESET of reset_bool_for_rst : signal is std.standard.true;
  signal use_Reg_Neg_DI1_out : STD_LOGIC;
  signal use_Reg_Neg_S3_out : STD_LOGIC;
  signal \^wb_halted\ : STD_LOGIC;
  signal \^wb_piperun_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^wb_byte_access\ : STD_LOGIC;
  signal wb_doublet_access : STD_LOGIC;
  signal wb_exception : STD_LOGIC;
  signal \^wb_gpr_wr_dbg\ : STD_LOGIC;
  signal wb_gpr_write_dbg0 : STD_LOGIC;
  signal wb_gpr_write_i : STD_LOGIC;
  signal wb_gpr_write_i0 : STD_LOGIC;
  signal wb_reset : STD_LOGIC;
  signal \^wb_valid_reg_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \LOCKSTEP_Master_Out[1]_INST_0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \LOCKSTEP_Master_Out[5]_INST_0\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \LOCKSTEP_Master_Out[7]_INST_0\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of M_AXI_DP_AWVALID_i_i_2 : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of Pause_Ack_i_1 : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \Performance_Debug_Control.dbg_freeze_nohalt_i_2\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \Performance_Debug_Control.dbg_stop_i_i_1\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of Trace_Exception_Taken_INST_0 : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of Trace_MB_Halted_INST_0 : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of Trace_Valid_Instr_INST_0 : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_14\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__53\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_1__98\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \Using_FPGA.Native_i_3__6\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of ex_mbar_sleep_i_2 : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of ex_mbar_stall_no_sleep_1_i_1 : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of ex_read_imm_reg_i_1 : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of ex_sleep_i_i_1 : label is "soft_lutpair56";
  attribute SOFT_HLUTNM of ex_suspend_i_i_1 : label is "soft_lutpair56";
  attribute KEEP : string;
  attribute KEEP of ex_valid_jump_reg : label is "yes";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of ex_valid_jump_reg : label is "no";
  attribute SOFT_HLUTNM of mem_Write_DCache_i_1 : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of sign_byte_inferred_i_1 : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of wb_exception_i_i_1 : label is "soft_lutpair47";
begin
  D(31 downto 0) <= \^d\(31 downto 0);
  \EX_ALU_Op_reg[0]_0\(1 downto 0) <= \^ex_alu_op_reg[0]_0\(1 downto 0);
  EX_ALU_Sel_Logic <= \^ex_alu_sel_logic\;
  EX_Fwd(0 to 31) <= \^ex_fwd\(0 to 31);
  \EX_Sext_Op_reg[0]_0\(1 downto 0) <= \^ex_sext_op_reg[0]_0\(1 downto 0);
  Hibernate <= \^hibernate\;
  LOCKSTEP_Master_Out(2 downto 0) <= \^lockstep_master_out\(2 downto 0);
  \Performance_Debug_Control.dbg_state_nohalt_reg\(159 downto 0) <= \^performance_debug_control.dbg_state_nohalt_reg\(159 downto 0);
  Sleep_Decode <= \^sleep_decode\;
  Suspend <= \^suspend\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \Using_FPGA.Native_0\ <= \^using_fpga.native_0\;
  \Using_FPGA.Native_1\ <= \^using_fpga.native_1\;
  ex_byte_access <= \^ex_byte_access\;
  ex_doublet_access <= \^ex_doublet_access\;
  ex_reverse_mem_access <= \^ex_reverse_mem_access\;
  ex_set_bip_reg_0 <= \^ex_set_bip_reg_0\;
  ex_use_carry <= \^ex_use_carry\;
  ex_valid <= \^ex_valid\;
  mem_Exception_Taken <= \^mem_exception_taken\;
  mem_byte_access <= \^mem_byte_access\;
  mem_databus_access <= \^mem_databus_access\;
  mem_databus_write <= \^mem_databus_write\;
  mem_doublet_access <= \^mem_doublet_access\;
  of_gpr_op1_rd_addr(0 to 4) <= \^of_gpr_op1_rd_addr\(0 to 4);
  of_gpr_op3_rd_addr(0 to 4) <= \^of_gpr_op3_rd_addr\(0 to 4);
  of_imm_data(0 to 15) <= \^of_imm_data\(0 to 15);
  of_pause <= \^of_pause\;
  of_pause_reg_0 <= of_PipeRun_for_ce;
  reset_bool_for_rst <= sync_reset;
  wb_Halted <= \^wb_halted\;
  wb_PipeRun_i_reg_0(0) <= \^wb_piperun_i_reg_0\(0);
  wb_byte_access <= \^wb_byte_access\;
  wb_gpr_wr_dbg <= \^wb_gpr_wr_dbg\;
  wb_valid_reg_0 <= \^wb_valid_reg_0\;
Dbg_Clean_Stop_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => Dbg_Clean_Stop0,
      Q => dbg_clean_stop,
      R => reset_bool_for_rst
    );
\EX_ALU_Op_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_64,
      Q => \^ex_alu_op_reg[0]_0\(1),
      R => reset_bool_for_rst
    );
\EX_ALU_Op_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_65,
      Q => \^ex_alu_op_reg[0]_0\(0),
      R => reset_bool_for_rst
    );
EX_CMP_Op_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_186,
      Q => ex_cmp_op,
      R => reset_bool_for_rst
    );
EX_SWAP_BYTE_Instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => p_2_in,
      Q => ex_swap_byte_instr,
      R => reset_bool_for_rst
    );
EX_SWAP_Instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_169,
      Q => ex_swap_instr,
      R => reset_bool_for_rst
    );
\EX_Sext_Op_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_176,
      Q => \^ex_sext_op_reg[0]_0\(1),
      R => reset_bool_for_rst
    );
\EX_Sext_Op_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_177,
      Q => \^ex_sext_op_reg[0]_0\(0),
      R => reset_bool_for_rst
    );
\EX_Shift_Op_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(9),
      Q => ex_shift_op(0),
      R => reset_bool_for_rst
    );
\EX_Shift_Op_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(10),
      Q => ex_shift_op(1),
      R => reset_bool_for_rst
    );
EX_Unsigned_Op_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_187,
      Q => ex_unsigned_op,
      R => reset_bool_for_rst
    );
EX_Use_Carry_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_188,
      Q => \^ex_use_carry\,
      R => reset_bool_for_rst
    );
IFetch_INST_0_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => reset_bool_for_rst,
      I1 => \ex_mbar_stall_no_sleep__0\,
      I2 => ex_mbar_sleep,
      I3 => if_missed_fetch_reg_0,
      I4 => \^wb_halted\,
      I5 => if_missed_fetch_reg_1,
      O => if_fetch_without_full_or_jump
    );
IFetch_INST_0_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"54000000"
    )
        port map (
      I0 => ex_jump_hold,
      I1 => ex_mbar_stall_no_sleep_1,
      I2 => ex_first_cycle,
      I3 => p_231_in,
      I4 => ex_mbar_decode,
      O => \ex_mbar_stall_no_sleep__0\
    );
\LOCKSTEP_Master_Out[1]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^mem_databus_access\,
      I1 => active_access_reg,
      O => \^lockstep_master_out\(2)
    );
\LOCKSTEP_Master_Out[5]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEAAA"
    )
        port map (
      I0 => if_missed_fetch_reg_1,
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I3 => wb_exception,
      I4 => if_missed_fetch_reg_0,
      O => \^lockstep_master_out\(1)
    );
\LOCKSTEP_Master_Out[7]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => \mem_pc_i_reg[0]_0\,
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      O => \^lockstep_master_out\(0)
    );
MEM_DataBus_Access_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA_2.ex_is_swx_instr_Inst_n_1\,
      Q => \^mem_databus_access\,
      R => '0'
    );
\MEM_DataBus_Addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(70),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(99),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(60),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(89),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(59),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(88),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(58),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(87),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(57),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(86),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(56),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(85),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(55),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(84),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(54),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(83),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(53),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(82),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(52),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(81),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(51),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(80),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(69),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(98),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(50),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(79),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(49),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(78),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(48),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(77),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(47),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(76),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(46),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(75),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(45),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(74),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(44),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(73),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(43),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(72),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(42),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(71),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(41),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(70),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(68),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(97),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(40),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(69),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(39),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(68),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(67),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(96),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(66),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(95),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(65),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(94),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(64),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(93),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(63),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(92),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(62),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(91),
      R => reset_bool_for_rst
    );
\MEM_DataBus_Addr_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(61),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(90),
      R => reset_bool_for_rst
    );
MEM_DataBus_Read_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \MEM_DataBus_Addr_reg[0]_0\(38),
      Q => mem_databus_read,
      R => reset_bool_for_rst
    );
MEM_DataBus_Write_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \^performance_debug_control.dbg_state_nohalt_reg\(100),
      Q => \^mem_databus_write\,
      R => reset_bool_for_rst
    );
MEM_Sel_MEM_Res_I_reg: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \Using_FPGA_2.ex_is_load_instr_Inst_n_3\,
      Q => mem_Sel_MEM_Res,
      S => reset_bool_for_rst
    );
M_AXI_DP_ARVALID_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F22"
    )
        port map (
      I0 => \Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1\,
      I1 => \^mem_databus_write\,
      I2 => M_AXI_DP_ARREADY,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(35),
      I4 => reset_bool_for_rst,
      O => MEM_DataBus_Write_reg_2
    );
M_AXI_DP_AWVALID_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F88"
    )
        port map (
      I0 => \Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1\,
      I1 => \^mem_databus_write\,
      I2 => M_AXI_DP_AWREADY,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(37),
      I4 => reset_bool_for_rst,
      O => MEM_DataBus_Write_reg_1
    );
M_AXI_DP_AWVALID_i_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => \^mem_databus_access\,
      I1 => DReady,
      I2 => DWait,
      I3 => active_access_d1,
      O => \Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1\
    );
M_AXI_DP_WVALID_i_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000F88"
    )
        port map (
      I0 => \Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1\,
      I1 => \^mem_databus_write\,
      I2 => M_AXI_DP_WREADY,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(36),
      I4 => reset_bool_for_rst,
      O => MEM_DataBus_Write_reg_0
    );
PC_Module_I: entity work.design_1_microblaze_0_0_PC_Module_gti
     port map (
      CI => if_pc_incr_carry3,
      Clk => Clk,
      D(31 downto 0) => \^d\(31 downto 0),
      E(0) => \Use_MuxCy[3].OF_Piperun_Stage_n_1\,
      IB_Ready => IB_Ready,
      IReady => IReady,
      O => O87_out,
      O56_out => O56_out,
      Q(1 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(3 downto 2),
      \Using_FPGA.Native\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_0\ => PreFetch_Buffer_I1_n_3,
      ex_jump_nodelay_reg => \Using_FPGA.Native_41\,
      ex_jump_nodelay_reg_0 => \mem_pc_i_reg[0]_0\,
      \ex_pc_i_reg[31]_0\ => of_PipeRun_for_ce,
      \if_pc_reg[0]_0\(0) => IF_PC_Write,
      \if_pc_reg[0]_1\(31 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(156 downto 125),
      \if_pc_reg[10]_0\ => O49_out,
      \if_pc_reg[11]_0\ => O51_out,
      \if_pc_reg[12]_0\ => O53_out,
      \if_pc_reg[13]_0\ => O55_out,
      \if_pc_reg[14]_0\ => O57_out,
      \if_pc_reg[15]_0\ => O59_out,
      \if_pc_reg[16]_0\ => O61_out,
      \if_pc_reg[17]_0\ => O63_out,
      \if_pc_reg[18]_0\ => O65_out,
      \if_pc_reg[19]_0\ => O67_out,
      \if_pc_reg[1]_0\ => O31_out,
      \if_pc_reg[20]_0\ => O69_out,
      \if_pc_reg[21]_0\ => O71_out,
      \if_pc_reg[22]_0\ => O73_out,
      \if_pc_reg[23]_0\ => O75_out,
      \if_pc_reg[24]_0\ => O77_out,
      \if_pc_reg[25]_0\ => O79_out,
      \if_pc_reg[26]_0\ => O81_out,
      \if_pc_reg[27]_0\ => O83_out,
      \if_pc_reg[28]_0\ => O85_out,
      \if_pc_reg[2]_0\ => O33_out,
      \if_pc_reg[30]_0\(1) => p_1_in3_in,
      \if_pc_reg[30]_0\(0) => PC_Module_I_n_35,
      \if_pc_reg[3]_0\ => O35_out,
      \if_pc_reg[4]_0\ => O37_out,
      \if_pc_reg[5]_0\ => O39_out,
      \if_pc_reg[6]_0\ => O41_out,
      \if_pc_reg[7]_0\ => O43_out,
      \if_pc_reg[8]_0\ => O45_out,
      \if_pc_reg[9]_0\ => O47_out,
      if_pre_buffer_addr(0) => if_pre_buffer_addr(1),
      if_sel_input(1) => if_sel_input(0),
      if_sel_input(0) => if_sel_input(4),
      lopt => lopt_7,
      lopt_1 => lopt_8,
      lopt_10 => lopt_37,
      lopt_11 => lopt_38,
      lopt_12 => lopt_39,
      lopt_13 => lopt_40,
      lopt_14 => lopt_41,
      lopt_15 => lopt_42,
      lopt_16 => lopt_43,
      lopt_17 => lopt_44,
      lopt_18 => lopt_45,
      lopt_19 => lopt_46,
      lopt_2 => lopt_9,
      lopt_3 => lopt_10,
      lopt_4 => lopt_31,
      lopt_5 => lopt_32,
      lopt_6 => lopt_33,
      lopt_7 => lopt_34,
      lopt_8 => lopt_35,
      lopt_9 => lopt_36,
      \mem_pc_i_reg[0]_0\(31 downto 0) => \mem_pc_i_reg[0]\(31 downto 0),
      sync_reset => reset_bool_for_rst,
      wb_exception => wb_exception
    );
Pause_Ack_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \^of_pause\,
      I1 => mem_valid_instr,
      I2 => if_fetch_in_progress,
      O => Pause_Ack0
    );
Pause_Ack_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Pause_Ack0,
      Q => Pause_Ack,
      R => reset_bool_for_rst
    );
\Performance_Debug_Control.dbg_brki_hit_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I2 => wb_exception,
      O => \^wb_halted\
    );
\Performance_Debug_Control.dbg_freeze_nohalt_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => wb_exception,
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0\,
      O => \p_4_out__0\
    );
\Performance_Debug_Control.dbg_stop_i_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF80"
    )
        port map (
      I0 => wb_exception,
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => reset_bool_for_rst,
      O => dbg_stop_i
    );
\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6666FFF0"
    )
        port map (
      I0 => Reset_Mode(0),
      I1 => Reset_Mode(1),
      I2 => \^wb_halted\,
      I3 => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0\,
      I4 => reset_bool_for_rst,
      O => dbg_halt_reset_mode_reg
    );
PreFetch_Buffer_I1: entity work.design_1_microblaze_0_0_PreFetch_Buffer_gti
     port map (
      Clk => Clk,
      D(1) => \^of_gpr_op3_rd_addr\(0),
      D(0) => \^of_gpr_op3_rd_addr\(1),
      D224_out => D224_out,
      Dbg_Clean_Stop0 => Dbg_Clean_Stop0,
      E(0) => \^using_fpga.native_1\,
      EX_Is_Div_Instr => EX_Is_Div_Instr,
      \EX_Op1_reg[0]\(31 downto 0) => \^d\(31 downto 0),
      \EX_Op2_reg[0]\(15 downto 0) => \EX_Op2_reg[0]\(15 downto 0),
      \EX_Op2_reg[0]_0\ => ex_read_imm_reg_i_1_n_0,
      \EX_Op2_reg[0]_1\ => \^ex_fwd\(0),
      \EX_Op2_reg[0]_2\ => \^performance_debug_control.dbg_state_nohalt_reg\(28),
      \EX_Op2_reg[10]\ => \^ex_fwd\(10),
      \EX_Op2_reg[10]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(18),
      \EX_Op2_reg[11]\ => \^ex_fwd\(11),
      \EX_Op2_reg[11]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(17),
      \EX_Op2_reg[12]\ => \^ex_fwd\(12),
      \EX_Op2_reg[12]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(16),
      \EX_Op2_reg[13]\ => \^ex_fwd\(13),
      \EX_Op2_reg[13]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(15),
      \EX_Op2_reg[14]\ => \^ex_fwd\(14),
      \EX_Op2_reg[14]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(14),
      \EX_Op2_reg[15]\ => \^ex_fwd\(15),
      \EX_Op2_reg[15]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(13),
      \EX_Op2_reg[16]\(7 downto 0) => \MEM_DataBus_Addr_reg[0]_0\(7 downto 0),
      \EX_Op2_reg[16]_0\ => \^ex_fwd\(16),
      \EX_Op2_reg[17]\ => \^ex_fwd\(17),
      \EX_Op2_reg[18]\ => \^ex_fwd\(18),
      \EX_Op2_reg[19]\ => \^ex_fwd\(19),
      \EX_Op2_reg[1]\ => \^ex_fwd\(1),
      \EX_Op2_reg[1]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(27),
      \EX_Op2_reg[20]\ => \^ex_fwd\(20),
      \EX_Op2_reg[21]\ => \^ex_fwd\(21),
      \EX_Op2_reg[22]\ => \^ex_fwd\(22),
      \EX_Op2_reg[23]\ => \^ex_fwd\(23),
      \EX_Op2_reg[24]\ => \^ex_fwd\(24),
      \EX_Op2_reg[24]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(12),
      \EX_Op2_reg[25]\ => \^ex_fwd\(25),
      \EX_Op2_reg[25]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(11),
      \EX_Op2_reg[26]\ => \^ex_fwd\(26),
      \EX_Op2_reg[26]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(10),
      \EX_Op2_reg[27]\ => \^ex_fwd\(27),
      \EX_Op2_reg[27]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(9),
      \EX_Op2_reg[28]\ => \^ex_fwd\(28),
      \EX_Op2_reg[28]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(8),
      \EX_Op2_reg[29]\ => \^ex_fwd\(29),
      \EX_Op2_reg[29]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(7),
      \EX_Op2_reg[2]\ => \^ex_fwd\(2),
      \EX_Op2_reg[2]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(26),
      \EX_Op2_reg[30]\ => \^ex_fwd\(30),
      \EX_Op2_reg[30]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(6),
      \EX_Op2_reg[31]\ => \^ex_fwd\(31),
      \EX_Op2_reg[31]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(5),
      \EX_Op2_reg[3]\ => \^ex_fwd\(3),
      \EX_Op2_reg[3]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(25),
      \EX_Op2_reg[4]\ => \^ex_fwd\(4),
      \EX_Op2_reg[4]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(24),
      \EX_Op2_reg[5]\ => \^ex_fwd\(5),
      \EX_Op2_reg[5]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(23),
      \EX_Op2_reg[6]\ => \^ex_fwd\(6),
      \EX_Op2_reg[6]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(22),
      \EX_Op2_reg[7]\ => \^ex_fwd\(7),
      \EX_Op2_reg[7]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(21),
      \EX_Op2_reg[8]\ => \^ex_fwd\(8),
      \EX_Op2_reg[8]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(20),
      \EX_Op2_reg[9]\ => \^ex_fwd\(9),
      \EX_Op2_reg[9]_0\ => \^performance_debug_control.dbg_state_nohalt_reg\(19),
      \EX_Op3[0]_i_2\ => \^performance_debug_control.dbg_state_nohalt_reg\(34),
      \EX_Op3[0]_i_6\ => \ex_gpr_write_addr_reg_n_0_[4]\,
      GPR_Op1(0 to 31) => GPR_Op1(0 to 31),
      GPR_Op2(0 to 31) => GPR_Op2(0 to 31),
      GPR_Op3(0 to 31) => GPR_Op3(0 to 31),
      I0 => I0,
      I139_out => I139_out,
      I1_0 => I1_0,
      I4 => I4,
      I5 => I5,
      IB_Ready => IB_Ready,
      IReady => IReady,
      IReady_0 => PreFetch_Buffer_I1_n_3,
      MEM_Fwd(0 to 31) => MEM_Fwd(0 to 31),
      \Performance_Debug_Control.ex_brki_hit_reg\(0) => Q(0),
      Q(1 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(3 downto 2),
      \Serial_Dbg_Intf.control_reg_reg[8]\ => \Serial_Dbg_Intf.control_reg_reg[8]\,
      \Using_FPGA.Native\(1) => if_sel_input(0),
      \Using_FPGA.Native\(0) => if_sel_input(4),
      \Using_FPGA.Native_0\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_1\ => \^of_gpr_op3_rd_addr\(2),
      \Using_FPGA.Native_10\ => PreFetch_Buffer_I1_n_66,
      \Using_FPGA.Native_11\(0) => E(0),
      \Using_FPGA.Native_12\ => PreFetch_Buffer_I1_n_169,
      \Using_FPGA.Native_13\ => PreFetch_Buffer_I1_n_173,
      \Using_FPGA.Native_14\(1) => PreFetch_Buffer_I1_n_176,
      \Using_FPGA.Native_14\(0) => PreFetch_Buffer_I1_n_177,
      \Using_FPGA.Native_15\ => PreFetch_Buffer_I1_n_178,
      \Using_FPGA.Native_16\ => PreFetch_Buffer_I1_n_179,
      \Using_FPGA.Native_17\ => PreFetch_Buffer_I1_n_182,
      \Using_FPGA.Native_18\ => PreFetch_Buffer_I1_n_185,
      \Using_FPGA.Native_19\ => PreFetch_Buffer_I1_n_186,
      \Using_FPGA.Native_2\ => \^of_gpr_op3_rd_addr\(3),
      \Using_FPGA.Native_20\ => PreFetch_Buffer_I1_n_187,
      \Using_FPGA.Native_21\ => PreFetch_Buffer_I1_n_188,
      \Using_FPGA.Native_22\ => PreFetch_Buffer_I1_n_189,
      \Using_FPGA.Native_23\ => PreFetch_Buffer_I1_n_191,
      \Using_FPGA.Native_24\ => \Using_FPGA.Native_2\,
      \Using_FPGA.Native_25\ => PreFetch_Buffer_I1_n_193,
      \Using_FPGA.Native_26\ => PreFetch_Buffer_I1_n_194,
      \Using_FPGA.Native_27\ => PreFetch_Buffer_I1_n_195,
      \Using_FPGA.Native_28\ => \Using_FPGA.Native_3\,
      \Using_FPGA.Native_29\ => \Using_FPGA.Native_4\,
      \Using_FPGA.Native_3\ => \^of_gpr_op3_rd_addr\(4),
      \Using_FPGA.Native_30\ => \Using_FPGA.Native_5\,
      \Using_FPGA.Native_31\ => \Using_FPGA.Native_6\,
      \Using_FPGA.Native_32\ => \Using_FPGA.Native_7\,
      \Using_FPGA.Native_33\ => \Using_FPGA.Native_8\,
      \Using_FPGA.Native_34\ => \Using_FPGA.Native_9\,
      \Using_FPGA.Native_35\ => \Using_FPGA.Native_10\,
      \Using_FPGA.Native_36\ => \Using_FPGA.Native_11\,
      \Using_FPGA.Native_37\ => \Using_FPGA.Native_12\,
      \Using_FPGA.Native_38\ => \Using_FPGA.Native_13\,
      \Using_FPGA.Native_39\ => \Using_FPGA.Native_14\,
      \Using_FPGA.Native_4\(20) => \^of_gpr_op1_rd_addr\(0),
      \Using_FPGA.Native_4\(19) => \^of_gpr_op1_rd_addr\(1),
      \Using_FPGA.Native_4\(18) => \^of_gpr_op1_rd_addr\(2),
      \Using_FPGA.Native_4\(17) => \^of_gpr_op1_rd_addr\(3),
      \Using_FPGA.Native_4\(16) => \^of_gpr_op1_rd_addr\(4),
      \Using_FPGA.Native_4\(15) => \^of_imm_data\(0),
      \Using_FPGA.Native_4\(14) => \^of_imm_data\(1),
      \Using_FPGA.Native_4\(13) => \^of_imm_data\(2),
      \Using_FPGA.Native_4\(12) => \^of_imm_data\(3),
      \Using_FPGA.Native_4\(11) => \^of_imm_data\(4),
      \Using_FPGA.Native_4\(10) => \^of_imm_data\(5),
      \Using_FPGA.Native_4\(9) => \^of_imm_data\(6),
      \Using_FPGA.Native_4\(8) => \^of_imm_data\(7),
      \Using_FPGA.Native_4\(7) => \^of_imm_data\(8),
      \Using_FPGA.Native_4\(6) => \^of_imm_data\(9),
      \Using_FPGA.Native_4\(5) => \^of_imm_data\(10),
      \Using_FPGA.Native_4\(4) => \^of_imm_data\(11),
      \Using_FPGA.Native_4\(3) => \^of_imm_data\(12),
      \Using_FPGA.Native_4\(2) => \^of_imm_data\(13),
      \Using_FPGA.Native_4\(1) => \^of_imm_data\(14),
      \Using_FPGA.Native_4\(0) => \^of_imm_data\(15),
      \Using_FPGA.Native_40\ => \Using_FPGA.Native_15\,
      \Using_FPGA.Native_41\ => \Using_FPGA.Native_16\,
      \Using_FPGA.Native_42\ => \Using_FPGA.Native_17\,
      \Using_FPGA.Native_43\ => \Using_FPGA.Native_18\,
      \Using_FPGA.Native_44\ => \Using_FPGA.Native_19\,
      \Using_FPGA.Native_45\ => \Using_FPGA.Native_20\,
      \Using_FPGA.Native_46\ => \Using_FPGA.Native_21\,
      \Using_FPGA.Native_47\ => \Using_FPGA.Native_22\,
      \Using_FPGA.Native_48\ => \Using_FPGA.Native_23\,
      \Using_FPGA.Native_49\ => \Using_FPGA.Native_24\,
      \Using_FPGA.Native_5\ => PreFetch_Buffer_I1_n_48,
      \Using_FPGA.Native_50\ => \Using_FPGA.Native_25\,
      \Using_FPGA.Native_51\ => \Using_FPGA.Native_26\,
      \Using_FPGA.Native_52\ => \Using_FPGA.Native_27\,
      \Using_FPGA.Native_53\ => \Using_FPGA.Native_28\,
      \Using_FPGA.Native_54\ => \Using_FPGA.Native_29\,
      \Using_FPGA.Native_55\ => \Using_FPGA.Native_30\,
      \Using_FPGA.Native_56\ => \Using_FPGA.Native_31\,
      \Using_FPGA.Native_57\ => \Using_FPGA.Native_32\,
      \Using_FPGA.Native_58\ => \Using_FPGA.Native_33\,
      \Using_FPGA.Native_59\(0) => \Using_FPGA.Native_34\(0),
      \Using_FPGA.Native_6\(1 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(158 downto 157),
      \Using_FPGA.Native_60\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_61\ => \mem_pc_i_reg[0]_0\,
      \Using_FPGA.Native_62\ => \Using_FPGA.Native_41\,
      \Using_FPGA.Native_7\ => PreFetch_Buffer_I1_n_56,
      \Using_FPGA.Native_8\ => PreFetch_Buffer_I1_n_59,
      \Using_FPGA.Native_9\(1) => PreFetch_Buffer_I1_n_64,
      \Using_FPGA.Native_9\(0) => PreFetch_Buffer_I1_n_65,
      \Using_FPGA.Native_i_5__0\(4) => mem_gpr_write_addr(0),
      \Using_FPGA.Native_i_5__0\(3) => mem_gpr_write_addr(1),
      \Using_FPGA.Native_i_5__0\(2) => mem_gpr_write_addr(2),
      \Using_FPGA.Native_i_5__0\(1) => mem_gpr_write_addr(3),
      \Using_FPGA.Native_i_5__0\(0) => mem_gpr_write_addr(4),
      \Using_FPGA.Native_i_5__0_0\(4 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(33 downto 29),
      \Using_FPGA.Native_i_5__0_1\(1) => \ex_gpr_write_addr_reg_n_0_[0]\,
      \Using_FPGA.Native_i_5__0_1\(0) => I2,
      ex_MSR(2 downto 0) => ex_MSR(2 downto 0),
      ex_branch_with_delayslot => ex_branch_with_delayslot,
      ex_branch_with_delayslot_i_reg_0 => \^wb_halted\,
      ex_branch_with_delayslot_reg => PreFetch_Buffer_I1_n_190,
      ex_enable_sext_shift_i0 => ex_enable_sext_shift_i0,
      \ex_gpr_write_dbg__0\ => \ex_gpr_write_dbg__0\,
      ex_gpr_write_reg => PreFetch_Buffer_I1_n_49,
      ex_gpr_write_reg_0 => ex_gpr_write_reg_n_0,
      ex_is_div_instr_I_reg => PreFetch_Buffer_I1_n_50,
      ex_is_multi_or_load_instr0 => ex_is_multi_or_load_instr0,
      ex_jump => ex_jump,
      ex_jump_nodelay => ex_jump_nodelay,
      ex_jump_q => ex_jump_q,
      ex_load_shift_carry0 => ex_load_shift_carry0,
      ex_mbar_decode => ex_mbar_decode,
      ex_mbar_decode_cmb => ex_mbar_decode_cmb,
      ex_mbar_is_sleep => ex_mbar_is_sleep,
      ex_mbar_is_sleep_cmb => ex_mbar_is_sleep_cmb,
      ex_move_to_MSR_instr93_out => ex_move_to_MSR_instr93_out,
      ex_op1_cmp_eq1 => ex_op1_cmp_eq1,
      ex_op1_cmp_eq_n5_out => ex_op1_cmp_eq_n5_out,
      ex_sel_alu_i0 => ex_sel_alu_i0,
      ex_sel_alu_i_reg(31 downto 0) => ex_sel_alu_i_reg_0(31 downto 0),
      ex_sel_alu_i_reg_0(31 downto 0) => ex_sel_alu_i_reg_1(31 downto 0),
      ex_sel_alu_i_reg_1(31 downto 0) => ex_sel_alu_i_reg_2(31 downto 0),
      ex_set_bip => ex_set_bip,
      force12_out => force12_out,
      force_Val10_out => force_Val10_out,
      if_fetch_for_timing_optimization1 => if_fetch_for_timing_optimization1,
      if_fetch_in_progress => if_fetch_in_progress,
      if_fetch_in_progress_reg(0) => IF_PC_Write,
      if_missed_fetch => if_missed_fetch,
      if_missed_fetch_reg => PreFetch_Buffer_I1_n_183,
      if_pre_buffer_addr(0) => if_pre_buffer_addr(1),
      \in\(32) => Y(0),
      \in\(31) => Y(1),
      \in\(30) => Y(2),
      \in\(29) => Y(3),
      \in\(28) => Y(4),
      \in\(27) => Y(5),
      \in\(26) => Y(6),
      \in\(25) => Y(7),
      \in\(24) => Y(8),
      \in\(23) => Y(9),
      \in\(22) => Y(10),
      \in\(21) => Y(21),
      \in\(20) => Y(22),
      \in\(19) => Y(23),
      \in\(18) => Y(24),
      \in\(17) => Y(25),
      \in\(16) => Y(26),
      \in\(15) => Y(27),
      \in\(14) => Y(28),
      \in\(13) => Y(29),
      \in\(12) => Y(30),
      \in\(11) => Y(31),
      \in\(10) => \in\(0),
      \in\(9) => Y(11),
      \in\(8) => Y(12),
      \in\(7) => Y(13),
      \in\(6) => Y(14),
      \in\(5) => Y(15),
      \in\(4) => Y(16),
      \in\(3) => Y(17),
      \in\(2) => Y(18),
      \in\(1) => Y(19),
      \in\(0) => Y(20),
      in0 => if_fetch_without_full_or_jump,
      mem_gpr_write => mem_gpr_write,
      mem_valid_instr => mem_valid_instr,
      of_Sel_SPR_MSR1 => of_Sel_SPR_MSR1,
      of_Sel_SPR_MSR88_out => of_Sel_SPR_MSR88_out,
      of_instr(5) => of_instr(0),
      of_instr(4) => of_instr(1),
      of_instr(3) => of_instr(2),
      of_instr(2) => of_instr(3),
      of_instr(1) => of_instr(4),
      of_instr(0) => of_instr(5),
      of_op1_sel_spr => of_op1_sel_spr,
      of_predecode(0 to 10) => of_predecode(0 to 10),
      of_use_op2_s => of_use_op2_s,
      of_valid => of_valid,
      \out\ => if_fetch_without_full_or_jump,
      p_213_in => p_213_in,
      p_216_in => p_216_in,
      p_2_in => p_2_in,
      p_9_in => p_9_in,
      sync_reset => reset_bool_for_rst,
      use_Reg_Neg_DI1_out => use_Reg_Neg_DI1_out,
      use_Reg_Neg_S3_out => use_Reg_Neg_S3_out,
      wb_exception => wb_exception,
      wb_exception_i_reg => PreFetch_Buffer_I1_n_184
    );
Sleep_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^sleep_decode\,
      I1 => Sleep_Out,
      O => Sleep
    );
Trace_Exception_Taken_INST_0: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => wb_exception,
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(4)
    );
Trace_MB_Halted_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => if_missed_fetch_reg_0,
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(159)
    );
\Trace_New_Reg_Value[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(23),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3007]_0\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(23),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(28)
    );
\Trace_New_Reg_Value[10]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(13),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3017]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(13),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(18)
    );
\Trace_New_Reg_Value[11]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(12),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3018]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(12),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(17)
    );
\Trace_New_Reg_Value[12]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(11),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3019]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(11),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(16)
    );
\Trace_New_Reg_Value[13]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(10),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3020]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(10),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(15)
    );
\Trace_New_Reg_Value[14]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(9),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3021]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(9),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(14)
    );
\Trace_New_Reg_Value[15]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(8),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3022]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(8),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(13)
    );
\Trace_New_Reg_Value[1]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(22),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3008]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(22),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(27)
    );
\Trace_New_Reg_Value[24]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(7),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(7),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(7),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(12)
    );
\Trace_New_Reg_Value[25]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(6),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(6),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(6),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(11)
    );
\Trace_New_Reg_Value[26]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(5),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(5),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(5),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(10)
    );
\Trace_New_Reg_Value[27]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(4),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(4),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(4),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(9)
    );
\Trace_New_Reg_Value[28]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(3),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(3),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(3),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(8)
    );
\Trace_New_Reg_Value[29]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(2),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(2),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(2),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(7)
    );
\Trace_New_Reg_Value[2]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(21),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3009]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(21),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(26)
    );
\Trace_New_Reg_Value[30]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(1),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(1),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(1),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(6)
    );
\Trace_New_Reg_Value[31]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FBBBFBBBFBBB0888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(0),
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => wb_databus_steered_read_data(0),
      I5 => \LOCKSTEP_Out_reg[3007]_1\(0),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(5)
    );
\Trace_New_Reg_Value[3]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(20),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3010]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(20),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(25)
    );
\Trace_New_Reg_Value[4]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(19),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3011]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(19),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(24)
    );
\Trace_New_Reg_Value[5]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(18),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3012]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(18),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(23)
    );
\Trace_New_Reg_Value[6]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(17),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3013]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(17),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(22)
    );
\Trace_New_Reg_Value[7]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(16),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3014]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(16),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(21)
    );
\Trace_New_Reg_Value[8]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(15),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3015]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(15),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(20)
    );
\Trace_New_Reg_Value[9]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBBBBBBB888B8888"
    )
        port map (
      I0 => \LOCKSTEP_Out_reg[3007]\(14),
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(4),
      I2 => wb_doublet_access,
      I3 => \^wb_byte_access\,
      I4 => \LOCKSTEP_Out_reg[3016]\,
      I5 => \LOCKSTEP_Out_reg[3007]_1\(14),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(19)
    );
Trace_Reg_Write_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AEAA"
    )
        port map (
      I0 => wb_reset,
      I1 => \^wb_valid_reg_0\,
      I2 => wb_exception,
      I3 => wb_gpr_write_i,
      O => \^performance_debug_control.dbg_state_nohalt_reg\(34)
    );
Trace_Valid_Instr_INST_0: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAA"
    )
        port map (
      I0 => \^wb_valid_reg_0\,
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      O => \^performance_debug_control.dbg_state_nohalt_reg\(35)
    );
Trace_WB_Jump_Taken_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_jump_taken,
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(1),
      R => reset_bool_for_rst
    );
\Use_MuxCy[10].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and
     port map (
      lopt => lopt_29,
      lopt_1 => lopt_30,
      of_PipeRun_carry_1 => of_PipeRun_carry_1,
      of_PipeRun_carry_2 => of_PipeRun_carry_2,
      use_Reg_Neg_S_reg => \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0\
    );
\Use_MuxCy[11].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_57
     port map (
      E(0) => \^using_fpga.native_1\,
      IB_Ready => IB_Ready,
      ex_jump => ex_jump,
      ex_jump_nodelay => ex_jump_nodelay,
      ex_jump_nodelay_reg => \Use_MuxCy[11].OF_Piperun_Stage_n_1\,
      ex_jump_nodelay_reg_0 => PreFetch_Buffer_I1_n_48,
      if_missed_fetch => if_missed_fetch,
      lopt => lopt_53,
      lopt_1 => lopt_54,
      lopt_2 => lopt_55,
      of_PipeRun_carry_1 => of_PipeRun_carry_1,
      of_PipeRun_for_ce => of_PipeRun_for_ce,
      of_pause => \^of_pause\,
      of_read_imm_reg_ii => of_read_imm_reg_ii,
      of_read_imm_reg_ii_reg => \Use_MuxCy[11].OF_Piperun_Stage_n_2\,
      of_read_imm_reg_ii_reg_0 => of_read_imm_reg_ii_i_2_n_0,
      p_9_in => p_9_in,
      sync_reset => reset_bool_for_rst,
      wb_exception => wb_exception,
      wb_exception_i_reg => \Use_MuxCy[11].OF_Piperun_Stage_n_3\,
      wb_exception_i_reg_0 => \Use_MuxCy[11].OF_Piperun_Stage_n_4\
    );
\Use_MuxCy[1].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_58
     port map (
      \Using_FPGA.Native\ => \^using_fpga.native_0\,
      lopt => lopt_14,
      lopt_1 => lopt_15,
      lopt_2 => lopt_16,
      of_PipeRun_carry_10 => of_PipeRun_carry_10
    );
\Use_MuxCy[2].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_59
     port map (
      \EX_MBAR_Stall__1\ => \EX_MBAR_Stall__1\,
      \Using_FPGA.Native\ => jump_logic_I1_n_42,
      ex_first_cycle => ex_first_cycle,
      ex_jump_hold => ex_jump_hold,
      ex_mbar_decode => ex_mbar_decode,
      ex_mbar_sleep => ex_mbar_sleep,
      ex_mbar_stall_no_sleep_1 => ex_mbar_stall_no_sleep_1,
      lopt => lopt_17,
      lopt_1 => lopt_18,
      of_PipeRun_carry_10 => of_PipeRun_carry_10,
      of_PipeRun_carry_9 => of_PipeRun_carry_9
    );
\Use_MuxCy[3].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_60
     port map (
      E(0) => \^using_fpga.native_1\,
      Q(1 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(3 downto 2),
      ex_Write_DCache_decode_reg => of_PipeRun_for_ce,
      ex_Write_ICache_i => ex_Write_ICache_i,
      ex_Write_ICache_i_cmb => ex_Write_ICache_i_cmb,
      ex_write_dcache_instr => ex_write_dcache_instr,
      in0 => ex_Write_DCache_decode_cmb,
      lopt => lopt_19,
      lopt_1 => lopt_20,
      lopt_10 => lopt_48,
      lopt_11 => lopt_49,
      lopt_12 => lopt_50,
      lopt_13 => lopt_51,
      lopt_14 => lopt_52,
      lopt_2 => PreFetch_Buffer_I1_n_191,
      lopt_3 => lopt_21,
      lopt_4 => lopt_22,
      lopt_5 => A,
      lopt_6 => lopt_23,
      lopt_7 => lopt_24,
      lopt_8 => \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0\,
      lopt_9 => lopt_47,
      \mem_pc_i_reg[0]\ => \mem_pc_i_reg[0]_0\,
      of_PipeRun_carry_9 => of_PipeRun_carry_9,
      wb_exception => wb_exception,
      \wb_exception_kind_i_reg[28]\(0) => \Use_MuxCy[3].OF_Piperun_Stage_n_1\
    );
\Use_MuxCy[4].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_61
     port map (
      E(0) => \^using_fpga.native_1\,
      \Using_FPGA.Native\ => PreFetch_Buffer_I1_n_191,
      lopt => lopt_19,
      lopt_1 => lopt_20,
      of_PipeRun_carry_7 => of_PipeRun_carry_7
    );
\Use_MuxCy[5].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_62
     port map (
      A => A,
      lopt => lopt_21,
      lopt_1 => lopt_22,
      of_PipeRun_carry_6 => of_PipeRun_carry_6,
      of_PipeRun_carry_7 => of_PipeRun_carry_7
    );
\Use_MuxCy[6].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_63
     port map (
      \Using_FPGA.Native\ => \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0\,
      lopt => lopt_23,
      lopt_1 => lopt_24,
      of_PipeRun_carry_5 => of_PipeRun_carry_5,
      of_PipeRun_carry_6 => of_PipeRun_carry_6
    );
\Use_MuxCy[7].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_64
     port map (
      \Using_FPGA.Native\ => \Using_FPGA_4.of_read_ex_write_op2_conflict_INST2_n_0\,
      lopt => lopt_25,
      lopt_1 => lopt_26,
      lopt_10 => lopt_54,
      lopt_11 => lopt_55,
      lopt_2 => \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0\,
      lopt_3 => lopt_27,
      lopt_4 => lopt_28,
      lopt_5 => \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0\,
      lopt_6 => lopt_29,
      lopt_7 => lopt_30,
      lopt_8 => \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0\,
      lopt_9 => lopt_53,
      of_PipeRun_carry_4 => of_PipeRun_carry_4,
      of_PipeRun_carry_5 => of_PipeRun_carry_5
    );
\Use_MuxCy[8].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_65
     port map (
      \Using_FPGA.Native\ => \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0\,
      lopt => lopt_25,
      lopt_1 => lopt_26,
      of_PipeRun_carry_3 => of_PipeRun_carry_3,
      of_PipeRun_carry_4 => of_PipeRun_carry_4
    );
\Use_MuxCy[9].OF_Piperun_Stage\: entity work.design_1_microblaze_0_0_carry_and_66
     port map (
      \Using_FPGA.Native\ => \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0\,
      lopt => lopt_27,
      lopt_1 => lopt_28,
      of_PipeRun_carry_2 => of_PipeRun_carry_2,
      of_PipeRun_carry_3 => of_PipeRun_carry_3
    );
\Using_FPGA.Gen_Bits[28].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE
     port map (
      Clk => Clk,
      D(0) => mem_exception_kind(28),
      E(0) => \^using_fpga.native_1\,
      ex_exception_no_load_store_mask => ex_exception_no_load_store_mask,
      mem_exception_from_ex => mem_exception_from_ex,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA.Gen_Bits[31].MEM_EX_Result_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_67
     port map (
      Clk => Clk,
      D(0) => mem_exception_kind(31),
      E(0) => \^using_fpga.native_1\,
      ex_exception_no_load_store_mask => ex_exception_no_load_store_mask,
      mem_exception_from_ex => mem_exception_from_ex,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA.Native_i_11\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => mem_gpr_write,
      I1 => mem_valid_instr,
      O => p_213_in
    );
\Using_FPGA.Native_i_14\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => ex_gpr_write_reg_n_0,
      I1 => \^ex_valid\,
      O => p_216_in
    );
\Using_FPGA.Native_i_1__52\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => reset_bool_for_rst,
      I1 => EX_Is_Div_Instr,
      O => R
    );
\Using_FPGA.Native_i_1__53\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      O => I1
    );
\Using_FPGA.Native_i_1__59\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \^ex_alu_op_reg[0]_0\(0),
      I1 => \^ex_alu_sel_logic\,
      I2 => \^ex_alu_op_reg[0]_0\(1),
      I3 => \^ex_use_carry\,
      O => DI
    );
\Using_FPGA.Native_i_1__60\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => ex_databus_addr(0),
      I1 => ex_sel_alu,
      I2 => swap_result(0),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O\,
      O => \^ex_fwd\(31)
    );
\Using_FPGA.Native_i_1__61\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => ex_databus_addr(1),
      I1 => ex_sel_alu,
      I2 => swap_result(1),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O31_out\,
      O => \^ex_fwd\(30)
    );
\Using_FPGA.Native_i_1__62\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(41),
      I1 => ex_sel_alu,
      I2 => swap_result(2),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O30_out\,
      O => \^ex_fwd\(29)
    );
\Using_FPGA.Native_i_1__63\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(42),
      I1 => ex_sel_alu,
      I2 => swap_result(3),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O29_out\,
      O => \^ex_fwd\(28)
    );
\Using_FPGA.Native_i_1__64\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(43),
      I1 => ex_sel_alu,
      I2 => swap_result(4),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O28_out\,
      O => \^ex_fwd\(27)
    );
\Using_FPGA.Native_i_1__65\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(44),
      I1 => ex_sel_alu,
      I2 => swap_result(5),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O27_out\,
      O => \^ex_fwd\(26)
    );
\Using_FPGA.Native_i_1__66\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(45),
      I1 => ex_sel_alu,
      I2 => swap_result(6),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O26_out\,
      O => \^ex_fwd\(25)
    );
\Using_FPGA.Native_i_1__67\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(46),
      I1 => ex_sel_alu,
      I2 => swap_result(7),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O24_out\,
      O => \^ex_fwd\(24)
    );
\Using_FPGA.Native_i_1__68\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(47),
      I1 => ex_sel_alu,
      I2 => swap_result(8),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O23_out\,
      O => \^ex_fwd\(23)
    );
\Using_FPGA.Native_i_1__69\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(48),
      I1 => ex_sel_alu,
      I2 => swap_result(9),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O22_out\,
      O => \^ex_fwd\(22)
    );
\Using_FPGA.Native_i_1__70\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(49),
      I1 => ex_sel_alu,
      I2 => swap_result(10),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O21_out\,
      O => \^ex_fwd\(21)
    );
\Using_FPGA.Native_i_1__71\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(50),
      I1 => ex_sel_alu,
      I2 => swap_result(11),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O20_out\,
      O => \^ex_fwd\(20)
    );
\Using_FPGA.Native_i_1__72\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(51),
      I1 => ex_sel_alu,
      I2 => swap_result(12),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O19_out\,
      O => \^ex_fwd\(19)
    );
\Using_FPGA.Native_i_1__73\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(52),
      I1 => ex_sel_alu,
      I2 => swap_result(13),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O18_out\,
      O => \^ex_fwd\(18)
    );
\Using_FPGA.Native_i_1__74\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(53),
      I1 => ex_sel_alu,
      I2 => swap_result(14),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O17_out\,
      O => \^ex_fwd\(17)
    );
\Using_FPGA.Native_i_1__75\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(54),
      I1 => ex_sel_alu,
      I2 => swap_result(15),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O15_out\,
      O => \^ex_fwd\(16)
    );
\Using_FPGA.Native_i_1__76\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(55),
      I1 => ex_sel_alu,
      I2 => swap_result(16),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O14_out\,
      O => \^ex_fwd\(15)
    );
\Using_FPGA.Native_i_1__77\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(56),
      I1 => ex_sel_alu,
      I2 => swap_result(17),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O13_out\,
      O => \^ex_fwd\(14)
    );
\Using_FPGA.Native_i_1__78\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(57),
      I1 => ex_sel_alu,
      I2 => swap_result(18),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O12_out\,
      O => \^ex_fwd\(13)
    );
\Using_FPGA.Native_i_1__79\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(58),
      I1 => ex_sel_alu,
      I2 => swap_result(19),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O11_out\,
      O => \^ex_fwd\(12)
    );
\Using_FPGA.Native_i_1__80\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(59),
      I1 => ex_sel_alu,
      I2 => swap_result(20),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O10_out\,
      O => \^ex_fwd\(11)
    );
\Using_FPGA.Native_i_1__81\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(60),
      I1 => ex_sel_alu,
      I2 => swap_result(21),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O9_out\,
      O => \^ex_fwd\(10)
    );
\Using_FPGA.Native_i_1__82\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(61),
      I1 => ex_sel_alu,
      I2 => swap_result(22),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O8_out\,
      O => \^ex_fwd\(9)
    );
\Using_FPGA.Native_i_1__83\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(62),
      I1 => ex_sel_alu,
      I2 => swap_result(23),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O7_out\,
      O => \^ex_fwd\(8)
    );
\Using_FPGA.Native_i_1__84\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(63),
      I1 => ex_sel_alu,
      I2 => swap_result_reg(7),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O6_out\,
      O => \^ex_fwd\(7)
    );
\Using_FPGA.Native_i_1__85\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(64),
      I1 => ex_sel_alu,
      I2 => swap_result_reg(6),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O5_out\,
      O => \^ex_fwd\(6)
    );
\Using_FPGA.Native_i_1__86\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(65),
      I1 => ex_sel_alu,
      I2 => swap_result_reg(5),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O4_out\,
      O => \^ex_fwd\(5)
    );
\Using_FPGA.Native_i_1__87\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(66),
      I1 => ex_sel_alu,
      I2 => swap_result_reg(4),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O3_out\,
      O => \^ex_fwd\(4)
    );
\Using_FPGA.Native_i_1__88\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(67),
      I1 => ex_sel_alu,
      I2 => swap_result_reg(3),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O2_out\,
      O => \^ex_fwd\(3)
    );
\Using_FPGA.Native_i_1__89\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(68),
      I1 => ex_sel_alu,
      I2 => swap_result_reg(2),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O1_out\,
      O => \^ex_fwd\(2)
    );
\Using_FPGA.Native_i_1__90\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B8BBB888"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(69),
      I1 => ex_sel_alu,
      I2 => swap_result_reg(1),
      I3 => ex_swap_instr,
      I4 => \Data_Flow_I/Shift_Logic_Module_I/O0_out\,
      O => \^ex_fwd\(1)
    );
\Using_FPGA.Native_i_1__98\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"1555"
    )
        port map (
      I0 => \mem_pc_i_reg[0]_0\,
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      O => \Performance_Debug_Control.dbg_freeze_nohalt_reg\
    );
\Using_FPGA.Native_i_2__85\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \MEM_DataBus_Addr_reg[0]_0\(70),
      I1 => ex_sel_alu,
      I2 => ex_shift_logic_result(0),
      O => \^ex_fwd\(0)
    );
\Using_FPGA.Native_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(0),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(1),
      O => \Data_Flow_I/Shift_Logic_Module_I/O\
    );
\Using_FPGA.Native_i_3__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(1),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(2),
      O => \Data_Flow_I/Shift_Logic_Module_I/O31_out\
    );
\Using_FPGA.Native_i_3__10\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(10),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(11),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O21_out\
    );
\Using_FPGA.Native_i_3__11\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(11),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(12),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O20_out\
    );
\Using_FPGA.Native_i_3__12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(12),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(13),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O19_out\
    );
\Using_FPGA.Native_i_3__13\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(13),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(14),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O18_out\
    );
\Using_FPGA.Native_i_3__14\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(14),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(15),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O17_out\
    );
\Using_FPGA.Native_i_3__15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(15),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(16),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O15_out\
    );
\Using_FPGA.Native_i_3__16\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(17),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(16),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O14_out\
    );
\Using_FPGA.Native_i_3__17\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(18),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(17),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O13_out\
    );
\Using_FPGA.Native_i_3__18\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(19),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(18),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O12_out\
    );
\Using_FPGA.Native_i_3__19\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(20),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(19),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O11_out\
    );
\Using_FPGA.Native_i_3__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(2),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(3),
      O => \Data_Flow_I/Shift_Logic_Module_I/O30_out\
    );
\Using_FPGA.Native_i_3__20\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(21),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(20),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O10_out\
    );
\Using_FPGA.Native_i_3__21\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(22),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(21),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O9_out\
    );
\Using_FPGA.Native_i_3__22\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(23),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(22),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O8_out\
    );
\Using_FPGA.Native_i_3__23\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(24),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(23),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O7_out\
    );
\Using_FPGA.Native_i_3__24\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(25),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(24),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O6_out\
    );
\Using_FPGA.Native_i_3__25\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(26),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(25),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O5_out\
    );
\Using_FPGA.Native_i_3__26\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(27),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(26),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O4_out\
    );
\Using_FPGA.Native_i_3__27\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(28),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(27),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O3_out\
    );
\Using_FPGA.Native_i_3__28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(29),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(28),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O2_out\
    );
\Using_FPGA.Native_i_3__29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(30),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(29),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O1_out\
    );
\Using_FPGA.Native_i_3__3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(3),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(4),
      O => \Data_Flow_I/Shift_Logic_Module_I/O29_out\
    );
\Using_FPGA.Native_i_3__30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80AAAA8A800000"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(31),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \Using_FPGA.Native_42\(30),
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O0_out\
    );
\Using_FPGA.Native_i_3__31\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"B888B8B8B8888888"
    )
        port map (
      I0 => swap_result_reg(0),
      I1 => ex_swap_instr,
      I2 => ex_Enable_Sext_Shift,
      I3 => \Using_FPGA.Native_i_5__1_n_0\,
      I4 => \^ex_sext_op_reg[0]_0\(1),
      I5 => \Using_FPGA.Native_43\,
      O => ex_shift_logic_result(0)
    );
\Using_FPGA.Native_i_3__4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(4),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(5),
      O => \Data_Flow_I/Shift_Logic_Module_I/O28_out\
    );
\Using_FPGA.Native_i_3__5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(5),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(6),
      O => \Data_Flow_I/Shift_Logic_Module_I/O27_out\
    );
\Using_FPGA.Native_i_3__6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(6),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(7),
      O => \Data_Flow_I/Shift_Logic_Module_I/O26_out\
    );
\Using_FPGA.Native_i_3__7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8880888"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(7),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(8),
      O => \Data_Flow_I/Shift_Logic_Module_I/O24_out\
    );
\Using_FPGA.Native_i_3__8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(8),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(9),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O23_out\
    );
\Using_FPGA.Native_i_3__9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A88A088AA8800880"
    )
        port map (
      I0 => ex_Enable_Sext_Shift,
      I1 => \Using_FPGA.Native_42\(9),
      I2 => \^ex_sext_op_reg[0]_0\(0),
      I3 => \^ex_sext_op_reg[0]_0\(1),
      I4 => \Using_FPGA.Native_42\(10),
      I5 => \out\,
      O => \Data_Flow_I/Shift_Logic_Module_I/O22_out\
    );
\Using_FPGA.Native_i_5__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0DFF0800"
    )
        port map (
      I0 => ex_shift_op(1),
      I1 => ex_MSR(1),
      I2 => ex_shift_op(0),
      I3 => \^ex_sext_op_reg[0]_0\(0),
      I4 => \Using_FPGA.Native_42\(31),
      O => \Using_FPGA.Native_i_5__1_n_0\
    );
\Using_FPGA_2.ex_byte_access_i_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_68
     port map (
      Clk => Clk,
      \MEM_DataBus_Write_Data_reg[0]\(31 downto 0) => \MEM_DataBus_Write_Data_reg[0]\(31 downto 0),
      \MEM_DataBus_Write_Data_reg[0]_0\ => \^ex_reverse_mem_access\,
      \MEM_DataBus_Write_Data_reg[0]_1\ => \^ex_doublet_access\,
      \Using_FPGA.Native_0\ => \^ex_byte_access\,
      \Using_FPGA.Native_1\(23 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(124 downto 101),
      \Using_FPGA.Native_2\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_3\ => PreFetch_Buffer_I1_n_178,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA_2.ex_doublet_access_i_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_69
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_1\ => PreFetch_Buffer_I1_n_179,
      ex_doublet_access => \^ex_doublet_access\,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA_2.ex_is_load_instr_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_70
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => ex_is_load_instr_s,
      \Using_FPGA.Native_1\(0) => \^performance_debug_control.dbg_state_nohalt_reg\(100),
      \Using_FPGA.Native_2\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_3\ => PreFetch_Buffer_I1_n_193,
      ex_Sel_SPR_BTR => ex_Sel_SPR_BTR,
      ex_Sel_SPR_EAR => ex_Sel_SPR_EAR,
      ex_Sel_SPR_EDR => ex_Sel_SPR_EDR,
      ex_Sel_SPR_ESR => ex_Sel_SPR_ESR,
      ex_Sel_SPR_FSR => ex_Sel_SPR_FSR,
      ex_Sel_SPR_PVR => ex_Sel_SPR_PVR,
      ex_Sel_SPR_PVR_reg => \Using_FPGA_2.ex_is_load_instr_Inst_n_3\,
      ex_Sel_SPR_SHR => ex_Sel_SPR_SHR,
      ex_Sel_SPR_SLR => ex_Sel_SPR_SLR,
      ex_is_multi_instr2 => ex_is_multi_instr2,
      ex_is_swx_instr_s => ex_is_swx_instr_s,
      ex_load_store_instr_s => ex_load_store_instr_s,
      ex_reservation => ex_reservation,
      mem_is_multi_or_load_instr0 => mem_is_multi_or_load_instr0,
      p_231_in => p_231_in,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA_2.ex_is_lwx_instr_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_71
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_1\ => PreFetch_Buffer_I1_n_173,
      \Using_FPGA.Native_i_2__21\ => \^mem_exception_taken\,
      \Using_LWX_SWX_instr.ex_reservation_reg\ => \Using_FPGA_2.ex_is_lwx_instr_Inst_n_1\,
      \Using_LWX_SWX_instr.ex_reservation_reg_0\ => \Using_FPGA_2.ex_is_swx_instr_Inst_n_4\,
      ex_MSR_Load_LWX_SWX_C => ex_MSR_Load_LWX_SWX_C,
      ex_is_swx_instr_s => ex_is_swx_instr_s,
      ex_load_store_instr_s => ex_load_store_instr_s,
      ex_reservation => ex_reservation,
      p_227_in => p_227_in,
      p_231_in => p_231_in,
      sync_reset => reset_bool_for_rst,
      wb_exception => wb_exception
    );
\Using_FPGA_2.ex_is_swx_instr_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_72
     port map (
      Clk => Clk,
      D224_out => D224_out,
      D_AS => \^mem_exception_taken\,
      E(0) => \^using_fpga.native_1\,
      MEM_DataBus_Access_reg => \Using_FPGA_2.ex_is_swx_instr_Inst_n_1\,
      MEM_DataBus_Access_reg_0 => \^mem_databus_access\,
      MEM_DataBus_Access_reg_1 => \^using_fpga.native_0\,
      SRI => SRI,
      \Using_FPGA.Native_0\ => of_PipeRun_for_ce,
      \Using_LWX_SWX_instr.ex_reservation_reg\ => \^wb_halted\,
      ex_MSR_Set_SW_BIP => ex_MSR_Set_SW_BIP,
      ex_is_swx_instr_s => ex_is_swx_instr_s,
      ex_load_store_instr_s => ex_load_store_instr_s,
      ex_reservation => ex_reservation,
      \ex_swx_access__0\ => \ex_swx_access__0\,
      p_227_in => p_227_in,
      p_231_in => p_231_in,
      sync_reset => reset_bool_for_rst,
      wb_exception => wb_exception,
      wb_exception_i_reg => \Using_FPGA_2.ex_is_swx_instr_Inst_n_4\
    );
\Using_FPGA_2.ex_load_store_instr_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_73
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_1\ => PreFetch_Buffer_I1_n_185,
      ex_is_swx_instr_s => ex_is_swx_instr_s,
      ex_load_store_instr_s => ex_load_store_instr_s,
      ex_reservation => ex_reservation,
      mem_exception_from_ex => mem_exception_from_ex,
      mem_load_store_access0 => mem_load_store_access0,
      mem_load_store_access_reg => \^ex_valid\,
      mem_load_store_access_reg_0 => \Using_FPGA.Native_39\,
      mem_load_store_access_reg_1 => \Using_FPGA.Native_40\,
      mem_valid_instr => mem_valid_instr,
      p_227_in => p_227_in,
      p_231_in => p_231_in,
      sync_reset => reset_bool_for_rst,
      wb_exception => wb_exception
    );
\Using_FPGA_2.ex_reverse_mem_access_inst\: entity work.design_1_microblaze_0_0_MB_FDRE_74
     port map (
      Clk => Clk,
      \Using_FPGA.Native_0\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_1\ => PreFetch_Buffer_I1_n_194,
      ex_reverse_mem_access => \^ex_reverse_mem_access\,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA_3.ex_clear_MSR_BIP_instr_Inst\: entity work.design_1_microblaze_0_0_MB_FDRE_75
     port map (
      Clk => Clk,
      E(0) => \^using_fpga.native_1\,
      \Using_FPGA.Native_0\ => of_PipeRun_for_ce,
      \Using_FPGA.Native_1\ => \Using_FPGA_3.of_clear_MSR_BIP_hold_Inst_n_0\,
      \Using_FPGA.Native_2\ => \^ex_set_bip_reg_0\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_38\,
      ex_MSR(0) => ex_MSR(2),
      ex_set_bip_reg => ex_set_bip_reg_1,
      p_231_in => p_231_in,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA_3.of_clear_MSR_BIP_hold_Inst\: entity work.design_1_microblaze_0_0_MB_FDR
     port map (
      Clk => Clk,
      E(0) => \^using_fpga.native_1\,
      I0 => I0,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg\ => \Using_FPGA_3.of_clear_MSR_BIP_hold_Inst_n_0\,
      Q(5) => ex_opcode(0),
      Q(4) => ex_opcode(1),
      Q(3) => ex_opcode(2),
      Q(2) => ex_opcode(3),
      Q(1) => ex_opcode(4),
      Q(0) => ex_opcode(5),
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_39\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_40\,
      \Using_FPGA.Native_2\ => \^ex_valid\,
      \Using_FPGA.Native_3\ => of_PipeRun_for_ce,
      sync_reset => reset_bool_for_rst
    );
\Using_FPGA_4.of_read_ex_write_op1_conflict_INST1\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized8\
     port map (
      D(2) => \ex_gpr_write_addr_reg_n_0_[0]\,
      D(1) => I2,
      D(0) => I4,
      O => O,
      of_predecode(2) => of_predecode(1),
      of_predecode(1) => of_predecode(2),
      of_predecode(0) => of_predecode(3)
    );
\Using_FPGA_4.of_read_ex_write_op1_conflict_INST2\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized10\
     port map (
      A => A,
      D(0) => \ex_gpr_write_addr_reg_n_0_[4]\,
      I0 => I0,
      O => O,
      \Using_FPGA.Native_i_1__58_0\ => ex_gpr_write_reg_n_0,
      \Using_FPGA.Native_i_1__58_1\ => \^ex_valid\,
      ex_is_multi_or_load_instr => ex_is_multi_or_load_instr,
      of_predecode(1) => of_predecode(4),
      of_predecode(0) => of_predecode(5)
    );
\Using_FPGA_4.of_read_ex_write_op2_conflict_INST1\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized8_76\
     port map (
      D(2) => \ex_gpr_write_addr_reg_n_0_[0]\,
      D(1) => I2,
      D(0) => I4,
      of_predecode(2) => of_predecode(6),
      of_predecode(1) => of_predecode(7),
      of_predecode(0) => of_predecode(8),
      of_read_ex_write_op2_conflict_part1 => of_read_ex_write_op2_conflict_part1
    );
\Using_FPGA_4.of_read_ex_write_op2_conflict_INST2\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized10_77\
     port map (
      D(0) => \ex_gpr_write_addr_reg_n_0_[4]\,
      I0 => I0,
      \Using_FPGA.Native_i_1__9_0\ => ex_gpr_write_reg_n_0,
      \Using_FPGA.Native_i_1__9_1\ => \^ex_valid\,
      ex_is_multi_or_load_instr => ex_is_multi_or_load_instr,
      ex_is_multi_or_load_instr_reg => \Using_FPGA_4.of_read_ex_write_op2_conflict_INST2_n_0\,
      of_predecode(1) => of_predecode(9),
      of_predecode(0) => of_predecode(10),
      of_read_ex_write_op2_conflict_part1 => of_read_ex_write_op2_conflict_part1,
      of_use_op2_s => of_use_op2_s
    );
\Using_FPGA_4.of_read_ex_write_op3_conflict_INST1\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized8_78\
     port map (
      D(2) => \ex_gpr_write_addr_reg_n_0_[0]\,
      D(1) => I2,
      D(0) => I4,
      \Using_FPGA.Native_i_1__56\(1) => \^of_gpr_op3_rd_addr\(0),
      \Using_FPGA.Native_i_1__56\(0) => \^of_gpr_op3_rd_addr\(1),
      \Using_FPGA.Native_i_1__56_0\ => \^of_gpr_op3_rd_addr\(2),
      of_read_ex_write_op3_conflict_part1 => of_read_ex_write_op3_conflict_part1
    );
\Using_FPGA_4.of_read_ex_write_op3_conflict_INST2\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized10_79\
     port map (
      D(0) => \ex_gpr_write_addr_reg_n_0_[4]\,
      I0 => I0,
      \Using_FPGA.Native_i_1__56_0\ => \^of_gpr_op3_rd_addr\(3),
      \Using_FPGA.Native_i_1__56_1\ => \^of_gpr_op3_rd_addr\(4),
      \Using_FPGA.Native_i_1__56_2\ => ex_gpr_write_reg_n_0,
      \Using_FPGA.Native_i_1__56_3\ => \^ex_valid\,
      ex_is_multi_or_load_instr => ex_is_multi_or_load_instr,
      ex_is_multi_or_load_instr_reg => \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0\,
      of_predecode(0) => of_predecode(0),
      of_read_ex_write_op3_conflict_part1 => of_read_ex_write_op3_conflict_part1
    );
\Using_FPGA_4.of_read_mem_write_op1_conflict_INST1\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized8_80\
     port map (
      Q(2) => mem_gpr_write_addr(0),
      Q(1) => mem_gpr_write_addr(1),
      Q(0) => mem_gpr_write_addr(2),
      mem_is_multi_or_load_instr => mem_is_multi_or_load_instr,
      mem_is_multi_or_load_instr_reg => \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0\,
      of_predecode(2) => of_predecode(1),
      of_predecode(1) => of_predecode(2),
      of_predecode(0) => of_predecode(3),
      of_read_mem_write_op1_conflict_part2 => of_read_mem_write_op1_conflict_part2
    );
\Using_FPGA_4.of_read_mem_write_op1_conflict_INST2\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized10_81\
     port map (
      Q(1) => mem_gpr_write_addr(3),
      Q(0) => mem_gpr_write_addr(4),
      mem_gpr_write => mem_gpr_write,
      mem_valid_instr => mem_valid_instr,
      of_predecode(1) => of_predecode(4),
      of_predecode(0) => of_predecode(5),
      of_read_mem_write_op1_conflict_part2 => of_read_mem_write_op1_conflict_part2
    );
\Using_FPGA_4.of_read_mem_write_op2_conflict_INST1\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized8_82\
     port map (
      Q(2) => mem_gpr_write_addr(0),
      Q(1) => mem_gpr_write_addr(1),
      Q(0) => mem_gpr_write_addr(2),
      of_predecode(2) => of_predecode(6),
      of_predecode(1) => of_predecode(7),
      of_predecode(0) => of_predecode(8),
      of_read_mem_write_op2_conflict_part1 => of_read_mem_write_op2_conflict_part1
    );
\Using_FPGA_4.of_read_mem_write_op2_conflict_INST2\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized10_83\
     port map (
      Q(1) => mem_gpr_write_addr(3),
      Q(0) => mem_gpr_write_addr(4),
      mem_gpr_write => mem_gpr_write,
      mem_is_multi_or_load_instr => mem_is_multi_or_load_instr,
      mem_is_multi_or_load_instr_reg => \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0\,
      mem_valid_instr => mem_valid_instr,
      of_predecode(1) => of_predecode(9),
      of_predecode(0) => of_predecode(10),
      of_read_mem_write_op2_conflict_part1 => of_read_mem_write_op2_conflict_part1,
      of_use_op2_s => of_use_op2_s
    );
\Using_FPGA_4.of_read_mem_write_op3_conflict_INST1\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized8_84\
     port map (
      D(1) => \^of_gpr_op3_rd_addr\(0),
      D(0) => \^of_gpr_op3_rd_addr\(1),
      Q(2) => mem_gpr_write_addr(0),
      Q(1) => mem_gpr_write_addr(1),
      Q(0) => mem_gpr_write_addr(2),
      \Using_FPGA.Native_i_1__55\ => \^of_gpr_op3_rd_addr\(2),
      of_read_mem_write_op3_conflict_part1 => of_read_mem_write_op3_conflict_part1
    );
\Using_FPGA_4.of_read_mem_write_op3_conflict_INST2\: entity work.\design_1_microblaze_0_0_MB_LUT6__parameterized10_85\
     port map (
      Q(1) => mem_gpr_write_addr(3),
      Q(0) => mem_gpr_write_addr(4),
      \Using_FPGA.Native_i_1__55_0\ => \^of_gpr_op3_rd_addr\(3),
      \Using_FPGA.Native_i_1__55_1\ => \^of_gpr_op3_rd_addr\(4),
      mem_gpr_write => mem_gpr_write,
      mem_is_multi_or_load_instr => mem_is_multi_or_load_instr,
      mem_is_multi_or_load_instr_reg => \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0\,
      mem_valid_instr => mem_valid_instr,
      of_predecode(0) => of_predecode(0),
      of_read_mem_write_op3_conflict_part1 => of_read_mem_write_op3_conflict_part1
    );
\Using_LWX_SWX_instr.ex_reservation_reg\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Using_FPGA_2.ex_is_lwx_instr_Inst_n_1\,
      Q => ex_reservation,
      R => '0'
    );
\Using_PC_Incr_Dbg_or_Prot.if_pc_incr_carry_and_1\: entity work.design_1_microblaze_0_0_carry_and_86
     port map (
      \Using_FPGA.Native\ => \Using_FPGA.Native_36\,
      if_pc_incr_carry0 => if_pc_incr_carry0,
      if_pc_incr_carry1 => if_pc_incr_carry1,
      lopt => lopt_3,
      lopt_1 => lopt_4
    );
WB_Byte_Access_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => \^mem_byte_access\,
      Q => \^wb_byte_access\,
      R => reset_bool_for_rst
    );
WB_DelaySlot_Instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_delayslot_instr,
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(0),
      R => reset_bool_for_rst
    );
WB_Doublet_Access_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => \^mem_doublet_access\,
      Q => wb_doublet_access,
      R => reset_bool_for_rst
    );
\WB_MEM_Result[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reset_bool_for_rst,
      I1 => mem_Sel_MEM_Res,
      O => SR(0)
    );
WB_PC_Valid_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_valid_instr,
      Q => wb_pc_valid,
      R => reset_bool_for_rst
    );
WB_Read_Imm_Reg_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_read_imm_reg_1,
      Q => wb_read_imm_reg_1,
      R => reset_bool_for_rst
    );
WB_Read_Imm_Reg_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_read_imm_reg,
      Q => wb_read_imm_reg,
      R => reset_bool_for_rst
    );
active_access_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000220322"
    )
        port map (
      I0 => \Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1\,
      I1 => \^lockstep_master_out\(2),
      I2 => M_AXI_DP_BVALID,
      I3 => active_access,
      I4 => M_AXI_DP_RVALID,
      I5 => reset_bool_for_rst,
      O => M_AXI_DP_BVALID_0
    );
active_wakeup_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EEEEEEE0"
    )
        port map (
      I0 => wakeup_i(0),
      I1 => wakeup_i(1),
      I2 => \^sleep_decode\,
      I3 => \^hibernate\,
      I4 => \^suspend\,
      O => active_wakeup0
    );
active_wakeup_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => active_wakeup0,
      Q => active_wakeup,
      R => reset_bool_for_rst
    );
\data_rd_reg[0]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(28),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(34),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(23)
    );
\data_rd_reg[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(18),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(24),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(13)
    );
\data_rd_reg[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(17),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(23),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(12)
    );
\data_rd_reg[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(16),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(22),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(11)
    );
\data_rd_reg[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(15),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(21),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(10)
    );
\data_rd_reg[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(14),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(20),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(9)
    );
\data_rd_reg[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(13),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(19),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(8)
    );
\data_rd_reg[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(27),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(33),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(22)
    );
\data_rd_reg[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(12),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(18),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(7)
    );
\data_rd_reg[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(11),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(17),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(6)
    );
\data_rd_reg[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(10),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(16),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(5)
    );
\data_rd_reg[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(9),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(15),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(4)
    );
\data_rd_reg[28]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF80BFBFBF808080"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(8),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(10),
      I4 => \data_rd_reg_reg[0]\,
      I5 => \MEM_DataBus_Addr_reg[0]_0\(14),
      O => wb_gpr_write_dbg_reg_0(3)
    );
\data_rd_reg[29]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF80BFBFBF808080"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(7),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(9),
      I4 => \data_rd_reg_reg[0]\,
      I5 => \MEM_DataBus_Addr_reg[0]_0\(13),
      O => wb_gpr_write_dbg_reg_0(2)
    );
\data_rd_reg[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(26),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(32),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(21)
    );
\data_rd_reg[30]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF80BFBFBF808080"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(6),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(8),
      I4 => \data_rd_reg_reg[0]\,
      I5 => \MEM_DataBus_Addr_reg[0]_0\(12),
      O => wb_gpr_write_dbg_reg_0(1)
    );
\data_rd_reg[31]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(5),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(11),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(0)
    );
\data_rd_reg[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(25),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(31),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(20)
    );
\data_rd_reg[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(24),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(30),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(19)
    );
\data_rd_reg[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(23),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(29),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(18)
    );
\data_rd_reg[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(22),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(28),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(17)
    );
\data_rd_reg[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(21),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(27),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(16)
    );
\data_rd_reg[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(20),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(26),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(15)
    );
\data_rd_reg[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8080BF80"
    )
        port map (
      I0 => \^performance_debug_control.dbg_state_nohalt_reg\(19),
      I1 => \^wb_gpr_wr_dbg\,
      I2 => if_missed_fetch_reg_1,
      I3 => \MEM_DataBus_Addr_reg[0]_0\(25),
      I4 => \data_rd_reg_reg[0]\,
      O => wb_gpr_write_dbg_reg_0(14)
    );
ex_Sel_SPR_BTR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_BTR,
      Q => ex_Sel_SPR_BTR,
      R => reset_bool_for_rst
    );
ex_Sel_SPR_EAR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_EAR,
      Q => ex_Sel_SPR_EAR,
      R => reset_bool_for_rst
    );
ex_Sel_SPR_EDR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_EDR,
      Q => ex_Sel_SPR_EDR,
      R => reset_bool_for_rst
    );
ex_Sel_SPR_ESR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_ESR,
      Q => ex_Sel_SPR_ESR,
      R => reset_bool_for_rst
    );
ex_Sel_SPR_FSR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_FSR,
      Q => ex_Sel_SPR_FSR,
      R => reset_bool_for_rst
    );
ex_Sel_SPR_PVR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_PVR,
      Q => ex_Sel_SPR_PVR,
      R => reset_bool_for_rst
    );
ex_Sel_SPR_SHR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_SHR,
      Q => ex_Sel_SPR_SHR,
      R => reset_bool_for_rst
    );
ex_Sel_SPR_SLR_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_SLR,
      Q => ex_Sel_SPR_SLR,
      R => reset_bool_for_rst
    );
ex_Write_DCache_decode_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => ex_Write_DCache_decode_cmb,
      Q => ex_write_dcache_instr,
      R => reset_bool_for_rst
    );
ex_Write_ICache_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => ex_Write_ICache_i_cmb,
      Q => ex_Write_ICache_i,
      R => reset_bool_for_rst
    );
ex_alu_sel_logic_i_reg: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_195,
      Q => \^ex_alu_sel_logic\,
      S => reset_bool_for_rst
    );
ex_branch_with_delayslot_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_48,
      Q => ex_branch_with_delayslot,
      R => reset_bool_for_rst
    );
ex_delayslot_Instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_delayslot_Instr0,
      Q => ex_delayslot_Instr,
      R => reset_bool_for_rst
    );
ex_enable_alu_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_66,
      Q => EX_Enable_ALU,
      R => reset_bool_for_rst
    );
ex_enable_sext_shift_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_enable_sext_shift_i0,
      Q => ex_Enable_Sext_Shift,
      R => reset_bool_for_rst
    );
ex_first_cycle_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Use_MuxCy[11].OF_Piperun_Stage_n_4\,
      Q => ex_first_cycle,
      R => '0'
    );
\ex_gpr_write_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(0),
      Q => \ex_gpr_write_addr_reg_n_0_[0]\,
      R => reset_bool_for_rst
    );
\ex_gpr_write_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(1),
      Q => I2,
      R => reset_bool_for_rst
    );
\ex_gpr_write_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(2),
      Q => I4,
      R => reset_bool_for_rst
    );
\ex_gpr_write_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(3),
      Q => I0,
      R => reset_bool_for_rst
    );
\ex_gpr_write_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(4),
      Q => \ex_gpr_write_addr_reg_n_0_[4]\,
      R => reset_bool_for_rst
    );
ex_gpr_write_dbg_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => PreFetch_Buffer_I1_n_184,
      Q => \ex_gpr_write_dbg__0\,
      R => '0'
    );
ex_gpr_write_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => PreFetch_Buffer_I1_n_49,
      Q => ex_gpr_write_reg_n_0,
      R => '0'
    );
ex_hibernate_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => active_wakeup,
      I1 => reset_bool_for_rst,
      O => ex_hibernate_i_i_1_n_0
    );
ex_hibernate_i_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA2A2A2AAA"
    )
        port map (
      I0 => ex_mbar_sleep,
      I1 => ex_mbar_decode,
      I2 => p_231_in,
      I3 => ex_first_cycle,
      I4 => ex_mbar_stall_no_sleep_1,
      I5 => ex_jump_hold,
      O => ex_sleep_i0
    );
ex_hibernate_i_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_1_in124_in,
      O => p_1_in
    );
ex_hibernate_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => ex_sleep_i0,
      D => p_1_in,
      Q => \^hibernate\,
      R => ex_hibernate_i_i_1_n_0
    );
\ex_instr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(0),
      Q => \ex_instr_reg_n_0_[0]\,
      R => '0'
    );
\ex_instr_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(4),
      Q => \ex_instr_reg_n_0_[10]\,
      R => '0'
    );
\ex_instr_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op1_rd_addr\(0),
      Q => \ex_instr_reg_n_0_[11]\,
      R => '0'
    );
\ex_instr_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op1_rd_addr\(1),
      Q => \ex_instr_reg_n_0_[12]\,
      R => '0'
    );
\ex_instr_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op1_rd_addr\(2),
      Q => \ex_instr_reg_n_0_[13]\,
      R => '0'
    );
\ex_instr_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op1_rd_addr\(3),
      Q => \ex_instr_reg_n_0_[14]\,
      R => '0'
    );
\ex_instr_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op1_rd_addr\(4),
      Q => \ex_instr_reg_n_0_[15]\,
      R => '0'
    );
\ex_instr_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(0),
      Q => \ex_instr_reg_n_0_[16]\,
      R => '0'
    );
\ex_instr_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(1),
      Q => \ex_instr_reg_n_0_[17]\,
      R => '0'
    );
\ex_instr_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(2),
      Q => \ex_instr_reg_n_0_[18]\,
      R => '0'
    );
\ex_instr_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(3),
      Q => \ex_instr_reg_n_0_[19]\,
      R => '0'
    );
\ex_instr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(1),
      Q => \ex_instr_reg_n_0_[1]\,
      R => '0'
    );
\ex_instr_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(4),
      Q => \ex_instr_reg_n_0_[20]\,
      R => '0'
    );
\ex_instr_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(5),
      Q => \ex_instr_reg_n_0_[21]\,
      R => '0'
    );
\ex_instr_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(6),
      Q => \ex_instr_reg_n_0_[22]\,
      R => '0'
    );
\ex_instr_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(7),
      Q => \ex_instr_reg_n_0_[23]\,
      R => '0'
    );
\ex_instr_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(8),
      Q => \ex_instr_reg_n_0_[24]\,
      R => '0'
    );
\ex_instr_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(9),
      Q => \ex_instr_reg_n_0_[25]\,
      R => '0'
    );
\ex_instr_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(10),
      Q => \ex_instr_reg_n_0_[26]\,
      R => '0'
    );
\ex_instr_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(11),
      Q => \ex_instr_reg_n_0_[27]\,
      R => '0'
    );
\ex_instr_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(12),
      Q => \ex_instr_reg_n_0_[28]\,
      R => '0'
    );
\ex_instr_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(13),
      Q => \ex_instr_reg_n_0_[29]\,
      R => '0'
    );
\ex_instr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(2),
      Q => \ex_instr_reg_n_0_[2]\,
      R => '0'
    );
\ex_instr_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(14),
      Q => \ex_instr_reg_n_0_[30]\,
      R => '0'
    );
\ex_instr_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_imm_data\(15),
      Q => \ex_instr_reg_n_0_[31]\,
      R => '0'
    );
\ex_instr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(3),
      Q => \ex_instr_reg_n_0_[3]\,
      R => '0'
    );
\ex_instr_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(4),
      Q => \ex_instr_reg_n_0_[4]\,
      R => '0'
    );
\ex_instr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(5),
      Q => \ex_instr_reg_n_0_[5]\,
      R => '0'
    );
\ex_instr_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(0),
      Q => p_1_in124_in,
      R => '0'
    );
\ex_instr_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(1),
      Q => p_0_in123_in,
      R => '0'
    );
\ex_instr_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(2),
      Q => \ex_instr_reg_n_0_[8]\,
      R => '0'
    );
\ex_instr_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => \^of_gpr_op3_rd_addr\(3),
      Q => \ex_instr_reg_n_0_[9]\,
      R => '0'
    );
ex_is_div_instr_I_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => PreFetch_Buffer_I1_n_50,
      Q => EX_Is_Div_Instr,
      R => '0'
    );
ex_is_multi_instr2_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_MSR1,
      Q => ex_is_multi_instr2,
      R => reset_bool_for_rst
    );
ex_is_multi_or_load_instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_is_multi_or_load_instr0,
      Q => ex_is_multi_or_load_instr,
      R => reset_bool_for_rst
    );
ex_jump_hold_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => jump_logic_I1_n_6,
      Q => ex_jump_hold,
      R => '0'
    );
ex_jump_nodelay_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Use_MuxCy[11].OF_Piperun_Stage_n_1\,
      Q => ex_jump_nodelay,
      R => '0'
    );
ex_load_alu_carry_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => PreFetch_Buffer_I1_n_189,
      Q => ex_load_alu_carry_reg_0,
      R => reset_bool_for_rst
    );
ex_load_shift_carry_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_load_shift_carry0,
      Q => ex_load_shift_carry,
      R => reset_bool_for_rst
    );
ex_mbar_decode_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => ex_mbar_decode_cmb,
      Q => ex_mbar_decode,
      R => reset_bool_for_rst
    );
ex_mbar_is_sleep_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => ex_mbar_is_sleep_cmb,
      Q => ex_mbar_is_sleep,
      R => reset_bool_for_rst
    );
ex_mbar_sleep_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000000EAAA"
    )
        port map (
      I0 => ex_mbar_sleep,
      I1 => ex_mbar_is_sleep,
      I2 => p_232_in,
      I3 => ex_first_cycle,
      I4 => active_wakeup,
      I5 => reset_bool_for_rst,
      O => ex_mbar_sleep_i_1_n_0
    );
ex_mbar_sleep_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A200"
    )
        port map (
      I0 => ex_mbar_decode,
      I1 => \Using_FPGA.Native_39\,
      I2 => \Using_FPGA.Native_40\,
      I3 => \^ex_valid\,
      O => p_232_in
    );
ex_mbar_sleep_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => ex_mbar_sleep_i_1_n_0,
      Q => ex_mbar_sleep,
      R => '0'
    );
ex_mbar_stall_no_sleep_1_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F44"
    )
        port map (
      I0 => \ex_gpr_write_addr_reg_n_0_[4]\,
      I1 => if_fetch_in_progress,
      I2 => I0,
      I3 => mem_valid_instr,
      O => ex_mbar_stall_no_sleep_10
    );
ex_mbar_stall_no_sleep_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => ex_mbar_stall_no_sleep_10,
      Q => ex_mbar_stall_no_sleep_1,
      R => reset_bool_for_rst
    );
ex_mfsmsr_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_Sel_SPR_MSR88_out,
      Q => ex_mfsmsr_i,
      R => reset_bool_for_rst
    );
ex_move_to_MSR_instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_move_to_MSR_instr93_out,
      Q => ex_move_to_MSR_instr,
      R => reset_bool_for_rst
    );
\ex_opcode_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(0),
      Q => ex_opcode(0),
      R => reset_bool_for_rst
    );
\ex_opcode_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(1),
      Q => ex_opcode(1),
      R => reset_bool_for_rst
    );
\ex_opcode_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(2),
      Q => ex_opcode(2),
      R => reset_bool_for_rst
    );
\ex_opcode_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(3),
      Q => ex_opcode(3),
      R => reset_bool_for_rst
    );
\ex_opcode_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(4),
      Q => ex_opcode(4),
      R => reset_bool_for_rst
    );
\ex_opcode_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_instr(5),
      Q => ex_opcode(5),
      R => reset_bool_for_rst
    );
ex_read_imm_reg_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_read_imm_reg,
      Q => ex_read_imm_reg_1,
      R => reset_bool_for_rst
    );
ex_read_imm_reg_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002AAA"
    )
        port map (
      I0 => of_read_imm_reg_ii,
      I1 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I3 => wb_exception,
      I4 => \mem_pc_i_reg[0]_0\,
      O => ex_read_imm_reg_i_1_n_0
    );
ex_read_imm_reg_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_read_imm_reg_i_1_n_0,
      Q => ex_read_imm_reg,
      R => reset_bool_for_rst
    );
ex_sel_alu_i_reg: unisim.vcomponents.FDSE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_sel_alu_i0,
      Q => ex_sel_alu,
      S => reset_bool_for_rst
    );
ex_set_bip_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => ex_set_bip,
      Q => \^ex_set_bip_reg_0\,
      R => reset_bool_for_rst
    );
ex_sleep_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => p_0_in123_in,
      O => ex_sleep_i_i_1_n_0
    );
ex_sleep_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => ex_sleep_i0,
      D => ex_sleep_i_i_1_n_0,
      Q => \^sleep_decode\,
      R => ex_hibernate_i_i_1_n_0
    );
ex_suspend_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => p_0_in123_in,
      I1 => p_1_in124_in,
      O => ex_suspend_i0
    );
ex_suspend_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => ex_sleep_i0,
      D => ex_suspend_i0,
      Q => \^suspend\,
      R => ex_hibernate_i_i_1_n_0
    );
ex_valid_jump_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_next_ex_valid,
      Q => ex_valid_jump,
      R => \Use_MuxCy[11].OF_Piperun_Stage_n_3\
    );
ex_valid_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => of_PipeRun_for_ce,
      D => of_next_ex_valid,
      Q => \^ex_valid\,
      R => \Use_MuxCy[11].OF_Piperun_Stage_n_3\
    );
exception_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F3B3B3B300808080"
    )
        port map (
      I0 => if_missed_fetch_reg_1,
      I1 => \^wb_valid_reg_0\,
      I2 => wb_exception,
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I4 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I5 => exception_reg(0),
      O => \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg\
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_FSR
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_SHR
    );
i_10: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_PVR_Select(2)
    );
i_11: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_PVR_Select(3)
    );
i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_EAR
    );
i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_SLR
    );
i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_EDR
    );
i_5: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_ESR
    );
i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_PVR
    );
i_7: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_Sel_SPR_BTR
    );
i_8: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_PVR_Select(0)
    );
i_9: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => of_PVR_Select(1)
    );
if_fetch_in_progress_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFEAAA"
    )
        port map (
      I0 => if_missed_fetch_reg_0,
      I1 => wb_exception,
      I2 => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      I3 => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      I4 => if_missed_fetch_reg_1,
      I5 => reset_bool_for_rst,
      O => if_fetch_in_progress_i_1_n_0
    );
if_fetch_in_progress_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => PreFetch_Buffer_I1_n_182,
      Q => if_fetch_in_progress,
      R => if_fetch_in_progress_i_1_n_0
    );
if_missed_fetch_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => PreFetch_Buffer_I1_n_183,
      Q => if_missed_fetch,
      R => if_fetch_in_progress_i_1_n_0
    );
if_pc_incr_carry_and_0: entity work.design_1_microblaze_0_0_carry_and_87
     port map (
      if_missed_fetch => if_missed_fetch,
      if_pc_incr_carry0 => if_pc_incr_carry0,
      lopt => lopt_3,
      lopt_1 => lopt_4,
      lopt_10 => lopt_31,
      lopt_11 => lopt_32,
      lopt_12 => lopt_33,
      lopt_13 => lopt_34,
      lopt_14 => lopt_35,
      lopt_15 => lopt_36,
      lopt_16 => lopt_37,
      lopt_17 => lopt_38,
      lopt_18 => lopt_39,
      lopt_19 => lopt_40,
      lopt_2 => \Using_FPGA.Native_36\,
      lopt_20 => lopt_41,
      lopt_21 => lopt_42,
      lopt_22 => lopt_43,
      lopt_23 => lopt_44,
      lopt_24 => lopt_45,
      lopt_25 => lopt_46,
      lopt_3 => lopt_5,
      lopt_4 => lopt_6,
      lopt_5 => if_fetch_for_timing_optimization1,
      lopt_6 => lopt_7,
      lopt_7 => lopt_8,
      lopt_8 => lopt_9,
      lopt_9 => lopt_10
    );
if_pc_incr_carry_and_3: entity work.design_1_microblaze_0_0_carry_and_88
     port map (
      CI => if_pc_incr_carry3,
      if_fetch_for_timing_optimization1 => if_fetch_for_timing_optimization1,
      if_pc_incr_carry1 => if_pc_incr_carry1,
      lopt => lopt_5,
      lopt_1 => lopt_6
    );
jump_logic_I1: entity work.design_1_microblaze_0_0_jump_logic
     port map (
      Clk => Clk,
      E(0) => \^using_fpga.native_1\,
      \EX_MBAR_Stall__1\ => \EX_MBAR_Stall__1\,
      I5 => I5,
      O => O87_out,
      O56_out => O56_out,
      Q(1 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(3 downto 2),
      \Using_FPGA.Native\ => jump_logic_I1_n_42,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_35\,
      \Using_FPGA.Native_1\ => PreFetch_Buffer_I1_n_190,
      \Using_FPGA.Native_2\(0) => \Using_FPGA.Native_37\(0),
      ex_Exception_Taken => ex_Exception_Taken,
      ex_branch_with_delayslot => ex_branch_with_delayslot,
      ex_databus_addr(1 downto 0) => ex_databus_addr(1 downto 0),
      ex_delayslot_Instr0 => ex_delayslot_Instr0,
      ex_first_cycle => ex_first_cycle,
      ex_jump => ex_jump,
      ex_jump_hold => ex_jump_hold,
      ex_jump_hold_reg => jump_logic_I1_n_6,
      ex_jump_nodelay => ex_jump_nodelay,
      ex_jump_q => ex_jump_q,
      ex_mbar_decode => ex_mbar_decode,
      ex_mbar_sleep => ex_mbar_sleep,
      ex_mbar_stall_no_sleep_1 => ex_mbar_stall_no_sleep_1,
      ex_op1_cmp_eq1 => ex_op1_cmp_eq1,
      ex_op1_cmp_eq_n5_out => ex_op1_cmp_eq_n5_out,
      ex_op1_cmp_eq_reg_0 => PreFetch_Buffer_I1_n_56,
      ex_op1_cmp_equal => ex_op1_cmp_equal,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      ex_op1_zero => ex_op1_zero,
      force12_out => force12_out,
      force_Val10_out => force_Val10_out,
      force_Val2_N_reg_0 => PreFetch_Buffer_I1_n_59,
      \if_pc_reg[0]\(31 downto 0) => \^performance_debug_control.dbg_state_nohalt_reg\(156 downto 125),
      \if_pc_reg[0]_0\(29 downto 0) => \MEM_DataBus_Addr_reg[0]_0\(70 downto 41),
      \if_pc_reg[10]\ => O49_out,
      \if_pc_reg[11]\ => O51_out,
      \if_pc_reg[12]\ => O53_out,
      \if_pc_reg[13]\ => O55_out,
      \if_pc_reg[14]\ => O57_out,
      \if_pc_reg[15]\ => O59_out,
      \if_pc_reg[16]\ => O61_out,
      \if_pc_reg[17]\ => O63_out,
      \if_pc_reg[18]\ => O65_out,
      \if_pc_reg[19]\ => O67_out,
      \if_pc_reg[1]\ => O31_out,
      \if_pc_reg[20]\ => O69_out,
      \if_pc_reg[21]\ => O71_out,
      \if_pc_reg[22]\ => O73_out,
      \if_pc_reg[23]\ => O75_out,
      \if_pc_reg[24]\ => O77_out,
      \if_pc_reg[25]\ => O79_out,
      \if_pc_reg[26]\ => O81_out,
      \if_pc_reg[27]\ => O83_out,
      \if_pc_reg[28]\ => O85_out,
      \if_pc_reg[2]\ => O33_out,
      \if_pc_reg[30]\(1) => p_1_in3_in,
      \if_pc_reg[30]\(0) => PC_Module_I_n_35,
      \if_pc_reg[3]\ => O35_out,
      \if_pc_reg[4]\ => O37_out,
      \if_pc_reg[5]\ => O39_out,
      \if_pc_reg[6]\ => O41_out,
      \if_pc_reg[7]\ => O43_out,
      \if_pc_reg[8]\ => O45_out,
      \if_pc_reg[9]\ => O47_out,
      keep_jump_taken_with_ds => keep_jump_taken_with_ds,
      keep_jump_taken_with_ds_reg => jump_logic_I1_n_8,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_2 => lopt_2,
      mem_exception_from_ex => mem_exception_from_ex,
      mem_jump_taken0 => mem_jump_taken0,
      mem_valid_instr => mem_valid_instr,
      of_next_ex_valid => of_next_ex_valid,
      of_valid => of_valid,
      \out\ => ex_valid_jump,
      sync_reset => reset_bool_for_rst,
      use_Reg_Neg_DI1_out => use_Reg_Neg_DI1_out,
      use_Reg_Neg_S3_out => use_Reg_Neg_S3_out,
      use_Reg_Neg_S_reg_0 => of_PipeRun_for_ce,
      wb_exception => wb_exception
    );
keep_jump_taken_with_ds_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => jump_logic_I1_n_8,
      Q => keep_jump_taken_with_ds,
      R => '0'
    );
mem_PipeRun_carry_and: entity work.design_1_microblaze_0_0_carry_and_89
     port map (
      E(0) => \^using_fpga.native_1\,
      \Using_FPGA.Native\ => \^using_fpga.native_0\,
      flush_pipe => flush_pipe,
      lopt => lopt_11,
      lopt_1 => lopt_12,
      lopt_2 => lopt_13,
      mem_exception_from_ex => mem_exception_from_ex,
      mem_gpr_write => mem_gpr_write,
      mem_gpr_write_dbg => mem_gpr_write_dbg,
      mem_valid_instr => mem_valid_instr,
      mem_valid_reg => mem_PipeRun_carry_and_n_1,
      mem_valid_reg_0 => \^ex_valid\,
      mem_wait_on_ready_N => mem_wait_on_ready_N,
      sync_reset => reset_bool_for_rst,
      wb_exception => wb_exception,
      wb_gpr_write_dbg0 => wb_gpr_write_dbg0,
      wb_gpr_write_i0 => wb_gpr_write_i0,
      wb_valid_reg => mem_PipeRun_carry_and_n_2,
      wb_valid_reg_0 => \^wb_valid_reg_0\,
      wb_valid_reg_1(0) => \^wb_piperun_i_reg_0\(0)
    );
mem_Write_DCache_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000888"
    )
        port map (
      I0 => ex_write_dcache_instr,
      I1 => p_231_in,
      I2 => mem_exception_from_ex,
      I3 => mem_valid_instr,
      I4 => wb_exception,
      O => mem_Write_DCache_i_1_n_0
    );
mem_Write_DCache_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => mem_Write_DCache_i_1_n_0,
      Q => mem_Write_DCache,
      R => reset_bool_for_rst
    );
mem_byte_access_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \^ex_byte_access\,
      Q => \^mem_byte_access\,
      R => reset_bool_for_rst
    );
mem_delayslot_instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => ex_delayslot_Instr,
      Q => mem_delayslot_instr,
      R => reset_bool_for_rst
    );
mem_doublet_access_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \^ex_doublet_access\,
      Q => \^mem_doublet_access\,
      R => reset_bool_for_rst
    );
mem_exception_from_ex_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => ex_Exception_Taken,
      Q => mem_exception_from_ex,
      R => reset_bool_for_rst
    );
\mem_gpr_write_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_gpr_write_addr_reg_n_0_[0]\,
      Q => mem_gpr_write_addr(0),
      R => reset_bool_for_rst
    );
\mem_gpr_write_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => I2,
      Q => mem_gpr_write_addr(1),
      R => reset_bool_for_rst
    );
\mem_gpr_write_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => I4,
      Q => mem_gpr_write_addr(2),
      R => reset_bool_for_rst
    );
\mem_gpr_write_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => I0,
      Q => mem_gpr_write_addr(3),
      R => reset_bool_for_rst
    );
\mem_gpr_write_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_gpr_write_addr_reg_n_0_[4]\,
      Q => mem_gpr_write_addr(4),
      R => reset_bool_for_rst
    );
mem_gpr_write_dbg_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_gpr_write_dbg__0\,
      Q => mem_gpr_write_dbg,
      R => flush_pipe
    );
mem_gpr_write_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => reset_bool_for_rst,
      I1 => wb_exception,
      O => flush_pipe
    );
mem_gpr_write_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => ex_gpr_write_reg_n_0,
      Q => mem_gpr_write,
      R => flush_pipe
    );
\mem_instr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[0]\,
      Q => mem_instr(0),
      R => '0'
    );
\mem_instr_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[10]\,
      Q => mem_instr(10),
      R => '0'
    );
\mem_instr_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[11]\,
      Q => mem_instr(11),
      R => '0'
    );
\mem_instr_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[12]\,
      Q => mem_instr(12),
      R => '0'
    );
\mem_instr_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[13]\,
      Q => mem_instr(13),
      R => '0'
    );
\mem_instr_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[14]\,
      Q => mem_instr(14),
      R => '0'
    );
\mem_instr_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[15]\,
      Q => mem_instr(15),
      R => '0'
    );
\mem_instr_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[16]\,
      Q => mem_instr(16),
      R => '0'
    );
\mem_instr_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[17]\,
      Q => mem_instr(17),
      R => '0'
    );
\mem_instr_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[18]\,
      Q => mem_instr(18),
      R => '0'
    );
\mem_instr_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[19]\,
      Q => mem_instr(19),
      R => '0'
    );
\mem_instr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[1]\,
      Q => mem_instr(1),
      R => '0'
    );
\mem_instr_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[20]\,
      Q => mem_instr(20),
      R => '0'
    );
\mem_instr_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[21]\,
      Q => mem_instr(21),
      R => '0'
    );
\mem_instr_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[22]\,
      Q => mem_instr(22),
      R => '0'
    );
\mem_instr_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[23]\,
      Q => mem_instr(23),
      R => '0'
    );
\mem_instr_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[24]\,
      Q => mem_instr(24),
      R => '0'
    );
\mem_instr_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[25]\,
      Q => mem_instr(25),
      R => '0'
    );
\mem_instr_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[26]\,
      Q => mem_instr(26),
      R => '0'
    );
\mem_instr_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[27]\,
      Q => mem_instr(27),
      R => '0'
    );
\mem_instr_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[28]\,
      Q => mem_instr(28),
      R => '0'
    );
\mem_instr_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[29]\,
      Q => mem_instr(29),
      R => '0'
    );
\mem_instr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[2]\,
      Q => mem_instr(2),
      R => '0'
    );
\mem_instr_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[30]\,
      Q => mem_instr(30),
      R => '0'
    );
\mem_instr_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[31]\,
      Q => mem_instr(31),
      R => '0'
    );
\mem_instr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[3]\,
      Q => mem_instr(3),
      R => '0'
    );
\mem_instr_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[4]\,
      Q => mem_instr(4),
      R => '0'
    );
\mem_instr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[5]\,
      Q => mem_instr(5),
      R => '0'
    );
\mem_instr_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => p_1_in124_in,
      Q => mem_instr(6),
      R => '0'
    );
\mem_instr_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => p_0_in123_in,
      Q => mem_instr(7),
      R => '0'
    );
\mem_instr_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[8]\,
      Q => mem_instr(8),
      R => '0'
    );
\mem_instr_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => \ex_instr_reg_n_0_[9]\,
      Q => mem_instr(9),
      R => '0'
    );
mem_is_msr_instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => ex_mfsmsr_i,
      Q => mem_sel_msr,
      R => reset_bool_for_rst
    );
mem_is_multi_or_load_instr_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => mem_is_multi_or_load_instr0,
      Q => mem_is_multi_or_load_instr,
      R => reset_bool_for_rst
    );
mem_jump_taken_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => mem_jump_taken0,
      Q => mem_jump_taken,
      R => reset_bool_for_rst
    );
mem_load_store_access_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => mem_load_store_access0,
      Q => mem_load_store_access,
      R => reset_bool_for_rst
    );
mem_read_imm_reg_1_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => ex_read_imm_reg_1,
      Q => mem_read_imm_reg_1,
      R => reset_bool_for_rst
    );
mem_read_imm_reg_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_1\,
      D => ex_read_imm_reg,
      Q => mem_read_imm_reg,
      R => reset_bool_for_rst
    );
mem_valid_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => mem_PipeRun_carry_and_n_1,
      Q => mem_valid_instr,
      R => '0'
    );
mem_wait_on_ready_N_carry_or: entity work.design_1_microblaze_0_0_carry_or
     port map (
      MEM_DataBus_Ready => MEM_DataBus_Ready,
      lopt => lopt_11,
      lopt_1 => lopt_12,
      lopt_10 => lopt_48,
      lopt_11 => lopt_49,
      lopt_12 => lopt_50,
      lopt_13 => lopt_24,
      lopt_14 => lopt_22,
      lopt_15 => lopt_20,
      lopt_16 => lopt_51,
      lopt_17 => \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0\,
      lopt_18 => A,
      lopt_19 => PreFetch_Buffer_I1_n_191,
      lopt_2 => lopt_13,
      lopt_20 => lopt_52,
      lopt_3 => lopt_14,
      lopt_4 => lopt_15,
      lopt_5 => lopt_16,
      lopt_6 => lopt_17,
      lopt_7 => lopt_18,
      lopt_8 => jump_logic_I1_n_42,
      lopt_9 => lopt_47,
      mem_Write_DCache => mem_Write_DCache,
      mem_load_store_access => mem_load_store_access,
      mem_valid_instr => mem_valid_instr,
      mem_wait_on_ready_N => mem_wait_on_ready_N
    );
of_pause_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Pause,
      Q => \^of_pause\,
      R => reset_bool_for_rst
    );
of_read_imm_reg_ii_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFEA"
    )
        port map (
      I0 => \^lockstep_master_out\(0),
      I1 => mem_valid_instr,
      I2 => mem_exception_from_ex,
      I3 => wb_exception,
      I4 => reset_bool_for_rst,
      I5 => ex_Exception_Taken,
      O => of_read_imm_reg_ii_i_2_n_0
    );
of_read_imm_reg_ii_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \Use_MuxCy[11].OF_Piperun_Stage_n_2\,
      Q => of_read_imm_reg_ii,
      R => '0'
    );
sign_byte_inferred_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"02"
    )
        port map (
      I0 => \Using_FPGA.Native_42\(7),
      I1 => \^ex_sext_op_reg[0]_0\(0),
      I2 => \^ex_sext_op_reg[0]_0\(1),
      O => in0
    );
wb_PipeRun_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^using_fpga.native_0\,
      Q => \^wb_piperun_i_reg_0\(0),
      R => reset_bool_for_rst
    );
wb_exception_i_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => mem_exception_from_ex,
      I1 => mem_valid_instr,
      O => \^mem_exception_taken\
    );
wb_exception_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => \^mem_exception_taken\,
      Q => wb_exception,
      R => reset_bool_for_rst
    );
\wb_exception_kind_i_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_exception_kind(28),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(3),
      R => reset_bool_for_rst
    );
\wb_exception_kind_i_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_exception_kind(31),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(2),
      R => reset_bool_for_rst
    );
\wb_gpr_write_addr_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_gpr_write_addr(0),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(33),
      R => reset_bool_for_rst
    );
\wb_gpr_write_addr_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_gpr_write_addr(1),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(32),
      R => reset_bool_for_rst
    );
\wb_gpr_write_addr_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_gpr_write_addr(2),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(31),
      R => reset_bool_for_rst
    );
\wb_gpr_write_addr_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_gpr_write_addr(3),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(30),
      R => reset_bool_for_rst
    );
\wb_gpr_write_addr_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_gpr_write_addr(4),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(29),
      R => reset_bool_for_rst
    );
wb_gpr_write_dbg_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => wb_gpr_write_dbg0,
      Q => \^wb_gpr_wr_dbg\,
      R => '0'
    );
wb_gpr_write_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => wb_gpr_write_i0,
      Q => wb_gpr_write_i,
      R => '0'
    );
\wb_instr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(0),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(67),
      R => '0'
    );
\wb_instr_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(10),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(57),
      R => '0'
    );
\wb_instr_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(11),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(56),
      R => '0'
    );
\wb_instr_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(12),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(55),
      R => '0'
    );
\wb_instr_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(13),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(54),
      R => '0'
    );
\wb_instr_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(14),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(53),
      R => '0'
    );
\wb_instr_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(15),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(52),
      R => '0'
    );
\wb_instr_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(16),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(51),
      R => '0'
    );
\wb_instr_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(17),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(50),
      R => '0'
    );
\wb_instr_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(18),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(49),
      R => '0'
    );
\wb_instr_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(19),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(48),
      R => '0'
    );
\wb_instr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(1),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(66),
      R => '0'
    );
\wb_instr_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(20),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(47),
      R => '0'
    );
\wb_instr_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(21),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(46),
      R => '0'
    );
\wb_instr_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(22),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(45),
      R => '0'
    );
\wb_instr_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(23),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(44),
      R => '0'
    );
\wb_instr_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(24),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(43),
      R => '0'
    );
\wb_instr_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(25),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(42),
      R => '0'
    );
\wb_instr_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(26),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(41),
      R => '0'
    );
\wb_instr_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(27),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(40),
      R => '0'
    );
\wb_instr_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(28),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(39),
      R => '0'
    );
\wb_instr_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(29),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(38),
      R => '0'
    );
\wb_instr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(2),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(65),
      R => '0'
    );
\wb_instr_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(30),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(37),
      R => '0'
    );
\wb_instr_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(31),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(36),
      R => '0'
    );
\wb_instr_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(3),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(64),
      R => '0'
    );
\wb_instr_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(4),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(63),
      R => '0'
    );
\wb_instr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(5),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(62),
      R => '0'
    );
\wb_instr_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(6),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(61),
      R => '0'
    );
\wb_instr_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(7),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(60),
      R => '0'
    );
\wb_instr_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(8),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(59),
      R => '0'
    );
\wb_instr_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => \^using_fpga.native_0\,
      D => mem_instr(9),
      Q => \^performance_debug_control.dbg_state_nohalt_reg\(58),
      R => '0'
    );
wb_reset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => Clk,
      CE => '1',
      D => reset_bool_for_rst,
      Q => wb_reset,
      R => '0'
    );
wb_valid_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => mem_PipeRun_carry_and_n_2,
      Q => \^wb_valid_reg_0\,
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_instr_mux is
  port (
    I139_out : out STD_LOGIC;
    Y : out STD_LOGIC_VECTOR ( 0 to 31 );
    \in\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
    LOCKSTEP_Master_Out : in STD_LOGIC_VECTOR ( 32 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_instr_mux : entity is "instr_mux";
end design_1_microblaze_0_0_instr_mux;

architecture STRUCTURE of design_1_microblaze_0_0_instr_mux is
begin
\Mux_LD.LD_inst\: entity work.design_1_microblaze_0_0_mux_bus
     port map (
      I139_out => I139_out,
      Instr(0 to 31) => Instr(0 to 31),
      LOCKSTEP_Master_Out(32 downto 0) => LOCKSTEP_Master_Out(32 downto 0),
      \Using_FPGA.Native\(0) => \Using_FPGA.Native\(0),
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native_0\(0),
      Y(0 to 31) => Y(0 to 31),
      \in\(0) => \in\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_Data_Flow_gti is
  port (
    \EX_Op1_reg[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    \out\ : out STD_LOGIC;
    \EX_Op1_reg[24]\ : out STD_LOGIC;
    ex_op1_zero : out STD_LOGIC;
    ex_MSR : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DI : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC;
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    \Using_FPGA.Native_1\ : out STD_LOGIC;
    \Using_FPGA.Native_2\ : out STD_LOGIC;
    \Using_FPGA.Native_3\ : out STD_LOGIC;
    \Using_FPGA.Native_4\ : out STD_LOGIC;
    \Using_FPGA.Native_5\ : out STD_LOGIC;
    \Using_FPGA.Native_6\ : out STD_LOGIC;
    \Using_FPGA.Native_7\ : out STD_LOGIC;
    \Using_FPGA.Native_8\ : out STD_LOGIC;
    \Using_FPGA.Native_9\ : out STD_LOGIC;
    \Using_FPGA.Native_10\ : out STD_LOGIC;
    \Using_FPGA.Native_11\ : out STD_LOGIC;
    \Using_FPGA.Native_12\ : out STD_LOGIC;
    \Using_FPGA.Native_13\ : out STD_LOGIC;
    \Using_FPGA.Native_14\ : out STD_LOGIC;
    \Using_FPGA.Native_15\ : out STD_LOGIC;
    \Using_FPGA.Native_16\ : out STD_LOGIC;
    \Using_FPGA.Native_17\ : out STD_LOGIC;
    \Using_FPGA.Native_18\ : out STD_LOGIC;
    \Using_FPGA.Native_19\ : out STD_LOGIC;
    \Using_FPGA.Native_20\ : out STD_LOGIC;
    \Using_FPGA.Native_21\ : out STD_LOGIC;
    \Using_FPGA.Native_22\ : out STD_LOGIC;
    \Using_FPGA.Native_23\ : out STD_LOGIC;
    \Using_FPGA.Native_24\ : out STD_LOGIC;
    \Using_FPGA.Native_25\ : out STD_LOGIC;
    \Using_FPGA.Native_26\ : out STD_LOGIC;
    \Using_FPGA.Native_27\ : out STD_LOGIC;
    \Using_FPGA.Native_28\ : out STD_LOGIC;
    \EX_Op2_reg[0]\ : out STD_LOGIC_VECTOR ( 91 downto 0 );
    \Using_FPGA.Native_29\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]\ : out STD_LOGIC;
    wb_read_msb_doublet_sel : out STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op1_reg[28]\ : out STD_LOGIC;
    wb_gpr_write_dbg_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \WB_MEM_Result_reg[0]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
    swap_result : out STD_LOGIC_VECTOR ( 23 downto 0 );
    swap_result_reg : out STD_LOGIC_VECTOR ( 0 to 7 );
    MEM_Fwd : out STD_LOGIC_VECTOR ( 0 to 31 );
    \EX_Op3_reg[0]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
    GPR_Op1 : out STD_LOGIC_VECTOR ( 0 to 31 );
    GPR_Op2 : out STD_LOGIC_VECTOR ( 0 to 31 );
    GPR_Op3 : out STD_LOGIC_VECTOR ( 0 to 31 );
    \imm_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_databus_addr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    of_op1_sel_spr : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 31 downto 0 );
    I1 : in STD_LOGIC;
    \EX_Op1_reg[1]\ : in STD_LOGIC;
    \EX_Op1_reg[2]\ : in STD_LOGIC;
    \EX_Op1_reg[3]\ : in STD_LOGIC;
    \EX_Op1_reg[4]\ : in STD_LOGIC;
    \EX_Op1_reg[5]\ : in STD_LOGIC;
    \EX_Op1_reg[6]\ : in STD_LOGIC;
    \EX_Op1_reg[7]\ : in STD_LOGIC;
    \EX_Op1_reg[8]\ : in STD_LOGIC;
    \EX_Op1_reg[9]\ : in STD_LOGIC;
    \EX_Op1_reg[10]\ : in STD_LOGIC;
    \EX_Op1_reg[11]\ : in STD_LOGIC;
    \EX_Op1_reg[12]\ : in STD_LOGIC;
    \EX_Op1_reg[13]\ : in STD_LOGIC;
    \EX_Op1_reg[14]\ : in STD_LOGIC;
    \EX_Op1_reg[15]\ : in STD_LOGIC;
    \EX_Op1_reg[16]\ : in STD_LOGIC;
    \EX_Op1_reg[17]\ : in STD_LOGIC;
    \EX_Op1_reg[18]\ : in STD_LOGIC;
    \EX_Op1_reg[19]\ : in STD_LOGIC;
    \EX_Op1_reg[20]\ : in STD_LOGIC;
    \EX_Op1_reg[21]\ : in STD_LOGIC;
    \EX_Op1_reg[22]\ : in STD_LOGIC;
    \EX_Op1_reg[23]\ : in STD_LOGIC;
    \EX_Op1_reg[24]_0\ : in STD_LOGIC;
    \EX_Op1_reg[25]\ : in STD_LOGIC;
    \EX_Op1_reg[26]\ : in STD_LOGIC;
    \EX_Op1_reg[27]\ : in STD_LOGIC;
    \EX_Op1_reg[28]_0\ : in STD_LOGIC;
    \EX_Op1_reg[29]\ : in STD_LOGIC;
    \EX_Op1_reg[30]\ : in STD_LOGIC;
    \EX_Op1_reg[31]\ : in STD_LOGIC;
    ex_use_carry : in STD_LOGIC;
    DI_0 : in STD_LOGIC;
    ex_unsigned_op : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
    EX_ALU_Sel_Logic : in STD_LOGIC;
    EX_Enable_ALU : in STD_LOGIC;
    in0 : in STD_LOGIC;
    ex_op1_cmp_equal : in STD_LOGIC;
    ex_op1_cmp_equal_n : in STD_LOGIC;
    R : in STD_LOGIC;
    \Using_FPGA.Native_30\ : in STD_LOGIC;
    EX_Fwd : in STD_LOGIC_VECTOR ( 0 to 31 );
    Clk : in STD_LOGIC;
    sync_reset : in STD_LOGIC;
    \Using_FPGA.Native_31\ : in STD_LOGIC;
    \Using_FPGA.Native_32\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_33\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \Using_FPGA.Native_34\ : in STD_LOGIC;
    \Using_FPGA.Native_35\ : in STD_LOGIC;
    I1_1 : in STD_LOGIC;
    ex_reverse_mem_access : in STD_LOGIC;
    p_231_in : in STD_LOGIC;
    \Using_FPGA.Native_36\ : in STD_LOGIC;
    ex_MSR_Load_ALU_C : in STD_LOGIC;
    \ex_swx_access__0\ : in STD_LOGIC;
    ex_MSR_Load_Shift_C : in STD_LOGIC;
    ex_MSR_Load_LWX_SWX_C : in STD_LOGIC;
    ex_move_to_MSR_instr : in STD_LOGIC;
    \Using_FPGA.Native_37\ : in STD_LOGIC;
    \Using_FPGA.Native_38\ : in STD_LOGIC;
    ex_valid : in STD_LOGIC;
    ex_cmp_op : in STD_LOGIC;
    ex_byte_access : in STD_LOGIC;
    ex_doublet_access : in STD_LOGIC;
    wb_gpr_wr_dbg : in STD_LOGIC;
    \data_rd_reg_reg[23]\ : in STD_LOGIC;
    \data_rd_reg_reg[23]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3030]\ : in STD_LOGIC;
    wb_byte_access : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3024]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3026]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3028]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3030]_0\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3029]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3027]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3025]\ : in STD_LOGIC;
    \LOCKSTEP_Out_reg[3023]\ : in STD_LOGIC;
    \Using_FPGA.Native_i_3__31\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ex_swap_byte_instr : in STD_LOGIC;
    mem_sel_msr : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[18]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[0]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[0]_1\ : in STD_LOGIC;
    of_gpr_op1_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    of_imm_data : in STD_LOGIC_VECTOR ( 0 to 15 );
    of_gpr_op3_rd_addr : in STD_LOGIC_VECTOR ( 0 to 4 );
    \EX_Branch_CMP_Op1_reg[18]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \EX_Branch_CMP_Op1_reg[2]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[2]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[4]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[4]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[6]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[6]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[8]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[8]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[10]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[10]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[12]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[12]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[14]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[14]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[24]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[24]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[26]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[26]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[28]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[28]_0\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[30]\ : in STD_LOGIC;
    \EX_Branch_CMP_Op1_reg[30]_0\ : in STD_LOGIC;
    E : in STD_LOGIC_VECTOR ( 0 to 0 );
    \EX_Op3_reg[31]\ : in STD_LOGIC;
    \EX_Op2_reg[0]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \EX_Op3_reg[0]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
    \MEM_DataBus_Write_Data_reg[0]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \wb_MSR_i_reg[30]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    mem_byte_access : in STD_LOGIC;
    mem_doublet_access : in STD_LOGIC;
    lopt : out STD_LOGIC;
    lopt_1 : in STD_LOGIC;
    lopt_2 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_Data_Flow_gti : entity is "Data_Flow_gti";
end design_1_microblaze_0_0_Data_Flow_gti;

architecture STRUCTURE of design_1_microblaze_0_0_Data_Flow_gti is
  signal \^ex_branch_cmp_op1_reg[0]\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^ex_op1_reg[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^ex_op2_reg[0]\ : STD_LOGIC_VECTOR ( 91 downto 0 );
  signal MEM_EX_Result : STD_LOGIC_VECTOR ( 0 to 30 );
  signal \^mem_fwd\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal Operand_Select_I_n_0 : STD_LOGIC;
  signal Operand_Select_I_n_150 : STD_LOGIC;
  signal Operand_Select_I_n_181 : STD_LOGIC;
  signal Operand_Select_I_n_33 : STD_LOGIC;
  signal Operand_Select_I_n_64 : STD_LOGIC;
  signal Operand_Select_I_n_65 : STD_LOGIC;
  signal Operand_Select_I_n_66 : STD_LOGIC;
  signal Operand_Select_I_n_67 : STD_LOGIC;
  signal Operand_Select_I_n_83 : STD_LOGIC;
  signal Operand_Select_I_n_85 : STD_LOGIC;
  signal \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I0\ : STD_LOGIC;
  signal \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I2\ : STD_LOGIC;
  signal \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/S\ : STD_LOGIC;
  signal \^ex_msr\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal ex_alu_carry_32 : STD_LOGIC;
  signal ex_alu_carryin : STD_LOGIC;
  signal ex_branch_cmp_op1 : STD_LOGIC_VECTOR ( 1 to 29 );
  signal ex_op2 : STD_LOGIC_VECTOR ( 0 to 27 );
  signal ex_pre_alu_carry : STD_LOGIC;
  signal \^lopt\ : STD_LOGIC;
  signal \^lopt_1\ : STD_LOGIC;
  signal lopt_10 : STD_LOGIC;
  signal lopt_11 : STD_LOGIC;
  signal lopt_12 : STD_LOGIC;
  signal lopt_13 : STD_LOGIC;
  signal lopt_14 : STD_LOGIC;
  signal lopt_15 : STD_LOGIC;
  signal lopt_16 : STD_LOGIC;
  signal lopt_17 : STD_LOGIC;
  signal lopt_18 : STD_LOGIC;
  signal lopt_19 : STD_LOGIC;
  signal \^lopt_2\ : STD_LOGIC;
  signal lopt_20 : STD_LOGIC;
  signal lopt_21 : STD_LOGIC;
  signal lopt_22 : STD_LOGIC;
  signal lopt_23 : STD_LOGIC;
  signal lopt_24 : STD_LOGIC;
  signal lopt_25 : STD_LOGIC;
  signal lopt_26 : STD_LOGIC;
  signal lopt_3 : STD_LOGIC;
  signal lopt_4 : STD_LOGIC;
  signal lopt_5 : STD_LOGIC;
  signal lopt_6 : STD_LOGIC;
  signal lopt_7 : STD_LOGIC;
  signal lopt_8 : STD_LOGIC;
  signal lopt_9 : STD_LOGIC;
  signal muxcy_di : STD_LOGIC;
  signal muxcy_sel : STD_LOGIC;
  signal wb_mem_result : STD_LOGIC_VECTOR ( 16 to 23 );
begin
  \EX_Branch_CMP_Op1_reg[0]\(0) <= \^ex_branch_cmp_op1_reg[0]\(0);
  \EX_Op1_reg[0]\(31 downto 0) <= \^ex_op1_reg[0]\(31 downto 0);
  \EX_Op2_reg[0]\(91 downto 0) <= \^ex_op2_reg[0]\(91 downto 0);
  MEM_Fwd(0 to 31) <= \^mem_fwd\(0 to 31);
  ex_MSR(2 downto 0) <= \^ex_msr\(2 downto 0);
  lopt <= lopt_8;
  lopt_10 <= lopt_2;
  lopt_9 <= lopt_1;
ALU_I: entity work.design_1_microblaze_0_0_ALU
     port map (
      DI_0 => DI_0,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      \EX_Op2_reg[0]\(29 downto 0) => \^ex_op2_reg[0]\(91 downto 62),
      I0 => \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I0\,
      I2 => \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I2\,
      LO => ex_alu_carry_32,
      \MEM_DataBus_Addr_reg[9]\(1 downto 0) => Q(1 downto 0),
      Q(31) => ex_op2(0),
      Q(30) => ex_op2(1),
      Q(29) => ex_op2(2),
      Q(28) => ex_op2(3),
      Q(27) => ex_op2(4),
      Q(26) => ex_op2(5),
      Q(25) => ex_op2(6),
      Q(24) => ex_op2(7),
      Q(23) => ex_op2(8),
      Q(22) => ex_op2(9),
      Q(21) => ex_op2(10),
      Q(20) => ex_op2(11),
      Q(19) => ex_op2(12),
      Q(18) => ex_op2(13),
      Q(17) => ex_op2(14),
      Q(16) => ex_op2(15),
      Q(15) => ex_op2(16),
      Q(14) => ex_op2(17),
      Q(13) => ex_op2(18),
      Q(12) => ex_op2(19),
      Q(11) => ex_op2(20),
      Q(10) => ex_op2(21),
      Q(9) => ex_op2(22),
      Q(8) => ex_op2(23),
      Q(7) => ex_op2(24),
      Q(6) => ex_op2(25),
      Q(5) => ex_op2(26),
      Q(4) => ex_op2(27),
      Q(3) => Operand_Select_I_n_64,
      Q(2) => Operand_Select_I_n_65,
      Q(1) => Operand_Select_I_n_66,
      Q(0) => Operand_Select_I_n_67,
      S => \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/S\,
      \Using_FPGA.Native\(31 downto 0) => \^ex_op1_reg[0]\(31 downto 0),
      ex_alu_carryin => ex_alu_carryin,
      ex_databus_addr(1 downto 0) => ex_databus_addr(1 downto 0),
      ex_unsigned_op => ex_unsigned_op,
      ex_use_carry => ex_use_carry,
      lopt => lopt_3,
      lopt_1 => lopt_4,
      lopt_10 => lopt_16,
      lopt_11 => lopt_17,
      lopt_12 => lopt_18,
      lopt_13 => lopt_19,
      lopt_14 => lopt_20,
      lopt_15 => lopt_21,
      lopt_16 => lopt_22,
      lopt_17 => lopt_23,
      lopt_18 => lopt_24,
      lopt_19 => lopt_25,
      lopt_2 => lopt_5,
      lopt_20 => lopt_26,
      lopt_3 => lopt_6,
      lopt_4 => lopt_7,
      lopt_5 => lopt_11,
      lopt_6 => lopt_12,
      lopt_7 => lopt_13,
      lopt_8 => lopt_14,
      lopt_9 => lopt_15
    );
Byte_Doublet_Handle_gti_I: entity work.design_1_microblaze_0_0_Byte_Doublet_Handle_gti
     port map (
      Clk => Clk,
      D(31 downto 16) => \MEM_DataBus_Write_Data_reg[0]\(23 downto 8),
      D(15 downto 8) => \^ex_op2_reg[0]\(59 downto 52),
      D(7 downto 0) => \MEM_DataBus_Write_Data_reg[0]\(7 downto 0),
      \MEM_DataBus_Byte_Enable_reg[0]_0\(3 downto 0) => \^ex_op2_reg[0]\(51 downto 48),
      \MEM_DataBus_Write_Data_reg[0]_0\(35 downto 0) => \^ex_op2_reg[0]\(47 downto 12),
      \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0\ => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]\,
      \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0\(1 downto 0) => \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]\(1 downto 0),
      \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0\ => \Using_FPGA.Native_35\,
      ex_reverse_mem_access => ex_reverse_mem_access,
      mem_byte_access => mem_byte_access,
      \mem_byte_selects_reg[0]_0\ => Operand_Select_I_n_83,
      \mem_byte_selects_reg[1]_0\(0) => Operand_Select_I_n_181,
      mem_doublet_access => mem_doublet_access,
      mem_reverse_byteorder_reg_0 => \Using_FPGA.Native_30\,
      sync_reset => sync_reset,
      wb_read_msb_doublet_sel => wb_read_msb_doublet_sel
    );
Data_Flow_Logic_I: entity work.design_1_microblaze_0_0_Data_Flow_Logic
     port map (
      Clk => Clk,
      EX_Fwd(0 to 31) => EX_Fwd(0 to 31),
      MEM_Fwd(27) => \^mem_fwd\(1),
      MEM_Fwd(26) => \^mem_fwd\(2),
      MEM_Fwd(25) => \^mem_fwd\(3),
      MEM_Fwd(24) => \^mem_fwd\(4),
      MEM_Fwd(23) => \^mem_fwd\(5),
      MEM_Fwd(22) => \^mem_fwd\(6),
      MEM_Fwd(21) => \^mem_fwd\(7),
      MEM_Fwd(20) => \^mem_fwd\(8),
      MEM_Fwd(19) => \^mem_fwd\(9),
      MEM_Fwd(18) => \^mem_fwd\(10),
      MEM_Fwd(17) => \^mem_fwd\(11),
      MEM_Fwd(16) => \^mem_fwd\(12),
      MEM_Fwd(15) => \^mem_fwd\(13),
      MEM_Fwd(14) => \^mem_fwd\(14),
      MEM_Fwd(13) => \^mem_fwd\(15),
      MEM_Fwd(12) => \^mem_fwd\(16),
      MEM_Fwd(11) => \^mem_fwd\(17),
      MEM_Fwd(10) => \^mem_fwd\(18),
      MEM_Fwd(9) => \^mem_fwd\(19),
      MEM_Fwd(8) => \^mem_fwd\(20),
      MEM_Fwd(7) => \^mem_fwd\(21),
      MEM_Fwd(6) => \^mem_fwd\(22),
      MEM_Fwd(5) => \^mem_fwd\(23),
      MEM_Fwd(4) => \^mem_fwd\(24),
      MEM_Fwd(3) => \^mem_fwd\(25),
      MEM_Fwd(2) => \^mem_fwd\(26),
      MEM_Fwd(1) => \^mem_fwd\(27),
      MEM_Fwd(0) => \^mem_fwd\(31),
      Q(31 downto 16) => \WB_MEM_Result_reg[0]\(23 downto 8),
      Q(15) => wb_mem_result(16),
      Q(14) => wb_mem_result(17),
      Q(13) => wb_mem_result(18),
      Q(12) => wb_mem_result(19),
      Q(11) => wb_mem_result(20),
      Q(10) => wb_mem_result(21),
      Q(9) => wb_mem_result(22),
      Q(8) => wb_mem_result(23),
      Q(7 downto 0) => \WB_MEM_Result_reg[0]\(7 downto 0),
      R => R,
      SR(0) => SR(0),
      \Using_FPGA.Native\(3) => MEM_EX_Result(0),
      \Using_FPGA.Native\(2) => MEM_EX_Result(28),
      \Using_FPGA.Native\(1) => MEM_EX_Result(29),
      \Using_FPGA.Native\(0) => MEM_EX_Result(30),
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_30\,
      \WB_MEM_Result_reg[0]_0\ => \Using_FPGA.Native_35\,
      \WB_MEM_Result_reg[0]_1\(3) => \^mem_fwd\(0),
      \WB_MEM_Result_reg[0]_1\(2) => \^mem_fwd\(28),
      \WB_MEM_Result_reg[0]_1\(1) => \^mem_fwd\(29),
      \WB_MEM_Result_reg[0]_1\(0) => \^mem_fwd\(30),
      mem_sel_msr => mem_sel_msr
    );
Operand_Select_I: entity work.design_1_microblaze_0_0_Operand_Select_gti
     port map (
      Clk => Clk,
      D(31 downto 0) => D(31 downto 0),
      E(0) => E(0),
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      \EX_Branch_CMP_Op1_reg[0]_0\(29) => \^ex_branch_cmp_op1_reg[0]\(0),
      \EX_Branch_CMP_Op1_reg[0]_0\(28) => ex_branch_cmp_op1(1),
      \EX_Branch_CMP_Op1_reg[0]_0\(27) => ex_branch_cmp_op1(2),
      \EX_Branch_CMP_Op1_reg[0]_0\(26) => ex_branch_cmp_op1(3),
      \EX_Branch_CMP_Op1_reg[0]_0\(25) => ex_branch_cmp_op1(4),
      \EX_Branch_CMP_Op1_reg[0]_0\(24) => ex_branch_cmp_op1(5),
      \EX_Branch_CMP_Op1_reg[0]_0\(23) => ex_branch_cmp_op1(6),
      \EX_Branch_CMP_Op1_reg[0]_0\(22) => ex_branch_cmp_op1(7),
      \EX_Branch_CMP_Op1_reg[0]_0\(21) => ex_branch_cmp_op1(8),
      \EX_Branch_CMP_Op1_reg[0]_0\(20) => ex_branch_cmp_op1(9),
      \EX_Branch_CMP_Op1_reg[0]_0\(19) => ex_branch_cmp_op1(10),
      \EX_Branch_CMP_Op1_reg[0]_0\(18) => ex_branch_cmp_op1(11),
      \EX_Branch_CMP_Op1_reg[0]_0\(17) => ex_branch_cmp_op1(12),
      \EX_Branch_CMP_Op1_reg[0]_0\(16) => ex_branch_cmp_op1(13),
      \EX_Branch_CMP_Op1_reg[0]_0\(15) => ex_branch_cmp_op1(14),
      \EX_Branch_CMP_Op1_reg[0]_0\(14) => ex_branch_cmp_op1(15),
      \EX_Branch_CMP_Op1_reg[0]_0\(13) => ex_branch_cmp_op1(16),
      \EX_Branch_CMP_Op1_reg[0]_0\(12) => ex_branch_cmp_op1(17),
      \EX_Branch_CMP_Op1_reg[0]_0\(11) => ex_branch_cmp_op1(18),
      \EX_Branch_CMP_Op1_reg[0]_0\(10) => ex_branch_cmp_op1(19),
      \EX_Branch_CMP_Op1_reg[0]_0\(9) => ex_branch_cmp_op1(20),
      \EX_Branch_CMP_Op1_reg[0]_0\(8) => ex_branch_cmp_op1(21),
      \EX_Branch_CMP_Op1_reg[0]_0\(7) => ex_branch_cmp_op1(22),
      \EX_Branch_CMP_Op1_reg[0]_0\(6) => ex_branch_cmp_op1(23),
      \EX_Branch_CMP_Op1_reg[0]_0\(5) => ex_branch_cmp_op1(24),
      \EX_Branch_CMP_Op1_reg[0]_0\(4) => ex_branch_cmp_op1(25),
      \EX_Branch_CMP_Op1_reg[0]_0\(3) => ex_branch_cmp_op1(26),
      \EX_Branch_CMP_Op1_reg[0]_0\(2) => ex_branch_cmp_op1(27),
      \EX_Branch_CMP_Op1_reg[0]_0\(1) => ex_branch_cmp_op1(28),
      \EX_Branch_CMP_Op1_reg[0]_0\(0) => ex_branch_cmp_op1(29),
      \EX_Branch_CMP_Op1_reg[30]_0\ => Operand_Select_I_n_150,
      \EX_Op1_reg[10]_0\ => \EX_Op1_reg[10]\,
      \EX_Op1_reg[11]_0\ => \EX_Op1_reg[11]\,
      \EX_Op1_reg[12]_0\ => \EX_Op1_reg[12]\,
      \EX_Op1_reg[13]_0\ => \EX_Op1_reg[13]\,
      \EX_Op1_reg[14]_0\ => \EX_Op1_reg[14]\,
      \EX_Op1_reg[15]_0\ => \EX_Op1_reg[15]\,
      \EX_Op1_reg[16]_0\ => \EX_Op1_reg[16]\,
      \EX_Op1_reg[17]_0\ => \EX_Op1_reg[17]\,
      \EX_Op1_reg[18]_0\ => \EX_Op1_reg[18]\,
      \EX_Op1_reg[19]_0\ => \EX_Op1_reg[19]\,
      \EX_Op1_reg[1]_0\ => \EX_Op1_reg[1]\,
      \EX_Op1_reg[20]_0\ => \EX_Op1_reg[20]\,
      \EX_Op1_reg[21]_0\ => \EX_Op1_reg[21]\,
      \EX_Op1_reg[22]_0\ => \EX_Op1_reg[22]\,
      \EX_Op1_reg[23]_0\ => \EX_Op1_reg[23]\,
      \EX_Op1_reg[24]_0\ => \EX_Op1_reg[24]_0\,
      \EX_Op1_reg[25]_0\ => \EX_Op1_reg[25]\,
      \EX_Op1_reg[26]_0\ => \EX_Op1_reg[26]\,
      \EX_Op1_reg[27]_0\ => \EX_Op1_reg[27]\,
      \EX_Op1_reg[28]_0\ => \EX_Op1_reg[28]\,
      \EX_Op1_reg[28]_1\ => \EX_Op1_reg[28]_0\,
      \EX_Op1_reg[29]_0\ => \EX_Op1_reg[29]\,
      \EX_Op1_reg[2]_0\ => \EX_Op1_reg[2]\,
      \EX_Op1_reg[30]_0\ => Operand_Select_I_n_33,
      \EX_Op1_reg[30]_1\ => \EX_Op1_reg[30]\,
      \EX_Op1_reg[31]_0\ => \EX_Op1_reg[31]\,
      \EX_Op1_reg[3]_0\ => \EX_Op1_reg[3]\,
      \EX_Op1_reg[4]_0\ => \EX_Op1_reg[4]\,
      \EX_Op1_reg[5]_0\ => \EX_Op1_reg[5]\,
      \EX_Op1_reg[6]_0\ => \EX_Op1_reg[6]\,
      \EX_Op1_reg[7]_0\ => \EX_Op1_reg[7]\,
      \EX_Op1_reg[8]_0\ => \EX_Op1_reg[8]\,
      \EX_Op1_reg[9]_0\ => \EX_Op1_reg[9]\,
      \EX_Op2_reg[0]_0\(31) => ex_op2(0),
      \EX_Op2_reg[0]_0\(30) => ex_op2(1),
      \EX_Op2_reg[0]_0\(29) => ex_op2(2),
      \EX_Op2_reg[0]_0\(28) => ex_op2(3),
      \EX_Op2_reg[0]_0\(27) => ex_op2(4),
      \EX_Op2_reg[0]_0\(26) => ex_op2(5),
      \EX_Op2_reg[0]_0\(25) => ex_op2(6),
      \EX_Op2_reg[0]_0\(24) => ex_op2(7),
      \EX_Op2_reg[0]_0\(23) => ex_op2(8),
      \EX_Op2_reg[0]_0\(22) => ex_op2(9),
      \EX_Op2_reg[0]_0\(21) => ex_op2(10),
      \EX_Op2_reg[0]_0\(20) => ex_op2(11),
      \EX_Op2_reg[0]_0\(19) => ex_op2(12),
      \EX_Op2_reg[0]_0\(18) => ex_op2(13),
      \EX_Op2_reg[0]_0\(17) => ex_op2(14),
      \EX_Op2_reg[0]_0\(16) => ex_op2(15),
      \EX_Op2_reg[0]_0\(15) => ex_op2(16),
      \EX_Op2_reg[0]_0\(14) => ex_op2(17),
      \EX_Op2_reg[0]_0\(13) => ex_op2(18),
      \EX_Op2_reg[0]_0\(12) => ex_op2(19),
      \EX_Op2_reg[0]_0\(11) => ex_op2(20),
      \EX_Op2_reg[0]_0\(10) => ex_op2(21),
      \EX_Op2_reg[0]_0\(9) => ex_op2(22),
      \EX_Op2_reg[0]_0\(8) => ex_op2(23),
      \EX_Op2_reg[0]_0\(7) => ex_op2(24),
      \EX_Op2_reg[0]_0\(6) => ex_op2(25),
      \EX_Op2_reg[0]_0\(5) => ex_op2(26),
      \EX_Op2_reg[0]_0\(4) => ex_op2(27),
      \EX_Op2_reg[0]_0\(3) => Operand_Select_I_n_64,
      \EX_Op2_reg[0]_0\(2) => Operand_Select_I_n_65,
      \EX_Op2_reg[0]_0\(1) => Operand_Select_I_n_66,
      \EX_Op2_reg[0]_0\(0) => Operand_Select_I_n_67,
      \EX_Op2_reg[0]_1\(31 downto 0) => \EX_Op2_reg[0]_0\(31 downto 0),
      \EX_Op3_reg[0]_0\(31 downto 0) => \EX_Op3_reg[0]\(31 downto 0),
      \EX_Op3_reg[0]_1\(31 downto 0) => \EX_Op3_reg[0]_0\(31 downto 0),
      \EX_Op3_reg[31]_0\ => \EX_Op3_reg[31]\,
      I0 => \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I0\,
      I1 => I1,
      I2 => \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I2\,
      LO => ex_alu_carry_32,
      Q(31 downto 0) => \^ex_op1_reg[0]\(31 downto 0),
      S => \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/S\,
      \Using_FPGA.Native\(13 downto 0) => \^ex_op2_reg[0]\(61 downto 48),
      \Using_FPGA.Native_0\ => Operand_Select_I_n_83,
      \Using_FPGA.Native_1\(0) => Operand_Select_I_n_181,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_36\,
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_30\,
      \Using_FPGA.Native_4\ => \^ex_msr\(1),
      \Using_FPGA.Native_5\ => \Using_FPGA.Native_37\,
      \Using_FPGA.Native_6\ => \Using_FPGA.Native_38\,
      \Using_FPGA.Native_i_3__31\(1 downto 0) => \Using_FPGA.Native_i_3__31\(1 downto 0),
      ex_MSR(1) => \^ex_msr\(2),
      ex_MSR(0) => \^ex_msr\(0),
      ex_MSR_Load_ALU_C => ex_MSR_Load_ALU_C,
      ex_MSR_Load_LWX_SWX_C => ex_MSR_Load_LWX_SWX_C,
      ex_MSR_Load_Shift_C => ex_MSR_Load_Shift_C,
      ex_byte_access => ex_byte_access,
      ex_cmp_op => ex_cmp_op,
      ex_doublet_access => ex_doublet_access,
      ex_load_alu_carry_reg => Operand_Select_I_n_0,
      ex_move_to_MSR_instr => ex_move_to_MSR_instr,
      ex_reverse_mem_access => ex_reverse_mem_access,
      ex_swap_byte_instr => ex_swap_byte_instr,
      \ex_swx_access__0\ => \ex_swx_access__0\,
      ex_valid => ex_valid,
      \imm_reg_reg[0]_0\(15 downto 0) => \imm_reg_reg[0]\(15 downto 0),
      in0 => Operand_Select_I_n_85,
      of_imm_data(0 to 15) => of_imm_data(0 to 15),
      of_op1_sel_spr => of_op1_sel_spr,
      p_231_in => p_231_in,
      swap_result(23 downto 0) => swap_result(23 downto 0),
      swap_result_reg(0 to 7) => swap_result_reg(0 to 7),
      sync_reset => sync_reset
    );
Register_File_I: entity work.design_1_microblaze_0_0_Register_File_gti
     port map (
      Clk => Clk,
      DID(1) => \EX_Branch_CMP_Op1_reg[0]_0\,
      DID(0) => \EX_Branch_CMP_Op1_reg[0]_1\,
      \EX_Branch_CMP_Op1_reg[10]\(1) => \EX_Branch_CMP_Op1_reg[10]\,
      \EX_Branch_CMP_Op1_reg[10]\(0) => \EX_Branch_CMP_Op1_reg[10]_0\,
      \EX_Branch_CMP_Op1_reg[12]\(1) => \EX_Branch_CMP_Op1_reg[12]\,
      \EX_Branch_CMP_Op1_reg[12]\(0) => \EX_Branch_CMP_Op1_reg[12]_0\,
      \EX_Branch_CMP_Op1_reg[14]\(1) => \EX_Branch_CMP_Op1_reg[14]\,
      \EX_Branch_CMP_Op1_reg[14]\(0) => \EX_Branch_CMP_Op1_reg[14]_0\,
      \EX_Branch_CMP_Op1_reg[16]\(1 downto 0) => \^ex_op2_reg[0]\(7 downto 6),
      \EX_Branch_CMP_Op1_reg[18]\ => \EX_Branch_CMP_Op1_reg[18]\,
      \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0) => \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0),
      \EX_Branch_CMP_Op1_reg[18]_1\(1 downto 0) => \^ex_op2_reg[0]\(5 downto 4),
      \EX_Branch_CMP_Op1_reg[20]\(1 downto 0) => \^ex_op2_reg[0]\(3 downto 2),
      \EX_Branch_CMP_Op1_reg[22]\(1 downto 0) => \^ex_op2_reg[0]\(1 downto 0),
      \EX_Branch_CMP_Op1_reg[24]\(1) => \EX_Branch_CMP_Op1_reg[24]\,
      \EX_Branch_CMP_Op1_reg[24]\(0) => \EX_Branch_CMP_Op1_reg[24]_0\,
      \EX_Branch_CMP_Op1_reg[26]\(1) => \EX_Branch_CMP_Op1_reg[26]\,
      \EX_Branch_CMP_Op1_reg[26]\(0) => \EX_Branch_CMP_Op1_reg[26]_0\,
      \EX_Branch_CMP_Op1_reg[28]\(1) => \EX_Branch_CMP_Op1_reg[28]\,
      \EX_Branch_CMP_Op1_reg[28]\(0) => \EX_Branch_CMP_Op1_reg[28]_0\,
      \EX_Branch_CMP_Op1_reg[2]\(1) => \EX_Branch_CMP_Op1_reg[2]\,
      \EX_Branch_CMP_Op1_reg[2]\(0) => \EX_Branch_CMP_Op1_reg[2]_0\,
      \EX_Branch_CMP_Op1_reg[30]\(1) => \EX_Branch_CMP_Op1_reg[30]\,
      \EX_Branch_CMP_Op1_reg[30]\(0) => \EX_Branch_CMP_Op1_reg[30]_0\,
      \EX_Branch_CMP_Op1_reg[4]\(1) => \EX_Branch_CMP_Op1_reg[4]\,
      \EX_Branch_CMP_Op1_reg[4]\(0) => \EX_Branch_CMP_Op1_reg[4]_0\,
      \EX_Branch_CMP_Op1_reg[6]\(1) => \EX_Branch_CMP_Op1_reg[6]\,
      \EX_Branch_CMP_Op1_reg[6]\(0) => \EX_Branch_CMP_Op1_reg[6]_0\,
      \EX_Branch_CMP_Op1_reg[8]\(1) => \EX_Branch_CMP_Op1_reg[8]\,
      \EX_Branch_CMP_Op1_reg[8]\(0) => \EX_Branch_CMP_Op1_reg[8]_0\,
      GPR_Op1(0 to 31) => GPR_Op1(0 to 31),
      GPR_Op2(0 to 31) => GPR_Op2(0 to 31),
      GPR_Op3(0 to 31) => GPR_Op3(0 to 31),
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(4) => of_imm_data(0),
      of_imm_data(3) => of_imm_data(1),
      of_imm_data(2) => of_imm_data(2),
      of_imm_data(1) => of_imm_data(3),
      of_imm_data(0) => of_imm_data(4)
    );
Shift_Logic_Module_I: entity work.design_1_microblaze_0_0_Shift_Logic_Module_gti
     port map (
      \EX_Op1_reg[24]\ => \EX_Op1_reg[24]\,
      \Using_FPGA.Native\ => Operand_Select_I_n_85,
      in0 => in0,
      \out\ => \out\
    );
\Using_DAXI_ALU_Carry.Direct_MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_299
     port map (
      \Using_FPGA.Native_0\ => \^ex_msr\(1),
      ex_pre_alu_carry => ex_pre_alu_carry,
      lopt => \^lopt\,
      lopt_1 => \^lopt_1\,
      lopt_10 => lopt_11,
      lopt_11 => lopt_12,
      lopt_12 => lopt_13,
      lopt_13 => lopt_14,
      lopt_14 => lopt_15,
      lopt_15 => lopt_16,
      lopt_16 => lopt_17,
      lopt_17 => lopt_18,
      lopt_18 => lopt_19,
      lopt_19 => lopt_20,
      lopt_2 => \^lopt_2\,
      lopt_20 => lopt_21,
      lopt_21 => lopt_22,
      lopt_22 => lopt_23,
      lopt_23 => lopt_24,
      lopt_24 => lopt_25,
      lopt_25 => lopt_26,
      lopt_3 => lopt_3,
      lopt_4 => DI_0,
      lopt_5 => ex_use_carry,
      lopt_6 => lopt_4,
      lopt_7 => lopt_5,
      lopt_8 => lopt_6,
      lopt_9 => lopt_7,
      muxcy_di => muxcy_di,
      muxcy_sel => muxcy_sel
    );
\Using_DAXI_ALU_Carry.Post_MUXCY_I\: entity work.design_1_microblaze_0_0_MB_MUXCY_300
     port map (
      ex_alu_carryin => ex_alu_carryin,
      ex_pre_alu_carry => ex_pre_alu_carry,
      lopt => \^lopt\,
      lopt_1 => \^lopt_1\,
      lopt_2 => \^lopt_2\
    );
\Using_DAXI_ALU_Carry.direct_lut_INST\: entity work.\design_1_microblaze_0_0_MB_LUT6_2__parameterized1\
     port map (
      muxcy_di => muxcy_di,
      muxcy_sel => muxcy_sel
    );
Zero_Detect_I: entity work.design_1_microblaze_0_0_Zero_Detect_gti
     port map (
      \Using_FPGA.Native\ => Operand_Select_I_n_150,
      \Using_FPGA.Native_0\(29) => \^ex_branch_cmp_op1_reg[0]\(0),
      \Using_FPGA.Native_0\(28) => ex_branch_cmp_op1(1),
      \Using_FPGA.Native_0\(27) => ex_branch_cmp_op1(2),
      \Using_FPGA.Native_0\(26) => ex_branch_cmp_op1(3),
      \Using_FPGA.Native_0\(25) => ex_branch_cmp_op1(4),
      \Using_FPGA.Native_0\(24) => ex_branch_cmp_op1(5),
      \Using_FPGA.Native_0\(23) => ex_branch_cmp_op1(6),
      \Using_FPGA.Native_0\(22) => ex_branch_cmp_op1(7),
      \Using_FPGA.Native_0\(21) => ex_branch_cmp_op1(8),
      \Using_FPGA.Native_0\(20) => ex_branch_cmp_op1(9),
      \Using_FPGA.Native_0\(19) => ex_branch_cmp_op1(10),
      \Using_FPGA.Native_0\(18) => ex_branch_cmp_op1(11),
      \Using_FPGA.Native_0\(17) => ex_branch_cmp_op1(12),
      \Using_FPGA.Native_0\(16) => ex_branch_cmp_op1(13),
      \Using_FPGA.Native_0\(15) => ex_branch_cmp_op1(14),
      \Using_FPGA.Native_0\(14) => ex_branch_cmp_op1(15),
      \Using_FPGA.Native_0\(13) => ex_branch_cmp_op1(16),
      \Using_FPGA.Native_0\(12) => ex_branch_cmp_op1(17),
      \Using_FPGA.Native_0\(11) => ex_branch_cmp_op1(18),
      \Using_FPGA.Native_0\(10) => ex_branch_cmp_op1(19),
      \Using_FPGA.Native_0\(9) => ex_branch_cmp_op1(20),
      \Using_FPGA.Native_0\(8) => ex_branch_cmp_op1(21),
      \Using_FPGA.Native_0\(7) => ex_branch_cmp_op1(22),
      \Using_FPGA.Native_0\(6) => ex_branch_cmp_op1(23),
      \Using_FPGA.Native_0\(5) => ex_branch_cmp_op1(24),
      \Using_FPGA.Native_0\(4) => ex_branch_cmp_op1(25),
      \Using_FPGA.Native_0\(3) => ex_branch_cmp_op1(26),
      \Using_FPGA.Native_0\(2) => ex_branch_cmp_op1(27),
      \Using_FPGA.Native_0\(1) => ex_branch_cmp_op1(28),
      \Using_FPGA.Native_0\(0) => ex_branch_cmp_op1(29),
      ex_op1_cmp_equal => ex_op1_cmp_equal,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      ex_op1_zero => ex_op1_zero,
      lopt => lopt_8,
      lopt_1 => lopt_9,
      lopt_2 => lopt_10
    );
exception_registers_I1: entity work.design_1_microblaze_0_0_exception_registers_gti
     port map (
      Clk => Clk,
      DI => DI,
      I1_1 => I1_1,
      \LOCKSTEP_Out_reg[3023]\ => \LOCKSTEP_Out_reg[3023]\,
      \LOCKSTEP_Out_reg[3024]\ => \LOCKSTEP_Out_reg[3024]\,
      \LOCKSTEP_Out_reg[3025]\ => \LOCKSTEP_Out_reg[3025]\,
      \LOCKSTEP_Out_reg[3026]\ => \LOCKSTEP_Out_reg[3026]\,
      \LOCKSTEP_Out_reg[3027]\ => \LOCKSTEP_Out_reg[3027]\,
      \LOCKSTEP_Out_reg[3028]\ => \LOCKSTEP_Out_reg[3028]\,
      \LOCKSTEP_Out_reg[3029]\ => \LOCKSTEP_Out_reg[3029]\,
      \LOCKSTEP_Out_reg[3030]\ => \LOCKSTEP_Out_reg[3030]\,
      \LOCKSTEP_Out_reg[3030]_0\ => \LOCKSTEP_Out_reg[3030]_0\,
      Q(7) => wb_mem_result(16),
      Q(6) => wb_mem_result(17),
      Q(5) => wb_mem_result(18),
      Q(4) => wb_mem_result(19),
      Q(3) => wb_mem_result(20),
      Q(2) => wb_mem_result(21),
      Q(1) => wb_mem_result(22),
      Q(0) => wb_mem_result(23),
      \Using_FPGA.Native\ => \Using_FPGA.Native\,
      \Using_FPGA.Native_0\ => \Using_FPGA.Native_0\,
      \Using_FPGA.Native_1\ => \Using_FPGA.Native_1\,
      \Using_FPGA.Native_10\ => \Using_FPGA.Native_10\,
      \Using_FPGA.Native_11\ => \Using_FPGA.Native_11\,
      \Using_FPGA.Native_12\ => \Using_FPGA.Native_12\,
      \Using_FPGA.Native_13\ => \Using_FPGA.Native_13\,
      \Using_FPGA.Native_14\ => \Using_FPGA.Native_14\,
      \Using_FPGA.Native_15\ => \Using_FPGA.Native_15\,
      \Using_FPGA.Native_16\ => \Using_FPGA.Native_16\,
      \Using_FPGA.Native_17\ => \Using_FPGA.Native_17\,
      \Using_FPGA.Native_18\ => \Using_FPGA.Native_18\,
      \Using_FPGA.Native_19\ => \Using_FPGA.Native_19\,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_2\,
      \Using_FPGA.Native_20\ => \Using_FPGA.Native_20\,
      \Using_FPGA.Native_21\ => \Using_FPGA.Native_21\,
      \Using_FPGA.Native_22\ => \Using_FPGA.Native_22\,
      \Using_FPGA.Native_23\ => \Using_FPGA.Native_23\,
      \Using_FPGA.Native_24\ => \Using_FPGA.Native_24\,
      \Using_FPGA.Native_25\ => \Using_FPGA.Native_25\,
      \Using_FPGA.Native_26\ => \Using_FPGA.Native_26\,
      \Using_FPGA.Native_27\ => \Using_FPGA.Native_27\,
      \Using_FPGA.Native_28\ => \Using_FPGA.Native_28\,
      \Using_FPGA.Native_29\(8) => \^ex_op2_reg[0]\(11),
      \Using_FPGA.Native_29\(7 downto 0) => \^ex_op2_reg[0]\(7 downto 0),
      \Using_FPGA.Native_3\ => \Using_FPGA.Native_3\,
      \Using_FPGA.Native_30\(23 downto 0) => \Using_FPGA.Native_29\(23 downto 0),
      \Using_FPGA.Native_31\(0) => \Using_FPGA.Native_32\(0),
      \Using_FPGA.Native_32\(31 downto 0) => \Using_FPGA.Native_33\(31 downto 0),
      \Using_FPGA.Native_33\ => \Using_FPGA.Native_34\,
      \Using_FPGA.Native_34\ => \Using_FPGA.Native_35\,
      \Using_FPGA.Native_4\ => \Using_FPGA.Native_4\,
      \Using_FPGA.Native_5\ => \Using_FPGA.Native_5\,
      \Using_FPGA.Native_6\ => \Using_FPGA.Native_6\,
      \Using_FPGA.Native_7\ => \Using_FPGA.Native_7\,
      \Using_FPGA.Native_8\ => \Using_FPGA.Native_8\,
      \Using_FPGA.Native_9\ => \Using_FPGA.Native_9\,
      \data_rd_reg_reg[23]\ => \data_rd_reg_reg[23]\,
      \data_rd_reg_reg[23]_0\ => \data_rd_reg_reg[23]_0\,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(7 downto 0) => wb_gpr_write_dbg_reg(7 downto 0)
    );
msr_reg_i: entity work.design_1_microblaze_0_0_msr_reg_gti
     port map (
      Clk => Clk,
      MEM_Fwd(3) => \^mem_fwd\(0),
      MEM_Fwd(2) => \^mem_fwd\(28),
      MEM_Fwd(1) => \^mem_fwd\(29),
      MEM_Fwd(0) => \^mem_fwd\(30),
      \Using_FPGA.Native\ => \Using_FPGA.Native_31\,
      \Using_FPGA.Native_0\ => Operand_Select_I_n_0,
      \Using_FPGA.Native_1\ => Operand_Select_I_n_33,
      \Using_FPGA.Native_2\ => \Using_FPGA.Native_35\,
      \WB_MEM_Result_reg[0]\(3) => MEM_EX_Result(0),
      \WB_MEM_Result_reg[0]\(2) => MEM_EX_Result(28),
      \WB_MEM_Result_reg[0]\(1) => MEM_EX_Result(29),
      \WB_MEM_Result_reg[0]\(0) => MEM_EX_Result(30),
      ex_MSR(2 downto 0) => \^ex_msr\(2 downto 0),
      mem_sel_msr => mem_sel_msr,
      sync_reset => sync_reset,
      \wb_MSR_i_reg[28]_0\(2 downto 0) => \^ex_op2_reg[0]\(10 downto 8),
      \wb_MSR_i_reg[30]_0\(0) => \wb_MSR_i_reg[30]\(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MicroBlaze_GTi is
  port (
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \Using_FPGA.Native_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    Hibernate : out STD_LOGIC;
    Suspend : out STD_LOGIC;
    Pause_Ack : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 358 downto 0 );
    Sleep : out STD_LOGIC;
    LOCKSTEP_Master_Out : out STD_LOGIC_VECTOR ( 40 downto 0 );
    Dbg_Trig_In : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_Trig_Ack_Out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_Reg_En_0_sp_1 : out STD_LOGIC;
    Dbg_TDO : out STD_LOGIC;
    sync_reset : in STD_LOGIC;
    Clk : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    Dbg_Trig_Ack_In : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_Trig_Out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Pause : in STD_LOGIC;
    Dbg_Update : in STD_LOGIC;
    Dbg_Stop : in STD_LOGIC;
    Dbg_Capture : in STD_LOGIC;
    M_AXI_DP_BVALID : in STD_LOGIC;
    M_AXI_DP_RVALID : in STD_LOGIC;
    M_AXI_DP_WREADY : in STD_LOGIC;
    M_AXI_DP_AWREADY : in STD_LOGIC;
    M_AXI_DP_ARREADY : in STD_LOGIC;
    Reset_Mode : in STD_LOGIC_VECTOR ( 0 to 1 );
    Data_Read_Reg_En : in STD_LOGIC;
    Config_Reg_En : in STD_LOGIC;
    IReady : in STD_LOGIC;
    Dbg_Shift : in STD_LOGIC;
    DReady : in STD_LOGIC;
    DWait : in STD_LOGIC;
    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
    wakeup_i : in STD_LOGIC_VECTOR ( 0 to 1 );
    Status_Reg_En : in STD_LOGIC;
    Scan_Reset_Sel : in STD_LOGIC;
    Scan_Reset : in STD_LOGIC;
    Scan_En : in STD_LOGIC;
    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
    M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_TDI : in STD_LOGIC;
    Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MicroBlaze_GTi : entity is "MicroBlaze_GTi";
end design_1_microblaze_0_0_MicroBlaze_GTi;

architecture STRUCTURE of design_1_microblaze_0_0_MicroBlaze_GTi is
  signal \ALU_I/DI\ : STD_LOGIC;
  signal \^d\ : STD_LOGIC_VECTOR ( 358 downto 0 );
  signal Data_Flow_I_n_0 : STD_LOGIC;
  signal Data_Flow_I_n_1 : STD_LOGIC;
  signal Data_Flow_I_n_10 : STD_LOGIC;
  signal Data_Flow_I_n_11 : STD_LOGIC;
  signal Data_Flow_I_n_12 : STD_LOGIC;
  signal Data_Flow_I_n_13 : STD_LOGIC;
  signal Data_Flow_I_n_14 : STD_LOGIC;
  signal Data_Flow_I_n_15 : STD_LOGIC;
  signal Data_Flow_I_n_16 : STD_LOGIC;
  signal Data_Flow_I_n_17 : STD_LOGIC;
  signal Data_Flow_I_n_18 : STD_LOGIC;
  signal Data_Flow_I_n_185 : STD_LOGIC;
  signal Data_Flow_I_n_188 : STD_LOGIC;
  signal Data_Flow_I_n_189 : STD_LOGIC;
  signal Data_Flow_I_n_19 : STD_LOGIC;
  signal Data_Flow_I_n_190 : STD_LOGIC;
  signal Data_Flow_I_n_191 : STD_LOGIC;
  signal Data_Flow_I_n_192 : STD_LOGIC;
  signal Data_Flow_I_n_193 : STD_LOGIC;
  signal Data_Flow_I_n_194 : STD_LOGIC;
  signal Data_Flow_I_n_195 : STD_LOGIC;
  signal Data_Flow_I_n_196 : STD_LOGIC;
  signal Data_Flow_I_n_2 : STD_LOGIC;
  signal Data_Flow_I_n_20 : STD_LOGIC;
  signal Data_Flow_I_n_21 : STD_LOGIC;
  signal Data_Flow_I_n_22 : STD_LOGIC;
  signal Data_Flow_I_n_23 : STD_LOGIC;
  signal Data_Flow_I_n_24 : STD_LOGIC;
  signal Data_Flow_I_n_25 : STD_LOGIC;
  signal Data_Flow_I_n_26 : STD_LOGIC;
  signal Data_Flow_I_n_27 : STD_LOGIC;
  signal Data_Flow_I_n_28 : STD_LOGIC;
  signal Data_Flow_I_n_29 : STD_LOGIC;
  signal Data_Flow_I_n_3 : STD_LOGIC;
  signal Data_Flow_I_n_30 : STD_LOGIC;
  signal Data_Flow_I_n_31 : STD_LOGIC;
  signal Data_Flow_I_n_33 : STD_LOGIC;
  signal Data_Flow_I_n_4 : STD_LOGIC;
  signal Data_Flow_I_n_429 : STD_LOGIC;
  signal Data_Flow_I_n_430 : STD_LOGIC;
  signal Data_Flow_I_n_5 : STD_LOGIC;
  signal Data_Flow_I_n_6 : STD_LOGIC;
  signal Data_Flow_I_n_7 : STD_LOGIC;
  signal Data_Flow_I_n_8 : STD_LOGIC;
  signal Data_Flow_I_n_9 : STD_LOGIC;
  signal \Data_Flow_Logic_I/R\ : STD_LOGIC;
  signal \Data_Flow_Logic_I/WB_MEM_Result0\ : STD_LOGIC;
  signal Dbg_Reg_En_0_sn_1 : STD_LOGIC;
  signal Decode_I_n_247 : STD_LOGIC;
  signal Decode_I_n_258 : STD_LOGIC;
  signal Decode_I_n_263 : STD_LOGIC;
  signal Decode_I_n_364 : STD_LOGIC;
  signal Decode_I_n_365 : STD_LOGIC;
  signal Decode_I_n_366 : STD_LOGIC;
  signal Decode_I_n_367 : STD_LOGIC;
  signal Decode_I_n_368 : STD_LOGIC;
  signal Decode_I_n_369 : STD_LOGIC;
  signal Decode_I_n_370 : STD_LOGIC;
  signal Decode_I_n_371 : STD_LOGIC;
  signal Decode_I_n_372 : STD_LOGIC;
  signal Decode_I_n_373 : STD_LOGIC;
  signal Decode_I_n_374 : STD_LOGIC;
  signal Decode_I_n_375 : STD_LOGIC;
  signal Decode_I_n_376 : STD_LOGIC;
  signal Decode_I_n_377 : STD_LOGIC;
  signal Decode_I_n_378 : STD_LOGIC;
  signal Decode_I_n_379 : STD_LOGIC;
  signal Decode_I_n_380 : STD_LOGIC;
  signal Decode_I_n_381 : STD_LOGIC;
  signal Decode_I_n_382 : STD_LOGIC;
  signal Decode_I_n_383 : STD_LOGIC;
  signal Decode_I_n_384 : STD_LOGIC;
  signal Decode_I_n_385 : STD_LOGIC;
  signal Decode_I_n_386 : STD_LOGIC;
  signal Decode_I_n_387 : STD_LOGIC;
  signal Decode_I_n_388 : STD_LOGIC;
  signal Decode_I_n_389 : STD_LOGIC;
  signal Decode_I_n_390 : STD_LOGIC;
  signal Decode_I_n_391 : STD_LOGIC;
  signal Decode_I_n_392 : STD_LOGIC;
  signal Decode_I_n_393 : STD_LOGIC;
  signal Decode_I_n_394 : STD_LOGIC;
  signal Decode_I_n_396 : STD_LOGIC;
  signal Decode_I_n_397 : STD_LOGIC;
  signal Decode_I_n_398 : STD_LOGIC;
  signal Decode_I_n_399 : STD_LOGIC;
  signal Decode_I_n_400 : STD_LOGIC;
  signal Decode_I_n_401 : STD_LOGIC;
  signal Decode_I_n_402 : STD_LOGIC;
  signal Decode_I_n_403 : STD_LOGIC;
  signal Decode_I_n_404 : STD_LOGIC;
  signal Decode_I_n_405 : STD_LOGIC;
  signal Decode_I_n_406 : STD_LOGIC;
  signal Decode_I_n_407 : STD_LOGIC;
  signal Decode_I_n_408 : STD_LOGIC;
  signal Decode_I_n_409 : STD_LOGIC;
  signal Decode_I_n_410 : STD_LOGIC;
  signal Decode_I_n_411 : STD_LOGIC;
  signal Decode_I_n_412 : STD_LOGIC;
  signal Decode_I_n_413 : STD_LOGIC;
  signal Decode_I_n_414 : STD_LOGIC;
  signal Decode_I_n_415 : STD_LOGIC;
  signal Decode_I_n_416 : STD_LOGIC;
  signal Decode_I_n_417 : STD_LOGIC;
  signal Decode_I_n_418 : STD_LOGIC;
  signal Decode_I_n_419 : STD_LOGIC;
  signal Decode_I_n_423 : STD_LOGIC;
  signal Decode_I_n_424 : STD_LOGIC;
  signal Decode_I_n_425 : STD_LOGIC;
  signal Decode_I_n_426 : STD_LOGIC;
  signal Decode_I_n_427 : STD_LOGIC;
  signal Decode_I_n_430 : STD_LOGIC;
  signal Decode_I_n_437 : STD_LOGIC;
  signal Decode_I_n_438 : STD_LOGIC;
  signal Decode_I_n_439 : STD_LOGIC;
  signal Decode_I_n_440 : STD_LOGIC;
  signal Decode_I_n_441 : STD_LOGIC;
  signal Decode_I_n_442 : STD_LOGIC;
  signal Decode_I_n_443 : STD_LOGIC;
  signal Decode_I_n_444 : STD_LOGIC;
  signal Decode_I_n_445 : STD_LOGIC;
  signal Decode_I_n_446 : STD_LOGIC;
  signal Decode_I_n_447 : STD_LOGIC;
  signal Decode_I_n_448 : STD_LOGIC;
  signal Decode_I_n_449 : STD_LOGIC;
  signal Decode_I_n_450 : STD_LOGIC;
  signal Decode_I_n_451 : STD_LOGIC;
  signal Decode_I_n_452 : STD_LOGIC;
  signal Decode_I_n_453 : STD_LOGIC;
  signal Decode_I_n_454 : STD_LOGIC;
  signal Decode_I_n_455 : STD_LOGIC;
  signal Decode_I_n_456 : STD_LOGIC;
  signal Decode_I_n_457 : STD_LOGIC;
  signal Decode_I_n_458 : STD_LOGIC;
  signal Decode_I_n_459 : STD_LOGIC;
  signal Decode_I_n_460 : STD_LOGIC;
  signal Decode_I_n_461 : STD_LOGIC;
  signal Decode_I_n_462 : STD_LOGIC;
  signal Decode_I_n_463 : STD_LOGIC;
  signal Decode_I_n_464 : STD_LOGIC;
  signal Decode_I_n_465 : STD_LOGIC;
  signal Decode_I_n_466 : STD_LOGIC;
  signal Decode_I_n_467 : STD_LOGIC;
  signal Decode_I_n_468 : STD_LOGIC;
  signal Decode_I_n_469 : STD_LOGIC;
  signal Decode_I_n_470 : STD_LOGIC;
  signal Decode_I_n_471 : STD_LOGIC;
  signal Decode_I_n_74 : STD_LOGIC;
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal EX_ALU_Sel_Logic : STD_LOGIC;
  signal EX_Enable_ALU : STD_LOGIC;
  signal EX_Fwd : STD_LOGIC_VECTOR ( 0 to 31 );
  signal EX_Op3 : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^lockstep_master_out\ : STD_LOGIC_VECTOR ( 40 downto 0 );
  signal MEM_DataBus_Ready : STD_LOGIC;
  signal MEM_Fwd : STD_LOGIC_VECTOR ( 0 to 31 );
  signal MEM_PC : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \Operand_Select_I/I0\ : STD_LOGIC;
  signal \Operand_Select_I/I1\ : STD_LOGIC;
  signal \PreFetch_Buffer_I1/I139_out\ : STD_LOGIC;
  signal \PreFetch_Buffer_I1/if_predecode\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \PreFetch_Buffer_I1/p_1_in49_in\ : STD_LOGIC;
  signal SRI : STD_LOGIC;
  signal \Shift_Logic_Module_I/I4\ : STD_LOGIC;
  signal \^sleep\ : STD_LOGIC;
  signal Sleep_Decode : STD_LOGIC;
  signal Sleep_Out : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_14\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_15\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_16\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_17\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_18\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_19\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_20\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_21\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_22\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_23\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_24\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_25\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_26\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_27\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_28\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_29\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_30\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_31\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_32\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_33\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_34\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_35\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_36\ : STD_LOGIC;
  signal \Use_DBUS.DAXI_Interface_I1_n_37\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_38\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_39\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_40\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_42\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_43\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_44\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_50\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_58\ : STD_LOGIC;
  signal \Use_Debug_Logic.Master_Core.Debug_Perf_n_59\ : STD_LOGIC;
  signal \^using_fpga.native\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^using_fpga.native_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal active_access : STD_LOGIC;
  signal active_access_d1 : STD_LOGIC;
  signal dbg_clean_stop : STD_LOGIC;
  signal dbg_stop_i : STD_LOGIC;
  signal ex_Exception_Taken : STD_LOGIC;
  signal ex_MSR : STD_LOGIC_VECTOR ( 28 to 30 );
  signal ex_MSR_Load_ALU_C : STD_LOGIC;
  signal ex_MSR_Load_LWX_SWX_C : STD_LOGIC;
  signal ex_MSR_Load_Shift_C : STD_LOGIC;
  signal ex_MSR_Set_SW_BIP : STD_LOGIC;
  signal ex_alu_op : STD_LOGIC_VECTOR ( 0 to 1 );
  signal ex_byte_access : STD_LOGIC;
  signal ex_cmp_op : STD_LOGIC;
  signal ex_databus_addr : STD_LOGIC_VECTOR ( 30 to 31 );
  signal ex_doublet_access : STD_LOGIC;
  signal ex_exception_no_load_store_mask : STD_LOGIC;
  signal ex_is_load_instr_s : STD_LOGIC;
  signal ex_load_shift_carry : STD_LOGIC;
  signal ex_move_to_MSR_instr : STD_LOGIC;
  signal ex_op1_cmp_equal : STD_LOGIC;
  signal ex_op1_cmp_equal_n : STD_LOGIC;
  signal ex_op1_neg : STD_LOGIC;
  signal ex_op1_zero : STD_LOGIC;
  signal ex_reverse_mem_access : STD_LOGIC;
  signal ex_sext_op : STD_LOGIC_VECTOR ( 0 to 1 );
  signal ex_swap_byte_instr : STD_LOGIC;
  signal \ex_swx_access__0\ : STD_LOGIC;
  signal ex_unsigned_op : STD_LOGIC;
  signal ex_use_carry : STD_LOGIC;
  signal ex_valid : STD_LOGIC;
  signal \exception_registers_I1/I1\ : STD_LOGIC;
  signal gpr_op1 : STD_LOGIC_VECTOR ( 0 to 31 );
  signal gpr_op2 : STD_LOGIC_VECTOR ( 0 to 31 );
  signal gpr_op3 : STD_LOGIC_VECTOR ( 0 to 31 );
  signal ib_data : STD_LOGIC_VECTOR ( 0 to 31 );
  signal if_sel_input : STD_LOGIC_VECTOR ( 3 to 3 );
  signal imm_reg : STD_LOGIC_VECTOR ( 0 to 15 );
  signal instr_rd_reg : STD_LOGIC_VECTOR ( 1 to 1 );
  signal lopt : STD_LOGIC;
  signal lopt_1 : STD_LOGIC;
  signal lopt_2 : STD_LOGIC;
  signal mem_Exception_Taken : STD_LOGIC;
  signal mem_byte_access : STD_LOGIC;
  signal mem_databus_access : STD_LOGIC;
  signal mem_databus_read : STD_LOGIC;
  signal mem_databus_write : STD_LOGIC;
  signal mem_doublet_access : STD_LOGIC;
  signal mem_sel_msr : STD_LOGIC;
  signal of_gpr_op1_rd_addr : STD_LOGIC_VECTOR ( 0 to 4 );
  signal of_gpr_op3_rd_addr : STD_LOGIC_VECTOR ( 0 to 4 );
  signal of_imm_data : STD_LOGIC_VECTOR ( 0 to 15 );
  signal of_op1_sel_spr : STD_LOGIC;
  signal of_op2 : STD_LOGIC_VECTOR ( 0 to 31 );
  signal of_op3 : STD_LOGIC_VECTOR ( 0 to 31 );
  signal of_pause : STD_LOGIC;
  signal of_pc : STD_LOGIC_VECTOR ( 0 to 31 );
  signal of_write_imm_reg : STD_LOGIC;
  signal p_1_out : STD_LOGIC;
  signal p_231_in : STD_LOGIC;
  signal \p_4_out__0\ : STD_LOGIC;
  signal swap_result : STD_LOGIC_VECTOR ( 8 to 31 );
  signal swap_result_reg : STD_LOGIC_VECTOR ( 0 to 7 );
  signal wb_Halted : STD_LOGIC;
  signal wb_byte_access : STD_LOGIC;
  signal wb_databus_steered_read_data : STD_LOGIC_VECTOR ( 24 to 31 );
  signal wb_dlmb_valid_read_data : STD_LOGIC_VECTOR ( 0 to 31 );
  signal wb_excep_return_addr : STD_LOGIC_VECTOR ( 0 to 31 );
  signal wb_gpr_wr_dbg : STD_LOGIC;
  signal wb_mem_result : STD_LOGIC_VECTOR ( 0 to 31 );
  signal wb_pc_valid : STD_LOGIC;
  signal wb_piperun : STD_LOGIC;
  signal wb_read_imm_reg : STD_LOGIC;
  signal wb_read_imm_reg_1 : STD_LOGIC;
  signal wb_read_msb_doublet_sel : STD_LOGIC;
begin
  D(358 downto 0) <= \^d\(358 downto 0);
  Dbg_Reg_En_0_sp_1 <= Dbg_Reg_En_0_sn_1;
  E(0) <= \^e\(0);
  LOCKSTEP_Master_Out(40 downto 0) <= \^lockstep_master_out\(40 downto 0);
  Sleep <= \^sleep\;
  \Using_FPGA.Native\(0) <= \^using_fpga.native\(0);
  \Using_FPGA.Native_0\(0) <= \^using_fpga.native_0\(0);
Data_Flow_I: entity work.design_1_microblaze_0_0_Data_Flow_gti
     port map (
      Clk => Clk,
      D(31) => \Operand_Select_I/I0\,
      D(30) => Decode_I_n_364,
      D(29) => Decode_I_n_365,
      D(28) => Decode_I_n_366,
      D(27) => Decode_I_n_367,
      D(26) => Decode_I_n_368,
      D(25) => Decode_I_n_369,
      D(24) => Decode_I_n_370,
      D(23) => Decode_I_n_371,
      D(22) => Decode_I_n_372,
      D(21) => Decode_I_n_373,
      D(20) => Decode_I_n_374,
      D(19) => Decode_I_n_375,
      D(18) => Decode_I_n_376,
      D(17) => Decode_I_n_377,
      D(16) => Decode_I_n_378,
      D(15) => Decode_I_n_379,
      D(14) => Decode_I_n_380,
      D(13) => Decode_I_n_381,
      D(12) => Decode_I_n_382,
      D(11) => Decode_I_n_383,
      D(10) => Decode_I_n_384,
      D(9) => Decode_I_n_385,
      D(8) => Decode_I_n_386,
      D(7) => Decode_I_n_387,
      D(6) => Decode_I_n_388,
      D(5) => Decode_I_n_389,
      D(4) => Decode_I_n_390,
      D(3) => Decode_I_n_391,
      D(2) => Decode_I_n_392,
      D(1) => Decode_I_n_393,
      D(0) => Decode_I_n_394,
      DI => \^d\(117),
      DI_0 => \ALU_I/DI\,
      E(0) => of_write_imm_reg,
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      \EX_Branch_CMP_Op1_reg[0]\(0) => ex_op1_neg,
      \EX_Branch_CMP_Op1_reg[0]_0\ => \^d\(107),
      \EX_Branch_CMP_Op1_reg[0]_1\ => \^d\(106),
      \EX_Branch_CMP_Op1_reg[10]\ => \^d\(97),
      \EX_Branch_CMP_Op1_reg[10]_0\ => \^d\(96),
      \EX_Branch_CMP_Op1_reg[12]\ => \^d\(95),
      \EX_Branch_CMP_Op1_reg[12]_0\ => \^d\(94),
      \EX_Branch_CMP_Op1_reg[14]\ => \^d\(93),
      \EX_Branch_CMP_Op1_reg[14]_0\ => \^d\(92),
      \EX_Branch_CMP_Op1_reg[18]\ => \^d\(116),
      \EX_Branch_CMP_Op1_reg[18]_0\(4 downto 0) => \^d\(115 downto 111),
      \EX_Branch_CMP_Op1_reg[24]\ => \^d\(83),
      \EX_Branch_CMP_Op1_reg[24]_0\ => \^d\(82),
      \EX_Branch_CMP_Op1_reg[26]\ => \^d\(81),
      \EX_Branch_CMP_Op1_reg[26]_0\ => \^d\(80),
      \EX_Branch_CMP_Op1_reg[28]\ => \^d\(79),
      \EX_Branch_CMP_Op1_reg[28]_0\ => \^d\(78),
      \EX_Branch_CMP_Op1_reg[2]\ => \^d\(105),
      \EX_Branch_CMP_Op1_reg[2]_0\ => \^d\(104),
      \EX_Branch_CMP_Op1_reg[30]\ => \^d\(77),
      \EX_Branch_CMP_Op1_reg[30]_0\ => \^d\(76),
      \EX_Branch_CMP_Op1_reg[4]\ => \^d\(103),
      \EX_Branch_CMP_Op1_reg[4]_0\ => \^d\(102),
      \EX_Branch_CMP_Op1_reg[6]\ => \^d\(101),
      \EX_Branch_CMP_Op1_reg[6]_0\ => \^d\(100),
      \EX_Branch_CMP_Op1_reg[8]\ => \^d\(99),
      \EX_Branch_CMP_Op1_reg[8]_0\ => \^d\(98),
      EX_Enable_ALU => EX_Enable_ALU,
      EX_Fwd(0 to 31) => EX_Fwd(0 to 31),
      \EX_Op1_reg[0]\(31) => Data_Flow_I_n_0,
      \EX_Op1_reg[0]\(30) => Data_Flow_I_n_1,
      \EX_Op1_reg[0]\(29) => Data_Flow_I_n_2,
      \EX_Op1_reg[0]\(28) => Data_Flow_I_n_3,
      \EX_Op1_reg[0]\(27) => Data_Flow_I_n_4,
      \EX_Op1_reg[0]\(26) => Data_Flow_I_n_5,
      \EX_Op1_reg[0]\(25) => Data_Flow_I_n_6,
      \EX_Op1_reg[0]\(24) => Data_Flow_I_n_7,
      \EX_Op1_reg[0]\(23) => Data_Flow_I_n_8,
      \EX_Op1_reg[0]\(22) => Data_Flow_I_n_9,
      \EX_Op1_reg[0]\(21) => Data_Flow_I_n_10,
      \EX_Op1_reg[0]\(20) => Data_Flow_I_n_11,
      \EX_Op1_reg[0]\(19) => Data_Flow_I_n_12,
      \EX_Op1_reg[0]\(18) => Data_Flow_I_n_13,
      \EX_Op1_reg[0]\(17) => Data_Flow_I_n_14,
      \EX_Op1_reg[0]\(16) => Data_Flow_I_n_15,
      \EX_Op1_reg[0]\(15) => Data_Flow_I_n_16,
      \EX_Op1_reg[0]\(14) => Data_Flow_I_n_17,
      \EX_Op1_reg[0]\(13) => Data_Flow_I_n_18,
      \EX_Op1_reg[0]\(12) => Data_Flow_I_n_19,
      \EX_Op1_reg[0]\(11) => Data_Flow_I_n_20,
      \EX_Op1_reg[0]\(10) => Data_Flow_I_n_21,
      \EX_Op1_reg[0]\(9) => Data_Flow_I_n_22,
      \EX_Op1_reg[0]\(8) => Data_Flow_I_n_23,
      \EX_Op1_reg[0]\(7) => Data_Flow_I_n_24,
      \EX_Op1_reg[0]\(6) => Data_Flow_I_n_25,
      \EX_Op1_reg[0]\(5) => Data_Flow_I_n_26,
      \EX_Op1_reg[0]\(4) => Data_Flow_I_n_27,
      \EX_Op1_reg[0]\(3) => Data_Flow_I_n_28,
      \EX_Op1_reg[0]\(2) => Data_Flow_I_n_29,
      \EX_Op1_reg[0]\(1) => Data_Flow_I_n_30,
      \EX_Op1_reg[0]\(0) => Data_Flow_I_n_31,
      \EX_Op1_reg[10]\ => Decode_I_n_462,
      \EX_Op1_reg[11]\ => Decode_I_n_461,
      \EX_Op1_reg[12]\ => Decode_I_n_460,
      \EX_Op1_reg[13]\ => Decode_I_n_459,
      \EX_Op1_reg[14]\ => Decode_I_n_458,
      \EX_Op1_reg[15]\ => Decode_I_n_457,
      \EX_Op1_reg[16]\ => Decode_I_n_456,
      \EX_Op1_reg[17]\ => Decode_I_n_455,
      \EX_Op1_reg[18]\ => Decode_I_n_454,
      \EX_Op1_reg[19]\ => Decode_I_n_453,
      \EX_Op1_reg[1]\ => Decode_I_n_471,
      \EX_Op1_reg[20]\ => Decode_I_n_452,
      \EX_Op1_reg[21]\ => Decode_I_n_451,
      \EX_Op1_reg[22]\ => Decode_I_n_450,
      \EX_Op1_reg[23]\ => Decode_I_n_449,
      \EX_Op1_reg[24]\ => Data_Flow_I_n_33,
      \EX_Op1_reg[24]_0\ => Decode_I_n_448,
      \EX_Op1_reg[25]\ => Decode_I_n_447,
      \EX_Op1_reg[26]\ => Decode_I_n_446,
      \EX_Op1_reg[27]\ => Decode_I_n_445,
      \EX_Op1_reg[28]\ => Data_Flow_I_n_188,
      \EX_Op1_reg[28]_0\ => Decode_I_n_444,
      \EX_Op1_reg[29]\ => Decode_I_n_443,
      \EX_Op1_reg[2]\ => Decode_I_n_470,
      \EX_Op1_reg[30]\ => Decode_I_n_442,
      \EX_Op1_reg[31]\ => Decode_I_n_441,
      \EX_Op1_reg[3]\ => Decode_I_n_469,
      \EX_Op1_reg[4]\ => Decode_I_n_468,
      \EX_Op1_reg[5]\ => Decode_I_n_467,
      \EX_Op1_reg[6]\ => Decode_I_n_466,
      \EX_Op1_reg[7]\ => Decode_I_n_465,
      \EX_Op1_reg[8]\ => Decode_I_n_464,
      \EX_Op1_reg[9]\ => Decode_I_n_463,
      \EX_Op2_reg[0]\(91 downto 60) => \^d\(323 downto 292),
      \EX_Op2_reg[0]\(59 downto 52) => \^d\(275 downto 268),
      \EX_Op2_reg[0]\(51 downto 48) => \^d\(256 downto 253),
      \EX_Op2_reg[0]\(47 downto 12) => \^d\(219 downto 184),
      \EX_Op2_reg[0]\(11) => \^d\(148),
      \EX_Op2_reg[0]\(10 downto 8) => \^d\(110 downto 108),
      \EX_Op2_reg[0]\(7 downto 0) => \^d\(91 downto 84),
      \EX_Op2_reg[0]_0\(31) => of_op2(0),
      \EX_Op2_reg[0]_0\(30) => of_op2(1),
      \EX_Op2_reg[0]_0\(29) => of_op2(2),
      \EX_Op2_reg[0]_0\(28) => of_op2(3),
      \EX_Op2_reg[0]_0\(27) => of_op2(4),
      \EX_Op2_reg[0]_0\(26) => of_op2(5),
      \EX_Op2_reg[0]_0\(25) => of_op2(6),
      \EX_Op2_reg[0]_0\(24) => of_op2(7),
      \EX_Op2_reg[0]_0\(23) => of_op2(8),
      \EX_Op2_reg[0]_0\(22) => of_op2(9),
      \EX_Op2_reg[0]_0\(21) => of_op2(10),
      \EX_Op2_reg[0]_0\(20) => of_op2(11),
      \EX_Op2_reg[0]_0\(19) => of_op2(12),
      \EX_Op2_reg[0]_0\(18) => of_op2(13),
      \EX_Op2_reg[0]_0\(17) => of_op2(14),
      \EX_Op2_reg[0]_0\(16) => of_op2(15),
      \EX_Op2_reg[0]_0\(15) => of_op2(16),
      \EX_Op2_reg[0]_0\(14) => of_op2(17),
      \EX_Op2_reg[0]_0\(13) => of_op2(18),
      \EX_Op2_reg[0]_0\(12) => of_op2(19),
      \EX_Op2_reg[0]_0\(11) => of_op2(20),
      \EX_Op2_reg[0]_0\(10) => of_op2(21),
      \EX_Op2_reg[0]_0\(9) => of_op2(22),
      \EX_Op2_reg[0]_0\(8) => of_op2(23),
      \EX_Op2_reg[0]_0\(7) => of_op2(24),
      \EX_Op2_reg[0]_0\(6) => of_op2(25),
      \EX_Op2_reg[0]_0\(5) => of_op2(26),
      \EX_Op2_reg[0]_0\(4) => of_op2(27),
      \EX_Op2_reg[0]_0\(3) => of_op2(28),
      \EX_Op2_reg[0]_0\(2) => of_op2(29),
      \EX_Op2_reg[0]_0\(1) => of_op2(30),
      \EX_Op2_reg[0]_0\(0) => of_op2(31),
      \EX_Op3_reg[0]\(31) => EX_Op3(0),
      \EX_Op3_reg[0]\(30) => EX_Op3(1),
      \EX_Op3_reg[0]\(29) => EX_Op3(2),
      \EX_Op3_reg[0]\(28) => EX_Op3(3),
      \EX_Op3_reg[0]\(27) => EX_Op3(4),
      \EX_Op3_reg[0]\(26) => EX_Op3(5),
      \EX_Op3_reg[0]\(25) => EX_Op3(6),
      \EX_Op3_reg[0]\(24) => EX_Op3(7),
      \EX_Op3_reg[0]\(23) => EX_Op3(8),
      \EX_Op3_reg[0]\(22) => EX_Op3(9),
      \EX_Op3_reg[0]\(21) => EX_Op3(10),
      \EX_Op3_reg[0]\(20) => EX_Op3(11),
      \EX_Op3_reg[0]\(19) => EX_Op3(12),
      \EX_Op3_reg[0]\(18) => EX_Op3(13),
      \EX_Op3_reg[0]\(17) => EX_Op3(14),
      \EX_Op3_reg[0]\(16) => EX_Op3(15),
      \EX_Op3_reg[0]\(15) => EX_Op3(16),
      \EX_Op3_reg[0]\(14) => EX_Op3(17),
      \EX_Op3_reg[0]\(13) => EX_Op3(18),
      \EX_Op3_reg[0]\(12) => EX_Op3(19),
      \EX_Op3_reg[0]\(11) => EX_Op3(20),
      \EX_Op3_reg[0]\(10) => EX_Op3(21),
      \EX_Op3_reg[0]\(9) => EX_Op3(22),
      \EX_Op3_reg[0]\(8) => EX_Op3(23),
      \EX_Op3_reg[0]\(7) => EX_Op3(24),
      \EX_Op3_reg[0]\(6) => EX_Op3(25),
      \EX_Op3_reg[0]\(5) => EX_Op3(26),
      \EX_Op3_reg[0]\(4) => EX_Op3(27),
      \EX_Op3_reg[0]\(3) => EX_Op3(28),
      \EX_Op3_reg[0]\(2) => EX_Op3(29),
      \EX_Op3_reg[0]\(1) => EX_Op3(30),
      \EX_Op3_reg[0]\(0) => EX_Op3(31),
      \EX_Op3_reg[0]_0\(31) => of_op3(0),
      \EX_Op3_reg[0]_0\(30) => of_op3(1),
      \EX_Op3_reg[0]_0\(29) => of_op3(2),
      \EX_Op3_reg[0]_0\(28) => of_op3(3),
      \EX_Op3_reg[0]_0\(27) => of_op3(4),
      \EX_Op3_reg[0]_0\(26) => of_op3(5),
      \EX_Op3_reg[0]_0\(25) => of_op3(6),
      \EX_Op3_reg[0]_0\(24) => of_op3(7),
      \EX_Op3_reg[0]_0\(23) => of_op3(8),
      \EX_Op3_reg[0]_0\(22) => of_op3(9),
      \EX_Op3_reg[0]_0\(21) => of_op3(10),
      \EX_Op3_reg[0]_0\(20) => of_op3(11),
      \EX_Op3_reg[0]_0\(19) => of_op3(12),
      \EX_Op3_reg[0]_0\(18) => of_op3(13),
      \EX_Op3_reg[0]_0\(17) => of_op3(14),
      \EX_Op3_reg[0]_0\(16) => of_op3(15),
      \EX_Op3_reg[0]_0\(15) => of_op3(16),
      \EX_Op3_reg[0]_0\(14) => of_op3(17),
      \EX_Op3_reg[0]_0\(13) => of_op3(18),
      \EX_Op3_reg[0]_0\(12) => of_op3(19),
      \EX_Op3_reg[0]_0\(11) => of_op3(20),
      \EX_Op3_reg[0]_0\(10) => of_op3(21),
      \EX_Op3_reg[0]_0\(9) => of_op3(22),
      \EX_Op3_reg[0]_0\(8) => of_op3(23),
      \EX_Op3_reg[0]_0\(7) => of_op3(24),
      \EX_Op3_reg[0]_0\(6) => of_op3(25),
      \EX_Op3_reg[0]_0\(5) => of_op3(26),
      \EX_Op3_reg[0]_0\(4) => of_op3(27),
      \EX_Op3_reg[0]_0\(3) => of_op3(28),
      \EX_Op3_reg[0]_0\(2) => of_op3(29),
      \EX_Op3_reg[0]_0\(1) => of_op3(30),
      \EX_Op3_reg[0]_0\(0) => of_op3(31),
      \EX_Op3_reg[31]\ => \^e\(0),
      GPR_Op1(0 to 31) => gpr_op1(0 to 31),
      GPR_Op2(0 to 31) => gpr_op2(0 to 31),
      GPR_Op3(0 to 31) => gpr_op3(0 to 31),
      I1 => \Operand_Select_I/I1\,
      I1_1 => \exception_registers_I1/I1\,
      \LOCKSTEP_Out_reg[3023]\ => \Use_DBUS.DAXI_Interface_I1_n_14\,
      \LOCKSTEP_Out_reg[3024]\ => \Use_DBUS.DAXI_Interface_I1_n_15\,
      \LOCKSTEP_Out_reg[3025]\ => \Use_DBUS.DAXI_Interface_I1_n_16\,
      \LOCKSTEP_Out_reg[3026]\ => \Use_DBUS.DAXI_Interface_I1_n_17\,
      \LOCKSTEP_Out_reg[3027]\ => \Use_DBUS.DAXI_Interface_I1_n_18\,
      \LOCKSTEP_Out_reg[3028]\ => \Use_DBUS.DAXI_Interface_I1_n_19\,
      \LOCKSTEP_Out_reg[3029]\ => \Use_DBUS.DAXI_Interface_I1_n_20\,
      \LOCKSTEP_Out_reg[3030]\ => \^d\(75),
      \LOCKSTEP_Out_reg[3030]_0\ => \Use_DBUS.DAXI_Interface_I1_n_21\,
      \MEM_DataBus_Write_Data_reg[0]\(23 downto 8) => \^d\(291 downto 276),
      \MEM_DataBus_Write_Data_reg[0]\(7 downto 0) => \^d\(267 downto 260),
      MEM_Fwd(0 to 31) => MEM_Fwd(0 to 31),
      \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]\ => Data_Flow_I_n_185,
      \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]\(1) => Data_Flow_I_n_429,
      \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]\(0) => Data_Flow_I_n_430,
      Q(1) => ex_alu_op(0),
      Q(0) => ex_alu_op(1),
      R => \Data_Flow_Logic_I/R\,
      SR(0) => \Data_Flow_Logic_I/WB_MEM_Result0\,
      \Using_FPGA.Native\ => \^d\(118),
      \Using_FPGA.Native_0\ => \^d\(119),
      \Using_FPGA.Native_1\ => \^d\(120),
      \Using_FPGA.Native_10\ => \^d\(129),
      \Using_FPGA.Native_11\ => \^d\(130),
      \Using_FPGA.Native_12\ => \^d\(131),
      \Using_FPGA.Native_13\ => \^d\(132),
      \Using_FPGA.Native_14\ => \^d\(133),
      \Using_FPGA.Native_15\ => \^d\(134),
      \Using_FPGA.Native_16\ => \^d\(135),
      \Using_FPGA.Native_17\ => \^d\(136),
      \Using_FPGA.Native_18\ => \^d\(137),
      \Using_FPGA.Native_19\ => \^d\(138),
      \Using_FPGA.Native_2\ => \^d\(121),
      \Using_FPGA.Native_20\ => \^d\(139),
      \Using_FPGA.Native_21\ => \^d\(140),
      \Using_FPGA.Native_22\ => \^d\(141),
      \Using_FPGA.Native_23\ => \^d\(142),
      \Using_FPGA.Native_24\ => \^d\(143),
      \Using_FPGA.Native_25\ => \^d\(144),
      \Using_FPGA.Native_26\ => \^d\(145),
      \Using_FPGA.Native_27\ => \^d\(146),
      \Using_FPGA.Native_28\ => \^d\(147),
      \Using_FPGA.Native_29\(23) => wb_excep_return_addr(0),
      \Using_FPGA.Native_29\(22) => wb_excep_return_addr(1),
      \Using_FPGA.Native_29\(21) => wb_excep_return_addr(2),
      \Using_FPGA.Native_29\(20) => wb_excep_return_addr(3),
      \Using_FPGA.Native_29\(19) => wb_excep_return_addr(4),
      \Using_FPGA.Native_29\(18) => wb_excep_return_addr(5),
      \Using_FPGA.Native_29\(17) => wb_excep_return_addr(6),
      \Using_FPGA.Native_29\(16) => wb_excep_return_addr(7),
      \Using_FPGA.Native_29\(15) => wb_excep_return_addr(8),
      \Using_FPGA.Native_29\(14) => wb_excep_return_addr(9),
      \Using_FPGA.Native_29\(13) => wb_excep_return_addr(10),
      \Using_FPGA.Native_29\(12) => wb_excep_return_addr(11),
      \Using_FPGA.Native_29\(11) => wb_excep_return_addr(12),
      \Using_FPGA.Native_29\(10) => wb_excep_return_addr(13),
      \Using_FPGA.Native_29\(9) => wb_excep_return_addr(14),
      \Using_FPGA.Native_29\(8) => wb_excep_return_addr(15),
      \Using_FPGA.Native_29\(7) => wb_excep_return_addr(24),
      \Using_FPGA.Native_29\(6) => wb_excep_return_addr(25),
      \Using_FPGA.Native_29\(5) => wb_excep_return_addr(26),
      \Using_FPGA.Native_29\(4) => wb_excep_return_addr(27),
      \Using_FPGA.Native_29\(3) => wb_excep_return_addr(28),
      \Using_FPGA.Native_29\(2) => wb_excep_return_addr(29),
      \Using_FPGA.Native_29\(1) => wb_excep_return_addr(30),
      \Using_FPGA.Native_29\(0) => wb_excep_return_addr(31),
      \Using_FPGA.Native_3\ => \^d\(122),
      \Using_FPGA.Native_30\ => \^using_fpga.native_0\(0),
      \Using_FPGA.Native_31\ => Decode_I_n_263,
      \Using_FPGA.Native_32\(0) => \^d\(74),
      \Using_FPGA.Native_33\(31) => MEM_PC(0),
      \Using_FPGA.Native_33\(30) => MEM_PC(1),
      \Using_FPGA.Native_33\(29) => MEM_PC(2),
      \Using_FPGA.Native_33\(28) => MEM_PC(3),
      \Using_FPGA.Native_33\(27) => MEM_PC(4),
      \Using_FPGA.Native_33\(26) => MEM_PC(5),
      \Using_FPGA.Native_33\(25) => MEM_PC(6),
      \Using_FPGA.Native_33\(24) => MEM_PC(7),
      \Using_FPGA.Native_33\(23) => MEM_PC(8),
      \Using_FPGA.Native_33\(22) => MEM_PC(9),
      \Using_FPGA.Native_33\(21) => MEM_PC(10),
      \Using_FPGA.Native_33\(20) => MEM_PC(11),
      \Using_FPGA.Native_33\(19) => MEM_PC(12),
      \Using_FPGA.Native_33\(18) => MEM_PC(13),
      \Using_FPGA.Native_33\(17) => MEM_PC(14),
      \Using_FPGA.Native_33\(16) => MEM_PC(15),
      \Using_FPGA.Native_33\(15) => MEM_PC(16),
      \Using_FPGA.Native_33\(14) => MEM_PC(17),
      \Using_FPGA.Native_33\(13) => MEM_PC(18),
      \Using_FPGA.Native_33\(12) => MEM_PC(19),
      \Using_FPGA.Native_33\(11) => MEM_PC(20),
      \Using_FPGA.Native_33\(10) => MEM_PC(21),
      \Using_FPGA.Native_33\(9) => MEM_PC(22),
      \Using_FPGA.Native_33\(8) => MEM_PC(23),
      \Using_FPGA.Native_33\(7) => MEM_PC(24),
      \Using_FPGA.Native_33\(6) => MEM_PC(25),
      \Using_FPGA.Native_33\(5) => MEM_PC(26),
      \Using_FPGA.Native_33\(4) => MEM_PC(27),
      \Using_FPGA.Native_33\(3) => MEM_PC(28),
      \Using_FPGA.Native_33\(2) => MEM_PC(29),
      \Using_FPGA.Native_33\(1) => MEM_PC(30),
      \Using_FPGA.Native_33\(0) => MEM_PC(31),
      \Using_FPGA.Native_34\ => Decode_I_n_439,
      \Using_FPGA.Native_35\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_36\ => Decode_I_n_247,
      \Using_FPGA.Native_37\ => \^lockstep_master_out\(36),
      \Using_FPGA.Native_38\ => \^lockstep_master_out\(32),
      \Using_FPGA.Native_4\ => \^d\(123),
      \Using_FPGA.Native_5\ => \^d\(124),
      \Using_FPGA.Native_6\ => \^d\(125),
      \Using_FPGA.Native_7\ => \^d\(126),
      \Using_FPGA.Native_8\ => \^d\(127),
      \Using_FPGA.Native_9\ => \^d\(128),
      \Using_FPGA.Native_i_3__31\(1) => ex_sext_op(0),
      \Using_FPGA.Native_i_3__31\(0) => ex_sext_op(1),
      \WB_MEM_Result_reg[0]\(23) => wb_mem_result(0),
      \WB_MEM_Result_reg[0]\(22) => wb_mem_result(1),
      \WB_MEM_Result_reg[0]\(21) => wb_mem_result(2),
      \WB_MEM_Result_reg[0]\(20) => wb_mem_result(3),
      \WB_MEM_Result_reg[0]\(19) => wb_mem_result(4),
      \WB_MEM_Result_reg[0]\(18) => wb_mem_result(5),
      \WB_MEM_Result_reg[0]\(17) => wb_mem_result(6),
      \WB_MEM_Result_reg[0]\(16) => wb_mem_result(7),
      \WB_MEM_Result_reg[0]\(15) => wb_mem_result(8),
      \WB_MEM_Result_reg[0]\(14) => wb_mem_result(9),
      \WB_MEM_Result_reg[0]\(13) => wb_mem_result(10),
      \WB_MEM_Result_reg[0]\(12) => wb_mem_result(11),
      \WB_MEM_Result_reg[0]\(11) => wb_mem_result(12),
      \WB_MEM_Result_reg[0]\(10) => wb_mem_result(13),
      \WB_MEM_Result_reg[0]\(9) => wb_mem_result(14),
      \WB_MEM_Result_reg[0]\(8) => wb_mem_result(15),
      \WB_MEM_Result_reg[0]\(7) => wb_mem_result(24),
      \WB_MEM_Result_reg[0]\(6) => wb_mem_result(25),
      \WB_MEM_Result_reg[0]\(5) => wb_mem_result(26),
      \WB_MEM_Result_reg[0]\(4) => wb_mem_result(27),
      \WB_MEM_Result_reg[0]\(3) => wb_mem_result(28),
      \WB_MEM_Result_reg[0]\(2) => wb_mem_result(29),
      \WB_MEM_Result_reg[0]\(1) => wb_mem_result(30),
      \WB_MEM_Result_reg[0]\(0) => wb_mem_result(31),
      \data_rd_reg_reg[23]\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_40\,
      \data_rd_reg_reg[23]_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_39\,
      ex_MSR(2) => ex_MSR(28),
      ex_MSR(1) => ex_MSR(29),
      ex_MSR(0) => ex_MSR(30),
      ex_MSR_Load_ALU_C => ex_MSR_Load_ALU_C,
      ex_MSR_Load_LWX_SWX_C => ex_MSR_Load_LWX_SWX_C,
      ex_MSR_Load_Shift_C => ex_MSR_Load_Shift_C,
      ex_byte_access => ex_byte_access,
      ex_cmp_op => ex_cmp_op,
      ex_databus_addr(1) => ex_databus_addr(30),
      ex_databus_addr(0) => ex_databus_addr(31),
      ex_doublet_access => ex_doublet_access,
      ex_move_to_MSR_instr => ex_move_to_MSR_instr,
      ex_op1_cmp_equal => ex_op1_cmp_equal,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      ex_op1_zero => ex_op1_zero,
      ex_reverse_mem_access => ex_reverse_mem_access,
      ex_swap_byte_instr => ex_swap_byte_instr,
      \ex_swx_access__0\ => \ex_swx_access__0\,
      ex_unsigned_op => ex_unsigned_op,
      ex_use_carry => ex_use_carry,
      ex_valid => ex_valid,
      \imm_reg_reg[0]\(15) => imm_reg(0),
      \imm_reg_reg[0]\(14) => imm_reg(1),
      \imm_reg_reg[0]\(13) => imm_reg(2),
      \imm_reg_reg[0]\(12) => imm_reg(3),
      \imm_reg_reg[0]\(11) => imm_reg(4),
      \imm_reg_reg[0]\(10) => imm_reg(5),
      \imm_reg_reg[0]\(9) => imm_reg(6),
      \imm_reg_reg[0]\(8) => imm_reg(7),
      \imm_reg_reg[0]\(7) => imm_reg(8),
      \imm_reg_reg[0]\(6) => imm_reg(9),
      \imm_reg_reg[0]\(5) => imm_reg(10),
      \imm_reg_reg[0]\(4) => imm_reg(11),
      \imm_reg_reg[0]\(3) => imm_reg(12),
      \imm_reg_reg[0]\(2) => imm_reg(13),
      \imm_reg_reg[0]\(1) => imm_reg(14),
      \imm_reg_reg[0]\(0) => imm_reg(15),
      in0 => Decode_I_n_437,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_2 => lopt_2,
      mem_byte_access => mem_byte_access,
      mem_doublet_access => mem_doublet_access,
      mem_sel_msr => mem_sel_msr,
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(0 to 15) => of_imm_data(0 to 15),
      of_op1_sel_spr => of_op1_sel_spr,
      \out\ => \Shift_Logic_Module_I/I4\,
      p_231_in => p_231_in,
      swap_result(23) => swap_result(8),
      swap_result(22) => swap_result(9),
      swap_result(21) => swap_result(10),
      swap_result(20) => swap_result(11),
      swap_result(19) => swap_result(12),
      swap_result(18) => swap_result(13),
      swap_result(17) => swap_result(14),
      swap_result(16) => swap_result(15),
      swap_result(15) => swap_result(16),
      swap_result(14) => swap_result(17),
      swap_result(13) => swap_result(18),
      swap_result(12) => swap_result(19),
      swap_result(11) => swap_result(20),
      swap_result(10) => swap_result(21),
      swap_result(9) => swap_result(22),
      swap_result(8) => swap_result(23),
      swap_result(7) => swap_result(24),
      swap_result(6) => swap_result(25),
      swap_result(5) => swap_result(26),
      swap_result(4) => swap_result(27),
      swap_result(3) => swap_result(28),
      swap_result(2) => swap_result(29),
      swap_result(1) => swap_result(30),
      swap_result(0) => swap_result(31),
      swap_result_reg(0 to 7) => swap_result_reg(0 to 7),
      sync_reset => sync_reset,
      \wb_MSR_i_reg[30]\(0) => wb_piperun,
      wb_byte_access => wb_byte_access,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg(7) => Data_Flow_I_n_189,
      wb_gpr_write_dbg_reg(6) => Data_Flow_I_n_190,
      wb_gpr_write_dbg_reg(5) => Data_Flow_I_n_191,
      wb_gpr_write_dbg_reg(4) => Data_Flow_I_n_192,
      wb_gpr_write_dbg_reg(3) => Data_Flow_I_n_193,
      wb_gpr_write_dbg_reg(2) => Data_Flow_I_n_194,
      wb_gpr_write_dbg_reg(1) => Data_Flow_I_n_195,
      wb_gpr_write_dbg_reg(0) => Data_Flow_I_n_196,
      wb_read_msb_doublet_sel => wb_read_msb_doublet_sel
    );
Decode_I: entity work.design_1_microblaze_0_0_Decode_gti
     port map (
      Clk => Clk,
      D(31) => of_pc(0),
      D(30) => of_pc(1),
      D(29) => of_pc(2),
      D(28) => of_pc(3),
      D(27) => of_pc(4),
      D(26) => of_pc(5),
      D(25) => of_pc(6),
      D(24) => of_pc(7),
      D(23) => of_pc(8),
      D(22) => of_pc(9),
      D(21) => of_pc(10),
      D(20) => of_pc(11),
      D(19) => of_pc(12),
      D(18) => of_pc(13),
      D(17) => of_pc(14),
      D(16) => of_pc(15),
      D(15) => of_pc(16),
      D(14) => of_pc(17),
      D(13) => of_pc(18),
      D(12) => of_pc(19),
      D(11) => of_pc(20),
      D(10) => of_pc(21),
      D(9) => of_pc(22),
      D(8) => of_pc(23),
      D(7) => of_pc(24),
      D(6) => of_pc(25),
      D(5) => of_pc(26),
      D(4) => of_pc(27),
      D(3) => of_pc(28),
      D(2) => of_pc(29),
      D(1) => of_pc(30),
      D(0) => of_pc(31),
      DI => \ALU_I/DI\,
      DReady => DReady,
      DWait => DWait,
      E(0) => of_write_imm_reg,
      \EX_ALU_Op_reg[0]_0\(1) => ex_alu_op(0),
      \EX_ALU_Op_reg[0]_0\(0) => ex_alu_op(1),
      EX_ALU_Sel_Logic => EX_ALU_Sel_Logic,
      EX_Enable_ALU => EX_Enable_ALU,
      EX_Fwd(0 to 31) => EX_Fwd(0 to 31),
      \EX_Op2_reg[0]\(15) => imm_reg(0),
      \EX_Op2_reg[0]\(14) => imm_reg(1),
      \EX_Op2_reg[0]\(13) => imm_reg(2),
      \EX_Op2_reg[0]\(12) => imm_reg(3),
      \EX_Op2_reg[0]\(11) => imm_reg(4),
      \EX_Op2_reg[0]\(10) => imm_reg(5),
      \EX_Op2_reg[0]\(9) => imm_reg(6),
      \EX_Op2_reg[0]\(8) => imm_reg(7),
      \EX_Op2_reg[0]\(7) => imm_reg(8),
      \EX_Op2_reg[0]\(6) => imm_reg(9),
      \EX_Op2_reg[0]\(5) => imm_reg(10),
      \EX_Op2_reg[0]\(4) => imm_reg(11),
      \EX_Op2_reg[0]\(3) => imm_reg(12),
      \EX_Op2_reg[0]\(2) => imm_reg(13),
      \EX_Op2_reg[0]\(1) => imm_reg(14),
      \EX_Op2_reg[0]\(0) => imm_reg(15),
      \EX_Sext_Op_reg[0]_0\(1) => ex_sext_op(0),
      \EX_Sext_Op_reg[0]_0\(0) => ex_sext_op(1),
      GPR_Op1(0 to 31) => gpr_op1(0 to 31),
      GPR_Op2(0 to 31) => gpr_op2(0 to 31),
      GPR_Op3(0 to 31) => gpr_op3(0 to 31),
      Hibernate => Hibernate,
      I1 => \exception_registers_I1/I1\,
      I139_out => \PreFetch_Buffer_I1/I139_out\,
      I1_0 => \Operand_Select_I/I1\,
      IReady => IReady,
      LOCKSTEP_Master_Out(2) => \^lockstep_master_out\(40),
      LOCKSTEP_Master_Out(1) => \^lockstep_master_out\(37),
      LOCKSTEP_Master_Out(0) => \^lockstep_master_out\(35),
      \LOCKSTEP_Out_reg[3007]\(23) => wb_excep_return_addr(0),
      \LOCKSTEP_Out_reg[3007]\(22) => wb_excep_return_addr(1),
      \LOCKSTEP_Out_reg[3007]\(21) => wb_excep_return_addr(2),
      \LOCKSTEP_Out_reg[3007]\(20) => wb_excep_return_addr(3),
      \LOCKSTEP_Out_reg[3007]\(19) => wb_excep_return_addr(4),
      \LOCKSTEP_Out_reg[3007]\(18) => wb_excep_return_addr(5),
      \LOCKSTEP_Out_reg[3007]\(17) => wb_excep_return_addr(6),
      \LOCKSTEP_Out_reg[3007]\(16) => wb_excep_return_addr(7),
      \LOCKSTEP_Out_reg[3007]\(15) => wb_excep_return_addr(8),
      \LOCKSTEP_Out_reg[3007]\(14) => wb_excep_return_addr(9),
      \LOCKSTEP_Out_reg[3007]\(13) => wb_excep_return_addr(10),
      \LOCKSTEP_Out_reg[3007]\(12) => wb_excep_return_addr(11),
      \LOCKSTEP_Out_reg[3007]\(11) => wb_excep_return_addr(12),
      \LOCKSTEP_Out_reg[3007]\(10) => wb_excep_return_addr(13),
      \LOCKSTEP_Out_reg[3007]\(9) => wb_excep_return_addr(14),
      \LOCKSTEP_Out_reg[3007]\(8) => wb_excep_return_addr(15),
      \LOCKSTEP_Out_reg[3007]\(7) => wb_excep_return_addr(24),
      \LOCKSTEP_Out_reg[3007]\(6) => wb_excep_return_addr(25),
      \LOCKSTEP_Out_reg[3007]\(5) => wb_excep_return_addr(26),
      \LOCKSTEP_Out_reg[3007]\(4) => wb_excep_return_addr(27),
      \LOCKSTEP_Out_reg[3007]\(3) => wb_excep_return_addr(28),
      \LOCKSTEP_Out_reg[3007]\(2) => wb_excep_return_addr(29),
      \LOCKSTEP_Out_reg[3007]\(1) => wb_excep_return_addr(30),
      \LOCKSTEP_Out_reg[3007]\(0) => wb_excep_return_addr(31),
      \LOCKSTEP_Out_reg[3007]_0\ => \Use_DBUS.DAXI_Interface_I1_n_37\,
      \LOCKSTEP_Out_reg[3007]_1\(23) => wb_mem_result(0),
      \LOCKSTEP_Out_reg[3007]_1\(22) => wb_mem_result(1),
      \LOCKSTEP_Out_reg[3007]_1\(21) => wb_mem_result(2),
      \LOCKSTEP_Out_reg[3007]_1\(20) => wb_mem_result(3),
      \LOCKSTEP_Out_reg[3007]_1\(19) => wb_mem_result(4),
      \LOCKSTEP_Out_reg[3007]_1\(18) => wb_mem_result(5),
      \LOCKSTEP_Out_reg[3007]_1\(17) => wb_mem_result(6),
      \LOCKSTEP_Out_reg[3007]_1\(16) => wb_mem_result(7),
      \LOCKSTEP_Out_reg[3007]_1\(15) => wb_mem_result(8),
      \LOCKSTEP_Out_reg[3007]_1\(14) => wb_mem_result(9),
      \LOCKSTEP_Out_reg[3007]_1\(13) => wb_mem_result(10),
      \LOCKSTEP_Out_reg[3007]_1\(12) => wb_mem_result(11),
      \LOCKSTEP_Out_reg[3007]_1\(11) => wb_mem_result(12),
      \LOCKSTEP_Out_reg[3007]_1\(10) => wb_mem_result(13),
      \LOCKSTEP_Out_reg[3007]_1\(9) => wb_mem_result(14),
      \LOCKSTEP_Out_reg[3007]_1\(8) => wb_mem_result(15),
      \LOCKSTEP_Out_reg[3007]_1\(7) => wb_mem_result(24),
      \LOCKSTEP_Out_reg[3007]_1\(6) => wb_mem_result(25),
      \LOCKSTEP_Out_reg[3007]_1\(5) => wb_mem_result(26),
      \LOCKSTEP_Out_reg[3007]_1\(4) => wb_mem_result(27),
      \LOCKSTEP_Out_reg[3007]_1\(3) => wb_mem_result(28),
      \LOCKSTEP_Out_reg[3007]_1\(2) => wb_mem_result(29),
      \LOCKSTEP_Out_reg[3007]_1\(1) => wb_mem_result(30),
      \LOCKSTEP_Out_reg[3007]_1\(0) => wb_mem_result(31),
      \LOCKSTEP_Out_reg[3008]\ => \Use_DBUS.DAXI_Interface_I1_n_36\,
      \LOCKSTEP_Out_reg[3009]\ => \Use_DBUS.DAXI_Interface_I1_n_35\,
      \LOCKSTEP_Out_reg[3010]\ => \Use_DBUS.DAXI_Interface_I1_n_34\,
      \LOCKSTEP_Out_reg[3011]\ => \Use_DBUS.DAXI_Interface_I1_n_33\,
      \LOCKSTEP_Out_reg[3012]\ => \Use_DBUS.DAXI_Interface_I1_n_32\,
      \LOCKSTEP_Out_reg[3013]\ => \Use_DBUS.DAXI_Interface_I1_n_31\,
      \LOCKSTEP_Out_reg[3014]\ => \Use_DBUS.DAXI_Interface_I1_n_30\,
      \LOCKSTEP_Out_reg[3015]\ => \Use_DBUS.DAXI_Interface_I1_n_29\,
      \LOCKSTEP_Out_reg[3016]\ => \Use_DBUS.DAXI_Interface_I1_n_28\,
      \LOCKSTEP_Out_reg[3017]\ => \Use_DBUS.DAXI_Interface_I1_n_27\,
      \LOCKSTEP_Out_reg[3018]\ => \Use_DBUS.DAXI_Interface_I1_n_26\,
      \LOCKSTEP_Out_reg[3019]\ => \Use_DBUS.DAXI_Interface_I1_n_25\,
      \LOCKSTEP_Out_reg[3020]\ => \Use_DBUS.DAXI_Interface_I1_n_24\,
      \LOCKSTEP_Out_reg[3021]\ => \Use_DBUS.DAXI_Interface_I1_n_23\,
      \LOCKSTEP_Out_reg[3022]\ => \Use_DBUS.DAXI_Interface_I1_n_22\,
      \MEM_DataBus_Addr_reg[0]_0\(70 downto 39) => \^d\(323 downto 292),
      \MEM_DataBus_Addr_reg[0]_0\(38) => \^d\(258),
      \MEM_DataBus_Addr_reg[0]_0\(37) => \^d\(220),
      \MEM_DataBus_Addr_reg[0]_0\(36 downto 35) => \^d\(183 downto 182),
      \MEM_DataBus_Addr_reg[0]_0\(34 downto 19) => \^d\(148 downto 133),
      \MEM_DataBus_Addr_reg[0]_0\(18 downto 11) => \^d\(124 downto 117),
      \MEM_DataBus_Addr_reg[0]_0\(10 downto 8) => \^d\(110 downto 108),
      \MEM_DataBus_Addr_reg[0]_0\(7 downto 0) => \^d\(91 downto 84),
      MEM_DataBus_Ready => MEM_DataBus_Ready,
      \MEM_DataBus_Write_Data_reg[0]\(31) => EX_Op3(0),
      \MEM_DataBus_Write_Data_reg[0]\(30) => EX_Op3(1),
      \MEM_DataBus_Write_Data_reg[0]\(29) => EX_Op3(2),
      \MEM_DataBus_Write_Data_reg[0]\(28) => EX_Op3(3),
      \MEM_DataBus_Write_Data_reg[0]\(27) => EX_Op3(4),
      \MEM_DataBus_Write_Data_reg[0]\(26) => EX_Op3(5),
      \MEM_DataBus_Write_Data_reg[0]\(25) => EX_Op3(6),
      \MEM_DataBus_Write_Data_reg[0]\(24) => EX_Op3(7),
      \MEM_DataBus_Write_Data_reg[0]\(23) => EX_Op3(8),
      \MEM_DataBus_Write_Data_reg[0]\(22) => EX_Op3(9),
      \MEM_DataBus_Write_Data_reg[0]\(21) => EX_Op3(10),
      \MEM_DataBus_Write_Data_reg[0]\(20) => EX_Op3(11),
      \MEM_DataBus_Write_Data_reg[0]\(19) => EX_Op3(12),
      \MEM_DataBus_Write_Data_reg[0]\(18) => EX_Op3(13),
      \MEM_DataBus_Write_Data_reg[0]\(17) => EX_Op3(14),
      \MEM_DataBus_Write_Data_reg[0]\(16) => EX_Op3(15),
      \MEM_DataBus_Write_Data_reg[0]\(15) => EX_Op3(16),
      \MEM_DataBus_Write_Data_reg[0]\(14) => EX_Op3(17),
      \MEM_DataBus_Write_Data_reg[0]\(13) => EX_Op3(18),
      \MEM_DataBus_Write_Data_reg[0]\(12) => EX_Op3(19),
      \MEM_DataBus_Write_Data_reg[0]\(11) => EX_Op3(20),
      \MEM_DataBus_Write_Data_reg[0]\(10) => EX_Op3(21),
      \MEM_DataBus_Write_Data_reg[0]\(9) => EX_Op3(22),
      \MEM_DataBus_Write_Data_reg[0]\(8) => EX_Op3(23),
      \MEM_DataBus_Write_Data_reg[0]\(7) => EX_Op3(24),
      \MEM_DataBus_Write_Data_reg[0]\(6) => EX_Op3(25),
      \MEM_DataBus_Write_Data_reg[0]\(5) => EX_Op3(26),
      \MEM_DataBus_Write_Data_reg[0]\(4) => EX_Op3(27),
      \MEM_DataBus_Write_Data_reg[0]\(3) => EX_Op3(28),
      \MEM_DataBus_Write_Data_reg[0]\(2) => EX_Op3(29),
      \MEM_DataBus_Write_Data_reg[0]\(1) => EX_Op3(30),
      \MEM_DataBus_Write_Data_reg[0]\(0) => EX_Op3(31),
      MEM_DataBus_Write_reg_0 => Decode_I_n_424,
      MEM_DataBus_Write_reg_1 => Decode_I_n_425,
      MEM_DataBus_Write_reg_2 => Decode_I_n_426,
      MEM_Fwd(0 to 31) => MEM_Fwd(0 to 31),
      M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
      M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
      M_AXI_DP_BVALID => M_AXI_DP_BVALID,
      M_AXI_DP_BVALID_0 => Decode_I_n_423,
      M_AXI_DP_RVALID => M_AXI_DP_RVALID,
      M_AXI_DP_WREADY => M_AXI_DP_WREADY,
      Pause => Pause,
      Pause_Ack => Pause_Ack,
      \Performance_Debug_Control.dbg_freeze_nohalt_reg\ => Decode_I_n_439,
      \Performance_Debug_Control.dbg_state_nohalt_reg\(159 downto 125) => \^d\(358 downto 324),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(124 downto 109) => \^d\(291 downto 276),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(108 downto 101) => \^d\(267 downto 260),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(100) => \^d\(257),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(99 downto 68) => \^d\(252 downto 221),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(67 downto 35) => \^d\(181 downto 149),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(34 downto 29) => \^d\(116 downto 111),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(28 downto 13) => \^d\(107 downto 92),
      \Performance_Debug_Control.dbg_state_nohalt_reg\(12 downto 0) => \^d\(83 downto 71),
      \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg\ => Decode_I_n_438,
      \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_42\,
      Q(0) => \Use_Debug_Logic.Master_Core.Debug_Perf_n_59\,
      R => \Data_Flow_Logic_I/R\,
      Reset_Mode(0 to 1) => Reset_Mode(0 to 1),
      SR(0) => \Data_Flow_Logic_I/WB_MEM_Result0\,
      SRI => SRI,
      \Serial_Dbg_Intf.control_reg_reg[8]\ => Decode_I_n_430,
      Sleep => \^sleep\,
      Sleep_Decode => Sleep_Decode,
      Sleep_Out => Sleep_Out,
      Suspend => Suspend,
      \Using_FPGA.Native\(0) => if_sel_input(3),
      \Using_FPGA.Native_0\ => \^using_fpga.native\(0),
      \Using_FPGA.Native_1\ => \^using_fpga.native_0\(0),
      \Using_FPGA.Native_10\ => Decode_I_n_448,
      \Using_FPGA.Native_11\ => Decode_I_n_449,
      \Using_FPGA.Native_12\ => Decode_I_n_450,
      \Using_FPGA.Native_13\ => Decode_I_n_451,
      \Using_FPGA.Native_14\ => Decode_I_n_452,
      \Using_FPGA.Native_15\ => Decode_I_n_453,
      \Using_FPGA.Native_16\ => Decode_I_n_454,
      \Using_FPGA.Native_17\ => Decode_I_n_455,
      \Using_FPGA.Native_18\ => Decode_I_n_456,
      \Using_FPGA.Native_19\ => Decode_I_n_457,
      \Using_FPGA.Native_2\ => Decode_I_n_440,
      \Using_FPGA.Native_20\ => Decode_I_n_458,
      \Using_FPGA.Native_21\ => Decode_I_n_459,
      \Using_FPGA.Native_22\ => Decode_I_n_460,
      \Using_FPGA.Native_23\ => Decode_I_n_461,
      \Using_FPGA.Native_24\ => Decode_I_n_462,
      \Using_FPGA.Native_25\ => Decode_I_n_463,
      \Using_FPGA.Native_26\ => Decode_I_n_464,
      \Using_FPGA.Native_27\ => Decode_I_n_465,
      \Using_FPGA.Native_28\ => Decode_I_n_466,
      \Using_FPGA.Native_29\ => Decode_I_n_467,
      \Using_FPGA.Native_3\ => Decode_I_n_441,
      \Using_FPGA.Native_30\ => Decode_I_n_468,
      \Using_FPGA.Native_31\ => Decode_I_n_469,
      \Using_FPGA.Native_32\ => Decode_I_n_470,
      \Using_FPGA.Native_33\ => Decode_I_n_471,
      \Using_FPGA.Native_34\(0) => \PreFetch_Buffer_I1/p_1_in49_in\,
      \Using_FPGA.Native_35\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_50\,
      \Using_FPGA.Native_36\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_58\,
      \Using_FPGA.Native_37\(0) => ex_op1_neg,
      \Using_FPGA.Native_38\ => Data_Flow_I_n_188,
      \Using_FPGA.Native_39\ => \^lockstep_master_out\(36),
      \Using_FPGA.Native_4\ => Decode_I_n_442,
      \Using_FPGA.Native_40\ => \^lockstep_master_out\(32),
      \Using_FPGA.Native_41\ => \^lockstep_master_out\(38),
      \Using_FPGA.Native_42\(31) => Data_Flow_I_n_0,
      \Using_FPGA.Native_42\(30) => Data_Flow_I_n_1,
      \Using_FPGA.Native_42\(29) => Data_Flow_I_n_2,
      \Using_FPGA.Native_42\(28) => Data_Flow_I_n_3,
      \Using_FPGA.Native_42\(27) => Data_Flow_I_n_4,
      \Using_FPGA.Native_42\(26) => Data_Flow_I_n_5,
      \Using_FPGA.Native_42\(25) => Data_Flow_I_n_6,
      \Using_FPGA.Native_42\(24) => Data_Flow_I_n_7,
      \Using_FPGA.Native_42\(23) => Data_Flow_I_n_8,
      \Using_FPGA.Native_42\(22) => Data_Flow_I_n_9,
      \Using_FPGA.Native_42\(21) => Data_Flow_I_n_10,
      \Using_FPGA.Native_42\(20) => Data_Flow_I_n_11,
      \Using_FPGA.Native_42\(19) => Data_Flow_I_n_12,
      \Using_FPGA.Native_42\(18) => Data_Flow_I_n_13,
      \Using_FPGA.Native_42\(17) => Data_Flow_I_n_14,
      \Using_FPGA.Native_42\(16) => Data_Flow_I_n_15,
      \Using_FPGA.Native_42\(15) => Data_Flow_I_n_16,
      \Using_FPGA.Native_42\(14) => Data_Flow_I_n_17,
      \Using_FPGA.Native_42\(13) => Data_Flow_I_n_18,
      \Using_FPGA.Native_42\(12) => Data_Flow_I_n_19,
      \Using_FPGA.Native_42\(11) => Data_Flow_I_n_20,
      \Using_FPGA.Native_42\(10) => Data_Flow_I_n_21,
      \Using_FPGA.Native_42\(9) => Data_Flow_I_n_22,
      \Using_FPGA.Native_42\(8) => Data_Flow_I_n_23,
      \Using_FPGA.Native_42\(7) => Data_Flow_I_n_24,
      \Using_FPGA.Native_42\(6) => Data_Flow_I_n_25,
      \Using_FPGA.Native_42\(5) => Data_Flow_I_n_26,
      \Using_FPGA.Native_42\(4) => Data_Flow_I_n_27,
      \Using_FPGA.Native_42\(3) => Data_Flow_I_n_28,
      \Using_FPGA.Native_42\(2) => Data_Flow_I_n_29,
      \Using_FPGA.Native_42\(1) => Data_Flow_I_n_30,
      \Using_FPGA.Native_42\(0) => Data_Flow_I_n_31,
      \Using_FPGA.Native_43\ => Data_Flow_I_n_33,
      \Using_FPGA.Native_5\ => Decode_I_n_443,
      \Using_FPGA.Native_6\ => Decode_I_n_444,
      \Using_FPGA.Native_7\ => Decode_I_n_445,
      \Using_FPGA.Native_8\ => Decode_I_n_446,
      \Using_FPGA.Native_9\ => Decode_I_n_447,
      Y(0 to 31) => ib_data(0 to 31),
      active_access => active_access,
      active_access_d1 => active_access_d1,
      active_access_reg => \Use_Debug_Logic.Master_Core.Debug_Perf_n_38\,
      \data_rd_reg_reg[0]\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_39\,
      dbg_clean_stop => dbg_clean_stop,
      dbg_halt_reset_mode_reg => Decode_I_n_427,
      dbg_stop_i => dbg_stop_i,
      ex_Exception_Taken => ex_Exception_Taken,
      ex_MSR(2) => ex_MSR(28),
      ex_MSR(1) => ex_MSR(29),
      ex_MSR(0) => ex_MSR(30),
      ex_MSR_Load_LWX_SWX_C => ex_MSR_Load_LWX_SWX_C,
      ex_MSR_Set_SW_BIP => ex_MSR_Set_SW_BIP,
      ex_byte_access => ex_byte_access,
      ex_cmp_op => ex_cmp_op,
      ex_databus_addr(1) => ex_databus_addr(30),
      ex_databus_addr(0) => ex_databus_addr(31),
      ex_doublet_access => ex_doublet_access,
      ex_exception_no_load_store_mask => ex_exception_no_load_store_mask,
      ex_is_load_instr_s => ex_is_load_instr_s,
      ex_load_alu_carry_reg_0 => Decode_I_n_247,
      ex_load_shift_carry => ex_load_shift_carry,
      ex_move_to_MSR_instr => ex_move_to_MSR_instr,
      ex_op1_cmp_equal => ex_op1_cmp_equal,
      ex_op1_cmp_equal_n => ex_op1_cmp_equal_n,
      ex_op1_zero => ex_op1_zero,
      ex_reverse_mem_access => ex_reverse_mem_access,
      ex_sel_alu_i_reg_0(31) => of_op2(0),
      ex_sel_alu_i_reg_0(30) => of_op2(1),
      ex_sel_alu_i_reg_0(29) => of_op2(2),
      ex_sel_alu_i_reg_0(28) => of_op2(3),
      ex_sel_alu_i_reg_0(27) => of_op2(4),
      ex_sel_alu_i_reg_0(26) => of_op2(5),
      ex_sel_alu_i_reg_0(25) => of_op2(6),
      ex_sel_alu_i_reg_0(24) => of_op2(7),
      ex_sel_alu_i_reg_0(23) => of_op2(8),
      ex_sel_alu_i_reg_0(22) => of_op2(9),
      ex_sel_alu_i_reg_0(21) => of_op2(10),
      ex_sel_alu_i_reg_0(20) => of_op2(11),
      ex_sel_alu_i_reg_0(19) => of_op2(12),
      ex_sel_alu_i_reg_0(18) => of_op2(13),
      ex_sel_alu_i_reg_0(17) => of_op2(14),
      ex_sel_alu_i_reg_0(16) => of_op2(15),
      ex_sel_alu_i_reg_0(15) => of_op2(16),
      ex_sel_alu_i_reg_0(14) => of_op2(17),
      ex_sel_alu_i_reg_0(13) => of_op2(18),
      ex_sel_alu_i_reg_0(12) => of_op2(19),
      ex_sel_alu_i_reg_0(11) => of_op2(20),
      ex_sel_alu_i_reg_0(10) => of_op2(21),
      ex_sel_alu_i_reg_0(9) => of_op2(22),
      ex_sel_alu_i_reg_0(8) => of_op2(23),
      ex_sel_alu_i_reg_0(7) => of_op2(24),
      ex_sel_alu_i_reg_0(6) => of_op2(25),
      ex_sel_alu_i_reg_0(5) => of_op2(26),
      ex_sel_alu_i_reg_0(4) => of_op2(27),
      ex_sel_alu_i_reg_0(3) => of_op2(28),
      ex_sel_alu_i_reg_0(2) => of_op2(29),
      ex_sel_alu_i_reg_0(1) => of_op2(30),
      ex_sel_alu_i_reg_0(0) => of_op2(31),
      ex_sel_alu_i_reg_1(31) => of_op3(0),
      ex_sel_alu_i_reg_1(30) => of_op3(1),
      ex_sel_alu_i_reg_1(29) => of_op3(2),
      ex_sel_alu_i_reg_1(28) => of_op3(3),
      ex_sel_alu_i_reg_1(27) => of_op3(4),
      ex_sel_alu_i_reg_1(26) => of_op3(5),
      ex_sel_alu_i_reg_1(25) => of_op3(6),
      ex_sel_alu_i_reg_1(24) => of_op3(7),
      ex_sel_alu_i_reg_1(23) => of_op3(8),
      ex_sel_alu_i_reg_1(22) => of_op3(9),
      ex_sel_alu_i_reg_1(21) => of_op3(10),
      ex_sel_alu_i_reg_1(20) => of_op3(11),
      ex_sel_alu_i_reg_1(19) => of_op3(12),
      ex_sel_alu_i_reg_1(18) => of_op3(13),
      ex_sel_alu_i_reg_1(17) => of_op3(14),
      ex_sel_alu_i_reg_1(16) => of_op3(15),
      ex_sel_alu_i_reg_1(15) => of_op3(16),
      ex_sel_alu_i_reg_1(14) => of_op3(17),
      ex_sel_alu_i_reg_1(13) => of_op3(18),
      ex_sel_alu_i_reg_1(12) => of_op3(19),
      ex_sel_alu_i_reg_1(11) => of_op3(20),
      ex_sel_alu_i_reg_1(10) => of_op3(21),
      ex_sel_alu_i_reg_1(9) => of_op3(22),
      ex_sel_alu_i_reg_1(8) => of_op3(23),
      ex_sel_alu_i_reg_1(7) => of_op3(24),
      ex_sel_alu_i_reg_1(6) => of_op3(25),
      ex_sel_alu_i_reg_1(5) => of_op3(26),
      ex_sel_alu_i_reg_1(4) => of_op3(27),
      ex_sel_alu_i_reg_1(3) => of_op3(28),
      ex_sel_alu_i_reg_1(2) => of_op3(29),
      ex_sel_alu_i_reg_1(1) => of_op3(30),
      ex_sel_alu_i_reg_1(0) => of_op3(31),
      ex_sel_alu_i_reg_2(31) => \Operand_Select_I/I0\,
      ex_sel_alu_i_reg_2(30) => Decode_I_n_364,
      ex_sel_alu_i_reg_2(29) => Decode_I_n_365,
      ex_sel_alu_i_reg_2(28) => Decode_I_n_366,
      ex_sel_alu_i_reg_2(27) => Decode_I_n_367,
      ex_sel_alu_i_reg_2(26) => Decode_I_n_368,
      ex_sel_alu_i_reg_2(25) => Decode_I_n_369,
      ex_sel_alu_i_reg_2(24) => Decode_I_n_370,
      ex_sel_alu_i_reg_2(23) => Decode_I_n_371,
      ex_sel_alu_i_reg_2(22) => Decode_I_n_372,
      ex_sel_alu_i_reg_2(21) => Decode_I_n_373,
      ex_sel_alu_i_reg_2(20) => Decode_I_n_374,
      ex_sel_alu_i_reg_2(19) => Decode_I_n_375,
      ex_sel_alu_i_reg_2(18) => Decode_I_n_376,
      ex_sel_alu_i_reg_2(17) => Decode_I_n_377,
      ex_sel_alu_i_reg_2(16) => Decode_I_n_378,
      ex_sel_alu_i_reg_2(15) => Decode_I_n_379,
      ex_sel_alu_i_reg_2(14) => Decode_I_n_380,
      ex_sel_alu_i_reg_2(13) => Decode_I_n_381,
      ex_sel_alu_i_reg_2(12) => Decode_I_n_382,
      ex_sel_alu_i_reg_2(11) => Decode_I_n_383,
      ex_sel_alu_i_reg_2(10) => Decode_I_n_384,
      ex_sel_alu_i_reg_2(9) => Decode_I_n_385,
      ex_sel_alu_i_reg_2(8) => Decode_I_n_386,
      ex_sel_alu_i_reg_2(7) => Decode_I_n_387,
      ex_sel_alu_i_reg_2(6) => Decode_I_n_388,
      ex_sel_alu_i_reg_2(5) => Decode_I_n_389,
      ex_sel_alu_i_reg_2(4) => Decode_I_n_390,
      ex_sel_alu_i_reg_2(3) => Decode_I_n_391,
      ex_sel_alu_i_reg_2(2) => Decode_I_n_392,
      ex_sel_alu_i_reg_2(1) => Decode_I_n_393,
      ex_sel_alu_i_reg_2(0) => Decode_I_n_394,
      ex_set_bip_reg_0 => Decode_I_n_74,
      ex_set_bip_reg_1 => Decode_I_n_263,
      ex_swap_byte_instr => ex_swap_byte_instr,
      \ex_swx_access__0\ => \ex_swx_access__0\,
      ex_unsigned_op => ex_unsigned_op,
      ex_use_carry => ex_use_carry,
      ex_valid => ex_valid,
      exception_reg(0) => instr_rd_reg(1),
      if_missed_fetch_reg_0 => \Use_Debug_Logic.Master_Core.Debug_Perf_n_43\,
      if_missed_fetch_reg_1 => \Use_Debug_Logic.Master_Core.Debug_Perf_n_40\,
      \in\(0) => \PreFetch_Buffer_I1/if_predecode\(0),
      in0 => Decode_I_n_437,
      lopt => lopt,
      lopt_1 => lopt_1,
      lopt_2 => lopt_2,
      mem_Exception_Taken => mem_Exception_Taken,
      mem_byte_access => mem_byte_access,
      mem_databus_access => mem_databus_access,
      mem_databus_read => mem_databus_read,
      mem_databus_write => mem_databus_write,
      mem_doublet_access => mem_doublet_access,
      \mem_pc_i_reg[0]\(31) => MEM_PC(0),
      \mem_pc_i_reg[0]\(30) => MEM_PC(1),
      \mem_pc_i_reg[0]\(29) => MEM_PC(2),
      \mem_pc_i_reg[0]\(28) => MEM_PC(3),
      \mem_pc_i_reg[0]\(27) => MEM_PC(4),
      \mem_pc_i_reg[0]\(26) => MEM_PC(5),
      \mem_pc_i_reg[0]\(25) => MEM_PC(6),
      \mem_pc_i_reg[0]\(24) => MEM_PC(7),
      \mem_pc_i_reg[0]\(23) => MEM_PC(8),
      \mem_pc_i_reg[0]\(22) => MEM_PC(9),
      \mem_pc_i_reg[0]\(21) => MEM_PC(10),
      \mem_pc_i_reg[0]\(20) => MEM_PC(11),
      \mem_pc_i_reg[0]\(19) => MEM_PC(12),
      \mem_pc_i_reg[0]\(18) => MEM_PC(13),
      \mem_pc_i_reg[0]\(17) => MEM_PC(14),
      \mem_pc_i_reg[0]\(16) => MEM_PC(15),
      \mem_pc_i_reg[0]\(15) => MEM_PC(16),
      \mem_pc_i_reg[0]\(14) => MEM_PC(17),
      \mem_pc_i_reg[0]\(13) => MEM_PC(18),
      \mem_pc_i_reg[0]\(12) => MEM_PC(19),
      \mem_pc_i_reg[0]\(11) => MEM_PC(20),
      \mem_pc_i_reg[0]\(10) => MEM_PC(21),
      \mem_pc_i_reg[0]\(9) => MEM_PC(22),
      \mem_pc_i_reg[0]\(8) => MEM_PC(23),
      \mem_pc_i_reg[0]\(7) => MEM_PC(24),
      \mem_pc_i_reg[0]\(6) => MEM_PC(25),
      \mem_pc_i_reg[0]\(5) => MEM_PC(26),
      \mem_pc_i_reg[0]\(4) => MEM_PC(27),
      \mem_pc_i_reg[0]\(3) => MEM_PC(28),
      \mem_pc_i_reg[0]\(2) => MEM_PC(29),
      \mem_pc_i_reg[0]\(1) => MEM_PC(30),
      \mem_pc_i_reg[0]\(0) => MEM_PC(31),
      \mem_pc_i_reg[0]_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_44\,
      mem_sel_msr => mem_sel_msr,
      of_gpr_op1_rd_addr(0 to 4) => of_gpr_op1_rd_addr(0 to 4),
      of_gpr_op3_rd_addr(0 to 4) => of_gpr_op3_rd_addr(0 to 4),
      of_imm_data(0 to 15) => of_imm_data(0 to 15),
      of_op1_sel_spr => of_op1_sel_spr,
      of_pause => of_pause,
      of_pause_reg_0 => \^e\(0),
      \out\ => \Shift_Logic_Module_I/I4\,
      p_231_in => p_231_in,
      \p_4_out__0\ => \p_4_out__0\,
      swap_result(23) => swap_result(8),
      swap_result(22) => swap_result(9),
      swap_result(21) => swap_result(10),
      swap_result(20) => swap_result(11),
      swap_result(19) => swap_result(12),
      swap_result(18) => swap_result(13),
      swap_result(17) => swap_result(14),
      swap_result(16) => swap_result(15),
      swap_result(15) => swap_result(16),
      swap_result(14) => swap_result(17),
      swap_result(13) => swap_result(18),
      swap_result(12) => swap_result(19),
      swap_result(11) => swap_result(20),
      swap_result(10) => swap_result(21),
      swap_result(9) => swap_result(22),
      swap_result(8) => swap_result(23),
      swap_result(7) => swap_result(24),
      swap_result(6) => swap_result(25),
      swap_result(5) => swap_result(26),
      swap_result(4) => swap_result(27),
      swap_result(3) => swap_result(28),
      swap_result(2) => swap_result(29),
      swap_result(1) => swap_result(30),
      swap_result(0) => swap_result(31),
      swap_result_reg(0 to 7) => swap_result_reg(0 to 7),
      sync_reset => sync_reset,
      wakeup_i(0 to 1) => wakeup_i(0 to 1),
      wb_Halted => wb_Halted,
      wb_PipeRun_i_reg_0(0) => wb_piperun,
      wb_byte_access => wb_byte_access,
      wb_databus_steered_read_data(7) => wb_databus_steered_read_data(24),
      wb_databus_steered_read_data(6) => wb_databus_steered_read_data(25),
      wb_databus_steered_read_data(5) => wb_databus_steered_read_data(26),
      wb_databus_steered_read_data(4) => wb_databus_steered_read_data(27),
      wb_databus_steered_read_data(3) => wb_databus_steered_read_data(28),
      wb_databus_steered_read_data(2) => wb_databus_steered_read_data(29),
      wb_databus_steered_read_data(1) => wb_databus_steered_read_data(30),
      wb_databus_steered_read_data(0) => wb_databus_steered_read_data(31),
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_gpr_write_dbg_reg_0(23) => Decode_I_n_396,
      wb_gpr_write_dbg_reg_0(22) => Decode_I_n_397,
      wb_gpr_write_dbg_reg_0(21) => Decode_I_n_398,
      wb_gpr_write_dbg_reg_0(20) => Decode_I_n_399,
      wb_gpr_write_dbg_reg_0(19) => Decode_I_n_400,
      wb_gpr_write_dbg_reg_0(18) => Decode_I_n_401,
      wb_gpr_write_dbg_reg_0(17) => Decode_I_n_402,
      wb_gpr_write_dbg_reg_0(16) => Decode_I_n_403,
      wb_gpr_write_dbg_reg_0(15) => Decode_I_n_404,
      wb_gpr_write_dbg_reg_0(14) => Decode_I_n_405,
      wb_gpr_write_dbg_reg_0(13) => Decode_I_n_406,
      wb_gpr_write_dbg_reg_0(12) => Decode_I_n_407,
      wb_gpr_write_dbg_reg_0(11) => Decode_I_n_408,
      wb_gpr_write_dbg_reg_0(10) => Decode_I_n_409,
      wb_gpr_write_dbg_reg_0(9) => Decode_I_n_410,
      wb_gpr_write_dbg_reg_0(8) => Decode_I_n_411,
      wb_gpr_write_dbg_reg_0(7) => Decode_I_n_412,
      wb_gpr_write_dbg_reg_0(6) => Decode_I_n_413,
      wb_gpr_write_dbg_reg_0(5) => Decode_I_n_414,
      wb_gpr_write_dbg_reg_0(4) => Decode_I_n_415,
      wb_gpr_write_dbg_reg_0(3) => Decode_I_n_416,
      wb_gpr_write_dbg_reg_0(2) => Decode_I_n_417,
      wb_gpr_write_dbg_reg_0(1) => Decode_I_n_418,
      wb_gpr_write_dbg_reg_0(0) => Decode_I_n_419,
      wb_pc_valid => wb_pc_valid,
      wb_read_imm_reg => wb_read_imm_reg,
      wb_read_imm_reg_1 => wb_read_imm_reg_1,
      wb_valid_reg_0 => Decode_I_n_258
    );
\Use_DBUS.DAXI_Interface_I1\: entity work.design_1_microblaze_0_0_DAXI_interface
     port map (
      Clk => Clk,
      D(2) => \^d\(220),
      D(1 downto 0) => \^d\(183 downto 182),
      DReady => DReady,
      \LOCKSTEP_Out_reg[3023]\ => Data_Flow_I_n_185,
      \LOCKSTEP_Out_reg[3031]\(1) => Data_Flow_I_n_429,
      \LOCKSTEP_Out_reg[3031]\(0) => Data_Flow_I_n_430,
      MEM_DataBus_Ready => MEM_DataBus_Ready,
      M_AXI_DP_ARVALID_i_reg_0 => Decode_I_n_426,
      M_AXI_DP_AWVALID_i_reg_0 => Decode_I_n_425,
      M_AXI_DP_BVALID => M_AXI_DP_BVALID,
      M_AXI_DP_RDATA(31 downto 0) => M_AXI_DP_RDATA(31 downto 0),
      M_AXI_DP_RVALID => M_AXI_DP_RVALID,
      M_AXI_DP_WVALID_i_reg_0 => Decode_I_n_424,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg\ => \Use_DBUS.DAXI_Interface_I1_n_14\,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0\ => \Use_DBUS.DAXI_Interface_I1_n_15\,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1\ => \Use_DBUS.DAXI_Interface_I1_n_16\,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2\ => \Use_DBUS.DAXI_Interface_I1_n_17\,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3\ => \Use_DBUS.DAXI_Interface_I1_n_18\,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4\ => \Use_DBUS.DAXI_Interface_I1_n_19\,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5\ => \Use_DBUS.DAXI_Interface_I1_n_20\,
      \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6\ => \Use_DBUS.DAXI_Interface_I1_n_21\,
      Q(31) => wb_dlmb_valid_read_data(0),
      Q(30) => wb_dlmb_valid_read_data(1),
      Q(29) => wb_dlmb_valid_read_data(2),
      Q(28) => wb_dlmb_valid_read_data(3),
      Q(27) => wb_dlmb_valid_read_data(4),
      Q(26) => wb_dlmb_valid_read_data(5),
      Q(25) => wb_dlmb_valid_read_data(6),
      Q(24) => wb_dlmb_valid_read_data(7),
      Q(23) => wb_dlmb_valid_read_data(8),
      Q(22) => wb_dlmb_valid_read_data(9),
      Q(21) => wb_dlmb_valid_read_data(10),
      Q(20) => wb_dlmb_valid_read_data(11),
      Q(19) => wb_dlmb_valid_read_data(12),
      Q(18) => wb_dlmb_valid_read_data(13),
      Q(17) => wb_dlmb_valid_read_data(14),
      Q(16) => wb_dlmb_valid_read_data(15),
      Q(15) => wb_dlmb_valid_read_data(16),
      Q(14) => wb_dlmb_valid_read_data(17),
      Q(13) => wb_dlmb_valid_read_data(18),
      Q(12) => wb_dlmb_valid_read_data(19),
      Q(11) => wb_dlmb_valid_read_data(20),
      Q(10) => wb_dlmb_valid_read_data(21),
      Q(9) => wb_dlmb_valid_read_data(22),
      Q(8) => wb_dlmb_valid_read_data(23),
      Q(7) => wb_dlmb_valid_read_data(24),
      Q(6) => wb_dlmb_valid_read_data(25),
      Q(5) => wb_dlmb_valid_read_data(26),
      Q(4) => wb_dlmb_valid_read_data(27),
      Q(3) => wb_dlmb_valid_read_data(28),
      Q(2) => wb_dlmb_valid_read_data(29),
      Q(1) => wb_dlmb_valid_read_data(30),
      Q(0) => wb_dlmb_valid_read_data(31),
      \Use_DLMB.wb_dlmb_valid_read_data_reg[16]\ => \Use_DBUS.DAXI_Interface_I1_n_29\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[17]\ => \Use_DBUS.DAXI_Interface_I1_n_28\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[18]\ => \Use_DBUS.DAXI_Interface_I1_n_27\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[19]\ => \Use_DBUS.DAXI_Interface_I1_n_26\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[20]\ => \Use_DBUS.DAXI_Interface_I1_n_25\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[21]\ => \Use_DBUS.DAXI_Interface_I1_n_24\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[22]\ => \Use_DBUS.DAXI_Interface_I1_n_23\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[23]\ => \Use_DBUS.DAXI_Interface_I1_n_22\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[24]\ => \Use_DBUS.DAXI_Interface_I1_n_37\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[25]\ => \Use_DBUS.DAXI_Interface_I1_n_36\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[26]\ => \Use_DBUS.DAXI_Interface_I1_n_35\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[27]\ => \Use_DBUS.DAXI_Interface_I1_n_34\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[28]\ => \Use_DBUS.DAXI_Interface_I1_n_33\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[29]\ => \Use_DBUS.DAXI_Interface_I1_n_32\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[30]\ => \Use_DBUS.DAXI_Interface_I1_n_31\,
      \Use_DLMB.wb_dlmb_valid_read_data_reg[31]\ => \Use_DBUS.DAXI_Interface_I1_n_30\,
      active_access => active_access,
      active_access_d1 => active_access_d1,
      active_access_reg_0 => Decode_I_n_423,
      sync_reset => sync_reset,
      wb_databus_steered_read_data(7) => wb_databus_steered_read_data(24),
      wb_databus_steered_read_data(6) => wb_databus_steered_read_data(25),
      wb_databus_steered_read_data(5) => wb_databus_steered_read_data(26),
      wb_databus_steered_read_data(4) => wb_databus_steered_read_data(27),
      wb_databus_steered_read_data(3) => wb_databus_steered_read_data(28),
      wb_databus_steered_read_data(2) => wb_databus_steered_read_data(29),
      wb_databus_steered_read_data(1) => wb_databus_steered_read_data(30),
      wb_databus_steered_read_data(0) => wb_databus_steered_read_data(31),
      wb_read_msb_doublet_sel => wb_read_msb_doublet_sel
    );
\Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1\: entity work.design_1_microblaze_0_0_MB_AND2B1L
     port map (
      D(0) => \^d\(259),
      E(0) => \^using_fpga.native\(0),
      SRI => SRI
    );
\Use_DLMB.wb_dlmb_valid_read_data[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => sync_reset,
      I1 => DReady,
      O => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(0),
      Q => wb_dlmb_valid_read_data(0),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(10),
      Q => wb_dlmb_valid_read_data(10),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(11),
      Q => wb_dlmb_valid_read_data(11),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(12),
      Q => wb_dlmb_valid_read_data(12),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(13),
      Q => wb_dlmb_valid_read_data(13),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(14),
      Q => wb_dlmb_valid_read_data(14),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(15),
      Q => wb_dlmb_valid_read_data(15),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(16),
      Q => wb_dlmb_valid_read_data(16),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(17),
      Q => wb_dlmb_valid_read_data(17),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(18),
      Q => wb_dlmb_valid_read_data(18),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(19),
      Q => wb_dlmb_valid_read_data(19),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(1),
      Q => wb_dlmb_valid_read_data(1),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(20),
      Q => wb_dlmb_valid_read_data(20),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(21),
      Q => wb_dlmb_valid_read_data(21),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(22),
      Q => wb_dlmb_valid_read_data(22),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(23),
      Q => wb_dlmb_valid_read_data(23),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(24),
      Q => wb_dlmb_valid_read_data(24),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(25),
      Q => wb_dlmb_valid_read_data(25),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(26),
      Q => wb_dlmb_valid_read_data(26),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(27),
      Q => wb_dlmb_valid_read_data(27),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(28),
      Q => wb_dlmb_valid_read_data(28),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(29),
      Q => wb_dlmb_valid_read_data(29),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(2),
      Q => wb_dlmb_valid_read_data(2),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(30),
      Q => wb_dlmb_valid_read_data(30),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(31),
      Q => wb_dlmb_valid_read_data(31),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(3),
      Q => wb_dlmb_valid_read_data(3),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(4),
      Q => wb_dlmb_valid_read_data(4),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(5),
      Q => wb_dlmb_valid_read_data(5),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(6),
      Q => wb_dlmb_valid_read_data(6),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(7),
      Q => wb_dlmb_valid_read_data(7),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(8),
      Q => wb_dlmb_valid_read_data(8),
      R => p_1_out
    );
\Use_DLMB.wb_dlmb_valid_read_data_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => Data_Read(9),
      Q => wb_dlmb_valid_read_data(9),
      R => p_1_out
    );
\Use_Debug_Logic.Master_Core.Debug_Perf\: entity work.design_1_microblaze_0_0_Debug
     port map (
      Address(0 to 31) => of_pc(0 to 31),
      Clk => Clk,
      Config_Reg_En => Config_Reg_En,
      D(2 downto 1) => \^d\(358 downto 357),
      D(0) => \^d\(71),
      Data_Read_Reg_En => Data_Read_Reg_En,
      Dbg_Capture => Dbg_Capture,
      Dbg_Clk => Dbg_Clk,
      Dbg_Reg_En(0 to 7) => Dbg_Reg_En(0 to 7),
      Dbg_Reg_En_0_sp_1 => Dbg_Reg_En_0_sn_1,
      Dbg_Shift => Dbg_Shift,
      Dbg_Stop => Dbg_Stop,
      Dbg_TDI => Dbg_TDI,
      Dbg_TDO => Dbg_TDO,
      Dbg_Trig_Ack_In(1 downto 0) => Dbg_Trig_Ack_In(1 downto 0),
      Dbg_Trig_Ack_Out(1 downto 0) => Dbg_Trig_Ack_Out(1 downto 0),
      Dbg_Trig_In(1 downto 0) => Dbg_Trig_In(1 downto 0),
      Dbg_Trig_Out(1 downto 0) => Dbg_Trig_Out(1 downto 0),
      Dbg_Update => Dbg_Update,
      LOCKSTEP_Master_Out(37 downto 36) => \^lockstep_master_out\(39 downto 38),
      LOCKSTEP_Master_Out(35) => \^lockstep_master_out\(36),
      LOCKSTEP_Master_Out(34 downto 0) => \^lockstep_master_out\(34 downto 0),
      Pause => Pause,
      \Performance_Debug_Control.dbg_freeze_nohalt_reg_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_44\,
      \Performance_Debug_Control.dbg_state_nohalt_reg_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_43\,
      \Performance_Debug_Control.dbg_stop_if_delay_i_reg_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_50\,
      \Performance_Debug_Control.dbg_stop_if_delay_i_reg_1\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_58\,
      \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_40\,
      \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1\ => Decode_I_n_427,
      \Performance_Debug_Control.ex_brki_hit_reg_0\ => Decode_I_n_430,
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0\(0) => \^d\(258),
      \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1\ => Decode_I_n_440,
      \Performance_Debug_Control.m0_dbg_hit_reg[0]_0\ => \^using_fpga.native_0\(0),
      \Performance_Debug_Control.wb_dbg_hit_reg[0]_0\ => \^using_fpga.native\(0),
      Q(0) => \Use_Debug_Logic.Master_Core.Debug_Perf_n_59\,
      Reset_Mode(0 to 1) => Reset_Mode(0 to 1),
      Scan_En => Scan_En,
      Scan_Reset => Scan_Reset,
      Scan_Reset_Sel => Scan_Reset_Sel,
      \Serial_Dbg_Intf.force_stop_cmd_i_reg_0\ => \Use_Debug_Logic.Master_Core.Debug_Perf_n_38\,
      \Serial_Dbg_Intf.status_reg_reg[22]_0\(0) => mem_databus_access,
      Sleep => \^sleep\,
      Sleep_Decode => Sleep_Decode,
      Sleep_Out => Sleep_Out,
      Status_Reg_En => Status_Reg_En,
      \Using_FPGA.Native_i_2__21\ => Decode_I_n_247,
      \Using_LWX_SWX_instr.ex_reservation_i_3\ => Decode_I_n_74,
      \data_rd_reg_reg[0]_0\(31) => Decode_I_n_396,
      \data_rd_reg_reg[0]_0\(30) => Decode_I_n_397,
      \data_rd_reg_reg[0]_0\(29) => Decode_I_n_398,
      \data_rd_reg_reg[0]_0\(28) => Decode_I_n_399,
      \data_rd_reg_reg[0]_0\(27) => Decode_I_n_400,
      \data_rd_reg_reg[0]_0\(26) => Decode_I_n_401,
      \data_rd_reg_reg[0]_0\(25) => Decode_I_n_402,
      \data_rd_reg_reg[0]_0\(24) => Decode_I_n_403,
      \data_rd_reg_reg[0]_0\(23) => Decode_I_n_404,
      \data_rd_reg_reg[0]_0\(22) => Decode_I_n_405,
      \data_rd_reg_reg[0]_0\(21) => Decode_I_n_406,
      \data_rd_reg_reg[0]_0\(20) => Decode_I_n_407,
      \data_rd_reg_reg[0]_0\(19) => Decode_I_n_408,
      \data_rd_reg_reg[0]_0\(18) => Decode_I_n_409,
      \data_rd_reg_reg[0]_0\(17) => Decode_I_n_410,
      \data_rd_reg_reg[0]_0\(16) => Decode_I_n_411,
      \data_rd_reg_reg[0]_0\(15) => Data_Flow_I_n_189,
      \data_rd_reg_reg[0]_0\(14) => Data_Flow_I_n_190,
      \data_rd_reg_reg[0]_0\(13) => Data_Flow_I_n_191,
      \data_rd_reg_reg[0]_0\(12) => Data_Flow_I_n_192,
      \data_rd_reg_reg[0]_0\(11) => Data_Flow_I_n_193,
      \data_rd_reg_reg[0]_0\(10) => Data_Flow_I_n_194,
      \data_rd_reg_reg[0]_0\(9) => Data_Flow_I_n_195,
      \data_rd_reg_reg[0]_0\(8) => Data_Flow_I_n_196,
      \data_rd_reg_reg[0]_0\(7) => Decode_I_n_412,
      \data_rd_reg_reg[0]_0\(6) => Decode_I_n_413,
      \data_rd_reg_reg[0]_0\(5) => Decode_I_n_414,
      \data_rd_reg_reg[0]_0\(4) => Decode_I_n_415,
      \data_rd_reg_reg[0]_0\(3) => Decode_I_n_416,
      \data_rd_reg_reg[0]_0\(2) => Decode_I_n_417,
      \data_rd_reg_reg[0]_0\(1) => Decode_I_n_418,
      \data_rd_reg_reg[0]_0\(0) => Decode_I_n_419,
      dbg_clean_stop => dbg_clean_stop,
      dbg_halt_reset_mode_reg_0 => \Use_Debug_Logic.Master_Core.Debug_Perf_n_42\,
      dbg_stop_i => dbg_stop_i,
      ex_Exception_Taken => ex_Exception_Taken,
      ex_MSR_Load_ALU_C => ex_MSR_Load_ALU_C,
      ex_MSR_Load_Shift_C => ex_MSR_Load_Shift_C,
      ex_MSR_Set_SW_BIP => ex_MSR_Set_SW_BIP,
      ex_exception_no_load_store_mask => ex_exception_no_load_store_mask,
      ex_is_load_instr_s => ex_is_load_instr_s,
      ex_load_shift_carry => ex_load_shift_carry,
      ex_valid => ex_valid,
      exception_reg_0(0) => instr_rd_reg(1),
      exception_reg_1 => Decode_I_n_438,
      executing_reg_0 => Decode_I_n_258,
      mem_Exception_Taken => mem_Exception_Taken,
      of_pause => of_pause,
      p_231_in => p_231_in,
      \p_4_out__0\ => \p_4_out__0\,
      read_register_MSR_1_reg_0 => \Use_Debug_Logic.Master_Core.Debug_Perf_n_39\,
      single_Step_N_reg_0 => \^e\(0),
      sync_reset => sync_reset,
      wakeup_i(0 to 1) => wakeup_i(0 to 1),
      wb_Halted => wb_Halted,
      wb_gpr_wr_dbg => wb_gpr_wr_dbg,
      wb_pc_valid => wb_pc_valid,
      wb_read_imm_reg => wb_read_imm_reg,
      wb_read_imm_reg_1 => wb_read_imm_reg_1
    );
instr_mux_I: entity work.design_1_microblaze_0_0_instr_mux
     port map (
      I139_out => \PreFetch_Buffer_I1/I139_out\,
      Instr(0 to 31) => Instr(0 to 31),
      LOCKSTEP_Master_Out(32) => \^lockstep_master_out\(38),
      LOCKSTEP_Master_Out(31 downto 0) => \^lockstep_master_out\(31 downto 0),
      \Using_FPGA.Native\(0) => \PreFetch_Buffer_I1/p_1_in49_in\,
      \Using_FPGA.Native_0\(0) => if_sel_input(3),
      Y(0 to 31) => ib_data(0 to 31),
      \in\(0) => \PreFetch_Buffer_I1/if_predecode\(0)
    );
trace_data_access_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => mem_databus_access,
      Q => \^d\(2),
      R => '0'
    );
\trace_data_address_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(252),
      Q => \^d\(70),
      R => '0'
    );
\trace_data_address_i_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(242),
      Q => \^d\(60),
      R => '0'
    );
\trace_data_address_i_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(241),
      Q => \^d\(59),
      R => '0'
    );
\trace_data_address_i_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(240),
      Q => \^d\(58),
      R => '0'
    );
\trace_data_address_i_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(239),
      Q => \^d\(57),
      R => '0'
    );
\trace_data_address_i_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(238),
      Q => \^d\(56),
      R => '0'
    );
\trace_data_address_i_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(237),
      Q => \^d\(55),
      R => '0'
    );
\trace_data_address_i_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(236),
      Q => \^d\(54),
      R => '0'
    );
\trace_data_address_i_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(235),
      Q => \^d\(53),
      R => '0'
    );
\trace_data_address_i_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(234),
      Q => \^d\(52),
      R => '0'
    );
\trace_data_address_i_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(233),
      Q => \^d\(51),
      R => '0'
    );
\trace_data_address_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(251),
      Q => \^d\(69),
      R => '0'
    );
\trace_data_address_i_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(232),
      Q => \^d\(50),
      R => '0'
    );
\trace_data_address_i_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(231),
      Q => \^d\(49),
      R => '0'
    );
\trace_data_address_i_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(230),
      Q => \^d\(48),
      R => '0'
    );
\trace_data_address_i_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(229),
      Q => \^d\(47),
      R => '0'
    );
\trace_data_address_i_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(228),
      Q => \^d\(46),
      R => '0'
    );
\trace_data_address_i_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(227),
      Q => \^d\(45),
      R => '0'
    );
\trace_data_address_i_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(226),
      Q => \^d\(44),
      R => '0'
    );
\trace_data_address_i_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(225),
      Q => \^d\(43),
      R => '0'
    );
\trace_data_address_i_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(224),
      Q => \^d\(42),
      R => '0'
    );
\trace_data_address_i_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(223),
      Q => \^d\(41),
      R => '0'
    );
\trace_data_address_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(250),
      Q => \^d\(68),
      R => '0'
    );
\trace_data_address_i_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(222),
      Q => \^d\(40),
      R => '0'
    );
\trace_data_address_i_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(221),
      Q => \^d\(39),
      R => '0'
    );
\trace_data_address_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(249),
      Q => \^d\(67),
      R => '0'
    );
\trace_data_address_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(248),
      Q => \^d\(66),
      R => '0'
    );
\trace_data_address_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(247),
      Q => \^d\(65),
      R => '0'
    );
\trace_data_address_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(246),
      Q => \^d\(64),
      R => '0'
    );
\trace_data_address_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(245),
      Q => \^d\(63),
      R => '0'
    );
\trace_data_address_i_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(244),
      Q => \^d\(62),
      R => '0'
    );
\trace_data_address_i_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(243),
      Q => \^d\(61),
      R => '0'
    );
\trace_data_byte_enable_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(187),
      Q => \^d\(6),
      R => '0'
    );
\trace_data_byte_enable_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(186),
      Q => \^d\(5),
      R => '0'
    );
\trace_data_byte_enable_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(185),
      Q => \^d\(4),
      R => '0'
    );
\trace_data_byte_enable_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(184),
      Q => \^d\(3),
      R => '0'
    );
trace_data_read_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => mem_databus_read,
      Q => \^d\(1),
      R => '0'
    );
trace_data_write_i_reg: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => mem_databus_write,
      Q => \^d\(0),
      R => '0'
    );
\trace_data_write_value_i_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(219),
      Q => \^d\(38),
      R => '0'
    );
\trace_data_write_value_i_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(209),
      Q => \^d\(28),
      R => '0'
    );
\trace_data_write_value_i_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(208),
      Q => \^d\(27),
      R => '0'
    );
\trace_data_write_value_i_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(207),
      Q => \^d\(26),
      R => '0'
    );
\trace_data_write_value_i_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(206),
      Q => \^d\(25),
      R => '0'
    );
\trace_data_write_value_i_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(205),
      Q => \^d\(24),
      R => '0'
    );
\trace_data_write_value_i_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(204),
      Q => \^d\(23),
      R => '0'
    );
\trace_data_write_value_i_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(203),
      Q => \^d\(22),
      R => '0'
    );
\trace_data_write_value_i_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(202),
      Q => \^d\(21),
      R => '0'
    );
\trace_data_write_value_i_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(201),
      Q => \^d\(20),
      R => '0'
    );
\trace_data_write_value_i_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(200),
      Q => \^d\(19),
      R => '0'
    );
\trace_data_write_value_i_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(218),
      Q => \^d\(37),
      R => '0'
    );
\trace_data_write_value_i_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(199),
      Q => \^d\(18),
      R => '0'
    );
\trace_data_write_value_i_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(198),
      Q => \^d\(17),
      R => '0'
    );
\trace_data_write_value_i_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(197),
      Q => \^d\(16),
      R => '0'
    );
\trace_data_write_value_i_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(196),
      Q => \^d\(15),
      R => '0'
    );
\trace_data_write_value_i_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(195),
      Q => \^d\(14),
      R => '0'
    );
\trace_data_write_value_i_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(194),
      Q => \^d\(13),
      R => '0'
    );
\trace_data_write_value_i_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(193),
      Q => \^d\(12),
      R => '0'
    );
\trace_data_write_value_i_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(192),
      Q => \^d\(11),
      R => '0'
    );
\trace_data_write_value_i_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(191),
      Q => \^d\(10),
      R => '0'
    );
\trace_data_write_value_i_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(190),
      Q => \^d\(9),
      R => '0'
    );
\trace_data_write_value_i_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(217),
      Q => \^d\(36),
      R => '0'
    );
\trace_data_write_value_i_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(189),
      Q => \^d\(8),
      R => '0'
    );
\trace_data_write_value_i_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(188),
      Q => \^d\(7),
      R => '0'
    );
\trace_data_write_value_i_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(216),
      Q => \^d\(35),
      R => '0'
    );
\trace_data_write_value_i_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(215),
      Q => \^d\(34),
      R => '0'
    );
\trace_data_write_value_i_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(214),
      Q => \^d\(33),
      R => '0'
    );
\trace_data_write_value_i_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(213),
      Q => \^d\(32),
      R => '0'
    );
\trace_data_write_value_i_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(212),
      Q => \^d\(31),
      R => '0'
    );
\trace_data_write_value_i_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(211),
      Q => \^d\(30),
      R => '0'
    );
\trace_data_write_value_i_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => \^using_fpga.native\(0),
      D => \^d\(210),
      Q => \^d\(29),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MicroBlaze_Core is
  port (
    of_pause_reg : out STD_LOGIC;
    \Using_FPGA.Native\ : out STD_LOGIC;
    \Using_FPGA.Native_0\ : out STD_LOGIC;
    Hibernate : out STD_LOGIC;
    Suspend : out STD_LOGIC;
    Pause_Ack : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 358 downto 0 );
    Sleep : out STD_LOGIC;
    LOCKSTEP_Master_Out : out STD_LOGIC_VECTOR ( 40 downto 0 );
    Dbg_Trig_In : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_Trig_Ack_Out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_Reg_En_0_sp_1 : out STD_LOGIC;
    Dbg_TDO : out STD_LOGIC;
    Clk : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    Dbg_Trig_Ack_In : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_Trig_Out : in STD_LOGIC_VECTOR ( 1 downto 0 );
    Pause : in STD_LOGIC;
    Dbg_Update : in STD_LOGIC;
    Dbg_Stop : in STD_LOGIC;
    Dbg_Capture : in STD_LOGIC;
    Reset : in STD_LOGIC;
    Mb_Reset : in STD_LOGIC;
    Debug_Rst : in STD_LOGIC;
    M_AXI_DP_BVALID : in STD_LOGIC;
    M_AXI_DP_RVALID : in STD_LOGIC;
    M_AXI_DP_WREADY : in STD_LOGIC;
    M_AXI_DP_AWREADY : in STD_LOGIC;
    M_AXI_DP_ARREADY : in STD_LOGIC;
    Reset_Mode : in STD_LOGIC_VECTOR ( 0 to 1 );
    Data_Read_Reg_En : in STD_LOGIC;
    Config_Reg_En : in STD_LOGIC;
    IReady : in STD_LOGIC;
    Dbg_Shift : in STD_LOGIC;
    DReady : in STD_LOGIC;
    DWait : in STD_LOGIC;
    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
    Status_Reg_En : in STD_LOGIC;
    Scan_Reset_Sel : in STD_LOGIC;
    Scan_Reset : in STD_LOGIC;
    Scan_En : in STD_LOGIC;
    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
    M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_TDI : in STD_LOGIC;
    Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
    Wakeup : in STD_LOGIC_VECTOR ( 0 to 1 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MicroBlaze_Core : entity is "MicroBlaze_Core";
end design_1_microblaze_0_0_MicroBlaze_Core;

architecture STRUCTURE of design_1_microblaze_0_0_MicroBlaze_Core is
  signal Dbg_Reg_En_0_sn_1 : STD_LOGIC;
  signal Synced : STD_LOGIC;
  signal \reset_temp__0\ : STD_LOGIC;
  signal sync_reset : STD_LOGIC;
  signal wakeup_i : STD_LOGIC_VECTOR ( 0 to 1 );
begin
  Dbg_Reg_En_0_sp_1 <= Dbg_Reg_En_0_sn_1;
\Performance.Core\: entity work.design_1_microblaze_0_0_MicroBlaze_GTi
     port map (
      Clk => Clk,
      Config_Reg_En => Config_Reg_En,
      D(358 downto 0) => D(358 downto 0),
      DReady => DReady,
      DWait => DWait,
      Data_Read(0 to 31) => Data_Read(0 to 31),
      Data_Read_Reg_En => Data_Read_Reg_En,
      Dbg_Capture => Dbg_Capture,
      Dbg_Clk => Dbg_Clk,
      Dbg_Reg_En(0 to 7) => Dbg_Reg_En(0 to 7),
      Dbg_Reg_En_0_sp_1 => Dbg_Reg_En_0_sn_1,
      Dbg_Shift => Dbg_Shift,
      Dbg_Stop => Dbg_Stop,
      Dbg_TDI => Dbg_TDI,
      Dbg_TDO => Dbg_TDO,
      Dbg_Trig_Ack_In(1 downto 0) => Dbg_Trig_Ack_In(1 downto 0),
      Dbg_Trig_Ack_Out(1 downto 0) => Dbg_Trig_Ack_Out(1 downto 0),
      Dbg_Trig_In(1 downto 0) => Dbg_Trig_In(1 downto 0),
      Dbg_Trig_Out(1 downto 0) => Dbg_Trig_Out(1 downto 0),
      Dbg_Update => Dbg_Update,
      E(0) => of_pause_reg,
      Hibernate => Hibernate,
      IReady => IReady,
      Instr(0 to 31) => Instr(0 to 31),
      LOCKSTEP_Master_Out(40 downto 0) => LOCKSTEP_Master_Out(40 downto 0),
      M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
      M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
      M_AXI_DP_BVALID => M_AXI_DP_BVALID,
      M_AXI_DP_RDATA(31 downto 0) => M_AXI_DP_RDATA(31 downto 0),
      M_AXI_DP_RVALID => M_AXI_DP_RVALID,
      M_AXI_DP_WREADY => M_AXI_DP_WREADY,
      Pause => Pause,
      Pause_Ack => Pause_Ack,
      Reset_Mode(0 to 1) => Reset_Mode(0 to 1),
      Scan_En => Scan_En,
      Scan_Reset => Scan_Reset,
      Scan_Reset_Sel => Scan_Reset_Sel,
      Sleep => Sleep,
      Status_Reg_En => Status_Reg_En,
      Suspend => Suspend,
      \Using_FPGA.Native\(0) => \Using_FPGA.Native\,
      \Using_FPGA.Native_0\(0) => \Using_FPGA.Native_0\,
      sync_reset => sync_reset,
      wakeup_i(0 to 1) => wakeup_i(0 to 1)
    );
Reset_DFF: entity work.design_1_microblaze_0_0_mb_sync_bit
     port map (
      Clk => Clk,
      \out\(0) => Synced,
      reset_temp => \reset_temp__0\
    );
\Use_Async_Reset.sync_reset_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => Clk,
      CE => '1',
      D => Synced,
      Q => sync_reset,
      R => '0'
    );
\Using_Async_Wakeup_0.Wakeup_DFF\: entity work.design_1_microblaze_0_0_mb_sync_bit_0
     port map (
      Clk => Clk,
      SR(0) => sync_reset,
      Wakeup(0) => Wakeup(0),
      \out\(0) => wakeup_i(0)
    );
\Using_Async_Wakeup_1.Wakeup_DFF\: entity work.design_1_microblaze_0_0_mb_sync_bit_1
     port map (
      Clk => Clk,
      SR(0) => sync_reset,
      Wakeup(0) => Wakeup(1),
      \out\(0) => wakeup_i(1)
    );
reset_temp: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => Reset,
      I1 => Mb_Reset,
      I2 => Debug_Rst,
      O => \reset_temp__0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0_MicroBlaze is
  port (
    RAM_To : in STD_LOGIC_VECTOR ( 255 downto 0 );
    RAM_From : out STD_LOGIC_VECTOR ( 255 downto 0 );
    Clk : in STD_LOGIC;
    Reset : in STD_LOGIC;
    Mb_Reset : in STD_LOGIC;
    Config_Reset : in STD_LOGIC;
    Scan_Reset_Sel : in STD_LOGIC;
    Scan_Reset : in STD_LOGIC;
    Scan_En : in STD_LOGIC;
    Reset_Mode : in STD_LOGIC_VECTOR ( 0 to 1 );
    Non_Secure : in STD_LOGIC_VECTOR ( 0 to 3 );
    Interrupt : in STD_LOGIC;
    Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
    Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
    Ext_BRK : in STD_LOGIC;
    Ext_NM_BRK : in STD_LOGIC;
    Pause : in STD_LOGIC;
    Pause_Ack : out STD_LOGIC;
    Dbg_Continue : out STD_LOGIC;
    Dbg_Stop : in STD_LOGIC;
    Dbg_Intr : out STD_LOGIC;
    MB_Halted : out STD_LOGIC;
    MB_Error : out STD_LOGIC;
    Wakeup : in STD_LOGIC_VECTOR ( 0 to 1 );
    Sleep : out STD_LOGIC;
    Hibernate : out STD_LOGIC;
    Suspend : out STD_LOGIC;
    Dbg_Wakeup : out STD_LOGIC;
    LOCKSTEP_Slave_In : in STD_LOGIC_VECTOR ( 0 to 4095 );
    LOCKSTEP_Master_Out : out STD_LOGIC_VECTOR ( 0 to 4095 );
    LOCKSTEP_Out : out STD_LOGIC_VECTOR ( 0 to 4095 );
    Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
    IFetch : out STD_LOGIC;
    I_AS : out STD_LOGIC;
    IReady : in STD_LOGIC;
    IWAIT : in STD_LOGIC;
    ICE : in STD_LOGIC;
    IUE : in STD_LOGIC;
    M_AXI_IP_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IP_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_IP_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IP_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IP_AWLOCK : out STD_LOGIC;
    M_AXI_IP_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IP_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IP_AWVALID : out STD_LOGIC;
    M_AXI_IP_AWREADY : in STD_LOGIC;
    M_AXI_IP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IP_WLAST : out STD_LOGIC;
    M_AXI_IP_WVALID : out STD_LOGIC;
    M_AXI_IP_WREADY : in STD_LOGIC;
    M_AXI_IP_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IP_BVALID : in STD_LOGIC;
    M_AXI_IP_BREADY : out STD_LOGIC;
    M_AXI_IP_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IP_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_IP_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IP_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IP_ARLOCK : out STD_LOGIC;
    M_AXI_IP_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IP_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IP_ARVALID : out STD_LOGIC;
    M_AXI_IP_ARREADY : in STD_LOGIC;
    M_AXI_IP_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IP_RLAST : in STD_LOGIC;
    M_AXI_IP_RVALID : in STD_LOGIC;
    M_AXI_IP_RREADY : out STD_LOGIC;
    Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
    Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
    Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
    D_AS : out STD_LOGIC;
    Read_Strobe : out STD_LOGIC;
    Write_Strobe : out STD_LOGIC;
    DReady : in STD_LOGIC;
    DWait : in STD_LOGIC;
    DCE : in STD_LOGIC;
    DUE : in STD_LOGIC;
    Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
    M_AXI_DP_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_DP_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DP_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DP_AWLOCK : out STD_LOGIC;
    M_AXI_DP_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DP_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DP_AWVALID : out STD_LOGIC;
    M_AXI_DP_AWREADY : in STD_LOGIC;
    M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DP_WLAST : out STD_LOGIC;
    M_AXI_DP_WVALID : out STD_LOGIC;
    M_AXI_DP_WREADY : in STD_LOGIC;
    M_AXI_DP_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DP_BVALID : in STD_LOGIC;
    M_AXI_DP_BREADY : out STD_LOGIC;
    M_AXI_DP_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_DP_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DP_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DP_ARLOCK : out STD_LOGIC;
    M_AXI_DP_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DP_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DP_ARVALID : out STD_LOGIC;
    M_AXI_DP_ARREADY : in STD_LOGIC;
    M_AXI_DP_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DP_RLAST : in STD_LOGIC;
    M_AXI_DP_RVALID : in STD_LOGIC;
    M_AXI_DP_RREADY : out STD_LOGIC;
    Dbg_Disable : in STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    Dbg_TDI : in STD_LOGIC;
    Dbg_TDO : out STD_LOGIC;
    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Shift : in STD_LOGIC;
    Dbg_Capture : in STD_LOGIC;
    Dbg_Update : in STD_LOGIC;
    Debug_Rst : in STD_LOGIC;
    Dbg_Trig_In : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_In : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Out : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trig_Ack_Out : out STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Trace_Clk : in STD_LOGIC;
    Dbg_Trace_Data : out STD_LOGIC_VECTOR ( 0 to 35 );
    Dbg_Trace_Ready : in STD_LOGIC;
    Dbg_Trace_Valid : out STD_LOGIC;
    Dbg_AWADDR : in STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_AWVALID : in STD_LOGIC;
    Dbg_AWREADY : out STD_LOGIC;
    Dbg_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_WVALID : in STD_LOGIC;
    Dbg_WREADY : out STD_LOGIC;
    Dbg_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_BVALID : out STD_LOGIC;
    Dbg_BREADY : in STD_LOGIC;
    Dbg_ARADDR : in STD_LOGIC_VECTOR ( 14 downto 2 );
    Dbg_ARVALID : in STD_LOGIC;
    Dbg_ARREADY : out STD_LOGIC;
    Dbg_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    Dbg_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Dbg_RVALID : out STD_LOGIC;
    Dbg_RREADY : in STD_LOGIC;
    DEBUG_ACLK : in STD_LOGIC;
    DEBUG_ARESETN : in STD_LOGIC;
    Trace_Instruction : out STD_LOGIC_VECTOR ( 0 to 31 );
    Trace_Valid_Instr : out STD_LOGIC;
    Trace_PC : out STD_LOGIC_VECTOR ( 0 to 31 );
    Trace_Reg_Write : out STD_LOGIC;
    Trace_Reg_Addr : out STD_LOGIC_VECTOR ( 0 to 4 );
    Trace_MSR_Reg : out STD_LOGIC_VECTOR ( 0 to 14 );
    Trace_PID_Reg : out STD_LOGIC_VECTOR ( 0 to 7 );
    Trace_New_Reg_Value : out STD_LOGIC_VECTOR ( 0 to 31 );
    Trace_Exception_Taken : out STD_LOGIC;
    Trace_Exception_Kind : out STD_LOGIC_VECTOR ( 0 to 4 );
    Trace_Jump_Taken : out STD_LOGIC;
    Trace_Delay_Slot : out STD_LOGIC;
    Trace_Data_Address : out STD_LOGIC_VECTOR ( 0 to 31 );
    Trace_Data_Write_Value : out STD_LOGIC_VECTOR ( 0 to 31 );
    Trace_Data_Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
    Trace_Data_Access : out STD_LOGIC;
    Trace_Data_Read : out STD_LOGIC;
    Trace_Data_Write : out STD_LOGIC;
    Trace_DCache_Req : out STD_LOGIC;
    Trace_DCache_Hit : out STD_LOGIC;
    Trace_DCache_Rdy : out STD_LOGIC;
    Trace_DCache_Read : out STD_LOGIC;
    Trace_ICache_Req : out STD_LOGIC;
    Trace_ICache_Hit : out STD_LOGIC;
    Trace_ICache_Rdy : out STD_LOGIC;
    Trace_OF_PipeRun : out STD_LOGIC;
    Trace_EX_PipeRun : out STD_LOGIC;
    Trace_MEM_PipeRun : out STD_LOGIC;
    Trace_MB_Halted : out STD_LOGIC;
    Trace_Jump_Hit : out STD_LOGIC;
    M0_AXIS_TLAST : out STD_LOGIC;
    M0_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M0_AXIS_TVALID : out STD_LOGIC;
    M0_AXIS_TREADY : in STD_LOGIC;
    M1_AXIS_TLAST : out STD_LOGIC;
    M1_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M1_AXIS_TVALID : out STD_LOGIC;
    M1_AXIS_TREADY : in STD_LOGIC;
    M2_AXIS_TLAST : out STD_LOGIC;
    M2_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M2_AXIS_TVALID : out STD_LOGIC;
    M2_AXIS_TREADY : in STD_LOGIC;
    M3_AXIS_TLAST : out STD_LOGIC;
    M3_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M3_AXIS_TVALID : out STD_LOGIC;
    M3_AXIS_TREADY : in STD_LOGIC;
    M4_AXIS_TLAST : out STD_LOGIC;
    M4_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M4_AXIS_TVALID : out STD_LOGIC;
    M4_AXIS_TREADY : in STD_LOGIC;
    M5_AXIS_TLAST : out STD_LOGIC;
    M5_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M5_AXIS_TVALID : out STD_LOGIC;
    M5_AXIS_TREADY : in STD_LOGIC;
    M6_AXIS_TLAST : out STD_LOGIC;
    M6_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M6_AXIS_TVALID : out STD_LOGIC;
    M6_AXIS_TREADY : in STD_LOGIC;
    M7_AXIS_TLAST : out STD_LOGIC;
    M7_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M7_AXIS_TVALID : out STD_LOGIC;
    M7_AXIS_TREADY : in STD_LOGIC;
    M8_AXIS_TLAST : out STD_LOGIC;
    M8_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M8_AXIS_TVALID : out STD_LOGIC;
    M8_AXIS_TREADY : in STD_LOGIC;
    M9_AXIS_TLAST : out STD_LOGIC;
    M9_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M9_AXIS_TVALID : out STD_LOGIC;
    M9_AXIS_TREADY : in STD_LOGIC;
    M10_AXIS_TLAST : out STD_LOGIC;
    M10_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M10_AXIS_TVALID : out STD_LOGIC;
    M10_AXIS_TREADY : in STD_LOGIC;
    M11_AXIS_TLAST : out STD_LOGIC;
    M11_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M11_AXIS_TVALID : out STD_LOGIC;
    M11_AXIS_TREADY : in STD_LOGIC;
    M12_AXIS_TLAST : out STD_LOGIC;
    M12_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M12_AXIS_TVALID : out STD_LOGIC;
    M12_AXIS_TREADY : in STD_LOGIC;
    M13_AXIS_TLAST : out STD_LOGIC;
    M13_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M13_AXIS_TVALID : out STD_LOGIC;
    M13_AXIS_TREADY : in STD_LOGIC;
    M14_AXIS_TLAST : out STD_LOGIC;
    M14_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M14_AXIS_TVALID : out STD_LOGIC;
    M14_AXIS_TREADY : in STD_LOGIC;
    M15_AXIS_TLAST : out STD_LOGIC;
    M15_AXIS_TDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M15_AXIS_TVALID : out STD_LOGIC;
    M15_AXIS_TREADY : in STD_LOGIC;
    S0_AXIS_TLAST : in STD_LOGIC;
    S0_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S0_AXIS_TVALID : in STD_LOGIC;
    S0_AXIS_TREADY : out STD_LOGIC;
    S1_AXIS_TLAST : in STD_LOGIC;
    S1_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S1_AXIS_TVALID : in STD_LOGIC;
    S1_AXIS_TREADY : out STD_LOGIC;
    S2_AXIS_TLAST : in STD_LOGIC;
    S2_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S2_AXIS_TVALID : in STD_LOGIC;
    S2_AXIS_TREADY : out STD_LOGIC;
    S3_AXIS_TLAST : in STD_LOGIC;
    S3_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S3_AXIS_TVALID : in STD_LOGIC;
    S3_AXIS_TREADY : out STD_LOGIC;
    S4_AXIS_TLAST : in STD_LOGIC;
    S4_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S4_AXIS_TVALID : in STD_LOGIC;
    S4_AXIS_TREADY : out STD_LOGIC;
    S5_AXIS_TLAST : in STD_LOGIC;
    S5_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S5_AXIS_TVALID : in STD_LOGIC;
    S5_AXIS_TREADY : out STD_LOGIC;
    S6_AXIS_TLAST : in STD_LOGIC;
    S6_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S6_AXIS_TVALID : in STD_LOGIC;
    S6_AXIS_TREADY : out STD_LOGIC;
    S7_AXIS_TLAST : in STD_LOGIC;
    S7_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S7_AXIS_TVALID : in STD_LOGIC;
    S7_AXIS_TREADY : out STD_LOGIC;
    S8_AXIS_TLAST : in STD_LOGIC;
    S8_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S8_AXIS_TVALID : in STD_LOGIC;
    S8_AXIS_TREADY : out STD_LOGIC;
    S9_AXIS_TLAST : in STD_LOGIC;
    S9_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S9_AXIS_TVALID : in STD_LOGIC;
    S9_AXIS_TREADY : out STD_LOGIC;
    S10_AXIS_TLAST : in STD_LOGIC;
    S10_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S10_AXIS_TVALID : in STD_LOGIC;
    S10_AXIS_TREADY : out STD_LOGIC;
    S11_AXIS_TLAST : in STD_LOGIC;
    S11_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S11_AXIS_TVALID : in STD_LOGIC;
    S11_AXIS_TREADY : out STD_LOGIC;
    S12_AXIS_TLAST : in STD_LOGIC;
    S12_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S12_AXIS_TVALID : in STD_LOGIC;
    S12_AXIS_TREADY : out STD_LOGIC;
    S13_AXIS_TLAST : in STD_LOGIC;
    S13_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S13_AXIS_TVALID : in STD_LOGIC;
    S13_AXIS_TREADY : out STD_LOGIC;
    S14_AXIS_TLAST : in STD_LOGIC;
    S14_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S14_AXIS_TVALID : in STD_LOGIC;
    S14_AXIS_TREADY : out STD_LOGIC;
    S15_AXIS_TLAST : in STD_LOGIC;
    S15_AXIS_TDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    S15_AXIS_TVALID : in STD_LOGIC;
    S15_AXIS_TREADY : out STD_LOGIC;
    M_AXI_IC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_IC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_AWLOCK : out STD_LOGIC;
    M_AXI_IC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IC_AWVALID : out STD_LOGIC;
    M_AXI_IC_AWREADY : in STD_LOGIC;
    M_AXI_IC_AWUSER : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M_AXI_IC_AWDOMAIN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_AWSNOOP : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IC_AWBAR : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IC_WLAST : out STD_LOGIC;
    M_AXI_IC_WVALID : out STD_LOGIC;
    M_AXI_IC_WREADY : in STD_LOGIC;
    M_AXI_IC_WUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_BVALID : in STD_LOGIC;
    M_AXI_IC_BREADY : out STD_LOGIC;
    M_AXI_IC_BUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IC_WACK : out STD_LOGIC;
    M_AXI_IC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_IC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_ARLOCK : out STD_LOGIC;
    M_AXI_IC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IC_ARVALID : out STD_LOGIC;
    M_AXI_IC_ARREADY : in STD_LOGIC;
    M_AXI_IC_ARUSER : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M_AXI_IC_ARDOMAIN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_ARSNOOP : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IC_ARBAR : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_IC_RLAST : in STD_LOGIC;
    M_AXI_IC_RVALID : in STD_LOGIC;
    M_AXI_IC_RREADY : out STD_LOGIC;
    M_AXI_IC_RUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_IC_RACK : out STD_LOGIC;
    M_AXI_IC_ACVALID : in STD_LOGIC;
    M_AXI_IC_ACADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IC_ACSNOOP : in STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_IC_ACPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_IC_ACREADY : out STD_LOGIC;
    M_AXI_IC_CRVALID : out STD_LOGIC;
    M_AXI_IC_CRRESP : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M_AXI_IC_CRREADY : in STD_LOGIC;
    M_AXI_IC_CDVALID : out STD_LOGIC;
    M_AXI_IC_CDDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_IC_CDLAST : out STD_LOGIC;
    M_AXI_IC_CDREADY : in STD_LOGIC;
    M_AXI_DC_AWID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DC_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DC_AWLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_DC_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DC_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_AWLOCK : out STD_LOGIC;
    M_AXI_DC_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DC_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DC_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DC_AWVALID : out STD_LOGIC;
    M_AXI_DC_AWREADY : in STD_LOGIC;
    M_AXI_DC_AWUSER : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M_AXI_DC_AWDOMAIN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_AWSNOOP : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DC_AWBAR : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DC_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DC_WLAST : out STD_LOGIC;
    M_AXI_DC_WVALID : out STD_LOGIC;
    M_AXI_DC_WREADY : in STD_LOGIC;
    M_AXI_DC_WUSER : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DC_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_BID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DC_BVALID : in STD_LOGIC;
    M_AXI_DC_BREADY : out STD_LOGIC;
    M_AXI_DC_BUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DC_WACK : out STD_LOGIC;
    M_AXI_DC_ARID : out STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DC_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DC_ARLEN : out STD_LOGIC_VECTOR ( 7 downto 0 );
    M_AXI_DC_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DC_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_ARLOCK : out STD_LOGIC;
    M_AXI_DC_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DC_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DC_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DC_ARVALID : out STD_LOGIC;
    M_AXI_DC_ARREADY : in STD_LOGIC;
    M_AXI_DC_ARUSER : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M_AXI_DC_ARDOMAIN : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_ARSNOOP : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DC_ARBAR : out STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_RID : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DC_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DC_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DC_RLAST : in STD_LOGIC;
    M_AXI_DC_RVALID : in STD_LOGIC;
    M_AXI_DC_RREADY : out STD_LOGIC;
    M_AXI_DC_RUSER : in STD_LOGIC_VECTOR ( 0 to 0 );
    M_AXI_DC_RACK : out STD_LOGIC;
    M_AXI_DC_ACVALID : in STD_LOGIC;
    M_AXI_DC_ACADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DC_ACSNOOP : in STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DC_ACPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DC_ACREADY : out STD_LOGIC;
    M_AXI_DC_CRVALID : out STD_LOGIC;
    M_AXI_DC_CRRESP : out STD_LOGIC_VECTOR ( 4 downto 0 );
    M_AXI_DC_CRREADY : in STD_LOGIC;
    M_AXI_DC_CDVALID : out STD_LOGIC;
    M_AXI_DC_CDDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DC_CDLAST : out STD_LOGIC;
    M_AXI_DC_CDREADY : in STD_LOGIC
  );
  attribute C_ADDR_TAG_BITS : integer;
  attribute C_ADDR_TAG_BITS of design_1_microblaze_0_0_MicroBlaze : entity is 17;
  attribute C_ALLOW_DCACHE_WR : integer;
  attribute C_ALLOW_DCACHE_WR of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_ALLOW_ICACHE_WR : integer;
  attribute C_ALLOW_ICACHE_WR of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_AREA_OPTIMIZED : integer;
  attribute C_AREA_OPTIMIZED of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_ASYNC_INTERRUPT : integer;
  attribute C_ASYNC_INTERRUPT of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_ASYNC_WAKEUP : integer;
  attribute C_ASYNC_WAKEUP of design_1_microblaze_0_0_MicroBlaze : entity is 3;
  attribute C_AVOID_PRIMITIVES : integer;
  attribute C_AVOID_PRIMITIVES of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_BASE_VECTORS : string;
  attribute C_BASE_VECTORS of design_1_microblaze_0_0_MicroBlaze : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_BRANCH_TARGET_CACHE_SIZE : integer;
  attribute C_BRANCH_TARGET_CACHE_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_CACHE_BYTE_SIZE : integer;
  attribute C_CACHE_BYTE_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 8192;
  attribute C_DADDR_SIZE : integer;
  attribute C_DADDR_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_DATA_SIZE : integer;
  attribute C_DATA_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_DCACHE_ADDR_TAG : integer;
  attribute C_DCACHE_ADDR_TAG of design_1_microblaze_0_0_MicroBlaze : entity is 17;
  attribute C_DCACHE_ALWAYS_USED : integer;
  attribute C_DCACHE_ALWAYS_USED of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DCACHE_BASEADDR : string;
  attribute C_DCACHE_BASEADDR of design_1_microblaze_0_0_MicroBlaze : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_DCACHE_BYTE_SIZE : integer;
  attribute C_DCACHE_BYTE_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 8192;
  attribute C_DCACHE_DATA_WIDTH : integer;
  attribute C_DCACHE_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DCACHE_FORCE_TAG_LUTRAM : integer;
  attribute C_DCACHE_FORCE_TAG_LUTRAM of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DCACHE_HIGHADDR : string;
  attribute C_DCACHE_HIGHADDR of design_1_microblaze_0_0_MicroBlaze : entity is "64'b0000000000000000000000000000000000111111111111111111111111111111";
  attribute C_DCACHE_LINE_LEN : integer;
  attribute C_DCACHE_LINE_LEN of design_1_microblaze_0_0_MicroBlaze : entity is 4;
  attribute C_DCACHE_USE_WRITEBACK : integer;
  attribute C_DCACHE_USE_WRITEBACK of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DCACHE_VICTIMS : integer;
  attribute C_DCACHE_VICTIMS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DEBUG_COUNTER_WIDTH : integer;
  attribute C_DEBUG_COUNTER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_DEBUG_ENABLED : integer;
  attribute C_DEBUG_ENABLED of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_DEBUG_EVENT_COUNTERS : integer;
  attribute C_DEBUG_EVENT_COUNTERS of design_1_microblaze_0_0_MicroBlaze : entity is 5;
  attribute C_DEBUG_EXTERNAL_TRACE : integer;
  attribute C_DEBUG_EXTERNAL_TRACE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DEBUG_INTERFACE : integer;
  attribute C_DEBUG_INTERFACE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DEBUG_LATENCY_COUNTERS : integer;
  attribute C_DEBUG_LATENCY_COUNTERS of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_DEBUG_PROFILE_SIZE : integer;
  attribute C_DEBUG_PROFILE_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DEBUG_TRACE_ASYNC_RESET : integer;
  attribute C_DEBUG_TRACE_ASYNC_RESET of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DEBUG_TRACE_SIZE : integer;
  attribute C_DEBUG_TRACE_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 8192;
  attribute C_DIV_ZERO_EXCEPTION : integer;
  attribute C_DIV_ZERO_EXCEPTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_DYNAMIC_BUS_SIZING : integer;
  attribute C_DYNAMIC_BUS_SIZING of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_D_AXI : integer;
  attribute C_D_AXI of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_D_LMB : integer;
  attribute C_D_LMB of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_ECC_USE_CE_EXCEPTION : integer;
  attribute C_ECC_USE_CE_EXCEPTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_EDGE_IS_POSITIVE : integer;
  attribute C_EDGE_IS_POSITIVE of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_ENDIANNESS : integer;
  attribute C_ENDIANNESS of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_FAMILY : string;
  attribute C_FAMILY of design_1_microblaze_0_0_MicroBlaze : entity is "kintexuplus";
  attribute C_FAULT_TOLERANT : integer;
  attribute C_FAULT_TOLERANT of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_FPU_EXCEPTION : integer;
  attribute C_FPU_EXCEPTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_FREQ : integer;
  attribute C_FREQ of design_1_microblaze_0_0_MicroBlaze : entity is 100000000;
  attribute C_FSL_EXCEPTION : integer;
  attribute C_FSL_EXCEPTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_FSL_LINKS : integer;
  attribute C_FSL_LINKS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_IADDR_SIZE : integer;
  attribute C_IADDR_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_ICACHE_ALWAYS_USED : integer;
  attribute C_ICACHE_ALWAYS_USED of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_ICACHE_BASEADDR : string;
  attribute C_ICACHE_BASEADDR of design_1_microblaze_0_0_MicroBlaze : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_ICACHE_DATA_WIDTH : integer;
  attribute C_ICACHE_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_ICACHE_FORCE_TAG_LUTRAM : integer;
  attribute C_ICACHE_FORCE_TAG_LUTRAM of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_ICACHE_HIGHADDR : string;
  attribute C_ICACHE_HIGHADDR of design_1_microblaze_0_0_MicroBlaze : entity is "64'b0000000000000000000000000000000000111111111111111111111111111111";
  attribute C_ICACHE_LINE_LEN : integer;
  attribute C_ICACHE_LINE_LEN of design_1_microblaze_0_0_MicroBlaze : entity is 4;
  attribute C_ICACHE_STREAMS : integer;
  attribute C_ICACHE_STREAMS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_ICACHE_VICTIMS : integer;
  attribute C_ICACHE_VICTIMS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_ILL_OPCODE_EXCEPTION : integer;
  attribute C_ILL_OPCODE_EXCEPTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_IMPRECISE_EXCEPTIONS : integer;
  attribute C_IMPRECISE_EXCEPTIONS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_INSTANCE : string;
  attribute C_INSTANCE of design_1_microblaze_0_0_MicroBlaze : entity is "design_1_microblaze_0_0";
  attribute C_INSTR_SIZE : integer;
  attribute C_INSTR_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_INTERCONNECT : integer;
  attribute C_INTERCONNECT of design_1_microblaze_0_0_MicroBlaze : entity is 2;
  attribute C_INTERRUPT_IS_EDGE : integer;
  attribute C_INTERRUPT_IS_EDGE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_I_AXI : integer;
  attribute C_I_AXI of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_I_LMB : integer;
  attribute C_I_LMB of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_LMB_DATA_SIZE : integer;
  attribute C_LMB_DATA_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_LOCKSTEP_MASTER : integer;
  attribute C_LOCKSTEP_MASTER of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_LOCKSTEP_SLAVE : integer;
  attribute C_LOCKSTEP_SLAVE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_M0_AXIS_DATA_WIDTH : integer;
  attribute C_M0_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M10_AXIS_DATA_WIDTH : integer;
  attribute C_M10_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M11_AXIS_DATA_WIDTH : integer;
  attribute C_M11_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M12_AXIS_DATA_WIDTH : integer;
  attribute C_M12_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M13_AXIS_DATA_WIDTH : integer;
  attribute C_M13_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M14_AXIS_DATA_WIDTH : integer;
  attribute C_M14_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M15_AXIS_DATA_WIDTH : integer;
  attribute C_M15_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M1_AXIS_DATA_WIDTH : integer;
  attribute C_M1_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M2_AXIS_DATA_WIDTH : integer;
  attribute C_M2_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M3_AXIS_DATA_WIDTH : integer;
  attribute C_M3_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M4_AXIS_DATA_WIDTH : integer;
  attribute C_M4_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M5_AXIS_DATA_WIDTH : integer;
  attribute C_M5_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M6_AXIS_DATA_WIDTH : integer;
  attribute C_M6_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M7_AXIS_DATA_WIDTH : integer;
  attribute C_M7_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M8_AXIS_DATA_WIDTH : integer;
  attribute C_M8_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M9_AXIS_DATA_WIDTH : integer;
  attribute C_M9_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_MMU_DTLB_SIZE : integer;
  attribute C_MMU_DTLB_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 4;
  attribute C_MMU_ITLB_SIZE : integer;
  attribute C_MMU_ITLB_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 2;
  attribute C_MMU_PRIVILEGED_INSTR : integer;
  attribute C_MMU_PRIVILEGED_INSTR of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_MMU_TLB_ACCESS : integer;
  attribute C_MMU_TLB_ACCESS of design_1_microblaze_0_0_MicroBlaze : entity is 3;
  attribute C_MMU_ZONES : integer;
  attribute C_MMU_ZONES of design_1_microblaze_0_0_MicroBlaze : entity is 16;
  attribute C_M_AXI_DC_ADDR_WIDTH : integer;
  attribute C_M_AXI_DC_ADDR_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_DC_ARUSER_WIDTH : integer;
  attribute C_M_AXI_DC_ARUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 5;
  attribute C_M_AXI_DC_AWUSER_WIDTH : integer;
  attribute C_M_AXI_DC_AWUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 5;
  attribute C_M_AXI_DC_BUSER_WIDTH : integer;
  attribute C_M_AXI_DC_BUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_DC_DATA_WIDTH : integer;
  attribute C_M_AXI_DC_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
  attribute C_M_AXI_DC_EXCLUSIVE_ACCESS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_M_AXI_DC_RUSER_WIDTH : integer;
  attribute C_M_AXI_DC_RUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_DC_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_DC_THREAD_ID_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_DC_USER_VALUE : integer;
  attribute C_M_AXI_DC_USER_VALUE of design_1_microblaze_0_0_MicroBlaze : entity is 31;
  attribute C_M_AXI_DC_WUSER_WIDTH : integer;
  attribute C_M_AXI_DC_WUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_DP_ADDR_WIDTH : integer;
  attribute C_M_AXI_DP_ADDR_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_DP_DATA_WIDTH : integer;
  attribute C_M_AXI_DP_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
  attribute C_M_AXI_DP_EXCLUSIVE_ACCESS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_M_AXI_DP_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_DP_THREAD_ID_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_D_BUS_EXCEPTION : integer;
  attribute C_M_AXI_D_BUS_EXCEPTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_M_AXI_IC_ADDR_WIDTH : integer;
  attribute C_M_AXI_IC_ADDR_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_IC_ARUSER_WIDTH : integer;
  attribute C_M_AXI_IC_ARUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 5;
  attribute C_M_AXI_IC_AWUSER_WIDTH : integer;
  attribute C_M_AXI_IC_AWUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 5;
  attribute C_M_AXI_IC_BUSER_WIDTH : integer;
  attribute C_M_AXI_IC_BUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_IC_DATA_WIDTH : integer;
  attribute C_M_AXI_IC_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_IC_RUSER_WIDTH : integer;
  attribute C_M_AXI_IC_RUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_IC_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_IC_THREAD_ID_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_IC_USER_VALUE : integer;
  attribute C_M_AXI_IC_USER_VALUE of design_1_microblaze_0_0_MicroBlaze : entity is 31;
  attribute C_M_AXI_IC_WUSER_WIDTH : integer;
  attribute C_M_AXI_IC_WUSER_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_IP_ADDR_WIDTH : integer;
  attribute C_M_AXI_IP_ADDR_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_IP_DATA_WIDTH : integer;
  attribute C_M_AXI_IP_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_M_AXI_IP_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_IP_THREAD_ID_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_M_AXI_I_BUS_EXCEPTION : integer;
  attribute C_M_AXI_I_BUS_EXCEPTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_NUMBER_OF_PC_BRK : integer;
  attribute C_NUMBER_OF_PC_BRK of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_NUMBER_OF_RD_ADDR_BRK : integer;
  attribute C_NUMBER_OF_RD_ADDR_BRK of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_NUMBER_OF_WR_ADDR_BRK : integer;
  attribute C_NUMBER_OF_WR_ADDR_BRK of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_NUM_SYNC_FF_CLK : integer;
  attribute C_NUM_SYNC_FF_CLK of design_1_microblaze_0_0_MicroBlaze : entity is 2;
  attribute C_NUM_SYNC_FF_CLK_DEBUG : integer;
  attribute C_NUM_SYNC_FF_CLK_DEBUG of design_1_microblaze_0_0_MicroBlaze : entity is 2;
  attribute C_NUM_SYNC_FF_CLK_IRQ : integer;
  attribute C_NUM_SYNC_FF_CLK_IRQ of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_NUM_SYNC_FF_DBG_CLK : integer;
  attribute C_NUM_SYNC_FF_DBG_CLK of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_NUM_SYNC_FF_DBG_TRACE_CLK : integer;
  attribute C_NUM_SYNC_FF_DBG_TRACE_CLK of design_1_microblaze_0_0_MicroBlaze : entity is 2;
  attribute C_OPCODE_0x0_ILLEGAL : integer;
  attribute C_OPCODE_0x0_ILLEGAL of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_OPTIMIZATION : integer;
  attribute C_OPTIMIZATION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_PC_WIDTH : integer;
  attribute C_PC_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_PIADDR_SIZE : integer;
  attribute C_PIADDR_SIZE of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_PVR : integer;
  attribute C_PVR of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_PVR_USER1 : string;
  attribute C_PVR_USER1 of design_1_microblaze_0_0_MicroBlaze : entity is "8'b00000000";
  attribute C_PVR_USER2 : integer;
  attribute C_PVR_USER2 of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_RESET_MSR : integer;
  attribute C_RESET_MSR of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_S0_AXIS_DATA_WIDTH : integer;
  attribute C_S0_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S10_AXIS_DATA_WIDTH : integer;
  attribute C_S10_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S11_AXIS_DATA_WIDTH : integer;
  attribute C_S11_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S12_AXIS_DATA_WIDTH : integer;
  attribute C_S12_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S13_AXIS_DATA_WIDTH : integer;
  attribute C_S13_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S14_AXIS_DATA_WIDTH : integer;
  attribute C_S14_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S15_AXIS_DATA_WIDTH : integer;
  attribute C_S15_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S1_AXIS_DATA_WIDTH : integer;
  attribute C_S1_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S2_AXIS_DATA_WIDTH : integer;
  attribute C_S2_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S3_AXIS_DATA_WIDTH : integer;
  attribute C_S3_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S4_AXIS_DATA_WIDTH : integer;
  attribute C_S4_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S5_AXIS_DATA_WIDTH : integer;
  attribute C_S5_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S6_AXIS_DATA_WIDTH : integer;
  attribute C_S6_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S7_AXIS_DATA_WIDTH : integer;
  attribute C_S7_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S8_AXIS_DATA_WIDTH : integer;
  attribute C_S8_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_S9_AXIS_DATA_WIDTH : integer;
  attribute C_S9_AXIS_DATA_WIDTH of design_1_microblaze_0_0_MicroBlaze : entity is 32;
  attribute C_SCO : integer;
  attribute C_SCO of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_UNALIGNED_EXCEPTIONS : integer;
  attribute C_UNALIGNED_EXCEPTIONS of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_BARREL : integer;
  attribute C_USE_BARREL of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_BRANCH_TARGET_CACHE : integer;
  attribute C_USE_BRANCH_TARGET_CACHE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_CONFIG_RESET : integer;
  attribute C_USE_CONFIG_RESET of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_DCACHE : integer;
  attribute C_USE_DCACHE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_DIV : integer;
  attribute C_USE_DIV of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_EXTENDED_FSL_INSTR : integer;
  attribute C_USE_EXTENDED_FSL_INSTR of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_EXT_BRK : integer;
  attribute C_USE_EXT_BRK of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_EXT_NM_BRK : integer;
  attribute C_USE_EXT_NM_BRK of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_FPU : integer;
  attribute C_USE_FPU of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_HW_MUL : integer;
  attribute C_USE_HW_MUL of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_ICACHE : integer;
  attribute C_USE_ICACHE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_INTERRUPT : integer;
  attribute C_USE_INTERRUPT of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_MMU : integer;
  attribute C_USE_MMU of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_MSR_INSTR : integer;
  attribute C_USE_MSR_INSTR of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_NON_SECURE : integer;
  attribute C_USE_NON_SECURE of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_PCMP_INSTR : integer;
  attribute C_USE_PCMP_INSTR of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute C_USE_REORDER_INSTR : integer;
  attribute C_USE_REORDER_INSTR of design_1_microblaze_0_0_MicroBlaze : entity is 1;
  attribute C_USE_STACK_PROTECTION : integer;
  attribute C_USE_STACK_PROTECTION of design_1_microblaze_0_0_MicroBlaze : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of design_1_microblaze_0_0_MicroBlaze : entity is "MicroBlaze";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_microblaze_0_0_MicroBlaze : entity is "yes";
end design_1_microblaze_0_0_MicroBlaze;

architecture STRUCTURE of design_1_microblaze_0_0_MicroBlaze is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^byte_enable\ : STD_LOGIC_VECTOR ( 0 to 3 );
  signal Config_Reg_En : STD_LOGIC;
  signal \^d_as\ : STD_LOGIC;
  signal \^data_addr\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal Data_Read_Reg_En : STD_LOGIC;
  signal \^data_write\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^dbg_continue\ : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_11_n_0 : STD_LOGIC;
  signal Dbg_TDO_INST_0_i_26_n_0 : STD_LOGIC;
  signal \^dbg_trig_ack_out\ : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \^dbg_trig_in\ : STD_LOGIC_VECTOR ( 0 to 1 );
  signal \^debug_rst\ : STD_LOGIC;
  signal \^ifetch\ : STD_LOGIC;
  signal \^i_as\ : STD_LOGIC;
  signal \^instr_addr\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^lockstep_master_out\ : STD_LOGIC_VECTOR ( 1 to 46 );
  signal \^lockstep_out\ : STD_LOGIC_VECTOR ( 2 to 3228 );
  signal \^m_axi_dp_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^m_axi_dp_arvalid\ : STD_LOGIC;
  signal \^m_axi_dp_awvalid\ : STD_LOGIC;
  signal \^m_axi_dp_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^m_axi_dp_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^m_axi_dp_wvalid\ : STD_LOGIC;
  signal MicroBlaze_Core_I_n_411 : STD_LOGIC;
  signal \Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Status_Reg_En\ : STD_LOGIC;
  signal \^read_strobe\ : STD_LOGIC;
  signal \^trace_data_access\ : STD_LOGIC;
  signal \^trace_data_address\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^trace_data_byte_enable\ : STD_LOGIC_VECTOR ( 0 to 3 );
  signal \^trace_data_read\ : STD_LOGIC;
  signal \^trace_data_write\ : STD_LOGIC;
  signal \^trace_data_write_value\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^trace_delay_slot\ : STD_LOGIC;
  signal \^trace_ex_piperun\ : STD_LOGIC;
  signal \^trace_exception_kind\ : STD_LOGIC_VECTOR ( 1 to 4 );
  signal \^trace_exception_taken\ : STD_LOGIC;
  signal \^trace_instruction\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^trace_jump_taken\ : STD_LOGIC;
  signal \^trace_mem_piperun\ : STD_LOGIC;
  signal \^trace_msr_reg\ : STD_LOGIC_VECTOR ( 11 to 13 );
  signal \^trace_new_reg_value\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^trace_of_piperun\ : STD_LOGIC;
  signal \^trace_pc\ : STD_LOGIC_VECTOR ( 0 to 31 );
  signal \^trace_reg_addr\ : STD_LOGIC_VECTOR ( 0 to 4 );
  signal \^trace_reg_write\ : STD_LOGIC;
  signal \^trace_valid_instr\ : STD_LOGIC;
  signal \^write_strobe\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of Dbg_TDO_INST_0_i_11 : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of Dbg_TDO_INST_0_i_26 : label is "soft_lutpair87";
  attribute mark_debug : string;
  attribute mark_debug of Trace_DCache_Hit : signal is "false";
  attribute mark_debug of Trace_DCache_Rdy : signal is "false";
  attribute mark_debug of Trace_DCache_Read : signal is "false";
  attribute mark_debug of Trace_DCache_Req : signal is "false";
  attribute mark_debug of Trace_Data_Access : signal is "false";
  attribute mark_debug of Trace_Data_Read : signal is "false";
  attribute mark_debug of Trace_Data_Write : signal is "false";
  attribute mark_debug of Trace_Delay_Slot : signal is "false";
  attribute mark_debug of Trace_EX_PipeRun : signal is "false";
  attribute mark_debug of Trace_Exception_Taken : signal is "false";
  attribute mark_debug of Trace_ICache_Hit : signal is "false";
  attribute mark_debug of Trace_ICache_Rdy : signal is "false";
  attribute mark_debug of Trace_ICache_Req : signal is "false";
  attribute mark_debug of Trace_Jump_Hit : signal is "false";
  attribute mark_debug of Trace_Jump_Taken : signal is "false";
  attribute mark_debug of Trace_MB_Halted : signal is "false";
  attribute mark_debug of Trace_MEM_PipeRun : signal is "false";
  attribute mark_debug of Trace_OF_PipeRun : signal is "false";
  attribute mark_debug of Trace_Reg_Write : signal is "false";
  attribute mark_debug of Trace_Valid_Instr : signal is "false";
  attribute mark_debug of Trace_Data_Address : signal is "false";
  attribute mark_debug of Trace_Data_Byte_Enable : signal is "false";
  attribute mark_debug of Trace_Data_Write_Value : signal is "false";
  attribute mark_debug of Trace_Exception_Kind : signal is "false";
  attribute mark_debug of Trace_Instruction : signal is "false";
  attribute mark_debug of Trace_MSR_Reg : signal is "false";
  attribute mark_debug of Trace_New_Reg_Value : signal is "false";
  attribute mark_debug of Trace_PC : signal is "false";
  attribute mark_debug of Trace_PID_Reg : signal is "false";
  attribute mark_debug of Trace_Reg_Addr : signal is "false";
begin
  Byte_Enable(0 to 3) <= \^byte_enable\(0 to 3);
  D_AS <= \^d_as\;
  Data_Addr(0 to 31) <= \^data_addr\(0 to 31);
  Data_Write(0 to 31) <= \^data_write\(0 to 31);
  Dbg_ARREADY <= \<const0>\;
  Dbg_AWREADY <= \<const0>\;
  Dbg_BRESP(1) <= \<const0>\;
  Dbg_BRESP(0) <= \<const0>\;
  Dbg_BVALID <= \<const0>\;
  Dbg_Continue <= \^dbg_continue\;
  Dbg_Intr <= \<const0>\;
  Dbg_RDATA(31) <= \<const0>\;
  Dbg_RDATA(30) <= \<const0>\;
  Dbg_RDATA(29) <= \<const0>\;
  Dbg_RDATA(28) <= \<const0>\;
  Dbg_RDATA(27) <= \<const0>\;
  Dbg_RDATA(26) <= \<const0>\;
  Dbg_RDATA(25) <= \<const0>\;
  Dbg_RDATA(24) <= \<const0>\;
  Dbg_RDATA(23) <= \<const0>\;
  Dbg_RDATA(22) <= \<const0>\;
  Dbg_RDATA(21) <= \<const0>\;
  Dbg_RDATA(20) <= \<const0>\;
  Dbg_RDATA(19) <= \<const0>\;
  Dbg_RDATA(18) <= \<const0>\;
  Dbg_RDATA(17) <= \<const0>\;
  Dbg_RDATA(16) <= \<const0>\;
  Dbg_RDATA(15) <= \<const0>\;
  Dbg_RDATA(14) <= \<const0>\;
  Dbg_RDATA(13) <= \<const0>\;
  Dbg_RDATA(12) <= \<const0>\;
  Dbg_RDATA(11) <= \<const0>\;
  Dbg_RDATA(10) <= \<const0>\;
  Dbg_RDATA(9) <= \<const0>\;
  Dbg_RDATA(8) <= \<const0>\;
  Dbg_RDATA(7) <= \<const0>\;
  Dbg_RDATA(6) <= \<const0>\;
  Dbg_RDATA(5) <= \<const0>\;
  Dbg_RDATA(4) <= \<const0>\;
  Dbg_RDATA(3) <= \<const0>\;
  Dbg_RDATA(2) <= \<const0>\;
  Dbg_RDATA(1) <= \<const0>\;
  Dbg_RDATA(0) <= \<const0>\;
  Dbg_RRESP(1) <= \<const0>\;
  Dbg_RRESP(0) <= \<const0>\;
  Dbg_RVALID <= \<const0>\;
  Dbg_Trace_Data(0) <= \<const0>\;
  Dbg_Trace_Data(1) <= \<const0>\;
  Dbg_Trace_Data(2) <= \<const0>\;
  Dbg_Trace_Data(3) <= \<const0>\;
  Dbg_Trace_Data(4) <= \<const0>\;
  Dbg_Trace_Data(5) <= \<const0>\;
  Dbg_Trace_Data(6) <= \<const0>\;
  Dbg_Trace_Data(7) <= \<const0>\;
  Dbg_Trace_Data(8) <= \<const0>\;
  Dbg_Trace_Data(9) <= \<const0>\;
  Dbg_Trace_Data(10) <= \<const0>\;
  Dbg_Trace_Data(11) <= \<const0>\;
  Dbg_Trace_Data(12) <= \<const0>\;
  Dbg_Trace_Data(13) <= \<const0>\;
  Dbg_Trace_Data(14) <= \<const0>\;
  Dbg_Trace_Data(15) <= \<const0>\;
  Dbg_Trace_Data(16) <= \<const0>\;
  Dbg_Trace_Data(17) <= \<const0>\;
  Dbg_Trace_Data(18) <= \<const0>\;
  Dbg_Trace_Data(19) <= \<const0>\;
  Dbg_Trace_Data(20) <= \<const0>\;
  Dbg_Trace_Data(21) <= \<const0>\;
  Dbg_Trace_Data(22) <= \<const0>\;
  Dbg_Trace_Data(23) <= \<const0>\;
  Dbg_Trace_Data(24) <= \<const0>\;
  Dbg_Trace_Data(25) <= \<const0>\;
  Dbg_Trace_Data(26) <= \<const0>\;
  Dbg_Trace_Data(27) <= \<const0>\;
  Dbg_Trace_Data(28) <= \<const0>\;
  Dbg_Trace_Data(29) <= \<const0>\;
  Dbg_Trace_Data(30) <= \<const0>\;
  Dbg_Trace_Data(31) <= \<const0>\;
  Dbg_Trace_Data(32) <= \<const0>\;
  Dbg_Trace_Data(33) <= \<const0>\;
  Dbg_Trace_Data(34) <= \<const0>\;
  Dbg_Trace_Data(35) <= \<const0>\;
  Dbg_Trace_Valid <= \<const0>\;
  Dbg_Trig_Ack_Out(0 to 1) <= \^dbg_trig_ack_out\(0 to 1);
  Dbg_Trig_Ack_Out(2) <= \<const0>\;
  Dbg_Trig_Ack_Out(3) <= \<const0>\;
  Dbg_Trig_Ack_Out(4) <= \<const0>\;
  Dbg_Trig_Ack_Out(5) <= \<const0>\;
  Dbg_Trig_Ack_Out(6) <= \<const0>\;
  Dbg_Trig_Ack_Out(7) <= \<const0>\;
  Dbg_Trig_In(0 to 1) <= \^dbg_trig_in\(0 to 1);
  Dbg_Trig_In(2) <= \<const0>\;
  Dbg_Trig_In(3) <= \<const0>\;
  Dbg_Trig_In(4) <= \<const0>\;
  Dbg_Trig_In(5) <= \<const0>\;
  Dbg_Trig_In(6) <= \<const0>\;
  Dbg_Trig_In(7) <= \<const0>\;
  Dbg_WREADY <= \<const0>\;
  Dbg_Wakeup <= \^lockstep_master_out\(11);
  IFetch <= \^ifetch\;
  I_AS <= \^i_as\;
  Instr_Addr(0 to 31) <= \^instr_addr\(0 to 31);
  Interrupt_Ack(0) <= \<const0>\;
  Interrupt_Ack(1) <= \<const0>\;
  LOCKSTEP_Master_Out(0) <= \<const0>\;
  LOCKSTEP_Master_Out(1) <= \^lockstep_master_out\(1);
  LOCKSTEP_Master_Out(2) <= \<const0>\;
  LOCKSTEP_Master_Out(3 to 7) <= \^lockstep_master_out\(3 to 7);
  LOCKSTEP_Master_Out(8) <= \^lockstep_master_out\(10);
  LOCKSTEP_Master_Out(9) <= \<const0>\;
  LOCKSTEP_Master_Out(10 to 11) <= \^lockstep_master_out\(10 to 11);
  LOCKSTEP_Master_Out(12) <= \^dbg_continue\;
  LOCKSTEP_Master_Out(13) <= \^lockstep_master_out\(13);
  LOCKSTEP_Master_Out(14) <= \^debug_rst\;
  LOCKSTEP_Master_Out(15 to 46) <= \^lockstep_master_out\(15 to 46);
  LOCKSTEP_Master_Out(47) <= \<const0>\;
  LOCKSTEP_Master_Out(48) <= \<const0>\;
  LOCKSTEP_Master_Out(49) <= \<const0>\;
  LOCKSTEP_Master_Out(50) <= \<const0>\;
  LOCKSTEP_Master_Out(51) <= \<const0>\;
  LOCKSTEP_Master_Out(52) <= \<const0>\;
  LOCKSTEP_Master_Out(53) <= \<const0>\;
  LOCKSTEP_Master_Out(54) <= \<const0>\;
  LOCKSTEP_Master_Out(55) <= \<const0>\;
  LOCKSTEP_Master_Out(56) <= \<const0>\;
  LOCKSTEP_Master_Out(57) <= \<const0>\;
  LOCKSTEP_Master_Out(58) <= \<const0>\;
  LOCKSTEP_Master_Out(59) <= \<const0>\;
  LOCKSTEP_Master_Out(60) <= \<const0>\;
  LOCKSTEP_Master_Out(61) <= \<const0>\;
  LOCKSTEP_Master_Out(62) <= \<const0>\;
  LOCKSTEP_Master_Out(63) <= \<const0>\;
  LOCKSTEP_Master_Out(64) <= \<const0>\;
  LOCKSTEP_Master_Out(65) <= \<const0>\;
  LOCKSTEP_Master_Out(66) <= \<const0>\;
  LOCKSTEP_Master_Out(67) <= \<const0>\;
  LOCKSTEP_Master_Out(68) <= \<const0>\;
  LOCKSTEP_Master_Out(69) <= \<const0>\;
  LOCKSTEP_Master_Out(70) <= \<const0>\;
  LOCKSTEP_Master_Out(71) <= \<const0>\;
  LOCKSTEP_Master_Out(72) <= \<const0>\;
  LOCKSTEP_Master_Out(73) <= \<const0>\;
  LOCKSTEP_Master_Out(74) <= \<const0>\;
  LOCKSTEP_Master_Out(75) <= \<const0>\;
  LOCKSTEP_Master_Out(76) <= \<const0>\;
  LOCKSTEP_Master_Out(77) <= \<const0>\;
  LOCKSTEP_Master_Out(78) <= \<const0>\;
  LOCKSTEP_Master_Out(79) <= \<const0>\;
  LOCKSTEP_Master_Out(80) <= \<const0>\;
  LOCKSTEP_Master_Out(81) <= \<const0>\;
  LOCKSTEP_Master_Out(82) <= \<const0>\;
  LOCKSTEP_Master_Out(83) <= \<const0>\;
  LOCKSTEP_Master_Out(84) <= \<const0>\;
  LOCKSTEP_Master_Out(85) <= \<const0>\;
  LOCKSTEP_Master_Out(86) <= \<const0>\;
  LOCKSTEP_Master_Out(87) <= \<const0>\;
  LOCKSTEP_Master_Out(88) <= \<const0>\;
  LOCKSTEP_Master_Out(89) <= \<const0>\;
  LOCKSTEP_Master_Out(90) <= \<const0>\;
  LOCKSTEP_Master_Out(91) <= \<const0>\;
  LOCKSTEP_Master_Out(92) <= \<const0>\;
  LOCKSTEP_Master_Out(93) <= \<const0>\;
  LOCKSTEP_Master_Out(94) <= \<const0>\;
  LOCKSTEP_Master_Out(95) <= \<const0>\;
  LOCKSTEP_Master_Out(96) <= \<const0>\;
  LOCKSTEP_Master_Out(97) <= \<const0>\;
  LOCKSTEP_Master_Out(98) <= \<const0>\;
  LOCKSTEP_Master_Out(99) <= \<const0>\;
  LOCKSTEP_Master_Out(100) <= \<const0>\;
  LOCKSTEP_Master_Out(101) <= \<const0>\;
  LOCKSTEP_Master_Out(102) <= \<const0>\;
  LOCKSTEP_Master_Out(103) <= \<const0>\;
  LOCKSTEP_Master_Out(104) <= \<const0>\;
  LOCKSTEP_Master_Out(105) <= \<const0>\;
  LOCKSTEP_Master_Out(106) <= \<const0>\;
  LOCKSTEP_Master_Out(107) <= \<const0>\;
  LOCKSTEP_Master_Out(108) <= \<const0>\;
  LOCKSTEP_Master_Out(109) <= \<const0>\;
  LOCKSTEP_Master_Out(110) <= \<const0>\;
  LOCKSTEP_Master_Out(111) <= \<const0>\;
  LOCKSTEP_Master_Out(112) <= \<const0>\;
  LOCKSTEP_Master_Out(113) <= \<const0>\;
  LOCKSTEP_Master_Out(114) <= \<const0>\;
  LOCKSTEP_Master_Out(115) <= \<const0>\;
  LOCKSTEP_Master_Out(116) <= \<const0>\;
  LOCKSTEP_Master_Out(117) <= \<const0>\;
  LOCKSTEP_Master_Out(118) <= \<const0>\;
  LOCKSTEP_Master_Out(119) <= \<const0>\;
  LOCKSTEP_Master_Out(120) <= \<const0>\;
  LOCKSTEP_Master_Out(121) <= \<const0>\;
  LOCKSTEP_Master_Out(122) <= \<const0>\;
  LOCKSTEP_Master_Out(123) <= \<const0>\;
  LOCKSTEP_Master_Out(124) <= \<const0>\;
  LOCKSTEP_Master_Out(125) <= \<const0>\;
  LOCKSTEP_Master_Out(126) <= \<const0>\;
  LOCKSTEP_Master_Out(127) <= \<const0>\;
  LOCKSTEP_Master_Out(128) <= \<const0>\;
  LOCKSTEP_Master_Out(129) <= \<const0>\;
  LOCKSTEP_Master_Out(130) <= \<const0>\;
  LOCKSTEP_Master_Out(131) <= \<const0>\;
  LOCKSTEP_Master_Out(132) <= \<const0>\;
  LOCKSTEP_Master_Out(133) <= \<const0>\;
  LOCKSTEP_Master_Out(134) <= \<const0>\;
  LOCKSTEP_Master_Out(135) <= \<const0>\;
  LOCKSTEP_Master_Out(136) <= \<const0>\;
  LOCKSTEP_Master_Out(137) <= \<const0>\;
  LOCKSTEP_Master_Out(138) <= \<const0>\;
  LOCKSTEP_Master_Out(139) <= \<const0>\;
  LOCKSTEP_Master_Out(140) <= \<const0>\;
  LOCKSTEP_Master_Out(141) <= \<const0>\;
  LOCKSTEP_Master_Out(142) <= \<const0>\;
  LOCKSTEP_Master_Out(143) <= \<const0>\;
  LOCKSTEP_Master_Out(144) <= \<const0>\;
  LOCKSTEP_Master_Out(145) <= \<const0>\;
  LOCKSTEP_Master_Out(146) <= \<const0>\;
  LOCKSTEP_Master_Out(147) <= \<const0>\;
  LOCKSTEP_Master_Out(148) <= \<const0>\;
  LOCKSTEP_Master_Out(149) <= \<const0>\;
  LOCKSTEP_Master_Out(150) <= \<const0>\;
  LOCKSTEP_Master_Out(151) <= \<const0>\;
  LOCKSTEP_Master_Out(152) <= \<const0>\;
  LOCKSTEP_Master_Out(153) <= \<const0>\;
  LOCKSTEP_Master_Out(154) <= \<const0>\;
  LOCKSTEP_Master_Out(155) <= \<const0>\;
  LOCKSTEP_Master_Out(156) <= \<const0>\;
  LOCKSTEP_Master_Out(157) <= \<const0>\;
  LOCKSTEP_Master_Out(158) <= \<const0>\;
  LOCKSTEP_Master_Out(159) <= \<const0>\;
  LOCKSTEP_Master_Out(160) <= \<const0>\;
  LOCKSTEP_Master_Out(161) <= \<const0>\;
  LOCKSTEP_Master_Out(162) <= \<const0>\;
  LOCKSTEP_Master_Out(163) <= \<const0>\;
  LOCKSTEP_Master_Out(164) <= \<const0>\;
  LOCKSTEP_Master_Out(165) <= \<const0>\;
  LOCKSTEP_Master_Out(166) <= \<const0>\;
  LOCKSTEP_Master_Out(167) <= \<const0>\;
  LOCKSTEP_Master_Out(168) <= \<const0>\;
  LOCKSTEP_Master_Out(169) <= \<const0>\;
  LOCKSTEP_Master_Out(170) <= \<const0>\;
  LOCKSTEP_Master_Out(171) <= \<const0>\;
  LOCKSTEP_Master_Out(172) <= \<const0>\;
  LOCKSTEP_Master_Out(173) <= \<const0>\;
  LOCKSTEP_Master_Out(174) <= \<const0>\;
  LOCKSTEP_Master_Out(175) <= \<const0>\;
  LOCKSTEP_Master_Out(176) <= \<const0>\;
  LOCKSTEP_Master_Out(177) <= \<const0>\;
  LOCKSTEP_Master_Out(178) <= \<const0>\;
  LOCKSTEP_Master_Out(179) <= \<const0>\;
  LOCKSTEP_Master_Out(180) <= \<const0>\;
  LOCKSTEP_Master_Out(181) <= \<const0>\;
  LOCKSTEP_Master_Out(182) <= \<const0>\;
  LOCKSTEP_Master_Out(183) <= \<const0>\;
  LOCKSTEP_Master_Out(184) <= \<const0>\;
  LOCKSTEP_Master_Out(185) <= \<const0>\;
  LOCKSTEP_Master_Out(186) <= \<const0>\;
  LOCKSTEP_Master_Out(187) <= \<const0>\;
  LOCKSTEP_Master_Out(188) <= \<const0>\;
  LOCKSTEP_Master_Out(189) <= \<const0>\;
  LOCKSTEP_Master_Out(190) <= \<const0>\;
  LOCKSTEP_Master_Out(191) <= \<const0>\;
  LOCKSTEP_Master_Out(192) <= \<const0>\;
  LOCKSTEP_Master_Out(193) <= \<const0>\;
  LOCKSTEP_Master_Out(194) <= \<const0>\;
  LOCKSTEP_Master_Out(195) <= \<const0>\;
  LOCKSTEP_Master_Out(196) <= \<const0>\;
  LOCKSTEP_Master_Out(197) <= \<const0>\;
  LOCKSTEP_Master_Out(198) <= \<const0>\;
  LOCKSTEP_Master_Out(199) <= \<const0>\;
  LOCKSTEP_Master_Out(200) <= \<const0>\;
  LOCKSTEP_Master_Out(201) <= \<const0>\;
  LOCKSTEP_Master_Out(202) <= \<const0>\;
  LOCKSTEP_Master_Out(203) <= \<const0>\;
  LOCKSTEP_Master_Out(204) <= \<const0>\;
  LOCKSTEP_Master_Out(205) <= \<const0>\;
  LOCKSTEP_Master_Out(206) <= \<const0>\;
  LOCKSTEP_Master_Out(207) <= \<const0>\;
  LOCKSTEP_Master_Out(208) <= \<const0>\;
  LOCKSTEP_Master_Out(209) <= \<const0>\;
  LOCKSTEP_Master_Out(210) <= \<const0>\;
  LOCKSTEP_Master_Out(211) <= \<const0>\;
  LOCKSTEP_Master_Out(212) <= \<const0>\;
  LOCKSTEP_Master_Out(213) <= \<const0>\;
  LOCKSTEP_Master_Out(214) <= \<const0>\;
  LOCKSTEP_Master_Out(215) <= \<const0>\;
  LOCKSTEP_Master_Out(216) <= \<const0>\;
  LOCKSTEP_Master_Out(217) <= \<const0>\;
  LOCKSTEP_Master_Out(218) <= \<const0>\;
  LOCKSTEP_Master_Out(219) <= \<const0>\;
  LOCKSTEP_Master_Out(220) <= \<const0>\;
  LOCKSTEP_Master_Out(221) <= \<const0>\;
  LOCKSTEP_Master_Out(222) <= \<const0>\;
  LOCKSTEP_Master_Out(223) <= \<const0>\;
  LOCKSTEP_Master_Out(224) <= \<const0>\;
  LOCKSTEP_Master_Out(225) <= \<const0>\;
  LOCKSTEP_Master_Out(226) <= \<const0>\;
  LOCKSTEP_Master_Out(227) <= \<const0>\;
  LOCKSTEP_Master_Out(228) <= \<const0>\;
  LOCKSTEP_Master_Out(229) <= \<const0>\;
  LOCKSTEP_Master_Out(230) <= \<const0>\;
  LOCKSTEP_Master_Out(231) <= \<const0>\;
  LOCKSTEP_Master_Out(232) <= \<const0>\;
  LOCKSTEP_Master_Out(233) <= \<const0>\;
  LOCKSTEP_Master_Out(234) <= \<const0>\;
  LOCKSTEP_Master_Out(235) <= \<const0>\;
  LOCKSTEP_Master_Out(236) <= \<const0>\;
  LOCKSTEP_Master_Out(237) <= \<const0>\;
  LOCKSTEP_Master_Out(238) <= \<const0>\;
  LOCKSTEP_Master_Out(239) <= \<const0>\;
  LOCKSTEP_Master_Out(240) <= \<const0>\;
  LOCKSTEP_Master_Out(241) <= \<const0>\;
  LOCKSTEP_Master_Out(242) <= \<const0>\;
  LOCKSTEP_Master_Out(243) <= \<const0>\;
  LOCKSTEP_Master_Out(244) <= \<const0>\;
  LOCKSTEP_Master_Out(245) <= \<const0>\;
  LOCKSTEP_Master_Out(246) <= \<const0>\;
  LOCKSTEP_Master_Out(247) <= \<const0>\;
  LOCKSTEP_Master_Out(248) <= \<const0>\;
  LOCKSTEP_Master_Out(249) <= \<const0>\;
  LOCKSTEP_Master_Out(250) <= \<const0>\;
  LOCKSTEP_Master_Out(251) <= \<const0>\;
  LOCKSTEP_Master_Out(252) <= \<const0>\;
  LOCKSTEP_Master_Out(253) <= \<const0>\;
  LOCKSTEP_Master_Out(254) <= \<const0>\;
  LOCKSTEP_Master_Out(255) <= \<const0>\;
  LOCKSTEP_Master_Out(256) <= \<const0>\;
  LOCKSTEP_Master_Out(257) <= \<const0>\;
  LOCKSTEP_Master_Out(258) <= \<const0>\;
  LOCKSTEP_Master_Out(259) <= \<const0>\;
  LOCKSTEP_Master_Out(260) <= \<const0>\;
  LOCKSTEP_Master_Out(261) <= \<const0>\;
  LOCKSTEP_Master_Out(262) <= \<const0>\;
  LOCKSTEP_Master_Out(263) <= \<const0>\;
  LOCKSTEP_Master_Out(264) <= \<const0>\;
  LOCKSTEP_Master_Out(265) <= \<const0>\;
  LOCKSTEP_Master_Out(266) <= \<const0>\;
  LOCKSTEP_Master_Out(267) <= \<const0>\;
  LOCKSTEP_Master_Out(268) <= \<const0>\;
  LOCKSTEP_Master_Out(269) <= \<const0>\;
  LOCKSTEP_Master_Out(270) <= \<const0>\;
  LOCKSTEP_Master_Out(271) <= \<const0>\;
  LOCKSTEP_Master_Out(272) <= \<const0>\;
  LOCKSTEP_Master_Out(273) <= \<const0>\;
  LOCKSTEP_Master_Out(274) <= \<const0>\;
  LOCKSTEP_Master_Out(275) <= \<const0>\;
  LOCKSTEP_Master_Out(276) <= \<const0>\;
  LOCKSTEP_Master_Out(277) <= \<const0>\;
  LOCKSTEP_Master_Out(278) <= \<const0>\;
  LOCKSTEP_Master_Out(279) <= \<const0>\;
  LOCKSTEP_Master_Out(280) <= \<const0>\;
  LOCKSTEP_Master_Out(281) <= \<const0>\;
  LOCKSTEP_Master_Out(282) <= \<const0>\;
  LOCKSTEP_Master_Out(283) <= \<const0>\;
  LOCKSTEP_Master_Out(284) <= \<const0>\;
  LOCKSTEP_Master_Out(285) <= \<const0>\;
  LOCKSTEP_Master_Out(286) <= \<const0>\;
  LOCKSTEP_Master_Out(287) <= \<const0>\;
  LOCKSTEP_Master_Out(288) <= \<const0>\;
  LOCKSTEP_Master_Out(289) <= \<const0>\;
  LOCKSTEP_Master_Out(290) <= \<const0>\;
  LOCKSTEP_Master_Out(291) <= \<const0>\;
  LOCKSTEP_Master_Out(292) <= \<const0>\;
  LOCKSTEP_Master_Out(293) <= \<const0>\;
  LOCKSTEP_Master_Out(294) <= \<const0>\;
  LOCKSTEP_Master_Out(295) <= \<const0>\;
  LOCKSTEP_Master_Out(296) <= \<const0>\;
  LOCKSTEP_Master_Out(297) <= \<const0>\;
  LOCKSTEP_Master_Out(298) <= \<const0>\;
  LOCKSTEP_Master_Out(299) <= \<const0>\;
  LOCKSTEP_Master_Out(300) <= \<const0>\;
  LOCKSTEP_Master_Out(301) <= \<const0>\;
  LOCKSTEP_Master_Out(302) <= \<const0>\;
  LOCKSTEP_Master_Out(303) <= \<const0>\;
  LOCKSTEP_Master_Out(304) <= \<const0>\;
  LOCKSTEP_Master_Out(305) <= \<const0>\;
  LOCKSTEP_Master_Out(306) <= \<const0>\;
  LOCKSTEP_Master_Out(307) <= \<const0>\;
  LOCKSTEP_Master_Out(308) <= \<const0>\;
  LOCKSTEP_Master_Out(309) <= \<const0>\;
  LOCKSTEP_Master_Out(310) <= \<const0>\;
  LOCKSTEP_Master_Out(311) <= \<const0>\;
  LOCKSTEP_Master_Out(312) <= \<const0>\;
  LOCKSTEP_Master_Out(313) <= \<const0>\;
  LOCKSTEP_Master_Out(314) <= \<const0>\;
  LOCKSTEP_Master_Out(315) <= \<const0>\;
  LOCKSTEP_Master_Out(316) <= \<const0>\;
  LOCKSTEP_Master_Out(317) <= \<const0>\;
  LOCKSTEP_Master_Out(318) <= \<const0>\;
  LOCKSTEP_Master_Out(319) <= \<const0>\;
  LOCKSTEP_Master_Out(320) <= \<const0>\;
  LOCKSTEP_Master_Out(321) <= \<const0>\;
  LOCKSTEP_Master_Out(322) <= \<const0>\;
  LOCKSTEP_Master_Out(323) <= \<const0>\;
  LOCKSTEP_Master_Out(324) <= \<const0>\;
  LOCKSTEP_Master_Out(325) <= \<const0>\;
  LOCKSTEP_Master_Out(326) <= \<const0>\;
  LOCKSTEP_Master_Out(327) <= \<const0>\;
  LOCKSTEP_Master_Out(328) <= \<const0>\;
  LOCKSTEP_Master_Out(329) <= \<const0>\;
  LOCKSTEP_Master_Out(330) <= \<const0>\;
  LOCKSTEP_Master_Out(331) <= \<const0>\;
  LOCKSTEP_Master_Out(332) <= \<const0>\;
  LOCKSTEP_Master_Out(333) <= \<const0>\;
  LOCKSTEP_Master_Out(334) <= \<const0>\;
  LOCKSTEP_Master_Out(335) <= \<const0>\;
  LOCKSTEP_Master_Out(336) <= \<const0>\;
  LOCKSTEP_Master_Out(337) <= \<const0>\;
  LOCKSTEP_Master_Out(338) <= \<const0>\;
  LOCKSTEP_Master_Out(339) <= \<const0>\;
  LOCKSTEP_Master_Out(340) <= \<const0>\;
  LOCKSTEP_Master_Out(341) <= \<const0>\;
  LOCKSTEP_Master_Out(342) <= \<const0>\;
  LOCKSTEP_Master_Out(343) <= \<const0>\;
  LOCKSTEP_Master_Out(344) <= \<const0>\;
  LOCKSTEP_Master_Out(345) <= \<const0>\;
  LOCKSTEP_Master_Out(346) <= \<const0>\;
  LOCKSTEP_Master_Out(347) <= \<const0>\;
  LOCKSTEP_Master_Out(348) <= \<const0>\;
  LOCKSTEP_Master_Out(349) <= \<const0>\;
  LOCKSTEP_Master_Out(350) <= \<const0>\;
  LOCKSTEP_Master_Out(351) <= \<const0>\;
  LOCKSTEP_Master_Out(352) <= \<const0>\;
  LOCKSTEP_Master_Out(353) <= \<const0>\;
  LOCKSTEP_Master_Out(354) <= \<const0>\;
  LOCKSTEP_Master_Out(355) <= \<const0>\;
  LOCKSTEP_Master_Out(356) <= \<const0>\;
  LOCKSTEP_Master_Out(357) <= \<const0>\;
  LOCKSTEP_Master_Out(358) <= \<const0>\;
  LOCKSTEP_Master_Out(359) <= \<const0>\;
  LOCKSTEP_Master_Out(360) <= \<const0>\;
  LOCKSTEP_Master_Out(361) <= \<const0>\;
  LOCKSTEP_Master_Out(362) <= \<const0>\;
  LOCKSTEP_Master_Out(363) <= \<const0>\;
  LOCKSTEP_Master_Out(364) <= \<const0>\;
  LOCKSTEP_Master_Out(365) <= \<const0>\;
  LOCKSTEP_Master_Out(366) <= \<const0>\;
  LOCKSTEP_Master_Out(367) <= \<const0>\;
  LOCKSTEP_Master_Out(368) <= \<const0>\;
  LOCKSTEP_Master_Out(369) <= \<const0>\;
  LOCKSTEP_Master_Out(370) <= \<const0>\;
  LOCKSTEP_Master_Out(371) <= \<const0>\;
  LOCKSTEP_Master_Out(372) <= \<const0>\;
  LOCKSTEP_Master_Out(373) <= \<const0>\;
  LOCKSTEP_Master_Out(374) <= \<const0>\;
  LOCKSTEP_Master_Out(375) <= \<const0>\;
  LOCKSTEP_Master_Out(376) <= \<const0>\;
  LOCKSTEP_Master_Out(377) <= \<const0>\;
  LOCKSTEP_Master_Out(378) <= \<const0>\;
  LOCKSTEP_Master_Out(379) <= \<const0>\;
  LOCKSTEP_Master_Out(380) <= \<const0>\;
  LOCKSTEP_Master_Out(381) <= \<const0>\;
  LOCKSTEP_Master_Out(382) <= \<const0>\;
  LOCKSTEP_Master_Out(383) <= \<const0>\;
  LOCKSTEP_Master_Out(384) <= \<const0>\;
  LOCKSTEP_Master_Out(385) <= \<const0>\;
  LOCKSTEP_Master_Out(386) <= \<const0>\;
  LOCKSTEP_Master_Out(387) <= \<const0>\;
  LOCKSTEP_Master_Out(388) <= \<const0>\;
  LOCKSTEP_Master_Out(389) <= \<const0>\;
  LOCKSTEP_Master_Out(390) <= \<const0>\;
  LOCKSTEP_Master_Out(391) <= \<const0>\;
  LOCKSTEP_Master_Out(392) <= \<const0>\;
  LOCKSTEP_Master_Out(393) <= \<const0>\;
  LOCKSTEP_Master_Out(394) <= \<const0>\;
  LOCKSTEP_Master_Out(395) <= \<const0>\;
  LOCKSTEP_Master_Out(396) <= \<const0>\;
  LOCKSTEP_Master_Out(397) <= \<const0>\;
  LOCKSTEP_Master_Out(398) <= \<const0>\;
  LOCKSTEP_Master_Out(399) <= \<const0>\;
  LOCKSTEP_Master_Out(400) <= \<const0>\;
  LOCKSTEP_Master_Out(401) <= \<const0>\;
  LOCKSTEP_Master_Out(402) <= \<const0>\;
  LOCKSTEP_Master_Out(403) <= \<const0>\;
  LOCKSTEP_Master_Out(404) <= \<const0>\;
  LOCKSTEP_Master_Out(405) <= \<const0>\;
  LOCKSTEP_Master_Out(406) <= \<const0>\;
  LOCKSTEP_Master_Out(407) <= \<const0>\;
  LOCKSTEP_Master_Out(408) <= \<const0>\;
  LOCKSTEP_Master_Out(409) <= \<const0>\;
  LOCKSTEP_Master_Out(410) <= \<const0>\;
  LOCKSTEP_Master_Out(411) <= \<const0>\;
  LOCKSTEP_Master_Out(412) <= \<const0>\;
  LOCKSTEP_Master_Out(413) <= \<const0>\;
  LOCKSTEP_Master_Out(414) <= \<const0>\;
  LOCKSTEP_Master_Out(415) <= \<const0>\;
  LOCKSTEP_Master_Out(416) <= \<const0>\;
  LOCKSTEP_Master_Out(417) <= \<const0>\;
  LOCKSTEP_Master_Out(418) <= \<const0>\;
  LOCKSTEP_Master_Out(419) <= \<const0>\;
  LOCKSTEP_Master_Out(420) <= \<const0>\;
  LOCKSTEP_Master_Out(421) <= \<const0>\;
  LOCKSTEP_Master_Out(422) <= \<const0>\;
  LOCKSTEP_Master_Out(423) <= \<const0>\;
  LOCKSTEP_Master_Out(424) <= \<const0>\;
  LOCKSTEP_Master_Out(425) <= \<const0>\;
  LOCKSTEP_Master_Out(426) <= \<const0>\;
  LOCKSTEP_Master_Out(427) <= \<const0>\;
  LOCKSTEP_Master_Out(428) <= \<const0>\;
  LOCKSTEP_Master_Out(429) <= \<const0>\;
  LOCKSTEP_Master_Out(430) <= \<const0>\;
  LOCKSTEP_Master_Out(431) <= \<const0>\;
  LOCKSTEP_Master_Out(432) <= \<const0>\;
  LOCKSTEP_Master_Out(433) <= \<const0>\;
  LOCKSTEP_Master_Out(434) <= \<const0>\;
  LOCKSTEP_Master_Out(435) <= \<const0>\;
  LOCKSTEP_Master_Out(436) <= \<const0>\;
  LOCKSTEP_Master_Out(437) <= \<const0>\;
  LOCKSTEP_Master_Out(438) <= \<const0>\;
  LOCKSTEP_Master_Out(439) <= \<const0>\;
  LOCKSTEP_Master_Out(440) <= \<const0>\;
  LOCKSTEP_Master_Out(441) <= \<const0>\;
  LOCKSTEP_Master_Out(442) <= \<const0>\;
  LOCKSTEP_Master_Out(443) <= \<const0>\;
  LOCKSTEP_Master_Out(444) <= \<const0>\;
  LOCKSTEP_Master_Out(445) <= \<const0>\;
  LOCKSTEP_Master_Out(446) <= \<const0>\;
  LOCKSTEP_Master_Out(447) <= \<const0>\;
  LOCKSTEP_Master_Out(448) <= \<const0>\;
  LOCKSTEP_Master_Out(449) <= \<const0>\;
  LOCKSTEP_Master_Out(450) <= \<const0>\;
  LOCKSTEP_Master_Out(451) <= \<const0>\;
  LOCKSTEP_Master_Out(452) <= \<const0>\;
  LOCKSTEP_Master_Out(453) <= \<const0>\;
  LOCKSTEP_Master_Out(454) <= \<const0>\;
  LOCKSTEP_Master_Out(455) <= \<const0>\;
  LOCKSTEP_Master_Out(456) <= \<const0>\;
  LOCKSTEP_Master_Out(457) <= \<const0>\;
  LOCKSTEP_Master_Out(458) <= \<const0>\;
  LOCKSTEP_Master_Out(459) <= \<const0>\;
  LOCKSTEP_Master_Out(460) <= \<const0>\;
  LOCKSTEP_Master_Out(461) <= \<const0>\;
  LOCKSTEP_Master_Out(462) <= \<const0>\;
  LOCKSTEP_Master_Out(463) <= \<const0>\;
  LOCKSTEP_Master_Out(464) <= \<const0>\;
  LOCKSTEP_Master_Out(465) <= \<const0>\;
  LOCKSTEP_Master_Out(466) <= \<const0>\;
  LOCKSTEP_Master_Out(467) <= \<const0>\;
  LOCKSTEP_Master_Out(468) <= \<const0>\;
  LOCKSTEP_Master_Out(469) <= \<const0>\;
  LOCKSTEP_Master_Out(470) <= \<const0>\;
  LOCKSTEP_Master_Out(471) <= \<const0>\;
  LOCKSTEP_Master_Out(472) <= \<const0>\;
  LOCKSTEP_Master_Out(473) <= \<const0>\;
  LOCKSTEP_Master_Out(474) <= \<const0>\;
  LOCKSTEP_Master_Out(475) <= \<const0>\;
  LOCKSTEP_Master_Out(476) <= \<const0>\;
  LOCKSTEP_Master_Out(477) <= \<const0>\;
  LOCKSTEP_Master_Out(478) <= \<const0>\;
  LOCKSTEP_Master_Out(479) <= \<const0>\;
  LOCKSTEP_Master_Out(480) <= \<const0>\;
  LOCKSTEP_Master_Out(481) <= \<const0>\;
  LOCKSTEP_Master_Out(482) <= \<const0>\;
  LOCKSTEP_Master_Out(483) <= \<const0>\;
  LOCKSTEP_Master_Out(484) <= \<const0>\;
  LOCKSTEP_Master_Out(485) <= \<const0>\;
  LOCKSTEP_Master_Out(486) <= \<const0>\;
  LOCKSTEP_Master_Out(487) <= \<const0>\;
  LOCKSTEP_Master_Out(488) <= \<const0>\;
  LOCKSTEP_Master_Out(489) <= \<const0>\;
  LOCKSTEP_Master_Out(490) <= \<const0>\;
  LOCKSTEP_Master_Out(491) <= \<const0>\;
  LOCKSTEP_Master_Out(492) <= \<const0>\;
  LOCKSTEP_Master_Out(493) <= \<const0>\;
  LOCKSTEP_Master_Out(494) <= \<const0>\;
  LOCKSTEP_Master_Out(495) <= \<const0>\;
  LOCKSTEP_Master_Out(496) <= \<const0>\;
  LOCKSTEP_Master_Out(497) <= \<const0>\;
  LOCKSTEP_Master_Out(498) <= \<const0>\;
  LOCKSTEP_Master_Out(499) <= \<const0>\;
  LOCKSTEP_Master_Out(500) <= \<const0>\;
  LOCKSTEP_Master_Out(501) <= \<const0>\;
  LOCKSTEP_Master_Out(502) <= \<const0>\;
  LOCKSTEP_Master_Out(503) <= \<const0>\;
  LOCKSTEP_Master_Out(504) <= \<const0>\;
  LOCKSTEP_Master_Out(505) <= \<const0>\;
  LOCKSTEP_Master_Out(506) <= \<const0>\;
  LOCKSTEP_Master_Out(507) <= \<const0>\;
  LOCKSTEP_Master_Out(508) <= \<const0>\;
  LOCKSTEP_Master_Out(509) <= \<const0>\;
  LOCKSTEP_Master_Out(510) <= \<const0>\;
  LOCKSTEP_Master_Out(511) <= \<const0>\;
  LOCKSTEP_Master_Out(512) <= \<const0>\;
  LOCKSTEP_Master_Out(513) <= \<const0>\;
  LOCKSTEP_Master_Out(514) <= \<const0>\;
  LOCKSTEP_Master_Out(515) <= \<const0>\;
  LOCKSTEP_Master_Out(516) <= \<const0>\;
  LOCKSTEP_Master_Out(517) <= \<const0>\;
  LOCKSTEP_Master_Out(518) <= \<const0>\;
  LOCKSTEP_Master_Out(519) <= \<const0>\;
  LOCKSTEP_Master_Out(520) <= \<const0>\;
  LOCKSTEP_Master_Out(521) <= \<const0>\;
  LOCKSTEP_Master_Out(522) <= \<const0>\;
  LOCKSTEP_Master_Out(523) <= \<const0>\;
  LOCKSTEP_Master_Out(524) <= \<const0>\;
  LOCKSTEP_Master_Out(525) <= \<const0>\;
  LOCKSTEP_Master_Out(526) <= \<const0>\;
  LOCKSTEP_Master_Out(527) <= \<const0>\;
  LOCKSTEP_Master_Out(528) <= \<const0>\;
  LOCKSTEP_Master_Out(529) <= \<const0>\;
  LOCKSTEP_Master_Out(530) <= \<const0>\;
  LOCKSTEP_Master_Out(531) <= \<const0>\;
  LOCKSTEP_Master_Out(532) <= \<const0>\;
  LOCKSTEP_Master_Out(533) <= \<const0>\;
  LOCKSTEP_Master_Out(534) <= \<const0>\;
  LOCKSTEP_Master_Out(535) <= \<const0>\;
  LOCKSTEP_Master_Out(536) <= \<const0>\;
  LOCKSTEP_Master_Out(537) <= \<const0>\;
  LOCKSTEP_Master_Out(538) <= \<const0>\;
  LOCKSTEP_Master_Out(539) <= \<const0>\;
  LOCKSTEP_Master_Out(540) <= \<const0>\;
  LOCKSTEP_Master_Out(541) <= \<const0>\;
  LOCKSTEP_Master_Out(542) <= \<const0>\;
  LOCKSTEP_Master_Out(543) <= \<const0>\;
  LOCKSTEP_Master_Out(544) <= \<const0>\;
  LOCKSTEP_Master_Out(545) <= \<const0>\;
  LOCKSTEP_Master_Out(546) <= \<const0>\;
  LOCKSTEP_Master_Out(547) <= \<const0>\;
  LOCKSTEP_Master_Out(548) <= \<const0>\;
  LOCKSTEP_Master_Out(549) <= \<const0>\;
  LOCKSTEP_Master_Out(550) <= \<const0>\;
  LOCKSTEP_Master_Out(551) <= \<const0>\;
  LOCKSTEP_Master_Out(552) <= \<const0>\;
  LOCKSTEP_Master_Out(553) <= \<const0>\;
  LOCKSTEP_Master_Out(554) <= \<const0>\;
  LOCKSTEP_Master_Out(555) <= \<const0>\;
  LOCKSTEP_Master_Out(556) <= \<const0>\;
  LOCKSTEP_Master_Out(557) <= \<const0>\;
  LOCKSTEP_Master_Out(558) <= \<const0>\;
  LOCKSTEP_Master_Out(559) <= \<const0>\;
  LOCKSTEP_Master_Out(560) <= \<const0>\;
  LOCKSTEP_Master_Out(561) <= \<const0>\;
  LOCKSTEP_Master_Out(562) <= \<const0>\;
  LOCKSTEP_Master_Out(563) <= \<const0>\;
  LOCKSTEP_Master_Out(564) <= \<const0>\;
  LOCKSTEP_Master_Out(565) <= \<const0>\;
  LOCKSTEP_Master_Out(566) <= \<const0>\;
  LOCKSTEP_Master_Out(567) <= \<const0>\;
  LOCKSTEP_Master_Out(568) <= \<const0>\;
  LOCKSTEP_Master_Out(569) <= \<const0>\;
  LOCKSTEP_Master_Out(570) <= \<const0>\;
  LOCKSTEP_Master_Out(571) <= \<const0>\;
  LOCKSTEP_Master_Out(572) <= \<const0>\;
  LOCKSTEP_Master_Out(573) <= \<const0>\;
  LOCKSTEP_Master_Out(574) <= \<const0>\;
  LOCKSTEP_Master_Out(575) <= \<const0>\;
  LOCKSTEP_Master_Out(576) <= \<const0>\;
  LOCKSTEP_Master_Out(577) <= \<const0>\;
  LOCKSTEP_Master_Out(578) <= \<const0>\;
  LOCKSTEP_Master_Out(579) <= \<const0>\;
  LOCKSTEP_Master_Out(580) <= \<const0>\;
  LOCKSTEP_Master_Out(581) <= \<const0>\;
  LOCKSTEP_Master_Out(582) <= \<const0>\;
  LOCKSTEP_Master_Out(583) <= \<const0>\;
  LOCKSTEP_Master_Out(584) <= \<const0>\;
  LOCKSTEP_Master_Out(585) <= \<const0>\;
  LOCKSTEP_Master_Out(586) <= \<const0>\;
  LOCKSTEP_Master_Out(587) <= \<const0>\;
  LOCKSTEP_Master_Out(588) <= \<const0>\;
  LOCKSTEP_Master_Out(589) <= \<const0>\;
  LOCKSTEP_Master_Out(590) <= \<const0>\;
  LOCKSTEP_Master_Out(591) <= \<const0>\;
  LOCKSTEP_Master_Out(592) <= \<const0>\;
  LOCKSTEP_Master_Out(593) <= \<const0>\;
  LOCKSTEP_Master_Out(594) <= \<const0>\;
  LOCKSTEP_Master_Out(595) <= \<const0>\;
  LOCKSTEP_Master_Out(596) <= \<const0>\;
  LOCKSTEP_Master_Out(597) <= \<const0>\;
  LOCKSTEP_Master_Out(598) <= \<const0>\;
  LOCKSTEP_Master_Out(599) <= \<const0>\;
  LOCKSTEP_Master_Out(600) <= \<const0>\;
  LOCKSTEP_Master_Out(601) <= \<const0>\;
  LOCKSTEP_Master_Out(602) <= \<const0>\;
  LOCKSTEP_Master_Out(603) <= \<const0>\;
  LOCKSTEP_Master_Out(604) <= \<const0>\;
  LOCKSTEP_Master_Out(605) <= \<const0>\;
  LOCKSTEP_Master_Out(606) <= \<const0>\;
  LOCKSTEP_Master_Out(607) <= \<const0>\;
  LOCKSTEP_Master_Out(608) <= \<const0>\;
  LOCKSTEP_Master_Out(609) <= \<const0>\;
  LOCKSTEP_Master_Out(610) <= \<const0>\;
  LOCKSTEP_Master_Out(611) <= \<const0>\;
  LOCKSTEP_Master_Out(612) <= \<const0>\;
  LOCKSTEP_Master_Out(613) <= \<const0>\;
  LOCKSTEP_Master_Out(614) <= \<const0>\;
  LOCKSTEP_Master_Out(615) <= \<const0>\;
  LOCKSTEP_Master_Out(616) <= \<const0>\;
  LOCKSTEP_Master_Out(617) <= \<const0>\;
  LOCKSTEP_Master_Out(618) <= \<const0>\;
  LOCKSTEP_Master_Out(619) <= \<const0>\;
  LOCKSTEP_Master_Out(620) <= \<const0>\;
  LOCKSTEP_Master_Out(621) <= \<const0>\;
  LOCKSTEP_Master_Out(622) <= \<const0>\;
  LOCKSTEP_Master_Out(623) <= \<const0>\;
  LOCKSTEP_Master_Out(624) <= \<const0>\;
  LOCKSTEP_Master_Out(625) <= \<const0>\;
  LOCKSTEP_Master_Out(626) <= \<const0>\;
  LOCKSTEP_Master_Out(627) <= \<const0>\;
  LOCKSTEP_Master_Out(628) <= \<const0>\;
  LOCKSTEP_Master_Out(629) <= \<const0>\;
  LOCKSTEP_Master_Out(630) <= \<const0>\;
  LOCKSTEP_Master_Out(631) <= \<const0>\;
  LOCKSTEP_Master_Out(632) <= \<const0>\;
  LOCKSTEP_Master_Out(633) <= \<const0>\;
  LOCKSTEP_Master_Out(634) <= \<const0>\;
  LOCKSTEP_Master_Out(635) <= \<const0>\;
  LOCKSTEP_Master_Out(636) <= \<const0>\;
  LOCKSTEP_Master_Out(637) <= \<const0>\;
  LOCKSTEP_Master_Out(638) <= \<const0>\;
  LOCKSTEP_Master_Out(639) <= \<const0>\;
  LOCKSTEP_Master_Out(640) <= \<const0>\;
  LOCKSTEP_Master_Out(641) <= \<const0>\;
  LOCKSTEP_Master_Out(642) <= \<const0>\;
  LOCKSTEP_Master_Out(643) <= \<const0>\;
  LOCKSTEP_Master_Out(644) <= \<const0>\;
  LOCKSTEP_Master_Out(645) <= \<const0>\;
  LOCKSTEP_Master_Out(646) <= \<const0>\;
  LOCKSTEP_Master_Out(647) <= \<const0>\;
  LOCKSTEP_Master_Out(648) <= \<const0>\;
  LOCKSTEP_Master_Out(649) <= \<const0>\;
  LOCKSTEP_Master_Out(650) <= \<const0>\;
  LOCKSTEP_Master_Out(651) <= \<const0>\;
  LOCKSTEP_Master_Out(652) <= \<const0>\;
  LOCKSTEP_Master_Out(653) <= \<const0>\;
  LOCKSTEP_Master_Out(654) <= \<const0>\;
  LOCKSTEP_Master_Out(655) <= \<const0>\;
  LOCKSTEP_Master_Out(656) <= \<const0>\;
  LOCKSTEP_Master_Out(657) <= \<const0>\;
  LOCKSTEP_Master_Out(658) <= \<const0>\;
  LOCKSTEP_Master_Out(659) <= \<const0>\;
  LOCKSTEP_Master_Out(660) <= \<const0>\;
  LOCKSTEP_Master_Out(661) <= \<const0>\;
  LOCKSTEP_Master_Out(662) <= \<const0>\;
  LOCKSTEP_Master_Out(663) <= \<const0>\;
  LOCKSTEP_Master_Out(664) <= \<const0>\;
  LOCKSTEP_Master_Out(665) <= \<const0>\;
  LOCKSTEP_Master_Out(666) <= \<const0>\;
  LOCKSTEP_Master_Out(667) <= \<const0>\;
  LOCKSTEP_Master_Out(668) <= \<const0>\;
  LOCKSTEP_Master_Out(669) <= \<const0>\;
  LOCKSTEP_Master_Out(670) <= \<const0>\;
  LOCKSTEP_Master_Out(671) <= \<const0>\;
  LOCKSTEP_Master_Out(672) <= \<const0>\;
  LOCKSTEP_Master_Out(673) <= \<const0>\;
  LOCKSTEP_Master_Out(674) <= \<const0>\;
  LOCKSTEP_Master_Out(675) <= \<const0>\;
  LOCKSTEP_Master_Out(676) <= \<const0>\;
  LOCKSTEP_Master_Out(677) <= \<const0>\;
  LOCKSTEP_Master_Out(678) <= \<const0>\;
  LOCKSTEP_Master_Out(679) <= \<const0>\;
  LOCKSTEP_Master_Out(680) <= \<const0>\;
  LOCKSTEP_Master_Out(681) <= \<const0>\;
  LOCKSTEP_Master_Out(682) <= \<const0>\;
  LOCKSTEP_Master_Out(683) <= \<const0>\;
  LOCKSTEP_Master_Out(684) <= \<const0>\;
  LOCKSTEP_Master_Out(685) <= \<const0>\;
  LOCKSTEP_Master_Out(686) <= \<const0>\;
  LOCKSTEP_Master_Out(687) <= \<const0>\;
  LOCKSTEP_Master_Out(688) <= \<const0>\;
  LOCKSTEP_Master_Out(689) <= \<const0>\;
  LOCKSTEP_Master_Out(690) <= \<const0>\;
  LOCKSTEP_Master_Out(691) <= \<const0>\;
  LOCKSTEP_Master_Out(692) <= \<const0>\;
  LOCKSTEP_Master_Out(693) <= \<const0>\;
  LOCKSTEP_Master_Out(694) <= \<const0>\;
  LOCKSTEP_Master_Out(695) <= \<const0>\;
  LOCKSTEP_Master_Out(696) <= \<const0>\;
  LOCKSTEP_Master_Out(697) <= \<const0>\;
  LOCKSTEP_Master_Out(698) <= \<const0>\;
  LOCKSTEP_Master_Out(699) <= \<const0>\;
  LOCKSTEP_Master_Out(700) <= \<const0>\;
  LOCKSTEP_Master_Out(701) <= \<const0>\;
  LOCKSTEP_Master_Out(702) <= \<const0>\;
  LOCKSTEP_Master_Out(703) <= \<const0>\;
  LOCKSTEP_Master_Out(704) <= \<const0>\;
  LOCKSTEP_Master_Out(705) <= \<const0>\;
  LOCKSTEP_Master_Out(706) <= \<const0>\;
  LOCKSTEP_Master_Out(707) <= \<const0>\;
  LOCKSTEP_Master_Out(708) <= \<const0>\;
  LOCKSTEP_Master_Out(709) <= \<const0>\;
  LOCKSTEP_Master_Out(710) <= \<const0>\;
  LOCKSTEP_Master_Out(711) <= \<const0>\;
  LOCKSTEP_Master_Out(712) <= \<const0>\;
  LOCKSTEP_Master_Out(713) <= \<const0>\;
  LOCKSTEP_Master_Out(714) <= \<const0>\;
  LOCKSTEP_Master_Out(715) <= \<const0>\;
  LOCKSTEP_Master_Out(716) <= \<const0>\;
  LOCKSTEP_Master_Out(717) <= \<const0>\;
  LOCKSTEP_Master_Out(718) <= \<const0>\;
  LOCKSTEP_Master_Out(719) <= \<const0>\;
  LOCKSTEP_Master_Out(720) <= \<const0>\;
  LOCKSTEP_Master_Out(721) <= \<const0>\;
  LOCKSTEP_Master_Out(722) <= \<const0>\;
  LOCKSTEP_Master_Out(723) <= \<const0>\;
  LOCKSTEP_Master_Out(724) <= \<const0>\;
  LOCKSTEP_Master_Out(725) <= \<const0>\;
  LOCKSTEP_Master_Out(726) <= \<const0>\;
  LOCKSTEP_Master_Out(727) <= \<const0>\;
  LOCKSTEP_Master_Out(728) <= \<const0>\;
  LOCKSTEP_Master_Out(729) <= \<const0>\;
  LOCKSTEP_Master_Out(730) <= \<const0>\;
  LOCKSTEP_Master_Out(731) <= \<const0>\;
  LOCKSTEP_Master_Out(732) <= \<const0>\;
  LOCKSTEP_Master_Out(733) <= \<const0>\;
  LOCKSTEP_Master_Out(734) <= \<const0>\;
  LOCKSTEP_Master_Out(735) <= \<const0>\;
  LOCKSTEP_Master_Out(736) <= \<const0>\;
  LOCKSTEP_Master_Out(737) <= \<const0>\;
  LOCKSTEP_Master_Out(738) <= \<const0>\;
  LOCKSTEP_Master_Out(739) <= \<const0>\;
  LOCKSTEP_Master_Out(740) <= \<const0>\;
  LOCKSTEP_Master_Out(741) <= \<const0>\;
  LOCKSTEP_Master_Out(742) <= \<const0>\;
  LOCKSTEP_Master_Out(743) <= \<const0>\;
  LOCKSTEP_Master_Out(744) <= \<const0>\;
  LOCKSTEP_Master_Out(745) <= \<const0>\;
  LOCKSTEP_Master_Out(746) <= \<const0>\;
  LOCKSTEP_Master_Out(747) <= \<const0>\;
  LOCKSTEP_Master_Out(748) <= \<const0>\;
  LOCKSTEP_Master_Out(749) <= \<const0>\;
  LOCKSTEP_Master_Out(750) <= \<const0>\;
  LOCKSTEP_Master_Out(751) <= \<const0>\;
  LOCKSTEP_Master_Out(752) <= \<const0>\;
  LOCKSTEP_Master_Out(753) <= \<const0>\;
  LOCKSTEP_Master_Out(754) <= \<const0>\;
  LOCKSTEP_Master_Out(755) <= \<const0>\;
  LOCKSTEP_Master_Out(756) <= \<const0>\;
  LOCKSTEP_Master_Out(757) <= \<const0>\;
  LOCKSTEP_Master_Out(758) <= \<const0>\;
  LOCKSTEP_Master_Out(759) <= \<const0>\;
  LOCKSTEP_Master_Out(760) <= \<const0>\;
  LOCKSTEP_Master_Out(761) <= \<const0>\;
  LOCKSTEP_Master_Out(762) <= \<const0>\;
  LOCKSTEP_Master_Out(763) <= \<const0>\;
  LOCKSTEP_Master_Out(764) <= \<const0>\;
  LOCKSTEP_Master_Out(765) <= \<const0>\;
  LOCKSTEP_Master_Out(766) <= \<const0>\;
  LOCKSTEP_Master_Out(767) <= \<const0>\;
  LOCKSTEP_Master_Out(768) <= \<const0>\;
  LOCKSTEP_Master_Out(769) <= \<const0>\;
  LOCKSTEP_Master_Out(770) <= \<const0>\;
  LOCKSTEP_Master_Out(771) <= \<const0>\;
  LOCKSTEP_Master_Out(772) <= \<const0>\;
  LOCKSTEP_Master_Out(773) <= \<const0>\;
  LOCKSTEP_Master_Out(774) <= \<const0>\;
  LOCKSTEP_Master_Out(775) <= \<const0>\;
  LOCKSTEP_Master_Out(776) <= \<const0>\;
  LOCKSTEP_Master_Out(777) <= \<const0>\;
  LOCKSTEP_Master_Out(778) <= \<const0>\;
  LOCKSTEP_Master_Out(779) <= \<const0>\;
  LOCKSTEP_Master_Out(780) <= \<const0>\;
  LOCKSTEP_Master_Out(781) <= \<const0>\;
  LOCKSTEP_Master_Out(782) <= \<const0>\;
  LOCKSTEP_Master_Out(783) <= \<const0>\;
  LOCKSTEP_Master_Out(784) <= \<const0>\;
  LOCKSTEP_Master_Out(785) <= \<const0>\;
  LOCKSTEP_Master_Out(786) <= \<const0>\;
  LOCKSTEP_Master_Out(787) <= \<const0>\;
  LOCKSTEP_Master_Out(788) <= \<const0>\;
  LOCKSTEP_Master_Out(789) <= \<const0>\;
  LOCKSTEP_Master_Out(790) <= \<const0>\;
  LOCKSTEP_Master_Out(791) <= \<const0>\;
  LOCKSTEP_Master_Out(792) <= \<const0>\;
  LOCKSTEP_Master_Out(793) <= \<const0>\;
  LOCKSTEP_Master_Out(794) <= \<const0>\;
  LOCKSTEP_Master_Out(795) <= \<const0>\;
  LOCKSTEP_Master_Out(796) <= \<const0>\;
  LOCKSTEP_Master_Out(797) <= \<const0>\;
  LOCKSTEP_Master_Out(798) <= \<const0>\;
  LOCKSTEP_Master_Out(799) <= \<const0>\;
  LOCKSTEP_Master_Out(800) <= \<const0>\;
  LOCKSTEP_Master_Out(801) <= \<const0>\;
  LOCKSTEP_Master_Out(802) <= \<const0>\;
  LOCKSTEP_Master_Out(803) <= \<const0>\;
  LOCKSTEP_Master_Out(804) <= \<const0>\;
  LOCKSTEP_Master_Out(805) <= \<const0>\;
  LOCKSTEP_Master_Out(806) <= \<const0>\;
  LOCKSTEP_Master_Out(807) <= \<const0>\;
  LOCKSTEP_Master_Out(808) <= \<const0>\;
  LOCKSTEP_Master_Out(809) <= \<const0>\;
  LOCKSTEP_Master_Out(810) <= \<const0>\;
  LOCKSTEP_Master_Out(811) <= \<const0>\;
  LOCKSTEP_Master_Out(812) <= \<const0>\;
  LOCKSTEP_Master_Out(813) <= \<const0>\;
  LOCKSTEP_Master_Out(814) <= \<const0>\;
  LOCKSTEP_Master_Out(815) <= \<const0>\;
  LOCKSTEP_Master_Out(816) <= \<const0>\;
  LOCKSTEP_Master_Out(817) <= \<const0>\;
  LOCKSTEP_Master_Out(818) <= \<const0>\;
  LOCKSTEP_Master_Out(819) <= \<const0>\;
  LOCKSTEP_Master_Out(820) <= \<const0>\;
  LOCKSTEP_Master_Out(821) <= \<const0>\;
  LOCKSTEP_Master_Out(822) <= \<const0>\;
  LOCKSTEP_Master_Out(823) <= \<const0>\;
  LOCKSTEP_Master_Out(824) <= \<const0>\;
  LOCKSTEP_Master_Out(825) <= \<const0>\;
  LOCKSTEP_Master_Out(826) <= \<const0>\;
  LOCKSTEP_Master_Out(827) <= \<const0>\;
  LOCKSTEP_Master_Out(828) <= \<const0>\;
  LOCKSTEP_Master_Out(829) <= \<const0>\;
  LOCKSTEP_Master_Out(830) <= \<const0>\;
  LOCKSTEP_Master_Out(831) <= \<const0>\;
  LOCKSTEP_Master_Out(832) <= \<const0>\;
  LOCKSTEP_Master_Out(833) <= \<const0>\;
  LOCKSTEP_Master_Out(834) <= \<const0>\;
  LOCKSTEP_Master_Out(835) <= \<const0>\;
  LOCKSTEP_Master_Out(836) <= \<const0>\;
  LOCKSTEP_Master_Out(837) <= \<const0>\;
  LOCKSTEP_Master_Out(838) <= \<const0>\;
  LOCKSTEP_Master_Out(839) <= \<const0>\;
  LOCKSTEP_Master_Out(840) <= \<const0>\;
  LOCKSTEP_Master_Out(841) <= \<const0>\;
  LOCKSTEP_Master_Out(842) <= \<const0>\;
  LOCKSTEP_Master_Out(843) <= \<const0>\;
  LOCKSTEP_Master_Out(844) <= \<const0>\;
  LOCKSTEP_Master_Out(845) <= \<const0>\;
  LOCKSTEP_Master_Out(846) <= \<const0>\;
  LOCKSTEP_Master_Out(847) <= \<const0>\;
  LOCKSTEP_Master_Out(848) <= \<const0>\;
  LOCKSTEP_Master_Out(849) <= \<const0>\;
  LOCKSTEP_Master_Out(850) <= \<const0>\;
  LOCKSTEP_Master_Out(851) <= \<const0>\;
  LOCKSTEP_Master_Out(852) <= \<const0>\;
  LOCKSTEP_Master_Out(853) <= \<const0>\;
  LOCKSTEP_Master_Out(854) <= \<const0>\;
  LOCKSTEP_Master_Out(855) <= \<const0>\;
  LOCKSTEP_Master_Out(856) <= \<const0>\;
  LOCKSTEP_Master_Out(857) <= \<const0>\;
  LOCKSTEP_Master_Out(858) <= \<const0>\;
  LOCKSTEP_Master_Out(859) <= \<const0>\;
  LOCKSTEP_Master_Out(860) <= \<const0>\;
  LOCKSTEP_Master_Out(861) <= \<const0>\;
  LOCKSTEP_Master_Out(862) <= \<const0>\;
  LOCKSTEP_Master_Out(863) <= \<const0>\;
  LOCKSTEP_Master_Out(864) <= \<const0>\;
  LOCKSTEP_Master_Out(865) <= \<const0>\;
  LOCKSTEP_Master_Out(866) <= \<const0>\;
  LOCKSTEP_Master_Out(867) <= \<const0>\;
  LOCKSTEP_Master_Out(868) <= \<const0>\;
  LOCKSTEP_Master_Out(869) <= \<const0>\;
  LOCKSTEP_Master_Out(870) <= \<const0>\;
  LOCKSTEP_Master_Out(871) <= \<const0>\;
  LOCKSTEP_Master_Out(872) <= \<const0>\;
  LOCKSTEP_Master_Out(873) <= \<const0>\;
  LOCKSTEP_Master_Out(874) <= \<const0>\;
  LOCKSTEP_Master_Out(875) <= \<const0>\;
  LOCKSTEP_Master_Out(876) <= \<const0>\;
  LOCKSTEP_Master_Out(877) <= \<const0>\;
  LOCKSTEP_Master_Out(878) <= \<const0>\;
  LOCKSTEP_Master_Out(879) <= \<const0>\;
  LOCKSTEP_Master_Out(880) <= \<const0>\;
  LOCKSTEP_Master_Out(881) <= \<const0>\;
  LOCKSTEP_Master_Out(882) <= \<const0>\;
  LOCKSTEP_Master_Out(883) <= \<const0>\;
  LOCKSTEP_Master_Out(884) <= \<const0>\;
  LOCKSTEP_Master_Out(885) <= \<const0>\;
  LOCKSTEP_Master_Out(886) <= \<const0>\;
  LOCKSTEP_Master_Out(887) <= \<const0>\;
  LOCKSTEP_Master_Out(888) <= \<const0>\;
  LOCKSTEP_Master_Out(889) <= \<const0>\;
  LOCKSTEP_Master_Out(890) <= \<const0>\;
  LOCKSTEP_Master_Out(891) <= \<const0>\;
  LOCKSTEP_Master_Out(892) <= \<const0>\;
  LOCKSTEP_Master_Out(893) <= \<const0>\;
  LOCKSTEP_Master_Out(894) <= \<const0>\;
  LOCKSTEP_Master_Out(895) <= \<const0>\;
  LOCKSTEP_Master_Out(896) <= \<const0>\;
  LOCKSTEP_Master_Out(897) <= \<const0>\;
  LOCKSTEP_Master_Out(898) <= \<const0>\;
  LOCKSTEP_Master_Out(899) <= \<const0>\;
  LOCKSTEP_Master_Out(900) <= \<const0>\;
  LOCKSTEP_Master_Out(901) <= \<const0>\;
  LOCKSTEP_Master_Out(902) <= \<const0>\;
  LOCKSTEP_Master_Out(903) <= \<const0>\;
  LOCKSTEP_Master_Out(904) <= \<const0>\;
  LOCKSTEP_Master_Out(905) <= \<const0>\;
  LOCKSTEP_Master_Out(906) <= \<const0>\;
  LOCKSTEP_Master_Out(907) <= \<const0>\;
  LOCKSTEP_Master_Out(908) <= \<const0>\;
  LOCKSTEP_Master_Out(909) <= \<const0>\;
  LOCKSTEP_Master_Out(910) <= \<const0>\;
  LOCKSTEP_Master_Out(911) <= \<const0>\;
  LOCKSTEP_Master_Out(912) <= \<const0>\;
  LOCKSTEP_Master_Out(913) <= \<const0>\;
  LOCKSTEP_Master_Out(914) <= \<const0>\;
  LOCKSTEP_Master_Out(915) <= \<const0>\;
  LOCKSTEP_Master_Out(916) <= \<const0>\;
  LOCKSTEP_Master_Out(917) <= \<const0>\;
  LOCKSTEP_Master_Out(918) <= \<const0>\;
  LOCKSTEP_Master_Out(919) <= \<const0>\;
  LOCKSTEP_Master_Out(920) <= \<const0>\;
  LOCKSTEP_Master_Out(921) <= \<const0>\;
  LOCKSTEP_Master_Out(922) <= \<const0>\;
  LOCKSTEP_Master_Out(923) <= \<const0>\;
  LOCKSTEP_Master_Out(924) <= \<const0>\;
  LOCKSTEP_Master_Out(925) <= \<const0>\;
  LOCKSTEP_Master_Out(926) <= \<const0>\;
  LOCKSTEP_Master_Out(927) <= \<const0>\;
  LOCKSTEP_Master_Out(928) <= \<const0>\;
  LOCKSTEP_Master_Out(929) <= \<const0>\;
  LOCKSTEP_Master_Out(930) <= \<const0>\;
  LOCKSTEP_Master_Out(931) <= \<const0>\;
  LOCKSTEP_Master_Out(932) <= \<const0>\;
  LOCKSTEP_Master_Out(933) <= \<const0>\;
  LOCKSTEP_Master_Out(934) <= \<const0>\;
  LOCKSTEP_Master_Out(935) <= \<const0>\;
  LOCKSTEP_Master_Out(936) <= \<const0>\;
  LOCKSTEP_Master_Out(937) <= \<const0>\;
  LOCKSTEP_Master_Out(938) <= \<const0>\;
  LOCKSTEP_Master_Out(939) <= \<const0>\;
  LOCKSTEP_Master_Out(940) <= \<const0>\;
  LOCKSTEP_Master_Out(941) <= \<const0>\;
  LOCKSTEP_Master_Out(942) <= \<const0>\;
  LOCKSTEP_Master_Out(943) <= \<const0>\;
  LOCKSTEP_Master_Out(944) <= \<const0>\;
  LOCKSTEP_Master_Out(945) <= \<const0>\;
  LOCKSTEP_Master_Out(946) <= \<const0>\;
  LOCKSTEP_Master_Out(947) <= \<const0>\;
  LOCKSTEP_Master_Out(948) <= \<const0>\;
  LOCKSTEP_Master_Out(949) <= \<const0>\;
  LOCKSTEP_Master_Out(950) <= \<const0>\;
  LOCKSTEP_Master_Out(951) <= \<const0>\;
  LOCKSTEP_Master_Out(952) <= \<const0>\;
  LOCKSTEP_Master_Out(953) <= \<const0>\;
  LOCKSTEP_Master_Out(954) <= \<const0>\;
  LOCKSTEP_Master_Out(955) <= \<const0>\;
  LOCKSTEP_Master_Out(956) <= \<const0>\;
  LOCKSTEP_Master_Out(957) <= \<const0>\;
  LOCKSTEP_Master_Out(958) <= \<const0>\;
  LOCKSTEP_Master_Out(959) <= \<const0>\;
  LOCKSTEP_Master_Out(960) <= \<const0>\;
  LOCKSTEP_Master_Out(961) <= \<const0>\;
  LOCKSTEP_Master_Out(962) <= \<const0>\;
  LOCKSTEP_Master_Out(963) <= \<const0>\;
  LOCKSTEP_Master_Out(964) <= \<const0>\;
  LOCKSTEP_Master_Out(965) <= \<const0>\;
  LOCKSTEP_Master_Out(966) <= \<const0>\;
  LOCKSTEP_Master_Out(967) <= \<const0>\;
  LOCKSTEP_Master_Out(968) <= \<const0>\;
  LOCKSTEP_Master_Out(969) <= \<const0>\;
  LOCKSTEP_Master_Out(970) <= \<const0>\;
  LOCKSTEP_Master_Out(971) <= \<const0>\;
  LOCKSTEP_Master_Out(972) <= \<const0>\;
  LOCKSTEP_Master_Out(973) <= \<const0>\;
  LOCKSTEP_Master_Out(974) <= \<const0>\;
  LOCKSTEP_Master_Out(975) <= \<const0>\;
  LOCKSTEP_Master_Out(976) <= \<const0>\;
  LOCKSTEP_Master_Out(977) <= \<const0>\;
  LOCKSTEP_Master_Out(978) <= \<const0>\;
  LOCKSTEP_Master_Out(979) <= \<const0>\;
  LOCKSTEP_Master_Out(980) <= \<const0>\;
  LOCKSTEP_Master_Out(981) <= \<const0>\;
  LOCKSTEP_Master_Out(982) <= \<const0>\;
  LOCKSTEP_Master_Out(983) <= \<const0>\;
  LOCKSTEP_Master_Out(984) <= \<const0>\;
  LOCKSTEP_Master_Out(985) <= \<const0>\;
  LOCKSTEP_Master_Out(986) <= \<const0>\;
  LOCKSTEP_Master_Out(987) <= \<const0>\;
  LOCKSTEP_Master_Out(988) <= \<const0>\;
  LOCKSTEP_Master_Out(989) <= \<const0>\;
  LOCKSTEP_Master_Out(990) <= \<const0>\;
  LOCKSTEP_Master_Out(991) <= \<const0>\;
  LOCKSTEP_Master_Out(992) <= \<const0>\;
  LOCKSTEP_Master_Out(993) <= \<const0>\;
  LOCKSTEP_Master_Out(994) <= \<const0>\;
  LOCKSTEP_Master_Out(995) <= \<const0>\;
  LOCKSTEP_Master_Out(996) <= \<const0>\;
  LOCKSTEP_Master_Out(997) <= \<const0>\;
  LOCKSTEP_Master_Out(998) <= \<const0>\;
  LOCKSTEP_Master_Out(999) <= \<const0>\;
  LOCKSTEP_Master_Out(1000) <= \<const0>\;
  LOCKSTEP_Master_Out(1001) <= \<const0>\;
  LOCKSTEP_Master_Out(1002) <= \<const0>\;
  LOCKSTEP_Master_Out(1003) <= \<const0>\;
  LOCKSTEP_Master_Out(1004) <= \<const0>\;
  LOCKSTEP_Master_Out(1005) <= \<const0>\;
  LOCKSTEP_Master_Out(1006) <= \<const0>\;
  LOCKSTEP_Master_Out(1007) <= \<const0>\;
  LOCKSTEP_Master_Out(1008) <= \<const0>\;
  LOCKSTEP_Master_Out(1009) <= \<const0>\;
  LOCKSTEP_Master_Out(1010) <= \<const0>\;
  LOCKSTEP_Master_Out(1011) <= \<const0>\;
  LOCKSTEP_Master_Out(1012) <= \<const0>\;
  LOCKSTEP_Master_Out(1013) <= \<const0>\;
  LOCKSTEP_Master_Out(1014) <= \<const0>\;
  LOCKSTEP_Master_Out(1015) <= \<const0>\;
  LOCKSTEP_Master_Out(1016) <= \<const0>\;
  LOCKSTEP_Master_Out(1017) <= \<const0>\;
  LOCKSTEP_Master_Out(1018) <= \<const0>\;
  LOCKSTEP_Master_Out(1019) <= \<const0>\;
  LOCKSTEP_Master_Out(1020) <= \<const0>\;
  LOCKSTEP_Master_Out(1021) <= \<const0>\;
  LOCKSTEP_Master_Out(1022) <= \<const0>\;
  LOCKSTEP_Master_Out(1023) <= \<const0>\;
  LOCKSTEP_Master_Out(1024) <= \<const0>\;
  LOCKSTEP_Master_Out(1025) <= \<const0>\;
  LOCKSTEP_Master_Out(1026) <= \<const0>\;
  LOCKSTEP_Master_Out(1027) <= \<const0>\;
  LOCKSTEP_Master_Out(1028) <= \<const0>\;
  LOCKSTEP_Master_Out(1029) <= \<const0>\;
  LOCKSTEP_Master_Out(1030) <= \<const0>\;
  LOCKSTEP_Master_Out(1031) <= \<const0>\;
  LOCKSTEP_Master_Out(1032) <= \<const0>\;
  LOCKSTEP_Master_Out(1033) <= \<const0>\;
  LOCKSTEP_Master_Out(1034) <= \<const0>\;
  LOCKSTEP_Master_Out(1035) <= \<const0>\;
  LOCKSTEP_Master_Out(1036) <= \<const0>\;
  LOCKSTEP_Master_Out(1037) <= \<const0>\;
  LOCKSTEP_Master_Out(1038) <= \<const0>\;
  LOCKSTEP_Master_Out(1039) <= \<const0>\;
  LOCKSTEP_Master_Out(1040) <= \<const0>\;
  LOCKSTEP_Master_Out(1041) <= \<const0>\;
  LOCKSTEP_Master_Out(1042) <= \<const0>\;
  LOCKSTEP_Master_Out(1043) <= \<const0>\;
  LOCKSTEP_Master_Out(1044) <= \<const0>\;
  LOCKSTEP_Master_Out(1045) <= \<const0>\;
  LOCKSTEP_Master_Out(1046) <= \<const0>\;
  LOCKSTEP_Master_Out(1047) <= \<const0>\;
  LOCKSTEP_Master_Out(1048) <= \<const0>\;
  LOCKSTEP_Master_Out(1049) <= \<const0>\;
  LOCKSTEP_Master_Out(1050) <= \<const0>\;
  LOCKSTEP_Master_Out(1051) <= \<const0>\;
  LOCKSTEP_Master_Out(1052) <= \<const0>\;
  LOCKSTEP_Master_Out(1053) <= \<const0>\;
  LOCKSTEP_Master_Out(1054) <= \<const0>\;
  LOCKSTEP_Master_Out(1055) <= \<const0>\;
  LOCKSTEP_Master_Out(1056) <= \<const0>\;
  LOCKSTEP_Master_Out(1057) <= \<const0>\;
  LOCKSTEP_Master_Out(1058) <= \<const0>\;
  LOCKSTEP_Master_Out(1059) <= \<const0>\;
  LOCKSTEP_Master_Out(1060) <= \<const0>\;
  LOCKSTEP_Master_Out(1061) <= \<const0>\;
  LOCKSTEP_Master_Out(1062) <= \<const0>\;
  LOCKSTEP_Master_Out(1063) <= \<const0>\;
  LOCKSTEP_Master_Out(1064) <= \<const0>\;
  LOCKSTEP_Master_Out(1065) <= \<const0>\;
  LOCKSTEP_Master_Out(1066) <= \<const0>\;
  LOCKSTEP_Master_Out(1067) <= \<const0>\;
  LOCKSTEP_Master_Out(1068) <= \<const0>\;
  LOCKSTEP_Master_Out(1069) <= \<const0>\;
  LOCKSTEP_Master_Out(1070) <= \<const0>\;
  LOCKSTEP_Master_Out(1071) <= \<const0>\;
  LOCKSTEP_Master_Out(1072) <= \<const0>\;
  LOCKSTEP_Master_Out(1073) <= \<const0>\;
  LOCKSTEP_Master_Out(1074) <= \<const0>\;
  LOCKSTEP_Master_Out(1075) <= \<const0>\;
  LOCKSTEP_Master_Out(1076) <= \<const0>\;
  LOCKSTEP_Master_Out(1077) <= \<const0>\;
  LOCKSTEP_Master_Out(1078) <= \<const0>\;
  LOCKSTEP_Master_Out(1079) <= \<const0>\;
  LOCKSTEP_Master_Out(1080) <= \<const0>\;
  LOCKSTEP_Master_Out(1081) <= \<const0>\;
  LOCKSTEP_Master_Out(1082) <= \<const0>\;
  LOCKSTEP_Master_Out(1083) <= \<const0>\;
  LOCKSTEP_Master_Out(1084) <= \<const0>\;
  LOCKSTEP_Master_Out(1085) <= \<const0>\;
  LOCKSTEP_Master_Out(1086) <= \<const0>\;
  LOCKSTEP_Master_Out(1087) <= \<const0>\;
  LOCKSTEP_Master_Out(1088) <= \<const0>\;
  LOCKSTEP_Master_Out(1089) <= \<const0>\;
  LOCKSTEP_Master_Out(1090) <= \<const0>\;
  LOCKSTEP_Master_Out(1091) <= \<const0>\;
  LOCKSTEP_Master_Out(1092) <= \<const0>\;
  LOCKSTEP_Master_Out(1093) <= \<const0>\;
  LOCKSTEP_Master_Out(1094) <= \<const0>\;
  LOCKSTEP_Master_Out(1095) <= \<const0>\;
  LOCKSTEP_Master_Out(1096) <= \<const0>\;
  LOCKSTEP_Master_Out(1097) <= \<const0>\;
  LOCKSTEP_Master_Out(1098) <= \<const0>\;
  LOCKSTEP_Master_Out(1099) <= \<const0>\;
  LOCKSTEP_Master_Out(1100) <= \<const0>\;
  LOCKSTEP_Master_Out(1101) <= \<const0>\;
  LOCKSTEP_Master_Out(1102) <= \<const0>\;
  LOCKSTEP_Master_Out(1103) <= \<const0>\;
  LOCKSTEP_Master_Out(1104) <= \<const0>\;
  LOCKSTEP_Master_Out(1105) <= \<const0>\;
  LOCKSTEP_Master_Out(1106) <= \<const0>\;
  LOCKSTEP_Master_Out(1107) <= \<const0>\;
  LOCKSTEP_Master_Out(1108) <= \<const0>\;
  LOCKSTEP_Master_Out(1109) <= \<const0>\;
  LOCKSTEP_Master_Out(1110) <= \<const0>\;
  LOCKSTEP_Master_Out(1111) <= \<const0>\;
  LOCKSTEP_Master_Out(1112) <= \<const0>\;
  LOCKSTEP_Master_Out(1113) <= \<const0>\;
  LOCKSTEP_Master_Out(1114) <= \<const0>\;
  LOCKSTEP_Master_Out(1115) <= \<const0>\;
  LOCKSTEP_Master_Out(1116) <= \<const0>\;
  LOCKSTEP_Master_Out(1117) <= \<const0>\;
  LOCKSTEP_Master_Out(1118) <= \<const0>\;
  LOCKSTEP_Master_Out(1119) <= \<const0>\;
  LOCKSTEP_Master_Out(1120) <= \<const0>\;
  LOCKSTEP_Master_Out(1121) <= \<const0>\;
  LOCKSTEP_Master_Out(1122) <= \<const0>\;
  LOCKSTEP_Master_Out(1123) <= \<const0>\;
  LOCKSTEP_Master_Out(1124) <= \<const0>\;
  LOCKSTEP_Master_Out(1125) <= \<const0>\;
  LOCKSTEP_Master_Out(1126) <= \<const0>\;
  LOCKSTEP_Master_Out(1127) <= \<const0>\;
  LOCKSTEP_Master_Out(1128) <= \<const0>\;
  LOCKSTEP_Master_Out(1129) <= \<const0>\;
  LOCKSTEP_Master_Out(1130) <= \<const0>\;
  LOCKSTEP_Master_Out(1131) <= \<const0>\;
  LOCKSTEP_Master_Out(1132) <= \<const0>\;
  LOCKSTEP_Master_Out(1133) <= \<const0>\;
  LOCKSTEP_Master_Out(1134) <= \<const0>\;
  LOCKSTEP_Master_Out(1135) <= \<const0>\;
  LOCKSTEP_Master_Out(1136) <= \<const0>\;
  LOCKSTEP_Master_Out(1137) <= \<const0>\;
  LOCKSTEP_Master_Out(1138) <= \<const0>\;
  LOCKSTEP_Master_Out(1139) <= \<const0>\;
  LOCKSTEP_Master_Out(1140) <= \<const0>\;
  LOCKSTEP_Master_Out(1141) <= \<const0>\;
  LOCKSTEP_Master_Out(1142) <= \<const0>\;
  LOCKSTEP_Master_Out(1143) <= \<const0>\;
  LOCKSTEP_Master_Out(1144) <= \<const0>\;
  LOCKSTEP_Master_Out(1145) <= \<const0>\;
  LOCKSTEP_Master_Out(1146) <= \<const0>\;
  LOCKSTEP_Master_Out(1147) <= \<const0>\;
  LOCKSTEP_Master_Out(1148) <= \<const0>\;
  LOCKSTEP_Master_Out(1149) <= \<const0>\;
  LOCKSTEP_Master_Out(1150) <= \<const0>\;
  LOCKSTEP_Master_Out(1151) <= \<const0>\;
  LOCKSTEP_Master_Out(1152) <= \<const0>\;
  LOCKSTEP_Master_Out(1153) <= \<const0>\;
  LOCKSTEP_Master_Out(1154) <= \<const0>\;
  LOCKSTEP_Master_Out(1155) <= \<const0>\;
  LOCKSTEP_Master_Out(1156) <= \<const0>\;
  LOCKSTEP_Master_Out(1157) <= \<const0>\;
  LOCKSTEP_Master_Out(1158) <= \<const0>\;
  LOCKSTEP_Master_Out(1159) <= \<const0>\;
  LOCKSTEP_Master_Out(1160) <= \<const0>\;
  LOCKSTEP_Master_Out(1161) <= \<const0>\;
  LOCKSTEP_Master_Out(1162) <= \<const0>\;
  LOCKSTEP_Master_Out(1163) <= \<const0>\;
  LOCKSTEP_Master_Out(1164) <= \<const0>\;
  LOCKSTEP_Master_Out(1165) <= \<const0>\;
  LOCKSTEP_Master_Out(1166) <= \<const0>\;
  LOCKSTEP_Master_Out(1167) <= \<const0>\;
  LOCKSTEP_Master_Out(1168) <= \<const0>\;
  LOCKSTEP_Master_Out(1169) <= \<const0>\;
  LOCKSTEP_Master_Out(1170) <= \<const0>\;
  LOCKSTEP_Master_Out(1171) <= \<const0>\;
  LOCKSTEP_Master_Out(1172) <= \<const0>\;
  LOCKSTEP_Master_Out(1173) <= \<const0>\;
  LOCKSTEP_Master_Out(1174) <= \<const0>\;
  LOCKSTEP_Master_Out(1175) <= \<const0>\;
  LOCKSTEP_Master_Out(1176) <= \<const0>\;
  LOCKSTEP_Master_Out(1177) <= \<const0>\;
  LOCKSTEP_Master_Out(1178) <= \<const0>\;
  LOCKSTEP_Master_Out(1179) <= \<const0>\;
  LOCKSTEP_Master_Out(1180) <= \<const0>\;
  LOCKSTEP_Master_Out(1181) <= \<const0>\;
  LOCKSTEP_Master_Out(1182) <= \<const0>\;
  LOCKSTEP_Master_Out(1183) <= \<const0>\;
  LOCKSTEP_Master_Out(1184) <= \<const0>\;
  LOCKSTEP_Master_Out(1185) <= \<const0>\;
  LOCKSTEP_Master_Out(1186) <= \<const0>\;
  LOCKSTEP_Master_Out(1187) <= \<const0>\;
  LOCKSTEP_Master_Out(1188) <= \<const0>\;
  LOCKSTEP_Master_Out(1189) <= \<const0>\;
  LOCKSTEP_Master_Out(1190) <= \<const0>\;
  LOCKSTEP_Master_Out(1191) <= \<const0>\;
  LOCKSTEP_Master_Out(1192) <= \<const0>\;
  LOCKSTEP_Master_Out(1193) <= \<const0>\;
  LOCKSTEP_Master_Out(1194) <= \<const0>\;
  LOCKSTEP_Master_Out(1195) <= \<const0>\;
  LOCKSTEP_Master_Out(1196) <= \<const0>\;
  LOCKSTEP_Master_Out(1197) <= \<const0>\;
  LOCKSTEP_Master_Out(1198) <= \<const0>\;
  LOCKSTEP_Master_Out(1199) <= \<const0>\;
  LOCKSTEP_Master_Out(1200) <= \<const0>\;
  LOCKSTEP_Master_Out(1201) <= \<const0>\;
  LOCKSTEP_Master_Out(1202) <= \<const0>\;
  LOCKSTEP_Master_Out(1203) <= \<const0>\;
  LOCKSTEP_Master_Out(1204) <= \<const0>\;
  LOCKSTEP_Master_Out(1205) <= \<const0>\;
  LOCKSTEP_Master_Out(1206) <= \<const0>\;
  LOCKSTEP_Master_Out(1207) <= \<const0>\;
  LOCKSTEP_Master_Out(1208) <= \<const0>\;
  LOCKSTEP_Master_Out(1209) <= \<const0>\;
  LOCKSTEP_Master_Out(1210) <= \<const0>\;
  LOCKSTEP_Master_Out(1211) <= \<const0>\;
  LOCKSTEP_Master_Out(1212) <= \<const0>\;
  LOCKSTEP_Master_Out(1213) <= \<const0>\;
  LOCKSTEP_Master_Out(1214) <= \<const0>\;
  LOCKSTEP_Master_Out(1215) <= \<const0>\;
  LOCKSTEP_Master_Out(1216) <= \<const0>\;
  LOCKSTEP_Master_Out(1217) <= \<const0>\;
  LOCKSTEP_Master_Out(1218) <= \<const0>\;
  LOCKSTEP_Master_Out(1219) <= \<const0>\;
  LOCKSTEP_Master_Out(1220) <= \<const0>\;
  LOCKSTEP_Master_Out(1221) <= \<const0>\;
  LOCKSTEP_Master_Out(1222) <= \<const0>\;
  LOCKSTEP_Master_Out(1223) <= \<const0>\;
  LOCKSTEP_Master_Out(1224) <= \<const0>\;
  LOCKSTEP_Master_Out(1225) <= \<const0>\;
  LOCKSTEP_Master_Out(1226) <= \<const0>\;
  LOCKSTEP_Master_Out(1227) <= \<const0>\;
  LOCKSTEP_Master_Out(1228) <= \<const0>\;
  LOCKSTEP_Master_Out(1229) <= \<const0>\;
  LOCKSTEP_Master_Out(1230) <= \<const0>\;
  LOCKSTEP_Master_Out(1231) <= \<const0>\;
  LOCKSTEP_Master_Out(1232) <= \<const0>\;
  LOCKSTEP_Master_Out(1233) <= \<const0>\;
  LOCKSTEP_Master_Out(1234) <= \<const0>\;
  LOCKSTEP_Master_Out(1235) <= \<const0>\;
  LOCKSTEP_Master_Out(1236) <= \<const0>\;
  LOCKSTEP_Master_Out(1237) <= \<const0>\;
  LOCKSTEP_Master_Out(1238) <= \<const0>\;
  LOCKSTEP_Master_Out(1239) <= \<const0>\;
  LOCKSTEP_Master_Out(1240) <= \<const0>\;
  LOCKSTEP_Master_Out(1241) <= \<const0>\;
  LOCKSTEP_Master_Out(1242) <= \<const0>\;
  LOCKSTEP_Master_Out(1243) <= \<const0>\;
  LOCKSTEP_Master_Out(1244) <= \<const0>\;
  LOCKSTEP_Master_Out(1245) <= \<const0>\;
  LOCKSTEP_Master_Out(1246) <= \<const0>\;
  LOCKSTEP_Master_Out(1247) <= \<const0>\;
  LOCKSTEP_Master_Out(1248) <= \<const0>\;
  LOCKSTEP_Master_Out(1249) <= \<const0>\;
  LOCKSTEP_Master_Out(1250) <= \<const0>\;
  LOCKSTEP_Master_Out(1251) <= \<const0>\;
  LOCKSTEP_Master_Out(1252) <= \<const0>\;
  LOCKSTEP_Master_Out(1253) <= \<const0>\;
  LOCKSTEP_Master_Out(1254) <= \<const0>\;
  LOCKSTEP_Master_Out(1255) <= \<const0>\;
  LOCKSTEP_Master_Out(1256) <= \<const0>\;
  LOCKSTEP_Master_Out(1257) <= \<const0>\;
  LOCKSTEP_Master_Out(1258) <= \<const0>\;
  LOCKSTEP_Master_Out(1259) <= \<const0>\;
  LOCKSTEP_Master_Out(1260) <= \<const0>\;
  LOCKSTEP_Master_Out(1261) <= \<const0>\;
  LOCKSTEP_Master_Out(1262) <= \<const0>\;
  LOCKSTEP_Master_Out(1263) <= \<const0>\;
  LOCKSTEP_Master_Out(1264) <= \<const0>\;
  LOCKSTEP_Master_Out(1265) <= \<const0>\;
  LOCKSTEP_Master_Out(1266) <= \<const0>\;
  LOCKSTEP_Master_Out(1267) <= \<const0>\;
  LOCKSTEP_Master_Out(1268) <= \<const0>\;
  LOCKSTEP_Master_Out(1269) <= \<const0>\;
  LOCKSTEP_Master_Out(1270) <= \<const0>\;
  LOCKSTEP_Master_Out(1271) <= \<const0>\;
  LOCKSTEP_Master_Out(1272) <= \<const0>\;
  LOCKSTEP_Master_Out(1273) <= \<const0>\;
  LOCKSTEP_Master_Out(1274) <= \<const0>\;
  LOCKSTEP_Master_Out(1275) <= \<const0>\;
  LOCKSTEP_Master_Out(1276) <= \<const0>\;
  LOCKSTEP_Master_Out(1277) <= \<const0>\;
  LOCKSTEP_Master_Out(1278) <= \<const0>\;
  LOCKSTEP_Master_Out(1279) <= \<const0>\;
  LOCKSTEP_Master_Out(1280) <= \<const0>\;
  LOCKSTEP_Master_Out(1281) <= \<const0>\;
  LOCKSTEP_Master_Out(1282) <= \<const0>\;
  LOCKSTEP_Master_Out(1283) <= \<const0>\;
  LOCKSTEP_Master_Out(1284) <= \<const0>\;
  LOCKSTEP_Master_Out(1285) <= \<const0>\;
  LOCKSTEP_Master_Out(1286) <= \<const0>\;
  LOCKSTEP_Master_Out(1287) <= \<const0>\;
  LOCKSTEP_Master_Out(1288) <= \<const0>\;
  LOCKSTEP_Master_Out(1289) <= \<const0>\;
  LOCKSTEP_Master_Out(1290) <= \<const0>\;
  LOCKSTEP_Master_Out(1291) <= \<const0>\;
  LOCKSTEP_Master_Out(1292) <= \<const0>\;
  LOCKSTEP_Master_Out(1293) <= \<const0>\;
  LOCKSTEP_Master_Out(1294) <= \<const0>\;
  LOCKSTEP_Master_Out(1295) <= \<const0>\;
  LOCKSTEP_Master_Out(1296) <= \<const0>\;
  LOCKSTEP_Master_Out(1297) <= \<const0>\;
  LOCKSTEP_Master_Out(1298) <= \<const0>\;
  LOCKSTEP_Master_Out(1299) <= \<const0>\;
  LOCKSTEP_Master_Out(1300) <= \<const0>\;
  LOCKSTEP_Master_Out(1301) <= \<const0>\;
  LOCKSTEP_Master_Out(1302) <= \<const0>\;
  LOCKSTEP_Master_Out(1303) <= \<const0>\;
  LOCKSTEP_Master_Out(1304) <= \<const0>\;
  LOCKSTEP_Master_Out(1305) <= \<const0>\;
  LOCKSTEP_Master_Out(1306) <= \<const0>\;
  LOCKSTEP_Master_Out(1307) <= \<const0>\;
  LOCKSTEP_Master_Out(1308) <= \<const0>\;
  LOCKSTEP_Master_Out(1309) <= \<const0>\;
  LOCKSTEP_Master_Out(1310) <= \<const0>\;
  LOCKSTEP_Master_Out(1311) <= \<const0>\;
  LOCKSTEP_Master_Out(1312) <= \<const0>\;
  LOCKSTEP_Master_Out(1313) <= \<const0>\;
  LOCKSTEP_Master_Out(1314) <= \<const0>\;
  LOCKSTEP_Master_Out(1315) <= \<const0>\;
  LOCKSTEP_Master_Out(1316) <= \<const0>\;
  LOCKSTEP_Master_Out(1317) <= \<const0>\;
  LOCKSTEP_Master_Out(1318) <= \<const0>\;
  LOCKSTEP_Master_Out(1319) <= \<const0>\;
  LOCKSTEP_Master_Out(1320) <= \<const0>\;
  LOCKSTEP_Master_Out(1321) <= \<const0>\;
  LOCKSTEP_Master_Out(1322) <= \<const0>\;
  LOCKSTEP_Master_Out(1323) <= \<const0>\;
  LOCKSTEP_Master_Out(1324) <= \<const0>\;
  LOCKSTEP_Master_Out(1325) <= \<const0>\;
  LOCKSTEP_Master_Out(1326) <= \<const0>\;
  LOCKSTEP_Master_Out(1327) <= \<const0>\;
  LOCKSTEP_Master_Out(1328) <= \<const0>\;
  LOCKSTEP_Master_Out(1329) <= \<const0>\;
  LOCKSTEP_Master_Out(1330) <= \<const0>\;
  LOCKSTEP_Master_Out(1331) <= \<const0>\;
  LOCKSTEP_Master_Out(1332) <= \<const0>\;
  LOCKSTEP_Master_Out(1333) <= \<const0>\;
  LOCKSTEP_Master_Out(1334) <= \<const0>\;
  LOCKSTEP_Master_Out(1335) <= \<const0>\;
  LOCKSTEP_Master_Out(1336) <= \<const0>\;
  LOCKSTEP_Master_Out(1337) <= \<const0>\;
  LOCKSTEP_Master_Out(1338) <= \<const0>\;
  LOCKSTEP_Master_Out(1339) <= \<const0>\;
  LOCKSTEP_Master_Out(1340) <= \<const0>\;
  LOCKSTEP_Master_Out(1341) <= \<const0>\;
  LOCKSTEP_Master_Out(1342) <= \<const0>\;
  LOCKSTEP_Master_Out(1343) <= \<const0>\;
  LOCKSTEP_Master_Out(1344) <= \<const0>\;
  LOCKSTEP_Master_Out(1345) <= \<const0>\;
  LOCKSTEP_Master_Out(1346) <= \<const0>\;
  LOCKSTEP_Master_Out(1347) <= \<const0>\;
  LOCKSTEP_Master_Out(1348) <= \<const0>\;
  LOCKSTEP_Master_Out(1349) <= \<const0>\;
  LOCKSTEP_Master_Out(1350) <= \<const0>\;
  LOCKSTEP_Master_Out(1351) <= \<const0>\;
  LOCKSTEP_Master_Out(1352) <= \<const0>\;
  LOCKSTEP_Master_Out(1353) <= \<const0>\;
  LOCKSTEP_Master_Out(1354) <= \<const0>\;
  LOCKSTEP_Master_Out(1355) <= \<const0>\;
  LOCKSTEP_Master_Out(1356) <= \<const0>\;
  LOCKSTEP_Master_Out(1357) <= \<const0>\;
  LOCKSTEP_Master_Out(1358) <= \<const0>\;
  LOCKSTEP_Master_Out(1359) <= \<const0>\;
  LOCKSTEP_Master_Out(1360) <= \<const0>\;
  LOCKSTEP_Master_Out(1361) <= \<const0>\;
  LOCKSTEP_Master_Out(1362) <= \<const0>\;
  LOCKSTEP_Master_Out(1363) <= \<const0>\;
  LOCKSTEP_Master_Out(1364) <= \<const0>\;
  LOCKSTEP_Master_Out(1365) <= \<const0>\;
  LOCKSTEP_Master_Out(1366) <= \<const0>\;
  LOCKSTEP_Master_Out(1367) <= \<const0>\;
  LOCKSTEP_Master_Out(1368) <= \<const0>\;
  LOCKSTEP_Master_Out(1369) <= \<const0>\;
  LOCKSTEP_Master_Out(1370) <= \<const0>\;
  LOCKSTEP_Master_Out(1371) <= \<const0>\;
  LOCKSTEP_Master_Out(1372) <= \<const0>\;
  LOCKSTEP_Master_Out(1373) <= \<const0>\;
  LOCKSTEP_Master_Out(1374) <= \<const0>\;
  LOCKSTEP_Master_Out(1375) <= \<const0>\;
  LOCKSTEP_Master_Out(1376) <= \<const0>\;
  LOCKSTEP_Master_Out(1377) <= \<const0>\;
  LOCKSTEP_Master_Out(1378) <= \<const0>\;
  LOCKSTEP_Master_Out(1379) <= \<const0>\;
  LOCKSTEP_Master_Out(1380) <= \<const0>\;
  LOCKSTEP_Master_Out(1381) <= \<const0>\;
  LOCKSTEP_Master_Out(1382) <= \<const0>\;
  LOCKSTEP_Master_Out(1383) <= \<const0>\;
  LOCKSTEP_Master_Out(1384) <= \<const0>\;
  LOCKSTEP_Master_Out(1385) <= \<const0>\;
  LOCKSTEP_Master_Out(1386) <= \<const0>\;
  LOCKSTEP_Master_Out(1387) <= \<const0>\;
  LOCKSTEP_Master_Out(1388) <= \<const0>\;
  LOCKSTEP_Master_Out(1389) <= \<const0>\;
  LOCKSTEP_Master_Out(1390) <= \<const0>\;
  LOCKSTEP_Master_Out(1391) <= \<const0>\;
  LOCKSTEP_Master_Out(1392) <= \<const0>\;
  LOCKSTEP_Master_Out(1393) <= \<const0>\;
  LOCKSTEP_Master_Out(1394) <= \<const0>\;
  LOCKSTEP_Master_Out(1395) <= \<const0>\;
  LOCKSTEP_Master_Out(1396) <= \<const0>\;
  LOCKSTEP_Master_Out(1397) <= \<const0>\;
  LOCKSTEP_Master_Out(1398) <= \<const0>\;
  LOCKSTEP_Master_Out(1399) <= \<const0>\;
  LOCKSTEP_Master_Out(1400) <= \<const0>\;
  LOCKSTEP_Master_Out(1401) <= \<const0>\;
  LOCKSTEP_Master_Out(1402) <= \<const0>\;
  LOCKSTEP_Master_Out(1403) <= \<const0>\;
  LOCKSTEP_Master_Out(1404) <= \<const0>\;
  LOCKSTEP_Master_Out(1405) <= \<const0>\;
  LOCKSTEP_Master_Out(1406) <= \<const0>\;
  LOCKSTEP_Master_Out(1407) <= \<const0>\;
  LOCKSTEP_Master_Out(1408) <= \<const0>\;
  LOCKSTEP_Master_Out(1409) <= \<const0>\;
  LOCKSTEP_Master_Out(1410) <= \<const0>\;
  LOCKSTEP_Master_Out(1411) <= \<const0>\;
  LOCKSTEP_Master_Out(1412) <= \<const0>\;
  LOCKSTEP_Master_Out(1413) <= \<const0>\;
  LOCKSTEP_Master_Out(1414) <= \<const0>\;
  LOCKSTEP_Master_Out(1415) <= \<const0>\;
  LOCKSTEP_Master_Out(1416) <= \<const0>\;
  LOCKSTEP_Master_Out(1417) <= \<const0>\;
  LOCKSTEP_Master_Out(1418) <= \<const0>\;
  LOCKSTEP_Master_Out(1419) <= \<const0>\;
  LOCKSTEP_Master_Out(1420) <= \<const0>\;
  LOCKSTEP_Master_Out(1421) <= \<const0>\;
  LOCKSTEP_Master_Out(1422) <= \<const0>\;
  LOCKSTEP_Master_Out(1423) <= \<const0>\;
  LOCKSTEP_Master_Out(1424) <= \<const0>\;
  LOCKSTEP_Master_Out(1425) <= \<const0>\;
  LOCKSTEP_Master_Out(1426) <= \<const0>\;
  LOCKSTEP_Master_Out(1427) <= \<const0>\;
  LOCKSTEP_Master_Out(1428) <= \<const0>\;
  LOCKSTEP_Master_Out(1429) <= \<const0>\;
  LOCKSTEP_Master_Out(1430) <= \<const0>\;
  LOCKSTEP_Master_Out(1431) <= \<const0>\;
  LOCKSTEP_Master_Out(1432) <= \<const0>\;
  LOCKSTEP_Master_Out(1433) <= \<const0>\;
  LOCKSTEP_Master_Out(1434) <= \<const0>\;
  LOCKSTEP_Master_Out(1435) <= \<const0>\;
  LOCKSTEP_Master_Out(1436) <= \<const0>\;
  LOCKSTEP_Master_Out(1437) <= \<const0>\;
  LOCKSTEP_Master_Out(1438) <= \<const0>\;
  LOCKSTEP_Master_Out(1439) <= \<const0>\;
  LOCKSTEP_Master_Out(1440) <= \<const0>\;
  LOCKSTEP_Master_Out(1441) <= \<const0>\;
  LOCKSTEP_Master_Out(1442) <= \<const0>\;
  LOCKSTEP_Master_Out(1443) <= \<const0>\;
  LOCKSTEP_Master_Out(1444) <= \<const0>\;
  LOCKSTEP_Master_Out(1445) <= \<const0>\;
  LOCKSTEP_Master_Out(1446) <= \<const0>\;
  LOCKSTEP_Master_Out(1447) <= \<const0>\;
  LOCKSTEP_Master_Out(1448) <= \<const0>\;
  LOCKSTEP_Master_Out(1449) <= \<const0>\;
  LOCKSTEP_Master_Out(1450) <= \<const0>\;
  LOCKSTEP_Master_Out(1451) <= \<const0>\;
  LOCKSTEP_Master_Out(1452) <= \<const0>\;
  LOCKSTEP_Master_Out(1453) <= \<const0>\;
  LOCKSTEP_Master_Out(1454) <= \<const0>\;
  LOCKSTEP_Master_Out(1455) <= \<const0>\;
  LOCKSTEP_Master_Out(1456) <= \<const0>\;
  LOCKSTEP_Master_Out(1457) <= \<const0>\;
  LOCKSTEP_Master_Out(1458) <= \<const0>\;
  LOCKSTEP_Master_Out(1459) <= \<const0>\;
  LOCKSTEP_Master_Out(1460) <= \<const0>\;
  LOCKSTEP_Master_Out(1461) <= \<const0>\;
  LOCKSTEP_Master_Out(1462) <= \<const0>\;
  LOCKSTEP_Master_Out(1463) <= \<const0>\;
  LOCKSTEP_Master_Out(1464) <= \<const0>\;
  LOCKSTEP_Master_Out(1465) <= \<const0>\;
  LOCKSTEP_Master_Out(1466) <= \<const0>\;
  LOCKSTEP_Master_Out(1467) <= \<const0>\;
  LOCKSTEP_Master_Out(1468) <= \<const0>\;
  LOCKSTEP_Master_Out(1469) <= \<const0>\;
  LOCKSTEP_Master_Out(1470) <= \<const0>\;
  LOCKSTEP_Master_Out(1471) <= \<const0>\;
  LOCKSTEP_Master_Out(1472) <= \<const0>\;
  LOCKSTEP_Master_Out(1473) <= \<const0>\;
  LOCKSTEP_Master_Out(1474) <= \<const0>\;
  LOCKSTEP_Master_Out(1475) <= \<const0>\;
  LOCKSTEP_Master_Out(1476) <= \<const0>\;
  LOCKSTEP_Master_Out(1477) <= \<const0>\;
  LOCKSTEP_Master_Out(1478) <= \<const0>\;
  LOCKSTEP_Master_Out(1479) <= \<const0>\;
  LOCKSTEP_Master_Out(1480) <= \<const0>\;
  LOCKSTEP_Master_Out(1481) <= \<const0>\;
  LOCKSTEP_Master_Out(1482) <= \<const0>\;
  LOCKSTEP_Master_Out(1483) <= \<const0>\;
  LOCKSTEP_Master_Out(1484) <= \<const0>\;
  LOCKSTEP_Master_Out(1485) <= \<const0>\;
  LOCKSTEP_Master_Out(1486) <= \<const0>\;
  LOCKSTEP_Master_Out(1487) <= \<const0>\;
  LOCKSTEP_Master_Out(1488) <= \<const0>\;
  LOCKSTEP_Master_Out(1489) <= \<const0>\;
  LOCKSTEP_Master_Out(1490) <= \<const0>\;
  LOCKSTEP_Master_Out(1491) <= \<const0>\;
  LOCKSTEP_Master_Out(1492) <= \<const0>\;
  LOCKSTEP_Master_Out(1493) <= \<const0>\;
  LOCKSTEP_Master_Out(1494) <= \<const0>\;
  LOCKSTEP_Master_Out(1495) <= \<const0>\;
  LOCKSTEP_Master_Out(1496) <= \<const0>\;
  LOCKSTEP_Master_Out(1497) <= \<const0>\;
  LOCKSTEP_Master_Out(1498) <= \<const0>\;
  LOCKSTEP_Master_Out(1499) <= \<const0>\;
  LOCKSTEP_Master_Out(1500) <= \<const0>\;
  LOCKSTEP_Master_Out(1501) <= \<const0>\;
  LOCKSTEP_Master_Out(1502) <= \<const0>\;
  LOCKSTEP_Master_Out(1503) <= \<const0>\;
  LOCKSTEP_Master_Out(1504) <= \<const0>\;
  LOCKSTEP_Master_Out(1505) <= \<const0>\;
  LOCKSTEP_Master_Out(1506) <= \<const0>\;
  LOCKSTEP_Master_Out(1507) <= \<const0>\;
  LOCKSTEP_Master_Out(1508) <= \<const0>\;
  LOCKSTEP_Master_Out(1509) <= \<const0>\;
  LOCKSTEP_Master_Out(1510) <= \<const0>\;
  LOCKSTEP_Master_Out(1511) <= \<const0>\;
  LOCKSTEP_Master_Out(1512) <= \<const0>\;
  LOCKSTEP_Master_Out(1513) <= \<const0>\;
  LOCKSTEP_Master_Out(1514) <= \<const0>\;
  LOCKSTEP_Master_Out(1515) <= \<const0>\;
  LOCKSTEP_Master_Out(1516) <= \<const0>\;
  LOCKSTEP_Master_Out(1517) <= \<const0>\;
  LOCKSTEP_Master_Out(1518) <= \<const0>\;
  LOCKSTEP_Master_Out(1519) <= \<const0>\;
  LOCKSTEP_Master_Out(1520) <= \<const0>\;
  LOCKSTEP_Master_Out(1521) <= \<const0>\;
  LOCKSTEP_Master_Out(1522) <= \<const0>\;
  LOCKSTEP_Master_Out(1523) <= \<const0>\;
  LOCKSTEP_Master_Out(1524) <= \<const0>\;
  LOCKSTEP_Master_Out(1525) <= \<const0>\;
  LOCKSTEP_Master_Out(1526) <= \<const0>\;
  LOCKSTEP_Master_Out(1527) <= \<const0>\;
  LOCKSTEP_Master_Out(1528) <= \<const0>\;
  LOCKSTEP_Master_Out(1529) <= \<const0>\;
  LOCKSTEP_Master_Out(1530) <= \<const0>\;
  LOCKSTEP_Master_Out(1531) <= \<const0>\;
  LOCKSTEP_Master_Out(1532) <= \<const0>\;
  LOCKSTEP_Master_Out(1533) <= \<const0>\;
  LOCKSTEP_Master_Out(1534) <= \<const0>\;
  LOCKSTEP_Master_Out(1535) <= \<const0>\;
  LOCKSTEP_Master_Out(1536) <= \<const0>\;
  LOCKSTEP_Master_Out(1537) <= \<const0>\;
  LOCKSTEP_Master_Out(1538) <= \<const0>\;
  LOCKSTEP_Master_Out(1539) <= \<const0>\;
  LOCKSTEP_Master_Out(1540) <= \<const0>\;
  LOCKSTEP_Master_Out(1541) <= \<const0>\;
  LOCKSTEP_Master_Out(1542) <= \<const0>\;
  LOCKSTEP_Master_Out(1543) <= \<const0>\;
  LOCKSTEP_Master_Out(1544) <= \<const0>\;
  LOCKSTEP_Master_Out(1545) <= \<const0>\;
  LOCKSTEP_Master_Out(1546) <= \<const0>\;
  LOCKSTEP_Master_Out(1547) <= \<const0>\;
  LOCKSTEP_Master_Out(1548) <= \<const0>\;
  LOCKSTEP_Master_Out(1549) <= \<const0>\;
  LOCKSTEP_Master_Out(1550) <= \<const0>\;
  LOCKSTEP_Master_Out(1551) <= \<const0>\;
  LOCKSTEP_Master_Out(1552) <= \<const0>\;
  LOCKSTEP_Master_Out(1553) <= \<const0>\;
  LOCKSTEP_Master_Out(1554) <= \<const0>\;
  LOCKSTEP_Master_Out(1555) <= \<const0>\;
  LOCKSTEP_Master_Out(1556) <= \<const0>\;
  LOCKSTEP_Master_Out(1557) <= \<const0>\;
  LOCKSTEP_Master_Out(1558) <= \<const0>\;
  LOCKSTEP_Master_Out(1559) <= \<const0>\;
  LOCKSTEP_Master_Out(1560) <= \<const0>\;
  LOCKSTEP_Master_Out(1561) <= \<const0>\;
  LOCKSTEP_Master_Out(1562) <= \<const0>\;
  LOCKSTEP_Master_Out(1563) <= \<const0>\;
  LOCKSTEP_Master_Out(1564) <= \<const0>\;
  LOCKSTEP_Master_Out(1565) <= \<const0>\;
  LOCKSTEP_Master_Out(1566) <= \<const0>\;
  LOCKSTEP_Master_Out(1567) <= \<const0>\;
  LOCKSTEP_Master_Out(1568) <= \<const0>\;
  LOCKSTEP_Master_Out(1569) <= \<const0>\;
  LOCKSTEP_Master_Out(1570) <= \<const0>\;
  LOCKSTEP_Master_Out(1571) <= \<const0>\;
  LOCKSTEP_Master_Out(1572) <= \<const0>\;
  LOCKSTEP_Master_Out(1573) <= \<const0>\;
  LOCKSTEP_Master_Out(1574) <= \<const0>\;
  LOCKSTEP_Master_Out(1575) <= \<const0>\;
  LOCKSTEP_Master_Out(1576) <= \<const0>\;
  LOCKSTEP_Master_Out(1577) <= \<const0>\;
  LOCKSTEP_Master_Out(1578) <= \<const0>\;
  LOCKSTEP_Master_Out(1579) <= \<const0>\;
  LOCKSTEP_Master_Out(1580) <= \<const0>\;
  LOCKSTEP_Master_Out(1581) <= \<const0>\;
  LOCKSTEP_Master_Out(1582) <= \<const0>\;
  LOCKSTEP_Master_Out(1583) <= \<const0>\;
  LOCKSTEP_Master_Out(1584) <= \<const0>\;
  LOCKSTEP_Master_Out(1585) <= \<const0>\;
  LOCKSTEP_Master_Out(1586) <= \<const0>\;
  LOCKSTEP_Master_Out(1587) <= \<const0>\;
  LOCKSTEP_Master_Out(1588) <= \<const0>\;
  LOCKSTEP_Master_Out(1589) <= \<const0>\;
  LOCKSTEP_Master_Out(1590) <= \<const0>\;
  LOCKSTEP_Master_Out(1591) <= \<const0>\;
  LOCKSTEP_Master_Out(1592) <= \<const0>\;
  LOCKSTEP_Master_Out(1593) <= \<const0>\;
  LOCKSTEP_Master_Out(1594) <= \<const0>\;
  LOCKSTEP_Master_Out(1595) <= \<const0>\;
  LOCKSTEP_Master_Out(1596) <= \<const0>\;
  LOCKSTEP_Master_Out(1597) <= \<const0>\;
  LOCKSTEP_Master_Out(1598) <= \<const0>\;
  LOCKSTEP_Master_Out(1599) <= \<const0>\;
  LOCKSTEP_Master_Out(1600) <= \<const0>\;
  LOCKSTEP_Master_Out(1601) <= \<const0>\;
  LOCKSTEP_Master_Out(1602) <= \<const0>\;
  LOCKSTEP_Master_Out(1603) <= \<const0>\;
  LOCKSTEP_Master_Out(1604) <= \<const0>\;
  LOCKSTEP_Master_Out(1605) <= \<const0>\;
  LOCKSTEP_Master_Out(1606) <= \<const0>\;
  LOCKSTEP_Master_Out(1607) <= \<const0>\;
  LOCKSTEP_Master_Out(1608) <= \<const0>\;
  LOCKSTEP_Master_Out(1609) <= \<const0>\;
  LOCKSTEP_Master_Out(1610) <= \<const0>\;
  LOCKSTEP_Master_Out(1611) <= \<const0>\;
  LOCKSTEP_Master_Out(1612) <= \<const0>\;
  LOCKSTEP_Master_Out(1613) <= \<const0>\;
  LOCKSTEP_Master_Out(1614) <= \<const0>\;
  LOCKSTEP_Master_Out(1615) <= \<const0>\;
  LOCKSTEP_Master_Out(1616) <= \<const0>\;
  LOCKSTEP_Master_Out(1617) <= \<const0>\;
  LOCKSTEP_Master_Out(1618) <= \<const0>\;
  LOCKSTEP_Master_Out(1619) <= \<const0>\;
  LOCKSTEP_Master_Out(1620) <= \<const0>\;
  LOCKSTEP_Master_Out(1621) <= \<const0>\;
  LOCKSTEP_Master_Out(1622) <= \<const0>\;
  LOCKSTEP_Master_Out(1623) <= \<const0>\;
  LOCKSTEP_Master_Out(1624) <= \<const0>\;
  LOCKSTEP_Master_Out(1625) <= \<const0>\;
  LOCKSTEP_Master_Out(1626) <= \<const0>\;
  LOCKSTEP_Master_Out(1627) <= \<const0>\;
  LOCKSTEP_Master_Out(1628) <= \<const0>\;
  LOCKSTEP_Master_Out(1629) <= \<const0>\;
  LOCKSTEP_Master_Out(1630) <= \<const0>\;
  LOCKSTEP_Master_Out(1631) <= \<const0>\;
  LOCKSTEP_Master_Out(1632) <= \<const0>\;
  LOCKSTEP_Master_Out(1633) <= \<const0>\;
  LOCKSTEP_Master_Out(1634) <= \<const0>\;
  LOCKSTEP_Master_Out(1635) <= \<const0>\;
  LOCKSTEP_Master_Out(1636) <= \<const0>\;
  LOCKSTEP_Master_Out(1637) <= \<const0>\;
  LOCKSTEP_Master_Out(1638) <= \<const0>\;
  LOCKSTEP_Master_Out(1639) <= \<const0>\;
  LOCKSTEP_Master_Out(1640) <= \<const0>\;
  LOCKSTEP_Master_Out(1641) <= \<const0>\;
  LOCKSTEP_Master_Out(1642) <= \<const0>\;
  LOCKSTEP_Master_Out(1643) <= \<const0>\;
  LOCKSTEP_Master_Out(1644) <= \<const0>\;
  LOCKSTEP_Master_Out(1645) <= \<const0>\;
  LOCKSTEP_Master_Out(1646) <= \<const0>\;
  LOCKSTEP_Master_Out(1647) <= \<const0>\;
  LOCKSTEP_Master_Out(1648) <= \<const0>\;
  LOCKSTEP_Master_Out(1649) <= \<const0>\;
  LOCKSTEP_Master_Out(1650) <= \<const0>\;
  LOCKSTEP_Master_Out(1651) <= \<const0>\;
  LOCKSTEP_Master_Out(1652) <= \<const0>\;
  LOCKSTEP_Master_Out(1653) <= \<const0>\;
  LOCKSTEP_Master_Out(1654) <= \<const0>\;
  LOCKSTEP_Master_Out(1655) <= \<const0>\;
  LOCKSTEP_Master_Out(1656) <= \<const0>\;
  LOCKSTEP_Master_Out(1657) <= \<const0>\;
  LOCKSTEP_Master_Out(1658) <= \<const0>\;
  LOCKSTEP_Master_Out(1659) <= \<const0>\;
  LOCKSTEP_Master_Out(1660) <= \<const0>\;
  LOCKSTEP_Master_Out(1661) <= \<const0>\;
  LOCKSTEP_Master_Out(1662) <= \<const0>\;
  LOCKSTEP_Master_Out(1663) <= \<const0>\;
  LOCKSTEP_Master_Out(1664) <= \<const0>\;
  LOCKSTEP_Master_Out(1665) <= \<const0>\;
  LOCKSTEP_Master_Out(1666) <= \<const0>\;
  LOCKSTEP_Master_Out(1667) <= \<const0>\;
  LOCKSTEP_Master_Out(1668) <= \<const0>\;
  LOCKSTEP_Master_Out(1669) <= \<const0>\;
  LOCKSTEP_Master_Out(1670) <= \<const0>\;
  LOCKSTEP_Master_Out(1671) <= \<const0>\;
  LOCKSTEP_Master_Out(1672) <= \<const0>\;
  LOCKSTEP_Master_Out(1673) <= \<const0>\;
  LOCKSTEP_Master_Out(1674) <= \<const0>\;
  LOCKSTEP_Master_Out(1675) <= \<const0>\;
  LOCKSTEP_Master_Out(1676) <= \<const0>\;
  LOCKSTEP_Master_Out(1677) <= \<const0>\;
  LOCKSTEP_Master_Out(1678) <= \<const0>\;
  LOCKSTEP_Master_Out(1679) <= \<const0>\;
  LOCKSTEP_Master_Out(1680) <= \<const0>\;
  LOCKSTEP_Master_Out(1681) <= \<const0>\;
  LOCKSTEP_Master_Out(1682) <= \<const0>\;
  LOCKSTEP_Master_Out(1683) <= \<const0>\;
  LOCKSTEP_Master_Out(1684) <= \<const0>\;
  LOCKSTEP_Master_Out(1685) <= \<const0>\;
  LOCKSTEP_Master_Out(1686) <= \<const0>\;
  LOCKSTEP_Master_Out(1687) <= \<const0>\;
  LOCKSTEP_Master_Out(1688) <= \<const0>\;
  LOCKSTEP_Master_Out(1689) <= \<const0>\;
  LOCKSTEP_Master_Out(1690) <= \<const0>\;
  LOCKSTEP_Master_Out(1691) <= \<const0>\;
  LOCKSTEP_Master_Out(1692) <= \<const0>\;
  LOCKSTEP_Master_Out(1693) <= \<const0>\;
  LOCKSTEP_Master_Out(1694) <= \<const0>\;
  LOCKSTEP_Master_Out(1695) <= \<const0>\;
  LOCKSTEP_Master_Out(1696) <= \<const0>\;
  LOCKSTEP_Master_Out(1697) <= \<const0>\;
  LOCKSTEP_Master_Out(1698) <= \<const0>\;
  LOCKSTEP_Master_Out(1699) <= \<const0>\;
  LOCKSTEP_Master_Out(1700) <= \<const0>\;
  LOCKSTEP_Master_Out(1701) <= \<const0>\;
  LOCKSTEP_Master_Out(1702) <= \<const0>\;
  LOCKSTEP_Master_Out(1703) <= \<const0>\;
  LOCKSTEP_Master_Out(1704) <= \<const0>\;
  LOCKSTEP_Master_Out(1705) <= \<const0>\;
  LOCKSTEP_Master_Out(1706) <= \<const0>\;
  LOCKSTEP_Master_Out(1707) <= \<const0>\;
  LOCKSTEP_Master_Out(1708) <= \<const0>\;
  LOCKSTEP_Master_Out(1709) <= \<const0>\;
  LOCKSTEP_Master_Out(1710) <= \<const0>\;
  LOCKSTEP_Master_Out(1711) <= \<const0>\;
  LOCKSTEP_Master_Out(1712) <= \<const0>\;
  LOCKSTEP_Master_Out(1713) <= \<const0>\;
  LOCKSTEP_Master_Out(1714) <= \<const0>\;
  LOCKSTEP_Master_Out(1715) <= \<const0>\;
  LOCKSTEP_Master_Out(1716) <= \<const0>\;
  LOCKSTEP_Master_Out(1717) <= \<const0>\;
  LOCKSTEP_Master_Out(1718) <= \<const0>\;
  LOCKSTEP_Master_Out(1719) <= \<const0>\;
  LOCKSTEP_Master_Out(1720) <= \<const0>\;
  LOCKSTEP_Master_Out(1721) <= \<const0>\;
  LOCKSTEP_Master_Out(1722) <= \<const0>\;
  LOCKSTEP_Master_Out(1723) <= \<const0>\;
  LOCKSTEP_Master_Out(1724) <= \<const0>\;
  LOCKSTEP_Master_Out(1725) <= \<const0>\;
  LOCKSTEP_Master_Out(1726) <= \<const0>\;
  LOCKSTEP_Master_Out(1727) <= \<const0>\;
  LOCKSTEP_Master_Out(1728) <= \<const0>\;
  LOCKSTEP_Master_Out(1729) <= \<const0>\;
  LOCKSTEP_Master_Out(1730) <= \<const0>\;
  LOCKSTEP_Master_Out(1731) <= \<const0>\;
  LOCKSTEP_Master_Out(1732) <= \<const0>\;
  LOCKSTEP_Master_Out(1733) <= \<const0>\;
  LOCKSTEP_Master_Out(1734) <= \<const0>\;
  LOCKSTEP_Master_Out(1735) <= \<const0>\;
  LOCKSTEP_Master_Out(1736) <= \<const0>\;
  LOCKSTEP_Master_Out(1737) <= \<const0>\;
  LOCKSTEP_Master_Out(1738) <= \<const0>\;
  LOCKSTEP_Master_Out(1739) <= \<const0>\;
  LOCKSTEP_Master_Out(1740) <= \<const0>\;
  LOCKSTEP_Master_Out(1741) <= \<const0>\;
  LOCKSTEP_Master_Out(1742) <= \<const0>\;
  LOCKSTEP_Master_Out(1743) <= \<const0>\;
  LOCKSTEP_Master_Out(1744) <= \<const0>\;
  LOCKSTEP_Master_Out(1745) <= \<const0>\;
  LOCKSTEP_Master_Out(1746) <= \<const0>\;
  LOCKSTEP_Master_Out(1747) <= \<const0>\;
  LOCKSTEP_Master_Out(1748) <= \<const0>\;
  LOCKSTEP_Master_Out(1749) <= \<const0>\;
  LOCKSTEP_Master_Out(1750) <= \<const0>\;
  LOCKSTEP_Master_Out(1751) <= \<const0>\;
  LOCKSTEP_Master_Out(1752) <= \<const0>\;
  LOCKSTEP_Master_Out(1753) <= \<const0>\;
  LOCKSTEP_Master_Out(1754) <= \<const0>\;
  LOCKSTEP_Master_Out(1755) <= \<const0>\;
  LOCKSTEP_Master_Out(1756) <= \<const0>\;
  LOCKSTEP_Master_Out(1757) <= \<const0>\;
  LOCKSTEP_Master_Out(1758) <= \<const0>\;
  LOCKSTEP_Master_Out(1759) <= \<const0>\;
  LOCKSTEP_Master_Out(1760) <= \<const0>\;
  LOCKSTEP_Master_Out(1761) <= \<const0>\;
  LOCKSTEP_Master_Out(1762) <= \<const0>\;
  LOCKSTEP_Master_Out(1763) <= \<const0>\;
  LOCKSTEP_Master_Out(1764) <= \<const0>\;
  LOCKSTEP_Master_Out(1765) <= \<const0>\;
  LOCKSTEP_Master_Out(1766) <= \<const0>\;
  LOCKSTEP_Master_Out(1767) <= \<const0>\;
  LOCKSTEP_Master_Out(1768) <= \<const0>\;
  LOCKSTEP_Master_Out(1769) <= \<const0>\;
  LOCKSTEP_Master_Out(1770) <= \<const0>\;
  LOCKSTEP_Master_Out(1771) <= \<const0>\;
  LOCKSTEP_Master_Out(1772) <= \<const0>\;
  LOCKSTEP_Master_Out(1773) <= \<const0>\;
  LOCKSTEP_Master_Out(1774) <= \<const0>\;
  LOCKSTEP_Master_Out(1775) <= \<const0>\;
  LOCKSTEP_Master_Out(1776) <= \<const0>\;
  LOCKSTEP_Master_Out(1777) <= \<const0>\;
  LOCKSTEP_Master_Out(1778) <= \<const0>\;
  LOCKSTEP_Master_Out(1779) <= \<const0>\;
  LOCKSTEP_Master_Out(1780) <= \<const0>\;
  LOCKSTEP_Master_Out(1781) <= \<const0>\;
  LOCKSTEP_Master_Out(1782) <= \<const0>\;
  LOCKSTEP_Master_Out(1783) <= \<const0>\;
  LOCKSTEP_Master_Out(1784) <= \<const0>\;
  LOCKSTEP_Master_Out(1785) <= \<const0>\;
  LOCKSTEP_Master_Out(1786) <= \<const0>\;
  LOCKSTEP_Master_Out(1787) <= \<const0>\;
  LOCKSTEP_Master_Out(1788) <= \<const0>\;
  LOCKSTEP_Master_Out(1789) <= \<const0>\;
  LOCKSTEP_Master_Out(1790) <= \<const0>\;
  LOCKSTEP_Master_Out(1791) <= \<const0>\;
  LOCKSTEP_Master_Out(1792) <= \<const0>\;
  LOCKSTEP_Master_Out(1793) <= \<const0>\;
  LOCKSTEP_Master_Out(1794) <= \<const0>\;
  LOCKSTEP_Master_Out(1795) <= \<const0>\;
  LOCKSTEP_Master_Out(1796) <= \<const0>\;
  LOCKSTEP_Master_Out(1797) <= \<const0>\;
  LOCKSTEP_Master_Out(1798) <= \<const0>\;
  LOCKSTEP_Master_Out(1799) <= \<const0>\;
  LOCKSTEP_Master_Out(1800) <= \<const0>\;
  LOCKSTEP_Master_Out(1801) <= \<const0>\;
  LOCKSTEP_Master_Out(1802) <= \<const0>\;
  LOCKSTEP_Master_Out(1803) <= \<const0>\;
  LOCKSTEP_Master_Out(1804) <= \<const0>\;
  LOCKSTEP_Master_Out(1805) <= \<const0>\;
  LOCKSTEP_Master_Out(1806) <= \<const0>\;
  LOCKSTEP_Master_Out(1807) <= \<const0>\;
  LOCKSTEP_Master_Out(1808) <= \<const0>\;
  LOCKSTEP_Master_Out(1809) <= \<const0>\;
  LOCKSTEP_Master_Out(1810) <= \<const0>\;
  LOCKSTEP_Master_Out(1811) <= \<const0>\;
  LOCKSTEP_Master_Out(1812) <= \<const0>\;
  LOCKSTEP_Master_Out(1813) <= \<const0>\;
  LOCKSTEP_Master_Out(1814) <= \<const0>\;
  LOCKSTEP_Master_Out(1815) <= \<const0>\;
  LOCKSTEP_Master_Out(1816) <= \<const0>\;
  LOCKSTEP_Master_Out(1817) <= \<const0>\;
  LOCKSTEP_Master_Out(1818) <= \<const0>\;
  LOCKSTEP_Master_Out(1819) <= \<const0>\;
  LOCKSTEP_Master_Out(1820) <= \<const0>\;
  LOCKSTEP_Master_Out(1821) <= \<const0>\;
  LOCKSTEP_Master_Out(1822) <= \<const0>\;
  LOCKSTEP_Master_Out(1823) <= \<const0>\;
  LOCKSTEP_Master_Out(1824) <= \<const0>\;
  LOCKSTEP_Master_Out(1825) <= \<const0>\;
  LOCKSTEP_Master_Out(1826) <= \<const0>\;
  LOCKSTEP_Master_Out(1827) <= \<const0>\;
  LOCKSTEP_Master_Out(1828) <= \<const0>\;
  LOCKSTEP_Master_Out(1829) <= \<const0>\;
  LOCKSTEP_Master_Out(1830) <= \<const0>\;
  LOCKSTEP_Master_Out(1831) <= \<const0>\;
  LOCKSTEP_Master_Out(1832) <= \<const0>\;
  LOCKSTEP_Master_Out(1833) <= \<const0>\;
  LOCKSTEP_Master_Out(1834) <= \<const0>\;
  LOCKSTEP_Master_Out(1835) <= \<const0>\;
  LOCKSTEP_Master_Out(1836) <= \<const0>\;
  LOCKSTEP_Master_Out(1837) <= \<const0>\;
  LOCKSTEP_Master_Out(1838) <= \<const0>\;
  LOCKSTEP_Master_Out(1839) <= \<const0>\;
  LOCKSTEP_Master_Out(1840) <= \<const0>\;
  LOCKSTEP_Master_Out(1841) <= \<const0>\;
  LOCKSTEP_Master_Out(1842) <= \<const0>\;
  LOCKSTEP_Master_Out(1843) <= \<const0>\;
  LOCKSTEP_Master_Out(1844) <= \<const0>\;
  LOCKSTEP_Master_Out(1845) <= \<const0>\;
  LOCKSTEP_Master_Out(1846) <= \<const0>\;
  LOCKSTEP_Master_Out(1847) <= \<const0>\;
  LOCKSTEP_Master_Out(1848) <= \<const0>\;
  LOCKSTEP_Master_Out(1849) <= \<const0>\;
  LOCKSTEP_Master_Out(1850) <= \<const0>\;
  LOCKSTEP_Master_Out(1851) <= \<const0>\;
  LOCKSTEP_Master_Out(1852) <= \<const0>\;
  LOCKSTEP_Master_Out(1853) <= \<const0>\;
  LOCKSTEP_Master_Out(1854) <= \<const0>\;
  LOCKSTEP_Master_Out(1855) <= \<const0>\;
  LOCKSTEP_Master_Out(1856) <= \<const0>\;
  LOCKSTEP_Master_Out(1857) <= \<const0>\;
  LOCKSTEP_Master_Out(1858) <= \<const0>\;
  LOCKSTEP_Master_Out(1859) <= \<const0>\;
  LOCKSTEP_Master_Out(1860) <= \<const0>\;
  LOCKSTEP_Master_Out(1861) <= \<const0>\;
  LOCKSTEP_Master_Out(1862) <= \<const0>\;
  LOCKSTEP_Master_Out(1863) <= \<const0>\;
  LOCKSTEP_Master_Out(1864) <= \<const0>\;
  LOCKSTEP_Master_Out(1865) <= \<const0>\;
  LOCKSTEP_Master_Out(1866) <= \<const0>\;
  LOCKSTEP_Master_Out(1867) <= \<const0>\;
  LOCKSTEP_Master_Out(1868) <= \<const0>\;
  LOCKSTEP_Master_Out(1869) <= \<const0>\;
  LOCKSTEP_Master_Out(1870) <= \<const0>\;
  LOCKSTEP_Master_Out(1871) <= \<const0>\;
  LOCKSTEP_Master_Out(1872) <= \<const0>\;
  LOCKSTEP_Master_Out(1873) <= \<const0>\;
  LOCKSTEP_Master_Out(1874) <= \<const0>\;
  LOCKSTEP_Master_Out(1875) <= \<const0>\;
  LOCKSTEP_Master_Out(1876) <= \<const0>\;
  LOCKSTEP_Master_Out(1877) <= \<const0>\;
  LOCKSTEP_Master_Out(1878) <= \<const0>\;
  LOCKSTEP_Master_Out(1879) <= \<const0>\;
  LOCKSTEP_Master_Out(1880) <= \<const0>\;
  LOCKSTEP_Master_Out(1881) <= \<const0>\;
  LOCKSTEP_Master_Out(1882) <= \<const0>\;
  LOCKSTEP_Master_Out(1883) <= \<const0>\;
  LOCKSTEP_Master_Out(1884) <= \<const0>\;
  LOCKSTEP_Master_Out(1885) <= \<const0>\;
  LOCKSTEP_Master_Out(1886) <= \<const0>\;
  LOCKSTEP_Master_Out(1887) <= \<const0>\;
  LOCKSTEP_Master_Out(1888) <= \<const0>\;
  LOCKSTEP_Master_Out(1889) <= \<const0>\;
  LOCKSTEP_Master_Out(1890) <= \<const0>\;
  LOCKSTEP_Master_Out(1891) <= \<const0>\;
  LOCKSTEP_Master_Out(1892) <= \<const0>\;
  LOCKSTEP_Master_Out(1893) <= \<const0>\;
  LOCKSTEP_Master_Out(1894) <= \<const0>\;
  LOCKSTEP_Master_Out(1895) <= \<const0>\;
  LOCKSTEP_Master_Out(1896) <= \<const0>\;
  LOCKSTEP_Master_Out(1897) <= \<const0>\;
  LOCKSTEP_Master_Out(1898) <= \<const0>\;
  LOCKSTEP_Master_Out(1899) <= \<const0>\;
  LOCKSTEP_Master_Out(1900) <= \<const0>\;
  LOCKSTEP_Master_Out(1901) <= \<const0>\;
  LOCKSTEP_Master_Out(1902) <= \<const0>\;
  LOCKSTEP_Master_Out(1903) <= \<const0>\;
  LOCKSTEP_Master_Out(1904) <= \<const0>\;
  LOCKSTEP_Master_Out(1905) <= \<const0>\;
  LOCKSTEP_Master_Out(1906) <= \<const0>\;
  LOCKSTEP_Master_Out(1907) <= \<const0>\;
  LOCKSTEP_Master_Out(1908) <= \<const0>\;
  LOCKSTEP_Master_Out(1909) <= \<const0>\;
  LOCKSTEP_Master_Out(1910) <= \<const0>\;
  LOCKSTEP_Master_Out(1911) <= \<const0>\;
  LOCKSTEP_Master_Out(1912) <= \<const0>\;
  LOCKSTEP_Master_Out(1913) <= \<const0>\;
  LOCKSTEP_Master_Out(1914) <= \<const0>\;
  LOCKSTEP_Master_Out(1915) <= \<const0>\;
  LOCKSTEP_Master_Out(1916) <= \<const0>\;
  LOCKSTEP_Master_Out(1917) <= \<const0>\;
  LOCKSTEP_Master_Out(1918) <= \<const0>\;
  LOCKSTEP_Master_Out(1919) <= \<const0>\;
  LOCKSTEP_Master_Out(1920) <= \<const0>\;
  LOCKSTEP_Master_Out(1921) <= \<const0>\;
  LOCKSTEP_Master_Out(1922) <= \<const0>\;
  LOCKSTEP_Master_Out(1923) <= \<const0>\;
  LOCKSTEP_Master_Out(1924) <= \<const0>\;
  LOCKSTEP_Master_Out(1925) <= \<const0>\;
  LOCKSTEP_Master_Out(1926) <= \<const0>\;
  LOCKSTEP_Master_Out(1927) <= \<const0>\;
  LOCKSTEP_Master_Out(1928) <= \<const0>\;
  LOCKSTEP_Master_Out(1929) <= \<const0>\;
  LOCKSTEP_Master_Out(1930) <= \<const0>\;
  LOCKSTEP_Master_Out(1931) <= \<const0>\;
  LOCKSTEP_Master_Out(1932) <= \<const0>\;
  LOCKSTEP_Master_Out(1933) <= \<const0>\;
  LOCKSTEP_Master_Out(1934) <= \<const0>\;
  LOCKSTEP_Master_Out(1935) <= \<const0>\;
  LOCKSTEP_Master_Out(1936) <= \<const0>\;
  LOCKSTEP_Master_Out(1937) <= \<const0>\;
  LOCKSTEP_Master_Out(1938) <= \<const0>\;
  LOCKSTEP_Master_Out(1939) <= \<const0>\;
  LOCKSTEP_Master_Out(1940) <= \<const0>\;
  LOCKSTEP_Master_Out(1941) <= \<const0>\;
  LOCKSTEP_Master_Out(1942) <= \<const0>\;
  LOCKSTEP_Master_Out(1943) <= \<const0>\;
  LOCKSTEP_Master_Out(1944) <= \<const0>\;
  LOCKSTEP_Master_Out(1945) <= \<const0>\;
  LOCKSTEP_Master_Out(1946) <= \<const0>\;
  LOCKSTEP_Master_Out(1947) <= \<const0>\;
  LOCKSTEP_Master_Out(1948) <= \<const0>\;
  LOCKSTEP_Master_Out(1949) <= \<const0>\;
  LOCKSTEP_Master_Out(1950) <= \<const0>\;
  LOCKSTEP_Master_Out(1951) <= \<const0>\;
  LOCKSTEP_Master_Out(1952) <= \<const0>\;
  LOCKSTEP_Master_Out(1953) <= \<const0>\;
  LOCKSTEP_Master_Out(1954) <= \<const0>\;
  LOCKSTEP_Master_Out(1955) <= \<const0>\;
  LOCKSTEP_Master_Out(1956) <= \<const0>\;
  LOCKSTEP_Master_Out(1957) <= \<const0>\;
  LOCKSTEP_Master_Out(1958) <= \<const0>\;
  LOCKSTEP_Master_Out(1959) <= \<const0>\;
  LOCKSTEP_Master_Out(1960) <= \<const0>\;
  LOCKSTEP_Master_Out(1961) <= \<const0>\;
  LOCKSTEP_Master_Out(1962) <= \<const0>\;
  LOCKSTEP_Master_Out(1963) <= \<const0>\;
  LOCKSTEP_Master_Out(1964) <= \<const0>\;
  LOCKSTEP_Master_Out(1965) <= \<const0>\;
  LOCKSTEP_Master_Out(1966) <= \<const0>\;
  LOCKSTEP_Master_Out(1967) <= \<const0>\;
  LOCKSTEP_Master_Out(1968) <= \<const0>\;
  LOCKSTEP_Master_Out(1969) <= \<const0>\;
  LOCKSTEP_Master_Out(1970) <= \<const0>\;
  LOCKSTEP_Master_Out(1971) <= \<const0>\;
  LOCKSTEP_Master_Out(1972) <= \<const0>\;
  LOCKSTEP_Master_Out(1973) <= \<const0>\;
  LOCKSTEP_Master_Out(1974) <= \<const0>\;
  LOCKSTEP_Master_Out(1975) <= \<const0>\;
  LOCKSTEP_Master_Out(1976) <= \<const0>\;
  LOCKSTEP_Master_Out(1977) <= \<const0>\;
  LOCKSTEP_Master_Out(1978) <= \<const0>\;
  LOCKSTEP_Master_Out(1979) <= \<const0>\;
  LOCKSTEP_Master_Out(1980) <= \<const0>\;
  LOCKSTEP_Master_Out(1981) <= \<const0>\;
  LOCKSTEP_Master_Out(1982) <= \<const0>\;
  LOCKSTEP_Master_Out(1983) <= \<const0>\;
  LOCKSTEP_Master_Out(1984) <= \<const0>\;
  LOCKSTEP_Master_Out(1985) <= \<const0>\;
  LOCKSTEP_Master_Out(1986) <= \<const0>\;
  LOCKSTEP_Master_Out(1987) <= \<const0>\;
  LOCKSTEP_Master_Out(1988) <= \<const0>\;
  LOCKSTEP_Master_Out(1989) <= \<const0>\;
  LOCKSTEP_Master_Out(1990) <= \<const0>\;
  LOCKSTEP_Master_Out(1991) <= \<const0>\;
  LOCKSTEP_Master_Out(1992) <= \<const0>\;
  LOCKSTEP_Master_Out(1993) <= \<const0>\;
  LOCKSTEP_Master_Out(1994) <= \<const0>\;
  LOCKSTEP_Master_Out(1995) <= \<const0>\;
  LOCKSTEP_Master_Out(1996) <= \<const0>\;
  LOCKSTEP_Master_Out(1997) <= \<const0>\;
  LOCKSTEP_Master_Out(1998) <= \<const0>\;
  LOCKSTEP_Master_Out(1999) <= \<const0>\;
  LOCKSTEP_Master_Out(2000) <= \<const0>\;
  LOCKSTEP_Master_Out(2001) <= \<const0>\;
  LOCKSTEP_Master_Out(2002) <= \<const0>\;
  LOCKSTEP_Master_Out(2003) <= \<const0>\;
  LOCKSTEP_Master_Out(2004) <= \<const0>\;
  LOCKSTEP_Master_Out(2005) <= \<const0>\;
  LOCKSTEP_Master_Out(2006) <= \<const0>\;
  LOCKSTEP_Master_Out(2007) <= \<const0>\;
  LOCKSTEP_Master_Out(2008) <= \<const0>\;
  LOCKSTEP_Master_Out(2009) <= \<const0>\;
  LOCKSTEP_Master_Out(2010) <= \<const0>\;
  LOCKSTEP_Master_Out(2011) <= \<const0>\;
  LOCKSTEP_Master_Out(2012) <= \<const0>\;
  LOCKSTEP_Master_Out(2013) <= \<const0>\;
  LOCKSTEP_Master_Out(2014) <= \<const0>\;
  LOCKSTEP_Master_Out(2015) <= \<const0>\;
  LOCKSTEP_Master_Out(2016) <= \<const0>\;
  LOCKSTEP_Master_Out(2017) <= \<const0>\;
  LOCKSTEP_Master_Out(2018) <= \<const0>\;
  LOCKSTEP_Master_Out(2019) <= \<const0>\;
  LOCKSTEP_Master_Out(2020) <= \<const0>\;
  LOCKSTEP_Master_Out(2021) <= \<const0>\;
  LOCKSTEP_Master_Out(2022) <= \<const0>\;
  LOCKSTEP_Master_Out(2023) <= \<const0>\;
  LOCKSTEP_Master_Out(2024) <= \<const0>\;
  LOCKSTEP_Master_Out(2025) <= \<const0>\;
  LOCKSTEP_Master_Out(2026) <= \<const0>\;
  LOCKSTEP_Master_Out(2027) <= \<const0>\;
  LOCKSTEP_Master_Out(2028) <= \<const0>\;
  LOCKSTEP_Master_Out(2029) <= \<const0>\;
  LOCKSTEP_Master_Out(2030) <= \<const0>\;
  LOCKSTEP_Master_Out(2031) <= \<const0>\;
  LOCKSTEP_Master_Out(2032) <= \<const0>\;
  LOCKSTEP_Master_Out(2033) <= \<const0>\;
  LOCKSTEP_Master_Out(2034) <= \<const0>\;
  LOCKSTEP_Master_Out(2035) <= \<const0>\;
  LOCKSTEP_Master_Out(2036) <= \<const0>\;
  LOCKSTEP_Master_Out(2037) <= \<const0>\;
  LOCKSTEP_Master_Out(2038) <= \<const0>\;
  LOCKSTEP_Master_Out(2039) <= \<const0>\;
  LOCKSTEP_Master_Out(2040) <= \<const0>\;
  LOCKSTEP_Master_Out(2041) <= \<const0>\;
  LOCKSTEP_Master_Out(2042) <= \<const0>\;
  LOCKSTEP_Master_Out(2043) <= \<const0>\;
  LOCKSTEP_Master_Out(2044) <= \<const0>\;
  LOCKSTEP_Master_Out(2045) <= \<const0>\;
  LOCKSTEP_Master_Out(2046) <= \<const0>\;
  LOCKSTEP_Master_Out(2047) <= \<const0>\;
  LOCKSTEP_Master_Out(2048) <= \<const0>\;
  LOCKSTEP_Master_Out(2049) <= \<const0>\;
  LOCKSTEP_Master_Out(2050) <= \<const0>\;
  LOCKSTEP_Master_Out(2051) <= \<const0>\;
  LOCKSTEP_Master_Out(2052) <= \<const0>\;
  LOCKSTEP_Master_Out(2053) <= \<const0>\;
  LOCKSTEP_Master_Out(2054) <= \<const0>\;
  LOCKSTEP_Master_Out(2055) <= \<const0>\;
  LOCKSTEP_Master_Out(2056) <= \<const0>\;
  LOCKSTEP_Master_Out(2057) <= \<const0>\;
  LOCKSTEP_Master_Out(2058) <= \<const0>\;
  LOCKSTEP_Master_Out(2059) <= \<const0>\;
  LOCKSTEP_Master_Out(2060) <= \<const0>\;
  LOCKSTEP_Master_Out(2061) <= \<const0>\;
  LOCKSTEP_Master_Out(2062) <= \<const0>\;
  LOCKSTEP_Master_Out(2063) <= \<const0>\;
  LOCKSTEP_Master_Out(2064) <= \<const0>\;
  LOCKSTEP_Master_Out(2065) <= \<const0>\;
  LOCKSTEP_Master_Out(2066) <= \<const0>\;
  LOCKSTEP_Master_Out(2067) <= \<const0>\;
  LOCKSTEP_Master_Out(2068) <= \<const0>\;
  LOCKSTEP_Master_Out(2069) <= \<const0>\;
  LOCKSTEP_Master_Out(2070) <= \<const0>\;
  LOCKSTEP_Master_Out(2071) <= \<const0>\;
  LOCKSTEP_Master_Out(2072) <= \<const0>\;
  LOCKSTEP_Master_Out(2073) <= \<const0>\;
  LOCKSTEP_Master_Out(2074) <= \<const0>\;
  LOCKSTEP_Master_Out(2075) <= \<const0>\;
  LOCKSTEP_Master_Out(2076) <= \<const0>\;
  LOCKSTEP_Master_Out(2077) <= \<const0>\;
  LOCKSTEP_Master_Out(2078) <= \<const0>\;
  LOCKSTEP_Master_Out(2079) <= \<const0>\;
  LOCKSTEP_Master_Out(2080) <= \<const0>\;
  LOCKSTEP_Master_Out(2081) <= \<const0>\;
  LOCKSTEP_Master_Out(2082) <= \<const0>\;
  LOCKSTEP_Master_Out(2083) <= \<const0>\;
  LOCKSTEP_Master_Out(2084) <= \<const0>\;
  LOCKSTEP_Master_Out(2085) <= \<const0>\;
  LOCKSTEP_Master_Out(2086) <= \<const0>\;
  LOCKSTEP_Master_Out(2087) <= \<const0>\;
  LOCKSTEP_Master_Out(2088) <= \<const0>\;
  LOCKSTEP_Master_Out(2089) <= \<const0>\;
  LOCKSTEP_Master_Out(2090) <= \<const0>\;
  LOCKSTEP_Master_Out(2091) <= \<const0>\;
  LOCKSTEP_Master_Out(2092) <= \<const0>\;
  LOCKSTEP_Master_Out(2093) <= \<const0>\;
  LOCKSTEP_Master_Out(2094) <= \<const0>\;
  LOCKSTEP_Master_Out(2095) <= \<const0>\;
  LOCKSTEP_Master_Out(2096) <= \<const0>\;
  LOCKSTEP_Master_Out(2097) <= \<const0>\;
  LOCKSTEP_Master_Out(2098) <= \<const0>\;
  LOCKSTEP_Master_Out(2099) <= \<const0>\;
  LOCKSTEP_Master_Out(2100) <= \<const0>\;
  LOCKSTEP_Master_Out(2101) <= \<const0>\;
  LOCKSTEP_Master_Out(2102) <= \<const0>\;
  LOCKSTEP_Master_Out(2103) <= \<const0>\;
  LOCKSTEP_Master_Out(2104) <= \<const0>\;
  LOCKSTEP_Master_Out(2105) <= \<const0>\;
  LOCKSTEP_Master_Out(2106) <= \<const0>\;
  LOCKSTEP_Master_Out(2107) <= \<const0>\;
  LOCKSTEP_Master_Out(2108) <= \<const0>\;
  LOCKSTEP_Master_Out(2109) <= \<const0>\;
  LOCKSTEP_Master_Out(2110) <= \<const0>\;
  LOCKSTEP_Master_Out(2111) <= \<const0>\;
  LOCKSTEP_Master_Out(2112) <= \<const0>\;
  LOCKSTEP_Master_Out(2113) <= \<const0>\;
  LOCKSTEP_Master_Out(2114) <= \<const0>\;
  LOCKSTEP_Master_Out(2115) <= \<const0>\;
  LOCKSTEP_Master_Out(2116) <= \<const0>\;
  LOCKSTEP_Master_Out(2117) <= \<const0>\;
  LOCKSTEP_Master_Out(2118) <= \<const0>\;
  LOCKSTEP_Master_Out(2119) <= \<const0>\;
  LOCKSTEP_Master_Out(2120) <= \<const0>\;
  LOCKSTEP_Master_Out(2121) <= \<const0>\;
  LOCKSTEP_Master_Out(2122) <= \<const0>\;
  LOCKSTEP_Master_Out(2123) <= \<const0>\;
  LOCKSTEP_Master_Out(2124) <= \<const0>\;
  LOCKSTEP_Master_Out(2125) <= \<const0>\;
  LOCKSTEP_Master_Out(2126) <= \<const0>\;
  LOCKSTEP_Master_Out(2127) <= \<const0>\;
  LOCKSTEP_Master_Out(2128) <= \<const0>\;
  LOCKSTEP_Master_Out(2129) <= \<const0>\;
  LOCKSTEP_Master_Out(2130) <= \<const0>\;
  LOCKSTEP_Master_Out(2131) <= \<const0>\;
  LOCKSTEP_Master_Out(2132) <= \<const0>\;
  LOCKSTEP_Master_Out(2133) <= \<const0>\;
  LOCKSTEP_Master_Out(2134) <= \<const0>\;
  LOCKSTEP_Master_Out(2135) <= \<const0>\;
  LOCKSTEP_Master_Out(2136) <= \<const0>\;
  LOCKSTEP_Master_Out(2137) <= \<const0>\;
  LOCKSTEP_Master_Out(2138) <= \<const0>\;
  LOCKSTEP_Master_Out(2139) <= \<const0>\;
  LOCKSTEP_Master_Out(2140) <= \<const0>\;
  LOCKSTEP_Master_Out(2141) <= \<const0>\;
  LOCKSTEP_Master_Out(2142) <= \<const0>\;
  LOCKSTEP_Master_Out(2143) <= \<const0>\;
  LOCKSTEP_Master_Out(2144) <= \<const0>\;
  LOCKSTEP_Master_Out(2145) <= \<const0>\;
  LOCKSTEP_Master_Out(2146) <= \<const0>\;
  LOCKSTEP_Master_Out(2147) <= \<const0>\;
  LOCKSTEP_Master_Out(2148) <= \<const0>\;
  LOCKSTEP_Master_Out(2149) <= \<const0>\;
  LOCKSTEP_Master_Out(2150) <= \<const0>\;
  LOCKSTEP_Master_Out(2151) <= \<const0>\;
  LOCKSTEP_Master_Out(2152) <= \<const0>\;
  LOCKSTEP_Master_Out(2153) <= \<const0>\;
  LOCKSTEP_Master_Out(2154) <= \<const0>\;
  LOCKSTEP_Master_Out(2155) <= \<const0>\;
  LOCKSTEP_Master_Out(2156) <= \<const0>\;
  LOCKSTEP_Master_Out(2157) <= \<const0>\;
  LOCKSTEP_Master_Out(2158) <= \<const0>\;
  LOCKSTEP_Master_Out(2159) <= \<const0>\;
  LOCKSTEP_Master_Out(2160) <= \<const0>\;
  LOCKSTEP_Master_Out(2161) <= \<const0>\;
  LOCKSTEP_Master_Out(2162) <= \<const0>\;
  LOCKSTEP_Master_Out(2163) <= \<const0>\;
  LOCKSTEP_Master_Out(2164) <= \<const0>\;
  LOCKSTEP_Master_Out(2165) <= \<const0>\;
  LOCKSTEP_Master_Out(2166) <= \<const0>\;
  LOCKSTEP_Master_Out(2167) <= \<const0>\;
  LOCKSTEP_Master_Out(2168) <= \<const0>\;
  LOCKSTEP_Master_Out(2169) <= \<const0>\;
  LOCKSTEP_Master_Out(2170) <= \<const0>\;
  LOCKSTEP_Master_Out(2171) <= \<const0>\;
  LOCKSTEP_Master_Out(2172) <= \<const0>\;
  LOCKSTEP_Master_Out(2173) <= \<const0>\;
  LOCKSTEP_Master_Out(2174) <= \<const0>\;
  LOCKSTEP_Master_Out(2175) <= \<const0>\;
  LOCKSTEP_Master_Out(2176) <= \<const0>\;
  LOCKSTEP_Master_Out(2177) <= \<const0>\;
  LOCKSTEP_Master_Out(2178) <= \<const0>\;
  LOCKSTEP_Master_Out(2179) <= \<const0>\;
  LOCKSTEP_Master_Out(2180) <= \<const0>\;
  LOCKSTEP_Master_Out(2181) <= \<const0>\;
  LOCKSTEP_Master_Out(2182) <= \<const0>\;
  LOCKSTEP_Master_Out(2183) <= \<const0>\;
  LOCKSTEP_Master_Out(2184) <= \<const0>\;
  LOCKSTEP_Master_Out(2185) <= \<const0>\;
  LOCKSTEP_Master_Out(2186) <= \<const0>\;
  LOCKSTEP_Master_Out(2187) <= \<const0>\;
  LOCKSTEP_Master_Out(2188) <= \<const0>\;
  LOCKSTEP_Master_Out(2189) <= \<const0>\;
  LOCKSTEP_Master_Out(2190) <= \<const0>\;
  LOCKSTEP_Master_Out(2191) <= \<const0>\;
  LOCKSTEP_Master_Out(2192) <= \<const0>\;
  LOCKSTEP_Master_Out(2193) <= \<const0>\;
  LOCKSTEP_Master_Out(2194) <= \<const0>\;
  LOCKSTEP_Master_Out(2195) <= \<const0>\;
  LOCKSTEP_Master_Out(2196) <= \<const0>\;
  LOCKSTEP_Master_Out(2197) <= \<const0>\;
  LOCKSTEP_Master_Out(2198) <= \<const0>\;
  LOCKSTEP_Master_Out(2199) <= \<const0>\;
  LOCKSTEP_Master_Out(2200) <= \<const0>\;
  LOCKSTEP_Master_Out(2201) <= \<const0>\;
  LOCKSTEP_Master_Out(2202) <= \<const0>\;
  LOCKSTEP_Master_Out(2203) <= \<const0>\;
  LOCKSTEP_Master_Out(2204) <= \<const0>\;
  LOCKSTEP_Master_Out(2205) <= \<const0>\;
  LOCKSTEP_Master_Out(2206) <= \<const0>\;
  LOCKSTEP_Master_Out(2207) <= \<const0>\;
  LOCKSTEP_Master_Out(2208) <= \<const0>\;
  LOCKSTEP_Master_Out(2209) <= \<const0>\;
  LOCKSTEP_Master_Out(2210) <= \<const0>\;
  LOCKSTEP_Master_Out(2211) <= \<const0>\;
  LOCKSTEP_Master_Out(2212) <= \<const0>\;
  LOCKSTEP_Master_Out(2213) <= \<const0>\;
  LOCKSTEP_Master_Out(2214) <= \<const0>\;
  LOCKSTEP_Master_Out(2215) <= \<const0>\;
  LOCKSTEP_Master_Out(2216) <= \<const0>\;
  LOCKSTEP_Master_Out(2217) <= \<const0>\;
  LOCKSTEP_Master_Out(2218) <= \<const0>\;
  LOCKSTEP_Master_Out(2219) <= \<const0>\;
  LOCKSTEP_Master_Out(2220) <= \<const0>\;
  LOCKSTEP_Master_Out(2221) <= \<const0>\;
  LOCKSTEP_Master_Out(2222) <= \<const0>\;
  LOCKSTEP_Master_Out(2223) <= \<const0>\;
  LOCKSTEP_Master_Out(2224) <= \<const0>\;
  LOCKSTEP_Master_Out(2225) <= \<const0>\;
  LOCKSTEP_Master_Out(2226) <= \<const0>\;
  LOCKSTEP_Master_Out(2227) <= \<const0>\;
  LOCKSTEP_Master_Out(2228) <= \<const0>\;
  LOCKSTEP_Master_Out(2229) <= \<const0>\;
  LOCKSTEP_Master_Out(2230) <= \<const0>\;
  LOCKSTEP_Master_Out(2231) <= \<const0>\;
  LOCKSTEP_Master_Out(2232) <= \<const0>\;
  LOCKSTEP_Master_Out(2233) <= \<const0>\;
  LOCKSTEP_Master_Out(2234) <= \<const0>\;
  LOCKSTEP_Master_Out(2235) <= \<const0>\;
  LOCKSTEP_Master_Out(2236) <= \<const0>\;
  LOCKSTEP_Master_Out(2237) <= \<const0>\;
  LOCKSTEP_Master_Out(2238) <= \<const0>\;
  LOCKSTEP_Master_Out(2239) <= \<const0>\;
  LOCKSTEP_Master_Out(2240) <= \<const0>\;
  LOCKSTEP_Master_Out(2241) <= \<const0>\;
  LOCKSTEP_Master_Out(2242) <= \<const0>\;
  LOCKSTEP_Master_Out(2243) <= \<const0>\;
  LOCKSTEP_Master_Out(2244) <= \<const0>\;
  LOCKSTEP_Master_Out(2245) <= \<const0>\;
  LOCKSTEP_Master_Out(2246) <= \<const0>\;
  LOCKSTEP_Master_Out(2247) <= \<const0>\;
  LOCKSTEP_Master_Out(2248) <= \<const0>\;
  LOCKSTEP_Master_Out(2249) <= \<const0>\;
  LOCKSTEP_Master_Out(2250) <= \<const0>\;
  LOCKSTEP_Master_Out(2251) <= \<const0>\;
  LOCKSTEP_Master_Out(2252) <= \<const0>\;
  LOCKSTEP_Master_Out(2253) <= \<const0>\;
  LOCKSTEP_Master_Out(2254) <= \<const0>\;
  LOCKSTEP_Master_Out(2255) <= \<const0>\;
  LOCKSTEP_Master_Out(2256) <= \<const0>\;
  LOCKSTEP_Master_Out(2257) <= \<const0>\;
  LOCKSTEP_Master_Out(2258) <= \<const0>\;
  LOCKSTEP_Master_Out(2259) <= \<const0>\;
  LOCKSTEP_Master_Out(2260) <= \<const0>\;
  LOCKSTEP_Master_Out(2261) <= \<const0>\;
  LOCKSTEP_Master_Out(2262) <= \<const0>\;
  LOCKSTEP_Master_Out(2263) <= \<const0>\;
  LOCKSTEP_Master_Out(2264) <= \<const0>\;
  LOCKSTEP_Master_Out(2265) <= \<const0>\;
  LOCKSTEP_Master_Out(2266) <= \<const0>\;
  LOCKSTEP_Master_Out(2267) <= \<const0>\;
  LOCKSTEP_Master_Out(2268) <= \<const0>\;
  LOCKSTEP_Master_Out(2269) <= \<const0>\;
  LOCKSTEP_Master_Out(2270) <= \<const0>\;
  LOCKSTEP_Master_Out(2271) <= \<const0>\;
  LOCKSTEP_Master_Out(2272) <= \<const0>\;
  LOCKSTEP_Master_Out(2273) <= \<const0>\;
  LOCKSTEP_Master_Out(2274) <= \<const0>\;
  LOCKSTEP_Master_Out(2275) <= \<const0>\;
  LOCKSTEP_Master_Out(2276) <= \<const0>\;
  LOCKSTEP_Master_Out(2277) <= \<const0>\;
  LOCKSTEP_Master_Out(2278) <= \<const0>\;
  LOCKSTEP_Master_Out(2279) <= \<const0>\;
  LOCKSTEP_Master_Out(2280) <= \<const0>\;
  LOCKSTEP_Master_Out(2281) <= \<const0>\;
  LOCKSTEP_Master_Out(2282) <= \<const0>\;
  LOCKSTEP_Master_Out(2283) <= \<const0>\;
  LOCKSTEP_Master_Out(2284) <= \<const0>\;
  LOCKSTEP_Master_Out(2285) <= \<const0>\;
  LOCKSTEP_Master_Out(2286) <= \<const0>\;
  LOCKSTEP_Master_Out(2287) <= \<const0>\;
  LOCKSTEP_Master_Out(2288) <= \<const0>\;
  LOCKSTEP_Master_Out(2289) <= \<const0>\;
  LOCKSTEP_Master_Out(2290) <= \<const0>\;
  LOCKSTEP_Master_Out(2291) <= \<const0>\;
  LOCKSTEP_Master_Out(2292) <= \<const0>\;
  LOCKSTEP_Master_Out(2293) <= \<const0>\;
  LOCKSTEP_Master_Out(2294) <= \<const0>\;
  LOCKSTEP_Master_Out(2295) <= \<const0>\;
  LOCKSTEP_Master_Out(2296) <= \<const0>\;
  LOCKSTEP_Master_Out(2297) <= \<const0>\;
  LOCKSTEP_Master_Out(2298) <= \<const0>\;
  LOCKSTEP_Master_Out(2299) <= \<const0>\;
  LOCKSTEP_Master_Out(2300) <= \<const0>\;
  LOCKSTEP_Master_Out(2301) <= \<const0>\;
  LOCKSTEP_Master_Out(2302) <= \<const0>\;
  LOCKSTEP_Master_Out(2303) <= \<const0>\;
  LOCKSTEP_Master_Out(2304) <= \<const0>\;
  LOCKSTEP_Master_Out(2305) <= \<const0>\;
  LOCKSTEP_Master_Out(2306) <= \<const0>\;
  LOCKSTEP_Master_Out(2307) <= \<const0>\;
  LOCKSTEP_Master_Out(2308) <= \<const0>\;
  LOCKSTEP_Master_Out(2309) <= \<const0>\;
  LOCKSTEP_Master_Out(2310) <= \<const0>\;
  LOCKSTEP_Master_Out(2311) <= \<const0>\;
  LOCKSTEP_Master_Out(2312) <= \<const0>\;
  LOCKSTEP_Master_Out(2313) <= \<const0>\;
  LOCKSTEP_Master_Out(2314) <= \<const0>\;
  LOCKSTEP_Master_Out(2315) <= \<const0>\;
  LOCKSTEP_Master_Out(2316) <= \<const0>\;
  LOCKSTEP_Master_Out(2317) <= \<const0>\;
  LOCKSTEP_Master_Out(2318) <= \<const0>\;
  LOCKSTEP_Master_Out(2319) <= \<const0>\;
  LOCKSTEP_Master_Out(2320) <= \<const0>\;
  LOCKSTEP_Master_Out(2321) <= \<const0>\;
  LOCKSTEP_Master_Out(2322) <= \<const0>\;
  LOCKSTEP_Master_Out(2323) <= \<const0>\;
  LOCKSTEP_Master_Out(2324) <= \<const0>\;
  LOCKSTEP_Master_Out(2325) <= \<const0>\;
  LOCKSTEP_Master_Out(2326) <= \<const0>\;
  LOCKSTEP_Master_Out(2327) <= \<const0>\;
  LOCKSTEP_Master_Out(2328) <= \<const0>\;
  LOCKSTEP_Master_Out(2329) <= \<const0>\;
  LOCKSTEP_Master_Out(2330) <= \<const0>\;
  LOCKSTEP_Master_Out(2331) <= \<const0>\;
  LOCKSTEP_Master_Out(2332) <= \<const0>\;
  LOCKSTEP_Master_Out(2333) <= \<const0>\;
  LOCKSTEP_Master_Out(2334) <= \<const0>\;
  LOCKSTEP_Master_Out(2335) <= \<const0>\;
  LOCKSTEP_Master_Out(2336) <= \<const0>\;
  LOCKSTEP_Master_Out(2337) <= \<const0>\;
  LOCKSTEP_Master_Out(2338) <= \<const0>\;
  LOCKSTEP_Master_Out(2339) <= \<const0>\;
  LOCKSTEP_Master_Out(2340) <= \<const0>\;
  LOCKSTEP_Master_Out(2341) <= \<const0>\;
  LOCKSTEP_Master_Out(2342) <= \<const0>\;
  LOCKSTEP_Master_Out(2343) <= \<const0>\;
  LOCKSTEP_Master_Out(2344) <= \<const0>\;
  LOCKSTEP_Master_Out(2345) <= \<const0>\;
  LOCKSTEP_Master_Out(2346) <= \<const0>\;
  LOCKSTEP_Master_Out(2347) <= \<const0>\;
  LOCKSTEP_Master_Out(2348) <= \<const0>\;
  LOCKSTEP_Master_Out(2349) <= \<const0>\;
  LOCKSTEP_Master_Out(2350) <= \<const0>\;
  LOCKSTEP_Master_Out(2351) <= \<const0>\;
  LOCKSTEP_Master_Out(2352) <= \<const0>\;
  LOCKSTEP_Master_Out(2353) <= \<const0>\;
  LOCKSTEP_Master_Out(2354) <= \<const0>\;
  LOCKSTEP_Master_Out(2355) <= \<const0>\;
  LOCKSTEP_Master_Out(2356) <= \<const0>\;
  LOCKSTEP_Master_Out(2357) <= \<const0>\;
  LOCKSTEP_Master_Out(2358) <= \<const0>\;
  LOCKSTEP_Master_Out(2359) <= \<const0>\;
  LOCKSTEP_Master_Out(2360) <= \<const0>\;
  LOCKSTEP_Master_Out(2361) <= \<const0>\;
  LOCKSTEP_Master_Out(2362) <= \<const0>\;
  LOCKSTEP_Master_Out(2363) <= \<const0>\;
  LOCKSTEP_Master_Out(2364) <= \<const0>\;
  LOCKSTEP_Master_Out(2365) <= \<const0>\;
  LOCKSTEP_Master_Out(2366) <= \<const0>\;
  LOCKSTEP_Master_Out(2367) <= \<const0>\;
  LOCKSTEP_Master_Out(2368) <= \<const0>\;
  LOCKSTEP_Master_Out(2369) <= \<const0>\;
  LOCKSTEP_Master_Out(2370) <= \<const0>\;
  LOCKSTEP_Master_Out(2371) <= \<const0>\;
  LOCKSTEP_Master_Out(2372) <= \<const0>\;
  LOCKSTEP_Master_Out(2373) <= \<const0>\;
  LOCKSTEP_Master_Out(2374) <= \<const0>\;
  LOCKSTEP_Master_Out(2375) <= \<const0>\;
  LOCKSTEP_Master_Out(2376) <= \<const0>\;
  LOCKSTEP_Master_Out(2377) <= \<const0>\;
  LOCKSTEP_Master_Out(2378) <= \<const0>\;
  LOCKSTEP_Master_Out(2379) <= \<const0>\;
  LOCKSTEP_Master_Out(2380) <= \<const0>\;
  LOCKSTEP_Master_Out(2381) <= \<const0>\;
  LOCKSTEP_Master_Out(2382) <= \<const0>\;
  LOCKSTEP_Master_Out(2383) <= \<const0>\;
  LOCKSTEP_Master_Out(2384) <= \<const0>\;
  LOCKSTEP_Master_Out(2385) <= \<const0>\;
  LOCKSTEP_Master_Out(2386) <= \<const0>\;
  LOCKSTEP_Master_Out(2387) <= \<const0>\;
  LOCKSTEP_Master_Out(2388) <= \<const0>\;
  LOCKSTEP_Master_Out(2389) <= \<const0>\;
  LOCKSTEP_Master_Out(2390) <= \<const0>\;
  LOCKSTEP_Master_Out(2391) <= \<const0>\;
  LOCKSTEP_Master_Out(2392) <= \<const0>\;
  LOCKSTEP_Master_Out(2393) <= \<const0>\;
  LOCKSTEP_Master_Out(2394) <= \<const0>\;
  LOCKSTEP_Master_Out(2395) <= \<const0>\;
  LOCKSTEP_Master_Out(2396) <= \<const0>\;
  LOCKSTEP_Master_Out(2397) <= \<const0>\;
  LOCKSTEP_Master_Out(2398) <= \<const0>\;
  LOCKSTEP_Master_Out(2399) <= \<const0>\;
  LOCKSTEP_Master_Out(2400) <= \<const0>\;
  LOCKSTEP_Master_Out(2401) <= \<const0>\;
  LOCKSTEP_Master_Out(2402) <= \<const0>\;
  LOCKSTEP_Master_Out(2403) <= \<const0>\;
  LOCKSTEP_Master_Out(2404) <= \<const0>\;
  LOCKSTEP_Master_Out(2405) <= \<const0>\;
  LOCKSTEP_Master_Out(2406) <= \<const0>\;
  LOCKSTEP_Master_Out(2407) <= \<const0>\;
  LOCKSTEP_Master_Out(2408) <= \<const0>\;
  LOCKSTEP_Master_Out(2409) <= \<const0>\;
  LOCKSTEP_Master_Out(2410) <= \<const0>\;
  LOCKSTEP_Master_Out(2411) <= \<const0>\;
  LOCKSTEP_Master_Out(2412) <= \<const0>\;
  LOCKSTEP_Master_Out(2413) <= \<const0>\;
  LOCKSTEP_Master_Out(2414) <= \<const0>\;
  LOCKSTEP_Master_Out(2415) <= \<const0>\;
  LOCKSTEP_Master_Out(2416) <= \<const0>\;
  LOCKSTEP_Master_Out(2417) <= \<const0>\;
  LOCKSTEP_Master_Out(2418) <= \<const0>\;
  LOCKSTEP_Master_Out(2419) <= \<const0>\;
  LOCKSTEP_Master_Out(2420) <= \<const0>\;
  LOCKSTEP_Master_Out(2421) <= \<const0>\;
  LOCKSTEP_Master_Out(2422) <= \<const0>\;
  LOCKSTEP_Master_Out(2423) <= \<const0>\;
  LOCKSTEP_Master_Out(2424) <= \<const0>\;
  LOCKSTEP_Master_Out(2425) <= \<const0>\;
  LOCKSTEP_Master_Out(2426) <= \<const0>\;
  LOCKSTEP_Master_Out(2427) <= \<const0>\;
  LOCKSTEP_Master_Out(2428) <= \<const0>\;
  LOCKSTEP_Master_Out(2429) <= \<const0>\;
  LOCKSTEP_Master_Out(2430) <= \<const0>\;
  LOCKSTEP_Master_Out(2431) <= \<const0>\;
  LOCKSTEP_Master_Out(2432) <= \<const0>\;
  LOCKSTEP_Master_Out(2433) <= \<const0>\;
  LOCKSTEP_Master_Out(2434) <= \<const0>\;
  LOCKSTEP_Master_Out(2435) <= \<const0>\;
  LOCKSTEP_Master_Out(2436) <= \<const0>\;
  LOCKSTEP_Master_Out(2437) <= \<const0>\;
  LOCKSTEP_Master_Out(2438) <= \<const0>\;
  LOCKSTEP_Master_Out(2439) <= \<const0>\;
  LOCKSTEP_Master_Out(2440) <= \<const0>\;
  LOCKSTEP_Master_Out(2441) <= \<const0>\;
  LOCKSTEP_Master_Out(2442) <= \<const0>\;
  LOCKSTEP_Master_Out(2443) <= \<const0>\;
  LOCKSTEP_Master_Out(2444) <= \<const0>\;
  LOCKSTEP_Master_Out(2445) <= \<const0>\;
  LOCKSTEP_Master_Out(2446) <= \<const0>\;
  LOCKSTEP_Master_Out(2447) <= \<const0>\;
  LOCKSTEP_Master_Out(2448) <= \<const0>\;
  LOCKSTEP_Master_Out(2449) <= \<const0>\;
  LOCKSTEP_Master_Out(2450) <= \<const0>\;
  LOCKSTEP_Master_Out(2451) <= \<const0>\;
  LOCKSTEP_Master_Out(2452) <= \<const0>\;
  LOCKSTEP_Master_Out(2453) <= \<const0>\;
  LOCKSTEP_Master_Out(2454) <= \<const0>\;
  LOCKSTEP_Master_Out(2455) <= \<const0>\;
  LOCKSTEP_Master_Out(2456) <= \<const0>\;
  LOCKSTEP_Master_Out(2457) <= \<const0>\;
  LOCKSTEP_Master_Out(2458) <= \<const0>\;
  LOCKSTEP_Master_Out(2459) <= \<const0>\;
  LOCKSTEP_Master_Out(2460) <= \<const0>\;
  LOCKSTEP_Master_Out(2461) <= \<const0>\;
  LOCKSTEP_Master_Out(2462) <= \<const0>\;
  LOCKSTEP_Master_Out(2463) <= \<const0>\;
  LOCKSTEP_Master_Out(2464) <= \<const0>\;
  LOCKSTEP_Master_Out(2465) <= \<const0>\;
  LOCKSTEP_Master_Out(2466) <= \<const0>\;
  LOCKSTEP_Master_Out(2467) <= \<const0>\;
  LOCKSTEP_Master_Out(2468) <= \<const0>\;
  LOCKSTEP_Master_Out(2469) <= \<const0>\;
  LOCKSTEP_Master_Out(2470) <= \<const0>\;
  LOCKSTEP_Master_Out(2471) <= \<const0>\;
  LOCKSTEP_Master_Out(2472) <= \<const0>\;
  LOCKSTEP_Master_Out(2473) <= \<const0>\;
  LOCKSTEP_Master_Out(2474) <= \<const0>\;
  LOCKSTEP_Master_Out(2475) <= \<const0>\;
  LOCKSTEP_Master_Out(2476) <= \<const0>\;
  LOCKSTEP_Master_Out(2477) <= \<const0>\;
  LOCKSTEP_Master_Out(2478) <= \<const0>\;
  LOCKSTEP_Master_Out(2479) <= \<const0>\;
  LOCKSTEP_Master_Out(2480) <= \<const0>\;
  LOCKSTEP_Master_Out(2481) <= \<const0>\;
  LOCKSTEP_Master_Out(2482) <= \<const0>\;
  LOCKSTEP_Master_Out(2483) <= \<const0>\;
  LOCKSTEP_Master_Out(2484) <= \<const0>\;
  LOCKSTEP_Master_Out(2485) <= \<const0>\;
  LOCKSTEP_Master_Out(2486) <= \<const0>\;
  LOCKSTEP_Master_Out(2487) <= \<const0>\;
  LOCKSTEP_Master_Out(2488) <= \<const0>\;
  LOCKSTEP_Master_Out(2489) <= \<const0>\;
  LOCKSTEP_Master_Out(2490) <= \<const0>\;
  LOCKSTEP_Master_Out(2491) <= \<const0>\;
  LOCKSTEP_Master_Out(2492) <= \<const0>\;
  LOCKSTEP_Master_Out(2493) <= \<const0>\;
  LOCKSTEP_Master_Out(2494) <= \<const0>\;
  LOCKSTEP_Master_Out(2495) <= \<const0>\;
  LOCKSTEP_Master_Out(2496) <= \<const0>\;
  LOCKSTEP_Master_Out(2497) <= \<const0>\;
  LOCKSTEP_Master_Out(2498) <= \<const0>\;
  LOCKSTEP_Master_Out(2499) <= \<const0>\;
  LOCKSTEP_Master_Out(2500) <= \<const0>\;
  LOCKSTEP_Master_Out(2501) <= \<const0>\;
  LOCKSTEP_Master_Out(2502) <= \<const0>\;
  LOCKSTEP_Master_Out(2503) <= \<const0>\;
  LOCKSTEP_Master_Out(2504) <= \<const0>\;
  LOCKSTEP_Master_Out(2505) <= \<const0>\;
  LOCKSTEP_Master_Out(2506) <= \<const0>\;
  LOCKSTEP_Master_Out(2507) <= \<const0>\;
  LOCKSTEP_Master_Out(2508) <= \<const0>\;
  LOCKSTEP_Master_Out(2509) <= \<const0>\;
  LOCKSTEP_Master_Out(2510) <= \<const0>\;
  LOCKSTEP_Master_Out(2511) <= \<const0>\;
  LOCKSTEP_Master_Out(2512) <= \<const0>\;
  LOCKSTEP_Master_Out(2513) <= \<const0>\;
  LOCKSTEP_Master_Out(2514) <= \<const0>\;
  LOCKSTEP_Master_Out(2515) <= \<const0>\;
  LOCKSTEP_Master_Out(2516) <= \<const0>\;
  LOCKSTEP_Master_Out(2517) <= \<const0>\;
  LOCKSTEP_Master_Out(2518) <= \<const0>\;
  LOCKSTEP_Master_Out(2519) <= \<const0>\;
  LOCKSTEP_Master_Out(2520) <= \<const0>\;
  LOCKSTEP_Master_Out(2521) <= \<const0>\;
  LOCKSTEP_Master_Out(2522) <= \<const0>\;
  LOCKSTEP_Master_Out(2523) <= \<const0>\;
  LOCKSTEP_Master_Out(2524) <= \<const0>\;
  LOCKSTEP_Master_Out(2525) <= \<const0>\;
  LOCKSTEP_Master_Out(2526) <= \<const0>\;
  LOCKSTEP_Master_Out(2527) <= \<const0>\;
  LOCKSTEP_Master_Out(2528) <= \<const0>\;
  LOCKSTEP_Master_Out(2529) <= \<const0>\;
  LOCKSTEP_Master_Out(2530) <= \<const0>\;
  LOCKSTEP_Master_Out(2531) <= \<const0>\;
  LOCKSTEP_Master_Out(2532) <= \<const0>\;
  LOCKSTEP_Master_Out(2533) <= \<const0>\;
  LOCKSTEP_Master_Out(2534) <= \<const0>\;
  LOCKSTEP_Master_Out(2535) <= \<const0>\;
  LOCKSTEP_Master_Out(2536) <= \<const0>\;
  LOCKSTEP_Master_Out(2537) <= \<const0>\;
  LOCKSTEP_Master_Out(2538) <= \<const0>\;
  LOCKSTEP_Master_Out(2539) <= \<const0>\;
  LOCKSTEP_Master_Out(2540) <= \<const0>\;
  LOCKSTEP_Master_Out(2541) <= \<const0>\;
  LOCKSTEP_Master_Out(2542) <= \<const0>\;
  LOCKSTEP_Master_Out(2543) <= \<const0>\;
  LOCKSTEP_Master_Out(2544) <= \<const0>\;
  LOCKSTEP_Master_Out(2545) <= \<const0>\;
  LOCKSTEP_Master_Out(2546) <= \<const0>\;
  LOCKSTEP_Master_Out(2547) <= \<const0>\;
  LOCKSTEP_Master_Out(2548) <= \<const0>\;
  LOCKSTEP_Master_Out(2549) <= \<const0>\;
  LOCKSTEP_Master_Out(2550) <= \<const0>\;
  LOCKSTEP_Master_Out(2551) <= \<const0>\;
  LOCKSTEP_Master_Out(2552) <= \<const0>\;
  LOCKSTEP_Master_Out(2553) <= \<const0>\;
  LOCKSTEP_Master_Out(2554) <= \<const0>\;
  LOCKSTEP_Master_Out(2555) <= \<const0>\;
  LOCKSTEP_Master_Out(2556) <= \<const0>\;
  LOCKSTEP_Master_Out(2557) <= \<const0>\;
  LOCKSTEP_Master_Out(2558) <= \<const0>\;
  LOCKSTEP_Master_Out(2559) <= \<const0>\;
  LOCKSTEP_Master_Out(2560) <= \<const0>\;
  LOCKSTEP_Master_Out(2561) <= \<const0>\;
  LOCKSTEP_Master_Out(2562) <= \<const0>\;
  LOCKSTEP_Master_Out(2563) <= \<const0>\;
  LOCKSTEP_Master_Out(2564) <= \<const0>\;
  LOCKSTEP_Master_Out(2565) <= \<const0>\;
  LOCKSTEP_Master_Out(2566) <= \<const0>\;
  LOCKSTEP_Master_Out(2567) <= \<const0>\;
  LOCKSTEP_Master_Out(2568) <= \<const0>\;
  LOCKSTEP_Master_Out(2569) <= \<const0>\;
  LOCKSTEP_Master_Out(2570) <= \<const0>\;
  LOCKSTEP_Master_Out(2571) <= \<const0>\;
  LOCKSTEP_Master_Out(2572) <= \<const0>\;
  LOCKSTEP_Master_Out(2573) <= \<const0>\;
  LOCKSTEP_Master_Out(2574) <= \<const0>\;
  LOCKSTEP_Master_Out(2575) <= \<const0>\;
  LOCKSTEP_Master_Out(2576) <= \<const0>\;
  LOCKSTEP_Master_Out(2577) <= \<const0>\;
  LOCKSTEP_Master_Out(2578) <= \<const0>\;
  LOCKSTEP_Master_Out(2579) <= \<const0>\;
  LOCKSTEP_Master_Out(2580) <= \<const0>\;
  LOCKSTEP_Master_Out(2581) <= \<const0>\;
  LOCKSTEP_Master_Out(2582) <= \<const0>\;
  LOCKSTEP_Master_Out(2583) <= \<const0>\;
  LOCKSTEP_Master_Out(2584) <= \<const0>\;
  LOCKSTEP_Master_Out(2585) <= \<const0>\;
  LOCKSTEP_Master_Out(2586) <= \<const0>\;
  LOCKSTEP_Master_Out(2587) <= \<const0>\;
  LOCKSTEP_Master_Out(2588) <= \<const0>\;
  LOCKSTEP_Master_Out(2589) <= \<const0>\;
  LOCKSTEP_Master_Out(2590) <= \<const0>\;
  LOCKSTEP_Master_Out(2591) <= \<const0>\;
  LOCKSTEP_Master_Out(2592) <= \<const0>\;
  LOCKSTEP_Master_Out(2593) <= \<const0>\;
  LOCKSTEP_Master_Out(2594) <= \<const0>\;
  LOCKSTEP_Master_Out(2595) <= \<const0>\;
  LOCKSTEP_Master_Out(2596) <= \<const0>\;
  LOCKSTEP_Master_Out(2597) <= \<const0>\;
  LOCKSTEP_Master_Out(2598) <= \<const0>\;
  LOCKSTEP_Master_Out(2599) <= \<const0>\;
  LOCKSTEP_Master_Out(2600) <= \<const0>\;
  LOCKSTEP_Master_Out(2601) <= \<const0>\;
  LOCKSTEP_Master_Out(2602) <= \<const0>\;
  LOCKSTEP_Master_Out(2603) <= \<const0>\;
  LOCKSTEP_Master_Out(2604) <= \<const0>\;
  LOCKSTEP_Master_Out(2605) <= \<const0>\;
  LOCKSTEP_Master_Out(2606) <= \<const0>\;
  LOCKSTEP_Master_Out(2607) <= \<const0>\;
  LOCKSTEP_Master_Out(2608) <= \<const0>\;
  LOCKSTEP_Master_Out(2609) <= \<const0>\;
  LOCKSTEP_Master_Out(2610) <= \<const0>\;
  LOCKSTEP_Master_Out(2611) <= \<const0>\;
  LOCKSTEP_Master_Out(2612) <= \<const0>\;
  LOCKSTEP_Master_Out(2613) <= \<const0>\;
  LOCKSTEP_Master_Out(2614) <= \<const0>\;
  LOCKSTEP_Master_Out(2615) <= \<const0>\;
  LOCKSTEP_Master_Out(2616) <= \<const0>\;
  LOCKSTEP_Master_Out(2617) <= \<const0>\;
  LOCKSTEP_Master_Out(2618) <= \<const0>\;
  LOCKSTEP_Master_Out(2619) <= \<const0>\;
  LOCKSTEP_Master_Out(2620) <= \<const0>\;
  LOCKSTEP_Master_Out(2621) <= \<const0>\;
  LOCKSTEP_Master_Out(2622) <= \<const0>\;
  LOCKSTEP_Master_Out(2623) <= \<const0>\;
  LOCKSTEP_Master_Out(2624) <= \<const0>\;
  LOCKSTEP_Master_Out(2625) <= \<const0>\;
  LOCKSTEP_Master_Out(2626) <= \<const0>\;
  LOCKSTEP_Master_Out(2627) <= \<const0>\;
  LOCKSTEP_Master_Out(2628) <= \<const0>\;
  LOCKSTEP_Master_Out(2629) <= \<const0>\;
  LOCKSTEP_Master_Out(2630) <= \<const0>\;
  LOCKSTEP_Master_Out(2631) <= \<const0>\;
  LOCKSTEP_Master_Out(2632) <= \<const0>\;
  LOCKSTEP_Master_Out(2633) <= \<const0>\;
  LOCKSTEP_Master_Out(2634) <= \<const0>\;
  LOCKSTEP_Master_Out(2635) <= \<const0>\;
  LOCKSTEP_Master_Out(2636) <= \<const0>\;
  LOCKSTEP_Master_Out(2637) <= \<const0>\;
  LOCKSTEP_Master_Out(2638) <= \<const0>\;
  LOCKSTEP_Master_Out(2639) <= \<const0>\;
  LOCKSTEP_Master_Out(2640) <= \<const0>\;
  LOCKSTEP_Master_Out(2641) <= \<const0>\;
  LOCKSTEP_Master_Out(2642) <= \<const0>\;
  LOCKSTEP_Master_Out(2643) <= \<const0>\;
  LOCKSTEP_Master_Out(2644) <= \<const0>\;
  LOCKSTEP_Master_Out(2645) <= \<const0>\;
  LOCKSTEP_Master_Out(2646) <= \<const0>\;
  LOCKSTEP_Master_Out(2647) <= \<const0>\;
  LOCKSTEP_Master_Out(2648) <= \<const0>\;
  LOCKSTEP_Master_Out(2649) <= \<const0>\;
  LOCKSTEP_Master_Out(2650) <= \<const0>\;
  LOCKSTEP_Master_Out(2651) <= \<const0>\;
  LOCKSTEP_Master_Out(2652) <= \<const0>\;
  LOCKSTEP_Master_Out(2653) <= \<const0>\;
  LOCKSTEP_Master_Out(2654) <= \<const0>\;
  LOCKSTEP_Master_Out(2655) <= \<const0>\;
  LOCKSTEP_Master_Out(2656) <= \<const0>\;
  LOCKSTEP_Master_Out(2657) <= \<const0>\;
  LOCKSTEP_Master_Out(2658) <= \<const0>\;
  LOCKSTEP_Master_Out(2659) <= \<const0>\;
  LOCKSTEP_Master_Out(2660) <= \<const0>\;
  LOCKSTEP_Master_Out(2661) <= \<const0>\;
  LOCKSTEP_Master_Out(2662) <= \<const0>\;
  LOCKSTEP_Master_Out(2663) <= \<const0>\;
  LOCKSTEP_Master_Out(2664) <= \<const0>\;
  LOCKSTEP_Master_Out(2665) <= \<const0>\;
  LOCKSTEP_Master_Out(2666) <= \<const0>\;
  LOCKSTEP_Master_Out(2667) <= \<const0>\;
  LOCKSTEP_Master_Out(2668) <= \<const0>\;
  LOCKSTEP_Master_Out(2669) <= \<const0>\;
  LOCKSTEP_Master_Out(2670) <= \<const0>\;
  LOCKSTEP_Master_Out(2671) <= \<const0>\;
  LOCKSTEP_Master_Out(2672) <= \<const0>\;
  LOCKSTEP_Master_Out(2673) <= \<const0>\;
  LOCKSTEP_Master_Out(2674) <= \<const0>\;
  LOCKSTEP_Master_Out(2675) <= \<const0>\;
  LOCKSTEP_Master_Out(2676) <= \<const0>\;
  LOCKSTEP_Master_Out(2677) <= \<const0>\;
  LOCKSTEP_Master_Out(2678) <= \<const0>\;
  LOCKSTEP_Master_Out(2679) <= \<const0>\;
  LOCKSTEP_Master_Out(2680) <= \<const0>\;
  LOCKSTEP_Master_Out(2681) <= \<const0>\;
  LOCKSTEP_Master_Out(2682) <= \<const0>\;
  LOCKSTEP_Master_Out(2683) <= \<const0>\;
  LOCKSTEP_Master_Out(2684) <= \<const0>\;
  LOCKSTEP_Master_Out(2685) <= \<const0>\;
  LOCKSTEP_Master_Out(2686) <= \<const0>\;
  LOCKSTEP_Master_Out(2687) <= \<const0>\;
  LOCKSTEP_Master_Out(2688) <= \<const0>\;
  LOCKSTEP_Master_Out(2689) <= \<const0>\;
  LOCKSTEP_Master_Out(2690) <= \<const0>\;
  LOCKSTEP_Master_Out(2691) <= \<const0>\;
  LOCKSTEP_Master_Out(2692) <= \<const0>\;
  LOCKSTEP_Master_Out(2693) <= \<const0>\;
  LOCKSTEP_Master_Out(2694) <= \<const0>\;
  LOCKSTEP_Master_Out(2695) <= \<const0>\;
  LOCKSTEP_Master_Out(2696) <= \<const0>\;
  LOCKSTEP_Master_Out(2697) <= \<const0>\;
  LOCKSTEP_Master_Out(2698) <= \<const0>\;
  LOCKSTEP_Master_Out(2699) <= \<const0>\;
  LOCKSTEP_Master_Out(2700) <= \<const0>\;
  LOCKSTEP_Master_Out(2701) <= \<const0>\;
  LOCKSTEP_Master_Out(2702) <= \<const0>\;
  LOCKSTEP_Master_Out(2703) <= \<const0>\;
  LOCKSTEP_Master_Out(2704) <= \<const0>\;
  LOCKSTEP_Master_Out(2705) <= \<const0>\;
  LOCKSTEP_Master_Out(2706) <= \<const0>\;
  LOCKSTEP_Master_Out(2707) <= \<const0>\;
  LOCKSTEP_Master_Out(2708) <= \<const0>\;
  LOCKSTEP_Master_Out(2709) <= \<const0>\;
  LOCKSTEP_Master_Out(2710) <= \<const0>\;
  LOCKSTEP_Master_Out(2711) <= \<const0>\;
  LOCKSTEP_Master_Out(2712) <= \<const0>\;
  LOCKSTEP_Master_Out(2713) <= \<const0>\;
  LOCKSTEP_Master_Out(2714) <= \<const0>\;
  LOCKSTEP_Master_Out(2715) <= \<const0>\;
  LOCKSTEP_Master_Out(2716) <= \<const0>\;
  LOCKSTEP_Master_Out(2717) <= \<const0>\;
  LOCKSTEP_Master_Out(2718) <= \<const0>\;
  LOCKSTEP_Master_Out(2719) <= \<const0>\;
  LOCKSTEP_Master_Out(2720) <= \<const0>\;
  LOCKSTEP_Master_Out(2721) <= \<const0>\;
  LOCKSTEP_Master_Out(2722) <= \<const0>\;
  LOCKSTEP_Master_Out(2723) <= \<const0>\;
  LOCKSTEP_Master_Out(2724) <= \<const0>\;
  LOCKSTEP_Master_Out(2725) <= \<const0>\;
  LOCKSTEP_Master_Out(2726) <= \<const0>\;
  LOCKSTEP_Master_Out(2727) <= \<const0>\;
  LOCKSTEP_Master_Out(2728) <= \<const0>\;
  LOCKSTEP_Master_Out(2729) <= \<const0>\;
  LOCKSTEP_Master_Out(2730) <= \<const0>\;
  LOCKSTEP_Master_Out(2731) <= \<const0>\;
  LOCKSTEP_Master_Out(2732) <= \<const0>\;
  LOCKSTEP_Master_Out(2733) <= \<const0>\;
  LOCKSTEP_Master_Out(2734) <= \<const0>\;
  LOCKSTEP_Master_Out(2735) <= \<const0>\;
  LOCKSTEP_Master_Out(2736) <= \<const0>\;
  LOCKSTEP_Master_Out(2737) <= \<const0>\;
  LOCKSTEP_Master_Out(2738) <= \<const0>\;
  LOCKSTEP_Master_Out(2739) <= \<const0>\;
  LOCKSTEP_Master_Out(2740) <= \<const0>\;
  LOCKSTEP_Master_Out(2741) <= \<const0>\;
  LOCKSTEP_Master_Out(2742) <= \<const0>\;
  LOCKSTEP_Master_Out(2743) <= \<const0>\;
  LOCKSTEP_Master_Out(2744) <= \<const0>\;
  LOCKSTEP_Master_Out(2745) <= \<const0>\;
  LOCKSTEP_Master_Out(2746) <= \<const0>\;
  LOCKSTEP_Master_Out(2747) <= \<const0>\;
  LOCKSTEP_Master_Out(2748) <= \<const0>\;
  LOCKSTEP_Master_Out(2749) <= \<const0>\;
  LOCKSTEP_Master_Out(2750) <= \<const0>\;
  LOCKSTEP_Master_Out(2751) <= \<const0>\;
  LOCKSTEP_Master_Out(2752) <= \<const0>\;
  LOCKSTEP_Master_Out(2753) <= \<const0>\;
  LOCKSTEP_Master_Out(2754) <= \<const0>\;
  LOCKSTEP_Master_Out(2755) <= \<const0>\;
  LOCKSTEP_Master_Out(2756) <= \<const0>\;
  LOCKSTEP_Master_Out(2757) <= \<const0>\;
  LOCKSTEP_Master_Out(2758) <= \<const0>\;
  LOCKSTEP_Master_Out(2759) <= \<const0>\;
  LOCKSTEP_Master_Out(2760) <= \<const0>\;
  LOCKSTEP_Master_Out(2761) <= \<const0>\;
  LOCKSTEP_Master_Out(2762) <= \<const0>\;
  LOCKSTEP_Master_Out(2763) <= \<const0>\;
  LOCKSTEP_Master_Out(2764) <= \<const0>\;
  LOCKSTEP_Master_Out(2765) <= \<const0>\;
  LOCKSTEP_Master_Out(2766) <= \<const0>\;
  LOCKSTEP_Master_Out(2767) <= \<const0>\;
  LOCKSTEP_Master_Out(2768) <= \<const0>\;
  LOCKSTEP_Master_Out(2769) <= \<const0>\;
  LOCKSTEP_Master_Out(2770) <= \<const0>\;
  LOCKSTEP_Master_Out(2771) <= \<const0>\;
  LOCKSTEP_Master_Out(2772) <= \<const0>\;
  LOCKSTEP_Master_Out(2773) <= \<const0>\;
  LOCKSTEP_Master_Out(2774) <= \<const0>\;
  LOCKSTEP_Master_Out(2775) <= \<const0>\;
  LOCKSTEP_Master_Out(2776) <= \<const0>\;
  LOCKSTEP_Master_Out(2777) <= \<const0>\;
  LOCKSTEP_Master_Out(2778) <= \<const0>\;
  LOCKSTEP_Master_Out(2779) <= \<const0>\;
  LOCKSTEP_Master_Out(2780) <= \<const0>\;
  LOCKSTEP_Master_Out(2781) <= \<const0>\;
  LOCKSTEP_Master_Out(2782) <= \<const0>\;
  LOCKSTEP_Master_Out(2783) <= \<const0>\;
  LOCKSTEP_Master_Out(2784) <= \<const0>\;
  LOCKSTEP_Master_Out(2785) <= \<const0>\;
  LOCKSTEP_Master_Out(2786) <= \<const0>\;
  LOCKSTEP_Master_Out(2787) <= \<const0>\;
  LOCKSTEP_Master_Out(2788) <= \<const0>\;
  LOCKSTEP_Master_Out(2789) <= \<const0>\;
  LOCKSTEP_Master_Out(2790) <= \<const0>\;
  LOCKSTEP_Master_Out(2791) <= \<const0>\;
  LOCKSTEP_Master_Out(2792) <= \<const0>\;
  LOCKSTEP_Master_Out(2793) <= \<const0>\;
  LOCKSTEP_Master_Out(2794) <= \<const0>\;
  LOCKSTEP_Master_Out(2795) <= \<const0>\;
  LOCKSTEP_Master_Out(2796) <= \<const0>\;
  LOCKSTEP_Master_Out(2797) <= \<const0>\;
  LOCKSTEP_Master_Out(2798) <= \<const0>\;
  LOCKSTEP_Master_Out(2799) <= \<const0>\;
  LOCKSTEP_Master_Out(2800) <= \<const0>\;
  LOCKSTEP_Master_Out(2801) <= \<const0>\;
  LOCKSTEP_Master_Out(2802) <= \<const0>\;
  LOCKSTEP_Master_Out(2803) <= \<const0>\;
  LOCKSTEP_Master_Out(2804) <= \<const0>\;
  LOCKSTEP_Master_Out(2805) <= \<const0>\;
  LOCKSTEP_Master_Out(2806) <= \<const0>\;
  LOCKSTEP_Master_Out(2807) <= \<const0>\;
  LOCKSTEP_Master_Out(2808) <= \<const0>\;
  LOCKSTEP_Master_Out(2809) <= \<const0>\;
  LOCKSTEP_Master_Out(2810) <= \<const0>\;
  LOCKSTEP_Master_Out(2811) <= \<const0>\;
  LOCKSTEP_Master_Out(2812) <= \<const0>\;
  LOCKSTEP_Master_Out(2813) <= \<const0>\;
  LOCKSTEP_Master_Out(2814) <= \<const0>\;
  LOCKSTEP_Master_Out(2815) <= \<const0>\;
  LOCKSTEP_Master_Out(2816) <= \<const0>\;
  LOCKSTEP_Master_Out(2817) <= \<const0>\;
  LOCKSTEP_Master_Out(2818) <= \<const0>\;
  LOCKSTEP_Master_Out(2819) <= \<const0>\;
  LOCKSTEP_Master_Out(2820) <= \<const0>\;
  LOCKSTEP_Master_Out(2821) <= \<const0>\;
  LOCKSTEP_Master_Out(2822) <= \<const0>\;
  LOCKSTEP_Master_Out(2823) <= \<const0>\;
  LOCKSTEP_Master_Out(2824) <= \<const0>\;
  LOCKSTEP_Master_Out(2825) <= \<const0>\;
  LOCKSTEP_Master_Out(2826) <= \<const0>\;
  LOCKSTEP_Master_Out(2827) <= \<const0>\;
  LOCKSTEP_Master_Out(2828) <= \<const0>\;
  LOCKSTEP_Master_Out(2829) <= \<const0>\;
  LOCKSTEP_Master_Out(2830) <= \<const0>\;
  LOCKSTEP_Master_Out(2831) <= \<const0>\;
  LOCKSTEP_Master_Out(2832) <= \<const0>\;
  LOCKSTEP_Master_Out(2833) <= \<const0>\;
  LOCKSTEP_Master_Out(2834) <= \<const0>\;
  LOCKSTEP_Master_Out(2835) <= \<const0>\;
  LOCKSTEP_Master_Out(2836) <= \<const0>\;
  LOCKSTEP_Master_Out(2837) <= \<const0>\;
  LOCKSTEP_Master_Out(2838) <= \<const0>\;
  LOCKSTEP_Master_Out(2839) <= \<const0>\;
  LOCKSTEP_Master_Out(2840) <= \<const0>\;
  LOCKSTEP_Master_Out(2841) <= \<const0>\;
  LOCKSTEP_Master_Out(2842) <= \<const0>\;
  LOCKSTEP_Master_Out(2843) <= \<const0>\;
  LOCKSTEP_Master_Out(2844) <= \<const0>\;
  LOCKSTEP_Master_Out(2845) <= \<const0>\;
  LOCKSTEP_Master_Out(2846) <= \<const0>\;
  LOCKSTEP_Master_Out(2847) <= \<const0>\;
  LOCKSTEP_Master_Out(2848) <= \<const0>\;
  LOCKSTEP_Master_Out(2849) <= \<const0>\;
  LOCKSTEP_Master_Out(2850) <= \<const0>\;
  LOCKSTEP_Master_Out(2851) <= \<const0>\;
  LOCKSTEP_Master_Out(2852) <= \<const0>\;
  LOCKSTEP_Master_Out(2853) <= \<const0>\;
  LOCKSTEP_Master_Out(2854) <= \<const0>\;
  LOCKSTEP_Master_Out(2855) <= \<const0>\;
  LOCKSTEP_Master_Out(2856) <= \<const0>\;
  LOCKSTEP_Master_Out(2857) <= \<const0>\;
  LOCKSTEP_Master_Out(2858) <= \<const0>\;
  LOCKSTEP_Master_Out(2859) <= \<const0>\;
  LOCKSTEP_Master_Out(2860) <= \<const0>\;
  LOCKSTEP_Master_Out(2861) <= \<const0>\;
  LOCKSTEP_Master_Out(2862) <= \<const0>\;
  LOCKSTEP_Master_Out(2863) <= \<const0>\;
  LOCKSTEP_Master_Out(2864) <= \<const0>\;
  LOCKSTEP_Master_Out(2865) <= \<const0>\;
  LOCKSTEP_Master_Out(2866) <= \<const0>\;
  LOCKSTEP_Master_Out(2867) <= \<const0>\;
  LOCKSTEP_Master_Out(2868) <= \<const0>\;
  LOCKSTEP_Master_Out(2869) <= \<const0>\;
  LOCKSTEP_Master_Out(2870) <= \<const0>\;
  LOCKSTEP_Master_Out(2871) <= \<const0>\;
  LOCKSTEP_Master_Out(2872) <= \<const0>\;
  LOCKSTEP_Master_Out(2873) <= \<const0>\;
  LOCKSTEP_Master_Out(2874) <= \<const0>\;
  LOCKSTEP_Master_Out(2875) <= \<const0>\;
  LOCKSTEP_Master_Out(2876) <= \<const0>\;
  LOCKSTEP_Master_Out(2877) <= \<const0>\;
  LOCKSTEP_Master_Out(2878) <= \<const0>\;
  LOCKSTEP_Master_Out(2879) <= \<const0>\;
  LOCKSTEP_Master_Out(2880) <= \<const0>\;
  LOCKSTEP_Master_Out(2881) <= \<const0>\;
  LOCKSTEP_Master_Out(2882) <= \<const0>\;
  LOCKSTEP_Master_Out(2883) <= \<const0>\;
  LOCKSTEP_Master_Out(2884) <= \<const0>\;
  LOCKSTEP_Master_Out(2885) <= \<const0>\;
  LOCKSTEP_Master_Out(2886) <= \<const0>\;
  LOCKSTEP_Master_Out(2887) <= \<const0>\;
  LOCKSTEP_Master_Out(2888) <= \<const0>\;
  LOCKSTEP_Master_Out(2889) <= \<const0>\;
  LOCKSTEP_Master_Out(2890) <= \<const0>\;
  LOCKSTEP_Master_Out(2891) <= \<const0>\;
  LOCKSTEP_Master_Out(2892) <= \<const0>\;
  LOCKSTEP_Master_Out(2893) <= \<const0>\;
  LOCKSTEP_Master_Out(2894) <= \<const0>\;
  LOCKSTEP_Master_Out(2895) <= \<const0>\;
  LOCKSTEP_Master_Out(2896) <= \<const0>\;
  LOCKSTEP_Master_Out(2897) <= \<const0>\;
  LOCKSTEP_Master_Out(2898) <= \<const0>\;
  LOCKSTEP_Master_Out(2899) <= \<const0>\;
  LOCKSTEP_Master_Out(2900) <= \<const0>\;
  LOCKSTEP_Master_Out(2901) <= \<const0>\;
  LOCKSTEP_Master_Out(2902) <= \<const0>\;
  LOCKSTEP_Master_Out(2903) <= \<const0>\;
  LOCKSTEP_Master_Out(2904) <= \<const0>\;
  LOCKSTEP_Master_Out(2905) <= \<const0>\;
  LOCKSTEP_Master_Out(2906) <= \<const0>\;
  LOCKSTEP_Master_Out(2907) <= \<const0>\;
  LOCKSTEP_Master_Out(2908) <= \<const0>\;
  LOCKSTEP_Master_Out(2909) <= \<const0>\;
  LOCKSTEP_Master_Out(2910) <= \<const0>\;
  LOCKSTEP_Master_Out(2911) <= \<const0>\;
  LOCKSTEP_Master_Out(2912) <= \<const0>\;
  LOCKSTEP_Master_Out(2913) <= \<const0>\;
  LOCKSTEP_Master_Out(2914) <= \<const0>\;
  LOCKSTEP_Master_Out(2915) <= \<const0>\;
  LOCKSTEP_Master_Out(2916) <= \<const0>\;
  LOCKSTEP_Master_Out(2917) <= \<const0>\;
  LOCKSTEP_Master_Out(2918) <= \<const0>\;
  LOCKSTEP_Master_Out(2919) <= \<const0>\;
  LOCKSTEP_Master_Out(2920) <= \<const0>\;
  LOCKSTEP_Master_Out(2921) <= \<const0>\;
  LOCKSTEP_Master_Out(2922) <= \<const0>\;
  LOCKSTEP_Master_Out(2923) <= \<const0>\;
  LOCKSTEP_Master_Out(2924) <= \<const0>\;
  LOCKSTEP_Master_Out(2925) <= \<const0>\;
  LOCKSTEP_Master_Out(2926) <= \<const0>\;
  LOCKSTEP_Master_Out(2927) <= \<const0>\;
  LOCKSTEP_Master_Out(2928) <= \<const0>\;
  LOCKSTEP_Master_Out(2929) <= \<const0>\;
  LOCKSTEP_Master_Out(2930) <= \<const0>\;
  LOCKSTEP_Master_Out(2931) <= \<const0>\;
  LOCKSTEP_Master_Out(2932) <= \<const0>\;
  LOCKSTEP_Master_Out(2933) <= \<const0>\;
  LOCKSTEP_Master_Out(2934) <= \<const0>\;
  LOCKSTEP_Master_Out(2935) <= \<const0>\;
  LOCKSTEP_Master_Out(2936) <= \<const0>\;
  LOCKSTEP_Master_Out(2937) <= \<const0>\;
  LOCKSTEP_Master_Out(2938) <= \<const0>\;
  LOCKSTEP_Master_Out(2939) <= \<const0>\;
  LOCKSTEP_Master_Out(2940) <= \<const0>\;
  LOCKSTEP_Master_Out(2941) <= \<const0>\;
  LOCKSTEP_Master_Out(2942) <= \<const0>\;
  LOCKSTEP_Master_Out(2943) <= \<const0>\;
  LOCKSTEP_Master_Out(2944) <= \<const0>\;
  LOCKSTEP_Master_Out(2945) <= \<const0>\;
  LOCKSTEP_Master_Out(2946) <= \<const0>\;
  LOCKSTEP_Master_Out(2947) <= \<const0>\;
  LOCKSTEP_Master_Out(2948) <= \<const0>\;
  LOCKSTEP_Master_Out(2949) <= \<const0>\;
  LOCKSTEP_Master_Out(2950) <= \<const0>\;
  LOCKSTEP_Master_Out(2951) <= \<const0>\;
  LOCKSTEP_Master_Out(2952) <= \<const0>\;
  LOCKSTEP_Master_Out(2953) <= \<const0>\;
  LOCKSTEP_Master_Out(2954) <= \<const0>\;
  LOCKSTEP_Master_Out(2955) <= \<const0>\;
  LOCKSTEP_Master_Out(2956) <= \<const0>\;
  LOCKSTEP_Master_Out(2957) <= \<const0>\;
  LOCKSTEP_Master_Out(2958) <= \<const0>\;
  LOCKSTEP_Master_Out(2959) <= \<const0>\;
  LOCKSTEP_Master_Out(2960) <= \<const0>\;
  LOCKSTEP_Master_Out(2961) <= \<const0>\;
  LOCKSTEP_Master_Out(2962) <= \<const0>\;
  LOCKSTEP_Master_Out(2963) <= \<const0>\;
  LOCKSTEP_Master_Out(2964) <= \<const0>\;
  LOCKSTEP_Master_Out(2965) <= \<const0>\;
  LOCKSTEP_Master_Out(2966) <= \<const0>\;
  LOCKSTEP_Master_Out(2967) <= \<const0>\;
  LOCKSTEP_Master_Out(2968) <= \<const0>\;
  LOCKSTEP_Master_Out(2969) <= \<const0>\;
  LOCKSTEP_Master_Out(2970) <= \<const0>\;
  LOCKSTEP_Master_Out(2971) <= \<const0>\;
  LOCKSTEP_Master_Out(2972) <= \<const0>\;
  LOCKSTEP_Master_Out(2973) <= \<const0>\;
  LOCKSTEP_Master_Out(2974) <= \<const0>\;
  LOCKSTEP_Master_Out(2975) <= \<const0>\;
  LOCKSTEP_Master_Out(2976) <= \<const0>\;
  LOCKSTEP_Master_Out(2977) <= \<const0>\;
  LOCKSTEP_Master_Out(2978) <= \<const0>\;
  LOCKSTEP_Master_Out(2979) <= \<const0>\;
  LOCKSTEP_Master_Out(2980) <= \<const0>\;
  LOCKSTEP_Master_Out(2981) <= \<const0>\;
  LOCKSTEP_Master_Out(2982) <= \<const0>\;
  LOCKSTEP_Master_Out(2983) <= \<const0>\;
  LOCKSTEP_Master_Out(2984) <= \<const0>\;
  LOCKSTEP_Master_Out(2985) <= \<const0>\;
  LOCKSTEP_Master_Out(2986) <= \<const0>\;
  LOCKSTEP_Master_Out(2987) <= \<const0>\;
  LOCKSTEP_Master_Out(2988) <= \<const0>\;
  LOCKSTEP_Master_Out(2989) <= \<const0>\;
  LOCKSTEP_Master_Out(2990) <= \<const0>\;
  LOCKSTEP_Master_Out(2991) <= \<const0>\;
  LOCKSTEP_Master_Out(2992) <= \<const0>\;
  LOCKSTEP_Master_Out(2993) <= \<const0>\;
  LOCKSTEP_Master_Out(2994) <= \<const0>\;
  LOCKSTEP_Master_Out(2995) <= \<const0>\;
  LOCKSTEP_Master_Out(2996) <= \<const0>\;
  LOCKSTEP_Master_Out(2997) <= \<const0>\;
  LOCKSTEP_Master_Out(2998) <= \<const0>\;
  LOCKSTEP_Master_Out(2999) <= \<const0>\;
  LOCKSTEP_Master_Out(3000) <= \<const0>\;
  LOCKSTEP_Master_Out(3001) <= \<const0>\;
  LOCKSTEP_Master_Out(3002) <= \<const0>\;
  LOCKSTEP_Master_Out(3003) <= \<const0>\;
  LOCKSTEP_Master_Out(3004) <= \<const0>\;
  LOCKSTEP_Master_Out(3005) <= \<const0>\;
  LOCKSTEP_Master_Out(3006) <= \<const0>\;
  LOCKSTEP_Master_Out(3007) <= \<const0>\;
  LOCKSTEP_Master_Out(3008) <= \<const0>\;
  LOCKSTEP_Master_Out(3009) <= \<const0>\;
  LOCKSTEP_Master_Out(3010) <= \<const0>\;
  LOCKSTEP_Master_Out(3011) <= \<const0>\;
  LOCKSTEP_Master_Out(3012) <= \<const0>\;
  LOCKSTEP_Master_Out(3013) <= \<const0>\;
  LOCKSTEP_Master_Out(3014) <= \<const0>\;
  LOCKSTEP_Master_Out(3015) <= \<const0>\;
  LOCKSTEP_Master_Out(3016) <= \<const0>\;
  LOCKSTEP_Master_Out(3017) <= \<const0>\;
  LOCKSTEP_Master_Out(3018) <= \<const0>\;
  LOCKSTEP_Master_Out(3019) <= \<const0>\;
  LOCKSTEP_Master_Out(3020) <= \<const0>\;
  LOCKSTEP_Master_Out(3021) <= \<const0>\;
  LOCKSTEP_Master_Out(3022) <= \<const0>\;
  LOCKSTEP_Master_Out(3023) <= \<const0>\;
  LOCKSTEP_Master_Out(3024) <= \<const0>\;
  LOCKSTEP_Master_Out(3025) <= \<const0>\;
  LOCKSTEP_Master_Out(3026) <= \<const0>\;
  LOCKSTEP_Master_Out(3027) <= \<const0>\;
  LOCKSTEP_Master_Out(3028) <= \<const0>\;
  LOCKSTEP_Master_Out(3029) <= \<const0>\;
  LOCKSTEP_Master_Out(3030) <= \<const0>\;
  LOCKSTEP_Master_Out(3031) <= \<const0>\;
  LOCKSTEP_Master_Out(3032) <= \<const0>\;
  LOCKSTEP_Master_Out(3033) <= \<const0>\;
  LOCKSTEP_Master_Out(3034) <= \<const0>\;
  LOCKSTEP_Master_Out(3035) <= \<const0>\;
  LOCKSTEP_Master_Out(3036) <= \<const0>\;
  LOCKSTEP_Master_Out(3037) <= \<const0>\;
  LOCKSTEP_Master_Out(3038) <= \<const0>\;
  LOCKSTEP_Master_Out(3039) <= \<const0>\;
  LOCKSTEP_Master_Out(3040) <= \<const0>\;
  LOCKSTEP_Master_Out(3041) <= \<const0>\;
  LOCKSTEP_Master_Out(3042) <= \<const0>\;
  LOCKSTEP_Master_Out(3043) <= \<const0>\;
  LOCKSTEP_Master_Out(3044) <= \<const0>\;
  LOCKSTEP_Master_Out(3045) <= \<const0>\;
  LOCKSTEP_Master_Out(3046) <= \<const0>\;
  LOCKSTEP_Master_Out(3047) <= \<const0>\;
  LOCKSTEP_Master_Out(3048) <= \<const0>\;
  LOCKSTEP_Master_Out(3049) <= \<const0>\;
  LOCKSTEP_Master_Out(3050) <= \<const0>\;
  LOCKSTEP_Master_Out(3051) <= \<const0>\;
  LOCKSTEP_Master_Out(3052) <= \<const0>\;
  LOCKSTEP_Master_Out(3053) <= \<const0>\;
  LOCKSTEP_Master_Out(3054) <= \<const0>\;
  LOCKSTEP_Master_Out(3055) <= \<const0>\;
  LOCKSTEP_Master_Out(3056) <= \<const0>\;
  LOCKSTEP_Master_Out(3057) <= \<const0>\;
  LOCKSTEP_Master_Out(3058) <= \<const0>\;
  LOCKSTEP_Master_Out(3059) <= \<const0>\;
  LOCKSTEP_Master_Out(3060) <= \<const0>\;
  LOCKSTEP_Master_Out(3061) <= \<const0>\;
  LOCKSTEP_Master_Out(3062) <= \<const0>\;
  LOCKSTEP_Master_Out(3063) <= \<const0>\;
  LOCKSTEP_Master_Out(3064) <= \<const0>\;
  LOCKSTEP_Master_Out(3065) <= \<const0>\;
  LOCKSTEP_Master_Out(3066) <= \<const0>\;
  LOCKSTEP_Master_Out(3067) <= \<const0>\;
  LOCKSTEP_Master_Out(3068) <= \<const0>\;
  LOCKSTEP_Master_Out(3069) <= \<const0>\;
  LOCKSTEP_Master_Out(3070) <= \<const0>\;
  LOCKSTEP_Master_Out(3071) <= \<const0>\;
  LOCKSTEP_Master_Out(3072) <= \<const0>\;
  LOCKSTEP_Master_Out(3073) <= \<const0>\;
  LOCKSTEP_Master_Out(3074) <= \<const0>\;
  LOCKSTEP_Master_Out(3075) <= \<const0>\;
  LOCKSTEP_Master_Out(3076) <= \<const0>\;
  LOCKSTEP_Master_Out(3077) <= \<const0>\;
  LOCKSTEP_Master_Out(3078) <= \<const0>\;
  LOCKSTEP_Master_Out(3079) <= \<const0>\;
  LOCKSTEP_Master_Out(3080) <= \<const0>\;
  LOCKSTEP_Master_Out(3081) <= \<const0>\;
  LOCKSTEP_Master_Out(3082) <= \<const0>\;
  LOCKSTEP_Master_Out(3083) <= \<const0>\;
  LOCKSTEP_Master_Out(3084) <= \<const0>\;
  LOCKSTEP_Master_Out(3085) <= \<const0>\;
  LOCKSTEP_Master_Out(3086) <= \<const0>\;
  LOCKSTEP_Master_Out(3087) <= \<const0>\;
  LOCKSTEP_Master_Out(3088) <= \<const0>\;
  LOCKSTEP_Master_Out(3089) <= \<const0>\;
  LOCKSTEP_Master_Out(3090) <= \<const0>\;
  LOCKSTEP_Master_Out(3091) <= \<const0>\;
  LOCKSTEP_Master_Out(3092) <= \<const0>\;
  LOCKSTEP_Master_Out(3093) <= \<const0>\;
  LOCKSTEP_Master_Out(3094) <= \<const0>\;
  LOCKSTEP_Master_Out(3095) <= \<const0>\;
  LOCKSTEP_Master_Out(3096) <= \<const0>\;
  LOCKSTEP_Master_Out(3097) <= \<const0>\;
  LOCKSTEP_Master_Out(3098) <= \<const0>\;
  LOCKSTEP_Master_Out(3099) <= \<const0>\;
  LOCKSTEP_Master_Out(3100) <= \<const0>\;
  LOCKSTEP_Master_Out(3101) <= \<const0>\;
  LOCKSTEP_Master_Out(3102) <= \<const0>\;
  LOCKSTEP_Master_Out(3103) <= \<const0>\;
  LOCKSTEP_Master_Out(3104) <= \<const0>\;
  LOCKSTEP_Master_Out(3105) <= \<const0>\;
  LOCKSTEP_Master_Out(3106) <= \<const0>\;
  LOCKSTEP_Master_Out(3107) <= \<const0>\;
  LOCKSTEP_Master_Out(3108) <= \<const0>\;
  LOCKSTEP_Master_Out(3109) <= \<const0>\;
  LOCKSTEP_Master_Out(3110) <= \<const0>\;
  LOCKSTEP_Master_Out(3111) <= \<const0>\;
  LOCKSTEP_Master_Out(3112) <= \<const0>\;
  LOCKSTEP_Master_Out(3113) <= \<const0>\;
  LOCKSTEP_Master_Out(3114) <= \<const0>\;
  LOCKSTEP_Master_Out(3115) <= \<const0>\;
  LOCKSTEP_Master_Out(3116) <= \<const0>\;
  LOCKSTEP_Master_Out(3117) <= \<const0>\;
  LOCKSTEP_Master_Out(3118) <= \<const0>\;
  LOCKSTEP_Master_Out(3119) <= \<const0>\;
  LOCKSTEP_Master_Out(3120) <= \<const0>\;
  LOCKSTEP_Master_Out(3121) <= \<const0>\;
  LOCKSTEP_Master_Out(3122) <= \<const0>\;
  LOCKSTEP_Master_Out(3123) <= \<const0>\;
  LOCKSTEP_Master_Out(3124) <= \<const0>\;
  LOCKSTEP_Master_Out(3125) <= \<const0>\;
  LOCKSTEP_Master_Out(3126) <= \<const0>\;
  LOCKSTEP_Master_Out(3127) <= \<const0>\;
  LOCKSTEP_Master_Out(3128) <= \<const0>\;
  LOCKSTEP_Master_Out(3129) <= \<const0>\;
  LOCKSTEP_Master_Out(3130) <= \<const0>\;
  LOCKSTEP_Master_Out(3131) <= \<const0>\;
  LOCKSTEP_Master_Out(3132) <= \<const0>\;
  LOCKSTEP_Master_Out(3133) <= \<const0>\;
  LOCKSTEP_Master_Out(3134) <= \<const0>\;
  LOCKSTEP_Master_Out(3135) <= \<const0>\;
  LOCKSTEP_Master_Out(3136) <= \<const0>\;
  LOCKSTEP_Master_Out(3137) <= \<const0>\;
  LOCKSTEP_Master_Out(3138) <= \<const0>\;
  LOCKSTEP_Master_Out(3139) <= \<const0>\;
  LOCKSTEP_Master_Out(3140) <= \<const0>\;
  LOCKSTEP_Master_Out(3141) <= \<const0>\;
  LOCKSTEP_Master_Out(3142) <= \<const0>\;
  LOCKSTEP_Master_Out(3143) <= \<const0>\;
  LOCKSTEP_Master_Out(3144) <= \<const0>\;
  LOCKSTEP_Master_Out(3145) <= \<const0>\;
  LOCKSTEP_Master_Out(3146) <= \<const0>\;
  LOCKSTEP_Master_Out(3147) <= \<const0>\;
  LOCKSTEP_Master_Out(3148) <= \<const0>\;
  LOCKSTEP_Master_Out(3149) <= \<const0>\;
  LOCKSTEP_Master_Out(3150) <= \<const0>\;
  LOCKSTEP_Master_Out(3151) <= \<const0>\;
  LOCKSTEP_Master_Out(3152) <= \<const0>\;
  LOCKSTEP_Master_Out(3153) <= \<const0>\;
  LOCKSTEP_Master_Out(3154) <= \<const0>\;
  LOCKSTEP_Master_Out(3155) <= \<const0>\;
  LOCKSTEP_Master_Out(3156) <= \<const0>\;
  LOCKSTEP_Master_Out(3157) <= \<const0>\;
  LOCKSTEP_Master_Out(3158) <= \<const0>\;
  LOCKSTEP_Master_Out(3159) <= \<const0>\;
  LOCKSTEP_Master_Out(3160) <= \<const0>\;
  LOCKSTEP_Master_Out(3161) <= \<const0>\;
  LOCKSTEP_Master_Out(3162) <= \<const0>\;
  LOCKSTEP_Master_Out(3163) <= \<const0>\;
  LOCKSTEP_Master_Out(3164) <= \<const0>\;
  LOCKSTEP_Master_Out(3165) <= \<const0>\;
  LOCKSTEP_Master_Out(3166) <= \<const0>\;
  LOCKSTEP_Master_Out(3167) <= \<const0>\;
  LOCKSTEP_Master_Out(3168) <= \<const0>\;
  LOCKSTEP_Master_Out(3169) <= \<const0>\;
  LOCKSTEP_Master_Out(3170) <= \<const0>\;
  LOCKSTEP_Master_Out(3171) <= \<const0>\;
  LOCKSTEP_Master_Out(3172) <= \<const0>\;
  LOCKSTEP_Master_Out(3173) <= \<const0>\;
  LOCKSTEP_Master_Out(3174) <= \<const0>\;
  LOCKSTEP_Master_Out(3175) <= \<const0>\;
  LOCKSTEP_Master_Out(3176) <= \<const0>\;
  LOCKSTEP_Master_Out(3177) <= \<const0>\;
  LOCKSTEP_Master_Out(3178) <= \<const0>\;
  LOCKSTEP_Master_Out(3179) <= \<const0>\;
  LOCKSTEP_Master_Out(3180) <= \<const0>\;
  LOCKSTEP_Master_Out(3181) <= \<const0>\;
  LOCKSTEP_Master_Out(3182) <= \<const0>\;
  LOCKSTEP_Master_Out(3183) <= \<const0>\;
  LOCKSTEP_Master_Out(3184) <= \<const0>\;
  LOCKSTEP_Master_Out(3185) <= \<const0>\;
  LOCKSTEP_Master_Out(3186) <= \<const0>\;
  LOCKSTEP_Master_Out(3187) <= \<const0>\;
  LOCKSTEP_Master_Out(3188) <= \<const0>\;
  LOCKSTEP_Master_Out(3189) <= \<const0>\;
  LOCKSTEP_Master_Out(3190) <= \<const0>\;
  LOCKSTEP_Master_Out(3191) <= \<const0>\;
  LOCKSTEP_Master_Out(3192) <= \<const0>\;
  LOCKSTEP_Master_Out(3193) <= \<const0>\;
  LOCKSTEP_Master_Out(3194) <= \<const0>\;
  LOCKSTEP_Master_Out(3195) <= \<const0>\;
  LOCKSTEP_Master_Out(3196) <= \<const0>\;
  LOCKSTEP_Master_Out(3197) <= \<const0>\;
  LOCKSTEP_Master_Out(3198) <= \<const0>\;
  LOCKSTEP_Master_Out(3199) <= \<const0>\;
  LOCKSTEP_Master_Out(3200) <= \<const0>\;
  LOCKSTEP_Master_Out(3201) <= \<const0>\;
  LOCKSTEP_Master_Out(3202) <= \<const0>\;
  LOCKSTEP_Master_Out(3203) <= \<const0>\;
  LOCKSTEP_Master_Out(3204) <= \<const0>\;
  LOCKSTEP_Master_Out(3205) <= \<const0>\;
  LOCKSTEP_Master_Out(3206) <= \<const0>\;
  LOCKSTEP_Master_Out(3207) <= \<const0>\;
  LOCKSTEP_Master_Out(3208) <= \<const0>\;
  LOCKSTEP_Master_Out(3209) <= \<const0>\;
  LOCKSTEP_Master_Out(3210) <= \<const0>\;
  LOCKSTEP_Master_Out(3211) <= \<const0>\;
  LOCKSTEP_Master_Out(3212) <= \<const0>\;
  LOCKSTEP_Master_Out(3213) <= \<const0>\;
  LOCKSTEP_Master_Out(3214) <= \<const0>\;
  LOCKSTEP_Master_Out(3215) <= \<const0>\;
  LOCKSTEP_Master_Out(3216) <= \<const0>\;
  LOCKSTEP_Master_Out(3217) <= \<const0>\;
  LOCKSTEP_Master_Out(3218) <= \<const0>\;
  LOCKSTEP_Master_Out(3219) <= \<const0>\;
  LOCKSTEP_Master_Out(3220) <= \<const0>\;
  LOCKSTEP_Master_Out(3221) <= \<const0>\;
  LOCKSTEP_Master_Out(3222) <= \<const0>\;
  LOCKSTEP_Master_Out(3223) <= \<const0>\;
  LOCKSTEP_Master_Out(3224) <= \<const0>\;
  LOCKSTEP_Master_Out(3225) <= \<const0>\;
  LOCKSTEP_Master_Out(3226) <= \<const0>\;
  LOCKSTEP_Master_Out(3227) <= \<const0>\;
  LOCKSTEP_Master_Out(3228) <= \<const0>\;
  LOCKSTEP_Master_Out(3229) <= \<const0>\;
  LOCKSTEP_Master_Out(3230) <= \<const0>\;
  LOCKSTEP_Master_Out(3231) <= \<const0>\;
  LOCKSTEP_Master_Out(3232) <= \<const0>\;
  LOCKSTEP_Master_Out(3233) <= \<const0>\;
  LOCKSTEP_Master_Out(3234) <= \<const0>\;
  LOCKSTEP_Master_Out(3235) <= \<const0>\;
  LOCKSTEP_Master_Out(3236) <= \<const0>\;
  LOCKSTEP_Master_Out(3237) <= \<const0>\;
  LOCKSTEP_Master_Out(3238) <= \<const0>\;
  LOCKSTEP_Master_Out(3239) <= \<const0>\;
  LOCKSTEP_Master_Out(3240) <= \<const0>\;
  LOCKSTEP_Master_Out(3241) <= \<const0>\;
  LOCKSTEP_Master_Out(3242) <= \<const0>\;
  LOCKSTEP_Master_Out(3243) <= \<const0>\;
  LOCKSTEP_Master_Out(3244) <= \<const0>\;
  LOCKSTEP_Master_Out(3245) <= \<const0>\;
  LOCKSTEP_Master_Out(3246) <= \<const0>\;
  LOCKSTEP_Master_Out(3247) <= \<const0>\;
  LOCKSTEP_Master_Out(3248) <= \<const0>\;
  LOCKSTEP_Master_Out(3249) <= \<const0>\;
  LOCKSTEP_Master_Out(3250) <= \<const0>\;
  LOCKSTEP_Master_Out(3251) <= \<const0>\;
  LOCKSTEP_Master_Out(3252) <= \<const0>\;
  LOCKSTEP_Master_Out(3253) <= \<const0>\;
  LOCKSTEP_Master_Out(3254) <= \<const0>\;
  LOCKSTEP_Master_Out(3255) <= \<const0>\;
  LOCKSTEP_Master_Out(3256) <= \<const0>\;
  LOCKSTEP_Master_Out(3257) <= \<const0>\;
  LOCKSTEP_Master_Out(3258) <= \<const0>\;
  LOCKSTEP_Master_Out(3259) <= \<const0>\;
  LOCKSTEP_Master_Out(3260) <= \<const0>\;
  LOCKSTEP_Master_Out(3261) <= \<const0>\;
  LOCKSTEP_Master_Out(3262) <= \<const0>\;
  LOCKSTEP_Master_Out(3263) <= \<const0>\;
  LOCKSTEP_Master_Out(3264) <= \<const0>\;
  LOCKSTEP_Master_Out(3265) <= \<const0>\;
  LOCKSTEP_Master_Out(3266) <= \<const0>\;
  LOCKSTEP_Master_Out(3267) <= \<const0>\;
  LOCKSTEP_Master_Out(3268) <= \<const0>\;
  LOCKSTEP_Master_Out(3269) <= \<const0>\;
  LOCKSTEP_Master_Out(3270) <= \<const0>\;
  LOCKSTEP_Master_Out(3271) <= \<const0>\;
  LOCKSTEP_Master_Out(3272) <= \<const0>\;
  LOCKSTEP_Master_Out(3273) <= \<const0>\;
  LOCKSTEP_Master_Out(3274) <= \<const0>\;
  LOCKSTEP_Master_Out(3275) <= \<const0>\;
  LOCKSTEP_Master_Out(3276) <= \<const0>\;
  LOCKSTEP_Master_Out(3277) <= \<const0>\;
  LOCKSTEP_Master_Out(3278) <= \<const0>\;
  LOCKSTEP_Master_Out(3279) <= \<const0>\;
  LOCKSTEP_Master_Out(3280) <= \<const0>\;
  LOCKSTEP_Master_Out(3281) <= \<const0>\;
  LOCKSTEP_Master_Out(3282) <= \<const0>\;
  LOCKSTEP_Master_Out(3283) <= \<const0>\;
  LOCKSTEP_Master_Out(3284) <= \<const0>\;
  LOCKSTEP_Master_Out(3285) <= \<const0>\;
  LOCKSTEP_Master_Out(3286) <= \<const0>\;
  LOCKSTEP_Master_Out(3287) <= \<const0>\;
  LOCKSTEP_Master_Out(3288) <= \<const0>\;
  LOCKSTEP_Master_Out(3289) <= \<const0>\;
  LOCKSTEP_Master_Out(3290) <= \<const0>\;
  LOCKSTEP_Master_Out(3291) <= \<const0>\;
  LOCKSTEP_Master_Out(3292) <= \<const0>\;
  LOCKSTEP_Master_Out(3293) <= \<const0>\;
  LOCKSTEP_Master_Out(3294) <= \<const0>\;
  LOCKSTEP_Master_Out(3295) <= \<const0>\;
  LOCKSTEP_Master_Out(3296) <= \<const0>\;
  LOCKSTEP_Master_Out(3297) <= \<const0>\;
  LOCKSTEP_Master_Out(3298) <= \<const0>\;
  LOCKSTEP_Master_Out(3299) <= \<const0>\;
  LOCKSTEP_Master_Out(3300) <= \<const0>\;
  LOCKSTEP_Master_Out(3301) <= \<const0>\;
  LOCKSTEP_Master_Out(3302) <= \<const0>\;
  LOCKSTEP_Master_Out(3303) <= \<const0>\;
  LOCKSTEP_Master_Out(3304) <= \<const0>\;
  LOCKSTEP_Master_Out(3305) <= \<const0>\;
  LOCKSTEP_Master_Out(3306) <= \<const0>\;
  LOCKSTEP_Master_Out(3307) <= \<const0>\;
  LOCKSTEP_Master_Out(3308) <= \<const0>\;
  LOCKSTEP_Master_Out(3309) <= \<const0>\;
  LOCKSTEP_Master_Out(3310) <= \<const0>\;
  LOCKSTEP_Master_Out(3311) <= \<const0>\;
  LOCKSTEP_Master_Out(3312) <= \<const0>\;
  LOCKSTEP_Master_Out(3313) <= \<const0>\;
  LOCKSTEP_Master_Out(3314) <= \<const0>\;
  LOCKSTEP_Master_Out(3315) <= \<const0>\;
  LOCKSTEP_Master_Out(3316) <= \<const0>\;
  LOCKSTEP_Master_Out(3317) <= \<const0>\;
  LOCKSTEP_Master_Out(3318) <= \<const0>\;
  LOCKSTEP_Master_Out(3319) <= \<const0>\;
  LOCKSTEP_Master_Out(3320) <= \<const0>\;
  LOCKSTEP_Master_Out(3321) <= \<const0>\;
  LOCKSTEP_Master_Out(3322) <= \<const0>\;
  LOCKSTEP_Master_Out(3323) <= \<const0>\;
  LOCKSTEP_Master_Out(3324) <= \<const0>\;
  LOCKSTEP_Master_Out(3325) <= \<const0>\;
  LOCKSTEP_Master_Out(3326) <= \<const0>\;
  LOCKSTEP_Master_Out(3327) <= \<const0>\;
  LOCKSTEP_Master_Out(3328) <= \<const0>\;
  LOCKSTEP_Master_Out(3329) <= \<const0>\;
  LOCKSTEP_Master_Out(3330) <= \<const0>\;
  LOCKSTEP_Master_Out(3331) <= \<const0>\;
  LOCKSTEP_Master_Out(3332) <= \<const0>\;
  LOCKSTEP_Master_Out(3333) <= \<const0>\;
  LOCKSTEP_Master_Out(3334) <= \<const0>\;
  LOCKSTEP_Master_Out(3335) <= \<const0>\;
  LOCKSTEP_Master_Out(3336) <= \<const0>\;
  LOCKSTEP_Master_Out(3337) <= \<const0>\;
  LOCKSTEP_Master_Out(3338) <= \<const0>\;
  LOCKSTEP_Master_Out(3339) <= \<const0>\;
  LOCKSTEP_Master_Out(3340) <= \<const0>\;
  LOCKSTEP_Master_Out(3341) <= \<const0>\;
  LOCKSTEP_Master_Out(3342) <= \<const0>\;
  LOCKSTEP_Master_Out(3343) <= \<const0>\;
  LOCKSTEP_Master_Out(3344) <= \<const0>\;
  LOCKSTEP_Master_Out(3345) <= \<const0>\;
  LOCKSTEP_Master_Out(3346) <= \<const0>\;
  LOCKSTEP_Master_Out(3347) <= \<const0>\;
  LOCKSTEP_Master_Out(3348) <= \<const0>\;
  LOCKSTEP_Master_Out(3349) <= \<const0>\;
  LOCKSTEP_Master_Out(3350) <= \<const0>\;
  LOCKSTEP_Master_Out(3351) <= \<const0>\;
  LOCKSTEP_Master_Out(3352) <= \<const0>\;
  LOCKSTEP_Master_Out(3353) <= \<const0>\;
  LOCKSTEP_Master_Out(3354) <= \<const0>\;
  LOCKSTEP_Master_Out(3355) <= \<const0>\;
  LOCKSTEP_Master_Out(3356) <= \<const0>\;
  LOCKSTEP_Master_Out(3357) <= \<const0>\;
  LOCKSTEP_Master_Out(3358) <= \<const0>\;
  LOCKSTEP_Master_Out(3359) <= \<const0>\;
  LOCKSTEP_Master_Out(3360) <= \<const0>\;
  LOCKSTEP_Master_Out(3361) <= \<const0>\;
  LOCKSTEP_Master_Out(3362) <= \<const0>\;
  LOCKSTEP_Master_Out(3363) <= \<const0>\;
  LOCKSTEP_Master_Out(3364) <= \<const0>\;
  LOCKSTEP_Master_Out(3365) <= \<const0>\;
  LOCKSTEP_Master_Out(3366) <= \<const0>\;
  LOCKSTEP_Master_Out(3367) <= \<const0>\;
  LOCKSTEP_Master_Out(3368) <= \<const0>\;
  LOCKSTEP_Master_Out(3369) <= \<const0>\;
  LOCKSTEP_Master_Out(3370) <= \<const0>\;
  LOCKSTEP_Master_Out(3371) <= \<const0>\;
  LOCKSTEP_Master_Out(3372) <= \<const0>\;
  LOCKSTEP_Master_Out(3373) <= \<const0>\;
  LOCKSTEP_Master_Out(3374) <= \<const0>\;
  LOCKSTEP_Master_Out(3375) <= \<const0>\;
  LOCKSTEP_Master_Out(3376) <= \<const0>\;
  LOCKSTEP_Master_Out(3377) <= \<const0>\;
  LOCKSTEP_Master_Out(3378) <= \<const0>\;
  LOCKSTEP_Master_Out(3379) <= \<const0>\;
  LOCKSTEP_Master_Out(3380) <= \<const0>\;
  LOCKSTEP_Master_Out(3381) <= \<const0>\;
  LOCKSTEP_Master_Out(3382) <= \<const0>\;
  LOCKSTEP_Master_Out(3383) <= \<const0>\;
  LOCKSTEP_Master_Out(3384) <= \<const0>\;
  LOCKSTEP_Master_Out(3385) <= \<const0>\;
  LOCKSTEP_Master_Out(3386) <= \<const0>\;
  LOCKSTEP_Master_Out(3387) <= \<const0>\;
  LOCKSTEP_Master_Out(3388) <= \<const0>\;
  LOCKSTEP_Master_Out(3389) <= \<const0>\;
  LOCKSTEP_Master_Out(3390) <= \<const0>\;
  LOCKSTEP_Master_Out(3391) <= \<const0>\;
  LOCKSTEP_Master_Out(3392) <= \<const0>\;
  LOCKSTEP_Master_Out(3393) <= \<const0>\;
  LOCKSTEP_Master_Out(3394) <= \<const0>\;
  LOCKSTEP_Master_Out(3395) <= \<const0>\;
  LOCKSTEP_Master_Out(3396) <= \<const0>\;
  LOCKSTEP_Master_Out(3397) <= \<const0>\;
  LOCKSTEP_Master_Out(3398) <= \<const0>\;
  LOCKSTEP_Master_Out(3399) <= \<const0>\;
  LOCKSTEP_Master_Out(3400) <= \<const0>\;
  LOCKSTEP_Master_Out(3401) <= \<const0>\;
  LOCKSTEP_Master_Out(3402) <= \<const0>\;
  LOCKSTEP_Master_Out(3403) <= \<const0>\;
  LOCKSTEP_Master_Out(3404) <= \<const0>\;
  LOCKSTEP_Master_Out(3405) <= \<const0>\;
  LOCKSTEP_Master_Out(3406) <= \<const0>\;
  LOCKSTEP_Master_Out(3407) <= \<const0>\;
  LOCKSTEP_Master_Out(3408) <= \<const0>\;
  LOCKSTEP_Master_Out(3409) <= \<const0>\;
  LOCKSTEP_Master_Out(3410) <= \<const0>\;
  LOCKSTEP_Master_Out(3411) <= \<const0>\;
  LOCKSTEP_Master_Out(3412) <= \<const0>\;
  LOCKSTEP_Master_Out(3413) <= \<const0>\;
  LOCKSTEP_Master_Out(3414) <= \<const0>\;
  LOCKSTEP_Master_Out(3415) <= \<const0>\;
  LOCKSTEP_Master_Out(3416) <= \<const0>\;
  LOCKSTEP_Master_Out(3417) <= \<const0>\;
  LOCKSTEP_Master_Out(3418) <= \<const0>\;
  LOCKSTEP_Master_Out(3419) <= \<const0>\;
  LOCKSTEP_Master_Out(3420) <= \<const0>\;
  LOCKSTEP_Master_Out(3421) <= \<const0>\;
  LOCKSTEP_Master_Out(3422) <= \<const0>\;
  LOCKSTEP_Master_Out(3423) <= \<const0>\;
  LOCKSTEP_Master_Out(3424) <= \<const0>\;
  LOCKSTEP_Master_Out(3425) <= \<const0>\;
  LOCKSTEP_Master_Out(3426) <= \<const0>\;
  LOCKSTEP_Master_Out(3427) <= \<const0>\;
  LOCKSTEP_Master_Out(3428) <= \<const0>\;
  LOCKSTEP_Master_Out(3429) <= \<const0>\;
  LOCKSTEP_Master_Out(3430) <= \<const0>\;
  LOCKSTEP_Master_Out(3431) <= \<const0>\;
  LOCKSTEP_Master_Out(3432) <= \<const0>\;
  LOCKSTEP_Master_Out(3433) <= \<const0>\;
  LOCKSTEP_Master_Out(3434) <= \<const0>\;
  LOCKSTEP_Master_Out(3435) <= \<const0>\;
  LOCKSTEP_Master_Out(3436) <= \<const0>\;
  LOCKSTEP_Master_Out(3437) <= \<const0>\;
  LOCKSTEP_Master_Out(3438) <= \<const0>\;
  LOCKSTEP_Master_Out(3439) <= \<const0>\;
  LOCKSTEP_Master_Out(3440) <= \<const0>\;
  LOCKSTEP_Master_Out(3441) <= \<const0>\;
  LOCKSTEP_Master_Out(3442) <= \<const0>\;
  LOCKSTEP_Master_Out(3443) <= \<const0>\;
  LOCKSTEP_Master_Out(3444) <= \<const0>\;
  LOCKSTEP_Master_Out(3445) <= \<const0>\;
  LOCKSTEP_Master_Out(3446) <= \<const0>\;
  LOCKSTEP_Master_Out(3447) <= \<const0>\;
  LOCKSTEP_Master_Out(3448) <= \<const0>\;
  LOCKSTEP_Master_Out(3449) <= \<const0>\;
  LOCKSTEP_Master_Out(3450) <= \<const0>\;
  LOCKSTEP_Master_Out(3451) <= \<const0>\;
  LOCKSTEP_Master_Out(3452) <= \<const0>\;
  LOCKSTEP_Master_Out(3453) <= \<const0>\;
  LOCKSTEP_Master_Out(3454) <= \<const0>\;
  LOCKSTEP_Master_Out(3455) <= \<const0>\;
  LOCKSTEP_Master_Out(3456) <= \<const0>\;
  LOCKSTEP_Master_Out(3457) <= \<const0>\;
  LOCKSTEP_Master_Out(3458) <= \<const0>\;
  LOCKSTEP_Master_Out(3459) <= \<const0>\;
  LOCKSTEP_Master_Out(3460) <= \<const0>\;
  LOCKSTEP_Master_Out(3461) <= \<const0>\;
  LOCKSTEP_Master_Out(3462) <= \<const0>\;
  LOCKSTEP_Master_Out(3463) <= \<const0>\;
  LOCKSTEP_Master_Out(3464) <= \<const0>\;
  LOCKSTEP_Master_Out(3465) <= \<const0>\;
  LOCKSTEP_Master_Out(3466) <= \<const0>\;
  LOCKSTEP_Master_Out(3467) <= \<const0>\;
  LOCKSTEP_Master_Out(3468) <= \<const0>\;
  LOCKSTEP_Master_Out(3469) <= \<const0>\;
  LOCKSTEP_Master_Out(3470) <= \<const0>\;
  LOCKSTEP_Master_Out(3471) <= \<const0>\;
  LOCKSTEP_Master_Out(3472) <= \<const0>\;
  LOCKSTEP_Master_Out(3473) <= \<const0>\;
  LOCKSTEP_Master_Out(3474) <= \<const0>\;
  LOCKSTEP_Master_Out(3475) <= \<const0>\;
  LOCKSTEP_Master_Out(3476) <= \<const0>\;
  LOCKSTEP_Master_Out(3477) <= \<const0>\;
  LOCKSTEP_Master_Out(3478) <= \<const0>\;
  LOCKSTEP_Master_Out(3479) <= \<const0>\;
  LOCKSTEP_Master_Out(3480) <= \<const0>\;
  LOCKSTEP_Master_Out(3481) <= \<const0>\;
  LOCKSTEP_Master_Out(3482) <= \<const0>\;
  LOCKSTEP_Master_Out(3483) <= \<const0>\;
  LOCKSTEP_Master_Out(3484) <= \<const0>\;
  LOCKSTEP_Master_Out(3485) <= \<const0>\;
  LOCKSTEP_Master_Out(3486) <= \<const0>\;
  LOCKSTEP_Master_Out(3487) <= \<const0>\;
  LOCKSTEP_Master_Out(3488) <= \<const0>\;
  LOCKSTEP_Master_Out(3489) <= \<const0>\;
  LOCKSTEP_Master_Out(3490) <= \<const0>\;
  LOCKSTEP_Master_Out(3491) <= \<const0>\;
  LOCKSTEP_Master_Out(3492) <= \<const0>\;
  LOCKSTEP_Master_Out(3493) <= \<const0>\;
  LOCKSTEP_Master_Out(3494) <= \<const0>\;
  LOCKSTEP_Master_Out(3495) <= \<const0>\;
  LOCKSTEP_Master_Out(3496) <= \<const0>\;
  LOCKSTEP_Master_Out(3497) <= \<const0>\;
  LOCKSTEP_Master_Out(3498) <= \<const0>\;
  LOCKSTEP_Master_Out(3499) <= \<const0>\;
  LOCKSTEP_Master_Out(3500) <= \<const0>\;
  LOCKSTEP_Master_Out(3501) <= \<const0>\;
  LOCKSTEP_Master_Out(3502) <= \<const0>\;
  LOCKSTEP_Master_Out(3503) <= \<const0>\;
  LOCKSTEP_Master_Out(3504) <= \<const0>\;
  LOCKSTEP_Master_Out(3505) <= \<const0>\;
  LOCKSTEP_Master_Out(3506) <= \<const0>\;
  LOCKSTEP_Master_Out(3507) <= \<const0>\;
  LOCKSTEP_Master_Out(3508) <= \<const0>\;
  LOCKSTEP_Master_Out(3509) <= \<const0>\;
  LOCKSTEP_Master_Out(3510) <= \<const0>\;
  LOCKSTEP_Master_Out(3511) <= \<const0>\;
  LOCKSTEP_Master_Out(3512) <= \<const0>\;
  LOCKSTEP_Master_Out(3513) <= \<const0>\;
  LOCKSTEP_Master_Out(3514) <= \<const0>\;
  LOCKSTEP_Master_Out(3515) <= \<const0>\;
  LOCKSTEP_Master_Out(3516) <= \<const0>\;
  LOCKSTEP_Master_Out(3517) <= \<const0>\;
  LOCKSTEP_Master_Out(3518) <= \<const0>\;
  LOCKSTEP_Master_Out(3519) <= \<const0>\;
  LOCKSTEP_Master_Out(3520) <= \<const0>\;
  LOCKSTEP_Master_Out(3521) <= \<const0>\;
  LOCKSTEP_Master_Out(3522) <= \<const0>\;
  LOCKSTEP_Master_Out(3523) <= \<const0>\;
  LOCKSTEP_Master_Out(3524) <= \<const0>\;
  LOCKSTEP_Master_Out(3525) <= \<const0>\;
  LOCKSTEP_Master_Out(3526) <= \<const0>\;
  LOCKSTEP_Master_Out(3527) <= \<const0>\;
  LOCKSTEP_Master_Out(3528) <= \<const0>\;
  LOCKSTEP_Master_Out(3529) <= \<const0>\;
  LOCKSTEP_Master_Out(3530) <= \<const0>\;
  LOCKSTEP_Master_Out(3531) <= \<const0>\;
  LOCKSTEP_Master_Out(3532) <= \<const0>\;
  LOCKSTEP_Master_Out(3533) <= \<const0>\;
  LOCKSTEP_Master_Out(3534) <= \<const0>\;
  LOCKSTEP_Master_Out(3535) <= \<const0>\;
  LOCKSTEP_Master_Out(3536) <= \<const0>\;
  LOCKSTEP_Master_Out(3537) <= \<const0>\;
  LOCKSTEP_Master_Out(3538) <= \<const0>\;
  LOCKSTEP_Master_Out(3539) <= \<const0>\;
  LOCKSTEP_Master_Out(3540) <= \<const0>\;
  LOCKSTEP_Master_Out(3541) <= \<const0>\;
  LOCKSTEP_Master_Out(3542) <= \<const0>\;
  LOCKSTEP_Master_Out(3543) <= \<const0>\;
  LOCKSTEP_Master_Out(3544) <= \<const0>\;
  LOCKSTEP_Master_Out(3545) <= \<const0>\;
  LOCKSTEP_Master_Out(3546) <= \<const0>\;
  LOCKSTEP_Master_Out(3547) <= \<const0>\;
  LOCKSTEP_Master_Out(3548) <= \<const0>\;
  LOCKSTEP_Master_Out(3549) <= \<const0>\;
  LOCKSTEP_Master_Out(3550) <= \<const0>\;
  LOCKSTEP_Master_Out(3551) <= \<const0>\;
  LOCKSTEP_Master_Out(3552) <= \<const0>\;
  LOCKSTEP_Master_Out(3553) <= \<const0>\;
  LOCKSTEP_Master_Out(3554) <= \<const0>\;
  LOCKSTEP_Master_Out(3555) <= \<const0>\;
  LOCKSTEP_Master_Out(3556) <= \<const0>\;
  LOCKSTEP_Master_Out(3557) <= \<const0>\;
  LOCKSTEP_Master_Out(3558) <= \<const0>\;
  LOCKSTEP_Master_Out(3559) <= \<const0>\;
  LOCKSTEP_Master_Out(3560) <= \<const0>\;
  LOCKSTEP_Master_Out(3561) <= \<const0>\;
  LOCKSTEP_Master_Out(3562) <= \<const0>\;
  LOCKSTEP_Master_Out(3563) <= \<const0>\;
  LOCKSTEP_Master_Out(3564) <= \<const0>\;
  LOCKSTEP_Master_Out(3565) <= \<const0>\;
  LOCKSTEP_Master_Out(3566) <= \<const0>\;
  LOCKSTEP_Master_Out(3567) <= \<const0>\;
  LOCKSTEP_Master_Out(3568) <= \<const0>\;
  LOCKSTEP_Master_Out(3569) <= \<const0>\;
  LOCKSTEP_Master_Out(3570) <= \<const0>\;
  LOCKSTEP_Master_Out(3571) <= \<const0>\;
  LOCKSTEP_Master_Out(3572) <= \<const0>\;
  LOCKSTEP_Master_Out(3573) <= \<const0>\;
  LOCKSTEP_Master_Out(3574) <= \<const0>\;
  LOCKSTEP_Master_Out(3575) <= \<const0>\;
  LOCKSTEP_Master_Out(3576) <= \<const0>\;
  LOCKSTEP_Master_Out(3577) <= \<const0>\;
  LOCKSTEP_Master_Out(3578) <= \<const0>\;
  LOCKSTEP_Master_Out(3579) <= \<const0>\;
  LOCKSTEP_Master_Out(3580) <= \<const0>\;
  LOCKSTEP_Master_Out(3581) <= \<const0>\;
  LOCKSTEP_Master_Out(3582) <= \<const0>\;
  LOCKSTEP_Master_Out(3583) <= \<const0>\;
  LOCKSTEP_Master_Out(3584) <= \<const0>\;
  LOCKSTEP_Master_Out(3585) <= \<const0>\;
  LOCKSTEP_Master_Out(3586) <= \<const0>\;
  LOCKSTEP_Master_Out(3587) <= \<const0>\;
  LOCKSTEP_Master_Out(3588) <= \<const0>\;
  LOCKSTEP_Master_Out(3589) <= \<const0>\;
  LOCKSTEP_Master_Out(3590) <= \<const0>\;
  LOCKSTEP_Master_Out(3591) <= \<const0>\;
  LOCKSTEP_Master_Out(3592) <= \<const0>\;
  LOCKSTEP_Master_Out(3593) <= \<const0>\;
  LOCKSTEP_Master_Out(3594) <= \<const0>\;
  LOCKSTEP_Master_Out(3595) <= \<const0>\;
  LOCKSTEP_Master_Out(3596) <= \<const0>\;
  LOCKSTEP_Master_Out(3597) <= \<const0>\;
  LOCKSTEP_Master_Out(3598) <= \<const0>\;
  LOCKSTEP_Master_Out(3599) <= \<const0>\;
  LOCKSTEP_Master_Out(3600) <= \<const0>\;
  LOCKSTEP_Master_Out(3601) <= \<const0>\;
  LOCKSTEP_Master_Out(3602) <= \<const0>\;
  LOCKSTEP_Master_Out(3603) <= \<const0>\;
  LOCKSTEP_Master_Out(3604) <= \<const0>\;
  LOCKSTEP_Master_Out(3605) <= \<const0>\;
  LOCKSTEP_Master_Out(3606) <= \<const0>\;
  LOCKSTEP_Master_Out(3607) <= \<const0>\;
  LOCKSTEP_Master_Out(3608) <= \<const0>\;
  LOCKSTEP_Master_Out(3609) <= \<const0>\;
  LOCKSTEP_Master_Out(3610) <= \<const0>\;
  LOCKSTEP_Master_Out(3611) <= \<const0>\;
  LOCKSTEP_Master_Out(3612) <= \<const0>\;
  LOCKSTEP_Master_Out(3613) <= \<const0>\;
  LOCKSTEP_Master_Out(3614) <= \<const0>\;
  LOCKSTEP_Master_Out(3615) <= \<const0>\;
  LOCKSTEP_Master_Out(3616) <= \<const0>\;
  LOCKSTEP_Master_Out(3617) <= \<const0>\;
  LOCKSTEP_Master_Out(3618) <= \<const0>\;
  LOCKSTEP_Master_Out(3619) <= \<const0>\;
  LOCKSTEP_Master_Out(3620) <= \<const0>\;
  LOCKSTEP_Master_Out(3621) <= \<const0>\;
  LOCKSTEP_Master_Out(3622) <= \<const0>\;
  LOCKSTEP_Master_Out(3623) <= \<const0>\;
  LOCKSTEP_Master_Out(3624) <= \<const0>\;
  LOCKSTEP_Master_Out(3625) <= \<const0>\;
  LOCKSTEP_Master_Out(3626) <= \<const0>\;
  LOCKSTEP_Master_Out(3627) <= \<const0>\;
  LOCKSTEP_Master_Out(3628) <= \<const0>\;
  LOCKSTEP_Master_Out(3629) <= \<const0>\;
  LOCKSTEP_Master_Out(3630) <= \<const0>\;
  LOCKSTEP_Master_Out(3631) <= \<const0>\;
  LOCKSTEP_Master_Out(3632) <= \<const0>\;
  LOCKSTEP_Master_Out(3633) <= \<const0>\;
  LOCKSTEP_Master_Out(3634) <= \<const0>\;
  LOCKSTEP_Master_Out(3635) <= \<const0>\;
  LOCKSTEP_Master_Out(3636) <= \<const0>\;
  LOCKSTEP_Master_Out(3637) <= \<const0>\;
  LOCKSTEP_Master_Out(3638) <= \<const0>\;
  LOCKSTEP_Master_Out(3639) <= \<const0>\;
  LOCKSTEP_Master_Out(3640) <= \<const0>\;
  LOCKSTEP_Master_Out(3641) <= \<const0>\;
  LOCKSTEP_Master_Out(3642) <= \<const0>\;
  LOCKSTEP_Master_Out(3643) <= \<const0>\;
  LOCKSTEP_Master_Out(3644) <= \<const0>\;
  LOCKSTEP_Master_Out(3645) <= \<const0>\;
  LOCKSTEP_Master_Out(3646) <= \<const0>\;
  LOCKSTEP_Master_Out(3647) <= \<const0>\;
  LOCKSTEP_Master_Out(3648) <= \<const0>\;
  LOCKSTEP_Master_Out(3649) <= \<const0>\;
  LOCKSTEP_Master_Out(3650) <= \<const0>\;
  LOCKSTEP_Master_Out(3651) <= \<const0>\;
  LOCKSTEP_Master_Out(3652) <= \<const0>\;
  LOCKSTEP_Master_Out(3653) <= \<const0>\;
  LOCKSTEP_Master_Out(3654) <= \<const0>\;
  LOCKSTEP_Master_Out(3655) <= \<const0>\;
  LOCKSTEP_Master_Out(3656) <= \<const0>\;
  LOCKSTEP_Master_Out(3657) <= \<const0>\;
  LOCKSTEP_Master_Out(3658) <= \<const0>\;
  LOCKSTEP_Master_Out(3659) <= \<const0>\;
  LOCKSTEP_Master_Out(3660) <= \<const0>\;
  LOCKSTEP_Master_Out(3661) <= \<const0>\;
  LOCKSTEP_Master_Out(3662) <= \<const0>\;
  LOCKSTEP_Master_Out(3663) <= \<const0>\;
  LOCKSTEP_Master_Out(3664) <= \<const0>\;
  LOCKSTEP_Master_Out(3665) <= \<const0>\;
  LOCKSTEP_Master_Out(3666) <= \<const0>\;
  LOCKSTEP_Master_Out(3667) <= \<const0>\;
  LOCKSTEP_Master_Out(3668) <= \<const0>\;
  LOCKSTEP_Master_Out(3669) <= \<const0>\;
  LOCKSTEP_Master_Out(3670) <= \<const0>\;
  LOCKSTEP_Master_Out(3671) <= \<const0>\;
  LOCKSTEP_Master_Out(3672) <= \<const0>\;
  LOCKSTEP_Master_Out(3673) <= \<const0>\;
  LOCKSTEP_Master_Out(3674) <= \<const0>\;
  LOCKSTEP_Master_Out(3675) <= \<const0>\;
  LOCKSTEP_Master_Out(3676) <= \<const0>\;
  LOCKSTEP_Master_Out(3677) <= \<const0>\;
  LOCKSTEP_Master_Out(3678) <= \<const0>\;
  LOCKSTEP_Master_Out(3679) <= \<const0>\;
  LOCKSTEP_Master_Out(3680) <= \<const0>\;
  LOCKSTEP_Master_Out(3681) <= \<const0>\;
  LOCKSTEP_Master_Out(3682) <= \<const0>\;
  LOCKSTEP_Master_Out(3683) <= \<const0>\;
  LOCKSTEP_Master_Out(3684) <= \<const0>\;
  LOCKSTEP_Master_Out(3685) <= \<const0>\;
  LOCKSTEP_Master_Out(3686) <= \<const0>\;
  LOCKSTEP_Master_Out(3687) <= \<const0>\;
  LOCKSTEP_Master_Out(3688) <= \<const0>\;
  LOCKSTEP_Master_Out(3689) <= \<const0>\;
  LOCKSTEP_Master_Out(3690) <= \<const0>\;
  LOCKSTEP_Master_Out(3691) <= \<const0>\;
  LOCKSTEP_Master_Out(3692) <= \<const0>\;
  LOCKSTEP_Master_Out(3693) <= \<const0>\;
  LOCKSTEP_Master_Out(3694) <= \<const0>\;
  LOCKSTEP_Master_Out(3695) <= \<const0>\;
  LOCKSTEP_Master_Out(3696) <= \<const0>\;
  LOCKSTEP_Master_Out(3697) <= \<const0>\;
  LOCKSTEP_Master_Out(3698) <= \<const0>\;
  LOCKSTEP_Master_Out(3699) <= \<const0>\;
  LOCKSTEP_Master_Out(3700) <= \<const0>\;
  LOCKSTEP_Master_Out(3701) <= \<const0>\;
  LOCKSTEP_Master_Out(3702) <= \<const0>\;
  LOCKSTEP_Master_Out(3703) <= \<const0>\;
  LOCKSTEP_Master_Out(3704) <= \<const0>\;
  LOCKSTEP_Master_Out(3705) <= \<const0>\;
  LOCKSTEP_Master_Out(3706) <= \<const0>\;
  LOCKSTEP_Master_Out(3707) <= \<const0>\;
  LOCKSTEP_Master_Out(3708) <= \<const0>\;
  LOCKSTEP_Master_Out(3709) <= \<const0>\;
  LOCKSTEP_Master_Out(3710) <= \<const0>\;
  LOCKSTEP_Master_Out(3711) <= \<const0>\;
  LOCKSTEP_Master_Out(3712) <= \<const0>\;
  LOCKSTEP_Master_Out(3713) <= \<const0>\;
  LOCKSTEP_Master_Out(3714) <= \<const0>\;
  LOCKSTEP_Master_Out(3715) <= \<const0>\;
  LOCKSTEP_Master_Out(3716) <= \<const0>\;
  LOCKSTEP_Master_Out(3717) <= \<const0>\;
  LOCKSTEP_Master_Out(3718) <= \<const0>\;
  LOCKSTEP_Master_Out(3719) <= \<const0>\;
  LOCKSTEP_Master_Out(3720) <= \<const0>\;
  LOCKSTEP_Master_Out(3721) <= \<const0>\;
  LOCKSTEP_Master_Out(3722) <= \<const0>\;
  LOCKSTEP_Master_Out(3723) <= \<const0>\;
  LOCKSTEP_Master_Out(3724) <= \<const0>\;
  LOCKSTEP_Master_Out(3725) <= \<const0>\;
  LOCKSTEP_Master_Out(3726) <= \<const0>\;
  LOCKSTEP_Master_Out(3727) <= \<const0>\;
  LOCKSTEP_Master_Out(3728) <= \<const0>\;
  LOCKSTEP_Master_Out(3729) <= \<const0>\;
  LOCKSTEP_Master_Out(3730) <= \<const0>\;
  LOCKSTEP_Master_Out(3731) <= \<const0>\;
  LOCKSTEP_Master_Out(3732) <= \<const0>\;
  LOCKSTEP_Master_Out(3733) <= \<const0>\;
  LOCKSTEP_Master_Out(3734) <= \<const0>\;
  LOCKSTEP_Master_Out(3735) <= \<const0>\;
  LOCKSTEP_Master_Out(3736) <= \<const0>\;
  LOCKSTEP_Master_Out(3737) <= \<const0>\;
  LOCKSTEP_Master_Out(3738) <= \<const0>\;
  LOCKSTEP_Master_Out(3739) <= \<const0>\;
  LOCKSTEP_Master_Out(3740) <= \<const0>\;
  LOCKSTEP_Master_Out(3741) <= \<const0>\;
  LOCKSTEP_Master_Out(3742) <= \<const0>\;
  LOCKSTEP_Master_Out(3743) <= \<const0>\;
  LOCKSTEP_Master_Out(3744) <= \<const0>\;
  LOCKSTEP_Master_Out(3745) <= \<const0>\;
  LOCKSTEP_Master_Out(3746) <= \<const0>\;
  LOCKSTEP_Master_Out(3747) <= \<const0>\;
  LOCKSTEP_Master_Out(3748) <= \<const0>\;
  LOCKSTEP_Master_Out(3749) <= \<const0>\;
  LOCKSTEP_Master_Out(3750) <= \<const0>\;
  LOCKSTEP_Master_Out(3751) <= \<const0>\;
  LOCKSTEP_Master_Out(3752) <= \<const0>\;
  LOCKSTEP_Master_Out(3753) <= \<const0>\;
  LOCKSTEP_Master_Out(3754) <= \<const0>\;
  LOCKSTEP_Master_Out(3755) <= \<const0>\;
  LOCKSTEP_Master_Out(3756) <= \<const0>\;
  LOCKSTEP_Master_Out(3757) <= \<const0>\;
  LOCKSTEP_Master_Out(3758) <= \<const0>\;
  LOCKSTEP_Master_Out(3759) <= \<const0>\;
  LOCKSTEP_Master_Out(3760) <= \<const0>\;
  LOCKSTEP_Master_Out(3761) <= \<const0>\;
  LOCKSTEP_Master_Out(3762) <= \<const0>\;
  LOCKSTEP_Master_Out(3763) <= \<const0>\;
  LOCKSTEP_Master_Out(3764) <= \<const0>\;
  LOCKSTEP_Master_Out(3765) <= \<const0>\;
  LOCKSTEP_Master_Out(3766) <= \<const0>\;
  LOCKSTEP_Master_Out(3767) <= \<const0>\;
  LOCKSTEP_Master_Out(3768) <= \<const0>\;
  LOCKSTEP_Master_Out(3769) <= \<const0>\;
  LOCKSTEP_Master_Out(3770) <= \<const0>\;
  LOCKSTEP_Master_Out(3771) <= \<const0>\;
  LOCKSTEP_Master_Out(3772) <= \<const0>\;
  LOCKSTEP_Master_Out(3773) <= \<const0>\;
  LOCKSTEP_Master_Out(3774) <= \<const0>\;
  LOCKSTEP_Master_Out(3775) <= \<const0>\;
  LOCKSTEP_Master_Out(3776) <= \<const0>\;
  LOCKSTEP_Master_Out(3777) <= \<const0>\;
  LOCKSTEP_Master_Out(3778) <= \<const0>\;
  LOCKSTEP_Master_Out(3779) <= \<const0>\;
  LOCKSTEP_Master_Out(3780) <= \<const0>\;
  LOCKSTEP_Master_Out(3781) <= \<const0>\;
  LOCKSTEP_Master_Out(3782) <= \<const0>\;
  LOCKSTEP_Master_Out(3783) <= \<const0>\;
  LOCKSTEP_Master_Out(3784) <= \<const0>\;
  LOCKSTEP_Master_Out(3785) <= \<const0>\;
  LOCKSTEP_Master_Out(3786) <= \<const0>\;
  LOCKSTEP_Master_Out(3787) <= \<const0>\;
  LOCKSTEP_Master_Out(3788) <= \<const0>\;
  LOCKSTEP_Master_Out(3789) <= \<const0>\;
  LOCKSTEP_Master_Out(3790) <= \<const0>\;
  LOCKSTEP_Master_Out(3791) <= \<const0>\;
  LOCKSTEP_Master_Out(3792) <= \<const0>\;
  LOCKSTEP_Master_Out(3793) <= \<const0>\;
  LOCKSTEP_Master_Out(3794) <= \<const0>\;
  LOCKSTEP_Master_Out(3795) <= \<const0>\;
  LOCKSTEP_Master_Out(3796) <= \<const0>\;
  LOCKSTEP_Master_Out(3797) <= \<const0>\;
  LOCKSTEP_Master_Out(3798) <= \<const0>\;
  LOCKSTEP_Master_Out(3799) <= \<const0>\;
  LOCKSTEP_Master_Out(3800) <= \<const0>\;
  LOCKSTEP_Master_Out(3801) <= \<const0>\;
  LOCKSTEP_Master_Out(3802) <= \<const0>\;
  LOCKSTEP_Master_Out(3803) <= \<const0>\;
  LOCKSTEP_Master_Out(3804) <= \<const0>\;
  LOCKSTEP_Master_Out(3805) <= \<const0>\;
  LOCKSTEP_Master_Out(3806) <= \<const0>\;
  LOCKSTEP_Master_Out(3807) <= \<const0>\;
  LOCKSTEP_Master_Out(3808) <= \<const0>\;
  LOCKSTEP_Master_Out(3809) <= \<const0>\;
  LOCKSTEP_Master_Out(3810) <= \<const0>\;
  LOCKSTEP_Master_Out(3811) <= \<const0>\;
  LOCKSTEP_Master_Out(3812) <= \<const0>\;
  LOCKSTEP_Master_Out(3813) <= \<const0>\;
  LOCKSTEP_Master_Out(3814) <= \<const0>\;
  LOCKSTEP_Master_Out(3815) <= \<const0>\;
  LOCKSTEP_Master_Out(3816) <= \<const0>\;
  LOCKSTEP_Master_Out(3817) <= \<const0>\;
  LOCKSTEP_Master_Out(3818) <= \<const0>\;
  LOCKSTEP_Master_Out(3819) <= \<const0>\;
  LOCKSTEP_Master_Out(3820) <= \<const0>\;
  LOCKSTEP_Master_Out(3821) <= \<const0>\;
  LOCKSTEP_Master_Out(3822) <= \<const0>\;
  LOCKSTEP_Master_Out(3823) <= \<const0>\;
  LOCKSTEP_Master_Out(3824) <= \<const0>\;
  LOCKSTEP_Master_Out(3825) <= \<const0>\;
  LOCKSTEP_Master_Out(3826) <= \<const0>\;
  LOCKSTEP_Master_Out(3827) <= \<const0>\;
  LOCKSTEP_Master_Out(3828) <= \<const0>\;
  LOCKSTEP_Master_Out(3829) <= \<const0>\;
  LOCKSTEP_Master_Out(3830) <= \<const0>\;
  LOCKSTEP_Master_Out(3831) <= \<const0>\;
  LOCKSTEP_Master_Out(3832) <= \<const0>\;
  LOCKSTEP_Master_Out(3833) <= \<const0>\;
  LOCKSTEP_Master_Out(3834) <= \<const0>\;
  LOCKSTEP_Master_Out(3835) <= \<const0>\;
  LOCKSTEP_Master_Out(3836) <= \<const0>\;
  LOCKSTEP_Master_Out(3837) <= \<const0>\;
  LOCKSTEP_Master_Out(3838) <= \<const0>\;
  LOCKSTEP_Master_Out(3839) <= \<const0>\;
  LOCKSTEP_Master_Out(3840) <= \<const0>\;
  LOCKSTEP_Master_Out(3841) <= \<const0>\;
  LOCKSTEP_Master_Out(3842) <= \<const0>\;
  LOCKSTEP_Master_Out(3843) <= \<const0>\;
  LOCKSTEP_Master_Out(3844) <= \<const0>\;
  LOCKSTEP_Master_Out(3845) <= \<const0>\;
  LOCKSTEP_Master_Out(3846) <= \<const0>\;
  LOCKSTEP_Master_Out(3847) <= \<const0>\;
  LOCKSTEP_Master_Out(3848) <= \<const0>\;
  LOCKSTEP_Master_Out(3849) <= \<const0>\;
  LOCKSTEP_Master_Out(3850) <= \<const0>\;
  LOCKSTEP_Master_Out(3851) <= \<const0>\;
  LOCKSTEP_Master_Out(3852) <= \<const0>\;
  LOCKSTEP_Master_Out(3853) <= \<const0>\;
  LOCKSTEP_Master_Out(3854) <= \<const0>\;
  LOCKSTEP_Master_Out(3855) <= \<const0>\;
  LOCKSTEP_Master_Out(3856) <= \<const0>\;
  LOCKSTEP_Master_Out(3857) <= \<const0>\;
  LOCKSTEP_Master_Out(3858) <= \<const0>\;
  LOCKSTEP_Master_Out(3859) <= \<const0>\;
  LOCKSTEP_Master_Out(3860) <= \<const0>\;
  LOCKSTEP_Master_Out(3861) <= \<const0>\;
  LOCKSTEP_Master_Out(3862) <= \<const0>\;
  LOCKSTEP_Master_Out(3863) <= \<const0>\;
  LOCKSTEP_Master_Out(3864) <= \<const0>\;
  LOCKSTEP_Master_Out(3865) <= \<const0>\;
  LOCKSTEP_Master_Out(3866) <= \<const0>\;
  LOCKSTEP_Master_Out(3867) <= \<const0>\;
  LOCKSTEP_Master_Out(3868) <= \<const0>\;
  LOCKSTEP_Master_Out(3869) <= \<const0>\;
  LOCKSTEP_Master_Out(3870) <= \<const0>\;
  LOCKSTEP_Master_Out(3871) <= \<const0>\;
  LOCKSTEP_Master_Out(3872) <= \<const0>\;
  LOCKSTEP_Master_Out(3873) <= \<const0>\;
  LOCKSTEP_Master_Out(3874) <= \<const0>\;
  LOCKSTEP_Master_Out(3875) <= \<const0>\;
  LOCKSTEP_Master_Out(3876) <= \<const0>\;
  LOCKSTEP_Master_Out(3877) <= \<const0>\;
  LOCKSTEP_Master_Out(3878) <= \<const0>\;
  LOCKSTEP_Master_Out(3879) <= \<const0>\;
  LOCKSTEP_Master_Out(3880) <= \<const0>\;
  LOCKSTEP_Master_Out(3881) <= \<const0>\;
  LOCKSTEP_Master_Out(3882) <= \<const0>\;
  LOCKSTEP_Master_Out(3883) <= \<const0>\;
  LOCKSTEP_Master_Out(3884) <= \<const0>\;
  LOCKSTEP_Master_Out(3885) <= \<const0>\;
  LOCKSTEP_Master_Out(3886) <= \<const0>\;
  LOCKSTEP_Master_Out(3887) <= \<const0>\;
  LOCKSTEP_Master_Out(3888) <= \<const0>\;
  LOCKSTEP_Master_Out(3889) <= \<const0>\;
  LOCKSTEP_Master_Out(3890) <= \<const0>\;
  LOCKSTEP_Master_Out(3891) <= \<const0>\;
  LOCKSTEP_Master_Out(3892) <= \<const0>\;
  LOCKSTEP_Master_Out(3893) <= \<const0>\;
  LOCKSTEP_Master_Out(3894) <= \<const0>\;
  LOCKSTEP_Master_Out(3895) <= \<const0>\;
  LOCKSTEP_Master_Out(3896) <= \<const0>\;
  LOCKSTEP_Master_Out(3897) <= \<const0>\;
  LOCKSTEP_Master_Out(3898) <= \<const0>\;
  LOCKSTEP_Master_Out(3899) <= \<const0>\;
  LOCKSTEP_Master_Out(3900) <= \<const0>\;
  LOCKSTEP_Master_Out(3901) <= \<const0>\;
  LOCKSTEP_Master_Out(3902) <= \<const0>\;
  LOCKSTEP_Master_Out(3903) <= \<const0>\;
  LOCKSTEP_Master_Out(3904) <= \<const0>\;
  LOCKSTEP_Master_Out(3905) <= \<const0>\;
  LOCKSTEP_Master_Out(3906) <= \<const0>\;
  LOCKSTEP_Master_Out(3907) <= \<const0>\;
  LOCKSTEP_Master_Out(3908) <= \<const0>\;
  LOCKSTEP_Master_Out(3909) <= \<const0>\;
  LOCKSTEP_Master_Out(3910) <= \<const0>\;
  LOCKSTEP_Master_Out(3911) <= \<const0>\;
  LOCKSTEP_Master_Out(3912) <= \<const0>\;
  LOCKSTEP_Master_Out(3913) <= \<const0>\;
  LOCKSTEP_Master_Out(3914) <= \<const0>\;
  LOCKSTEP_Master_Out(3915) <= \<const0>\;
  LOCKSTEP_Master_Out(3916) <= \<const0>\;
  LOCKSTEP_Master_Out(3917) <= \<const0>\;
  LOCKSTEP_Master_Out(3918) <= \<const0>\;
  LOCKSTEP_Master_Out(3919) <= \<const0>\;
  LOCKSTEP_Master_Out(3920) <= \<const0>\;
  LOCKSTEP_Master_Out(3921) <= \<const0>\;
  LOCKSTEP_Master_Out(3922) <= \<const0>\;
  LOCKSTEP_Master_Out(3923) <= \<const0>\;
  LOCKSTEP_Master_Out(3924) <= \<const0>\;
  LOCKSTEP_Master_Out(3925) <= \<const0>\;
  LOCKSTEP_Master_Out(3926) <= \<const0>\;
  LOCKSTEP_Master_Out(3927) <= \<const0>\;
  LOCKSTEP_Master_Out(3928) <= \<const0>\;
  LOCKSTEP_Master_Out(3929) <= \<const0>\;
  LOCKSTEP_Master_Out(3930) <= \<const0>\;
  LOCKSTEP_Master_Out(3931) <= \<const0>\;
  LOCKSTEP_Master_Out(3932) <= \<const0>\;
  LOCKSTEP_Master_Out(3933) <= \<const0>\;
  LOCKSTEP_Master_Out(3934) <= \<const0>\;
  LOCKSTEP_Master_Out(3935) <= \<const0>\;
  LOCKSTEP_Master_Out(3936) <= \<const0>\;
  LOCKSTEP_Master_Out(3937) <= \<const0>\;
  LOCKSTEP_Master_Out(3938) <= \<const0>\;
  LOCKSTEP_Master_Out(3939) <= \<const0>\;
  LOCKSTEP_Master_Out(3940) <= \<const0>\;
  LOCKSTEP_Master_Out(3941) <= \<const0>\;
  LOCKSTEP_Master_Out(3942) <= \<const0>\;
  LOCKSTEP_Master_Out(3943) <= \<const0>\;
  LOCKSTEP_Master_Out(3944) <= \<const0>\;
  LOCKSTEP_Master_Out(3945) <= \<const0>\;
  LOCKSTEP_Master_Out(3946) <= \<const0>\;
  LOCKSTEP_Master_Out(3947) <= \<const0>\;
  LOCKSTEP_Master_Out(3948) <= \<const0>\;
  LOCKSTEP_Master_Out(3949) <= \<const0>\;
  LOCKSTEP_Master_Out(3950) <= \<const0>\;
  LOCKSTEP_Master_Out(3951) <= \<const0>\;
  LOCKSTEP_Master_Out(3952) <= \<const0>\;
  LOCKSTEP_Master_Out(3953) <= \<const0>\;
  LOCKSTEP_Master_Out(3954) <= \<const0>\;
  LOCKSTEP_Master_Out(3955) <= \<const0>\;
  LOCKSTEP_Master_Out(3956) <= \<const0>\;
  LOCKSTEP_Master_Out(3957) <= \<const0>\;
  LOCKSTEP_Master_Out(3958) <= \<const0>\;
  LOCKSTEP_Master_Out(3959) <= \<const0>\;
  LOCKSTEP_Master_Out(3960) <= \<const0>\;
  LOCKSTEP_Master_Out(3961) <= \<const0>\;
  LOCKSTEP_Master_Out(3962) <= \<const0>\;
  LOCKSTEP_Master_Out(3963) <= \<const0>\;
  LOCKSTEP_Master_Out(3964) <= \<const0>\;
  LOCKSTEP_Master_Out(3965) <= \<const0>\;
  LOCKSTEP_Master_Out(3966) <= \<const0>\;
  LOCKSTEP_Master_Out(3967) <= \<const0>\;
  LOCKSTEP_Master_Out(3968) <= \<const0>\;
  LOCKSTEP_Master_Out(3969) <= \<const0>\;
  LOCKSTEP_Master_Out(3970) <= \<const0>\;
  LOCKSTEP_Master_Out(3971) <= \<const0>\;
  LOCKSTEP_Master_Out(3972) <= \<const0>\;
  LOCKSTEP_Master_Out(3973) <= \<const0>\;
  LOCKSTEP_Master_Out(3974) <= \<const0>\;
  LOCKSTEP_Master_Out(3975) <= \<const0>\;
  LOCKSTEP_Master_Out(3976) <= \<const0>\;
  LOCKSTEP_Master_Out(3977) <= \<const0>\;
  LOCKSTEP_Master_Out(3978) <= \<const0>\;
  LOCKSTEP_Master_Out(3979) <= \<const0>\;
  LOCKSTEP_Master_Out(3980) <= \<const0>\;
  LOCKSTEP_Master_Out(3981) <= \<const0>\;
  LOCKSTEP_Master_Out(3982) <= \<const0>\;
  LOCKSTEP_Master_Out(3983) <= \<const0>\;
  LOCKSTEP_Master_Out(3984) <= \<const0>\;
  LOCKSTEP_Master_Out(3985) <= \<const0>\;
  LOCKSTEP_Master_Out(3986) <= \<const0>\;
  LOCKSTEP_Master_Out(3987) <= \<const0>\;
  LOCKSTEP_Master_Out(3988) <= \<const0>\;
  LOCKSTEP_Master_Out(3989) <= \<const0>\;
  LOCKSTEP_Master_Out(3990) <= \<const0>\;
  LOCKSTEP_Master_Out(3991) <= \<const0>\;
  LOCKSTEP_Master_Out(3992) <= \<const0>\;
  LOCKSTEP_Master_Out(3993) <= \<const0>\;
  LOCKSTEP_Master_Out(3994) <= \<const0>\;
  LOCKSTEP_Master_Out(3995) <= \<const0>\;
  LOCKSTEP_Master_Out(3996) <= \<const0>\;
  LOCKSTEP_Master_Out(3997) <= \<const0>\;
  LOCKSTEP_Master_Out(3998) <= \<const0>\;
  LOCKSTEP_Master_Out(3999) <= \<const0>\;
  LOCKSTEP_Master_Out(4000) <= \<const0>\;
  LOCKSTEP_Master_Out(4001) <= \<const0>\;
  LOCKSTEP_Master_Out(4002) <= \<const0>\;
  LOCKSTEP_Master_Out(4003) <= \<const0>\;
  LOCKSTEP_Master_Out(4004) <= \<const0>\;
  LOCKSTEP_Master_Out(4005) <= \<const0>\;
  LOCKSTEP_Master_Out(4006) <= \<const0>\;
  LOCKSTEP_Master_Out(4007) <= \<const0>\;
  LOCKSTEP_Master_Out(4008) <= \<const0>\;
  LOCKSTEP_Master_Out(4009) <= \<const0>\;
  LOCKSTEP_Master_Out(4010) <= \<const0>\;
  LOCKSTEP_Master_Out(4011) <= \<const0>\;
  LOCKSTEP_Master_Out(4012) <= \<const0>\;
  LOCKSTEP_Master_Out(4013) <= \<const0>\;
  LOCKSTEP_Master_Out(4014) <= \<const0>\;
  LOCKSTEP_Master_Out(4015) <= \<const0>\;
  LOCKSTEP_Master_Out(4016) <= \<const0>\;
  LOCKSTEP_Master_Out(4017) <= \<const0>\;
  LOCKSTEP_Master_Out(4018) <= \<const0>\;
  LOCKSTEP_Master_Out(4019) <= \<const0>\;
  LOCKSTEP_Master_Out(4020) <= \<const0>\;
  LOCKSTEP_Master_Out(4021) <= \<const0>\;
  LOCKSTEP_Master_Out(4022) <= \<const0>\;
  LOCKSTEP_Master_Out(4023) <= \<const0>\;
  LOCKSTEP_Master_Out(4024) <= \<const0>\;
  LOCKSTEP_Master_Out(4025) <= \<const0>\;
  LOCKSTEP_Master_Out(4026) <= \<const0>\;
  LOCKSTEP_Master_Out(4027) <= \<const0>\;
  LOCKSTEP_Master_Out(4028) <= \<const0>\;
  LOCKSTEP_Master_Out(4029) <= \<const0>\;
  LOCKSTEP_Master_Out(4030) <= \<const0>\;
  LOCKSTEP_Master_Out(4031) <= \<const0>\;
  LOCKSTEP_Master_Out(4032) <= \<const0>\;
  LOCKSTEP_Master_Out(4033) <= \<const0>\;
  LOCKSTEP_Master_Out(4034) <= \<const0>\;
  LOCKSTEP_Master_Out(4035) <= \<const0>\;
  LOCKSTEP_Master_Out(4036) <= \<const0>\;
  LOCKSTEP_Master_Out(4037) <= \<const0>\;
  LOCKSTEP_Master_Out(4038) <= \<const0>\;
  LOCKSTEP_Master_Out(4039) <= \<const0>\;
  LOCKSTEP_Master_Out(4040) <= \<const0>\;
  LOCKSTEP_Master_Out(4041) <= \<const0>\;
  LOCKSTEP_Master_Out(4042) <= \<const0>\;
  LOCKSTEP_Master_Out(4043) <= \<const0>\;
  LOCKSTEP_Master_Out(4044) <= \<const0>\;
  LOCKSTEP_Master_Out(4045) <= \<const0>\;
  LOCKSTEP_Master_Out(4046) <= \<const0>\;
  LOCKSTEP_Master_Out(4047) <= \<const0>\;
  LOCKSTEP_Master_Out(4048) <= \<const0>\;
  LOCKSTEP_Master_Out(4049) <= \<const0>\;
  LOCKSTEP_Master_Out(4050) <= \<const0>\;
  LOCKSTEP_Master_Out(4051) <= \<const0>\;
  LOCKSTEP_Master_Out(4052) <= \<const0>\;
  LOCKSTEP_Master_Out(4053) <= \<const0>\;
  LOCKSTEP_Master_Out(4054) <= \<const0>\;
  LOCKSTEP_Master_Out(4055) <= \<const0>\;
  LOCKSTEP_Master_Out(4056) <= \<const0>\;
  LOCKSTEP_Master_Out(4057) <= \<const0>\;
  LOCKSTEP_Master_Out(4058) <= \<const0>\;
  LOCKSTEP_Master_Out(4059) <= \<const0>\;
  LOCKSTEP_Master_Out(4060) <= \<const0>\;
  LOCKSTEP_Master_Out(4061) <= \<const0>\;
  LOCKSTEP_Master_Out(4062) <= \<const0>\;
  LOCKSTEP_Master_Out(4063) <= \<const0>\;
  LOCKSTEP_Master_Out(4064) <= \<const0>\;
  LOCKSTEP_Master_Out(4065) <= \<const0>\;
  LOCKSTEP_Master_Out(4066) <= \<const0>\;
  LOCKSTEP_Master_Out(4067) <= \<const0>\;
  LOCKSTEP_Master_Out(4068) <= \<const0>\;
  LOCKSTEP_Master_Out(4069) <= \<const0>\;
  LOCKSTEP_Master_Out(4070) <= \<const0>\;
  LOCKSTEP_Master_Out(4071) <= \<const0>\;
  LOCKSTEP_Master_Out(4072) <= \<const0>\;
  LOCKSTEP_Master_Out(4073) <= \<const0>\;
  LOCKSTEP_Master_Out(4074) <= \<const0>\;
  LOCKSTEP_Master_Out(4075) <= \<const0>\;
  LOCKSTEP_Master_Out(4076) <= \<const0>\;
  LOCKSTEP_Master_Out(4077) <= \<const0>\;
  LOCKSTEP_Master_Out(4078) <= \<const0>\;
  LOCKSTEP_Master_Out(4079) <= \<const0>\;
  LOCKSTEP_Master_Out(4080) <= \<const0>\;
  LOCKSTEP_Master_Out(4081) <= \<const0>\;
  LOCKSTEP_Master_Out(4082) <= \<const0>\;
  LOCKSTEP_Master_Out(4083) <= \<const0>\;
  LOCKSTEP_Master_Out(4084) <= \<const0>\;
  LOCKSTEP_Master_Out(4085) <= \<const0>\;
  LOCKSTEP_Master_Out(4086) <= \<const0>\;
  LOCKSTEP_Master_Out(4087) <= \<const0>\;
  LOCKSTEP_Master_Out(4088) <= \<const0>\;
  LOCKSTEP_Master_Out(4089) <= \<const0>\;
  LOCKSTEP_Master_Out(4090) <= \<const0>\;
  LOCKSTEP_Master_Out(4091) <= \<const0>\;
  LOCKSTEP_Master_Out(4092) <= \<const0>\;
  LOCKSTEP_Master_Out(4093) <= \<const0>\;
  LOCKSTEP_Master_Out(4094) <= \<const0>\;
  LOCKSTEP_Master_Out(4095) <= \<const0>\;
  LOCKSTEP_Out(0) <= \^lockstep_out\(3228);
  LOCKSTEP_Out(1) <= \<const0>\;
  LOCKSTEP_Out(2 to 35) <= \^lockstep_out\(2 to 35);
  LOCKSTEP_Out(36) <= \<const0>\;
  LOCKSTEP_Out(37) <= \<const0>\;
  LOCKSTEP_Out(38) <= \<const0>\;
  LOCKSTEP_Out(39) <= \<const0>\;
  LOCKSTEP_Out(40) <= \<const0>\;
  LOCKSTEP_Out(41) <= \<const0>\;
  LOCKSTEP_Out(42) <= \<const0>\;
  LOCKSTEP_Out(43) <= \<const0>\;
  LOCKSTEP_Out(44) <= \<const0>\;
  LOCKSTEP_Out(45) <= \<const0>\;
  LOCKSTEP_Out(46) <= \<const0>\;
  LOCKSTEP_Out(47) <= \<const0>\;
  LOCKSTEP_Out(48) <= \<const0>\;
  LOCKSTEP_Out(49) <= \<const0>\;
  LOCKSTEP_Out(50) <= \<const0>\;
  LOCKSTEP_Out(51) <= \<const0>\;
  LOCKSTEP_Out(52) <= \<const0>\;
  LOCKSTEP_Out(53) <= \<const0>\;
  LOCKSTEP_Out(54) <= \<const0>\;
  LOCKSTEP_Out(55) <= \<const0>\;
  LOCKSTEP_Out(56) <= \<const0>\;
  LOCKSTEP_Out(57) <= \<const0>\;
  LOCKSTEP_Out(58) <= \<const0>\;
  LOCKSTEP_Out(59) <= \<const0>\;
  LOCKSTEP_Out(60) <= \<const0>\;
  LOCKSTEP_Out(61) <= \<const0>\;
  LOCKSTEP_Out(62) <= \<const0>\;
  LOCKSTEP_Out(63) <= \<const0>\;
  LOCKSTEP_Out(64) <= \<const0>\;
  LOCKSTEP_Out(65) <= \<const0>\;
  LOCKSTEP_Out(66) <= \<const0>\;
  LOCKSTEP_Out(67) <= \<const0>\;
  LOCKSTEP_Out(68 to 99) <= \^lockstep_out\(68 to 99);
  LOCKSTEP_Out(100) <= \<const0>\;
  LOCKSTEP_Out(101) <= \<const0>\;
  LOCKSTEP_Out(102) <= \<const0>\;
  LOCKSTEP_Out(103) <= \<const0>\;
  LOCKSTEP_Out(104) <= \<const0>\;
  LOCKSTEP_Out(105) <= \<const0>\;
  LOCKSTEP_Out(106) <= \<const0>\;
  LOCKSTEP_Out(107) <= \<const0>\;
  LOCKSTEP_Out(108) <= \<const0>\;
  LOCKSTEP_Out(109) <= \<const0>\;
  LOCKSTEP_Out(110) <= \<const0>\;
  LOCKSTEP_Out(111) <= \<const0>\;
  LOCKSTEP_Out(112) <= \<const0>\;
  LOCKSTEP_Out(113) <= \<const0>\;
  LOCKSTEP_Out(114) <= \<const0>\;
  LOCKSTEP_Out(115) <= \<const0>\;
  LOCKSTEP_Out(116) <= \<const0>\;
  LOCKSTEP_Out(117) <= \<const0>\;
  LOCKSTEP_Out(118) <= \<const0>\;
  LOCKSTEP_Out(119) <= \<const0>\;
  LOCKSTEP_Out(120) <= \<const0>\;
  LOCKSTEP_Out(121) <= \<const0>\;
  LOCKSTEP_Out(122) <= \<const0>\;
  LOCKSTEP_Out(123) <= \<const0>\;
  LOCKSTEP_Out(124) <= \<const0>\;
  LOCKSTEP_Out(125) <= \<const0>\;
  LOCKSTEP_Out(126) <= \<const0>\;
  LOCKSTEP_Out(127) <= \<const0>\;
  LOCKSTEP_Out(128) <= \<const0>\;
  LOCKSTEP_Out(129) <= \<const0>\;
  LOCKSTEP_Out(130) <= \<const0>\;
  LOCKSTEP_Out(131) <= \<const0>\;
  LOCKSTEP_Out(132 to 163) <= \^lockstep_out\(132 to 163);
  LOCKSTEP_Out(164) <= \<const0>\;
  LOCKSTEP_Out(165) <= \<const0>\;
  LOCKSTEP_Out(166) <= \<const0>\;
  LOCKSTEP_Out(167) <= \<const0>\;
  LOCKSTEP_Out(168) <= \<const0>\;
  LOCKSTEP_Out(169) <= \<const0>\;
  LOCKSTEP_Out(170) <= \<const0>\;
  LOCKSTEP_Out(171) <= \<const0>\;
  LOCKSTEP_Out(172) <= \<const0>\;
  LOCKSTEP_Out(173) <= \<const0>\;
  LOCKSTEP_Out(174) <= \<const0>\;
  LOCKSTEP_Out(175) <= \<const0>\;
  LOCKSTEP_Out(176) <= \<const0>\;
  LOCKSTEP_Out(177) <= \<const0>\;
  LOCKSTEP_Out(178) <= \<const0>\;
  LOCKSTEP_Out(179) <= \<const0>\;
  LOCKSTEP_Out(180) <= \<const0>\;
  LOCKSTEP_Out(181) <= \<const0>\;
  LOCKSTEP_Out(182) <= \<const0>\;
  LOCKSTEP_Out(183) <= \<const0>\;
  LOCKSTEP_Out(184) <= \<const0>\;
  LOCKSTEP_Out(185) <= \<const0>\;
  LOCKSTEP_Out(186) <= \<const0>\;
  LOCKSTEP_Out(187) <= \<const0>\;
  LOCKSTEP_Out(188) <= \<const0>\;
  LOCKSTEP_Out(189) <= \<const0>\;
  LOCKSTEP_Out(190) <= \<const0>\;
  LOCKSTEP_Out(191) <= \<const0>\;
  LOCKSTEP_Out(192) <= \<const0>\;
  LOCKSTEP_Out(193) <= \<const0>\;
  LOCKSTEP_Out(194) <= \<const0>\;
  LOCKSTEP_Out(195) <= \<const0>\;
  LOCKSTEP_Out(196 to 202) <= \^lockstep_out\(196 to 202);
  LOCKSTEP_Out(203) <= \<const0>\;
  LOCKSTEP_Out(204) <= \<const0>\;
  LOCKSTEP_Out(205) <= \<const0>\;
  LOCKSTEP_Out(206) <= \<const0>\;
  LOCKSTEP_Out(207) <= \<const0>\;
  LOCKSTEP_Out(208) <= \<const0>\;
  LOCKSTEP_Out(209) <= \<const0>\;
  LOCKSTEP_Out(210) <= \<const0>\;
  LOCKSTEP_Out(211) <= \<const0>\;
  LOCKSTEP_Out(212) <= \<const0>\;
  LOCKSTEP_Out(213) <= \<const0>\;
  LOCKSTEP_Out(214) <= \<const0>\;
  LOCKSTEP_Out(215) <= \<const0>\;
  LOCKSTEP_Out(216) <= \<const0>\;
  LOCKSTEP_Out(217) <= \<const0>\;
  LOCKSTEP_Out(218) <= \<const0>\;
  LOCKSTEP_Out(219) <= \<const0>\;
  LOCKSTEP_Out(220) <= \<const0>\;
  LOCKSTEP_Out(221) <= \<const0>\;
  LOCKSTEP_Out(222) <= \<const0>\;
  LOCKSTEP_Out(223) <= \<const0>\;
  LOCKSTEP_Out(224) <= \<const0>\;
  LOCKSTEP_Out(225) <= \<const0>\;
  LOCKSTEP_Out(226) <= \<const0>\;
  LOCKSTEP_Out(227) <= \<const0>\;
  LOCKSTEP_Out(228) <= \<const0>\;
  LOCKSTEP_Out(229) <= \<const0>\;
  LOCKSTEP_Out(230) <= \<const0>\;
  LOCKSTEP_Out(231) <= \<const0>\;
  LOCKSTEP_Out(232) <= \<const0>\;
  LOCKSTEP_Out(233) <= \<const0>\;
  LOCKSTEP_Out(234) <= \<const0>\;
  LOCKSTEP_Out(235) <= \<const0>\;
  LOCKSTEP_Out(236) <= \<const0>\;
  LOCKSTEP_Out(237) <= \<const0>\;
  LOCKSTEP_Out(238) <= \<const0>\;
  LOCKSTEP_Out(239) <= \<const0>\;
  LOCKSTEP_Out(240) <= \<const0>\;
  LOCKSTEP_Out(241) <= \<const0>\;
  LOCKSTEP_Out(242) <= \<const0>\;
  LOCKSTEP_Out(243) <= \<const0>\;
  LOCKSTEP_Out(244) <= \<const0>\;
  LOCKSTEP_Out(245) <= \<const0>\;
  LOCKSTEP_Out(246) <= \<const0>\;
  LOCKSTEP_Out(247) <= \<const0>\;
  LOCKSTEP_Out(248) <= \<const0>\;
  LOCKSTEP_Out(249) <= \<const0>\;
  LOCKSTEP_Out(250) <= \<const0>\;
  LOCKSTEP_Out(251) <= \<const0>\;
  LOCKSTEP_Out(252) <= \<const0>\;
  LOCKSTEP_Out(253) <= \<const0>\;
  LOCKSTEP_Out(254) <= \<const0>\;
  LOCKSTEP_Out(255) <= \<const0>\;
  LOCKSTEP_Out(256) <= \<const0>\;
  LOCKSTEP_Out(257) <= \<const0>\;
  LOCKSTEP_Out(258) <= \<const0>\;
  LOCKSTEP_Out(259) <= \<const0>\;
  LOCKSTEP_Out(260) <= \<const0>\;
  LOCKSTEP_Out(261) <= \<const0>\;
  LOCKSTEP_Out(262) <= \<const0>\;
  LOCKSTEP_Out(263) <= \<const0>\;
  LOCKSTEP_Out(264) <= \<const0>\;
  LOCKSTEP_Out(265) <= \<const0>\;
  LOCKSTEP_Out(266) <= \<const0>\;
  LOCKSTEP_Out(267) <= \<const0>\;
  LOCKSTEP_Out(268) <= \<const0>\;
  LOCKSTEP_Out(269) <= \<const0>\;
  LOCKSTEP_Out(270) <= \<const0>\;
  LOCKSTEP_Out(271) <= \<const0>\;
  LOCKSTEP_Out(272) <= \<const0>\;
  LOCKSTEP_Out(273) <= \<const0>\;
  LOCKSTEP_Out(274) <= \<const0>\;
  LOCKSTEP_Out(275) <= \<const0>\;
  LOCKSTEP_Out(276) <= \<const0>\;
  LOCKSTEP_Out(277) <= \<const0>\;
  LOCKSTEP_Out(278) <= \<const0>\;
  LOCKSTEP_Out(279) <= \<const0>\;
  LOCKSTEP_Out(280) <= \<const0>\;
  LOCKSTEP_Out(281) <= \<const0>\;
  LOCKSTEP_Out(282) <= \<const0>\;
  LOCKSTEP_Out(283) <= \<const0>\;
  LOCKSTEP_Out(284) <= \<const0>\;
  LOCKSTEP_Out(285) <= \<const0>\;
  LOCKSTEP_Out(286) <= \<const0>\;
  LOCKSTEP_Out(287) <= \<const0>\;
  LOCKSTEP_Out(288) <= \<const0>\;
  LOCKSTEP_Out(289) <= \<const0>\;
  LOCKSTEP_Out(290) <= \<const0>\;
  LOCKSTEP_Out(291) <= \<const0>\;
  LOCKSTEP_Out(292) <= \<const0>\;
  LOCKSTEP_Out(293) <= \<const0>\;
  LOCKSTEP_Out(294) <= \<const0>\;
  LOCKSTEP_Out(295) <= \<const0>\;
  LOCKSTEP_Out(296) <= \<const0>\;
  LOCKSTEP_Out(297) <= \<const0>\;
  LOCKSTEP_Out(298) <= \<const0>\;
  LOCKSTEP_Out(299) <= \<const0>\;
  LOCKSTEP_Out(300) <= \<const0>\;
  LOCKSTEP_Out(301) <= \<const0>\;
  LOCKSTEP_Out(302) <= \<const0>\;
  LOCKSTEP_Out(303) <= \<const0>\;
  LOCKSTEP_Out(304) <= \<const0>\;
  LOCKSTEP_Out(305) <= \<const0>\;
  LOCKSTEP_Out(306) <= \<const0>\;
  LOCKSTEP_Out(307) <= \<const0>\;
  LOCKSTEP_Out(308) <= \<const0>\;
  LOCKSTEP_Out(309) <= \<const0>\;
  LOCKSTEP_Out(310) <= \<const0>\;
  LOCKSTEP_Out(311) <= \<const0>\;
  LOCKSTEP_Out(312) <= \<const0>\;
  LOCKSTEP_Out(313) <= \<const0>\;
  LOCKSTEP_Out(314) <= \<const0>\;
  LOCKSTEP_Out(315) <= \<const0>\;
  LOCKSTEP_Out(316) <= \<const0>\;
  LOCKSTEP_Out(317) <= \<const0>\;
  LOCKSTEP_Out(318) <= \<const0>\;
  LOCKSTEP_Out(319) <= \<const0>\;
  LOCKSTEP_Out(320) <= \<const0>\;
  LOCKSTEP_Out(321) <= \<const0>\;
  LOCKSTEP_Out(322) <= \<const0>\;
  LOCKSTEP_Out(323) <= \<const0>\;
  LOCKSTEP_Out(324) <= \<const0>\;
  LOCKSTEP_Out(325) <= \<const0>\;
  LOCKSTEP_Out(326) <= \<const0>\;
  LOCKSTEP_Out(327) <= \<const0>\;
  LOCKSTEP_Out(328) <= \<const0>\;
  LOCKSTEP_Out(329) <= \<const0>\;
  LOCKSTEP_Out(330) <= \<const0>\;
  LOCKSTEP_Out(331) <= \<const0>\;
  LOCKSTEP_Out(332) <= \<const0>\;
  LOCKSTEP_Out(333) <= \<const0>\;
  LOCKSTEP_Out(334) <= \<const0>\;
  LOCKSTEP_Out(335) <= \<const0>\;
  LOCKSTEP_Out(336) <= \<const0>\;
  LOCKSTEP_Out(337) <= \<const0>\;
  LOCKSTEP_Out(338) <= \<const0>\;
  LOCKSTEP_Out(339) <= \<const0>\;
  LOCKSTEP_Out(340) <= \<const0>\;
  LOCKSTEP_Out(341) <= \<const0>\;
  LOCKSTEP_Out(342) <= \<const0>\;
  LOCKSTEP_Out(343) <= \<const0>\;
  LOCKSTEP_Out(344) <= \<const0>\;
  LOCKSTEP_Out(345) <= \<const0>\;
  LOCKSTEP_Out(346) <= \<const0>\;
  LOCKSTEP_Out(347) <= \<const0>\;
  LOCKSTEP_Out(348) <= \<const0>\;
  LOCKSTEP_Out(349) <= \<const0>\;
  LOCKSTEP_Out(350) <= \<const0>\;
  LOCKSTEP_Out(351) <= \<const0>\;
  LOCKSTEP_Out(352) <= \<const0>\;
  LOCKSTEP_Out(353) <= \<const0>\;
  LOCKSTEP_Out(354) <= \<const0>\;
  LOCKSTEP_Out(355) <= \<const0>\;
  LOCKSTEP_Out(356) <= \<const0>\;
  LOCKSTEP_Out(357) <= \<const0>\;
  LOCKSTEP_Out(358) <= \<const0>\;
  LOCKSTEP_Out(359) <= \<const0>\;
  LOCKSTEP_Out(360) <= \<const0>\;
  LOCKSTEP_Out(361) <= \<const0>\;
  LOCKSTEP_Out(362) <= \<const0>\;
  LOCKSTEP_Out(363) <= \<const0>\;
  LOCKSTEP_Out(364) <= \<const0>\;
  LOCKSTEP_Out(365) <= \<const0>\;
  LOCKSTEP_Out(366) <= \<const0>\;
  LOCKSTEP_Out(367) <= \<const0>\;
  LOCKSTEP_Out(368) <= \<const0>\;
  LOCKSTEP_Out(369) <= \<const0>\;
  LOCKSTEP_Out(370) <= \<const0>\;
  LOCKSTEP_Out(371) <= \<const0>\;
  LOCKSTEP_Out(372) <= \<const0>\;
  LOCKSTEP_Out(373) <= \<const0>\;
  LOCKSTEP_Out(374) <= \<const0>\;
  LOCKSTEP_Out(375) <= \<const0>\;
  LOCKSTEP_Out(376) <= \<const0>\;
  LOCKSTEP_Out(377) <= \<const0>\;
  LOCKSTEP_Out(378) <= \<const0>\;
  LOCKSTEP_Out(379) <= \<const0>\;
  LOCKSTEP_Out(380) <= \<const0>\;
  LOCKSTEP_Out(381) <= \<const0>\;
  LOCKSTEP_Out(382) <= \<const0>\;
  LOCKSTEP_Out(383) <= \<const0>\;
  LOCKSTEP_Out(384) <= \<const0>\;
  LOCKSTEP_Out(385) <= \<const0>\;
  LOCKSTEP_Out(386) <= \<const0>\;
  LOCKSTEP_Out(387) <= \<const0>\;
  LOCKSTEP_Out(388) <= \<const0>\;
  LOCKSTEP_Out(389) <= \<const0>\;
  LOCKSTEP_Out(390) <= \<const0>\;
  LOCKSTEP_Out(391) <= \<const0>\;
  LOCKSTEP_Out(392) <= \<const0>\;
  LOCKSTEP_Out(393) <= \<const0>\;
  LOCKSTEP_Out(394) <= \<const0>\;
  LOCKSTEP_Out(395) <= \<const0>\;
  LOCKSTEP_Out(396) <= \<const0>\;
  LOCKSTEP_Out(397) <= \<const0>\;
  LOCKSTEP_Out(398) <= \<const0>\;
  LOCKSTEP_Out(399) <= \<const0>\;
  LOCKSTEP_Out(400) <= \<const0>\;
  LOCKSTEP_Out(401) <= \<const0>\;
  LOCKSTEP_Out(402) <= \<const0>\;
  LOCKSTEP_Out(403) <= \<const0>\;
  LOCKSTEP_Out(404) <= \<const0>\;
  LOCKSTEP_Out(405) <= \<const0>\;
  LOCKSTEP_Out(406) <= \<const0>\;
  LOCKSTEP_Out(407) <= \<const0>\;
  LOCKSTEP_Out(408) <= \<const0>\;
  LOCKSTEP_Out(409) <= \<const0>\;
  LOCKSTEP_Out(410) <= \<const0>\;
  LOCKSTEP_Out(411) <= \<const0>\;
  LOCKSTEP_Out(412) <= \<const0>\;
  LOCKSTEP_Out(413) <= \<const0>\;
  LOCKSTEP_Out(414) <= \<const0>\;
  LOCKSTEP_Out(415) <= \<const0>\;
  LOCKSTEP_Out(416) <= \<const0>\;
  LOCKSTEP_Out(417) <= \<const0>\;
  LOCKSTEP_Out(418) <= \<const0>\;
  LOCKSTEP_Out(419) <= \<const0>\;
  LOCKSTEP_Out(420) <= \<const0>\;
  LOCKSTEP_Out(421) <= \<const0>\;
  LOCKSTEP_Out(422) <= \<const0>\;
  LOCKSTEP_Out(423) <= \<const0>\;
  LOCKSTEP_Out(424) <= \<const0>\;
  LOCKSTEP_Out(425) <= \<const0>\;
  LOCKSTEP_Out(426) <= \<const0>\;
  LOCKSTEP_Out(427) <= \<const0>\;
  LOCKSTEP_Out(428) <= \<const0>\;
  LOCKSTEP_Out(429) <= \<const0>\;
  LOCKSTEP_Out(430) <= \<const0>\;
  LOCKSTEP_Out(431) <= \<const0>\;
  LOCKSTEP_Out(432) <= \<const0>\;
  LOCKSTEP_Out(433) <= \<const0>\;
  LOCKSTEP_Out(434) <= \<const0>\;
  LOCKSTEP_Out(435) <= \<const0>\;
  LOCKSTEP_Out(436) <= \<const0>\;
  LOCKSTEP_Out(437) <= \<const0>\;
  LOCKSTEP_Out(438) <= \<const0>\;
  LOCKSTEP_Out(439) <= \<const0>\;
  LOCKSTEP_Out(440) <= \<const0>\;
  LOCKSTEP_Out(441) <= \<const0>\;
  LOCKSTEP_Out(442) <= \<const0>\;
  LOCKSTEP_Out(443) <= \<const0>\;
  LOCKSTEP_Out(444) <= \<const0>\;
  LOCKSTEP_Out(445) <= \<const0>\;
  LOCKSTEP_Out(446) <= \<const0>\;
  LOCKSTEP_Out(447) <= \<const0>\;
  LOCKSTEP_Out(448) <= \<const0>\;
  LOCKSTEP_Out(449) <= \<const0>\;
  LOCKSTEP_Out(450) <= \<const0>\;
  LOCKSTEP_Out(451) <= \<const0>\;
  LOCKSTEP_Out(452) <= \<const0>\;
  LOCKSTEP_Out(453) <= \<const0>\;
  LOCKSTEP_Out(454) <= \<const0>\;
  LOCKSTEP_Out(455) <= \<const0>\;
  LOCKSTEP_Out(456) <= \<const0>\;
  LOCKSTEP_Out(457) <= \<const0>\;
  LOCKSTEP_Out(458) <= \<const0>\;
  LOCKSTEP_Out(459) <= \<const0>\;
  LOCKSTEP_Out(460) <= \<const0>\;
  LOCKSTEP_Out(461) <= \<const0>\;
  LOCKSTEP_Out(462) <= \<const0>\;
  LOCKSTEP_Out(463) <= \<const0>\;
  LOCKSTEP_Out(464) <= \<const0>\;
  LOCKSTEP_Out(465) <= \<const0>\;
  LOCKSTEP_Out(466 to 497) <= \^lockstep_out\(632 to 663);
  LOCKSTEP_Out(498) <= \<const0>\;
  LOCKSTEP_Out(499) <= \<const0>\;
  LOCKSTEP_Out(500) <= \<const0>\;
  LOCKSTEP_Out(501) <= \<const0>\;
  LOCKSTEP_Out(502) <= \<const0>\;
  LOCKSTEP_Out(503) <= \<const0>\;
  LOCKSTEP_Out(504) <= \<const0>\;
  LOCKSTEP_Out(505) <= \<const0>\;
  LOCKSTEP_Out(506) <= \<const0>\;
  LOCKSTEP_Out(507) <= \<const0>\;
  LOCKSTEP_Out(508) <= \<const0>\;
  LOCKSTEP_Out(509) <= \<const0>\;
  LOCKSTEP_Out(510) <= \<const0>\;
  LOCKSTEP_Out(511) <= \<const0>\;
  LOCKSTEP_Out(512) <= \<const0>\;
  LOCKSTEP_Out(513) <= \<const0>\;
  LOCKSTEP_Out(514) <= \<const0>\;
  LOCKSTEP_Out(515) <= \<const0>\;
  LOCKSTEP_Out(516) <= \<const0>\;
  LOCKSTEP_Out(517) <= \<const0>\;
  LOCKSTEP_Out(518) <= \<const0>\;
  LOCKSTEP_Out(519) <= \<const0>\;
  LOCKSTEP_Out(520) <= \<const0>\;
  LOCKSTEP_Out(521) <= \<const0>\;
  LOCKSTEP_Out(522) <= \<const0>\;
  LOCKSTEP_Out(523) <= \<const0>\;
  LOCKSTEP_Out(524) <= \<const0>\;
  LOCKSTEP_Out(525) <= \<const0>\;
  LOCKSTEP_Out(526) <= \<const0>\;
  LOCKSTEP_Out(527) <= \<const0>\;
  LOCKSTEP_Out(528) <= \<const0>\;
  LOCKSTEP_Out(529) <= \<const0>\;
  LOCKSTEP_Out(530) <= \<const0>\;
  LOCKSTEP_Out(531) <= \<const0>\;
  LOCKSTEP_Out(532) <= \<const0>\;
  LOCKSTEP_Out(533) <= \<const0>\;
  LOCKSTEP_Out(534) <= \<const0>\;
  LOCKSTEP_Out(535) <= \<const0>\;
  LOCKSTEP_Out(536) <= \<const0>\;
  LOCKSTEP_Out(537) <= \<const0>\;
  LOCKSTEP_Out(538) <= \<const0>\;
  LOCKSTEP_Out(539) <= \^lockstep_out\(542);
  LOCKSTEP_Out(540) <= \<const0>\;
  LOCKSTEP_Out(541) <= \<const0>\;
  LOCKSTEP_Out(542) <= \^lockstep_out\(542);
  LOCKSTEP_Out(543) <= \<const0>\;
  LOCKSTEP_Out(544) <= \<const0>\;
  LOCKSTEP_Out(545) <= \<const0>\;
  LOCKSTEP_Out(546) <= \^lockstep_out\(542);
  LOCKSTEP_Out(547) <= \^lockstep_out\(542);
  LOCKSTEP_Out(548) <= \<const0>\;
  LOCKSTEP_Out(549) <= \<const0>\;
  LOCKSTEP_Out(550) <= \<const0>\;
  LOCKSTEP_Out(551) <= \^lockstep_out\(542);
  LOCKSTEP_Out(552) <= \<const0>\;
  LOCKSTEP_Out(553) <= \<const0>\;
  LOCKSTEP_Out(554) <= \<const0>\;
  LOCKSTEP_Out(555 to 587) <= \^lockstep_out\(555 to 587);
  LOCKSTEP_Out(588) <= \<const0>\;
  LOCKSTEP_Out(589) <= \<const0>\;
  LOCKSTEP_Out(590) <= \<const0>\;
  LOCKSTEP_Out(591) <= \<const0>\;
  LOCKSTEP_Out(592) <= \<const0>\;
  LOCKSTEP_Out(593) <= \<const0>\;
  LOCKSTEP_Out(594) <= \<const0>\;
  LOCKSTEP_Out(595) <= \<const0>\;
  LOCKSTEP_Out(596) <= \<const0>\;
  LOCKSTEP_Out(597) <= \<const0>\;
  LOCKSTEP_Out(598) <= \<const0>\;
  LOCKSTEP_Out(599) <= \<const0>\;
  LOCKSTEP_Out(600) <= \<const0>\;
  LOCKSTEP_Out(601) <= \<const0>\;
  LOCKSTEP_Out(602) <= \<const0>\;
  LOCKSTEP_Out(603) <= \<const0>\;
  LOCKSTEP_Out(604) <= \<const0>\;
  LOCKSTEP_Out(605) <= \<const0>\;
  LOCKSTEP_Out(606) <= \<const0>\;
  LOCKSTEP_Out(607) <= \<const0>\;
  LOCKSTEP_Out(608) <= \<const0>\;
  LOCKSTEP_Out(609) <= \<const0>\;
  LOCKSTEP_Out(610) <= \<const0>\;
  LOCKSTEP_Out(611) <= \<const0>\;
  LOCKSTEP_Out(612) <= \<const0>\;
  LOCKSTEP_Out(613) <= \<const0>\;
  LOCKSTEP_Out(614) <= \<const0>\;
  LOCKSTEP_Out(615) <= \<const0>\;
  LOCKSTEP_Out(616) <= \<const0>\;
  LOCKSTEP_Out(617) <= \<const0>\;
  LOCKSTEP_Out(618) <= \<const0>\;
  LOCKSTEP_Out(619) <= \<const0>\;
  LOCKSTEP_Out(620 to 623) <= \^lockstep_out\(620 to 623);
  LOCKSTEP_Out(624) <= \<const0>\;
  LOCKSTEP_Out(625) <= \<const0>\;
  LOCKSTEP_Out(626) <= \<const0>\;
  LOCKSTEP_Out(627) <= \<const0>\;
  LOCKSTEP_Out(628) <= \^lockstep_out\(542);
  LOCKSTEP_Out(629) <= \^lockstep_out\(629);
  LOCKSTEP_Out(630) <= \^lockstep_out\(542);
  LOCKSTEP_Out(631) <= \<const0>\;
  LOCKSTEP_Out(632 to 663) <= \^lockstep_out\(632 to 663);
  LOCKSTEP_Out(664) <= \<const0>\;
  LOCKSTEP_Out(665) <= \<const0>\;
  LOCKSTEP_Out(666) <= \<const0>\;
  LOCKSTEP_Out(667) <= \<const0>\;
  LOCKSTEP_Out(668) <= \<const0>\;
  LOCKSTEP_Out(669) <= \<const0>\;
  LOCKSTEP_Out(670) <= \<const0>\;
  LOCKSTEP_Out(671) <= \<const0>\;
  LOCKSTEP_Out(672) <= \<const0>\;
  LOCKSTEP_Out(673) <= \<const0>\;
  LOCKSTEP_Out(674) <= \<const0>\;
  LOCKSTEP_Out(675) <= \<const0>\;
  LOCKSTEP_Out(676) <= \<const0>\;
  LOCKSTEP_Out(677) <= \<const0>\;
  LOCKSTEP_Out(678) <= \<const0>\;
  LOCKSTEP_Out(679) <= \<const0>\;
  LOCKSTEP_Out(680) <= \<const0>\;
  LOCKSTEP_Out(681) <= \<const0>\;
  LOCKSTEP_Out(682) <= \<const0>\;
  LOCKSTEP_Out(683) <= \<const0>\;
  LOCKSTEP_Out(684) <= \<const0>\;
  LOCKSTEP_Out(685) <= \<const0>\;
  LOCKSTEP_Out(686) <= \<const0>\;
  LOCKSTEP_Out(687) <= \<const0>\;
  LOCKSTEP_Out(688) <= \<const0>\;
  LOCKSTEP_Out(689) <= \<const0>\;
  LOCKSTEP_Out(690) <= \<const0>\;
  LOCKSTEP_Out(691) <= \<const0>\;
  LOCKSTEP_Out(692) <= \<const0>\;
  LOCKSTEP_Out(693) <= \<const0>\;
  LOCKSTEP_Out(694) <= \<const0>\;
  LOCKSTEP_Out(695) <= \<const0>\;
  LOCKSTEP_Out(696) <= \<const0>\;
  LOCKSTEP_Out(697) <= \<const0>\;
  LOCKSTEP_Out(698) <= \<const0>\;
  LOCKSTEP_Out(699) <= \<const0>\;
  LOCKSTEP_Out(700) <= \<const0>\;
  LOCKSTEP_Out(701) <= \<const0>\;
  LOCKSTEP_Out(702) <= \<const0>\;
  LOCKSTEP_Out(703) <= \<const0>\;
  LOCKSTEP_Out(704) <= \<const0>\;
  LOCKSTEP_Out(705) <= \^lockstep_out\(542);
  LOCKSTEP_Out(706) <= \<const0>\;
  LOCKSTEP_Out(707) <= \<const0>\;
  LOCKSTEP_Out(708) <= \^lockstep_out\(542);
  LOCKSTEP_Out(709) <= \<const0>\;
  LOCKSTEP_Out(710) <= \<const0>\;
  LOCKSTEP_Out(711) <= \<const0>\;
  LOCKSTEP_Out(712) <= \^lockstep_out\(542);
  LOCKSTEP_Out(713) <= \^lockstep_out\(542);
  LOCKSTEP_Out(714) <= \<const0>\;
  LOCKSTEP_Out(715) <= \<const0>\;
  LOCKSTEP_Out(716) <= \<const0>\;
  LOCKSTEP_Out(717) <= \^lockstep_out\(542);
  LOCKSTEP_Out(718) <= \<const0>\;
  LOCKSTEP_Out(719) <= \<const0>\;
  LOCKSTEP_Out(720) <= \<const0>\;
  LOCKSTEP_Out(721) <= \^lockstep_out\(721);
  LOCKSTEP_Out(722) <= \^lockstep_out\(542);
  LOCKSTEP_Out(723) <= \<const0>\;
  LOCKSTEP_Out(724) <= \<const0>\;
  LOCKSTEP_Out(725) <= \<const0>\;
  LOCKSTEP_Out(726) <= \<const0>\;
  LOCKSTEP_Out(727) <= \<const0>\;
  LOCKSTEP_Out(728) <= \<const0>\;
  LOCKSTEP_Out(729) <= \<const0>\;
  LOCKSTEP_Out(730) <= \<const0>\;
  LOCKSTEP_Out(731) <= \<const0>\;
  LOCKSTEP_Out(732) <= \<const0>\;
  LOCKSTEP_Out(733) <= \<const0>\;
  LOCKSTEP_Out(734) <= \<const0>\;
  LOCKSTEP_Out(735) <= \<const0>\;
  LOCKSTEP_Out(736) <= \<const0>\;
  LOCKSTEP_Out(737) <= \<const0>\;
  LOCKSTEP_Out(738) <= \<const0>\;
  LOCKSTEP_Out(739) <= \<const0>\;
  LOCKSTEP_Out(740) <= \<const0>\;
  LOCKSTEP_Out(741) <= \<const0>\;
  LOCKSTEP_Out(742) <= \<const0>\;
  LOCKSTEP_Out(743) <= \<const0>\;
  LOCKSTEP_Out(744) <= \<const0>\;
  LOCKSTEP_Out(745) <= \<const0>\;
  LOCKSTEP_Out(746) <= \<const0>\;
  LOCKSTEP_Out(747) <= \<const0>\;
  LOCKSTEP_Out(748) <= \<const0>\;
  LOCKSTEP_Out(749) <= \<const0>\;
  LOCKSTEP_Out(750) <= \<const0>\;
  LOCKSTEP_Out(751) <= \<const0>\;
  LOCKSTEP_Out(752) <= \<const0>\;
  LOCKSTEP_Out(753) <= \<const0>\;
  LOCKSTEP_Out(754) <= \<const0>\;
  LOCKSTEP_Out(755) <= \<const0>\;
  LOCKSTEP_Out(756) <= \<const0>\;
  LOCKSTEP_Out(757) <= \<const0>\;
  LOCKSTEP_Out(758) <= \<const0>\;
  LOCKSTEP_Out(759) <= \<const0>\;
  LOCKSTEP_Out(760) <= \<const0>\;
  LOCKSTEP_Out(761) <= \<const0>\;
  LOCKSTEP_Out(762) <= \<const0>\;
  LOCKSTEP_Out(763) <= \<const0>\;
  LOCKSTEP_Out(764) <= \<const0>\;
  LOCKSTEP_Out(765) <= \<const0>\;
  LOCKSTEP_Out(766) <= \<const0>\;
  LOCKSTEP_Out(767) <= \<const0>\;
  LOCKSTEP_Out(768) <= \<const0>\;
  LOCKSTEP_Out(769) <= \<const0>\;
  LOCKSTEP_Out(770) <= \<const0>\;
  LOCKSTEP_Out(771) <= \<const0>\;
  LOCKSTEP_Out(772) <= \<const0>\;
  LOCKSTEP_Out(773) <= \<const0>\;
  LOCKSTEP_Out(774) <= \<const0>\;
  LOCKSTEP_Out(775) <= \<const0>\;
  LOCKSTEP_Out(776) <= \<const0>\;
  LOCKSTEP_Out(777) <= \<const0>\;
  LOCKSTEP_Out(778) <= \<const0>\;
  LOCKSTEP_Out(779) <= \<const0>\;
  LOCKSTEP_Out(780) <= \<const0>\;
  LOCKSTEP_Out(781) <= \<const0>\;
  LOCKSTEP_Out(782) <= \<const0>\;
  LOCKSTEP_Out(783) <= \<const0>\;
  LOCKSTEP_Out(784) <= \<const0>\;
  LOCKSTEP_Out(785) <= \<const0>\;
  LOCKSTEP_Out(786) <= \<const0>\;
  LOCKSTEP_Out(787) <= \<const0>\;
  LOCKSTEP_Out(788) <= \<const0>\;
  LOCKSTEP_Out(789) <= \<const0>\;
  LOCKSTEP_Out(790) <= \<const0>\;
  LOCKSTEP_Out(791) <= \<const0>\;
  LOCKSTEP_Out(792) <= \<const0>\;
  LOCKSTEP_Out(793) <= \<const0>\;
  LOCKSTEP_Out(794) <= \<const0>\;
  LOCKSTEP_Out(795) <= \<const0>\;
  LOCKSTEP_Out(796) <= \<const0>\;
  LOCKSTEP_Out(797) <= \<const0>\;
  LOCKSTEP_Out(798) <= \<const0>\;
  LOCKSTEP_Out(799) <= \<const0>\;
  LOCKSTEP_Out(800) <= \<const0>\;
  LOCKSTEP_Out(801) <= \<const0>\;
  LOCKSTEP_Out(802) <= \<const0>\;
  LOCKSTEP_Out(803) <= \<const0>\;
  LOCKSTEP_Out(804) <= \<const0>\;
  LOCKSTEP_Out(805) <= \<const0>\;
  LOCKSTEP_Out(806) <= \<const0>\;
  LOCKSTEP_Out(807) <= \<const0>\;
  LOCKSTEP_Out(808) <= \<const0>\;
  LOCKSTEP_Out(809) <= \<const0>\;
  LOCKSTEP_Out(810) <= \<const0>\;
  LOCKSTEP_Out(811) <= \<const0>\;
  LOCKSTEP_Out(812) <= \<const0>\;
  LOCKSTEP_Out(813) <= \<const0>\;
  LOCKSTEP_Out(814) <= \<const0>\;
  LOCKSTEP_Out(815) <= \<const0>\;
  LOCKSTEP_Out(816) <= \<const0>\;
  LOCKSTEP_Out(817) <= \<const0>\;
  LOCKSTEP_Out(818) <= \<const0>\;
  LOCKSTEP_Out(819) <= \<const0>\;
  LOCKSTEP_Out(820) <= \<const0>\;
  LOCKSTEP_Out(821) <= \<const0>\;
  LOCKSTEP_Out(822) <= \<const0>\;
  LOCKSTEP_Out(823) <= \<const0>\;
  LOCKSTEP_Out(824) <= \<const0>\;
  LOCKSTEP_Out(825) <= \<const0>\;
  LOCKSTEP_Out(826) <= \<const0>\;
  LOCKSTEP_Out(827) <= \<const0>\;
  LOCKSTEP_Out(828) <= \<const0>\;
  LOCKSTEP_Out(829) <= \<const0>\;
  LOCKSTEP_Out(830) <= \<const0>\;
  LOCKSTEP_Out(831) <= \<const0>\;
  LOCKSTEP_Out(832) <= \<const0>\;
  LOCKSTEP_Out(833) <= \<const0>\;
  LOCKSTEP_Out(834) <= \<const0>\;
  LOCKSTEP_Out(835) <= \<const0>\;
  LOCKSTEP_Out(836) <= \<const0>\;
  LOCKSTEP_Out(837) <= \<const0>\;
  LOCKSTEP_Out(838) <= \<const0>\;
  LOCKSTEP_Out(839) <= \<const0>\;
  LOCKSTEP_Out(840) <= \<const0>\;
  LOCKSTEP_Out(841) <= \<const0>\;
  LOCKSTEP_Out(842) <= \<const0>\;
  LOCKSTEP_Out(843) <= \<const0>\;
  LOCKSTEP_Out(844) <= \<const0>\;
  LOCKSTEP_Out(845) <= \<const0>\;
  LOCKSTEP_Out(846) <= \<const0>\;
  LOCKSTEP_Out(847) <= \<const0>\;
  LOCKSTEP_Out(848) <= \<const0>\;
  LOCKSTEP_Out(849) <= \<const0>\;
  LOCKSTEP_Out(850) <= \<const0>\;
  LOCKSTEP_Out(851) <= \<const0>\;
  LOCKSTEP_Out(852) <= \<const0>\;
  LOCKSTEP_Out(853) <= \<const0>\;
  LOCKSTEP_Out(854) <= \<const0>\;
  LOCKSTEP_Out(855) <= \<const0>\;
  LOCKSTEP_Out(856) <= \<const0>\;
  LOCKSTEP_Out(857) <= \<const0>\;
  LOCKSTEP_Out(858) <= \<const0>\;
  LOCKSTEP_Out(859) <= \<const0>\;
  LOCKSTEP_Out(860) <= \<const0>\;
  LOCKSTEP_Out(861) <= \<const0>\;
  LOCKSTEP_Out(862) <= \<const0>\;
  LOCKSTEP_Out(863) <= \<const0>\;
  LOCKSTEP_Out(864) <= \<const0>\;
  LOCKSTEP_Out(865) <= \<const0>\;
  LOCKSTEP_Out(866) <= \<const0>\;
  LOCKSTEP_Out(867) <= \<const0>\;
  LOCKSTEP_Out(868) <= \<const0>\;
  LOCKSTEP_Out(869) <= \<const0>\;
  LOCKSTEP_Out(870) <= \<const0>\;
  LOCKSTEP_Out(871) <= \<const0>\;
  LOCKSTEP_Out(872) <= \<const0>\;
  LOCKSTEP_Out(873) <= \<const0>\;
  LOCKSTEP_Out(874) <= \<const0>\;
  LOCKSTEP_Out(875) <= \<const0>\;
  LOCKSTEP_Out(876) <= \<const0>\;
  LOCKSTEP_Out(877) <= \<const0>\;
  LOCKSTEP_Out(878) <= \<const0>\;
  LOCKSTEP_Out(879) <= \<const0>\;
  LOCKSTEP_Out(880) <= \<const0>\;
  LOCKSTEP_Out(881) <= \<const0>\;
  LOCKSTEP_Out(882) <= \<const0>\;
  LOCKSTEP_Out(883) <= \<const0>\;
  LOCKSTEP_Out(884) <= \<const0>\;
  LOCKSTEP_Out(885) <= \<const0>\;
  LOCKSTEP_Out(886) <= \<const0>\;
  LOCKSTEP_Out(887) <= \<const0>\;
  LOCKSTEP_Out(888) <= \<const0>\;
  LOCKSTEP_Out(889) <= \<const0>\;
  LOCKSTEP_Out(890) <= \<const0>\;
  LOCKSTEP_Out(891) <= \<const0>\;
  LOCKSTEP_Out(892) <= \<const0>\;
  LOCKSTEP_Out(893) <= \<const0>\;
  LOCKSTEP_Out(894) <= \<const0>\;
  LOCKSTEP_Out(895) <= \<const0>\;
  LOCKSTEP_Out(896) <= \<const0>\;
  LOCKSTEP_Out(897) <= \<const0>\;
  LOCKSTEP_Out(898) <= \<const0>\;
  LOCKSTEP_Out(899) <= \<const0>\;
  LOCKSTEP_Out(900) <= \<const0>\;
  LOCKSTEP_Out(901) <= \<const0>\;
  LOCKSTEP_Out(902) <= \<const0>\;
  LOCKSTEP_Out(903) <= \<const0>\;
  LOCKSTEP_Out(904) <= \<const0>\;
  LOCKSTEP_Out(905) <= \<const0>\;
  LOCKSTEP_Out(906) <= \<const0>\;
  LOCKSTEP_Out(907) <= \<const0>\;
  LOCKSTEP_Out(908) <= \<const0>\;
  LOCKSTEP_Out(909) <= \<const0>\;
  LOCKSTEP_Out(910) <= \<const0>\;
  LOCKSTEP_Out(911) <= \<const0>\;
  LOCKSTEP_Out(912) <= \<const0>\;
  LOCKSTEP_Out(913) <= \<const0>\;
  LOCKSTEP_Out(914) <= \<const0>\;
  LOCKSTEP_Out(915) <= \<const0>\;
  LOCKSTEP_Out(916) <= \<const0>\;
  LOCKSTEP_Out(917) <= \<const0>\;
  LOCKSTEP_Out(918) <= \<const0>\;
  LOCKSTEP_Out(919) <= \<const0>\;
  LOCKSTEP_Out(920) <= \<const0>\;
  LOCKSTEP_Out(921) <= \<const0>\;
  LOCKSTEP_Out(922) <= \<const0>\;
  LOCKSTEP_Out(923) <= \<const0>\;
  LOCKSTEP_Out(924) <= \<const0>\;
  LOCKSTEP_Out(925) <= \<const0>\;
  LOCKSTEP_Out(926) <= \<const0>\;
  LOCKSTEP_Out(927) <= \<const0>\;
  LOCKSTEP_Out(928) <= \<const0>\;
  LOCKSTEP_Out(929) <= \<const0>\;
  LOCKSTEP_Out(930) <= \<const0>\;
  LOCKSTEP_Out(931) <= \<const0>\;
  LOCKSTEP_Out(932) <= \<const0>\;
  LOCKSTEP_Out(933) <= \<const0>\;
  LOCKSTEP_Out(934) <= \<const0>\;
  LOCKSTEP_Out(935) <= \<const0>\;
  LOCKSTEP_Out(936) <= \<const0>\;
  LOCKSTEP_Out(937) <= \<const0>\;
  LOCKSTEP_Out(938) <= \<const0>\;
  LOCKSTEP_Out(939) <= \<const0>\;
  LOCKSTEP_Out(940) <= \<const0>\;
  LOCKSTEP_Out(941) <= \<const0>\;
  LOCKSTEP_Out(942) <= \<const0>\;
  LOCKSTEP_Out(943) <= \<const0>\;
  LOCKSTEP_Out(944) <= \<const0>\;
  LOCKSTEP_Out(945) <= \<const0>\;
  LOCKSTEP_Out(946) <= \<const0>\;
  LOCKSTEP_Out(947) <= \<const0>\;
  LOCKSTEP_Out(948) <= \<const0>\;
  LOCKSTEP_Out(949) <= \<const0>\;
  LOCKSTEP_Out(950) <= \<const0>\;
  LOCKSTEP_Out(951) <= \<const0>\;
  LOCKSTEP_Out(952) <= \<const0>\;
  LOCKSTEP_Out(953) <= \<const0>\;
  LOCKSTEP_Out(954) <= \<const0>\;
  LOCKSTEP_Out(955) <= \<const0>\;
  LOCKSTEP_Out(956) <= \<const0>\;
  LOCKSTEP_Out(957) <= \<const0>\;
  LOCKSTEP_Out(958) <= \<const0>\;
  LOCKSTEP_Out(959) <= \<const0>\;
  LOCKSTEP_Out(960) <= \<const0>\;
  LOCKSTEP_Out(961) <= \<const0>\;
  LOCKSTEP_Out(962) <= \<const0>\;
  LOCKSTEP_Out(963) <= \<const0>\;
  LOCKSTEP_Out(964) <= \<const0>\;
  LOCKSTEP_Out(965) <= \<const0>\;
  LOCKSTEP_Out(966) <= \<const0>\;
  LOCKSTEP_Out(967) <= \<const0>\;
  LOCKSTEP_Out(968) <= \<const0>\;
  LOCKSTEP_Out(969) <= \<const0>\;
  LOCKSTEP_Out(970) <= \<const0>\;
  LOCKSTEP_Out(971) <= \<const0>\;
  LOCKSTEP_Out(972) <= \<const0>\;
  LOCKSTEP_Out(973) <= \<const0>\;
  LOCKSTEP_Out(974) <= \<const0>\;
  LOCKSTEP_Out(975) <= \<const0>\;
  LOCKSTEP_Out(976) <= \<const0>\;
  LOCKSTEP_Out(977) <= \<const0>\;
  LOCKSTEP_Out(978) <= \<const0>\;
  LOCKSTEP_Out(979) <= \<const0>\;
  LOCKSTEP_Out(980) <= \<const0>\;
  LOCKSTEP_Out(981) <= \<const0>\;
  LOCKSTEP_Out(982) <= \<const0>\;
  LOCKSTEP_Out(983) <= \<const0>\;
  LOCKSTEP_Out(984) <= \<const0>\;
  LOCKSTEP_Out(985) <= \<const0>\;
  LOCKSTEP_Out(986) <= \<const0>\;
  LOCKSTEP_Out(987) <= \<const0>\;
  LOCKSTEP_Out(988) <= \<const0>\;
  LOCKSTEP_Out(989) <= \<const0>\;
  LOCKSTEP_Out(990) <= \<const0>\;
  LOCKSTEP_Out(991) <= \<const0>\;
  LOCKSTEP_Out(992) <= \<const0>\;
  LOCKSTEP_Out(993) <= \<const0>\;
  LOCKSTEP_Out(994) <= \<const0>\;
  LOCKSTEP_Out(995) <= \<const0>\;
  LOCKSTEP_Out(996) <= \<const0>\;
  LOCKSTEP_Out(997) <= \<const0>\;
  LOCKSTEP_Out(998) <= \<const0>\;
  LOCKSTEP_Out(999) <= \<const0>\;
  LOCKSTEP_Out(1000) <= \<const0>\;
  LOCKSTEP_Out(1001) <= \<const0>\;
  LOCKSTEP_Out(1002) <= \<const0>\;
  LOCKSTEP_Out(1003) <= \<const0>\;
  LOCKSTEP_Out(1004) <= \<const0>\;
  LOCKSTEP_Out(1005) <= \<const0>\;
  LOCKSTEP_Out(1006) <= \<const0>\;
  LOCKSTEP_Out(1007) <= \<const0>\;
  LOCKSTEP_Out(1008) <= \<const0>\;
  LOCKSTEP_Out(1009) <= \<const0>\;
  LOCKSTEP_Out(1010) <= \<const0>\;
  LOCKSTEP_Out(1011) <= \<const0>\;
  LOCKSTEP_Out(1012) <= \<const0>\;
  LOCKSTEP_Out(1013) <= \<const0>\;
  LOCKSTEP_Out(1014) <= \<const0>\;
  LOCKSTEP_Out(1015) <= \<const0>\;
  LOCKSTEP_Out(1016) <= \<const0>\;
  LOCKSTEP_Out(1017) <= \<const0>\;
  LOCKSTEP_Out(1018) <= \<const0>\;
  LOCKSTEP_Out(1019) <= \<const0>\;
  LOCKSTEP_Out(1020) <= \<const0>\;
  LOCKSTEP_Out(1021) <= \<const0>\;
  LOCKSTEP_Out(1022) <= \<const0>\;
  LOCKSTEP_Out(1023) <= \<const0>\;
  LOCKSTEP_Out(1024) <= \<const0>\;
  LOCKSTEP_Out(1025) <= \<const0>\;
  LOCKSTEP_Out(1026) <= \<const0>\;
  LOCKSTEP_Out(1027) <= \<const0>\;
  LOCKSTEP_Out(1028) <= \<const0>\;
  LOCKSTEP_Out(1029) <= \<const0>\;
  LOCKSTEP_Out(1030) <= \<const0>\;
  LOCKSTEP_Out(1031) <= \<const0>\;
  LOCKSTEP_Out(1032) <= \<const0>\;
  LOCKSTEP_Out(1033) <= \<const0>\;
  LOCKSTEP_Out(1034) <= \<const0>\;
  LOCKSTEP_Out(1035) <= \<const0>\;
  LOCKSTEP_Out(1036) <= \<const0>\;
  LOCKSTEP_Out(1037) <= \<const0>\;
  LOCKSTEP_Out(1038) <= \<const0>\;
  LOCKSTEP_Out(1039) <= \<const0>\;
  LOCKSTEP_Out(1040) <= \<const0>\;
  LOCKSTEP_Out(1041) <= \<const0>\;
  LOCKSTEP_Out(1042) <= \<const0>\;
  LOCKSTEP_Out(1043) <= \<const0>\;
  LOCKSTEP_Out(1044) <= \<const0>\;
  LOCKSTEP_Out(1045) <= \<const0>\;
  LOCKSTEP_Out(1046) <= \<const0>\;
  LOCKSTEP_Out(1047) <= \<const0>\;
  LOCKSTEP_Out(1048) <= \<const0>\;
  LOCKSTEP_Out(1049) <= \<const0>\;
  LOCKSTEP_Out(1050) <= \<const0>\;
  LOCKSTEP_Out(1051) <= \<const0>\;
  LOCKSTEP_Out(1052) <= \<const0>\;
  LOCKSTEP_Out(1053) <= \<const0>\;
  LOCKSTEP_Out(1054) <= \<const0>\;
  LOCKSTEP_Out(1055) <= \<const0>\;
  LOCKSTEP_Out(1056) <= \<const0>\;
  LOCKSTEP_Out(1057) <= \<const0>\;
  LOCKSTEP_Out(1058) <= \<const0>\;
  LOCKSTEP_Out(1059) <= \<const0>\;
  LOCKSTEP_Out(1060) <= \<const0>\;
  LOCKSTEP_Out(1061) <= \<const0>\;
  LOCKSTEP_Out(1062) <= \<const0>\;
  LOCKSTEP_Out(1063) <= \<const0>\;
  LOCKSTEP_Out(1064) <= \<const0>\;
  LOCKSTEP_Out(1065) <= \<const0>\;
  LOCKSTEP_Out(1066) <= \<const0>\;
  LOCKSTEP_Out(1067) <= \<const0>\;
  LOCKSTEP_Out(1068) <= \<const0>\;
  LOCKSTEP_Out(1069) <= \<const0>\;
  LOCKSTEP_Out(1070) <= \<const0>\;
  LOCKSTEP_Out(1071) <= \<const0>\;
  LOCKSTEP_Out(1072) <= \<const0>\;
  LOCKSTEP_Out(1073) <= \<const0>\;
  LOCKSTEP_Out(1074) <= \<const0>\;
  LOCKSTEP_Out(1075) <= \<const0>\;
  LOCKSTEP_Out(1076) <= \<const0>\;
  LOCKSTEP_Out(1077) <= \<const0>\;
  LOCKSTEP_Out(1078) <= \<const0>\;
  LOCKSTEP_Out(1079) <= \<const0>\;
  LOCKSTEP_Out(1080) <= \<const0>\;
  LOCKSTEP_Out(1081) <= \<const0>\;
  LOCKSTEP_Out(1082) <= \<const0>\;
  LOCKSTEP_Out(1083) <= \<const0>\;
  LOCKSTEP_Out(1084) <= \<const0>\;
  LOCKSTEP_Out(1085) <= \<const0>\;
  LOCKSTEP_Out(1086) <= \<const0>\;
  LOCKSTEP_Out(1087) <= \<const0>\;
  LOCKSTEP_Out(1088) <= \<const0>\;
  LOCKSTEP_Out(1089) <= \<const0>\;
  LOCKSTEP_Out(1090) <= \<const0>\;
  LOCKSTEP_Out(1091) <= \<const0>\;
  LOCKSTEP_Out(1092) <= \<const0>\;
  LOCKSTEP_Out(1093) <= \<const0>\;
  LOCKSTEP_Out(1094) <= \<const0>\;
  LOCKSTEP_Out(1095) <= \<const0>\;
  LOCKSTEP_Out(1096) <= \<const0>\;
  LOCKSTEP_Out(1097) <= \<const0>\;
  LOCKSTEP_Out(1098) <= \<const0>\;
  LOCKSTEP_Out(1099) <= \<const0>\;
  LOCKSTEP_Out(1100) <= \<const0>\;
  LOCKSTEP_Out(1101) <= \<const0>\;
  LOCKSTEP_Out(1102) <= \<const0>\;
  LOCKSTEP_Out(1103) <= \<const0>\;
  LOCKSTEP_Out(1104) <= \<const0>\;
  LOCKSTEP_Out(1105) <= \<const0>\;
  LOCKSTEP_Out(1106) <= \<const0>\;
  LOCKSTEP_Out(1107) <= \<const0>\;
  LOCKSTEP_Out(1108) <= \<const0>\;
  LOCKSTEP_Out(1109) <= \<const0>\;
  LOCKSTEP_Out(1110) <= \<const0>\;
  LOCKSTEP_Out(1111) <= \<const0>\;
  LOCKSTEP_Out(1112) <= \<const0>\;
  LOCKSTEP_Out(1113) <= \<const0>\;
  LOCKSTEP_Out(1114) <= \<const0>\;
  LOCKSTEP_Out(1115) <= \<const0>\;
  LOCKSTEP_Out(1116) <= \<const0>\;
  LOCKSTEP_Out(1117) <= \<const0>\;
  LOCKSTEP_Out(1118) <= \<const0>\;
  LOCKSTEP_Out(1119) <= \<const0>\;
  LOCKSTEP_Out(1120) <= \<const0>\;
  LOCKSTEP_Out(1121) <= \<const0>\;
  LOCKSTEP_Out(1122) <= \<const0>\;
  LOCKSTEP_Out(1123) <= \<const0>\;
  LOCKSTEP_Out(1124) <= \<const0>\;
  LOCKSTEP_Out(1125) <= \<const0>\;
  LOCKSTEP_Out(1126) <= \<const0>\;
  LOCKSTEP_Out(1127) <= \<const0>\;
  LOCKSTEP_Out(1128) <= \<const0>\;
  LOCKSTEP_Out(1129) <= \<const0>\;
  LOCKSTEP_Out(1130) <= \<const0>\;
  LOCKSTEP_Out(1131) <= \<const0>\;
  LOCKSTEP_Out(1132) <= \<const0>\;
  LOCKSTEP_Out(1133) <= \<const0>\;
  LOCKSTEP_Out(1134) <= \<const0>\;
  LOCKSTEP_Out(1135) <= \<const0>\;
  LOCKSTEP_Out(1136) <= \<const0>\;
  LOCKSTEP_Out(1137) <= \<const0>\;
  LOCKSTEP_Out(1138) <= \<const0>\;
  LOCKSTEP_Out(1139) <= \<const0>\;
  LOCKSTEP_Out(1140) <= \<const0>\;
  LOCKSTEP_Out(1141) <= \<const0>\;
  LOCKSTEP_Out(1142) <= \<const0>\;
  LOCKSTEP_Out(1143) <= \<const0>\;
  LOCKSTEP_Out(1144) <= \<const0>\;
  LOCKSTEP_Out(1145) <= \<const0>\;
  LOCKSTEP_Out(1146) <= \<const0>\;
  LOCKSTEP_Out(1147) <= \<const0>\;
  LOCKSTEP_Out(1148) <= \<const0>\;
  LOCKSTEP_Out(1149) <= \<const0>\;
  LOCKSTEP_Out(1150) <= \<const0>\;
  LOCKSTEP_Out(1151) <= \<const0>\;
  LOCKSTEP_Out(1152) <= \<const0>\;
  LOCKSTEP_Out(1153) <= \<const0>\;
  LOCKSTEP_Out(1154) <= \<const0>\;
  LOCKSTEP_Out(1155) <= \<const0>\;
  LOCKSTEP_Out(1156) <= \<const0>\;
  LOCKSTEP_Out(1157) <= \<const0>\;
  LOCKSTEP_Out(1158) <= \<const0>\;
  LOCKSTEP_Out(1159) <= \<const0>\;
  LOCKSTEP_Out(1160) <= \<const0>\;
  LOCKSTEP_Out(1161) <= \<const0>\;
  LOCKSTEP_Out(1162) <= \<const0>\;
  LOCKSTEP_Out(1163) <= \<const0>\;
  LOCKSTEP_Out(1164) <= \<const0>\;
  LOCKSTEP_Out(1165) <= \<const0>\;
  LOCKSTEP_Out(1166) <= \<const0>\;
  LOCKSTEP_Out(1167) <= \<const0>\;
  LOCKSTEP_Out(1168) <= \<const0>\;
  LOCKSTEP_Out(1169) <= \<const0>\;
  LOCKSTEP_Out(1170) <= \<const0>\;
  LOCKSTEP_Out(1171) <= \<const0>\;
  LOCKSTEP_Out(1172) <= \<const0>\;
  LOCKSTEP_Out(1173) <= \<const0>\;
  LOCKSTEP_Out(1174) <= \<const0>\;
  LOCKSTEP_Out(1175) <= \<const0>\;
  LOCKSTEP_Out(1176) <= \<const0>\;
  LOCKSTEP_Out(1177) <= \<const0>\;
  LOCKSTEP_Out(1178) <= \<const0>\;
  LOCKSTEP_Out(1179) <= \<const0>\;
  LOCKSTEP_Out(1180) <= \<const0>\;
  LOCKSTEP_Out(1181) <= \<const0>\;
  LOCKSTEP_Out(1182) <= \<const0>\;
  LOCKSTEP_Out(1183) <= \<const0>\;
  LOCKSTEP_Out(1184) <= \<const0>\;
  LOCKSTEP_Out(1185) <= \<const0>\;
  LOCKSTEP_Out(1186) <= \<const0>\;
  LOCKSTEP_Out(1187) <= \<const0>\;
  LOCKSTEP_Out(1188) <= \<const0>\;
  LOCKSTEP_Out(1189) <= \<const0>\;
  LOCKSTEP_Out(1190) <= \<const0>\;
  LOCKSTEP_Out(1191) <= \<const0>\;
  LOCKSTEP_Out(1192) <= \<const0>\;
  LOCKSTEP_Out(1193) <= \<const0>\;
  LOCKSTEP_Out(1194) <= \<const0>\;
  LOCKSTEP_Out(1195) <= \<const0>\;
  LOCKSTEP_Out(1196) <= \<const0>\;
  LOCKSTEP_Out(1197) <= \<const0>\;
  LOCKSTEP_Out(1198) <= \<const0>\;
  LOCKSTEP_Out(1199) <= \<const0>\;
  LOCKSTEP_Out(1200) <= \<const0>\;
  LOCKSTEP_Out(1201) <= \<const0>\;
  LOCKSTEP_Out(1202) <= \<const0>\;
  LOCKSTEP_Out(1203) <= \<const0>\;
  LOCKSTEP_Out(1204) <= \<const0>\;
  LOCKSTEP_Out(1205) <= \<const0>\;
  LOCKSTEP_Out(1206) <= \<const0>\;
  LOCKSTEP_Out(1207) <= \<const0>\;
  LOCKSTEP_Out(1208) <= \<const0>\;
  LOCKSTEP_Out(1209) <= \<const0>\;
  LOCKSTEP_Out(1210) <= \<const0>\;
  LOCKSTEP_Out(1211) <= \<const0>\;
  LOCKSTEP_Out(1212) <= \<const0>\;
  LOCKSTEP_Out(1213) <= \<const0>\;
  LOCKSTEP_Out(1214) <= \<const0>\;
  LOCKSTEP_Out(1215) <= \<const0>\;
  LOCKSTEP_Out(1216) <= \<const0>\;
  LOCKSTEP_Out(1217) <= \<const0>\;
  LOCKSTEP_Out(1218) <= \<const0>\;
  LOCKSTEP_Out(1219) <= \<const0>\;
  LOCKSTEP_Out(1220) <= \<const0>\;
  LOCKSTEP_Out(1221) <= \<const0>\;
  LOCKSTEP_Out(1222) <= \<const0>\;
  LOCKSTEP_Out(1223) <= \<const0>\;
  LOCKSTEP_Out(1224) <= \<const0>\;
  LOCKSTEP_Out(1225) <= \<const0>\;
  LOCKSTEP_Out(1226) <= \<const0>\;
  LOCKSTEP_Out(1227) <= \<const0>\;
  LOCKSTEP_Out(1228) <= \<const0>\;
  LOCKSTEP_Out(1229) <= \<const0>\;
  LOCKSTEP_Out(1230) <= \<const0>\;
  LOCKSTEP_Out(1231) <= \<const0>\;
  LOCKSTEP_Out(1232) <= \<const0>\;
  LOCKSTEP_Out(1233) <= \<const0>\;
  LOCKSTEP_Out(1234) <= \<const0>\;
  LOCKSTEP_Out(1235) <= \<const0>\;
  LOCKSTEP_Out(1236) <= \<const0>\;
  LOCKSTEP_Out(1237) <= \<const0>\;
  LOCKSTEP_Out(1238) <= \<const0>\;
  LOCKSTEP_Out(1239) <= \<const0>\;
  LOCKSTEP_Out(1240) <= \<const0>\;
  LOCKSTEP_Out(1241) <= \<const0>\;
  LOCKSTEP_Out(1242) <= \<const0>\;
  LOCKSTEP_Out(1243) <= \<const0>\;
  LOCKSTEP_Out(1244) <= \<const0>\;
  LOCKSTEP_Out(1245) <= \<const0>\;
  LOCKSTEP_Out(1246) <= \<const0>\;
  LOCKSTEP_Out(1247) <= \<const0>\;
  LOCKSTEP_Out(1248) <= \<const0>\;
  LOCKSTEP_Out(1249) <= \<const0>\;
  LOCKSTEP_Out(1250) <= \<const0>\;
  LOCKSTEP_Out(1251) <= \<const0>\;
  LOCKSTEP_Out(1252) <= \<const0>\;
  LOCKSTEP_Out(1253) <= \<const0>\;
  LOCKSTEP_Out(1254) <= \<const0>\;
  LOCKSTEP_Out(1255) <= \<const0>\;
  LOCKSTEP_Out(1256) <= \<const0>\;
  LOCKSTEP_Out(1257) <= \<const0>\;
  LOCKSTEP_Out(1258) <= \<const0>\;
  LOCKSTEP_Out(1259) <= \<const0>\;
  LOCKSTEP_Out(1260) <= \<const0>\;
  LOCKSTEP_Out(1261) <= \<const0>\;
  LOCKSTEP_Out(1262) <= \<const0>\;
  LOCKSTEP_Out(1263) <= \<const0>\;
  LOCKSTEP_Out(1264) <= \<const0>\;
  LOCKSTEP_Out(1265) <= \<const0>\;
  LOCKSTEP_Out(1266) <= \<const0>\;
  LOCKSTEP_Out(1267) <= \<const0>\;
  LOCKSTEP_Out(1268) <= \<const0>\;
  LOCKSTEP_Out(1269) <= \<const0>\;
  LOCKSTEP_Out(1270) <= \<const0>\;
  LOCKSTEP_Out(1271) <= \<const0>\;
  LOCKSTEP_Out(1272) <= \<const0>\;
  LOCKSTEP_Out(1273) <= \<const0>\;
  LOCKSTEP_Out(1274) <= \<const0>\;
  LOCKSTEP_Out(1275) <= \<const0>\;
  LOCKSTEP_Out(1276) <= \<const0>\;
  LOCKSTEP_Out(1277) <= \<const0>\;
  LOCKSTEP_Out(1278) <= \<const0>\;
  LOCKSTEP_Out(1279) <= \<const0>\;
  LOCKSTEP_Out(1280) <= \<const0>\;
  LOCKSTEP_Out(1281) <= \<const0>\;
  LOCKSTEP_Out(1282) <= \<const0>\;
  LOCKSTEP_Out(1283) <= \<const0>\;
  LOCKSTEP_Out(1284) <= \<const0>\;
  LOCKSTEP_Out(1285) <= \<const0>\;
  LOCKSTEP_Out(1286) <= \<const0>\;
  LOCKSTEP_Out(1287) <= \<const0>\;
  LOCKSTEP_Out(1288) <= \<const0>\;
  LOCKSTEP_Out(1289) <= \<const0>\;
  LOCKSTEP_Out(1290) <= \<const0>\;
  LOCKSTEP_Out(1291) <= \<const0>\;
  LOCKSTEP_Out(1292) <= \<const0>\;
  LOCKSTEP_Out(1293) <= \<const0>\;
  LOCKSTEP_Out(1294) <= \<const0>\;
  LOCKSTEP_Out(1295) <= \<const0>\;
  LOCKSTEP_Out(1296) <= \<const0>\;
  LOCKSTEP_Out(1297) <= \<const0>\;
  LOCKSTEP_Out(1298) <= \<const0>\;
  LOCKSTEP_Out(1299) <= \<const0>\;
  LOCKSTEP_Out(1300) <= \<const0>\;
  LOCKSTEP_Out(1301) <= \<const0>\;
  LOCKSTEP_Out(1302) <= \<const0>\;
  LOCKSTEP_Out(1303) <= \<const0>\;
  LOCKSTEP_Out(1304) <= \<const0>\;
  LOCKSTEP_Out(1305) <= \<const0>\;
  LOCKSTEP_Out(1306) <= \<const0>\;
  LOCKSTEP_Out(1307) <= \<const0>\;
  LOCKSTEP_Out(1308) <= \<const0>\;
  LOCKSTEP_Out(1309) <= \<const0>\;
  LOCKSTEP_Out(1310) <= \<const0>\;
  LOCKSTEP_Out(1311) <= \<const0>\;
  LOCKSTEP_Out(1312) <= \<const0>\;
  LOCKSTEP_Out(1313) <= \<const0>\;
  LOCKSTEP_Out(1314) <= \<const0>\;
  LOCKSTEP_Out(1315) <= \<const0>\;
  LOCKSTEP_Out(1316) <= \<const0>\;
  LOCKSTEP_Out(1317) <= \<const0>\;
  LOCKSTEP_Out(1318) <= \<const0>\;
  LOCKSTEP_Out(1319) <= \<const0>\;
  LOCKSTEP_Out(1320) <= \<const0>\;
  LOCKSTEP_Out(1321) <= \<const0>\;
  LOCKSTEP_Out(1322) <= \<const0>\;
  LOCKSTEP_Out(1323) <= \<const0>\;
  LOCKSTEP_Out(1324) <= \<const0>\;
  LOCKSTEP_Out(1325) <= \<const0>\;
  LOCKSTEP_Out(1326) <= \<const0>\;
  LOCKSTEP_Out(1327) <= \<const0>\;
  LOCKSTEP_Out(1328) <= \<const0>\;
  LOCKSTEP_Out(1329) <= \<const0>\;
  LOCKSTEP_Out(1330) <= \<const0>\;
  LOCKSTEP_Out(1331) <= \<const0>\;
  LOCKSTEP_Out(1332) <= \<const0>\;
  LOCKSTEP_Out(1333) <= \<const0>\;
  LOCKSTEP_Out(1334) <= \<const0>\;
  LOCKSTEP_Out(1335) <= \<const0>\;
  LOCKSTEP_Out(1336) <= \<const0>\;
  LOCKSTEP_Out(1337) <= \<const0>\;
  LOCKSTEP_Out(1338) <= \<const0>\;
  LOCKSTEP_Out(1339) <= \<const0>\;
  LOCKSTEP_Out(1340) <= \<const0>\;
  LOCKSTEP_Out(1341) <= \<const0>\;
  LOCKSTEP_Out(1342) <= \<const0>\;
  LOCKSTEP_Out(1343) <= \<const0>\;
  LOCKSTEP_Out(1344) <= \<const0>\;
  LOCKSTEP_Out(1345) <= \<const0>\;
  LOCKSTEP_Out(1346) <= \<const0>\;
  LOCKSTEP_Out(1347) <= \<const0>\;
  LOCKSTEP_Out(1348) <= \<const0>\;
  LOCKSTEP_Out(1349) <= \<const0>\;
  LOCKSTEP_Out(1350) <= \<const0>\;
  LOCKSTEP_Out(1351) <= \<const0>\;
  LOCKSTEP_Out(1352) <= \<const0>\;
  LOCKSTEP_Out(1353) <= \<const0>\;
  LOCKSTEP_Out(1354) <= \<const0>\;
  LOCKSTEP_Out(1355) <= \<const0>\;
  LOCKSTEP_Out(1356) <= \<const0>\;
  LOCKSTEP_Out(1357) <= \<const0>\;
  LOCKSTEP_Out(1358) <= \<const0>\;
  LOCKSTEP_Out(1359) <= \<const0>\;
  LOCKSTEP_Out(1360) <= \<const0>\;
  LOCKSTEP_Out(1361) <= \<const0>\;
  LOCKSTEP_Out(1362) <= \<const0>\;
  LOCKSTEP_Out(1363) <= \<const0>\;
  LOCKSTEP_Out(1364) <= \<const0>\;
  LOCKSTEP_Out(1365) <= \<const0>\;
  LOCKSTEP_Out(1366) <= \<const0>\;
  LOCKSTEP_Out(1367) <= \<const0>\;
  LOCKSTEP_Out(1368) <= \<const0>\;
  LOCKSTEP_Out(1369) <= \<const0>\;
  LOCKSTEP_Out(1370) <= \<const0>\;
  LOCKSTEP_Out(1371) <= \<const0>\;
  LOCKSTEP_Out(1372) <= \<const0>\;
  LOCKSTEP_Out(1373) <= \<const0>\;
  LOCKSTEP_Out(1374) <= \<const0>\;
  LOCKSTEP_Out(1375) <= \<const0>\;
  LOCKSTEP_Out(1376) <= \<const0>\;
  LOCKSTEP_Out(1377) <= \<const0>\;
  LOCKSTEP_Out(1378) <= \<const0>\;
  LOCKSTEP_Out(1379) <= \<const0>\;
  LOCKSTEP_Out(1380) <= \<const0>\;
  LOCKSTEP_Out(1381) <= \<const0>\;
  LOCKSTEP_Out(1382) <= \<const0>\;
  LOCKSTEP_Out(1383) <= \<const0>\;
  LOCKSTEP_Out(1384) <= \<const0>\;
  LOCKSTEP_Out(1385) <= \<const0>\;
  LOCKSTEP_Out(1386) <= \<const0>\;
  LOCKSTEP_Out(1387) <= \<const0>\;
  LOCKSTEP_Out(1388) <= \<const0>\;
  LOCKSTEP_Out(1389) <= \<const0>\;
  LOCKSTEP_Out(1390) <= \<const0>\;
  LOCKSTEP_Out(1391) <= \<const0>\;
  LOCKSTEP_Out(1392) <= \<const0>\;
  LOCKSTEP_Out(1393) <= \<const0>\;
  LOCKSTEP_Out(1394) <= \<const0>\;
  LOCKSTEP_Out(1395) <= \<const0>\;
  LOCKSTEP_Out(1396) <= \<const0>\;
  LOCKSTEP_Out(1397) <= \<const0>\;
  LOCKSTEP_Out(1398) <= \<const0>\;
  LOCKSTEP_Out(1399) <= \<const0>\;
  LOCKSTEP_Out(1400) <= \<const0>\;
  LOCKSTEP_Out(1401) <= \<const0>\;
  LOCKSTEP_Out(1402) <= \<const0>\;
  LOCKSTEP_Out(1403) <= \<const0>\;
  LOCKSTEP_Out(1404) <= \<const0>\;
  LOCKSTEP_Out(1405) <= \<const0>\;
  LOCKSTEP_Out(1406) <= \<const0>\;
  LOCKSTEP_Out(1407) <= \<const0>\;
  LOCKSTEP_Out(1408) <= \<const0>\;
  LOCKSTEP_Out(1409) <= \<const0>\;
  LOCKSTEP_Out(1410) <= \<const0>\;
  LOCKSTEP_Out(1411) <= \<const0>\;
  LOCKSTEP_Out(1412) <= \<const0>\;
  LOCKSTEP_Out(1413) <= \<const0>\;
  LOCKSTEP_Out(1414) <= \<const0>\;
  LOCKSTEP_Out(1415) <= \<const0>\;
  LOCKSTEP_Out(1416) <= \<const0>\;
  LOCKSTEP_Out(1417) <= \<const0>\;
  LOCKSTEP_Out(1418) <= \<const0>\;
  LOCKSTEP_Out(1419) <= \<const0>\;
  LOCKSTEP_Out(1420) <= \<const0>\;
  LOCKSTEP_Out(1421) <= \<const0>\;
  LOCKSTEP_Out(1422) <= \<const0>\;
  LOCKSTEP_Out(1423) <= \<const0>\;
  LOCKSTEP_Out(1424) <= \<const0>\;
  LOCKSTEP_Out(1425) <= \<const0>\;
  LOCKSTEP_Out(1426) <= \<const0>\;
  LOCKSTEP_Out(1427) <= \<const0>\;
  LOCKSTEP_Out(1428) <= \<const0>\;
  LOCKSTEP_Out(1429) <= \<const0>\;
  LOCKSTEP_Out(1430) <= \<const0>\;
  LOCKSTEP_Out(1431) <= \<const0>\;
  LOCKSTEP_Out(1432) <= \<const0>\;
  LOCKSTEP_Out(1433) <= \<const0>\;
  LOCKSTEP_Out(1434) <= \<const0>\;
  LOCKSTEP_Out(1435) <= \<const0>\;
  LOCKSTEP_Out(1436) <= \<const0>\;
  LOCKSTEP_Out(1437) <= \<const0>\;
  LOCKSTEP_Out(1438) <= \<const0>\;
  LOCKSTEP_Out(1439) <= \<const0>\;
  LOCKSTEP_Out(1440) <= \<const0>\;
  LOCKSTEP_Out(1441) <= \<const0>\;
  LOCKSTEP_Out(1442) <= \<const0>\;
  LOCKSTEP_Out(1443) <= \<const0>\;
  LOCKSTEP_Out(1444) <= \<const0>\;
  LOCKSTEP_Out(1445) <= \<const0>\;
  LOCKSTEP_Out(1446) <= \<const0>\;
  LOCKSTEP_Out(1447) <= \<const0>\;
  LOCKSTEP_Out(1448) <= \<const0>\;
  LOCKSTEP_Out(1449) <= \<const0>\;
  LOCKSTEP_Out(1450) <= \<const0>\;
  LOCKSTEP_Out(1451) <= \<const0>\;
  LOCKSTEP_Out(1452) <= \<const0>\;
  LOCKSTEP_Out(1453) <= \<const0>\;
  LOCKSTEP_Out(1454) <= \<const0>\;
  LOCKSTEP_Out(1455) <= \<const0>\;
  LOCKSTEP_Out(1456) <= \<const0>\;
  LOCKSTEP_Out(1457) <= \<const0>\;
  LOCKSTEP_Out(1458) <= \<const0>\;
  LOCKSTEP_Out(1459) <= \<const0>\;
  LOCKSTEP_Out(1460) <= \<const0>\;
  LOCKSTEP_Out(1461) <= \<const0>\;
  LOCKSTEP_Out(1462) <= \<const0>\;
  LOCKSTEP_Out(1463) <= \<const0>\;
  LOCKSTEP_Out(1464) <= \<const0>\;
  LOCKSTEP_Out(1465) <= \<const0>\;
  LOCKSTEP_Out(1466) <= \<const0>\;
  LOCKSTEP_Out(1467) <= \<const0>\;
  LOCKSTEP_Out(1468) <= \<const0>\;
  LOCKSTEP_Out(1469) <= \<const0>\;
  LOCKSTEP_Out(1470) <= \<const0>\;
  LOCKSTEP_Out(1471) <= \<const0>\;
  LOCKSTEP_Out(1472) <= \<const0>\;
  LOCKSTEP_Out(1473) <= \<const0>\;
  LOCKSTEP_Out(1474) <= \<const0>\;
  LOCKSTEP_Out(1475) <= \<const0>\;
  LOCKSTEP_Out(1476) <= \<const0>\;
  LOCKSTEP_Out(1477) <= \<const0>\;
  LOCKSTEP_Out(1478) <= \<const0>\;
  LOCKSTEP_Out(1479) <= \<const0>\;
  LOCKSTEP_Out(1480) <= \<const0>\;
  LOCKSTEP_Out(1481) <= \<const0>\;
  LOCKSTEP_Out(1482) <= \<const0>\;
  LOCKSTEP_Out(1483) <= \<const0>\;
  LOCKSTEP_Out(1484) <= \<const0>\;
  LOCKSTEP_Out(1485) <= \<const0>\;
  LOCKSTEP_Out(1486) <= \<const0>\;
  LOCKSTEP_Out(1487) <= \<const0>\;
  LOCKSTEP_Out(1488) <= \<const0>\;
  LOCKSTEP_Out(1489) <= \<const0>\;
  LOCKSTEP_Out(1490) <= \<const0>\;
  LOCKSTEP_Out(1491) <= \<const0>\;
  LOCKSTEP_Out(1492) <= \<const0>\;
  LOCKSTEP_Out(1493) <= \<const0>\;
  LOCKSTEP_Out(1494) <= \<const0>\;
  LOCKSTEP_Out(1495) <= \<const0>\;
  LOCKSTEP_Out(1496) <= \<const0>\;
  LOCKSTEP_Out(1497) <= \<const0>\;
  LOCKSTEP_Out(1498) <= \<const0>\;
  LOCKSTEP_Out(1499) <= \<const0>\;
  LOCKSTEP_Out(1500) <= \<const0>\;
  LOCKSTEP_Out(1501) <= \<const0>\;
  LOCKSTEP_Out(1502) <= \<const0>\;
  LOCKSTEP_Out(1503) <= \<const0>\;
  LOCKSTEP_Out(1504) <= \<const0>\;
  LOCKSTEP_Out(1505) <= \<const0>\;
  LOCKSTEP_Out(1506) <= \<const0>\;
  LOCKSTEP_Out(1507) <= \<const0>\;
  LOCKSTEP_Out(1508) <= \<const0>\;
  LOCKSTEP_Out(1509) <= \<const0>\;
  LOCKSTEP_Out(1510) <= \<const0>\;
  LOCKSTEP_Out(1511) <= \<const0>\;
  LOCKSTEP_Out(1512) <= \<const0>\;
  LOCKSTEP_Out(1513) <= \<const0>\;
  LOCKSTEP_Out(1514) <= \<const0>\;
  LOCKSTEP_Out(1515) <= \<const0>\;
  LOCKSTEP_Out(1516) <= \<const0>\;
  LOCKSTEP_Out(1517) <= \<const0>\;
  LOCKSTEP_Out(1518) <= \<const0>\;
  LOCKSTEP_Out(1519) <= \<const0>\;
  LOCKSTEP_Out(1520) <= \<const0>\;
  LOCKSTEP_Out(1521) <= \<const0>\;
  LOCKSTEP_Out(1522) <= \<const0>\;
  LOCKSTEP_Out(1523) <= \<const0>\;
  LOCKSTEP_Out(1524) <= \<const0>\;
  LOCKSTEP_Out(1525) <= \<const0>\;
  LOCKSTEP_Out(1526) <= \<const0>\;
  LOCKSTEP_Out(1527) <= \<const0>\;
  LOCKSTEP_Out(1528) <= \<const0>\;
  LOCKSTEP_Out(1529) <= \<const0>\;
  LOCKSTEP_Out(1530) <= \<const0>\;
  LOCKSTEP_Out(1531) <= \<const0>\;
  LOCKSTEP_Out(1532) <= \<const0>\;
  LOCKSTEP_Out(1533) <= \<const0>\;
  LOCKSTEP_Out(1534) <= \<const0>\;
  LOCKSTEP_Out(1535) <= \<const0>\;
  LOCKSTEP_Out(1536) <= \<const0>\;
  LOCKSTEP_Out(1537) <= \<const0>\;
  LOCKSTEP_Out(1538) <= \<const0>\;
  LOCKSTEP_Out(1539) <= \<const0>\;
  LOCKSTEP_Out(1540) <= \<const0>\;
  LOCKSTEP_Out(1541) <= \<const0>\;
  LOCKSTEP_Out(1542) <= \<const0>\;
  LOCKSTEP_Out(1543) <= \<const0>\;
  LOCKSTEP_Out(1544) <= \<const0>\;
  LOCKSTEP_Out(1545) <= \<const0>\;
  LOCKSTEP_Out(1546) <= \<const0>\;
  LOCKSTEP_Out(1547) <= \<const0>\;
  LOCKSTEP_Out(1548) <= \<const0>\;
  LOCKSTEP_Out(1549) <= \<const0>\;
  LOCKSTEP_Out(1550) <= \<const0>\;
  LOCKSTEP_Out(1551) <= \<const0>\;
  LOCKSTEP_Out(1552) <= \<const0>\;
  LOCKSTEP_Out(1553) <= \<const0>\;
  LOCKSTEP_Out(1554) <= \<const0>\;
  LOCKSTEP_Out(1555) <= \<const0>\;
  LOCKSTEP_Out(1556) <= \<const0>\;
  LOCKSTEP_Out(1557) <= \<const0>\;
  LOCKSTEP_Out(1558) <= \<const0>\;
  LOCKSTEP_Out(1559) <= \<const0>\;
  LOCKSTEP_Out(1560) <= \<const0>\;
  LOCKSTEP_Out(1561) <= \<const0>\;
  LOCKSTEP_Out(1562) <= \<const0>\;
  LOCKSTEP_Out(1563) <= \<const0>\;
  LOCKSTEP_Out(1564) <= \<const0>\;
  LOCKSTEP_Out(1565) <= \<const0>\;
  LOCKSTEP_Out(1566) <= \<const0>\;
  LOCKSTEP_Out(1567) <= \<const0>\;
  LOCKSTEP_Out(1568) <= \<const0>\;
  LOCKSTEP_Out(1569) <= \<const0>\;
  LOCKSTEP_Out(1570) <= \<const0>\;
  LOCKSTEP_Out(1571) <= \<const0>\;
  LOCKSTEP_Out(1572) <= \<const0>\;
  LOCKSTEP_Out(1573) <= \<const0>\;
  LOCKSTEP_Out(1574) <= \<const0>\;
  LOCKSTEP_Out(1575) <= \<const0>\;
  LOCKSTEP_Out(1576) <= \<const0>\;
  LOCKSTEP_Out(1577) <= \<const0>\;
  LOCKSTEP_Out(1578) <= \<const0>\;
  LOCKSTEP_Out(1579) <= \<const0>\;
  LOCKSTEP_Out(1580) <= \<const0>\;
  LOCKSTEP_Out(1581) <= \<const0>\;
  LOCKSTEP_Out(1582) <= \<const0>\;
  LOCKSTEP_Out(1583) <= \<const0>\;
  LOCKSTEP_Out(1584) <= \<const0>\;
  LOCKSTEP_Out(1585) <= \<const0>\;
  LOCKSTEP_Out(1586) <= \<const0>\;
  LOCKSTEP_Out(1587) <= \<const0>\;
  LOCKSTEP_Out(1588) <= \<const0>\;
  LOCKSTEP_Out(1589) <= \<const0>\;
  LOCKSTEP_Out(1590) <= \<const0>\;
  LOCKSTEP_Out(1591) <= \<const0>\;
  LOCKSTEP_Out(1592) <= \<const0>\;
  LOCKSTEP_Out(1593) <= \<const0>\;
  LOCKSTEP_Out(1594) <= \<const0>\;
  LOCKSTEP_Out(1595) <= \<const0>\;
  LOCKSTEP_Out(1596) <= \<const0>\;
  LOCKSTEP_Out(1597) <= \<const0>\;
  LOCKSTEP_Out(1598) <= \<const0>\;
  LOCKSTEP_Out(1599) <= \<const0>\;
  LOCKSTEP_Out(1600) <= \<const0>\;
  LOCKSTEP_Out(1601) <= \<const0>\;
  LOCKSTEP_Out(1602) <= \<const0>\;
  LOCKSTEP_Out(1603) <= \<const0>\;
  LOCKSTEP_Out(1604) <= \<const0>\;
  LOCKSTEP_Out(1605) <= \<const0>\;
  LOCKSTEP_Out(1606) <= \<const0>\;
  LOCKSTEP_Out(1607) <= \<const0>\;
  LOCKSTEP_Out(1608) <= \<const0>\;
  LOCKSTEP_Out(1609) <= \<const0>\;
  LOCKSTEP_Out(1610) <= \<const0>\;
  LOCKSTEP_Out(1611) <= \<const0>\;
  LOCKSTEP_Out(1612) <= \<const0>\;
  LOCKSTEP_Out(1613) <= \<const0>\;
  LOCKSTEP_Out(1614) <= \<const0>\;
  LOCKSTEP_Out(1615) <= \<const0>\;
  LOCKSTEP_Out(1616) <= \<const0>\;
  LOCKSTEP_Out(1617) <= \<const0>\;
  LOCKSTEP_Out(1618) <= \<const0>\;
  LOCKSTEP_Out(1619) <= \<const0>\;
  LOCKSTEP_Out(1620) <= \<const0>\;
  LOCKSTEP_Out(1621) <= \<const0>\;
  LOCKSTEP_Out(1622) <= \<const0>\;
  LOCKSTEP_Out(1623) <= \<const0>\;
  LOCKSTEP_Out(1624) <= \<const0>\;
  LOCKSTEP_Out(1625) <= \<const0>\;
  LOCKSTEP_Out(1626) <= \<const0>\;
  LOCKSTEP_Out(1627) <= \<const0>\;
  LOCKSTEP_Out(1628) <= \<const0>\;
  LOCKSTEP_Out(1629) <= \<const0>\;
  LOCKSTEP_Out(1630) <= \<const0>\;
  LOCKSTEP_Out(1631) <= \<const0>\;
  LOCKSTEP_Out(1632) <= \<const0>\;
  LOCKSTEP_Out(1633) <= \<const0>\;
  LOCKSTEP_Out(1634) <= \<const0>\;
  LOCKSTEP_Out(1635) <= \<const0>\;
  LOCKSTEP_Out(1636) <= \<const0>\;
  LOCKSTEP_Out(1637) <= \<const0>\;
  LOCKSTEP_Out(1638) <= \<const0>\;
  LOCKSTEP_Out(1639) <= \<const0>\;
  LOCKSTEP_Out(1640) <= \<const0>\;
  LOCKSTEP_Out(1641) <= \<const0>\;
  LOCKSTEP_Out(1642) <= \<const0>\;
  LOCKSTEP_Out(1643) <= \<const0>\;
  LOCKSTEP_Out(1644) <= \<const0>\;
  LOCKSTEP_Out(1645) <= \<const0>\;
  LOCKSTEP_Out(1646) <= \<const0>\;
  LOCKSTEP_Out(1647) <= \<const0>\;
  LOCKSTEP_Out(1648) <= \<const0>\;
  LOCKSTEP_Out(1649) <= \<const0>\;
  LOCKSTEP_Out(1650) <= \<const0>\;
  LOCKSTEP_Out(1651) <= \<const0>\;
  LOCKSTEP_Out(1652) <= \<const0>\;
  LOCKSTEP_Out(1653) <= \<const0>\;
  LOCKSTEP_Out(1654) <= \<const0>\;
  LOCKSTEP_Out(1655) <= \<const0>\;
  LOCKSTEP_Out(1656) <= \<const0>\;
  LOCKSTEP_Out(1657) <= \<const0>\;
  LOCKSTEP_Out(1658) <= \<const0>\;
  LOCKSTEP_Out(1659) <= \<const0>\;
  LOCKSTEP_Out(1660) <= \<const0>\;
  LOCKSTEP_Out(1661) <= \<const0>\;
  LOCKSTEP_Out(1662) <= \<const0>\;
  LOCKSTEP_Out(1663) <= \<const0>\;
  LOCKSTEP_Out(1664) <= \<const0>\;
  LOCKSTEP_Out(1665) <= \<const0>\;
  LOCKSTEP_Out(1666) <= \<const0>\;
  LOCKSTEP_Out(1667) <= \<const0>\;
  LOCKSTEP_Out(1668) <= \<const0>\;
  LOCKSTEP_Out(1669) <= \<const0>\;
  LOCKSTEP_Out(1670) <= \<const0>\;
  LOCKSTEP_Out(1671) <= \<const0>\;
  LOCKSTEP_Out(1672) <= \<const0>\;
  LOCKSTEP_Out(1673) <= \<const0>\;
  LOCKSTEP_Out(1674) <= \<const0>\;
  LOCKSTEP_Out(1675) <= \<const0>\;
  LOCKSTEP_Out(1676) <= \<const0>\;
  LOCKSTEP_Out(1677) <= \<const0>\;
  LOCKSTEP_Out(1678) <= \<const0>\;
  LOCKSTEP_Out(1679) <= \<const0>\;
  LOCKSTEP_Out(1680) <= \<const0>\;
  LOCKSTEP_Out(1681) <= \<const0>\;
  LOCKSTEP_Out(1682) <= \<const0>\;
  LOCKSTEP_Out(1683) <= \<const0>\;
  LOCKSTEP_Out(1684) <= \<const0>\;
  LOCKSTEP_Out(1685) <= \<const0>\;
  LOCKSTEP_Out(1686) <= \<const0>\;
  LOCKSTEP_Out(1687) <= \<const0>\;
  LOCKSTEP_Out(1688) <= \<const0>\;
  LOCKSTEP_Out(1689) <= \<const0>\;
  LOCKSTEP_Out(1690) <= \<const0>\;
  LOCKSTEP_Out(1691) <= \<const0>\;
  LOCKSTEP_Out(1692) <= \<const0>\;
  LOCKSTEP_Out(1693) <= \<const0>\;
  LOCKSTEP_Out(1694) <= \<const0>\;
  LOCKSTEP_Out(1695) <= \<const0>\;
  LOCKSTEP_Out(1696) <= \<const0>\;
  LOCKSTEP_Out(1697) <= \<const0>\;
  LOCKSTEP_Out(1698) <= \<const0>\;
  LOCKSTEP_Out(1699) <= \<const0>\;
  LOCKSTEP_Out(1700) <= \<const0>\;
  LOCKSTEP_Out(1701) <= \<const0>\;
  LOCKSTEP_Out(1702) <= \<const0>\;
  LOCKSTEP_Out(1703) <= \<const0>\;
  LOCKSTEP_Out(1704) <= \<const0>\;
  LOCKSTEP_Out(1705) <= \<const0>\;
  LOCKSTEP_Out(1706) <= \<const0>\;
  LOCKSTEP_Out(1707) <= \<const0>\;
  LOCKSTEP_Out(1708) <= \<const0>\;
  LOCKSTEP_Out(1709) <= \<const0>\;
  LOCKSTEP_Out(1710) <= \<const0>\;
  LOCKSTEP_Out(1711) <= \<const0>\;
  LOCKSTEP_Out(1712) <= \<const0>\;
  LOCKSTEP_Out(1713) <= \<const0>\;
  LOCKSTEP_Out(1714) <= \<const0>\;
  LOCKSTEP_Out(1715) <= \<const0>\;
  LOCKSTEP_Out(1716) <= \<const0>\;
  LOCKSTEP_Out(1717) <= \<const0>\;
  LOCKSTEP_Out(1718) <= \<const0>\;
  LOCKSTEP_Out(1719) <= \<const0>\;
  LOCKSTEP_Out(1720) <= \<const0>\;
  LOCKSTEP_Out(1721) <= \<const0>\;
  LOCKSTEP_Out(1722) <= \<const0>\;
  LOCKSTEP_Out(1723) <= \<const0>\;
  LOCKSTEP_Out(1724) <= \<const0>\;
  LOCKSTEP_Out(1725) <= \<const0>\;
  LOCKSTEP_Out(1726) <= \<const0>\;
  LOCKSTEP_Out(1727) <= \<const0>\;
  LOCKSTEP_Out(1728) <= \<const0>\;
  LOCKSTEP_Out(1729) <= \<const0>\;
  LOCKSTEP_Out(1730) <= \<const0>\;
  LOCKSTEP_Out(1731) <= \<const0>\;
  LOCKSTEP_Out(1732) <= \<const0>\;
  LOCKSTEP_Out(1733) <= \<const0>\;
  LOCKSTEP_Out(1734) <= \<const0>\;
  LOCKSTEP_Out(1735) <= \<const0>\;
  LOCKSTEP_Out(1736) <= \<const0>\;
  LOCKSTEP_Out(1737) <= \<const0>\;
  LOCKSTEP_Out(1738) <= \<const0>\;
  LOCKSTEP_Out(1739) <= \<const0>\;
  LOCKSTEP_Out(1740) <= \<const0>\;
  LOCKSTEP_Out(1741) <= \<const0>\;
  LOCKSTEP_Out(1742) <= \<const0>\;
  LOCKSTEP_Out(1743) <= \<const0>\;
  LOCKSTEP_Out(1744) <= \<const0>\;
  LOCKSTEP_Out(1745) <= \<const0>\;
  LOCKSTEP_Out(1746) <= \<const0>\;
  LOCKSTEP_Out(1747) <= \<const0>\;
  LOCKSTEP_Out(1748) <= \<const0>\;
  LOCKSTEP_Out(1749) <= \<const0>\;
  LOCKSTEP_Out(1750) <= \<const0>\;
  LOCKSTEP_Out(1751) <= \<const0>\;
  LOCKSTEP_Out(1752) <= \<const0>\;
  LOCKSTEP_Out(1753) <= \<const0>\;
  LOCKSTEP_Out(1754) <= \<const0>\;
  LOCKSTEP_Out(1755) <= \<const0>\;
  LOCKSTEP_Out(1756) <= \<const0>\;
  LOCKSTEP_Out(1757) <= \<const0>\;
  LOCKSTEP_Out(1758) <= \<const0>\;
  LOCKSTEP_Out(1759) <= \<const0>\;
  LOCKSTEP_Out(1760) <= \<const0>\;
  LOCKSTEP_Out(1761) <= \<const0>\;
  LOCKSTEP_Out(1762) <= \<const0>\;
  LOCKSTEP_Out(1763) <= \<const0>\;
  LOCKSTEP_Out(1764) <= \<const0>\;
  LOCKSTEP_Out(1765) <= \<const0>\;
  LOCKSTEP_Out(1766) <= \<const0>\;
  LOCKSTEP_Out(1767) <= \<const0>\;
  LOCKSTEP_Out(1768) <= \<const0>\;
  LOCKSTEP_Out(1769) <= \<const0>\;
  LOCKSTEP_Out(1770) <= \<const0>\;
  LOCKSTEP_Out(1771) <= \<const0>\;
  LOCKSTEP_Out(1772) <= \<const0>\;
  LOCKSTEP_Out(1773) <= \<const0>\;
  LOCKSTEP_Out(1774) <= \<const0>\;
  LOCKSTEP_Out(1775) <= \<const0>\;
  LOCKSTEP_Out(1776) <= \<const0>\;
  LOCKSTEP_Out(1777) <= \<const0>\;
  LOCKSTEP_Out(1778) <= \<const0>\;
  LOCKSTEP_Out(1779) <= \<const0>\;
  LOCKSTEP_Out(1780) <= \<const0>\;
  LOCKSTEP_Out(1781) <= \<const0>\;
  LOCKSTEP_Out(1782) <= \<const0>\;
  LOCKSTEP_Out(1783) <= \<const0>\;
  LOCKSTEP_Out(1784) <= \<const0>\;
  LOCKSTEP_Out(1785) <= \<const0>\;
  LOCKSTEP_Out(1786) <= \<const0>\;
  LOCKSTEP_Out(1787) <= \<const0>\;
  LOCKSTEP_Out(1788) <= \<const0>\;
  LOCKSTEP_Out(1789) <= \<const0>\;
  LOCKSTEP_Out(1790) <= \<const0>\;
  LOCKSTEP_Out(1791) <= \<const0>\;
  LOCKSTEP_Out(1792) <= \<const0>\;
  LOCKSTEP_Out(1793) <= \<const0>\;
  LOCKSTEP_Out(1794) <= \<const0>\;
  LOCKSTEP_Out(1795) <= \<const0>\;
  LOCKSTEP_Out(1796) <= \<const0>\;
  LOCKSTEP_Out(1797) <= \<const0>\;
  LOCKSTEP_Out(1798) <= \<const0>\;
  LOCKSTEP_Out(1799) <= \<const0>\;
  LOCKSTEP_Out(1800) <= \<const0>\;
  LOCKSTEP_Out(1801) <= \<const0>\;
  LOCKSTEP_Out(1802) <= \<const0>\;
  LOCKSTEP_Out(1803) <= \<const0>\;
  LOCKSTEP_Out(1804) <= \<const0>\;
  LOCKSTEP_Out(1805) <= \<const0>\;
  LOCKSTEP_Out(1806) <= \<const0>\;
  LOCKSTEP_Out(1807) <= \<const0>\;
  LOCKSTEP_Out(1808) <= \<const0>\;
  LOCKSTEP_Out(1809) <= \<const0>\;
  LOCKSTEP_Out(1810) <= \<const0>\;
  LOCKSTEP_Out(1811) <= \<const0>\;
  LOCKSTEP_Out(1812) <= \<const0>\;
  LOCKSTEP_Out(1813) <= \<const0>\;
  LOCKSTEP_Out(1814) <= \<const0>\;
  LOCKSTEP_Out(1815) <= \<const0>\;
  LOCKSTEP_Out(1816) <= \<const0>\;
  LOCKSTEP_Out(1817) <= \<const0>\;
  LOCKSTEP_Out(1818) <= \<const0>\;
  LOCKSTEP_Out(1819) <= \<const0>\;
  LOCKSTEP_Out(1820) <= \<const0>\;
  LOCKSTEP_Out(1821) <= \<const0>\;
  LOCKSTEP_Out(1822) <= \<const0>\;
  LOCKSTEP_Out(1823) <= \<const0>\;
  LOCKSTEP_Out(1824) <= \<const0>\;
  LOCKSTEP_Out(1825) <= \<const0>\;
  LOCKSTEP_Out(1826) <= \<const0>\;
  LOCKSTEP_Out(1827) <= \<const0>\;
  LOCKSTEP_Out(1828) <= \<const0>\;
  LOCKSTEP_Out(1829) <= \<const0>\;
  LOCKSTEP_Out(1830) <= \<const0>\;
  LOCKSTEP_Out(1831) <= \<const0>\;
  LOCKSTEP_Out(1832) <= \<const0>\;
  LOCKSTEP_Out(1833) <= \<const0>\;
  LOCKSTEP_Out(1834) <= \<const0>\;
  LOCKSTEP_Out(1835) <= \<const0>\;
  LOCKSTEP_Out(1836) <= \<const0>\;
  LOCKSTEP_Out(1837) <= \<const0>\;
  LOCKSTEP_Out(1838) <= \<const0>\;
  LOCKSTEP_Out(1839) <= \<const0>\;
  LOCKSTEP_Out(1840) <= \<const0>\;
  LOCKSTEP_Out(1841) <= \<const0>\;
  LOCKSTEP_Out(1842) <= \<const0>\;
  LOCKSTEP_Out(1843) <= \<const0>\;
  LOCKSTEP_Out(1844) <= \<const0>\;
  LOCKSTEP_Out(1845) <= \<const0>\;
  LOCKSTEP_Out(1846) <= \<const0>\;
  LOCKSTEP_Out(1847) <= \<const0>\;
  LOCKSTEP_Out(1848) <= \<const0>\;
  LOCKSTEP_Out(1849) <= \<const0>\;
  LOCKSTEP_Out(1850) <= \<const0>\;
  LOCKSTEP_Out(1851) <= \<const0>\;
  LOCKSTEP_Out(1852) <= \<const0>\;
  LOCKSTEP_Out(1853) <= \<const0>\;
  LOCKSTEP_Out(1854) <= \<const0>\;
  LOCKSTEP_Out(1855) <= \<const0>\;
  LOCKSTEP_Out(1856) <= \<const0>\;
  LOCKSTEP_Out(1857) <= \<const0>\;
  LOCKSTEP_Out(1858) <= \<const0>\;
  LOCKSTEP_Out(1859) <= \<const0>\;
  LOCKSTEP_Out(1860) <= \<const0>\;
  LOCKSTEP_Out(1861) <= \<const0>\;
  LOCKSTEP_Out(1862) <= \<const0>\;
  LOCKSTEP_Out(1863) <= \<const0>\;
  LOCKSTEP_Out(1864) <= \<const0>\;
  LOCKSTEP_Out(1865) <= \<const0>\;
  LOCKSTEP_Out(1866) <= \<const0>\;
  LOCKSTEP_Out(1867) <= \<const0>\;
  LOCKSTEP_Out(1868) <= \<const0>\;
  LOCKSTEP_Out(1869) <= \<const0>\;
  LOCKSTEP_Out(1870) <= \<const0>\;
  LOCKSTEP_Out(1871) <= \<const0>\;
  LOCKSTEP_Out(1872) <= \<const0>\;
  LOCKSTEP_Out(1873) <= \<const0>\;
  LOCKSTEP_Out(1874) <= \<const0>\;
  LOCKSTEP_Out(1875) <= \<const0>\;
  LOCKSTEP_Out(1876) <= \<const0>\;
  LOCKSTEP_Out(1877) <= \<const0>\;
  LOCKSTEP_Out(1878) <= \<const0>\;
  LOCKSTEP_Out(1879) <= \<const0>\;
  LOCKSTEP_Out(1880) <= \<const0>\;
  LOCKSTEP_Out(1881) <= \<const0>\;
  LOCKSTEP_Out(1882) <= \<const0>\;
  LOCKSTEP_Out(1883) <= \<const0>\;
  LOCKSTEP_Out(1884) <= \<const0>\;
  LOCKSTEP_Out(1885) <= \<const0>\;
  LOCKSTEP_Out(1886) <= \<const0>\;
  LOCKSTEP_Out(1887) <= \<const0>\;
  LOCKSTEP_Out(1888) <= \<const0>\;
  LOCKSTEP_Out(1889) <= \<const0>\;
  LOCKSTEP_Out(1890) <= \<const0>\;
  LOCKSTEP_Out(1891) <= \<const0>\;
  LOCKSTEP_Out(1892) <= \<const0>\;
  LOCKSTEP_Out(1893) <= \<const0>\;
  LOCKSTEP_Out(1894) <= \<const0>\;
  LOCKSTEP_Out(1895) <= \<const0>\;
  LOCKSTEP_Out(1896) <= \<const0>\;
  LOCKSTEP_Out(1897) <= \<const0>\;
  LOCKSTEP_Out(1898) <= \<const0>\;
  LOCKSTEP_Out(1899) <= \<const0>\;
  LOCKSTEP_Out(1900) <= \<const0>\;
  LOCKSTEP_Out(1901) <= \<const0>\;
  LOCKSTEP_Out(1902) <= \<const0>\;
  LOCKSTEP_Out(1903) <= \<const0>\;
  LOCKSTEP_Out(1904) <= \<const0>\;
  LOCKSTEP_Out(1905) <= \<const0>\;
  LOCKSTEP_Out(1906) <= \<const0>\;
  LOCKSTEP_Out(1907) <= \<const0>\;
  LOCKSTEP_Out(1908) <= \<const0>\;
  LOCKSTEP_Out(1909) <= \<const0>\;
  LOCKSTEP_Out(1910) <= \<const0>\;
  LOCKSTEP_Out(1911) <= \<const0>\;
  LOCKSTEP_Out(1912) <= \<const0>\;
  LOCKSTEP_Out(1913) <= \<const0>\;
  LOCKSTEP_Out(1914) <= \<const0>\;
  LOCKSTEP_Out(1915) <= \<const0>\;
  LOCKSTEP_Out(1916) <= \<const0>\;
  LOCKSTEP_Out(1917) <= \<const0>\;
  LOCKSTEP_Out(1918) <= \<const0>\;
  LOCKSTEP_Out(1919) <= \<const0>\;
  LOCKSTEP_Out(1920) <= \<const0>\;
  LOCKSTEP_Out(1921) <= \<const0>\;
  LOCKSTEP_Out(1922) <= \<const0>\;
  LOCKSTEP_Out(1923) <= \<const0>\;
  LOCKSTEP_Out(1924) <= \<const0>\;
  LOCKSTEP_Out(1925) <= \<const0>\;
  LOCKSTEP_Out(1926) <= \<const0>\;
  LOCKSTEP_Out(1927) <= \<const0>\;
  LOCKSTEP_Out(1928) <= \<const0>\;
  LOCKSTEP_Out(1929) <= \<const0>\;
  LOCKSTEP_Out(1930) <= \<const0>\;
  LOCKSTEP_Out(1931) <= \<const0>\;
  LOCKSTEP_Out(1932) <= \<const0>\;
  LOCKSTEP_Out(1933) <= \<const0>\;
  LOCKSTEP_Out(1934) <= \<const0>\;
  LOCKSTEP_Out(1935) <= \<const0>\;
  LOCKSTEP_Out(1936) <= \<const0>\;
  LOCKSTEP_Out(1937) <= \<const0>\;
  LOCKSTEP_Out(1938) <= \<const0>\;
  LOCKSTEP_Out(1939) <= \<const0>\;
  LOCKSTEP_Out(1940) <= \<const0>\;
  LOCKSTEP_Out(1941) <= \<const0>\;
  LOCKSTEP_Out(1942) <= \<const0>\;
  LOCKSTEP_Out(1943) <= \<const0>\;
  LOCKSTEP_Out(1944) <= \<const0>\;
  LOCKSTEP_Out(1945) <= \<const0>\;
  LOCKSTEP_Out(1946) <= \<const0>\;
  LOCKSTEP_Out(1947) <= \<const0>\;
  LOCKSTEP_Out(1948) <= \<const0>\;
  LOCKSTEP_Out(1949) <= \<const0>\;
  LOCKSTEP_Out(1950) <= \<const0>\;
  LOCKSTEP_Out(1951) <= \<const0>\;
  LOCKSTEP_Out(1952) <= \<const0>\;
  LOCKSTEP_Out(1953) <= \<const0>\;
  LOCKSTEP_Out(1954) <= \<const0>\;
  LOCKSTEP_Out(1955) <= \<const0>\;
  LOCKSTEP_Out(1956) <= \<const0>\;
  LOCKSTEP_Out(1957) <= \<const0>\;
  LOCKSTEP_Out(1958) <= \<const0>\;
  LOCKSTEP_Out(1959) <= \<const0>\;
  LOCKSTEP_Out(1960) <= \<const0>\;
  LOCKSTEP_Out(1961) <= \<const0>\;
  LOCKSTEP_Out(1962) <= \<const0>\;
  LOCKSTEP_Out(1963) <= \<const0>\;
  LOCKSTEP_Out(1964) <= \<const0>\;
  LOCKSTEP_Out(1965) <= \<const0>\;
  LOCKSTEP_Out(1966) <= \<const0>\;
  LOCKSTEP_Out(1967) <= \<const0>\;
  LOCKSTEP_Out(1968) <= \<const0>\;
  LOCKSTEP_Out(1969) <= \<const0>\;
  LOCKSTEP_Out(1970) <= \<const0>\;
  LOCKSTEP_Out(1971) <= \<const0>\;
  LOCKSTEP_Out(1972) <= \<const0>\;
  LOCKSTEP_Out(1973) <= \<const0>\;
  LOCKSTEP_Out(1974) <= \<const0>\;
  LOCKSTEP_Out(1975) <= \<const0>\;
  LOCKSTEP_Out(1976) <= \<const0>\;
  LOCKSTEP_Out(1977) <= \<const0>\;
  LOCKSTEP_Out(1978) <= \<const0>\;
  LOCKSTEP_Out(1979) <= \<const0>\;
  LOCKSTEP_Out(1980) <= \<const0>\;
  LOCKSTEP_Out(1981) <= \<const0>\;
  LOCKSTEP_Out(1982) <= \<const0>\;
  LOCKSTEP_Out(1983) <= \<const0>\;
  LOCKSTEP_Out(1984) <= \<const0>\;
  LOCKSTEP_Out(1985) <= \<const0>\;
  LOCKSTEP_Out(1986) <= \<const0>\;
  LOCKSTEP_Out(1987) <= \<const0>\;
  LOCKSTEP_Out(1988) <= \<const0>\;
  LOCKSTEP_Out(1989) <= \<const0>\;
  LOCKSTEP_Out(1990) <= \<const0>\;
  LOCKSTEP_Out(1991) <= \<const0>\;
  LOCKSTEP_Out(1992) <= \<const0>\;
  LOCKSTEP_Out(1993) <= \<const0>\;
  LOCKSTEP_Out(1994) <= \<const0>\;
  LOCKSTEP_Out(1995) <= \<const0>\;
  LOCKSTEP_Out(1996) <= \<const0>\;
  LOCKSTEP_Out(1997) <= \<const0>\;
  LOCKSTEP_Out(1998) <= \<const0>\;
  LOCKSTEP_Out(1999) <= \<const0>\;
  LOCKSTEP_Out(2000) <= \<const0>\;
  LOCKSTEP_Out(2001) <= \<const0>\;
  LOCKSTEP_Out(2002) <= \<const0>\;
  LOCKSTEP_Out(2003) <= \<const0>\;
  LOCKSTEP_Out(2004) <= \<const0>\;
  LOCKSTEP_Out(2005) <= \<const0>\;
  LOCKSTEP_Out(2006) <= \<const0>\;
  LOCKSTEP_Out(2007) <= \<const0>\;
  LOCKSTEP_Out(2008) <= \<const0>\;
  LOCKSTEP_Out(2009) <= \<const0>\;
  LOCKSTEP_Out(2010) <= \<const0>\;
  LOCKSTEP_Out(2011) <= \<const0>\;
  LOCKSTEP_Out(2012) <= \<const0>\;
  LOCKSTEP_Out(2013) <= \<const0>\;
  LOCKSTEP_Out(2014) <= \<const0>\;
  LOCKSTEP_Out(2015) <= \<const0>\;
  LOCKSTEP_Out(2016) <= \<const0>\;
  LOCKSTEP_Out(2017) <= \<const0>\;
  LOCKSTEP_Out(2018) <= \<const0>\;
  LOCKSTEP_Out(2019) <= \<const0>\;
  LOCKSTEP_Out(2020) <= \<const0>\;
  LOCKSTEP_Out(2021) <= \<const0>\;
  LOCKSTEP_Out(2022) <= \<const0>\;
  LOCKSTEP_Out(2023) <= \<const0>\;
  LOCKSTEP_Out(2024) <= \<const0>\;
  LOCKSTEP_Out(2025) <= \<const0>\;
  LOCKSTEP_Out(2026) <= \<const0>\;
  LOCKSTEP_Out(2027) <= \<const0>\;
  LOCKSTEP_Out(2028) <= \<const0>\;
  LOCKSTEP_Out(2029) <= \<const0>\;
  LOCKSTEP_Out(2030) <= \<const0>\;
  LOCKSTEP_Out(2031) <= \<const0>\;
  LOCKSTEP_Out(2032) <= \<const0>\;
  LOCKSTEP_Out(2033) <= \<const0>\;
  LOCKSTEP_Out(2034) <= \<const0>\;
  LOCKSTEP_Out(2035) <= \<const0>\;
  LOCKSTEP_Out(2036) <= \<const0>\;
  LOCKSTEP_Out(2037) <= \<const0>\;
  LOCKSTEP_Out(2038) <= \<const0>\;
  LOCKSTEP_Out(2039) <= \<const0>\;
  LOCKSTEP_Out(2040) <= \<const0>\;
  LOCKSTEP_Out(2041) <= \<const0>\;
  LOCKSTEP_Out(2042) <= \<const0>\;
  LOCKSTEP_Out(2043) <= \<const0>\;
  LOCKSTEP_Out(2044) <= \<const0>\;
  LOCKSTEP_Out(2045) <= \<const0>\;
  LOCKSTEP_Out(2046) <= \<const0>\;
  LOCKSTEP_Out(2047) <= \<const0>\;
  LOCKSTEP_Out(2048) <= \<const0>\;
  LOCKSTEP_Out(2049) <= \<const0>\;
  LOCKSTEP_Out(2050) <= \<const0>\;
  LOCKSTEP_Out(2051) <= \<const0>\;
  LOCKSTEP_Out(2052) <= \<const0>\;
  LOCKSTEP_Out(2053) <= \<const0>\;
  LOCKSTEP_Out(2054) <= \<const0>\;
  LOCKSTEP_Out(2055) <= \<const0>\;
  LOCKSTEP_Out(2056) <= \<const0>\;
  LOCKSTEP_Out(2057) <= \<const0>\;
  LOCKSTEP_Out(2058) <= \<const0>\;
  LOCKSTEP_Out(2059) <= \<const0>\;
  LOCKSTEP_Out(2060) <= \<const0>\;
  LOCKSTEP_Out(2061) <= \<const0>\;
  LOCKSTEP_Out(2062) <= \<const0>\;
  LOCKSTEP_Out(2063) <= \<const0>\;
  LOCKSTEP_Out(2064) <= \<const0>\;
  LOCKSTEP_Out(2065) <= \<const0>\;
  LOCKSTEP_Out(2066) <= \<const0>\;
  LOCKSTEP_Out(2067) <= \<const0>\;
  LOCKSTEP_Out(2068) <= \<const0>\;
  LOCKSTEP_Out(2069) <= \<const0>\;
  LOCKSTEP_Out(2070) <= \<const0>\;
  LOCKSTEP_Out(2071) <= \<const0>\;
  LOCKSTEP_Out(2072) <= \<const0>\;
  LOCKSTEP_Out(2073) <= \<const0>\;
  LOCKSTEP_Out(2074) <= \<const0>\;
  LOCKSTEP_Out(2075) <= \<const0>\;
  LOCKSTEP_Out(2076) <= \<const0>\;
  LOCKSTEP_Out(2077) <= \<const0>\;
  LOCKSTEP_Out(2078) <= \<const0>\;
  LOCKSTEP_Out(2079) <= \<const0>\;
  LOCKSTEP_Out(2080) <= \<const0>\;
  LOCKSTEP_Out(2081) <= \<const0>\;
  LOCKSTEP_Out(2082) <= \<const0>\;
  LOCKSTEP_Out(2083) <= \<const0>\;
  LOCKSTEP_Out(2084) <= \<const0>\;
  LOCKSTEP_Out(2085) <= \<const0>\;
  LOCKSTEP_Out(2086) <= \<const0>\;
  LOCKSTEP_Out(2087) <= \<const0>\;
  LOCKSTEP_Out(2088) <= \<const0>\;
  LOCKSTEP_Out(2089) <= \<const0>\;
  LOCKSTEP_Out(2090) <= \<const0>\;
  LOCKSTEP_Out(2091) <= \<const0>\;
  LOCKSTEP_Out(2092) <= \<const0>\;
  LOCKSTEP_Out(2093) <= \<const0>\;
  LOCKSTEP_Out(2094) <= \<const0>\;
  LOCKSTEP_Out(2095) <= \<const0>\;
  LOCKSTEP_Out(2096) <= \<const0>\;
  LOCKSTEP_Out(2097) <= \<const0>\;
  LOCKSTEP_Out(2098) <= \<const0>\;
  LOCKSTEP_Out(2099) <= \<const0>\;
  LOCKSTEP_Out(2100) <= \<const0>\;
  LOCKSTEP_Out(2101) <= \<const0>\;
  LOCKSTEP_Out(2102) <= \<const0>\;
  LOCKSTEP_Out(2103) <= \<const0>\;
  LOCKSTEP_Out(2104) <= \<const0>\;
  LOCKSTEP_Out(2105) <= \<const0>\;
  LOCKSTEP_Out(2106) <= \<const0>\;
  LOCKSTEP_Out(2107) <= \<const0>\;
  LOCKSTEP_Out(2108) <= \<const0>\;
  LOCKSTEP_Out(2109) <= \<const0>\;
  LOCKSTEP_Out(2110) <= \<const0>\;
  LOCKSTEP_Out(2111) <= \<const0>\;
  LOCKSTEP_Out(2112) <= \<const0>\;
  LOCKSTEP_Out(2113) <= \<const0>\;
  LOCKSTEP_Out(2114) <= \<const0>\;
  LOCKSTEP_Out(2115) <= \<const0>\;
  LOCKSTEP_Out(2116) <= \<const0>\;
  LOCKSTEP_Out(2117) <= \<const0>\;
  LOCKSTEP_Out(2118) <= \<const0>\;
  LOCKSTEP_Out(2119) <= \<const0>\;
  LOCKSTEP_Out(2120) <= \<const0>\;
  LOCKSTEP_Out(2121) <= \<const0>\;
  LOCKSTEP_Out(2122) <= \<const0>\;
  LOCKSTEP_Out(2123) <= \<const0>\;
  LOCKSTEP_Out(2124) <= \<const0>\;
  LOCKSTEP_Out(2125) <= \<const0>\;
  LOCKSTEP_Out(2126) <= \<const0>\;
  LOCKSTEP_Out(2127) <= \<const0>\;
  LOCKSTEP_Out(2128) <= \<const0>\;
  LOCKSTEP_Out(2129) <= \<const0>\;
  LOCKSTEP_Out(2130) <= \<const0>\;
  LOCKSTEP_Out(2131) <= \<const0>\;
  LOCKSTEP_Out(2132) <= \<const0>\;
  LOCKSTEP_Out(2133) <= \<const0>\;
  LOCKSTEP_Out(2134) <= \<const0>\;
  LOCKSTEP_Out(2135) <= \<const0>\;
  LOCKSTEP_Out(2136) <= \<const0>\;
  LOCKSTEP_Out(2137) <= \<const0>\;
  LOCKSTEP_Out(2138) <= \<const0>\;
  LOCKSTEP_Out(2139) <= \<const0>\;
  LOCKSTEP_Out(2140) <= \<const0>\;
  LOCKSTEP_Out(2141) <= \<const0>\;
  LOCKSTEP_Out(2142) <= \<const0>\;
  LOCKSTEP_Out(2143) <= \<const0>\;
  LOCKSTEP_Out(2144) <= \<const0>\;
  LOCKSTEP_Out(2145) <= \<const0>\;
  LOCKSTEP_Out(2146) <= \<const0>\;
  LOCKSTEP_Out(2147) <= \<const0>\;
  LOCKSTEP_Out(2148) <= \<const0>\;
  LOCKSTEP_Out(2149) <= \<const0>\;
  LOCKSTEP_Out(2150) <= \<const0>\;
  LOCKSTEP_Out(2151) <= \<const0>\;
  LOCKSTEP_Out(2152) <= \<const0>\;
  LOCKSTEP_Out(2153) <= \<const0>\;
  LOCKSTEP_Out(2154) <= \<const0>\;
  LOCKSTEP_Out(2155) <= \<const0>\;
  LOCKSTEP_Out(2156) <= \<const0>\;
  LOCKSTEP_Out(2157) <= \<const0>\;
  LOCKSTEP_Out(2158) <= \<const0>\;
  LOCKSTEP_Out(2159) <= \<const0>\;
  LOCKSTEP_Out(2160) <= \<const0>\;
  LOCKSTEP_Out(2161) <= \<const0>\;
  LOCKSTEP_Out(2162) <= \<const0>\;
  LOCKSTEP_Out(2163) <= \<const0>\;
  LOCKSTEP_Out(2164) <= \<const0>\;
  LOCKSTEP_Out(2165) <= \<const0>\;
  LOCKSTEP_Out(2166) <= \<const0>\;
  LOCKSTEP_Out(2167) <= \<const0>\;
  LOCKSTEP_Out(2168) <= \<const0>\;
  LOCKSTEP_Out(2169) <= \<const0>\;
  LOCKSTEP_Out(2170) <= \<const0>\;
  LOCKSTEP_Out(2171) <= \<const0>\;
  LOCKSTEP_Out(2172) <= \<const0>\;
  LOCKSTEP_Out(2173) <= \<const0>\;
  LOCKSTEP_Out(2174) <= \<const0>\;
  LOCKSTEP_Out(2175) <= \<const0>\;
  LOCKSTEP_Out(2176) <= \<const0>\;
  LOCKSTEP_Out(2177) <= \<const0>\;
  LOCKSTEP_Out(2178) <= \<const0>\;
  LOCKSTEP_Out(2179) <= \<const0>\;
  LOCKSTEP_Out(2180) <= \<const0>\;
  LOCKSTEP_Out(2181) <= \<const0>\;
  LOCKSTEP_Out(2182) <= \<const0>\;
  LOCKSTEP_Out(2183) <= \<const0>\;
  LOCKSTEP_Out(2184) <= \<const0>\;
  LOCKSTEP_Out(2185) <= \<const0>\;
  LOCKSTEP_Out(2186) <= \<const0>\;
  LOCKSTEP_Out(2187) <= \<const0>\;
  LOCKSTEP_Out(2188) <= \<const0>\;
  LOCKSTEP_Out(2189) <= \<const0>\;
  LOCKSTEP_Out(2190) <= \<const0>\;
  LOCKSTEP_Out(2191) <= \<const0>\;
  LOCKSTEP_Out(2192) <= \<const0>\;
  LOCKSTEP_Out(2193) <= \<const0>\;
  LOCKSTEP_Out(2194) <= \<const0>\;
  LOCKSTEP_Out(2195) <= \<const0>\;
  LOCKSTEP_Out(2196) <= \<const0>\;
  LOCKSTEP_Out(2197) <= \<const0>\;
  LOCKSTEP_Out(2198) <= \<const0>\;
  LOCKSTEP_Out(2199) <= \<const0>\;
  LOCKSTEP_Out(2200) <= \<const0>\;
  LOCKSTEP_Out(2201) <= \<const0>\;
  LOCKSTEP_Out(2202) <= \<const0>\;
  LOCKSTEP_Out(2203) <= \<const0>\;
  LOCKSTEP_Out(2204) <= \<const0>\;
  LOCKSTEP_Out(2205) <= \<const0>\;
  LOCKSTEP_Out(2206) <= \<const0>\;
  LOCKSTEP_Out(2207) <= \<const0>\;
  LOCKSTEP_Out(2208) <= \<const0>\;
  LOCKSTEP_Out(2209) <= \<const0>\;
  LOCKSTEP_Out(2210) <= \<const0>\;
  LOCKSTEP_Out(2211) <= \<const0>\;
  LOCKSTEP_Out(2212) <= \<const0>\;
  LOCKSTEP_Out(2213) <= \<const0>\;
  LOCKSTEP_Out(2214) <= \<const0>\;
  LOCKSTEP_Out(2215) <= \<const0>\;
  LOCKSTEP_Out(2216) <= \<const0>\;
  LOCKSTEP_Out(2217) <= \<const0>\;
  LOCKSTEP_Out(2218) <= \<const0>\;
  LOCKSTEP_Out(2219) <= \<const0>\;
  LOCKSTEP_Out(2220) <= \<const0>\;
  LOCKSTEP_Out(2221) <= \<const0>\;
  LOCKSTEP_Out(2222) <= \<const0>\;
  LOCKSTEP_Out(2223) <= \<const0>\;
  LOCKSTEP_Out(2224) <= \<const0>\;
  LOCKSTEP_Out(2225) <= \<const0>\;
  LOCKSTEP_Out(2226) <= \<const0>\;
  LOCKSTEP_Out(2227) <= \<const0>\;
  LOCKSTEP_Out(2228) <= \<const0>\;
  LOCKSTEP_Out(2229) <= \<const0>\;
  LOCKSTEP_Out(2230) <= \<const0>\;
  LOCKSTEP_Out(2231) <= \<const0>\;
  LOCKSTEP_Out(2232) <= \<const0>\;
  LOCKSTEP_Out(2233) <= \<const0>\;
  LOCKSTEP_Out(2234) <= \<const0>\;
  LOCKSTEP_Out(2235) <= \<const0>\;
  LOCKSTEP_Out(2236) <= \<const0>\;
  LOCKSTEP_Out(2237) <= \<const0>\;
  LOCKSTEP_Out(2238) <= \<const0>\;
  LOCKSTEP_Out(2239) <= \<const0>\;
  LOCKSTEP_Out(2240) <= \<const0>\;
  LOCKSTEP_Out(2241) <= \<const0>\;
  LOCKSTEP_Out(2242) <= \<const0>\;
  LOCKSTEP_Out(2243) <= \<const0>\;
  LOCKSTEP_Out(2244) <= \<const0>\;
  LOCKSTEP_Out(2245) <= \<const0>\;
  LOCKSTEP_Out(2246) <= \<const0>\;
  LOCKSTEP_Out(2247) <= \<const0>\;
  LOCKSTEP_Out(2248) <= \<const0>\;
  LOCKSTEP_Out(2249) <= \<const0>\;
  LOCKSTEP_Out(2250) <= \<const0>\;
  LOCKSTEP_Out(2251) <= \<const0>\;
  LOCKSTEP_Out(2252) <= \<const0>\;
  LOCKSTEP_Out(2253) <= \<const0>\;
  LOCKSTEP_Out(2254) <= \<const0>\;
  LOCKSTEP_Out(2255) <= \<const0>\;
  LOCKSTEP_Out(2256) <= \<const0>\;
  LOCKSTEP_Out(2257) <= \<const0>\;
  LOCKSTEP_Out(2258) <= \<const0>\;
  LOCKSTEP_Out(2259) <= \<const0>\;
  LOCKSTEP_Out(2260) <= \<const0>\;
  LOCKSTEP_Out(2261) <= \<const0>\;
  LOCKSTEP_Out(2262) <= \<const0>\;
  LOCKSTEP_Out(2263) <= \<const0>\;
  LOCKSTEP_Out(2264) <= \<const0>\;
  LOCKSTEP_Out(2265) <= \<const0>\;
  LOCKSTEP_Out(2266) <= \<const0>\;
  LOCKSTEP_Out(2267) <= \<const0>\;
  LOCKSTEP_Out(2268) <= \<const0>\;
  LOCKSTEP_Out(2269) <= \<const0>\;
  LOCKSTEP_Out(2270) <= \<const0>\;
  LOCKSTEP_Out(2271) <= \<const0>\;
  LOCKSTEP_Out(2272) <= \<const0>\;
  LOCKSTEP_Out(2273) <= \<const0>\;
  LOCKSTEP_Out(2274) <= \<const0>\;
  LOCKSTEP_Out(2275) <= \<const0>\;
  LOCKSTEP_Out(2276) <= \<const0>\;
  LOCKSTEP_Out(2277) <= \<const0>\;
  LOCKSTEP_Out(2278) <= \<const0>\;
  LOCKSTEP_Out(2279) <= \<const0>\;
  LOCKSTEP_Out(2280) <= \<const0>\;
  LOCKSTEP_Out(2281) <= \<const0>\;
  LOCKSTEP_Out(2282) <= \<const0>\;
  LOCKSTEP_Out(2283) <= \<const0>\;
  LOCKSTEP_Out(2284) <= \<const0>\;
  LOCKSTEP_Out(2285) <= \<const0>\;
  LOCKSTEP_Out(2286) <= \<const0>\;
  LOCKSTEP_Out(2287) <= \<const0>\;
  LOCKSTEP_Out(2288) <= \<const0>\;
  LOCKSTEP_Out(2289) <= \<const0>\;
  LOCKSTEP_Out(2290) <= \<const0>\;
  LOCKSTEP_Out(2291) <= \<const0>\;
  LOCKSTEP_Out(2292) <= \<const0>\;
  LOCKSTEP_Out(2293) <= \<const0>\;
  LOCKSTEP_Out(2294) <= \<const0>\;
  LOCKSTEP_Out(2295) <= \<const0>\;
  LOCKSTEP_Out(2296) <= \<const0>\;
  LOCKSTEP_Out(2297) <= \<const0>\;
  LOCKSTEP_Out(2298) <= \<const0>\;
  LOCKSTEP_Out(2299) <= \<const0>\;
  LOCKSTEP_Out(2300) <= \<const0>\;
  LOCKSTEP_Out(2301) <= \<const0>\;
  LOCKSTEP_Out(2302) <= \<const0>\;
  LOCKSTEP_Out(2303) <= \<const0>\;
  LOCKSTEP_Out(2304) <= \<const0>\;
  LOCKSTEP_Out(2305) <= \<const0>\;
  LOCKSTEP_Out(2306) <= \<const0>\;
  LOCKSTEP_Out(2307) <= \<const0>\;
  LOCKSTEP_Out(2308) <= \<const0>\;
  LOCKSTEP_Out(2309) <= \<const0>\;
  LOCKSTEP_Out(2310) <= \<const0>\;
  LOCKSTEP_Out(2311) <= \<const0>\;
  LOCKSTEP_Out(2312) <= \<const0>\;
  LOCKSTEP_Out(2313) <= \<const0>\;
  LOCKSTEP_Out(2314) <= \<const0>\;
  LOCKSTEP_Out(2315) <= \<const0>\;
  LOCKSTEP_Out(2316) <= \<const0>\;
  LOCKSTEP_Out(2317) <= \<const0>\;
  LOCKSTEP_Out(2318) <= \<const0>\;
  LOCKSTEP_Out(2319) <= \<const0>\;
  LOCKSTEP_Out(2320) <= \<const0>\;
  LOCKSTEP_Out(2321) <= \<const0>\;
  LOCKSTEP_Out(2322) <= \<const0>\;
  LOCKSTEP_Out(2323) <= \<const0>\;
  LOCKSTEP_Out(2324) <= \<const0>\;
  LOCKSTEP_Out(2325) <= \<const0>\;
  LOCKSTEP_Out(2326) <= \<const0>\;
  LOCKSTEP_Out(2327) <= \<const0>\;
  LOCKSTEP_Out(2328) <= \<const0>\;
  LOCKSTEP_Out(2329) <= \<const0>\;
  LOCKSTEP_Out(2330) <= \<const0>\;
  LOCKSTEP_Out(2331) <= \<const0>\;
  LOCKSTEP_Out(2332) <= \<const0>\;
  LOCKSTEP_Out(2333) <= \<const0>\;
  LOCKSTEP_Out(2334) <= \<const0>\;
  LOCKSTEP_Out(2335) <= \<const0>\;
  LOCKSTEP_Out(2336) <= \<const0>\;
  LOCKSTEP_Out(2337) <= \<const0>\;
  LOCKSTEP_Out(2338) <= \<const0>\;
  LOCKSTEP_Out(2339) <= \<const0>\;
  LOCKSTEP_Out(2340) <= \<const0>\;
  LOCKSTEP_Out(2341) <= \<const0>\;
  LOCKSTEP_Out(2342) <= \<const0>\;
  LOCKSTEP_Out(2343) <= \<const0>\;
  LOCKSTEP_Out(2344) <= \<const0>\;
  LOCKSTEP_Out(2345) <= \<const0>\;
  LOCKSTEP_Out(2346) <= \<const0>\;
  LOCKSTEP_Out(2347) <= \<const0>\;
  LOCKSTEP_Out(2348) <= \<const0>\;
  LOCKSTEP_Out(2349) <= \<const0>\;
  LOCKSTEP_Out(2350) <= \<const0>\;
  LOCKSTEP_Out(2351) <= \<const0>\;
  LOCKSTEP_Out(2352) <= \<const0>\;
  LOCKSTEP_Out(2353) <= \<const0>\;
  LOCKSTEP_Out(2354) <= \<const0>\;
  LOCKSTEP_Out(2355) <= \<const0>\;
  LOCKSTEP_Out(2356) <= \<const0>\;
  LOCKSTEP_Out(2357) <= \<const0>\;
  LOCKSTEP_Out(2358) <= \<const0>\;
  LOCKSTEP_Out(2359) <= \<const0>\;
  LOCKSTEP_Out(2360) <= \<const0>\;
  LOCKSTEP_Out(2361) <= \<const0>\;
  LOCKSTEP_Out(2362) <= \<const0>\;
  LOCKSTEP_Out(2363) <= \<const0>\;
  LOCKSTEP_Out(2364) <= \<const0>\;
  LOCKSTEP_Out(2365) <= \<const0>\;
  LOCKSTEP_Out(2366) <= \<const0>\;
  LOCKSTEP_Out(2367) <= \<const0>\;
  LOCKSTEP_Out(2368) <= \<const0>\;
  LOCKSTEP_Out(2369) <= \<const0>\;
  LOCKSTEP_Out(2370) <= \<const0>\;
  LOCKSTEP_Out(2371) <= \<const0>\;
  LOCKSTEP_Out(2372) <= \<const0>\;
  LOCKSTEP_Out(2373) <= \<const0>\;
  LOCKSTEP_Out(2374) <= \<const0>\;
  LOCKSTEP_Out(2375) <= \<const0>\;
  LOCKSTEP_Out(2376) <= \<const0>\;
  LOCKSTEP_Out(2377) <= \<const0>\;
  LOCKSTEP_Out(2378) <= \<const0>\;
  LOCKSTEP_Out(2379) <= \<const0>\;
  LOCKSTEP_Out(2380) <= \<const0>\;
  LOCKSTEP_Out(2381) <= \<const0>\;
  LOCKSTEP_Out(2382) <= \<const0>\;
  LOCKSTEP_Out(2383) <= \<const0>\;
  LOCKSTEP_Out(2384) <= \<const0>\;
  LOCKSTEP_Out(2385) <= \<const0>\;
  LOCKSTEP_Out(2386) <= \<const0>\;
  LOCKSTEP_Out(2387) <= \<const0>\;
  LOCKSTEP_Out(2388) <= \<const0>\;
  LOCKSTEP_Out(2389) <= \<const0>\;
  LOCKSTEP_Out(2390) <= \<const0>\;
  LOCKSTEP_Out(2391) <= \<const0>\;
  LOCKSTEP_Out(2392) <= \<const0>\;
  LOCKSTEP_Out(2393) <= \<const0>\;
  LOCKSTEP_Out(2394) <= \<const0>\;
  LOCKSTEP_Out(2395) <= \<const0>\;
  LOCKSTEP_Out(2396) <= \<const0>\;
  LOCKSTEP_Out(2397) <= \<const0>\;
  LOCKSTEP_Out(2398) <= \<const0>\;
  LOCKSTEP_Out(2399) <= \<const0>\;
  LOCKSTEP_Out(2400) <= \<const0>\;
  LOCKSTEP_Out(2401) <= \<const0>\;
  LOCKSTEP_Out(2402) <= \<const0>\;
  LOCKSTEP_Out(2403) <= \<const0>\;
  LOCKSTEP_Out(2404) <= \<const0>\;
  LOCKSTEP_Out(2405) <= \<const0>\;
  LOCKSTEP_Out(2406) <= \<const0>\;
  LOCKSTEP_Out(2407) <= \<const0>\;
  LOCKSTEP_Out(2408) <= \<const0>\;
  LOCKSTEP_Out(2409) <= \<const0>\;
  LOCKSTEP_Out(2410) <= \<const0>\;
  LOCKSTEP_Out(2411) <= \<const0>\;
  LOCKSTEP_Out(2412) <= \<const0>\;
  LOCKSTEP_Out(2413) <= \<const0>\;
  LOCKSTEP_Out(2414) <= \<const0>\;
  LOCKSTEP_Out(2415) <= \<const0>\;
  LOCKSTEP_Out(2416) <= \<const0>\;
  LOCKSTEP_Out(2417) <= \<const0>\;
  LOCKSTEP_Out(2418) <= \<const0>\;
  LOCKSTEP_Out(2419) <= \<const0>\;
  LOCKSTEP_Out(2420) <= \<const0>\;
  LOCKSTEP_Out(2421) <= \<const0>\;
  LOCKSTEP_Out(2422) <= \<const0>\;
  LOCKSTEP_Out(2423) <= \<const0>\;
  LOCKSTEP_Out(2424) <= \<const0>\;
  LOCKSTEP_Out(2425) <= \<const0>\;
  LOCKSTEP_Out(2426) <= \<const0>\;
  LOCKSTEP_Out(2427) <= \<const0>\;
  LOCKSTEP_Out(2428) <= \<const0>\;
  LOCKSTEP_Out(2429) <= \<const0>\;
  LOCKSTEP_Out(2430) <= \<const0>\;
  LOCKSTEP_Out(2431) <= \<const0>\;
  LOCKSTEP_Out(2432) <= \<const0>\;
  LOCKSTEP_Out(2433) <= \<const0>\;
  LOCKSTEP_Out(2434) <= \<const0>\;
  LOCKSTEP_Out(2435) <= \<const0>\;
  LOCKSTEP_Out(2436) <= \<const0>\;
  LOCKSTEP_Out(2437) <= \<const0>\;
  LOCKSTEP_Out(2438) <= \<const0>\;
  LOCKSTEP_Out(2439) <= \<const0>\;
  LOCKSTEP_Out(2440) <= \<const0>\;
  LOCKSTEP_Out(2441) <= \<const0>\;
  LOCKSTEP_Out(2442) <= \<const0>\;
  LOCKSTEP_Out(2443) <= \<const0>\;
  LOCKSTEP_Out(2444) <= \<const0>\;
  LOCKSTEP_Out(2445) <= \<const0>\;
  LOCKSTEP_Out(2446) <= \<const0>\;
  LOCKSTEP_Out(2447) <= \<const0>\;
  LOCKSTEP_Out(2448) <= \<const0>\;
  LOCKSTEP_Out(2449) <= \<const0>\;
  LOCKSTEP_Out(2450) <= \<const0>\;
  LOCKSTEP_Out(2451) <= \<const0>\;
  LOCKSTEP_Out(2452) <= \<const0>\;
  LOCKSTEP_Out(2453) <= \<const0>\;
  LOCKSTEP_Out(2454) <= \<const0>\;
  LOCKSTEP_Out(2455) <= \<const0>\;
  LOCKSTEP_Out(2456) <= \<const0>\;
  LOCKSTEP_Out(2457) <= \<const0>\;
  LOCKSTEP_Out(2458) <= \<const0>\;
  LOCKSTEP_Out(2459) <= \<const0>\;
  LOCKSTEP_Out(2460) <= \<const0>\;
  LOCKSTEP_Out(2461) <= \<const0>\;
  LOCKSTEP_Out(2462) <= \<const0>\;
  LOCKSTEP_Out(2463) <= \<const0>\;
  LOCKSTEP_Out(2464) <= \<const0>\;
  LOCKSTEP_Out(2465) <= \<const0>\;
  LOCKSTEP_Out(2466) <= \<const0>\;
  LOCKSTEP_Out(2467) <= \<const0>\;
  LOCKSTEP_Out(2468) <= \<const0>\;
  LOCKSTEP_Out(2469) <= \<const0>\;
  LOCKSTEP_Out(2470) <= \<const0>\;
  LOCKSTEP_Out(2471) <= \<const0>\;
  LOCKSTEP_Out(2472) <= \<const0>\;
  LOCKSTEP_Out(2473) <= \<const0>\;
  LOCKSTEP_Out(2474) <= \<const0>\;
  LOCKSTEP_Out(2475) <= \<const0>\;
  LOCKSTEP_Out(2476) <= \<const0>\;
  LOCKSTEP_Out(2477) <= \<const0>\;
  LOCKSTEP_Out(2478) <= \<const0>\;
  LOCKSTEP_Out(2479) <= \<const0>\;
  LOCKSTEP_Out(2480) <= \<const0>\;
  LOCKSTEP_Out(2481) <= \<const0>\;
  LOCKSTEP_Out(2482) <= \<const0>\;
  LOCKSTEP_Out(2483) <= \<const0>\;
  LOCKSTEP_Out(2484) <= \<const0>\;
  LOCKSTEP_Out(2485) <= \<const0>\;
  LOCKSTEP_Out(2486) <= \<const0>\;
  LOCKSTEP_Out(2487) <= \<const0>\;
  LOCKSTEP_Out(2488) <= \<const0>\;
  LOCKSTEP_Out(2489) <= \<const0>\;
  LOCKSTEP_Out(2490) <= \<const0>\;
  LOCKSTEP_Out(2491) <= \<const0>\;
  LOCKSTEP_Out(2492) <= \<const0>\;
  LOCKSTEP_Out(2493) <= \<const0>\;
  LOCKSTEP_Out(2494) <= \<const0>\;
  LOCKSTEP_Out(2495) <= \<const0>\;
  LOCKSTEP_Out(2496) <= \<const0>\;
  LOCKSTEP_Out(2497) <= \<const0>\;
  LOCKSTEP_Out(2498) <= \<const0>\;
  LOCKSTEP_Out(2499) <= \<const0>\;
  LOCKSTEP_Out(2500) <= \<const0>\;
  LOCKSTEP_Out(2501) <= \<const0>\;
  LOCKSTEP_Out(2502) <= \<const0>\;
  LOCKSTEP_Out(2503) <= \<const0>\;
  LOCKSTEP_Out(2504) <= \<const0>\;
  LOCKSTEP_Out(2505) <= \<const0>\;
  LOCKSTEP_Out(2506) <= \<const0>\;
  LOCKSTEP_Out(2507) <= \<const0>\;
  LOCKSTEP_Out(2508) <= \<const0>\;
  LOCKSTEP_Out(2509) <= \<const0>\;
  LOCKSTEP_Out(2510) <= \<const0>\;
  LOCKSTEP_Out(2511) <= \<const0>\;
  LOCKSTEP_Out(2512) <= \<const0>\;
  LOCKSTEP_Out(2513) <= \<const0>\;
  LOCKSTEP_Out(2514) <= \<const0>\;
  LOCKSTEP_Out(2515) <= \<const0>\;
  LOCKSTEP_Out(2516) <= \<const0>\;
  LOCKSTEP_Out(2517) <= \<const0>\;
  LOCKSTEP_Out(2518) <= \<const0>\;
  LOCKSTEP_Out(2519) <= \<const0>\;
  LOCKSTEP_Out(2520) <= \<const0>\;
  LOCKSTEP_Out(2521) <= \<const0>\;
  LOCKSTEP_Out(2522) <= \<const0>\;
  LOCKSTEP_Out(2523) <= \<const0>\;
  LOCKSTEP_Out(2524) <= \<const0>\;
  LOCKSTEP_Out(2525) <= \<const0>\;
  LOCKSTEP_Out(2526) <= \<const0>\;
  LOCKSTEP_Out(2527) <= \<const0>\;
  LOCKSTEP_Out(2528) <= \<const0>\;
  LOCKSTEP_Out(2529) <= \<const0>\;
  LOCKSTEP_Out(2530) <= \<const0>\;
  LOCKSTEP_Out(2531) <= \<const0>\;
  LOCKSTEP_Out(2532) <= \<const0>\;
  LOCKSTEP_Out(2533) <= \<const0>\;
  LOCKSTEP_Out(2534) <= \<const0>\;
  LOCKSTEP_Out(2535) <= \<const0>\;
  LOCKSTEP_Out(2536) <= \<const0>\;
  LOCKSTEP_Out(2537) <= \<const0>\;
  LOCKSTEP_Out(2538) <= \<const0>\;
  LOCKSTEP_Out(2539) <= \<const0>\;
  LOCKSTEP_Out(2540) <= \<const0>\;
  LOCKSTEP_Out(2541) <= \<const0>\;
  LOCKSTEP_Out(2542) <= \<const0>\;
  LOCKSTEP_Out(2543) <= \<const0>\;
  LOCKSTEP_Out(2544) <= \<const0>\;
  LOCKSTEP_Out(2545) <= \<const0>\;
  LOCKSTEP_Out(2546) <= \<const0>\;
  LOCKSTEP_Out(2547) <= \<const0>\;
  LOCKSTEP_Out(2548) <= \<const0>\;
  LOCKSTEP_Out(2549) <= \<const0>\;
  LOCKSTEP_Out(2550) <= \<const0>\;
  LOCKSTEP_Out(2551) <= \<const0>\;
  LOCKSTEP_Out(2552) <= \<const0>\;
  LOCKSTEP_Out(2553) <= \<const0>\;
  LOCKSTEP_Out(2554) <= \<const0>\;
  LOCKSTEP_Out(2555) <= \<const0>\;
  LOCKSTEP_Out(2556) <= \<const0>\;
  LOCKSTEP_Out(2557) <= \<const0>\;
  LOCKSTEP_Out(2558) <= \<const0>\;
  LOCKSTEP_Out(2559) <= \<const0>\;
  LOCKSTEP_Out(2560) <= \<const0>\;
  LOCKSTEP_Out(2561) <= \<const0>\;
  LOCKSTEP_Out(2562) <= \<const0>\;
  LOCKSTEP_Out(2563) <= \<const0>\;
  LOCKSTEP_Out(2564) <= \<const0>\;
  LOCKSTEP_Out(2565) <= \<const0>\;
  LOCKSTEP_Out(2566) <= \<const0>\;
  LOCKSTEP_Out(2567) <= \<const0>\;
  LOCKSTEP_Out(2568) <= \<const0>\;
  LOCKSTEP_Out(2569) <= \<const0>\;
  LOCKSTEP_Out(2570) <= \<const0>\;
  LOCKSTEP_Out(2571) <= \<const0>\;
  LOCKSTEP_Out(2572) <= \<const0>\;
  LOCKSTEP_Out(2573) <= \<const0>\;
  LOCKSTEP_Out(2574) <= \<const0>\;
  LOCKSTEP_Out(2575) <= \<const0>\;
  LOCKSTEP_Out(2576) <= \<const0>\;
  LOCKSTEP_Out(2577) <= \<const0>\;
  LOCKSTEP_Out(2578) <= \<const0>\;
  LOCKSTEP_Out(2579) <= \<const0>\;
  LOCKSTEP_Out(2580) <= \<const0>\;
  LOCKSTEP_Out(2581) <= \<const0>\;
  LOCKSTEP_Out(2582) <= \<const0>\;
  LOCKSTEP_Out(2583) <= \<const0>\;
  LOCKSTEP_Out(2584) <= \<const0>\;
  LOCKSTEP_Out(2585) <= \<const0>\;
  LOCKSTEP_Out(2586) <= \<const0>\;
  LOCKSTEP_Out(2587) <= \<const0>\;
  LOCKSTEP_Out(2588) <= \<const0>\;
  LOCKSTEP_Out(2589) <= \<const0>\;
  LOCKSTEP_Out(2590) <= \<const0>\;
  LOCKSTEP_Out(2591) <= \<const0>\;
  LOCKSTEP_Out(2592) <= \<const0>\;
  LOCKSTEP_Out(2593) <= \<const0>\;
  LOCKSTEP_Out(2594) <= \<const0>\;
  LOCKSTEP_Out(2595) <= \<const0>\;
  LOCKSTEP_Out(2596) <= \<const0>\;
  LOCKSTEP_Out(2597) <= \<const0>\;
  LOCKSTEP_Out(2598) <= \<const0>\;
  LOCKSTEP_Out(2599) <= \<const0>\;
  LOCKSTEP_Out(2600) <= \<const0>\;
  LOCKSTEP_Out(2601) <= \<const0>\;
  LOCKSTEP_Out(2602) <= \<const0>\;
  LOCKSTEP_Out(2603) <= \<const0>\;
  LOCKSTEP_Out(2604) <= \<const0>\;
  LOCKSTEP_Out(2605) <= \<const0>\;
  LOCKSTEP_Out(2606) <= \<const0>\;
  LOCKSTEP_Out(2607) <= \<const0>\;
  LOCKSTEP_Out(2608) <= \<const0>\;
  LOCKSTEP_Out(2609) <= \<const0>\;
  LOCKSTEP_Out(2610) <= \<const0>\;
  LOCKSTEP_Out(2611) <= \<const0>\;
  LOCKSTEP_Out(2612) <= \<const0>\;
  LOCKSTEP_Out(2613) <= \<const0>\;
  LOCKSTEP_Out(2614) <= \<const0>\;
  LOCKSTEP_Out(2615) <= \<const0>\;
  LOCKSTEP_Out(2616) <= \<const0>\;
  LOCKSTEP_Out(2617) <= \<const0>\;
  LOCKSTEP_Out(2618) <= \<const0>\;
  LOCKSTEP_Out(2619) <= \<const0>\;
  LOCKSTEP_Out(2620) <= \<const0>\;
  LOCKSTEP_Out(2621) <= \<const0>\;
  LOCKSTEP_Out(2622) <= \<const0>\;
  LOCKSTEP_Out(2623) <= \<const0>\;
  LOCKSTEP_Out(2624) <= \<const0>\;
  LOCKSTEP_Out(2625) <= \<const0>\;
  LOCKSTEP_Out(2626) <= \<const0>\;
  LOCKSTEP_Out(2627) <= \<const0>\;
  LOCKSTEP_Out(2628) <= \<const0>\;
  LOCKSTEP_Out(2629) <= \<const0>\;
  LOCKSTEP_Out(2630) <= \<const0>\;
  LOCKSTEP_Out(2631) <= \<const0>\;
  LOCKSTEP_Out(2632) <= \<const0>\;
  LOCKSTEP_Out(2633) <= \<const0>\;
  LOCKSTEP_Out(2634) <= \<const0>\;
  LOCKSTEP_Out(2635) <= \<const0>\;
  LOCKSTEP_Out(2636) <= \<const0>\;
  LOCKSTEP_Out(2637) <= \<const0>\;
  LOCKSTEP_Out(2638) <= \<const0>\;
  LOCKSTEP_Out(2639) <= \<const0>\;
  LOCKSTEP_Out(2640) <= \<const0>\;
  LOCKSTEP_Out(2641) <= \<const0>\;
  LOCKSTEP_Out(2642) <= \<const0>\;
  LOCKSTEP_Out(2643) <= \<const0>\;
  LOCKSTEP_Out(2644) <= \<const0>\;
  LOCKSTEP_Out(2645) <= \<const0>\;
  LOCKSTEP_Out(2646) <= \<const0>\;
  LOCKSTEP_Out(2647) <= \<const0>\;
  LOCKSTEP_Out(2648) <= \<const0>\;
  LOCKSTEP_Out(2649) <= \<const0>\;
  LOCKSTEP_Out(2650) <= \<const0>\;
  LOCKSTEP_Out(2651) <= \<const0>\;
  LOCKSTEP_Out(2652) <= \<const0>\;
  LOCKSTEP_Out(2653) <= \<const0>\;
  LOCKSTEP_Out(2654) <= \<const0>\;
  LOCKSTEP_Out(2655) <= \<const0>\;
  LOCKSTEP_Out(2656) <= \<const0>\;
  LOCKSTEP_Out(2657) <= \<const0>\;
  LOCKSTEP_Out(2658) <= \<const0>\;
  LOCKSTEP_Out(2659) <= \<const0>\;
  LOCKSTEP_Out(2660) <= \<const0>\;
  LOCKSTEP_Out(2661) <= \<const0>\;
  LOCKSTEP_Out(2662) <= \<const0>\;
  LOCKSTEP_Out(2663) <= \<const0>\;
  LOCKSTEP_Out(2664) <= \<const0>\;
  LOCKSTEP_Out(2665) <= \<const0>\;
  LOCKSTEP_Out(2666) <= \<const0>\;
  LOCKSTEP_Out(2667) <= \<const0>\;
  LOCKSTEP_Out(2668) <= \<const0>\;
  LOCKSTEP_Out(2669) <= \<const0>\;
  LOCKSTEP_Out(2670) <= \<const0>\;
  LOCKSTEP_Out(2671) <= \<const0>\;
  LOCKSTEP_Out(2672) <= \<const0>\;
  LOCKSTEP_Out(2673) <= \<const0>\;
  LOCKSTEP_Out(2674) <= \<const0>\;
  LOCKSTEP_Out(2675) <= \<const0>\;
  LOCKSTEP_Out(2676) <= \<const0>\;
  LOCKSTEP_Out(2677) <= \<const0>\;
  LOCKSTEP_Out(2678) <= \<const0>\;
  LOCKSTEP_Out(2679) <= \<const0>\;
  LOCKSTEP_Out(2680) <= \<const0>\;
  LOCKSTEP_Out(2681) <= \<const0>\;
  LOCKSTEP_Out(2682) <= \<const0>\;
  LOCKSTEP_Out(2683) <= \<const0>\;
  LOCKSTEP_Out(2684) <= \<const0>\;
  LOCKSTEP_Out(2685) <= \<const0>\;
  LOCKSTEP_Out(2686) <= \<const0>\;
  LOCKSTEP_Out(2687) <= \<const0>\;
  LOCKSTEP_Out(2688) <= \<const0>\;
  LOCKSTEP_Out(2689) <= \<const0>\;
  LOCKSTEP_Out(2690) <= \<const0>\;
  LOCKSTEP_Out(2691) <= \<const0>\;
  LOCKSTEP_Out(2692) <= \<const0>\;
  LOCKSTEP_Out(2693) <= \<const0>\;
  LOCKSTEP_Out(2694) <= \<const0>\;
  LOCKSTEP_Out(2695) <= \<const0>\;
  LOCKSTEP_Out(2696) <= \<const0>\;
  LOCKSTEP_Out(2697) <= \<const0>\;
  LOCKSTEP_Out(2698) <= \<const0>\;
  LOCKSTEP_Out(2699) <= \<const0>\;
  LOCKSTEP_Out(2700) <= \<const0>\;
  LOCKSTEP_Out(2701) <= \<const0>\;
  LOCKSTEP_Out(2702) <= \<const0>\;
  LOCKSTEP_Out(2703) <= \<const0>\;
  LOCKSTEP_Out(2704) <= \<const0>\;
  LOCKSTEP_Out(2705) <= \<const0>\;
  LOCKSTEP_Out(2706) <= \<const0>\;
  LOCKSTEP_Out(2707) <= \<const0>\;
  LOCKSTEP_Out(2708) <= \<const0>\;
  LOCKSTEP_Out(2709) <= \<const0>\;
  LOCKSTEP_Out(2710) <= \<const0>\;
  LOCKSTEP_Out(2711) <= \<const0>\;
  LOCKSTEP_Out(2712) <= \<const0>\;
  LOCKSTEP_Out(2713) <= \<const0>\;
  LOCKSTEP_Out(2714) <= \<const0>\;
  LOCKSTEP_Out(2715) <= \<const0>\;
  LOCKSTEP_Out(2716) <= \<const0>\;
  LOCKSTEP_Out(2717) <= \<const0>\;
  LOCKSTEP_Out(2718) <= \<const0>\;
  LOCKSTEP_Out(2719) <= \<const0>\;
  LOCKSTEP_Out(2720) <= \<const0>\;
  LOCKSTEP_Out(2721) <= \<const0>\;
  LOCKSTEP_Out(2722) <= \<const0>\;
  LOCKSTEP_Out(2723) <= \<const0>\;
  LOCKSTEP_Out(2724) <= \<const0>\;
  LOCKSTEP_Out(2725) <= \<const0>\;
  LOCKSTEP_Out(2726) <= \<const0>\;
  LOCKSTEP_Out(2727) <= \<const0>\;
  LOCKSTEP_Out(2728) <= \<const0>\;
  LOCKSTEP_Out(2729) <= \<const0>\;
  LOCKSTEP_Out(2730) <= \<const0>\;
  LOCKSTEP_Out(2731) <= \<const0>\;
  LOCKSTEP_Out(2732) <= \<const0>\;
  LOCKSTEP_Out(2733) <= \<const0>\;
  LOCKSTEP_Out(2734) <= \<const0>\;
  LOCKSTEP_Out(2735) <= \<const0>\;
  LOCKSTEP_Out(2736) <= \<const0>\;
  LOCKSTEP_Out(2737) <= \<const0>\;
  LOCKSTEP_Out(2738) <= \<const0>\;
  LOCKSTEP_Out(2739) <= \<const0>\;
  LOCKSTEP_Out(2740) <= \<const0>\;
  LOCKSTEP_Out(2741) <= \<const0>\;
  LOCKSTEP_Out(2742) <= \<const0>\;
  LOCKSTEP_Out(2743) <= \<const0>\;
  LOCKSTEP_Out(2744) <= \<const0>\;
  LOCKSTEP_Out(2745) <= \<const0>\;
  LOCKSTEP_Out(2746) <= \<const0>\;
  LOCKSTEP_Out(2747) <= \<const0>\;
  LOCKSTEP_Out(2748) <= \<const0>\;
  LOCKSTEP_Out(2749) <= \<const0>\;
  LOCKSTEP_Out(2750) <= \<const0>\;
  LOCKSTEP_Out(2751) <= \<const0>\;
  LOCKSTEP_Out(2752) <= \<const0>\;
  LOCKSTEP_Out(2753) <= \<const0>\;
  LOCKSTEP_Out(2754) <= \<const0>\;
  LOCKSTEP_Out(2755) <= \<const0>\;
  LOCKSTEP_Out(2756) <= \<const0>\;
  LOCKSTEP_Out(2757) <= \<const0>\;
  LOCKSTEP_Out(2758) <= \<const0>\;
  LOCKSTEP_Out(2759) <= \<const0>\;
  LOCKSTEP_Out(2760) <= \<const0>\;
  LOCKSTEP_Out(2761) <= \<const0>\;
  LOCKSTEP_Out(2762) <= \<const0>\;
  LOCKSTEP_Out(2763) <= \<const0>\;
  LOCKSTEP_Out(2764) <= \<const0>\;
  LOCKSTEP_Out(2765) <= \<const0>\;
  LOCKSTEP_Out(2766) <= \<const0>\;
  LOCKSTEP_Out(2767) <= \<const0>\;
  LOCKSTEP_Out(2768) <= \<const0>\;
  LOCKSTEP_Out(2769) <= \<const0>\;
  LOCKSTEP_Out(2770) <= \<const0>\;
  LOCKSTEP_Out(2771) <= \<const0>\;
  LOCKSTEP_Out(2772) <= \<const0>\;
  LOCKSTEP_Out(2773) <= \<const0>\;
  LOCKSTEP_Out(2774) <= \<const0>\;
  LOCKSTEP_Out(2775) <= \<const0>\;
  LOCKSTEP_Out(2776) <= \<const0>\;
  LOCKSTEP_Out(2777) <= \<const0>\;
  LOCKSTEP_Out(2778) <= \<const0>\;
  LOCKSTEP_Out(2779) <= \<const0>\;
  LOCKSTEP_Out(2780) <= \<const0>\;
  LOCKSTEP_Out(2781) <= \<const0>\;
  LOCKSTEP_Out(2782) <= \<const0>\;
  LOCKSTEP_Out(2783) <= \<const0>\;
  LOCKSTEP_Out(2784) <= \<const0>\;
  LOCKSTEP_Out(2785) <= \<const0>\;
  LOCKSTEP_Out(2786) <= \<const0>\;
  LOCKSTEP_Out(2787) <= \<const0>\;
  LOCKSTEP_Out(2788) <= \<const0>\;
  LOCKSTEP_Out(2789) <= \<const0>\;
  LOCKSTEP_Out(2790) <= \<const0>\;
  LOCKSTEP_Out(2791) <= \<const0>\;
  LOCKSTEP_Out(2792) <= \<const0>\;
  LOCKSTEP_Out(2793) <= \<const0>\;
  LOCKSTEP_Out(2794) <= \<const0>\;
  LOCKSTEP_Out(2795) <= \<const0>\;
  LOCKSTEP_Out(2796) <= \<const0>\;
  LOCKSTEP_Out(2797) <= \<const0>\;
  LOCKSTEP_Out(2798) <= \<const0>\;
  LOCKSTEP_Out(2799) <= \<const0>\;
  LOCKSTEP_Out(2800) <= \<const0>\;
  LOCKSTEP_Out(2801) <= \<const0>\;
  LOCKSTEP_Out(2802) <= \<const0>\;
  LOCKSTEP_Out(2803) <= \<const0>\;
  LOCKSTEP_Out(2804) <= \<const0>\;
  LOCKSTEP_Out(2805) <= \<const0>\;
  LOCKSTEP_Out(2806) <= \<const0>\;
  LOCKSTEP_Out(2807) <= \<const0>\;
  LOCKSTEP_Out(2808) <= \<const0>\;
  LOCKSTEP_Out(2809) <= \<const0>\;
  LOCKSTEP_Out(2810) <= \<const0>\;
  LOCKSTEP_Out(2811) <= \<const0>\;
  LOCKSTEP_Out(2812) <= \<const0>\;
  LOCKSTEP_Out(2813) <= \<const0>\;
  LOCKSTEP_Out(2814) <= \<const0>\;
  LOCKSTEP_Out(2815) <= \<const0>\;
  LOCKSTEP_Out(2816) <= \<const0>\;
  LOCKSTEP_Out(2817) <= \<const0>\;
  LOCKSTEP_Out(2818) <= \<const0>\;
  LOCKSTEP_Out(2819) <= \<const0>\;
  LOCKSTEP_Out(2820) <= \<const0>\;
  LOCKSTEP_Out(2821) <= \<const0>\;
  LOCKSTEP_Out(2822) <= \<const0>\;
  LOCKSTEP_Out(2823) <= \<const0>\;
  LOCKSTEP_Out(2824) <= \<const0>\;
  LOCKSTEP_Out(2825) <= \<const0>\;
  LOCKSTEP_Out(2826) <= \<const0>\;
  LOCKSTEP_Out(2827) <= \<const0>\;
  LOCKSTEP_Out(2828) <= \<const0>\;
  LOCKSTEP_Out(2829) <= \<const0>\;
  LOCKSTEP_Out(2830) <= \<const0>\;
  LOCKSTEP_Out(2831) <= \<const0>\;
  LOCKSTEP_Out(2832) <= \<const0>\;
  LOCKSTEP_Out(2833) <= \<const0>\;
  LOCKSTEP_Out(2834) <= \<const0>\;
  LOCKSTEP_Out(2835) <= \<const0>\;
  LOCKSTEP_Out(2836) <= \<const0>\;
  LOCKSTEP_Out(2837) <= \<const0>\;
  LOCKSTEP_Out(2838) <= \<const0>\;
  LOCKSTEP_Out(2839) <= \<const0>\;
  LOCKSTEP_Out(2840) <= \<const0>\;
  LOCKSTEP_Out(2841) <= \<const0>\;
  LOCKSTEP_Out(2842) <= \<const0>\;
  LOCKSTEP_Out(2843) <= \<const0>\;
  LOCKSTEP_Out(2844) <= \<const0>\;
  LOCKSTEP_Out(2845) <= \<const0>\;
  LOCKSTEP_Out(2846) <= \<const0>\;
  LOCKSTEP_Out(2847) <= \<const0>\;
  LOCKSTEP_Out(2848) <= \<const0>\;
  LOCKSTEP_Out(2849) <= \<const0>\;
  LOCKSTEP_Out(2850) <= \<const0>\;
  LOCKSTEP_Out(2851) <= \<const0>\;
  LOCKSTEP_Out(2852) <= \<const0>\;
  LOCKSTEP_Out(2853) <= \<const0>\;
  LOCKSTEP_Out(2854) <= \<const0>\;
  LOCKSTEP_Out(2855) <= \<const0>\;
  LOCKSTEP_Out(2856) <= \<const0>\;
  LOCKSTEP_Out(2857) <= \<const0>\;
  LOCKSTEP_Out(2858) <= \<const0>\;
  LOCKSTEP_Out(2859) <= \<const0>\;
  LOCKSTEP_Out(2860) <= \<const0>\;
  LOCKSTEP_Out(2861) <= \<const0>\;
  LOCKSTEP_Out(2862) <= \<const0>\;
  LOCKSTEP_Out(2863) <= \<const0>\;
  LOCKSTEP_Out(2864) <= \<const0>\;
  LOCKSTEP_Out(2865) <= \<const0>\;
  LOCKSTEP_Out(2866) <= \<const0>\;
  LOCKSTEP_Out(2867) <= \<const0>\;
  LOCKSTEP_Out(2868) <= \<const0>\;
  LOCKSTEP_Out(2869) <= \<const0>\;
  LOCKSTEP_Out(2870) <= \<const0>\;
  LOCKSTEP_Out(2871) <= \<const0>\;
  LOCKSTEP_Out(2872) <= \<const0>\;
  LOCKSTEP_Out(2873) <= \<const0>\;
  LOCKSTEP_Out(2874) <= \<const0>\;
  LOCKSTEP_Out(2875) <= \<const0>\;
  LOCKSTEP_Out(2876) <= \<const0>\;
  LOCKSTEP_Out(2877) <= \<const0>\;
  LOCKSTEP_Out(2878) <= \<const0>\;
  LOCKSTEP_Out(2879) <= \<const0>\;
  LOCKSTEP_Out(2880) <= \<const0>\;
  LOCKSTEP_Out(2881 to 2945) <= \^lockstep_out\(2881 to 2945);
  LOCKSTEP_Out(2946) <= \<const0>\;
  LOCKSTEP_Out(2947) <= \<const0>\;
  LOCKSTEP_Out(2948) <= \<const0>\;
  LOCKSTEP_Out(2949) <= \<const0>\;
  LOCKSTEP_Out(2950) <= \<const0>\;
  LOCKSTEP_Out(2951) <= \<const0>\;
  LOCKSTEP_Out(2952) <= \<const0>\;
  LOCKSTEP_Out(2953) <= \<const0>\;
  LOCKSTEP_Out(2954) <= \<const0>\;
  LOCKSTEP_Out(2955) <= \<const0>\;
  LOCKSTEP_Out(2956) <= \<const0>\;
  LOCKSTEP_Out(2957) <= \<const0>\;
  LOCKSTEP_Out(2958) <= \<const0>\;
  LOCKSTEP_Out(2959) <= \<const0>\;
  LOCKSTEP_Out(2960) <= \<const0>\;
  LOCKSTEP_Out(2961) <= \<const0>\;
  LOCKSTEP_Out(2962) <= \<const0>\;
  LOCKSTEP_Out(2963) <= \<const0>\;
  LOCKSTEP_Out(2964) <= \<const0>\;
  LOCKSTEP_Out(2965) <= \<const0>\;
  LOCKSTEP_Out(2966) <= \<const0>\;
  LOCKSTEP_Out(2967) <= \<const0>\;
  LOCKSTEP_Out(2968) <= \<const0>\;
  LOCKSTEP_Out(2969) <= \<const0>\;
  LOCKSTEP_Out(2970) <= \<const0>\;
  LOCKSTEP_Out(2971) <= \<const0>\;
  LOCKSTEP_Out(2972) <= \<const0>\;
  LOCKSTEP_Out(2973) <= \<const0>\;
  LOCKSTEP_Out(2974) <= \<const0>\;
  LOCKSTEP_Out(2975) <= \<const0>\;
  LOCKSTEP_Out(2976) <= \<const0>\;
  LOCKSTEP_Out(2977) <= \<const0>\;
  LOCKSTEP_Out(2978 to 2983) <= \^lockstep_out\(2978 to 2983);
  LOCKSTEP_Out(2984) <= \<const0>\;
  LOCKSTEP_Out(2985) <= \<const0>\;
  LOCKSTEP_Out(2986) <= \<const0>\;
  LOCKSTEP_Out(2987) <= \<const0>\;
  LOCKSTEP_Out(2988) <= \<const0>\;
  LOCKSTEP_Out(2989) <= \<const0>\;
  LOCKSTEP_Out(2990) <= \<const0>\;
  LOCKSTEP_Out(2991) <= \<const0>\;
  LOCKSTEP_Out(2992) <= \<const0>\;
  LOCKSTEP_Out(2993) <= \<const0>\;
  LOCKSTEP_Out(2994) <= \<const0>\;
  LOCKSTEP_Out(2995 to 2997) <= \^lockstep_out\(2995 to 2997);
  LOCKSTEP_Out(2998) <= \<const0>\;
  LOCKSTEP_Out(2999) <= \<const0>\;
  LOCKSTEP_Out(3000) <= \<const0>\;
  LOCKSTEP_Out(3001) <= \<const0>\;
  LOCKSTEP_Out(3002) <= \<const0>\;
  LOCKSTEP_Out(3003) <= \<const0>\;
  LOCKSTEP_Out(3004) <= \<const0>\;
  LOCKSTEP_Out(3005) <= \<const0>\;
  LOCKSTEP_Out(3006) <= \<const0>\;
  LOCKSTEP_Out(3007 to 3038) <= \^lockstep_out\(3007 to 3038);
  LOCKSTEP_Out(3039) <= \<const0>\;
  LOCKSTEP_Out(3040) <= \<const0>\;
  LOCKSTEP_Out(3041) <= \<const0>\;
  LOCKSTEP_Out(3042) <= \<const0>\;
  LOCKSTEP_Out(3043) <= \<const0>\;
  LOCKSTEP_Out(3044) <= \<const0>\;
  LOCKSTEP_Out(3045) <= \<const0>\;
  LOCKSTEP_Out(3046) <= \<const0>\;
  LOCKSTEP_Out(3047) <= \<const0>\;
  LOCKSTEP_Out(3048) <= \<const0>\;
  LOCKSTEP_Out(3049) <= \<const0>\;
  LOCKSTEP_Out(3050) <= \<const0>\;
  LOCKSTEP_Out(3051) <= \<const0>\;
  LOCKSTEP_Out(3052) <= \<const0>\;
  LOCKSTEP_Out(3053) <= \<const0>\;
  LOCKSTEP_Out(3054) <= \<const0>\;
  LOCKSTEP_Out(3055) <= \<const0>\;
  LOCKSTEP_Out(3056) <= \<const0>\;
  LOCKSTEP_Out(3057) <= \<const0>\;
  LOCKSTEP_Out(3058) <= \<const0>\;
  LOCKSTEP_Out(3059) <= \<const0>\;
  LOCKSTEP_Out(3060) <= \<const0>\;
  LOCKSTEP_Out(3061) <= \<const0>\;
  LOCKSTEP_Out(3062) <= \<const0>\;
  LOCKSTEP_Out(3063) <= \<const0>\;
  LOCKSTEP_Out(3064) <= \<const0>\;
  LOCKSTEP_Out(3065) <= \<const0>\;
  LOCKSTEP_Out(3066) <= \<const0>\;
  LOCKSTEP_Out(3067) <= \<const0>\;
  LOCKSTEP_Out(3068) <= \<const0>\;
  LOCKSTEP_Out(3069) <= \<const0>\;
  LOCKSTEP_Out(3070) <= \<const0>\;
  LOCKSTEP_Out(3071) <= \^lockstep_out\(3071);
  LOCKSTEP_Out(3072) <= \<const0>\;
  LOCKSTEP_Out(3073) <= \^lockstep_out\(3073);
  LOCKSTEP_Out(3074) <= \<const0>\;
  LOCKSTEP_Out(3075) <= \<const0>\;
  LOCKSTEP_Out(3076 to 3110) <= \^lockstep_out\(3076 to 3110);
  LOCKSTEP_Out(3111) <= \<const0>\;
  LOCKSTEP_Out(3112) <= \<const0>\;
  LOCKSTEP_Out(3113) <= \<const0>\;
  LOCKSTEP_Out(3114) <= \<const0>\;
  LOCKSTEP_Out(3115) <= \<const0>\;
  LOCKSTEP_Out(3116) <= \<const0>\;
  LOCKSTEP_Out(3117) <= \<const0>\;
  LOCKSTEP_Out(3118) <= \<const0>\;
  LOCKSTEP_Out(3119) <= \<const0>\;
  LOCKSTEP_Out(3120) <= \<const0>\;
  LOCKSTEP_Out(3121) <= \<const0>\;
  LOCKSTEP_Out(3122) <= \<const0>\;
  LOCKSTEP_Out(3123) <= \<const0>\;
  LOCKSTEP_Out(3124) <= \<const0>\;
  LOCKSTEP_Out(3125) <= \<const0>\;
  LOCKSTEP_Out(3126) <= \<const0>\;
  LOCKSTEP_Out(3127) <= \<const0>\;
  LOCKSTEP_Out(3128) <= \<const0>\;
  LOCKSTEP_Out(3129) <= \<const0>\;
  LOCKSTEP_Out(3130) <= \<const0>\;
  LOCKSTEP_Out(3131) <= \<const0>\;
  LOCKSTEP_Out(3132) <= \<const0>\;
  LOCKSTEP_Out(3133) <= \<const0>\;
  LOCKSTEP_Out(3134) <= \<const0>\;
  LOCKSTEP_Out(3135) <= \<const0>\;
  LOCKSTEP_Out(3136) <= \<const0>\;
  LOCKSTEP_Out(3137) <= \<const0>\;
  LOCKSTEP_Out(3138) <= \<const0>\;
  LOCKSTEP_Out(3139) <= \<const0>\;
  LOCKSTEP_Out(3140) <= \<const0>\;
  LOCKSTEP_Out(3141) <= \<const0>\;
  LOCKSTEP_Out(3142) <= \<const0>\;
  LOCKSTEP_Out(3143 to 3174) <= \^lockstep_out\(3143 to 3174);
  LOCKSTEP_Out(3175) <= \<const0>\;
  LOCKSTEP_Out(3176) <= \<const0>\;
  LOCKSTEP_Out(3177) <= \<const0>\;
  LOCKSTEP_Out(3178) <= \<const0>\;
  LOCKSTEP_Out(3179) <= \<const0>\;
  LOCKSTEP_Out(3180) <= \<const0>\;
  LOCKSTEP_Out(3181) <= \<const0>\;
  LOCKSTEP_Out(3182) <= \<const0>\;
  LOCKSTEP_Out(3183) <= \<const0>\;
  LOCKSTEP_Out(3184) <= \<const0>\;
  LOCKSTEP_Out(3185) <= \<const0>\;
  LOCKSTEP_Out(3186) <= \<const0>\;
  LOCKSTEP_Out(3187) <= \<const0>\;
  LOCKSTEP_Out(3188) <= \<const0>\;
  LOCKSTEP_Out(3189) <= \<const0>\;
  LOCKSTEP_Out(3190) <= \<const0>\;
  LOCKSTEP_Out(3191) <= \<const0>\;
  LOCKSTEP_Out(3192) <= \<const0>\;
  LOCKSTEP_Out(3193) <= \<const0>\;
  LOCKSTEP_Out(3194) <= \<const0>\;
  LOCKSTEP_Out(3195) <= \<const0>\;
  LOCKSTEP_Out(3196) <= \<const0>\;
  LOCKSTEP_Out(3197) <= \<const0>\;
  LOCKSTEP_Out(3198) <= \<const0>\;
  LOCKSTEP_Out(3199) <= \<const0>\;
  LOCKSTEP_Out(3200) <= \<const0>\;
  LOCKSTEP_Out(3201) <= \<const0>\;
  LOCKSTEP_Out(3202) <= \<const0>\;
  LOCKSTEP_Out(3203) <= \<const0>\;
  LOCKSTEP_Out(3204) <= \<const0>\;
  LOCKSTEP_Out(3205) <= \<const0>\;
  LOCKSTEP_Out(3206) <= \<const0>\;
  LOCKSTEP_Out(3207 to 3210) <= \^lockstep_out\(3207 to 3210);
  LOCKSTEP_Out(3211) <= \<const0>\;
  LOCKSTEP_Out(3212) <= \<const0>\;
  LOCKSTEP_Out(3213) <= \<const0>\;
  LOCKSTEP_Out(3214) <= \<const0>\;
  LOCKSTEP_Out(3215 to 3217) <= \^lockstep_out\(3215 to 3217);
  LOCKSTEP_Out(3218) <= \<const0>\;
  LOCKSTEP_Out(3219) <= \<const0>\;
  LOCKSTEP_Out(3220) <= \<const0>\;
  LOCKSTEP_Out(3221) <= \<const0>\;
  LOCKSTEP_Out(3222) <= \<const0>\;
  LOCKSTEP_Out(3223) <= \<const0>\;
  LOCKSTEP_Out(3224) <= \<const0>\;
  LOCKSTEP_Out(3225 to 3228) <= \^lockstep_out\(3225 to 3228);
  LOCKSTEP_Out(3229) <= \<const0>\;
  LOCKSTEP_Out(3230) <= \<const0>\;
  LOCKSTEP_Out(3231) <= \<const0>\;
  LOCKSTEP_Out(3232) <= \<const0>\;
  LOCKSTEP_Out(3233) <= \<const0>\;
  LOCKSTEP_Out(3234) <= \<const0>\;
  LOCKSTEP_Out(3235) <= \<const0>\;
  LOCKSTEP_Out(3236) <= \<const0>\;
  LOCKSTEP_Out(3237) <= \<const0>\;
  LOCKSTEP_Out(3238) <= \<const0>\;
  LOCKSTEP_Out(3239) <= \<const0>\;
  LOCKSTEP_Out(3240) <= \<const0>\;
  LOCKSTEP_Out(3241) <= \<const0>\;
  LOCKSTEP_Out(3242) <= \<const0>\;
  LOCKSTEP_Out(3243) <= \<const0>\;
  LOCKSTEP_Out(3244) <= \<const0>\;
  LOCKSTEP_Out(3245) <= \<const0>\;
  LOCKSTEP_Out(3246) <= \<const0>\;
  LOCKSTEP_Out(3247) <= \<const0>\;
  LOCKSTEP_Out(3248) <= \<const0>\;
  LOCKSTEP_Out(3249) <= \<const0>\;
  LOCKSTEP_Out(3250) <= \<const0>\;
  LOCKSTEP_Out(3251) <= \<const0>\;
  LOCKSTEP_Out(3252) <= \<const0>\;
  LOCKSTEP_Out(3253) <= \<const0>\;
  LOCKSTEP_Out(3254) <= \<const0>\;
  LOCKSTEP_Out(3255) <= \<const0>\;
  LOCKSTEP_Out(3256) <= \<const0>\;
  LOCKSTEP_Out(3257) <= \<const0>\;
  LOCKSTEP_Out(3258) <= \<const0>\;
  LOCKSTEP_Out(3259) <= \<const0>\;
  LOCKSTEP_Out(3260) <= \<const0>\;
  LOCKSTEP_Out(3261) <= \<const0>\;
  LOCKSTEP_Out(3262) <= \<const0>\;
  LOCKSTEP_Out(3263) <= \<const0>\;
  LOCKSTEP_Out(3264) <= \<const0>\;
  LOCKSTEP_Out(3265) <= \<const0>\;
  LOCKSTEP_Out(3266) <= \<const0>\;
  LOCKSTEP_Out(3267) <= \<const0>\;
  LOCKSTEP_Out(3268) <= \<const0>\;
  LOCKSTEP_Out(3269) <= \<const0>\;
  LOCKSTEP_Out(3270) <= \<const0>\;
  LOCKSTEP_Out(3271) <= \<const0>\;
  LOCKSTEP_Out(3272) <= \<const0>\;
  LOCKSTEP_Out(3273) <= \<const0>\;
  LOCKSTEP_Out(3274) <= \<const0>\;
  LOCKSTEP_Out(3275) <= \<const0>\;
  LOCKSTEP_Out(3276) <= \<const0>\;
  LOCKSTEP_Out(3277) <= \<const0>\;
  LOCKSTEP_Out(3278) <= \<const0>\;
  LOCKSTEP_Out(3279) <= \<const0>\;
  LOCKSTEP_Out(3280) <= \<const0>\;
  LOCKSTEP_Out(3281) <= \<const0>\;
  LOCKSTEP_Out(3282) <= \<const0>\;
  LOCKSTEP_Out(3283) <= \<const0>\;
  LOCKSTEP_Out(3284) <= \<const0>\;
  LOCKSTEP_Out(3285) <= \<const0>\;
  LOCKSTEP_Out(3286) <= \<const0>\;
  LOCKSTEP_Out(3287) <= \<const0>\;
  LOCKSTEP_Out(3288) <= \<const0>\;
  LOCKSTEP_Out(3289) <= \<const0>\;
  LOCKSTEP_Out(3290) <= \<const0>\;
  LOCKSTEP_Out(3291) <= \<const0>\;
  LOCKSTEP_Out(3292) <= \<const0>\;
  LOCKSTEP_Out(3293) <= \<const0>\;
  LOCKSTEP_Out(3294) <= \<const0>\;
  LOCKSTEP_Out(3295) <= \<const0>\;
  LOCKSTEP_Out(3296) <= \<const0>\;
  LOCKSTEP_Out(3297) <= \<const0>\;
  LOCKSTEP_Out(3298) <= \<const0>\;
  LOCKSTEP_Out(3299) <= \<const0>\;
  LOCKSTEP_Out(3300) <= \<const0>\;
  LOCKSTEP_Out(3301) <= \<const0>\;
  LOCKSTEP_Out(3302) <= \<const0>\;
  LOCKSTEP_Out(3303) <= \<const0>\;
  LOCKSTEP_Out(3304) <= \<const0>\;
  LOCKSTEP_Out(3305) <= \<const0>\;
  LOCKSTEP_Out(3306) <= \<const0>\;
  LOCKSTEP_Out(3307) <= \<const0>\;
  LOCKSTEP_Out(3308) <= \<const0>\;
  LOCKSTEP_Out(3309) <= \<const0>\;
  LOCKSTEP_Out(3310) <= \<const0>\;
  LOCKSTEP_Out(3311) <= \<const0>\;
  LOCKSTEP_Out(3312) <= \<const0>\;
  LOCKSTEP_Out(3313) <= \<const0>\;
  LOCKSTEP_Out(3314) <= \<const0>\;
  LOCKSTEP_Out(3315) <= \<const0>\;
  LOCKSTEP_Out(3316) <= \<const0>\;
  LOCKSTEP_Out(3317) <= \<const0>\;
  LOCKSTEP_Out(3318) <= \<const0>\;
  LOCKSTEP_Out(3319) <= \<const0>\;
  LOCKSTEP_Out(3320) <= \<const0>\;
  LOCKSTEP_Out(3321) <= \<const0>\;
  LOCKSTEP_Out(3322) <= \<const0>\;
  LOCKSTEP_Out(3323) <= \<const0>\;
  LOCKSTEP_Out(3324) <= \<const0>\;
  LOCKSTEP_Out(3325) <= \<const0>\;
  LOCKSTEP_Out(3326) <= \<const0>\;
  LOCKSTEP_Out(3327) <= \<const0>\;
  LOCKSTEP_Out(3328) <= \<const0>\;
  LOCKSTEP_Out(3329) <= \<const0>\;
  LOCKSTEP_Out(3330) <= \<const0>\;
  LOCKSTEP_Out(3331) <= \<const0>\;
  LOCKSTEP_Out(3332) <= \<const0>\;
  LOCKSTEP_Out(3333) <= \<const0>\;
  LOCKSTEP_Out(3334) <= \<const0>\;
  LOCKSTEP_Out(3335) <= \<const0>\;
  LOCKSTEP_Out(3336) <= \<const0>\;
  LOCKSTEP_Out(3337) <= \<const0>\;
  LOCKSTEP_Out(3338) <= \<const0>\;
  LOCKSTEP_Out(3339) <= \<const0>\;
  LOCKSTEP_Out(3340) <= \<const0>\;
  LOCKSTEP_Out(3341) <= \<const0>\;
  LOCKSTEP_Out(3342) <= \<const0>\;
  LOCKSTEP_Out(3343) <= \<const0>\;
  LOCKSTEP_Out(3344) <= \<const0>\;
  LOCKSTEP_Out(3345) <= \<const0>\;
  LOCKSTEP_Out(3346) <= \<const0>\;
  LOCKSTEP_Out(3347) <= \<const0>\;
  LOCKSTEP_Out(3348) <= \<const0>\;
  LOCKSTEP_Out(3349) <= \<const0>\;
  LOCKSTEP_Out(3350) <= \<const0>\;
  LOCKSTEP_Out(3351) <= \<const0>\;
  LOCKSTEP_Out(3352) <= \<const0>\;
  LOCKSTEP_Out(3353) <= \<const0>\;
  LOCKSTEP_Out(3354) <= \<const0>\;
  LOCKSTEP_Out(3355) <= \<const0>\;
  LOCKSTEP_Out(3356) <= \<const0>\;
  LOCKSTEP_Out(3357) <= \<const0>\;
  LOCKSTEP_Out(3358) <= \<const0>\;
  LOCKSTEP_Out(3359) <= \<const0>\;
  LOCKSTEP_Out(3360) <= \<const0>\;
  LOCKSTEP_Out(3361) <= \<const0>\;
  LOCKSTEP_Out(3362) <= \<const0>\;
  LOCKSTEP_Out(3363) <= \<const0>\;
  LOCKSTEP_Out(3364) <= \<const0>\;
  LOCKSTEP_Out(3365) <= \<const0>\;
  LOCKSTEP_Out(3366) <= \<const0>\;
  LOCKSTEP_Out(3367) <= \<const0>\;
  LOCKSTEP_Out(3368) <= \<const0>\;
  LOCKSTEP_Out(3369) <= \<const0>\;
  LOCKSTEP_Out(3370) <= \<const0>\;
  LOCKSTEP_Out(3371) <= \<const0>\;
  LOCKSTEP_Out(3372) <= \<const0>\;
  LOCKSTEP_Out(3373) <= \<const0>\;
  LOCKSTEP_Out(3374) <= \<const0>\;
  LOCKSTEP_Out(3375) <= \<const0>\;
  LOCKSTEP_Out(3376) <= \<const0>\;
  LOCKSTEP_Out(3377) <= \<const0>\;
  LOCKSTEP_Out(3378) <= \<const0>\;
  LOCKSTEP_Out(3379) <= \<const0>\;
  LOCKSTEP_Out(3380) <= \<const0>\;
  LOCKSTEP_Out(3381) <= \<const0>\;
  LOCKSTEP_Out(3382) <= \<const0>\;
  LOCKSTEP_Out(3383) <= \<const0>\;
  LOCKSTEP_Out(3384) <= \<const0>\;
  LOCKSTEP_Out(3385) <= \<const0>\;
  LOCKSTEP_Out(3386) <= \<const0>\;
  LOCKSTEP_Out(3387) <= \<const0>\;
  LOCKSTEP_Out(3388) <= \<const0>\;
  LOCKSTEP_Out(3389) <= \<const0>\;
  LOCKSTEP_Out(3390) <= \<const0>\;
  LOCKSTEP_Out(3391) <= \<const0>\;
  LOCKSTEP_Out(3392) <= \<const0>\;
  LOCKSTEP_Out(3393) <= \<const0>\;
  LOCKSTEP_Out(3394) <= \<const0>\;
  LOCKSTEP_Out(3395) <= \<const0>\;
  LOCKSTEP_Out(3396) <= \<const0>\;
  LOCKSTEP_Out(3397) <= \<const0>\;
  LOCKSTEP_Out(3398) <= \<const0>\;
  LOCKSTEP_Out(3399) <= \<const0>\;
  LOCKSTEP_Out(3400) <= \<const0>\;
  LOCKSTEP_Out(3401) <= \<const0>\;
  LOCKSTEP_Out(3402) <= \<const0>\;
  LOCKSTEP_Out(3403) <= \<const0>\;
  LOCKSTEP_Out(3404) <= \<const0>\;
  LOCKSTEP_Out(3405) <= \<const0>\;
  LOCKSTEP_Out(3406) <= \<const0>\;
  LOCKSTEP_Out(3407) <= \<const0>\;
  LOCKSTEP_Out(3408) <= \<const0>\;
  LOCKSTEP_Out(3409) <= \<const0>\;
  LOCKSTEP_Out(3410) <= \<const0>\;
  LOCKSTEP_Out(3411) <= \<const0>\;
  LOCKSTEP_Out(3412) <= \<const0>\;
  LOCKSTEP_Out(3413) <= \<const0>\;
  LOCKSTEP_Out(3414) <= \<const0>\;
  LOCKSTEP_Out(3415) <= \<const0>\;
  LOCKSTEP_Out(3416) <= \<const0>\;
  LOCKSTEP_Out(3417) <= \<const0>\;
  LOCKSTEP_Out(3418) <= \<const0>\;
  LOCKSTEP_Out(3419) <= \<const0>\;
  LOCKSTEP_Out(3420) <= \<const0>\;
  LOCKSTEP_Out(3421) <= \<const0>\;
  LOCKSTEP_Out(3422) <= \<const0>\;
  LOCKSTEP_Out(3423) <= \<const0>\;
  LOCKSTEP_Out(3424) <= \<const0>\;
  LOCKSTEP_Out(3425) <= \<const0>\;
  LOCKSTEP_Out(3426) <= \<const0>\;
  LOCKSTEP_Out(3427) <= \<const0>\;
  LOCKSTEP_Out(3428) <= \<const0>\;
  LOCKSTEP_Out(3429) <= \<const0>\;
  LOCKSTEP_Out(3430) <= \<const0>\;
  LOCKSTEP_Out(3431) <= \<const0>\;
  LOCKSTEP_Out(3432) <= \<const0>\;
  LOCKSTEP_Out(3433) <= \<const0>\;
  LOCKSTEP_Out(3434) <= \<const0>\;
  LOCKSTEP_Out(3435) <= \<const0>\;
  LOCKSTEP_Out(3436) <= \<const0>\;
  LOCKSTEP_Out(3437) <= \<const0>\;
  LOCKSTEP_Out(3438) <= \<const0>\;
  LOCKSTEP_Out(3439) <= \<const0>\;
  LOCKSTEP_Out(3440) <= \<const0>\;
  LOCKSTEP_Out(3441) <= \<const0>\;
  LOCKSTEP_Out(3442) <= \<const0>\;
  LOCKSTEP_Out(3443) <= \<const0>\;
  LOCKSTEP_Out(3444) <= \<const0>\;
  LOCKSTEP_Out(3445) <= \<const0>\;
  LOCKSTEP_Out(3446) <= \<const0>\;
  LOCKSTEP_Out(3447) <= \<const0>\;
  LOCKSTEP_Out(3448) <= \<const0>\;
  LOCKSTEP_Out(3449) <= \<const0>\;
  LOCKSTEP_Out(3450) <= \<const0>\;
  LOCKSTEP_Out(3451) <= \<const0>\;
  LOCKSTEP_Out(3452) <= \<const0>\;
  LOCKSTEP_Out(3453) <= \<const0>\;
  LOCKSTEP_Out(3454) <= \<const0>\;
  LOCKSTEP_Out(3455) <= \<const0>\;
  LOCKSTEP_Out(3456) <= \<const0>\;
  LOCKSTEP_Out(3457) <= \<const0>\;
  LOCKSTEP_Out(3458) <= \<const0>\;
  LOCKSTEP_Out(3459) <= \<const0>\;
  LOCKSTEP_Out(3460) <= \<const0>\;
  LOCKSTEP_Out(3461) <= \<const0>\;
  LOCKSTEP_Out(3462) <= \<const0>\;
  LOCKSTEP_Out(3463) <= \<const0>\;
  LOCKSTEP_Out(3464) <= \<const0>\;
  LOCKSTEP_Out(3465) <= \<const0>\;
  LOCKSTEP_Out(3466) <= \<const0>\;
  LOCKSTEP_Out(3467) <= \<const0>\;
  LOCKSTEP_Out(3468) <= \<const0>\;
  LOCKSTEP_Out(3469) <= \<const0>\;
  LOCKSTEP_Out(3470) <= \<const0>\;
  LOCKSTEP_Out(3471) <= \<const0>\;
  LOCKSTEP_Out(3472) <= \<const0>\;
  LOCKSTEP_Out(3473) <= \<const0>\;
  LOCKSTEP_Out(3474) <= \<const0>\;
  LOCKSTEP_Out(3475) <= \<const0>\;
  LOCKSTEP_Out(3476) <= \<const0>\;
  LOCKSTEP_Out(3477) <= \<const0>\;
  LOCKSTEP_Out(3478) <= \<const0>\;
  LOCKSTEP_Out(3479) <= \<const0>\;
  LOCKSTEP_Out(3480) <= \<const0>\;
  LOCKSTEP_Out(3481) <= \<const0>\;
  LOCKSTEP_Out(3482) <= \<const0>\;
  LOCKSTEP_Out(3483) <= \<const0>\;
  LOCKSTEP_Out(3484) <= \<const0>\;
  LOCKSTEP_Out(3485) <= \<const0>\;
  LOCKSTEP_Out(3486) <= \<const0>\;
  LOCKSTEP_Out(3487) <= \<const0>\;
  LOCKSTEP_Out(3488) <= \<const0>\;
  LOCKSTEP_Out(3489) <= \<const0>\;
  LOCKSTEP_Out(3490) <= \<const0>\;
  LOCKSTEP_Out(3491) <= \<const0>\;
  LOCKSTEP_Out(3492) <= \<const0>\;
  LOCKSTEP_Out(3493) <= \<const0>\;
  LOCKSTEP_Out(3494) <= \<const0>\;
  LOCKSTEP_Out(3495) <= \<const0>\;
  LOCKSTEP_Out(3496) <= \<const0>\;
  LOCKSTEP_Out(3497) <= \<const0>\;
  LOCKSTEP_Out(3498) <= \<const0>\;
  LOCKSTEP_Out(3499) <= \<const0>\;
  LOCKSTEP_Out(3500) <= \<const0>\;
  LOCKSTEP_Out(3501) <= \<const0>\;
  LOCKSTEP_Out(3502) <= \<const0>\;
  LOCKSTEP_Out(3503) <= \<const0>\;
  LOCKSTEP_Out(3504) <= \<const0>\;
  LOCKSTEP_Out(3505) <= \<const0>\;
  LOCKSTEP_Out(3506) <= \<const0>\;
  LOCKSTEP_Out(3507) <= \<const0>\;
  LOCKSTEP_Out(3508) <= \<const0>\;
  LOCKSTEP_Out(3509) <= \<const0>\;
  LOCKSTEP_Out(3510) <= \<const0>\;
  LOCKSTEP_Out(3511) <= \<const0>\;
  LOCKSTEP_Out(3512) <= \<const0>\;
  LOCKSTEP_Out(3513) <= \<const0>\;
  LOCKSTEP_Out(3514) <= \<const0>\;
  LOCKSTEP_Out(3515) <= \<const0>\;
  LOCKSTEP_Out(3516) <= \<const0>\;
  LOCKSTEP_Out(3517) <= \<const0>\;
  LOCKSTEP_Out(3518) <= \<const0>\;
  LOCKSTEP_Out(3519) <= \<const0>\;
  LOCKSTEP_Out(3520) <= \<const0>\;
  LOCKSTEP_Out(3521) <= \<const0>\;
  LOCKSTEP_Out(3522) <= \<const0>\;
  LOCKSTEP_Out(3523) <= \<const0>\;
  LOCKSTEP_Out(3524) <= \<const0>\;
  LOCKSTEP_Out(3525) <= \<const0>\;
  LOCKSTEP_Out(3526) <= \<const0>\;
  LOCKSTEP_Out(3527) <= \<const0>\;
  LOCKSTEP_Out(3528) <= \<const0>\;
  LOCKSTEP_Out(3529) <= \<const0>\;
  LOCKSTEP_Out(3530) <= \<const0>\;
  LOCKSTEP_Out(3531) <= \<const0>\;
  LOCKSTEP_Out(3532) <= \<const0>\;
  LOCKSTEP_Out(3533) <= \<const0>\;
  LOCKSTEP_Out(3534) <= \<const0>\;
  LOCKSTEP_Out(3535) <= \<const0>\;
  LOCKSTEP_Out(3536) <= \<const0>\;
  LOCKSTEP_Out(3537) <= \<const0>\;
  LOCKSTEP_Out(3538) <= \<const0>\;
  LOCKSTEP_Out(3539) <= \<const0>\;
  LOCKSTEP_Out(3540) <= \<const0>\;
  LOCKSTEP_Out(3541) <= \<const0>\;
  LOCKSTEP_Out(3542) <= \<const0>\;
  LOCKSTEP_Out(3543) <= \<const0>\;
  LOCKSTEP_Out(3544) <= \<const0>\;
  LOCKSTEP_Out(3545) <= \<const0>\;
  LOCKSTEP_Out(3546) <= \<const0>\;
  LOCKSTEP_Out(3547) <= \<const0>\;
  LOCKSTEP_Out(3548) <= \<const0>\;
  LOCKSTEP_Out(3549) <= \<const0>\;
  LOCKSTEP_Out(3550) <= \<const0>\;
  LOCKSTEP_Out(3551) <= \<const0>\;
  LOCKSTEP_Out(3552) <= \<const0>\;
  LOCKSTEP_Out(3553) <= \<const0>\;
  LOCKSTEP_Out(3554) <= \<const0>\;
  LOCKSTEP_Out(3555) <= \<const0>\;
  LOCKSTEP_Out(3556) <= \<const0>\;
  LOCKSTEP_Out(3557) <= \<const0>\;
  LOCKSTEP_Out(3558) <= \<const0>\;
  LOCKSTEP_Out(3559) <= \<const0>\;
  LOCKSTEP_Out(3560) <= \<const0>\;
  LOCKSTEP_Out(3561) <= \<const0>\;
  LOCKSTEP_Out(3562) <= \<const0>\;
  LOCKSTEP_Out(3563) <= \<const0>\;
  LOCKSTEP_Out(3564) <= \<const0>\;
  LOCKSTEP_Out(3565) <= \<const0>\;
  LOCKSTEP_Out(3566) <= \<const0>\;
  LOCKSTEP_Out(3567) <= \<const0>\;
  LOCKSTEP_Out(3568) <= \<const0>\;
  LOCKSTEP_Out(3569) <= \<const0>\;
  LOCKSTEP_Out(3570) <= \<const0>\;
  LOCKSTEP_Out(3571) <= \<const0>\;
  LOCKSTEP_Out(3572) <= \<const0>\;
  LOCKSTEP_Out(3573) <= \<const0>\;
  LOCKSTEP_Out(3574) <= \<const0>\;
  LOCKSTEP_Out(3575) <= \<const0>\;
  LOCKSTEP_Out(3576) <= \<const0>\;
  LOCKSTEP_Out(3577) <= \<const0>\;
  LOCKSTEP_Out(3578) <= \<const0>\;
  LOCKSTEP_Out(3579) <= \<const0>\;
  LOCKSTEP_Out(3580) <= \<const0>\;
  LOCKSTEP_Out(3581) <= \<const0>\;
  LOCKSTEP_Out(3582) <= \<const0>\;
  LOCKSTEP_Out(3583) <= \<const0>\;
  LOCKSTEP_Out(3584) <= \<const0>\;
  LOCKSTEP_Out(3585) <= \<const0>\;
  LOCKSTEP_Out(3586) <= \<const0>\;
  LOCKSTEP_Out(3587) <= \<const0>\;
  LOCKSTEP_Out(3588) <= \<const0>\;
  LOCKSTEP_Out(3589) <= \<const0>\;
  LOCKSTEP_Out(3590) <= \<const0>\;
  LOCKSTEP_Out(3591) <= \<const0>\;
  LOCKSTEP_Out(3592) <= \<const0>\;
  LOCKSTEP_Out(3593) <= \<const0>\;
  LOCKSTEP_Out(3594) <= \<const0>\;
  LOCKSTEP_Out(3595) <= \<const0>\;
  LOCKSTEP_Out(3596) <= \<const0>\;
  LOCKSTEP_Out(3597) <= \<const0>\;
  LOCKSTEP_Out(3598) <= \<const0>\;
  LOCKSTEP_Out(3599) <= \<const0>\;
  LOCKSTEP_Out(3600) <= \<const0>\;
  LOCKSTEP_Out(3601) <= \<const0>\;
  LOCKSTEP_Out(3602) <= \<const0>\;
  LOCKSTEP_Out(3603) <= \<const0>\;
  LOCKSTEP_Out(3604) <= \<const0>\;
  LOCKSTEP_Out(3605) <= \<const0>\;
  LOCKSTEP_Out(3606) <= \<const0>\;
  LOCKSTEP_Out(3607) <= \<const0>\;
  LOCKSTEP_Out(3608) <= \<const0>\;
  LOCKSTEP_Out(3609) <= \<const0>\;
  LOCKSTEP_Out(3610) <= \<const0>\;
  LOCKSTEP_Out(3611) <= \<const0>\;
  LOCKSTEP_Out(3612) <= \<const0>\;
  LOCKSTEP_Out(3613) <= \<const0>\;
  LOCKSTEP_Out(3614) <= \<const0>\;
  LOCKSTEP_Out(3615) <= \<const0>\;
  LOCKSTEP_Out(3616) <= \<const0>\;
  LOCKSTEP_Out(3617) <= \<const0>\;
  LOCKSTEP_Out(3618) <= \<const0>\;
  LOCKSTEP_Out(3619) <= \<const0>\;
  LOCKSTEP_Out(3620) <= \<const0>\;
  LOCKSTEP_Out(3621) <= \<const0>\;
  LOCKSTEP_Out(3622) <= \<const0>\;
  LOCKSTEP_Out(3623) <= \<const0>\;
  LOCKSTEP_Out(3624) <= \<const0>\;
  LOCKSTEP_Out(3625) <= \<const0>\;
  LOCKSTEP_Out(3626) <= \<const0>\;
  LOCKSTEP_Out(3627) <= \<const0>\;
  LOCKSTEP_Out(3628) <= \<const0>\;
  LOCKSTEP_Out(3629) <= \<const0>\;
  LOCKSTEP_Out(3630) <= \<const0>\;
  LOCKSTEP_Out(3631) <= \<const0>\;
  LOCKSTEP_Out(3632) <= \<const0>\;
  LOCKSTEP_Out(3633) <= \<const0>\;
  LOCKSTEP_Out(3634) <= \<const0>\;
  LOCKSTEP_Out(3635) <= \<const0>\;
  LOCKSTEP_Out(3636) <= \<const0>\;
  LOCKSTEP_Out(3637) <= \<const0>\;
  LOCKSTEP_Out(3638) <= \<const0>\;
  LOCKSTEP_Out(3639) <= \<const0>\;
  LOCKSTEP_Out(3640) <= \<const0>\;
  LOCKSTEP_Out(3641) <= \<const0>\;
  LOCKSTEP_Out(3642) <= \<const0>\;
  LOCKSTEP_Out(3643) <= \<const0>\;
  LOCKSTEP_Out(3644) <= \<const0>\;
  LOCKSTEP_Out(3645) <= \<const0>\;
  LOCKSTEP_Out(3646) <= \<const0>\;
  LOCKSTEP_Out(3647) <= \<const0>\;
  LOCKSTEP_Out(3648) <= \<const0>\;
  LOCKSTEP_Out(3649) <= \<const0>\;
  LOCKSTEP_Out(3650) <= \<const0>\;
  LOCKSTEP_Out(3651) <= \<const0>\;
  LOCKSTEP_Out(3652) <= \<const0>\;
  LOCKSTEP_Out(3653) <= \<const0>\;
  LOCKSTEP_Out(3654) <= \<const0>\;
  LOCKSTEP_Out(3655) <= \<const0>\;
  LOCKSTEP_Out(3656) <= \<const0>\;
  LOCKSTEP_Out(3657) <= \<const0>\;
  LOCKSTEP_Out(3658) <= \<const0>\;
  LOCKSTEP_Out(3659) <= \<const0>\;
  LOCKSTEP_Out(3660) <= \<const0>\;
  LOCKSTEP_Out(3661) <= \<const0>\;
  LOCKSTEP_Out(3662) <= \<const0>\;
  LOCKSTEP_Out(3663) <= \<const0>\;
  LOCKSTEP_Out(3664) <= \<const0>\;
  LOCKSTEP_Out(3665) <= \<const0>\;
  LOCKSTEP_Out(3666) <= \<const0>\;
  LOCKSTEP_Out(3667) <= \<const0>\;
  LOCKSTEP_Out(3668) <= \<const0>\;
  LOCKSTEP_Out(3669) <= \<const0>\;
  LOCKSTEP_Out(3670) <= \<const0>\;
  LOCKSTEP_Out(3671) <= \<const0>\;
  LOCKSTEP_Out(3672) <= \<const0>\;
  LOCKSTEP_Out(3673) <= \<const0>\;
  LOCKSTEP_Out(3674) <= \<const0>\;
  LOCKSTEP_Out(3675) <= \<const0>\;
  LOCKSTEP_Out(3676) <= \<const0>\;
  LOCKSTEP_Out(3677) <= \<const0>\;
  LOCKSTEP_Out(3678) <= \<const0>\;
  LOCKSTEP_Out(3679) <= \<const0>\;
  LOCKSTEP_Out(3680) <= \<const0>\;
  LOCKSTEP_Out(3681) <= \<const0>\;
  LOCKSTEP_Out(3682) <= \<const0>\;
  LOCKSTEP_Out(3683) <= \<const0>\;
  LOCKSTEP_Out(3684) <= \<const0>\;
  LOCKSTEP_Out(3685) <= \<const0>\;
  LOCKSTEP_Out(3686) <= \<const0>\;
  LOCKSTEP_Out(3687) <= \<const0>\;
  LOCKSTEP_Out(3688) <= \<const0>\;
  LOCKSTEP_Out(3689) <= \<const0>\;
  LOCKSTEP_Out(3690) <= \<const0>\;
  LOCKSTEP_Out(3691) <= \<const0>\;
  LOCKSTEP_Out(3692) <= \<const0>\;
  LOCKSTEP_Out(3693) <= \<const0>\;
  LOCKSTEP_Out(3694) <= \<const0>\;
  LOCKSTEP_Out(3695) <= \<const0>\;
  LOCKSTEP_Out(3696) <= \<const0>\;
  LOCKSTEP_Out(3697) <= \<const0>\;
  LOCKSTEP_Out(3698) <= \<const0>\;
  LOCKSTEP_Out(3699) <= \<const0>\;
  LOCKSTEP_Out(3700) <= \<const0>\;
  LOCKSTEP_Out(3701) <= \<const0>\;
  LOCKSTEP_Out(3702) <= \<const0>\;
  LOCKSTEP_Out(3703) <= \<const0>\;
  LOCKSTEP_Out(3704) <= \<const0>\;
  LOCKSTEP_Out(3705) <= \<const0>\;
  LOCKSTEP_Out(3706) <= \<const0>\;
  LOCKSTEP_Out(3707) <= \<const0>\;
  LOCKSTEP_Out(3708) <= \<const0>\;
  LOCKSTEP_Out(3709) <= \<const0>\;
  LOCKSTEP_Out(3710) <= \<const0>\;
  LOCKSTEP_Out(3711) <= \<const0>\;
  LOCKSTEP_Out(3712) <= \<const0>\;
  LOCKSTEP_Out(3713) <= \<const0>\;
  LOCKSTEP_Out(3714) <= \<const0>\;
  LOCKSTEP_Out(3715) <= \<const0>\;
  LOCKSTEP_Out(3716) <= \<const0>\;
  LOCKSTEP_Out(3717) <= \<const0>\;
  LOCKSTEP_Out(3718) <= \<const0>\;
  LOCKSTEP_Out(3719) <= \<const0>\;
  LOCKSTEP_Out(3720) <= \<const0>\;
  LOCKSTEP_Out(3721) <= \<const0>\;
  LOCKSTEP_Out(3722) <= \<const0>\;
  LOCKSTEP_Out(3723) <= \<const0>\;
  LOCKSTEP_Out(3724) <= \<const0>\;
  LOCKSTEP_Out(3725) <= \<const0>\;
  LOCKSTEP_Out(3726) <= \<const0>\;
  LOCKSTEP_Out(3727) <= \<const0>\;
  LOCKSTEP_Out(3728) <= \<const0>\;
  LOCKSTEP_Out(3729) <= \<const0>\;
  LOCKSTEP_Out(3730) <= \<const0>\;
  LOCKSTEP_Out(3731) <= \<const0>\;
  LOCKSTEP_Out(3732) <= \<const0>\;
  LOCKSTEP_Out(3733) <= \<const0>\;
  LOCKSTEP_Out(3734) <= \<const0>\;
  LOCKSTEP_Out(3735) <= \<const0>\;
  LOCKSTEP_Out(3736) <= \<const0>\;
  LOCKSTEP_Out(3737) <= \<const0>\;
  LOCKSTEP_Out(3738) <= \<const0>\;
  LOCKSTEP_Out(3739) <= \<const0>\;
  LOCKSTEP_Out(3740) <= \<const0>\;
  LOCKSTEP_Out(3741) <= \<const0>\;
  LOCKSTEP_Out(3742) <= \<const0>\;
  LOCKSTEP_Out(3743) <= \<const0>\;
  LOCKSTEP_Out(3744) <= \<const0>\;
  LOCKSTEP_Out(3745) <= \<const0>\;
  LOCKSTEP_Out(3746) <= \<const0>\;
  LOCKSTEP_Out(3747) <= \<const0>\;
  LOCKSTEP_Out(3748) <= \<const0>\;
  LOCKSTEP_Out(3749) <= \<const0>\;
  LOCKSTEP_Out(3750) <= \<const0>\;
  LOCKSTEP_Out(3751) <= \<const0>\;
  LOCKSTEP_Out(3752) <= \<const0>\;
  LOCKSTEP_Out(3753) <= \<const0>\;
  LOCKSTEP_Out(3754) <= \<const0>\;
  LOCKSTEP_Out(3755) <= \<const0>\;
  LOCKSTEP_Out(3756) <= \<const0>\;
  LOCKSTEP_Out(3757) <= \<const0>\;
  LOCKSTEP_Out(3758) <= \<const0>\;
  LOCKSTEP_Out(3759) <= \<const0>\;
  LOCKSTEP_Out(3760) <= \<const0>\;
  LOCKSTEP_Out(3761) <= \<const0>\;
  LOCKSTEP_Out(3762) <= \<const0>\;
  LOCKSTEP_Out(3763) <= \<const0>\;
  LOCKSTEP_Out(3764) <= \<const0>\;
  LOCKSTEP_Out(3765) <= \<const0>\;
  LOCKSTEP_Out(3766) <= \<const0>\;
  LOCKSTEP_Out(3767) <= \<const0>\;
  LOCKSTEP_Out(3768) <= \<const0>\;
  LOCKSTEP_Out(3769) <= \<const0>\;
  LOCKSTEP_Out(3770) <= \<const0>\;
  LOCKSTEP_Out(3771) <= \<const0>\;
  LOCKSTEP_Out(3772) <= \<const0>\;
  LOCKSTEP_Out(3773) <= \<const0>\;
  LOCKSTEP_Out(3774) <= \<const0>\;
  LOCKSTEP_Out(3775) <= \<const0>\;
  LOCKSTEP_Out(3776) <= \<const0>\;
  LOCKSTEP_Out(3777) <= \<const0>\;
  LOCKSTEP_Out(3778) <= \<const0>\;
  LOCKSTEP_Out(3779) <= \<const0>\;
  LOCKSTEP_Out(3780) <= \<const0>\;
  LOCKSTEP_Out(3781) <= \<const0>\;
  LOCKSTEP_Out(3782) <= \<const0>\;
  LOCKSTEP_Out(3783) <= \<const0>\;
  LOCKSTEP_Out(3784) <= \<const0>\;
  LOCKSTEP_Out(3785) <= \<const0>\;
  LOCKSTEP_Out(3786) <= \<const0>\;
  LOCKSTEP_Out(3787) <= \<const0>\;
  LOCKSTEP_Out(3788) <= \<const0>\;
  LOCKSTEP_Out(3789) <= \<const0>\;
  LOCKSTEP_Out(3790) <= \<const0>\;
  LOCKSTEP_Out(3791) <= \<const0>\;
  LOCKSTEP_Out(3792) <= \<const0>\;
  LOCKSTEP_Out(3793) <= \<const0>\;
  LOCKSTEP_Out(3794) <= \<const0>\;
  LOCKSTEP_Out(3795) <= \<const0>\;
  LOCKSTEP_Out(3796) <= \<const0>\;
  LOCKSTEP_Out(3797) <= \<const0>\;
  LOCKSTEP_Out(3798) <= \<const0>\;
  LOCKSTEP_Out(3799) <= \<const0>\;
  LOCKSTEP_Out(3800) <= \<const0>\;
  LOCKSTEP_Out(3801) <= \<const0>\;
  LOCKSTEP_Out(3802) <= \<const0>\;
  LOCKSTEP_Out(3803) <= \<const0>\;
  LOCKSTEP_Out(3804) <= \<const0>\;
  LOCKSTEP_Out(3805) <= \<const0>\;
  LOCKSTEP_Out(3806) <= \<const0>\;
  LOCKSTEP_Out(3807) <= \<const0>\;
  LOCKSTEP_Out(3808) <= \<const0>\;
  LOCKSTEP_Out(3809) <= \<const0>\;
  LOCKSTEP_Out(3810) <= \<const0>\;
  LOCKSTEP_Out(3811) <= \<const0>\;
  LOCKSTEP_Out(3812) <= \<const0>\;
  LOCKSTEP_Out(3813) <= \<const0>\;
  LOCKSTEP_Out(3814) <= \<const0>\;
  LOCKSTEP_Out(3815) <= \<const0>\;
  LOCKSTEP_Out(3816) <= \<const0>\;
  LOCKSTEP_Out(3817) <= \<const0>\;
  LOCKSTEP_Out(3818) <= \<const0>\;
  LOCKSTEP_Out(3819) <= \<const0>\;
  LOCKSTEP_Out(3820) <= \<const0>\;
  LOCKSTEP_Out(3821) <= \<const0>\;
  LOCKSTEP_Out(3822) <= \<const0>\;
  LOCKSTEP_Out(3823) <= \<const0>\;
  LOCKSTEP_Out(3824) <= \<const0>\;
  LOCKSTEP_Out(3825) <= \<const0>\;
  LOCKSTEP_Out(3826) <= \<const0>\;
  LOCKSTEP_Out(3827) <= \<const0>\;
  LOCKSTEP_Out(3828) <= \<const0>\;
  LOCKSTEP_Out(3829) <= \<const0>\;
  LOCKSTEP_Out(3830) <= \<const0>\;
  LOCKSTEP_Out(3831) <= \<const0>\;
  LOCKSTEP_Out(3832) <= \<const0>\;
  LOCKSTEP_Out(3833) <= \<const0>\;
  LOCKSTEP_Out(3834) <= \<const0>\;
  LOCKSTEP_Out(3835) <= \<const0>\;
  LOCKSTEP_Out(3836) <= \<const0>\;
  LOCKSTEP_Out(3837) <= \<const0>\;
  LOCKSTEP_Out(3838) <= \<const0>\;
  LOCKSTEP_Out(3839) <= \<const0>\;
  LOCKSTEP_Out(3840) <= \<const0>\;
  LOCKSTEP_Out(3841) <= \<const0>\;
  LOCKSTEP_Out(3842) <= \<const0>\;
  LOCKSTEP_Out(3843) <= \<const0>\;
  LOCKSTEP_Out(3844) <= \<const0>\;
  LOCKSTEP_Out(3845) <= \<const0>\;
  LOCKSTEP_Out(3846) <= \<const0>\;
  LOCKSTEP_Out(3847) <= \<const0>\;
  LOCKSTEP_Out(3848) <= \<const0>\;
  LOCKSTEP_Out(3849) <= \<const0>\;
  LOCKSTEP_Out(3850) <= \<const0>\;
  LOCKSTEP_Out(3851) <= \<const0>\;
  LOCKSTEP_Out(3852) <= \<const0>\;
  LOCKSTEP_Out(3853) <= \<const0>\;
  LOCKSTEP_Out(3854) <= \<const0>\;
  LOCKSTEP_Out(3855) <= \<const0>\;
  LOCKSTEP_Out(3856) <= \<const0>\;
  LOCKSTEP_Out(3857) <= \<const0>\;
  LOCKSTEP_Out(3858) <= \<const0>\;
  LOCKSTEP_Out(3859) <= \<const0>\;
  LOCKSTEP_Out(3860) <= \<const0>\;
  LOCKSTEP_Out(3861) <= \<const0>\;
  LOCKSTEP_Out(3862) <= \<const0>\;
  LOCKSTEP_Out(3863) <= \<const0>\;
  LOCKSTEP_Out(3864) <= \<const0>\;
  LOCKSTEP_Out(3865) <= \<const0>\;
  LOCKSTEP_Out(3866) <= \<const0>\;
  LOCKSTEP_Out(3867) <= \<const0>\;
  LOCKSTEP_Out(3868) <= \<const0>\;
  LOCKSTEP_Out(3869) <= \<const0>\;
  LOCKSTEP_Out(3870) <= \<const0>\;
  LOCKSTEP_Out(3871) <= \<const0>\;
  LOCKSTEP_Out(3872) <= \<const0>\;
  LOCKSTEP_Out(3873) <= \<const0>\;
  LOCKSTEP_Out(3874) <= \<const0>\;
  LOCKSTEP_Out(3875) <= \<const0>\;
  LOCKSTEP_Out(3876) <= \<const0>\;
  LOCKSTEP_Out(3877) <= \<const0>\;
  LOCKSTEP_Out(3878) <= \<const0>\;
  LOCKSTEP_Out(3879) <= \<const0>\;
  LOCKSTEP_Out(3880) <= \<const0>\;
  LOCKSTEP_Out(3881) <= \<const0>\;
  LOCKSTEP_Out(3882) <= \<const0>\;
  LOCKSTEP_Out(3883) <= \<const0>\;
  LOCKSTEP_Out(3884) <= \<const0>\;
  LOCKSTEP_Out(3885) <= \<const0>\;
  LOCKSTEP_Out(3886) <= \<const0>\;
  LOCKSTEP_Out(3887) <= \<const0>\;
  LOCKSTEP_Out(3888) <= \<const0>\;
  LOCKSTEP_Out(3889) <= \<const0>\;
  LOCKSTEP_Out(3890) <= \<const0>\;
  LOCKSTEP_Out(3891) <= \<const0>\;
  LOCKSTEP_Out(3892) <= \<const0>\;
  LOCKSTEP_Out(3893) <= \<const0>\;
  LOCKSTEP_Out(3894) <= \<const0>\;
  LOCKSTEP_Out(3895) <= \<const0>\;
  LOCKSTEP_Out(3896) <= \<const0>\;
  LOCKSTEP_Out(3897) <= \<const0>\;
  LOCKSTEP_Out(3898) <= \<const0>\;
  LOCKSTEP_Out(3899) <= \<const0>\;
  LOCKSTEP_Out(3900) <= \<const0>\;
  LOCKSTEP_Out(3901) <= \<const0>\;
  LOCKSTEP_Out(3902) <= \<const0>\;
  LOCKSTEP_Out(3903) <= \<const0>\;
  LOCKSTEP_Out(3904) <= \<const0>\;
  LOCKSTEP_Out(3905) <= \<const0>\;
  LOCKSTEP_Out(3906) <= \<const0>\;
  LOCKSTEP_Out(3907) <= \<const0>\;
  LOCKSTEP_Out(3908) <= \<const0>\;
  LOCKSTEP_Out(3909) <= \<const0>\;
  LOCKSTEP_Out(3910) <= \<const0>\;
  LOCKSTEP_Out(3911) <= \<const0>\;
  LOCKSTEP_Out(3912) <= \<const0>\;
  LOCKSTEP_Out(3913) <= \<const0>\;
  LOCKSTEP_Out(3914) <= \<const0>\;
  LOCKSTEP_Out(3915) <= \<const0>\;
  LOCKSTEP_Out(3916) <= \<const0>\;
  LOCKSTEP_Out(3917) <= \<const0>\;
  LOCKSTEP_Out(3918) <= \<const0>\;
  LOCKSTEP_Out(3919) <= \<const0>\;
  LOCKSTEP_Out(3920) <= \<const0>\;
  LOCKSTEP_Out(3921) <= \<const0>\;
  LOCKSTEP_Out(3922) <= \<const0>\;
  LOCKSTEP_Out(3923) <= \<const0>\;
  LOCKSTEP_Out(3924) <= \<const0>\;
  LOCKSTEP_Out(3925) <= \<const0>\;
  LOCKSTEP_Out(3926) <= \<const0>\;
  LOCKSTEP_Out(3927) <= \<const0>\;
  LOCKSTEP_Out(3928) <= \<const0>\;
  LOCKSTEP_Out(3929) <= \<const0>\;
  LOCKSTEP_Out(3930) <= \<const0>\;
  LOCKSTEP_Out(3931) <= \<const0>\;
  LOCKSTEP_Out(3932) <= \<const0>\;
  LOCKSTEP_Out(3933) <= \<const0>\;
  LOCKSTEP_Out(3934) <= \<const0>\;
  LOCKSTEP_Out(3935) <= \<const0>\;
  LOCKSTEP_Out(3936) <= \<const0>\;
  LOCKSTEP_Out(3937) <= \<const0>\;
  LOCKSTEP_Out(3938) <= \<const0>\;
  LOCKSTEP_Out(3939) <= \<const0>\;
  LOCKSTEP_Out(3940) <= \<const0>\;
  LOCKSTEP_Out(3941) <= \<const0>\;
  LOCKSTEP_Out(3942) <= \<const0>\;
  LOCKSTEP_Out(3943) <= \<const0>\;
  LOCKSTEP_Out(3944) <= \<const0>\;
  LOCKSTEP_Out(3945) <= \<const0>\;
  LOCKSTEP_Out(3946) <= \<const0>\;
  LOCKSTEP_Out(3947) <= \<const0>\;
  LOCKSTEP_Out(3948) <= \<const0>\;
  LOCKSTEP_Out(3949) <= \<const0>\;
  LOCKSTEP_Out(3950) <= \<const0>\;
  LOCKSTEP_Out(3951) <= \<const0>\;
  LOCKSTEP_Out(3952) <= \<const0>\;
  LOCKSTEP_Out(3953) <= \<const0>\;
  LOCKSTEP_Out(3954) <= \<const0>\;
  LOCKSTEP_Out(3955) <= \<const0>\;
  LOCKSTEP_Out(3956) <= \<const0>\;
  LOCKSTEP_Out(3957) <= \<const0>\;
  LOCKSTEP_Out(3958) <= \<const0>\;
  LOCKSTEP_Out(3959) <= \<const0>\;
  LOCKSTEP_Out(3960) <= \<const0>\;
  LOCKSTEP_Out(3961) <= \<const0>\;
  LOCKSTEP_Out(3962) <= \<const0>\;
  LOCKSTEP_Out(3963) <= \<const0>\;
  LOCKSTEP_Out(3964) <= \<const0>\;
  LOCKSTEP_Out(3965) <= \<const0>\;
  LOCKSTEP_Out(3966) <= \<const0>\;
  LOCKSTEP_Out(3967) <= \<const0>\;
  LOCKSTEP_Out(3968) <= \<const0>\;
  LOCKSTEP_Out(3969) <= \<const0>\;
  LOCKSTEP_Out(3970) <= \<const0>\;
  LOCKSTEP_Out(3971) <= \<const0>\;
  LOCKSTEP_Out(3972) <= \<const0>\;
  LOCKSTEP_Out(3973) <= \<const0>\;
  LOCKSTEP_Out(3974) <= \<const0>\;
  LOCKSTEP_Out(3975) <= \<const0>\;
  LOCKSTEP_Out(3976) <= \<const0>\;
  LOCKSTEP_Out(3977) <= \<const0>\;
  LOCKSTEP_Out(3978) <= \<const0>\;
  LOCKSTEP_Out(3979) <= \<const0>\;
  LOCKSTEP_Out(3980) <= \<const0>\;
  LOCKSTEP_Out(3981) <= \<const0>\;
  LOCKSTEP_Out(3982) <= \<const0>\;
  LOCKSTEP_Out(3983) <= \<const0>\;
  LOCKSTEP_Out(3984) <= \<const0>\;
  LOCKSTEP_Out(3985) <= \<const0>\;
  LOCKSTEP_Out(3986) <= \<const0>\;
  LOCKSTEP_Out(3987) <= \<const0>\;
  LOCKSTEP_Out(3988) <= \<const0>\;
  LOCKSTEP_Out(3989) <= \<const0>\;
  LOCKSTEP_Out(3990) <= \<const0>\;
  LOCKSTEP_Out(3991) <= \<const0>\;
  LOCKSTEP_Out(3992) <= \<const0>\;
  LOCKSTEP_Out(3993) <= \<const0>\;
  LOCKSTEP_Out(3994) <= \<const0>\;
  LOCKSTEP_Out(3995) <= \<const0>\;
  LOCKSTEP_Out(3996) <= \<const0>\;
  LOCKSTEP_Out(3997) <= \<const0>\;
  LOCKSTEP_Out(3998) <= \<const0>\;
  LOCKSTEP_Out(3999) <= \<const0>\;
  LOCKSTEP_Out(4000) <= \<const0>\;
  LOCKSTEP_Out(4001) <= \<const0>\;
  LOCKSTEP_Out(4002) <= \<const0>\;
  LOCKSTEP_Out(4003) <= \<const0>\;
  LOCKSTEP_Out(4004) <= \<const0>\;
  LOCKSTEP_Out(4005) <= \<const0>\;
  LOCKSTEP_Out(4006) <= \<const0>\;
  LOCKSTEP_Out(4007) <= \<const0>\;
  LOCKSTEP_Out(4008) <= \<const0>\;
  LOCKSTEP_Out(4009) <= \<const0>\;
  LOCKSTEP_Out(4010) <= \<const0>\;
  LOCKSTEP_Out(4011) <= \<const0>\;
  LOCKSTEP_Out(4012) <= \<const0>\;
  LOCKSTEP_Out(4013) <= \<const0>\;
  LOCKSTEP_Out(4014) <= \<const0>\;
  LOCKSTEP_Out(4015) <= \<const0>\;
  LOCKSTEP_Out(4016) <= \<const0>\;
  LOCKSTEP_Out(4017) <= \<const0>\;
  LOCKSTEP_Out(4018) <= \<const0>\;
  LOCKSTEP_Out(4019) <= \<const0>\;
  LOCKSTEP_Out(4020) <= \<const0>\;
  LOCKSTEP_Out(4021) <= \<const0>\;
  LOCKSTEP_Out(4022) <= \<const0>\;
  LOCKSTEP_Out(4023) <= \<const0>\;
  LOCKSTEP_Out(4024) <= \<const0>\;
  LOCKSTEP_Out(4025) <= \<const0>\;
  LOCKSTEP_Out(4026) <= \<const0>\;
  LOCKSTEP_Out(4027) <= \<const0>\;
  LOCKSTEP_Out(4028) <= \<const0>\;
  LOCKSTEP_Out(4029) <= \<const0>\;
  LOCKSTEP_Out(4030) <= \<const0>\;
  LOCKSTEP_Out(4031) <= \<const0>\;
  LOCKSTEP_Out(4032) <= \<const0>\;
  LOCKSTEP_Out(4033) <= \<const0>\;
  LOCKSTEP_Out(4034) <= \<const0>\;
  LOCKSTEP_Out(4035) <= \<const0>\;
  LOCKSTEP_Out(4036) <= \<const0>\;
  LOCKSTEP_Out(4037) <= \<const0>\;
  LOCKSTEP_Out(4038) <= \<const0>\;
  LOCKSTEP_Out(4039) <= \<const0>\;
  LOCKSTEP_Out(4040) <= \<const0>\;
  LOCKSTEP_Out(4041) <= \<const0>\;
  LOCKSTEP_Out(4042) <= \<const0>\;
  LOCKSTEP_Out(4043) <= \<const0>\;
  LOCKSTEP_Out(4044) <= \<const0>\;
  LOCKSTEP_Out(4045) <= \<const0>\;
  LOCKSTEP_Out(4046) <= \<const0>\;
  LOCKSTEP_Out(4047) <= \<const0>\;
  LOCKSTEP_Out(4048) <= \<const0>\;
  LOCKSTEP_Out(4049) <= \<const0>\;
  LOCKSTEP_Out(4050) <= \<const0>\;
  LOCKSTEP_Out(4051) <= \<const0>\;
  LOCKSTEP_Out(4052) <= \<const0>\;
  LOCKSTEP_Out(4053) <= \<const0>\;
  LOCKSTEP_Out(4054) <= \<const0>\;
  LOCKSTEP_Out(4055) <= \<const0>\;
  LOCKSTEP_Out(4056) <= \<const0>\;
  LOCKSTEP_Out(4057) <= \<const0>\;
  LOCKSTEP_Out(4058) <= \<const0>\;
  LOCKSTEP_Out(4059) <= \<const0>\;
  LOCKSTEP_Out(4060) <= \<const0>\;
  LOCKSTEP_Out(4061) <= \<const0>\;
  LOCKSTEP_Out(4062) <= \<const0>\;
  LOCKSTEP_Out(4063) <= \<const0>\;
  LOCKSTEP_Out(4064) <= \<const0>\;
  LOCKSTEP_Out(4065) <= \<const0>\;
  LOCKSTEP_Out(4066) <= \<const0>\;
  LOCKSTEP_Out(4067) <= \<const0>\;
  LOCKSTEP_Out(4068) <= \<const0>\;
  LOCKSTEP_Out(4069) <= \<const0>\;
  LOCKSTEP_Out(4070) <= \<const0>\;
  LOCKSTEP_Out(4071) <= \<const0>\;
  LOCKSTEP_Out(4072) <= \<const0>\;
  LOCKSTEP_Out(4073) <= \<const0>\;
  LOCKSTEP_Out(4074) <= \<const0>\;
  LOCKSTEP_Out(4075) <= \<const0>\;
  LOCKSTEP_Out(4076) <= \<const0>\;
  LOCKSTEP_Out(4077) <= \<const0>\;
  LOCKSTEP_Out(4078) <= \<const0>\;
  LOCKSTEP_Out(4079) <= \<const0>\;
  LOCKSTEP_Out(4080) <= \<const0>\;
  LOCKSTEP_Out(4081) <= \<const0>\;
  LOCKSTEP_Out(4082) <= \<const0>\;
  LOCKSTEP_Out(4083) <= \<const0>\;
  LOCKSTEP_Out(4084) <= \<const0>\;
  LOCKSTEP_Out(4085) <= \<const0>\;
  LOCKSTEP_Out(4086) <= \<const0>\;
  LOCKSTEP_Out(4087) <= \<const0>\;
  LOCKSTEP_Out(4088) <= \<const0>\;
  LOCKSTEP_Out(4089) <= \<const0>\;
  LOCKSTEP_Out(4090) <= \<const0>\;
  LOCKSTEP_Out(4091) <= \<const0>\;
  LOCKSTEP_Out(4092) <= \<const0>\;
  LOCKSTEP_Out(4093) <= \<const0>\;
  LOCKSTEP_Out(4094) <= \<const0>\;
  LOCKSTEP_Out(4095) <= \<const0>\;
  M0_AXIS_TDATA(31) <= \<const0>\;
  M0_AXIS_TDATA(30) <= \<const0>\;
  M0_AXIS_TDATA(29) <= \<const0>\;
  M0_AXIS_TDATA(28) <= \<const0>\;
  M0_AXIS_TDATA(27) <= \<const0>\;
  M0_AXIS_TDATA(26) <= \<const0>\;
  M0_AXIS_TDATA(25) <= \<const0>\;
  M0_AXIS_TDATA(24) <= \<const0>\;
  M0_AXIS_TDATA(23) <= \<const0>\;
  M0_AXIS_TDATA(22) <= \<const0>\;
  M0_AXIS_TDATA(21) <= \<const0>\;
  M0_AXIS_TDATA(20) <= \<const0>\;
  M0_AXIS_TDATA(19) <= \<const0>\;
  M0_AXIS_TDATA(18) <= \<const0>\;
  M0_AXIS_TDATA(17) <= \<const0>\;
  M0_AXIS_TDATA(16) <= \<const0>\;
  M0_AXIS_TDATA(15) <= \<const0>\;
  M0_AXIS_TDATA(14) <= \<const0>\;
  M0_AXIS_TDATA(13) <= \<const0>\;
  M0_AXIS_TDATA(12) <= \<const0>\;
  M0_AXIS_TDATA(11) <= \<const0>\;
  M0_AXIS_TDATA(10) <= \<const0>\;
  M0_AXIS_TDATA(9) <= \<const0>\;
  M0_AXIS_TDATA(8) <= \<const0>\;
  M0_AXIS_TDATA(7) <= \<const0>\;
  M0_AXIS_TDATA(6) <= \<const0>\;
  M0_AXIS_TDATA(5) <= \<const0>\;
  M0_AXIS_TDATA(4) <= \<const0>\;
  M0_AXIS_TDATA(3) <= \<const0>\;
  M0_AXIS_TDATA(2) <= \<const0>\;
  M0_AXIS_TDATA(1) <= \<const0>\;
  M0_AXIS_TDATA(0) <= \<const0>\;
  M0_AXIS_TLAST <= \<const0>\;
  M0_AXIS_TVALID <= \<const0>\;
  M10_AXIS_TDATA(31) <= \<const0>\;
  M10_AXIS_TDATA(30) <= \<const0>\;
  M10_AXIS_TDATA(29) <= \<const0>\;
  M10_AXIS_TDATA(28) <= \<const0>\;
  M10_AXIS_TDATA(27) <= \<const0>\;
  M10_AXIS_TDATA(26) <= \<const0>\;
  M10_AXIS_TDATA(25) <= \<const0>\;
  M10_AXIS_TDATA(24) <= \<const0>\;
  M10_AXIS_TDATA(23) <= \<const0>\;
  M10_AXIS_TDATA(22) <= \<const0>\;
  M10_AXIS_TDATA(21) <= \<const0>\;
  M10_AXIS_TDATA(20) <= \<const0>\;
  M10_AXIS_TDATA(19) <= \<const0>\;
  M10_AXIS_TDATA(18) <= \<const0>\;
  M10_AXIS_TDATA(17) <= \<const0>\;
  M10_AXIS_TDATA(16) <= \<const0>\;
  M10_AXIS_TDATA(15) <= \<const0>\;
  M10_AXIS_TDATA(14) <= \<const0>\;
  M10_AXIS_TDATA(13) <= \<const0>\;
  M10_AXIS_TDATA(12) <= \<const0>\;
  M10_AXIS_TDATA(11) <= \<const0>\;
  M10_AXIS_TDATA(10) <= \<const0>\;
  M10_AXIS_TDATA(9) <= \<const0>\;
  M10_AXIS_TDATA(8) <= \<const0>\;
  M10_AXIS_TDATA(7) <= \<const0>\;
  M10_AXIS_TDATA(6) <= \<const0>\;
  M10_AXIS_TDATA(5) <= \<const0>\;
  M10_AXIS_TDATA(4) <= \<const0>\;
  M10_AXIS_TDATA(3) <= \<const0>\;
  M10_AXIS_TDATA(2) <= \<const0>\;
  M10_AXIS_TDATA(1) <= \<const0>\;
  M10_AXIS_TDATA(0) <= \<const0>\;
  M10_AXIS_TLAST <= \<const0>\;
  M10_AXIS_TVALID <= \<const0>\;
  M11_AXIS_TDATA(31) <= \<const0>\;
  M11_AXIS_TDATA(30) <= \<const0>\;
  M11_AXIS_TDATA(29) <= \<const0>\;
  M11_AXIS_TDATA(28) <= \<const0>\;
  M11_AXIS_TDATA(27) <= \<const0>\;
  M11_AXIS_TDATA(26) <= \<const0>\;
  M11_AXIS_TDATA(25) <= \<const0>\;
  M11_AXIS_TDATA(24) <= \<const0>\;
  M11_AXIS_TDATA(23) <= \<const0>\;
  M11_AXIS_TDATA(22) <= \<const0>\;
  M11_AXIS_TDATA(21) <= \<const0>\;
  M11_AXIS_TDATA(20) <= \<const0>\;
  M11_AXIS_TDATA(19) <= \<const0>\;
  M11_AXIS_TDATA(18) <= \<const0>\;
  M11_AXIS_TDATA(17) <= \<const0>\;
  M11_AXIS_TDATA(16) <= \<const0>\;
  M11_AXIS_TDATA(15) <= \<const0>\;
  M11_AXIS_TDATA(14) <= \<const0>\;
  M11_AXIS_TDATA(13) <= \<const0>\;
  M11_AXIS_TDATA(12) <= \<const0>\;
  M11_AXIS_TDATA(11) <= \<const0>\;
  M11_AXIS_TDATA(10) <= \<const0>\;
  M11_AXIS_TDATA(9) <= \<const0>\;
  M11_AXIS_TDATA(8) <= \<const0>\;
  M11_AXIS_TDATA(7) <= \<const0>\;
  M11_AXIS_TDATA(6) <= \<const0>\;
  M11_AXIS_TDATA(5) <= \<const0>\;
  M11_AXIS_TDATA(4) <= \<const0>\;
  M11_AXIS_TDATA(3) <= \<const0>\;
  M11_AXIS_TDATA(2) <= \<const0>\;
  M11_AXIS_TDATA(1) <= \<const0>\;
  M11_AXIS_TDATA(0) <= \<const0>\;
  M11_AXIS_TLAST <= \<const0>\;
  M11_AXIS_TVALID <= \<const0>\;
  M12_AXIS_TDATA(31) <= \<const0>\;
  M12_AXIS_TDATA(30) <= \<const0>\;
  M12_AXIS_TDATA(29) <= \<const0>\;
  M12_AXIS_TDATA(28) <= \<const0>\;
  M12_AXIS_TDATA(27) <= \<const0>\;
  M12_AXIS_TDATA(26) <= \<const0>\;
  M12_AXIS_TDATA(25) <= \<const0>\;
  M12_AXIS_TDATA(24) <= \<const0>\;
  M12_AXIS_TDATA(23) <= \<const0>\;
  M12_AXIS_TDATA(22) <= \<const0>\;
  M12_AXIS_TDATA(21) <= \<const0>\;
  M12_AXIS_TDATA(20) <= \<const0>\;
  M12_AXIS_TDATA(19) <= \<const0>\;
  M12_AXIS_TDATA(18) <= \<const0>\;
  M12_AXIS_TDATA(17) <= \<const0>\;
  M12_AXIS_TDATA(16) <= \<const0>\;
  M12_AXIS_TDATA(15) <= \<const0>\;
  M12_AXIS_TDATA(14) <= \<const0>\;
  M12_AXIS_TDATA(13) <= \<const0>\;
  M12_AXIS_TDATA(12) <= \<const0>\;
  M12_AXIS_TDATA(11) <= \<const0>\;
  M12_AXIS_TDATA(10) <= \<const0>\;
  M12_AXIS_TDATA(9) <= \<const0>\;
  M12_AXIS_TDATA(8) <= \<const0>\;
  M12_AXIS_TDATA(7) <= \<const0>\;
  M12_AXIS_TDATA(6) <= \<const0>\;
  M12_AXIS_TDATA(5) <= \<const0>\;
  M12_AXIS_TDATA(4) <= \<const0>\;
  M12_AXIS_TDATA(3) <= \<const0>\;
  M12_AXIS_TDATA(2) <= \<const0>\;
  M12_AXIS_TDATA(1) <= \<const0>\;
  M12_AXIS_TDATA(0) <= \<const0>\;
  M12_AXIS_TLAST <= \<const0>\;
  M12_AXIS_TVALID <= \<const0>\;
  M13_AXIS_TDATA(31) <= \<const0>\;
  M13_AXIS_TDATA(30) <= \<const0>\;
  M13_AXIS_TDATA(29) <= \<const0>\;
  M13_AXIS_TDATA(28) <= \<const0>\;
  M13_AXIS_TDATA(27) <= \<const0>\;
  M13_AXIS_TDATA(26) <= \<const0>\;
  M13_AXIS_TDATA(25) <= \<const0>\;
  M13_AXIS_TDATA(24) <= \<const0>\;
  M13_AXIS_TDATA(23) <= \<const0>\;
  M13_AXIS_TDATA(22) <= \<const0>\;
  M13_AXIS_TDATA(21) <= \<const0>\;
  M13_AXIS_TDATA(20) <= \<const0>\;
  M13_AXIS_TDATA(19) <= \<const0>\;
  M13_AXIS_TDATA(18) <= \<const0>\;
  M13_AXIS_TDATA(17) <= \<const0>\;
  M13_AXIS_TDATA(16) <= \<const0>\;
  M13_AXIS_TDATA(15) <= \<const0>\;
  M13_AXIS_TDATA(14) <= \<const0>\;
  M13_AXIS_TDATA(13) <= \<const0>\;
  M13_AXIS_TDATA(12) <= \<const0>\;
  M13_AXIS_TDATA(11) <= \<const0>\;
  M13_AXIS_TDATA(10) <= \<const0>\;
  M13_AXIS_TDATA(9) <= \<const0>\;
  M13_AXIS_TDATA(8) <= \<const0>\;
  M13_AXIS_TDATA(7) <= \<const0>\;
  M13_AXIS_TDATA(6) <= \<const0>\;
  M13_AXIS_TDATA(5) <= \<const0>\;
  M13_AXIS_TDATA(4) <= \<const0>\;
  M13_AXIS_TDATA(3) <= \<const0>\;
  M13_AXIS_TDATA(2) <= \<const0>\;
  M13_AXIS_TDATA(1) <= \<const0>\;
  M13_AXIS_TDATA(0) <= \<const0>\;
  M13_AXIS_TLAST <= \<const0>\;
  M13_AXIS_TVALID <= \<const0>\;
  M14_AXIS_TDATA(31) <= \<const0>\;
  M14_AXIS_TDATA(30) <= \<const0>\;
  M14_AXIS_TDATA(29) <= \<const0>\;
  M14_AXIS_TDATA(28) <= \<const0>\;
  M14_AXIS_TDATA(27) <= \<const0>\;
  M14_AXIS_TDATA(26) <= \<const0>\;
  M14_AXIS_TDATA(25) <= \<const0>\;
  M14_AXIS_TDATA(24) <= \<const0>\;
  M14_AXIS_TDATA(23) <= \<const0>\;
  M14_AXIS_TDATA(22) <= \<const0>\;
  M14_AXIS_TDATA(21) <= \<const0>\;
  M14_AXIS_TDATA(20) <= \<const0>\;
  M14_AXIS_TDATA(19) <= \<const0>\;
  M14_AXIS_TDATA(18) <= \<const0>\;
  M14_AXIS_TDATA(17) <= \<const0>\;
  M14_AXIS_TDATA(16) <= \<const0>\;
  M14_AXIS_TDATA(15) <= \<const0>\;
  M14_AXIS_TDATA(14) <= \<const0>\;
  M14_AXIS_TDATA(13) <= \<const0>\;
  M14_AXIS_TDATA(12) <= \<const0>\;
  M14_AXIS_TDATA(11) <= \<const0>\;
  M14_AXIS_TDATA(10) <= \<const0>\;
  M14_AXIS_TDATA(9) <= \<const0>\;
  M14_AXIS_TDATA(8) <= \<const0>\;
  M14_AXIS_TDATA(7) <= \<const0>\;
  M14_AXIS_TDATA(6) <= \<const0>\;
  M14_AXIS_TDATA(5) <= \<const0>\;
  M14_AXIS_TDATA(4) <= \<const0>\;
  M14_AXIS_TDATA(3) <= \<const0>\;
  M14_AXIS_TDATA(2) <= \<const0>\;
  M14_AXIS_TDATA(1) <= \<const0>\;
  M14_AXIS_TDATA(0) <= \<const0>\;
  M14_AXIS_TLAST <= \<const0>\;
  M14_AXIS_TVALID <= \<const0>\;
  M15_AXIS_TDATA(31) <= \<const0>\;
  M15_AXIS_TDATA(30) <= \<const0>\;
  M15_AXIS_TDATA(29) <= \<const0>\;
  M15_AXIS_TDATA(28) <= \<const0>\;
  M15_AXIS_TDATA(27) <= \<const0>\;
  M15_AXIS_TDATA(26) <= \<const0>\;
  M15_AXIS_TDATA(25) <= \<const0>\;
  M15_AXIS_TDATA(24) <= \<const0>\;
  M15_AXIS_TDATA(23) <= \<const0>\;
  M15_AXIS_TDATA(22) <= \<const0>\;
  M15_AXIS_TDATA(21) <= \<const0>\;
  M15_AXIS_TDATA(20) <= \<const0>\;
  M15_AXIS_TDATA(19) <= \<const0>\;
  M15_AXIS_TDATA(18) <= \<const0>\;
  M15_AXIS_TDATA(17) <= \<const0>\;
  M15_AXIS_TDATA(16) <= \<const0>\;
  M15_AXIS_TDATA(15) <= \<const0>\;
  M15_AXIS_TDATA(14) <= \<const0>\;
  M15_AXIS_TDATA(13) <= \<const0>\;
  M15_AXIS_TDATA(12) <= \<const0>\;
  M15_AXIS_TDATA(11) <= \<const0>\;
  M15_AXIS_TDATA(10) <= \<const0>\;
  M15_AXIS_TDATA(9) <= \<const0>\;
  M15_AXIS_TDATA(8) <= \<const0>\;
  M15_AXIS_TDATA(7) <= \<const0>\;
  M15_AXIS_TDATA(6) <= \<const0>\;
  M15_AXIS_TDATA(5) <= \<const0>\;
  M15_AXIS_TDATA(4) <= \<const0>\;
  M15_AXIS_TDATA(3) <= \<const0>\;
  M15_AXIS_TDATA(2) <= \<const0>\;
  M15_AXIS_TDATA(1) <= \<const0>\;
  M15_AXIS_TDATA(0) <= \<const0>\;
  M15_AXIS_TLAST <= \<const0>\;
  M15_AXIS_TVALID <= \<const0>\;
  M1_AXIS_TDATA(31) <= \<const0>\;
  M1_AXIS_TDATA(30) <= \<const0>\;
  M1_AXIS_TDATA(29) <= \<const0>\;
  M1_AXIS_TDATA(28) <= \<const0>\;
  M1_AXIS_TDATA(27) <= \<const0>\;
  M1_AXIS_TDATA(26) <= \<const0>\;
  M1_AXIS_TDATA(25) <= \<const0>\;
  M1_AXIS_TDATA(24) <= \<const0>\;
  M1_AXIS_TDATA(23) <= \<const0>\;
  M1_AXIS_TDATA(22) <= \<const0>\;
  M1_AXIS_TDATA(21) <= \<const0>\;
  M1_AXIS_TDATA(20) <= \<const0>\;
  M1_AXIS_TDATA(19) <= \<const0>\;
  M1_AXIS_TDATA(18) <= \<const0>\;
  M1_AXIS_TDATA(17) <= \<const0>\;
  M1_AXIS_TDATA(16) <= \<const0>\;
  M1_AXIS_TDATA(15) <= \<const0>\;
  M1_AXIS_TDATA(14) <= \<const0>\;
  M1_AXIS_TDATA(13) <= \<const0>\;
  M1_AXIS_TDATA(12) <= \<const0>\;
  M1_AXIS_TDATA(11) <= \<const0>\;
  M1_AXIS_TDATA(10) <= \<const0>\;
  M1_AXIS_TDATA(9) <= \<const0>\;
  M1_AXIS_TDATA(8) <= \<const0>\;
  M1_AXIS_TDATA(7) <= \<const0>\;
  M1_AXIS_TDATA(6) <= \<const0>\;
  M1_AXIS_TDATA(5) <= \<const0>\;
  M1_AXIS_TDATA(4) <= \<const0>\;
  M1_AXIS_TDATA(3) <= \<const0>\;
  M1_AXIS_TDATA(2) <= \<const0>\;
  M1_AXIS_TDATA(1) <= \<const0>\;
  M1_AXIS_TDATA(0) <= \<const0>\;
  M1_AXIS_TLAST <= \<const0>\;
  M1_AXIS_TVALID <= \<const0>\;
  M2_AXIS_TDATA(31) <= \<const0>\;
  M2_AXIS_TDATA(30) <= \<const0>\;
  M2_AXIS_TDATA(29) <= \<const0>\;
  M2_AXIS_TDATA(28) <= \<const0>\;
  M2_AXIS_TDATA(27) <= \<const0>\;
  M2_AXIS_TDATA(26) <= \<const0>\;
  M2_AXIS_TDATA(25) <= \<const0>\;
  M2_AXIS_TDATA(24) <= \<const0>\;
  M2_AXIS_TDATA(23) <= \<const0>\;
  M2_AXIS_TDATA(22) <= \<const0>\;
  M2_AXIS_TDATA(21) <= \<const0>\;
  M2_AXIS_TDATA(20) <= \<const0>\;
  M2_AXIS_TDATA(19) <= \<const0>\;
  M2_AXIS_TDATA(18) <= \<const0>\;
  M2_AXIS_TDATA(17) <= \<const0>\;
  M2_AXIS_TDATA(16) <= \<const0>\;
  M2_AXIS_TDATA(15) <= \<const0>\;
  M2_AXIS_TDATA(14) <= \<const0>\;
  M2_AXIS_TDATA(13) <= \<const0>\;
  M2_AXIS_TDATA(12) <= \<const0>\;
  M2_AXIS_TDATA(11) <= \<const0>\;
  M2_AXIS_TDATA(10) <= \<const0>\;
  M2_AXIS_TDATA(9) <= \<const0>\;
  M2_AXIS_TDATA(8) <= \<const0>\;
  M2_AXIS_TDATA(7) <= \<const0>\;
  M2_AXIS_TDATA(6) <= \<const0>\;
  M2_AXIS_TDATA(5) <= \<const0>\;
  M2_AXIS_TDATA(4) <= \<const0>\;
  M2_AXIS_TDATA(3) <= \<const0>\;
  M2_AXIS_TDATA(2) <= \<const0>\;
  M2_AXIS_TDATA(1) <= \<const0>\;
  M2_AXIS_TDATA(0) <= \<const0>\;
  M2_AXIS_TLAST <= \<const0>\;
  M2_AXIS_TVALID <= \<const0>\;
  M3_AXIS_TDATA(31) <= \<const0>\;
  M3_AXIS_TDATA(30) <= \<const0>\;
  M3_AXIS_TDATA(29) <= \<const0>\;
  M3_AXIS_TDATA(28) <= \<const0>\;
  M3_AXIS_TDATA(27) <= \<const0>\;
  M3_AXIS_TDATA(26) <= \<const0>\;
  M3_AXIS_TDATA(25) <= \<const0>\;
  M3_AXIS_TDATA(24) <= \<const0>\;
  M3_AXIS_TDATA(23) <= \<const0>\;
  M3_AXIS_TDATA(22) <= \<const0>\;
  M3_AXIS_TDATA(21) <= \<const0>\;
  M3_AXIS_TDATA(20) <= \<const0>\;
  M3_AXIS_TDATA(19) <= \<const0>\;
  M3_AXIS_TDATA(18) <= \<const0>\;
  M3_AXIS_TDATA(17) <= \<const0>\;
  M3_AXIS_TDATA(16) <= \<const0>\;
  M3_AXIS_TDATA(15) <= \<const0>\;
  M3_AXIS_TDATA(14) <= \<const0>\;
  M3_AXIS_TDATA(13) <= \<const0>\;
  M3_AXIS_TDATA(12) <= \<const0>\;
  M3_AXIS_TDATA(11) <= \<const0>\;
  M3_AXIS_TDATA(10) <= \<const0>\;
  M3_AXIS_TDATA(9) <= \<const0>\;
  M3_AXIS_TDATA(8) <= \<const0>\;
  M3_AXIS_TDATA(7) <= \<const0>\;
  M3_AXIS_TDATA(6) <= \<const0>\;
  M3_AXIS_TDATA(5) <= \<const0>\;
  M3_AXIS_TDATA(4) <= \<const0>\;
  M3_AXIS_TDATA(3) <= \<const0>\;
  M3_AXIS_TDATA(2) <= \<const0>\;
  M3_AXIS_TDATA(1) <= \<const0>\;
  M3_AXIS_TDATA(0) <= \<const0>\;
  M3_AXIS_TLAST <= \<const0>\;
  M3_AXIS_TVALID <= \<const0>\;
  M4_AXIS_TDATA(31) <= \<const0>\;
  M4_AXIS_TDATA(30) <= \<const0>\;
  M4_AXIS_TDATA(29) <= \<const0>\;
  M4_AXIS_TDATA(28) <= \<const0>\;
  M4_AXIS_TDATA(27) <= \<const0>\;
  M4_AXIS_TDATA(26) <= \<const0>\;
  M4_AXIS_TDATA(25) <= \<const0>\;
  M4_AXIS_TDATA(24) <= \<const0>\;
  M4_AXIS_TDATA(23) <= \<const0>\;
  M4_AXIS_TDATA(22) <= \<const0>\;
  M4_AXIS_TDATA(21) <= \<const0>\;
  M4_AXIS_TDATA(20) <= \<const0>\;
  M4_AXIS_TDATA(19) <= \<const0>\;
  M4_AXIS_TDATA(18) <= \<const0>\;
  M4_AXIS_TDATA(17) <= \<const0>\;
  M4_AXIS_TDATA(16) <= \<const0>\;
  M4_AXIS_TDATA(15) <= \<const0>\;
  M4_AXIS_TDATA(14) <= \<const0>\;
  M4_AXIS_TDATA(13) <= \<const0>\;
  M4_AXIS_TDATA(12) <= \<const0>\;
  M4_AXIS_TDATA(11) <= \<const0>\;
  M4_AXIS_TDATA(10) <= \<const0>\;
  M4_AXIS_TDATA(9) <= \<const0>\;
  M4_AXIS_TDATA(8) <= \<const0>\;
  M4_AXIS_TDATA(7) <= \<const0>\;
  M4_AXIS_TDATA(6) <= \<const0>\;
  M4_AXIS_TDATA(5) <= \<const0>\;
  M4_AXIS_TDATA(4) <= \<const0>\;
  M4_AXIS_TDATA(3) <= \<const0>\;
  M4_AXIS_TDATA(2) <= \<const0>\;
  M4_AXIS_TDATA(1) <= \<const0>\;
  M4_AXIS_TDATA(0) <= \<const0>\;
  M4_AXIS_TLAST <= \<const0>\;
  M4_AXIS_TVALID <= \<const0>\;
  M5_AXIS_TDATA(31) <= \<const0>\;
  M5_AXIS_TDATA(30) <= \<const0>\;
  M5_AXIS_TDATA(29) <= \<const0>\;
  M5_AXIS_TDATA(28) <= \<const0>\;
  M5_AXIS_TDATA(27) <= \<const0>\;
  M5_AXIS_TDATA(26) <= \<const0>\;
  M5_AXIS_TDATA(25) <= \<const0>\;
  M5_AXIS_TDATA(24) <= \<const0>\;
  M5_AXIS_TDATA(23) <= \<const0>\;
  M5_AXIS_TDATA(22) <= \<const0>\;
  M5_AXIS_TDATA(21) <= \<const0>\;
  M5_AXIS_TDATA(20) <= \<const0>\;
  M5_AXIS_TDATA(19) <= \<const0>\;
  M5_AXIS_TDATA(18) <= \<const0>\;
  M5_AXIS_TDATA(17) <= \<const0>\;
  M5_AXIS_TDATA(16) <= \<const0>\;
  M5_AXIS_TDATA(15) <= \<const0>\;
  M5_AXIS_TDATA(14) <= \<const0>\;
  M5_AXIS_TDATA(13) <= \<const0>\;
  M5_AXIS_TDATA(12) <= \<const0>\;
  M5_AXIS_TDATA(11) <= \<const0>\;
  M5_AXIS_TDATA(10) <= \<const0>\;
  M5_AXIS_TDATA(9) <= \<const0>\;
  M5_AXIS_TDATA(8) <= \<const0>\;
  M5_AXIS_TDATA(7) <= \<const0>\;
  M5_AXIS_TDATA(6) <= \<const0>\;
  M5_AXIS_TDATA(5) <= \<const0>\;
  M5_AXIS_TDATA(4) <= \<const0>\;
  M5_AXIS_TDATA(3) <= \<const0>\;
  M5_AXIS_TDATA(2) <= \<const0>\;
  M5_AXIS_TDATA(1) <= \<const0>\;
  M5_AXIS_TDATA(0) <= \<const0>\;
  M5_AXIS_TLAST <= \<const0>\;
  M5_AXIS_TVALID <= \<const0>\;
  M6_AXIS_TDATA(31) <= \<const0>\;
  M6_AXIS_TDATA(30) <= \<const0>\;
  M6_AXIS_TDATA(29) <= \<const0>\;
  M6_AXIS_TDATA(28) <= \<const0>\;
  M6_AXIS_TDATA(27) <= \<const0>\;
  M6_AXIS_TDATA(26) <= \<const0>\;
  M6_AXIS_TDATA(25) <= \<const0>\;
  M6_AXIS_TDATA(24) <= \<const0>\;
  M6_AXIS_TDATA(23) <= \<const0>\;
  M6_AXIS_TDATA(22) <= \<const0>\;
  M6_AXIS_TDATA(21) <= \<const0>\;
  M6_AXIS_TDATA(20) <= \<const0>\;
  M6_AXIS_TDATA(19) <= \<const0>\;
  M6_AXIS_TDATA(18) <= \<const0>\;
  M6_AXIS_TDATA(17) <= \<const0>\;
  M6_AXIS_TDATA(16) <= \<const0>\;
  M6_AXIS_TDATA(15) <= \<const0>\;
  M6_AXIS_TDATA(14) <= \<const0>\;
  M6_AXIS_TDATA(13) <= \<const0>\;
  M6_AXIS_TDATA(12) <= \<const0>\;
  M6_AXIS_TDATA(11) <= \<const0>\;
  M6_AXIS_TDATA(10) <= \<const0>\;
  M6_AXIS_TDATA(9) <= \<const0>\;
  M6_AXIS_TDATA(8) <= \<const0>\;
  M6_AXIS_TDATA(7) <= \<const0>\;
  M6_AXIS_TDATA(6) <= \<const0>\;
  M6_AXIS_TDATA(5) <= \<const0>\;
  M6_AXIS_TDATA(4) <= \<const0>\;
  M6_AXIS_TDATA(3) <= \<const0>\;
  M6_AXIS_TDATA(2) <= \<const0>\;
  M6_AXIS_TDATA(1) <= \<const0>\;
  M6_AXIS_TDATA(0) <= \<const0>\;
  M6_AXIS_TLAST <= \<const0>\;
  M6_AXIS_TVALID <= \<const0>\;
  M7_AXIS_TDATA(31) <= \<const0>\;
  M7_AXIS_TDATA(30) <= \<const0>\;
  M7_AXIS_TDATA(29) <= \<const0>\;
  M7_AXIS_TDATA(28) <= \<const0>\;
  M7_AXIS_TDATA(27) <= \<const0>\;
  M7_AXIS_TDATA(26) <= \<const0>\;
  M7_AXIS_TDATA(25) <= \<const0>\;
  M7_AXIS_TDATA(24) <= \<const0>\;
  M7_AXIS_TDATA(23) <= \<const0>\;
  M7_AXIS_TDATA(22) <= \<const0>\;
  M7_AXIS_TDATA(21) <= \<const0>\;
  M7_AXIS_TDATA(20) <= \<const0>\;
  M7_AXIS_TDATA(19) <= \<const0>\;
  M7_AXIS_TDATA(18) <= \<const0>\;
  M7_AXIS_TDATA(17) <= \<const0>\;
  M7_AXIS_TDATA(16) <= \<const0>\;
  M7_AXIS_TDATA(15) <= \<const0>\;
  M7_AXIS_TDATA(14) <= \<const0>\;
  M7_AXIS_TDATA(13) <= \<const0>\;
  M7_AXIS_TDATA(12) <= \<const0>\;
  M7_AXIS_TDATA(11) <= \<const0>\;
  M7_AXIS_TDATA(10) <= \<const0>\;
  M7_AXIS_TDATA(9) <= \<const0>\;
  M7_AXIS_TDATA(8) <= \<const0>\;
  M7_AXIS_TDATA(7) <= \<const0>\;
  M7_AXIS_TDATA(6) <= \<const0>\;
  M7_AXIS_TDATA(5) <= \<const0>\;
  M7_AXIS_TDATA(4) <= \<const0>\;
  M7_AXIS_TDATA(3) <= \<const0>\;
  M7_AXIS_TDATA(2) <= \<const0>\;
  M7_AXIS_TDATA(1) <= \<const0>\;
  M7_AXIS_TDATA(0) <= \<const0>\;
  M7_AXIS_TLAST <= \<const0>\;
  M7_AXIS_TVALID <= \<const0>\;
  M8_AXIS_TDATA(31) <= \<const0>\;
  M8_AXIS_TDATA(30) <= \<const0>\;
  M8_AXIS_TDATA(29) <= \<const0>\;
  M8_AXIS_TDATA(28) <= \<const0>\;
  M8_AXIS_TDATA(27) <= \<const0>\;
  M8_AXIS_TDATA(26) <= \<const0>\;
  M8_AXIS_TDATA(25) <= \<const0>\;
  M8_AXIS_TDATA(24) <= \<const0>\;
  M8_AXIS_TDATA(23) <= \<const0>\;
  M8_AXIS_TDATA(22) <= \<const0>\;
  M8_AXIS_TDATA(21) <= \<const0>\;
  M8_AXIS_TDATA(20) <= \<const0>\;
  M8_AXIS_TDATA(19) <= \<const0>\;
  M8_AXIS_TDATA(18) <= \<const0>\;
  M8_AXIS_TDATA(17) <= \<const0>\;
  M8_AXIS_TDATA(16) <= \<const0>\;
  M8_AXIS_TDATA(15) <= \<const0>\;
  M8_AXIS_TDATA(14) <= \<const0>\;
  M8_AXIS_TDATA(13) <= \<const0>\;
  M8_AXIS_TDATA(12) <= \<const0>\;
  M8_AXIS_TDATA(11) <= \<const0>\;
  M8_AXIS_TDATA(10) <= \<const0>\;
  M8_AXIS_TDATA(9) <= \<const0>\;
  M8_AXIS_TDATA(8) <= \<const0>\;
  M8_AXIS_TDATA(7) <= \<const0>\;
  M8_AXIS_TDATA(6) <= \<const0>\;
  M8_AXIS_TDATA(5) <= \<const0>\;
  M8_AXIS_TDATA(4) <= \<const0>\;
  M8_AXIS_TDATA(3) <= \<const0>\;
  M8_AXIS_TDATA(2) <= \<const0>\;
  M8_AXIS_TDATA(1) <= \<const0>\;
  M8_AXIS_TDATA(0) <= \<const0>\;
  M8_AXIS_TLAST <= \<const0>\;
  M8_AXIS_TVALID <= \<const0>\;
  M9_AXIS_TDATA(31) <= \<const0>\;
  M9_AXIS_TDATA(30) <= \<const0>\;
  M9_AXIS_TDATA(29) <= \<const0>\;
  M9_AXIS_TDATA(28) <= \<const0>\;
  M9_AXIS_TDATA(27) <= \<const0>\;
  M9_AXIS_TDATA(26) <= \<const0>\;
  M9_AXIS_TDATA(25) <= \<const0>\;
  M9_AXIS_TDATA(24) <= \<const0>\;
  M9_AXIS_TDATA(23) <= \<const0>\;
  M9_AXIS_TDATA(22) <= \<const0>\;
  M9_AXIS_TDATA(21) <= \<const0>\;
  M9_AXIS_TDATA(20) <= \<const0>\;
  M9_AXIS_TDATA(19) <= \<const0>\;
  M9_AXIS_TDATA(18) <= \<const0>\;
  M9_AXIS_TDATA(17) <= \<const0>\;
  M9_AXIS_TDATA(16) <= \<const0>\;
  M9_AXIS_TDATA(15) <= \<const0>\;
  M9_AXIS_TDATA(14) <= \<const0>\;
  M9_AXIS_TDATA(13) <= \<const0>\;
  M9_AXIS_TDATA(12) <= \<const0>\;
  M9_AXIS_TDATA(11) <= \<const0>\;
  M9_AXIS_TDATA(10) <= \<const0>\;
  M9_AXIS_TDATA(9) <= \<const0>\;
  M9_AXIS_TDATA(8) <= \<const0>\;
  M9_AXIS_TDATA(7) <= \<const0>\;
  M9_AXIS_TDATA(6) <= \<const0>\;
  M9_AXIS_TDATA(5) <= \<const0>\;
  M9_AXIS_TDATA(4) <= \<const0>\;
  M9_AXIS_TDATA(3) <= \<const0>\;
  M9_AXIS_TDATA(2) <= \<const0>\;
  M9_AXIS_TDATA(1) <= \<const0>\;
  M9_AXIS_TDATA(0) <= \<const0>\;
  M9_AXIS_TLAST <= \<const0>\;
  M9_AXIS_TVALID <= \<const0>\;
  MB_Error <= \<const0>\;
  MB_Halted <= \^lockstep_master_out\(10);
  M_AXI_DC_ACREADY <= \<const0>\;
  M_AXI_DC_ARADDR(31) <= \<const0>\;
  M_AXI_DC_ARADDR(30) <= \<const0>\;
  M_AXI_DC_ARADDR(29) <= \<const0>\;
  M_AXI_DC_ARADDR(28) <= \<const0>\;
  M_AXI_DC_ARADDR(27) <= \<const0>\;
  M_AXI_DC_ARADDR(26) <= \<const0>\;
  M_AXI_DC_ARADDR(25) <= \<const0>\;
  M_AXI_DC_ARADDR(24) <= \<const0>\;
  M_AXI_DC_ARADDR(23) <= \<const0>\;
  M_AXI_DC_ARADDR(22) <= \<const0>\;
  M_AXI_DC_ARADDR(21) <= \<const0>\;
  M_AXI_DC_ARADDR(20) <= \<const0>\;
  M_AXI_DC_ARADDR(19) <= \<const0>\;
  M_AXI_DC_ARADDR(18) <= \<const0>\;
  M_AXI_DC_ARADDR(17) <= \<const0>\;
  M_AXI_DC_ARADDR(16) <= \<const0>\;
  M_AXI_DC_ARADDR(15) <= \<const0>\;
  M_AXI_DC_ARADDR(14) <= \<const0>\;
  M_AXI_DC_ARADDR(13) <= \<const0>\;
  M_AXI_DC_ARADDR(12) <= \<const0>\;
  M_AXI_DC_ARADDR(11) <= \<const0>\;
  M_AXI_DC_ARADDR(10) <= \<const0>\;
  M_AXI_DC_ARADDR(9) <= \<const0>\;
  M_AXI_DC_ARADDR(8) <= \<const0>\;
  M_AXI_DC_ARADDR(7) <= \<const0>\;
  M_AXI_DC_ARADDR(6) <= \<const0>\;
  M_AXI_DC_ARADDR(5) <= \<const0>\;
  M_AXI_DC_ARADDR(4) <= \<const0>\;
  M_AXI_DC_ARADDR(3) <= \<const0>\;
  M_AXI_DC_ARADDR(2) <= \<const0>\;
  M_AXI_DC_ARADDR(1) <= \<const0>\;
  M_AXI_DC_ARADDR(0) <= \<const0>\;
  M_AXI_DC_ARBAR(1) <= \<const0>\;
  M_AXI_DC_ARBAR(0) <= \<const0>\;
  M_AXI_DC_ARBURST(1) <= \<const0>\;
  M_AXI_DC_ARBURST(0) <= \<const0>\;
  M_AXI_DC_ARCACHE(3) <= \<const0>\;
  M_AXI_DC_ARCACHE(2) <= \<const0>\;
  M_AXI_DC_ARCACHE(1) <= \<const0>\;
  M_AXI_DC_ARCACHE(0) <= \<const0>\;
  M_AXI_DC_ARDOMAIN(1) <= \<const0>\;
  M_AXI_DC_ARDOMAIN(0) <= \<const0>\;
  M_AXI_DC_ARID(0) <= \<const0>\;
  M_AXI_DC_ARLEN(7) <= \<const0>\;
  M_AXI_DC_ARLEN(6) <= \<const0>\;
  M_AXI_DC_ARLEN(5) <= \<const0>\;
  M_AXI_DC_ARLEN(4) <= \<const0>\;
  M_AXI_DC_ARLEN(3) <= \<const0>\;
  M_AXI_DC_ARLEN(2) <= \<const0>\;
  M_AXI_DC_ARLEN(1) <= \<const0>\;
  M_AXI_DC_ARLEN(0) <= \<const0>\;
  M_AXI_DC_ARLOCK <= \<const0>\;
  M_AXI_DC_ARPROT(2) <= \<const0>\;
  M_AXI_DC_ARPROT(1) <= \<const0>\;
  M_AXI_DC_ARPROT(0) <= \<const0>\;
  M_AXI_DC_ARQOS(3) <= \<const0>\;
  M_AXI_DC_ARQOS(2) <= \<const0>\;
  M_AXI_DC_ARQOS(1) <= \<const0>\;
  M_AXI_DC_ARQOS(0) <= \<const0>\;
  M_AXI_DC_ARSIZE(2) <= \<const0>\;
  M_AXI_DC_ARSIZE(1) <= \<const0>\;
  M_AXI_DC_ARSIZE(0) <= \<const0>\;
  M_AXI_DC_ARSNOOP(3) <= \<const0>\;
  M_AXI_DC_ARSNOOP(2) <= \<const0>\;
  M_AXI_DC_ARSNOOP(1) <= \<const0>\;
  M_AXI_DC_ARSNOOP(0) <= \<const0>\;
  M_AXI_DC_ARUSER(4) <= \<const0>\;
  M_AXI_DC_ARUSER(3) <= \<const0>\;
  M_AXI_DC_ARUSER(2) <= \<const0>\;
  M_AXI_DC_ARUSER(1) <= \<const0>\;
  M_AXI_DC_ARUSER(0) <= \<const0>\;
  M_AXI_DC_ARVALID <= \<const0>\;
  M_AXI_DC_AWADDR(31) <= \<const0>\;
  M_AXI_DC_AWADDR(30) <= \<const0>\;
  M_AXI_DC_AWADDR(29) <= \<const0>\;
  M_AXI_DC_AWADDR(28) <= \<const0>\;
  M_AXI_DC_AWADDR(27) <= \<const0>\;
  M_AXI_DC_AWADDR(26) <= \<const0>\;
  M_AXI_DC_AWADDR(25) <= \<const0>\;
  M_AXI_DC_AWADDR(24) <= \<const0>\;
  M_AXI_DC_AWADDR(23) <= \<const0>\;
  M_AXI_DC_AWADDR(22) <= \<const0>\;
  M_AXI_DC_AWADDR(21) <= \<const0>\;
  M_AXI_DC_AWADDR(20) <= \<const0>\;
  M_AXI_DC_AWADDR(19) <= \<const0>\;
  M_AXI_DC_AWADDR(18) <= \<const0>\;
  M_AXI_DC_AWADDR(17) <= \<const0>\;
  M_AXI_DC_AWADDR(16) <= \<const0>\;
  M_AXI_DC_AWADDR(15) <= \<const0>\;
  M_AXI_DC_AWADDR(14) <= \<const0>\;
  M_AXI_DC_AWADDR(13) <= \<const0>\;
  M_AXI_DC_AWADDR(12) <= \<const0>\;
  M_AXI_DC_AWADDR(11) <= \<const0>\;
  M_AXI_DC_AWADDR(10) <= \<const0>\;
  M_AXI_DC_AWADDR(9) <= \<const0>\;
  M_AXI_DC_AWADDR(8) <= \<const0>\;
  M_AXI_DC_AWADDR(7) <= \<const0>\;
  M_AXI_DC_AWADDR(6) <= \<const0>\;
  M_AXI_DC_AWADDR(5) <= \<const0>\;
  M_AXI_DC_AWADDR(4) <= \<const0>\;
  M_AXI_DC_AWADDR(3) <= \<const0>\;
  M_AXI_DC_AWADDR(2) <= \<const0>\;
  M_AXI_DC_AWADDR(1) <= \<const0>\;
  M_AXI_DC_AWADDR(0) <= \<const0>\;
  M_AXI_DC_AWBAR(1) <= \<const0>\;
  M_AXI_DC_AWBAR(0) <= \<const0>\;
  M_AXI_DC_AWBURST(1) <= \<const0>\;
  M_AXI_DC_AWBURST(0) <= \<const0>\;
  M_AXI_DC_AWCACHE(3) <= \<const0>\;
  M_AXI_DC_AWCACHE(2) <= \<const0>\;
  M_AXI_DC_AWCACHE(1) <= \<const0>\;
  M_AXI_DC_AWCACHE(0) <= \<const0>\;
  M_AXI_DC_AWDOMAIN(1) <= \<const0>\;
  M_AXI_DC_AWDOMAIN(0) <= \<const0>\;
  M_AXI_DC_AWID(0) <= \<const0>\;
  M_AXI_DC_AWLEN(7) <= \<const0>\;
  M_AXI_DC_AWLEN(6) <= \<const0>\;
  M_AXI_DC_AWLEN(5) <= \<const0>\;
  M_AXI_DC_AWLEN(4) <= \<const0>\;
  M_AXI_DC_AWLEN(3) <= \<const0>\;
  M_AXI_DC_AWLEN(2) <= \<const0>\;
  M_AXI_DC_AWLEN(1) <= \<const0>\;
  M_AXI_DC_AWLEN(0) <= \<const0>\;
  M_AXI_DC_AWLOCK <= \<const0>\;
  M_AXI_DC_AWPROT(2) <= \<const0>\;
  M_AXI_DC_AWPROT(1) <= \<const0>\;
  M_AXI_DC_AWPROT(0) <= \<const0>\;
  M_AXI_DC_AWQOS(3) <= \<const0>\;
  M_AXI_DC_AWQOS(2) <= \<const0>\;
  M_AXI_DC_AWQOS(1) <= \<const0>\;
  M_AXI_DC_AWQOS(0) <= \<const0>\;
  M_AXI_DC_AWSIZE(2) <= \<const0>\;
  M_AXI_DC_AWSIZE(1) <= \<const0>\;
  M_AXI_DC_AWSIZE(0) <= \<const0>\;
  M_AXI_DC_AWSNOOP(2) <= \<const0>\;
  M_AXI_DC_AWSNOOP(1) <= \<const0>\;
  M_AXI_DC_AWSNOOP(0) <= \<const0>\;
  M_AXI_DC_AWUSER(4) <= \<const0>\;
  M_AXI_DC_AWUSER(3) <= \<const0>\;
  M_AXI_DC_AWUSER(2) <= \<const0>\;
  M_AXI_DC_AWUSER(1) <= \<const0>\;
  M_AXI_DC_AWUSER(0) <= \<const0>\;
  M_AXI_DC_AWVALID <= \<const0>\;
  M_AXI_DC_BREADY <= \<const0>\;
  M_AXI_DC_CDDATA(31) <= \<const0>\;
  M_AXI_DC_CDDATA(30) <= \<const0>\;
  M_AXI_DC_CDDATA(29) <= \<const0>\;
  M_AXI_DC_CDDATA(28) <= \<const0>\;
  M_AXI_DC_CDDATA(27) <= \<const0>\;
  M_AXI_DC_CDDATA(26) <= \<const0>\;
  M_AXI_DC_CDDATA(25) <= \<const0>\;
  M_AXI_DC_CDDATA(24) <= \<const0>\;
  M_AXI_DC_CDDATA(23) <= \<const0>\;
  M_AXI_DC_CDDATA(22) <= \<const0>\;
  M_AXI_DC_CDDATA(21) <= \<const0>\;
  M_AXI_DC_CDDATA(20) <= \<const0>\;
  M_AXI_DC_CDDATA(19) <= \<const0>\;
  M_AXI_DC_CDDATA(18) <= \<const0>\;
  M_AXI_DC_CDDATA(17) <= \<const0>\;
  M_AXI_DC_CDDATA(16) <= \<const0>\;
  M_AXI_DC_CDDATA(15) <= \<const0>\;
  M_AXI_DC_CDDATA(14) <= \<const0>\;
  M_AXI_DC_CDDATA(13) <= \<const0>\;
  M_AXI_DC_CDDATA(12) <= \<const0>\;
  M_AXI_DC_CDDATA(11) <= \<const0>\;
  M_AXI_DC_CDDATA(10) <= \<const0>\;
  M_AXI_DC_CDDATA(9) <= \<const0>\;
  M_AXI_DC_CDDATA(8) <= \<const0>\;
  M_AXI_DC_CDDATA(7) <= \<const0>\;
  M_AXI_DC_CDDATA(6) <= \<const0>\;
  M_AXI_DC_CDDATA(5) <= \<const0>\;
  M_AXI_DC_CDDATA(4) <= \<const0>\;
  M_AXI_DC_CDDATA(3) <= \<const0>\;
  M_AXI_DC_CDDATA(2) <= \<const0>\;
  M_AXI_DC_CDDATA(1) <= \<const0>\;
  M_AXI_DC_CDDATA(0) <= \<const0>\;
  M_AXI_DC_CDLAST <= \<const0>\;
  M_AXI_DC_CDVALID <= \<const0>\;
  M_AXI_DC_CRRESP(4) <= \<const0>\;
  M_AXI_DC_CRRESP(3) <= \<const0>\;
  M_AXI_DC_CRRESP(2) <= \<const0>\;
  M_AXI_DC_CRRESP(1) <= \<const0>\;
  M_AXI_DC_CRRESP(0) <= \<const0>\;
  M_AXI_DC_CRVALID <= \<const0>\;
  M_AXI_DC_RACK <= \<const0>\;
  M_AXI_DC_RREADY <= \<const0>\;
  M_AXI_DC_WACK <= \<const0>\;
  M_AXI_DC_WDATA(31) <= \<const0>\;
  M_AXI_DC_WDATA(30) <= \<const0>\;
  M_AXI_DC_WDATA(29) <= \<const0>\;
  M_AXI_DC_WDATA(28) <= \<const0>\;
  M_AXI_DC_WDATA(27) <= \<const0>\;
  M_AXI_DC_WDATA(26) <= \<const0>\;
  M_AXI_DC_WDATA(25) <= \<const0>\;
  M_AXI_DC_WDATA(24) <= \<const0>\;
  M_AXI_DC_WDATA(23) <= \<const0>\;
  M_AXI_DC_WDATA(22) <= \<const0>\;
  M_AXI_DC_WDATA(21) <= \<const0>\;
  M_AXI_DC_WDATA(20) <= \<const0>\;
  M_AXI_DC_WDATA(19) <= \<const0>\;
  M_AXI_DC_WDATA(18) <= \<const0>\;
  M_AXI_DC_WDATA(17) <= \<const0>\;
  M_AXI_DC_WDATA(16) <= \<const0>\;
  M_AXI_DC_WDATA(15) <= \<const0>\;
  M_AXI_DC_WDATA(14) <= \<const0>\;
  M_AXI_DC_WDATA(13) <= \<const0>\;
  M_AXI_DC_WDATA(12) <= \<const0>\;
  M_AXI_DC_WDATA(11) <= \<const0>\;
  M_AXI_DC_WDATA(10) <= \<const0>\;
  M_AXI_DC_WDATA(9) <= \<const0>\;
  M_AXI_DC_WDATA(8) <= \<const0>\;
  M_AXI_DC_WDATA(7) <= \<const0>\;
  M_AXI_DC_WDATA(6) <= \<const0>\;
  M_AXI_DC_WDATA(5) <= \<const0>\;
  M_AXI_DC_WDATA(4) <= \<const0>\;
  M_AXI_DC_WDATA(3) <= \<const0>\;
  M_AXI_DC_WDATA(2) <= \<const0>\;
  M_AXI_DC_WDATA(1) <= \<const0>\;
  M_AXI_DC_WDATA(0) <= \<const0>\;
  M_AXI_DC_WLAST <= \<const0>\;
  M_AXI_DC_WSTRB(3) <= \<const0>\;
  M_AXI_DC_WSTRB(2) <= \<const0>\;
  M_AXI_DC_WSTRB(1) <= \<const0>\;
  M_AXI_DC_WSTRB(0) <= \<const0>\;
  M_AXI_DC_WUSER(0) <= \<const0>\;
  M_AXI_DC_WVALID <= \<const0>\;
  M_AXI_DP_ARADDR(31 downto 0) <= \^m_axi_dp_araddr\(31 downto 0);
  M_AXI_DP_ARBURST(1) <= \<const0>\;
  M_AXI_DP_ARBURST(0) <= \<const1>\;
  M_AXI_DP_ARCACHE(3) <= \<const0>\;
  M_AXI_DP_ARCACHE(2) <= \<const0>\;
  M_AXI_DP_ARCACHE(1) <= \<const1>\;
  M_AXI_DP_ARCACHE(0) <= \<const1>\;
  M_AXI_DP_ARID(0) <= \<const0>\;
  M_AXI_DP_ARLEN(7) <= \<const0>\;
  M_AXI_DP_ARLEN(6) <= \<const0>\;
  M_AXI_DP_ARLEN(5) <= \<const0>\;
  M_AXI_DP_ARLEN(4) <= \<const0>\;
  M_AXI_DP_ARLEN(3) <= \<const0>\;
  M_AXI_DP_ARLEN(2) <= \<const0>\;
  M_AXI_DP_ARLEN(1) <= \<const0>\;
  M_AXI_DP_ARLEN(0) <= \<const0>\;
  M_AXI_DP_ARLOCK <= \<const0>\;
  M_AXI_DP_ARPROT(2) <= \<const0>\;
  M_AXI_DP_ARPROT(1) <= \<const0>\;
  M_AXI_DP_ARPROT(0) <= \<const0>\;
  M_AXI_DP_ARQOS(3) <= \<const1>\;
  M_AXI_DP_ARQOS(2) <= \<const0>\;
  M_AXI_DP_ARQOS(1) <= \<const0>\;
  M_AXI_DP_ARQOS(0) <= \<const0>\;
  M_AXI_DP_ARSIZE(2) <= \<const0>\;
  M_AXI_DP_ARSIZE(1) <= \<const1>\;
  M_AXI_DP_ARSIZE(0) <= \<const0>\;
  M_AXI_DP_ARVALID <= \^m_axi_dp_arvalid\;
  M_AXI_DP_AWADDR(31 downto 0) <= \^m_axi_dp_araddr\(31 downto 0);
  M_AXI_DP_AWBURST(1) <= \<const0>\;
  M_AXI_DP_AWBURST(0) <= \<const1>\;
  M_AXI_DP_AWCACHE(3) <= \<const0>\;
  M_AXI_DP_AWCACHE(2) <= \<const0>\;
  M_AXI_DP_AWCACHE(1) <= \<const1>\;
  M_AXI_DP_AWCACHE(0) <= \<const1>\;
  M_AXI_DP_AWID(0) <= \<const0>\;
  M_AXI_DP_AWLEN(7) <= \<const0>\;
  M_AXI_DP_AWLEN(6) <= \<const0>\;
  M_AXI_DP_AWLEN(5) <= \<const0>\;
  M_AXI_DP_AWLEN(4) <= \<const0>\;
  M_AXI_DP_AWLEN(3) <= \<const0>\;
  M_AXI_DP_AWLEN(2) <= \<const0>\;
  M_AXI_DP_AWLEN(1) <= \<const0>\;
  M_AXI_DP_AWLEN(0) <= \<const0>\;
  M_AXI_DP_AWLOCK <= \<const0>\;
  M_AXI_DP_AWPROT(2) <= \<const0>\;
  M_AXI_DP_AWPROT(1) <= \<const0>\;
  M_AXI_DP_AWPROT(0) <= \<const0>\;
  M_AXI_DP_AWQOS(3) <= \<const1>\;
  M_AXI_DP_AWQOS(2) <= \<const0>\;
  M_AXI_DP_AWQOS(1) <= \<const0>\;
  M_AXI_DP_AWQOS(0) <= \<const0>\;
  M_AXI_DP_AWSIZE(2) <= \<const0>\;
  M_AXI_DP_AWSIZE(1) <= \<const1>\;
  M_AXI_DP_AWSIZE(0) <= \<const0>\;
  M_AXI_DP_AWVALID <= \^m_axi_dp_awvalid\;
  M_AXI_DP_BREADY <= \<const1>\;
  M_AXI_DP_RREADY <= \<const1>\;
  M_AXI_DP_WDATA(31 downto 0) <= \^m_axi_dp_wdata\(31 downto 0);
  M_AXI_DP_WLAST <= \<const1>\;
  M_AXI_DP_WSTRB(3 downto 0) <= \^m_axi_dp_wstrb\(3 downto 0);
  M_AXI_DP_WVALID <= \^m_axi_dp_wvalid\;
  M_AXI_IC_ACREADY <= \<const0>\;
  M_AXI_IC_ARADDR(31) <= \<const0>\;
  M_AXI_IC_ARADDR(30) <= \<const0>\;
  M_AXI_IC_ARADDR(29) <= \<const0>\;
  M_AXI_IC_ARADDR(28) <= \<const0>\;
  M_AXI_IC_ARADDR(27) <= \<const0>\;
  M_AXI_IC_ARADDR(26) <= \<const0>\;
  M_AXI_IC_ARADDR(25) <= \<const0>\;
  M_AXI_IC_ARADDR(24) <= \<const0>\;
  M_AXI_IC_ARADDR(23) <= \<const0>\;
  M_AXI_IC_ARADDR(22) <= \<const0>\;
  M_AXI_IC_ARADDR(21) <= \<const0>\;
  M_AXI_IC_ARADDR(20) <= \<const0>\;
  M_AXI_IC_ARADDR(19) <= \<const0>\;
  M_AXI_IC_ARADDR(18) <= \<const0>\;
  M_AXI_IC_ARADDR(17) <= \<const0>\;
  M_AXI_IC_ARADDR(16) <= \<const0>\;
  M_AXI_IC_ARADDR(15) <= \<const0>\;
  M_AXI_IC_ARADDR(14) <= \<const0>\;
  M_AXI_IC_ARADDR(13) <= \<const0>\;
  M_AXI_IC_ARADDR(12) <= \<const0>\;
  M_AXI_IC_ARADDR(11) <= \<const0>\;
  M_AXI_IC_ARADDR(10) <= \<const0>\;
  M_AXI_IC_ARADDR(9) <= \<const0>\;
  M_AXI_IC_ARADDR(8) <= \<const0>\;
  M_AXI_IC_ARADDR(7) <= \<const0>\;
  M_AXI_IC_ARADDR(6) <= \<const0>\;
  M_AXI_IC_ARADDR(5) <= \<const0>\;
  M_AXI_IC_ARADDR(4) <= \<const0>\;
  M_AXI_IC_ARADDR(3) <= \<const0>\;
  M_AXI_IC_ARADDR(2) <= \<const0>\;
  M_AXI_IC_ARADDR(1) <= \<const0>\;
  M_AXI_IC_ARADDR(0) <= \<const0>\;
  M_AXI_IC_ARBAR(1) <= \<const0>\;
  M_AXI_IC_ARBAR(0) <= \<const0>\;
  M_AXI_IC_ARBURST(1) <= \<const0>\;
  M_AXI_IC_ARBURST(0) <= \<const0>\;
  M_AXI_IC_ARCACHE(3) <= \<const0>\;
  M_AXI_IC_ARCACHE(2) <= \<const0>\;
  M_AXI_IC_ARCACHE(1) <= \<const0>\;
  M_AXI_IC_ARCACHE(0) <= \<const0>\;
  M_AXI_IC_ARDOMAIN(1) <= \<const0>\;
  M_AXI_IC_ARDOMAIN(0) <= \<const0>\;
  M_AXI_IC_ARID(0) <= \<const0>\;
  M_AXI_IC_ARLEN(7) <= \<const0>\;
  M_AXI_IC_ARLEN(6) <= \<const0>\;
  M_AXI_IC_ARLEN(5) <= \<const0>\;
  M_AXI_IC_ARLEN(4) <= \<const0>\;
  M_AXI_IC_ARLEN(3) <= \<const0>\;
  M_AXI_IC_ARLEN(2) <= \<const0>\;
  M_AXI_IC_ARLEN(1) <= \<const0>\;
  M_AXI_IC_ARLEN(0) <= \<const0>\;
  M_AXI_IC_ARLOCK <= \<const0>\;
  M_AXI_IC_ARPROT(2) <= \<const0>\;
  M_AXI_IC_ARPROT(1) <= \<const0>\;
  M_AXI_IC_ARPROT(0) <= \<const0>\;
  M_AXI_IC_ARQOS(3) <= \<const0>\;
  M_AXI_IC_ARQOS(2) <= \<const0>\;
  M_AXI_IC_ARQOS(1) <= \<const0>\;
  M_AXI_IC_ARQOS(0) <= \<const0>\;
  M_AXI_IC_ARSIZE(2) <= \<const0>\;
  M_AXI_IC_ARSIZE(1) <= \<const0>\;
  M_AXI_IC_ARSIZE(0) <= \<const0>\;
  M_AXI_IC_ARSNOOP(3) <= \<const0>\;
  M_AXI_IC_ARSNOOP(2) <= \<const0>\;
  M_AXI_IC_ARSNOOP(1) <= \<const0>\;
  M_AXI_IC_ARSNOOP(0) <= \<const0>\;
  M_AXI_IC_ARUSER(4) <= \<const0>\;
  M_AXI_IC_ARUSER(3) <= \<const0>\;
  M_AXI_IC_ARUSER(2) <= \<const0>\;
  M_AXI_IC_ARUSER(1) <= \<const0>\;
  M_AXI_IC_ARUSER(0) <= \<const0>\;
  M_AXI_IC_ARVALID <= \<const0>\;
  M_AXI_IC_AWADDR(31) <= \<const0>\;
  M_AXI_IC_AWADDR(30) <= \<const0>\;
  M_AXI_IC_AWADDR(29) <= \<const0>\;
  M_AXI_IC_AWADDR(28) <= \<const0>\;
  M_AXI_IC_AWADDR(27) <= \<const0>\;
  M_AXI_IC_AWADDR(26) <= \<const0>\;
  M_AXI_IC_AWADDR(25) <= \<const0>\;
  M_AXI_IC_AWADDR(24) <= \<const0>\;
  M_AXI_IC_AWADDR(23) <= \<const0>\;
  M_AXI_IC_AWADDR(22) <= \<const0>\;
  M_AXI_IC_AWADDR(21) <= \<const0>\;
  M_AXI_IC_AWADDR(20) <= \<const0>\;
  M_AXI_IC_AWADDR(19) <= \<const0>\;
  M_AXI_IC_AWADDR(18) <= \<const0>\;
  M_AXI_IC_AWADDR(17) <= \<const0>\;
  M_AXI_IC_AWADDR(16) <= \<const0>\;
  M_AXI_IC_AWADDR(15) <= \<const0>\;
  M_AXI_IC_AWADDR(14) <= \<const0>\;
  M_AXI_IC_AWADDR(13) <= \<const0>\;
  M_AXI_IC_AWADDR(12) <= \<const0>\;
  M_AXI_IC_AWADDR(11) <= \<const0>\;
  M_AXI_IC_AWADDR(10) <= \<const0>\;
  M_AXI_IC_AWADDR(9) <= \<const0>\;
  M_AXI_IC_AWADDR(8) <= \<const0>\;
  M_AXI_IC_AWADDR(7) <= \<const0>\;
  M_AXI_IC_AWADDR(6) <= \<const0>\;
  M_AXI_IC_AWADDR(5) <= \<const0>\;
  M_AXI_IC_AWADDR(4) <= \<const0>\;
  M_AXI_IC_AWADDR(3) <= \<const0>\;
  M_AXI_IC_AWADDR(2) <= \<const0>\;
  M_AXI_IC_AWADDR(1) <= \<const0>\;
  M_AXI_IC_AWADDR(0) <= \<const0>\;
  M_AXI_IC_AWBAR(1) <= \<const0>\;
  M_AXI_IC_AWBAR(0) <= \<const0>\;
  M_AXI_IC_AWBURST(1) <= \<const0>\;
  M_AXI_IC_AWBURST(0) <= \<const0>\;
  M_AXI_IC_AWCACHE(3) <= \<const0>\;
  M_AXI_IC_AWCACHE(2) <= \<const0>\;
  M_AXI_IC_AWCACHE(1) <= \<const0>\;
  M_AXI_IC_AWCACHE(0) <= \<const0>\;
  M_AXI_IC_AWDOMAIN(1) <= \<const0>\;
  M_AXI_IC_AWDOMAIN(0) <= \<const0>\;
  M_AXI_IC_AWID(0) <= \<const0>\;
  M_AXI_IC_AWLEN(7) <= \<const0>\;
  M_AXI_IC_AWLEN(6) <= \<const0>\;
  M_AXI_IC_AWLEN(5) <= \<const0>\;
  M_AXI_IC_AWLEN(4) <= \<const0>\;
  M_AXI_IC_AWLEN(3) <= \<const0>\;
  M_AXI_IC_AWLEN(2) <= \<const0>\;
  M_AXI_IC_AWLEN(1) <= \<const0>\;
  M_AXI_IC_AWLEN(0) <= \<const0>\;
  M_AXI_IC_AWLOCK <= \<const0>\;
  M_AXI_IC_AWPROT(2) <= \<const0>\;
  M_AXI_IC_AWPROT(1) <= \<const0>\;
  M_AXI_IC_AWPROT(0) <= \<const0>\;
  M_AXI_IC_AWQOS(3) <= \<const0>\;
  M_AXI_IC_AWQOS(2) <= \<const0>\;
  M_AXI_IC_AWQOS(1) <= \<const0>\;
  M_AXI_IC_AWQOS(0) <= \<const0>\;
  M_AXI_IC_AWSIZE(2) <= \<const0>\;
  M_AXI_IC_AWSIZE(1) <= \<const0>\;
  M_AXI_IC_AWSIZE(0) <= \<const0>\;
  M_AXI_IC_AWSNOOP(2) <= \<const0>\;
  M_AXI_IC_AWSNOOP(1) <= \<const0>\;
  M_AXI_IC_AWSNOOP(0) <= \<const0>\;
  M_AXI_IC_AWUSER(4) <= \<const0>\;
  M_AXI_IC_AWUSER(3) <= \<const0>\;
  M_AXI_IC_AWUSER(2) <= \<const0>\;
  M_AXI_IC_AWUSER(1) <= \<const0>\;
  M_AXI_IC_AWUSER(0) <= \<const0>\;
  M_AXI_IC_AWVALID <= \<const0>\;
  M_AXI_IC_BREADY <= \<const0>\;
  M_AXI_IC_CDDATA(31) <= \<const0>\;
  M_AXI_IC_CDDATA(30) <= \<const0>\;
  M_AXI_IC_CDDATA(29) <= \<const0>\;
  M_AXI_IC_CDDATA(28) <= \<const0>\;
  M_AXI_IC_CDDATA(27) <= \<const0>\;
  M_AXI_IC_CDDATA(26) <= \<const0>\;
  M_AXI_IC_CDDATA(25) <= \<const0>\;
  M_AXI_IC_CDDATA(24) <= \<const0>\;
  M_AXI_IC_CDDATA(23) <= \<const0>\;
  M_AXI_IC_CDDATA(22) <= \<const0>\;
  M_AXI_IC_CDDATA(21) <= \<const0>\;
  M_AXI_IC_CDDATA(20) <= \<const0>\;
  M_AXI_IC_CDDATA(19) <= \<const0>\;
  M_AXI_IC_CDDATA(18) <= \<const0>\;
  M_AXI_IC_CDDATA(17) <= \<const0>\;
  M_AXI_IC_CDDATA(16) <= \<const0>\;
  M_AXI_IC_CDDATA(15) <= \<const0>\;
  M_AXI_IC_CDDATA(14) <= \<const0>\;
  M_AXI_IC_CDDATA(13) <= \<const0>\;
  M_AXI_IC_CDDATA(12) <= \<const0>\;
  M_AXI_IC_CDDATA(11) <= \<const0>\;
  M_AXI_IC_CDDATA(10) <= \<const0>\;
  M_AXI_IC_CDDATA(9) <= \<const0>\;
  M_AXI_IC_CDDATA(8) <= \<const0>\;
  M_AXI_IC_CDDATA(7) <= \<const0>\;
  M_AXI_IC_CDDATA(6) <= \<const0>\;
  M_AXI_IC_CDDATA(5) <= \<const0>\;
  M_AXI_IC_CDDATA(4) <= \<const0>\;
  M_AXI_IC_CDDATA(3) <= \<const0>\;
  M_AXI_IC_CDDATA(2) <= \<const0>\;
  M_AXI_IC_CDDATA(1) <= \<const0>\;
  M_AXI_IC_CDDATA(0) <= \<const0>\;
  M_AXI_IC_CDLAST <= \<const0>\;
  M_AXI_IC_CDVALID <= \<const0>\;
  M_AXI_IC_CRRESP(4) <= \<const0>\;
  M_AXI_IC_CRRESP(3) <= \<const0>\;
  M_AXI_IC_CRRESP(2) <= \<const0>\;
  M_AXI_IC_CRRESP(1) <= \<const0>\;
  M_AXI_IC_CRRESP(0) <= \<const0>\;
  M_AXI_IC_CRVALID <= \<const0>\;
  M_AXI_IC_RACK <= \<const0>\;
  M_AXI_IC_RREADY <= \<const0>\;
  M_AXI_IC_WACK <= \<const0>\;
  M_AXI_IC_WDATA(31) <= \<const0>\;
  M_AXI_IC_WDATA(30) <= \<const0>\;
  M_AXI_IC_WDATA(29) <= \<const0>\;
  M_AXI_IC_WDATA(28) <= \<const0>\;
  M_AXI_IC_WDATA(27) <= \<const0>\;
  M_AXI_IC_WDATA(26) <= \<const0>\;
  M_AXI_IC_WDATA(25) <= \<const0>\;
  M_AXI_IC_WDATA(24) <= \<const0>\;
  M_AXI_IC_WDATA(23) <= \<const0>\;
  M_AXI_IC_WDATA(22) <= \<const0>\;
  M_AXI_IC_WDATA(21) <= \<const0>\;
  M_AXI_IC_WDATA(20) <= \<const0>\;
  M_AXI_IC_WDATA(19) <= \<const0>\;
  M_AXI_IC_WDATA(18) <= \<const0>\;
  M_AXI_IC_WDATA(17) <= \<const0>\;
  M_AXI_IC_WDATA(16) <= \<const0>\;
  M_AXI_IC_WDATA(15) <= \<const0>\;
  M_AXI_IC_WDATA(14) <= \<const0>\;
  M_AXI_IC_WDATA(13) <= \<const0>\;
  M_AXI_IC_WDATA(12) <= \<const0>\;
  M_AXI_IC_WDATA(11) <= \<const0>\;
  M_AXI_IC_WDATA(10) <= \<const0>\;
  M_AXI_IC_WDATA(9) <= \<const0>\;
  M_AXI_IC_WDATA(8) <= \<const0>\;
  M_AXI_IC_WDATA(7) <= \<const0>\;
  M_AXI_IC_WDATA(6) <= \<const0>\;
  M_AXI_IC_WDATA(5) <= \<const0>\;
  M_AXI_IC_WDATA(4) <= \<const0>\;
  M_AXI_IC_WDATA(3) <= \<const0>\;
  M_AXI_IC_WDATA(2) <= \<const0>\;
  M_AXI_IC_WDATA(1) <= \<const0>\;
  M_AXI_IC_WDATA(0) <= \<const0>\;
  M_AXI_IC_WLAST <= \<const0>\;
  M_AXI_IC_WSTRB(3) <= \<const0>\;
  M_AXI_IC_WSTRB(2) <= \<const0>\;
  M_AXI_IC_WSTRB(1) <= \<const0>\;
  M_AXI_IC_WSTRB(0) <= \<const0>\;
  M_AXI_IC_WUSER(0) <= \<const0>\;
  M_AXI_IC_WVALID <= \<const0>\;
  M_AXI_IP_ARADDR(31) <= \<const0>\;
  M_AXI_IP_ARADDR(30) <= \<const0>\;
  M_AXI_IP_ARADDR(29) <= \<const0>\;
  M_AXI_IP_ARADDR(28) <= \<const0>\;
  M_AXI_IP_ARADDR(27) <= \<const0>\;
  M_AXI_IP_ARADDR(26) <= \<const0>\;
  M_AXI_IP_ARADDR(25) <= \<const0>\;
  M_AXI_IP_ARADDR(24) <= \<const0>\;
  M_AXI_IP_ARADDR(23) <= \<const0>\;
  M_AXI_IP_ARADDR(22) <= \<const0>\;
  M_AXI_IP_ARADDR(21) <= \<const0>\;
  M_AXI_IP_ARADDR(20) <= \<const0>\;
  M_AXI_IP_ARADDR(19) <= \<const0>\;
  M_AXI_IP_ARADDR(18) <= \<const0>\;
  M_AXI_IP_ARADDR(17) <= \<const0>\;
  M_AXI_IP_ARADDR(16) <= \<const0>\;
  M_AXI_IP_ARADDR(15) <= \<const0>\;
  M_AXI_IP_ARADDR(14) <= \<const0>\;
  M_AXI_IP_ARADDR(13) <= \<const0>\;
  M_AXI_IP_ARADDR(12) <= \<const0>\;
  M_AXI_IP_ARADDR(11) <= \<const0>\;
  M_AXI_IP_ARADDR(10) <= \<const0>\;
  M_AXI_IP_ARADDR(9) <= \<const0>\;
  M_AXI_IP_ARADDR(8) <= \<const0>\;
  M_AXI_IP_ARADDR(7) <= \<const0>\;
  M_AXI_IP_ARADDR(6) <= \<const0>\;
  M_AXI_IP_ARADDR(5) <= \<const0>\;
  M_AXI_IP_ARADDR(4) <= \<const0>\;
  M_AXI_IP_ARADDR(3) <= \<const0>\;
  M_AXI_IP_ARADDR(2) <= \<const0>\;
  M_AXI_IP_ARADDR(1) <= \<const0>\;
  M_AXI_IP_ARADDR(0) <= \<const0>\;
  M_AXI_IP_ARBURST(1) <= \<const0>\;
  M_AXI_IP_ARBURST(0) <= \<const0>\;
  M_AXI_IP_ARCACHE(3) <= \<const0>\;
  M_AXI_IP_ARCACHE(2) <= \<const0>\;
  M_AXI_IP_ARCACHE(1) <= \<const0>\;
  M_AXI_IP_ARCACHE(0) <= \<const0>\;
  M_AXI_IP_ARID(0) <= \<const0>\;
  M_AXI_IP_ARLEN(7) <= \<const0>\;
  M_AXI_IP_ARLEN(6) <= \<const0>\;
  M_AXI_IP_ARLEN(5) <= \<const0>\;
  M_AXI_IP_ARLEN(4) <= \<const0>\;
  M_AXI_IP_ARLEN(3) <= \<const0>\;
  M_AXI_IP_ARLEN(2) <= \<const0>\;
  M_AXI_IP_ARLEN(1) <= \<const0>\;
  M_AXI_IP_ARLEN(0) <= \<const0>\;
  M_AXI_IP_ARLOCK <= \<const0>\;
  M_AXI_IP_ARPROT(2) <= \<const0>\;
  M_AXI_IP_ARPROT(1) <= \<const0>\;
  M_AXI_IP_ARPROT(0) <= \<const0>\;
  M_AXI_IP_ARQOS(3) <= \<const0>\;
  M_AXI_IP_ARQOS(2) <= \<const0>\;
  M_AXI_IP_ARQOS(1) <= \<const0>\;
  M_AXI_IP_ARQOS(0) <= \<const0>\;
  M_AXI_IP_ARSIZE(2) <= \<const0>\;
  M_AXI_IP_ARSIZE(1) <= \<const0>\;
  M_AXI_IP_ARSIZE(0) <= \<const0>\;
  M_AXI_IP_ARVALID <= \<const0>\;
  M_AXI_IP_AWADDR(31) <= \<const0>\;
  M_AXI_IP_AWADDR(30) <= \<const0>\;
  M_AXI_IP_AWADDR(29) <= \<const0>\;
  M_AXI_IP_AWADDR(28) <= \<const0>\;
  M_AXI_IP_AWADDR(27) <= \<const0>\;
  M_AXI_IP_AWADDR(26) <= \<const0>\;
  M_AXI_IP_AWADDR(25) <= \<const0>\;
  M_AXI_IP_AWADDR(24) <= \<const0>\;
  M_AXI_IP_AWADDR(23) <= \<const0>\;
  M_AXI_IP_AWADDR(22) <= \<const0>\;
  M_AXI_IP_AWADDR(21) <= \<const0>\;
  M_AXI_IP_AWADDR(20) <= \<const0>\;
  M_AXI_IP_AWADDR(19) <= \<const0>\;
  M_AXI_IP_AWADDR(18) <= \<const0>\;
  M_AXI_IP_AWADDR(17) <= \<const0>\;
  M_AXI_IP_AWADDR(16) <= \<const0>\;
  M_AXI_IP_AWADDR(15) <= \<const0>\;
  M_AXI_IP_AWADDR(14) <= \<const0>\;
  M_AXI_IP_AWADDR(13) <= \<const0>\;
  M_AXI_IP_AWADDR(12) <= \<const0>\;
  M_AXI_IP_AWADDR(11) <= \<const0>\;
  M_AXI_IP_AWADDR(10) <= \<const0>\;
  M_AXI_IP_AWADDR(9) <= \<const0>\;
  M_AXI_IP_AWADDR(8) <= \<const0>\;
  M_AXI_IP_AWADDR(7) <= \<const0>\;
  M_AXI_IP_AWADDR(6) <= \<const0>\;
  M_AXI_IP_AWADDR(5) <= \<const0>\;
  M_AXI_IP_AWADDR(4) <= \<const0>\;
  M_AXI_IP_AWADDR(3) <= \<const0>\;
  M_AXI_IP_AWADDR(2) <= \<const0>\;
  M_AXI_IP_AWADDR(1) <= \<const0>\;
  M_AXI_IP_AWADDR(0) <= \<const0>\;
  M_AXI_IP_AWBURST(1) <= \<const0>\;
  M_AXI_IP_AWBURST(0) <= \<const0>\;
  M_AXI_IP_AWCACHE(3) <= \<const0>\;
  M_AXI_IP_AWCACHE(2) <= \<const0>\;
  M_AXI_IP_AWCACHE(1) <= \<const0>\;
  M_AXI_IP_AWCACHE(0) <= \<const0>\;
  M_AXI_IP_AWID(0) <= \<const0>\;
  M_AXI_IP_AWLEN(7) <= \<const0>\;
  M_AXI_IP_AWLEN(6) <= \<const0>\;
  M_AXI_IP_AWLEN(5) <= \<const0>\;
  M_AXI_IP_AWLEN(4) <= \<const0>\;
  M_AXI_IP_AWLEN(3) <= \<const0>\;
  M_AXI_IP_AWLEN(2) <= \<const0>\;
  M_AXI_IP_AWLEN(1) <= \<const0>\;
  M_AXI_IP_AWLEN(0) <= \<const0>\;
  M_AXI_IP_AWLOCK <= \<const0>\;
  M_AXI_IP_AWPROT(2) <= \<const0>\;
  M_AXI_IP_AWPROT(1) <= \<const0>\;
  M_AXI_IP_AWPROT(0) <= \<const0>\;
  M_AXI_IP_AWQOS(3) <= \<const0>\;
  M_AXI_IP_AWQOS(2) <= \<const0>\;
  M_AXI_IP_AWQOS(1) <= \<const0>\;
  M_AXI_IP_AWQOS(0) <= \<const0>\;
  M_AXI_IP_AWSIZE(2) <= \<const0>\;
  M_AXI_IP_AWSIZE(1) <= \<const0>\;
  M_AXI_IP_AWSIZE(0) <= \<const0>\;
  M_AXI_IP_AWVALID <= \<const0>\;
  M_AXI_IP_BREADY <= \<const0>\;
  M_AXI_IP_RREADY <= \<const0>\;
  M_AXI_IP_WDATA(31) <= \<const0>\;
  M_AXI_IP_WDATA(30) <= \<const0>\;
  M_AXI_IP_WDATA(29) <= \<const0>\;
  M_AXI_IP_WDATA(28) <= \<const0>\;
  M_AXI_IP_WDATA(27) <= \<const0>\;
  M_AXI_IP_WDATA(26) <= \<const0>\;
  M_AXI_IP_WDATA(25) <= \<const0>\;
  M_AXI_IP_WDATA(24) <= \<const0>\;
  M_AXI_IP_WDATA(23) <= \<const0>\;
  M_AXI_IP_WDATA(22) <= \<const0>\;
  M_AXI_IP_WDATA(21) <= \<const0>\;
  M_AXI_IP_WDATA(20) <= \<const0>\;
  M_AXI_IP_WDATA(19) <= \<const0>\;
  M_AXI_IP_WDATA(18) <= \<const0>\;
  M_AXI_IP_WDATA(17) <= \<const0>\;
  M_AXI_IP_WDATA(16) <= \<const0>\;
  M_AXI_IP_WDATA(15) <= \<const0>\;
  M_AXI_IP_WDATA(14) <= \<const0>\;
  M_AXI_IP_WDATA(13) <= \<const0>\;
  M_AXI_IP_WDATA(12) <= \<const0>\;
  M_AXI_IP_WDATA(11) <= \<const0>\;
  M_AXI_IP_WDATA(10) <= \<const0>\;
  M_AXI_IP_WDATA(9) <= \<const0>\;
  M_AXI_IP_WDATA(8) <= \<const0>\;
  M_AXI_IP_WDATA(7) <= \<const0>\;
  M_AXI_IP_WDATA(6) <= \<const0>\;
  M_AXI_IP_WDATA(5) <= \<const0>\;
  M_AXI_IP_WDATA(4) <= \<const0>\;
  M_AXI_IP_WDATA(3) <= \<const0>\;
  M_AXI_IP_WDATA(2) <= \<const0>\;
  M_AXI_IP_WDATA(1) <= \<const0>\;
  M_AXI_IP_WDATA(0) <= \<const0>\;
  M_AXI_IP_WLAST <= \<const0>\;
  M_AXI_IP_WSTRB(3) <= \<const0>\;
  M_AXI_IP_WSTRB(2) <= \<const0>\;
  M_AXI_IP_WSTRB(1) <= \<const0>\;
  M_AXI_IP_WSTRB(0) <= \<const0>\;
  M_AXI_IP_WVALID <= \<const0>\;
  RAM_From(255) <= \<const0>\;
  RAM_From(254) <= \<const0>\;
  RAM_From(253) <= \<const0>\;
  RAM_From(252) <= \<const0>\;
  RAM_From(251) <= \<const0>\;
  RAM_From(250) <= \<const0>\;
  RAM_From(249) <= \<const0>\;
  RAM_From(248) <= \<const0>\;
  RAM_From(247) <= \<const0>\;
  RAM_From(246) <= \<const0>\;
  RAM_From(245) <= \<const0>\;
  RAM_From(244) <= \<const0>\;
  RAM_From(243) <= \<const0>\;
  RAM_From(242) <= \<const0>\;
  RAM_From(241) <= \<const0>\;
  RAM_From(240) <= \<const0>\;
  RAM_From(239) <= \<const0>\;
  RAM_From(238) <= \<const0>\;
  RAM_From(237) <= \<const0>\;
  RAM_From(236) <= \<const0>\;
  RAM_From(235) <= \<const0>\;
  RAM_From(234) <= \<const0>\;
  RAM_From(233) <= \<const0>\;
  RAM_From(232) <= \<const0>\;
  RAM_From(231) <= \<const0>\;
  RAM_From(230) <= \<const0>\;
  RAM_From(229) <= \<const0>\;
  RAM_From(228) <= \<const0>\;
  RAM_From(227) <= \<const0>\;
  RAM_From(226) <= \<const0>\;
  RAM_From(225) <= \<const0>\;
  RAM_From(224) <= \<const0>\;
  RAM_From(223) <= \<const0>\;
  RAM_From(222) <= \<const0>\;
  RAM_From(221) <= \<const0>\;
  RAM_From(220) <= \<const0>\;
  RAM_From(219) <= \<const0>\;
  RAM_From(218) <= \<const0>\;
  RAM_From(217) <= \<const0>\;
  RAM_From(216) <= \<const0>\;
  RAM_From(215) <= \<const0>\;
  RAM_From(214) <= \<const0>\;
  RAM_From(213) <= \<const0>\;
  RAM_From(212) <= \<const0>\;
  RAM_From(211) <= \<const0>\;
  RAM_From(210) <= \<const0>\;
  RAM_From(209) <= \<const0>\;
  RAM_From(208) <= \<const0>\;
  RAM_From(207) <= \<const0>\;
  RAM_From(206) <= \<const0>\;
  RAM_From(205) <= \<const0>\;
  RAM_From(204) <= \<const0>\;
  RAM_From(203) <= \<const0>\;
  RAM_From(202) <= \<const0>\;
  RAM_From(201) <= \<const0>\;
  RAM_From(200) <= \<const0>\;
  RAM_From(199) <= \<const0>\;
  RAM_From(198) <= \<const0>\;
  RAM_From(197) <= \<const0>\;
  RAM_From(196) <= \<const0>\;
  RAM_From(195) <= \<const0>\;
  RAM_From(194) <= \<const0>\;
  RAM_From(193) <= \<const0>\;
  RAM_From(192) <= \<const0>\;
  RAM_From(191) <= \<const0>\;
  RAM_From(190) <= \<const0>\;
  RAM_From(189) <= \<const0>\;
  RAM_From(188) <= \<const0>\;
  RAM_From(187) <= \<const0>\;
  RAM_From(186) <= \<const0>\;
  RAM_From(185) <= \<const0>\;
  RAM_From(184) <= \<const0>\;
  RAM_From(183) <= \<const0>\;
  RAM_From(182) <= \<const0>\;
  RAM_From(181) <= \<const0>\;
  RAM_From(180) <= \<const0>\;
  RAM_From(179) <= \<const0>\;
  RAM_From(178) <= \<const0>\;
  RAM_From(177) <= \<const0>\;
  RAM_From(176) <= \<const0>\;
  RAM_From(175) <= \<const0>\;
  RAM_From(174) <= \<const0>\;
  RAM_From(173) <= \<const0>\;
  RAM_From(172) <= \<const0>\;
  RAM_From(171) <= \<const0>\;
  RAM_From(170) <= \<const0>\;
  RAM_From(169) <= \<const0>\;
  RAM_From(168) <= \<const0>\;
  RAM_From(167) <= \<const0>\;
  RAM_From(166) <= \<const0>\;
  RAM_From(165) <= \<const0>\;
  RAM_From(164) <= \<const0>\;
  RAM_From(163) <= \<const0>\;
  RAM_From(162) <= \<const0>\;
  RAM_From(161) <= \<const0>\;
  RAM_From(160) <= \<const0>\;
  RAM_From(159) <= \<const0>\;
  RAM_From(158) <= \<const0>\;
  RAM_From(157) <= \<const0>\;
  RAM_From(156) <= \<const0>\;
  RAM_From(155) <= \<const0>\;
  RAM_From(154) <= \<const0>\;
  RAM_From(153) <= \<const0>\;
  RAM_From(152) <= \<const0>\;
  RAM_From(151) <= \<const0>\;
  RAM_From(150) <= \<const0>\;
  RAM_From(149) <= \<const0>\;
  RAM_From(148) <= \<const0>\;
  RAM_From(147) <= \<const0>\;
  RAM_From(146) <= \<const0>\;
  RAM_From(145) <= \<const0>\;
  RAM_From(144) <= \<const0>\;
  RAM_From(143) <= \<const0>\;
  RAM_From(142) <= \<const0>\;
  RAM_From(141) <= \<const0>\;
  RAM_From(140) <= \<const0>\;
  RAM_From(139) <= \<const0>\;
  RAM_From(138) <= \<const0>\;
  RAM_From(137) <= \<const0>\;
  RAM_From(136) <= \<const0>\;
  RAM_From(135) <= \<const0>\;
  RAM_From(134) <= \<const0>\;
  RAM_From(133) <= \<const0>\;
  RAM_From(132) <= \<const0>\;
  RAM_From(131) <= \<const0>\;
  RAM_From(130) <= \<const0>\;
  RAM_From(129) <= \<const0>\;
  RAM_From(128) <= \<const0>\;
  RAM_From(127) <= \<const0>\;
  RAM_From(126) <= \<const0>\;
  RAM_From(125) <= \<const0>\;
  RAM_From(124) <= \<const0>\;
  RAM_From(123) <= \<const0>\;
  RAM_From(122) <= \<const0>\;
  RAM_From(121) <= \<const0>\;
  RAM_From(120) <= \<const0>\;
  RAM_From(119) <= \<const0>\;
  RAM_From(118) <= \<const0>\;
  RAM_From(117) <= \<const0>\;
  RAM_From(116) <= \<const0>\;
  RAM_From(115) <= \<const0>\;
  RAM_From(114) <= \<const0>\;
  RAM_From(113) <= \<const0>\;
  RAM_From(112) <= \<const0>\;
  RAM_From(111) <= \<const0>\;
  RAM_From(110) <= \<const0>\;
  RAM_From(109) <= \<const0>\;
  RAM_From(108) <= \<const0>\;
  RAM_From(107) <= \<const0>\;
  RAM_From(106) <= \<const0>\;
  RAM_From(105) <= \<const0>\;
  RAM_From(104) <= \<const0>\;
  RAM_From(103) <= \<const0>\;
  RAM_From(102) <= \<const0>\;
  RAM_From(101) <= \<const0>\;
  RAM_From(100) <= \<const0>\;
  RAM_From(99) <= \<const0>\;
  RAM_From(98) <= \<const0>\;
  RAM_From(97) <= \<const0>\;
  RAM_From(96) <= \<const0>\;
  RAM_From(95) <= \<const0>\;
  RAM_From(94) <= \<const0>\;
  RAM_From(93) <= \<const0>\;
  RAM_From(92) <= \<const0>\;
  RAM_From(91) <= \<const0>\;
  RAM_From(90) <= \<const0>\;
  RAM_From(89) <= \<const0>\;
  RAM_From(88) <= \<const0>\;
  RAM_From(87) <= \<const0>\;
  RAM_From(86) <= \<const0>\;
  RAM_From(85) <= \<const0>\;
  RAM_From(84) <= \<const0>\;
  RAM_From(83) <= \<const0>\;
  RAM_From(82) <= \<const0>\;
  RAM_From(81) <= \<const0>\;
  RAM_From(80) <= \<const0>\;
  RAM_From(79) <= \<const0>\;
  RAM_From(78) <= \<const0>\;
  RAM_From(77) <= \<const0>\;
  RAM_From(76) <= \<const0>\;
  RAM_From(75) <= \<const0>\;
  RAM_From(74) <= \<const0>\;
  RAM_From(73) <= \<const0>\;
  RAM_From(72) <= \<const0>\;
  RAM_From(71) <= \<const0>\;
  RAM_From(70) <= \<const0>\;
  RAM_From(69) <= \<const0>\;
  RAM_From(68) <= \<const0>\;
  RAM_From(67) <= \<const0>\;
  RAM_From(66) <= \<const0>\;
  RAM_From(65) <= \<const0>\;
  RAM_From(64) <= \<const0>\;
  RAM_From(63) <= \<const0>\;
  RAM_From(62) <= \<const0>\;
  RAM_From(61) <= \<const0>\;
  RAM_From(60) <= \<const0>\;
  RAM_From(59) <= \<const0>\;
  RAM_From(58) <= \<const0>\;
  RAM_From(57) <= \<const0>\;
  RAM_From(56) <= \<const0>\;
  RAM_From(55) <= \<const0>\;
  RAM_From(54) <= \<const0>\;
  RAM_From(53) <= \<const0>\;
  RAM_From(52) <= \<const0>\;
  RAM_From(51) <= \<const0>\;
  RAM_From(50) <= \<const0>\;
  RAM_From(49) <= \<const0>\;
  RAM_From(48) <= \<const0>\;
  RAM_From(47) <= \<const0>\;
  RAM_From(46) <= \<const0>\;
  RAM_From(45) <= \<const0>\;
  RAM_From(44) <= \<const0>\;
  RAM_From(43) <= \<const0>\;
  RAM_From(42) <= \<const0>\;
  RAM_From(41) <= \<const0>\;
  RAM_From(40) <= \<const0>\;
  RAM_From(39) <= \<const0>\;
  RAM_From(38) <= \<const0>\;
  RAM_From(37) <= \<const0>\;
  RAM_From(36) <= \<const0>\;
  RAM_From(35) <= \<const0>\;
  RAM_From(34) <= \<const0>\;
  RAM_From(33) <= \<const0>\;
  RAM_From(32) <= \<const0>\;
  RAM_From(31) <= \<const0>\;
  RAM_From(30) <= \<const0>\;
  RAM_From(29) <= \<const0>\;
  RAM_From(28) <= \<const0>\;
  RAM_From(27) <= \<const0>\;
  RAM_From(26) <= \<const0>\;
  RAM_From(25) <= \<const0>\;
  RAM_From(24) <= \<const0>\;
  RAM_From(23) <= \<const0>\;
  RAM_From(22) <= \<const0>\;
  RAM_From(21) <= \<const0>\;
  RAM_From(20) <= \<const0>\;
  RAM_From(19) <= \<const0>\;
  RAM_From(18) <= \<const0>\;
  RAM_From(17) <= \<const0>\;
  RAM_From(16) <= \<const0>\;
  RAM_From(15) <= \<const0>\;
  RAM_From(14) <= \<const0>\;
  RAM_From(13) <= \<const0>\;
  RAM_From(12) <= \<const0>\;
  RAM_From(11) <= \<const0>\;
  RAM_From(10) <= \<const0>\;
  RAM_From(9) <= \<const0>\;
  RAM_From(8) <= \<const0>\;
  RAM_From(7) <= \<const0>\;
  RAM_From(6) <= \<const0>\;
  RAM_From(5) <= \<const0>\;
  RAM_From(4) <= \<const0>\;
  RAM_From(3) <= \<const0>\;
  RAM_From(2) <= \<const0>\;
  RAM_From(1) <= \<const0>\;
  RAM_From(0) <= \<const0>\;
  Read_Strobe <= \^read_strobe\;
  S0_AXIS_TREADY <= \<const0>\;
  S10_AXIS_TREADY <= \<const0>\;
  S11_AXIS_TREADY <= \<const0>\;
  S12_AXIS_TREADY <= \<const0>\;
  S13_AXIS_TREADY <= \<const0>\;
  S14_AXIS_TREADY <= \<const0>\;
  S15_AXIS_TREADY <= \<const0>\;
  S1_AXIS_TREADY <= \<const0>\;
  S2_AXIS_TREADY <= \<const0>\;
  S3_AXIS_TREADY <= \<const0>\;
  S4_AXIS_TREADY <= \<const0>\;
  S5_AXIS_TREADY <= \<const0>\;
  S6_AXIS_TREADY <= \<const0>\;
  S7_AXIS_TREADY <= \<const0>\;
  S8_AXIS_TREADY <= \<const0>\;
  S9_AXIS_TREADY <= \<const0>\;
  Trace_DCache_Hit <= \<const0>\;
  Trace_DCache_Rdy <= \<const0>\;
  Trace_DCache_Read <= \<const0>\;
  Trace_DCache_Req <= \<const0>\;
  Trace_Data_Access <= \^trace_data_access\;
  Trace_Data_Address(0 to 31) <= \^trace_data_address\(0 to 31);
  Trace_Data_Byte_Enable(0 to 3) <= \^trace_data_byte_enable\(0 to 3);
  Trace_Data_Read <= \^trace_data_read\;
  Trace_Data_Write <= \^trace_data_write\;
  Trace_Data_Write_Value(0 to 31) <= \^trace_data_write_value\(0 to 31);
  Trace_Delay_Slot <= \^trace_delay_slot\;
  Trace_EX_PipeRun <= \^trace_ex_piperun\;
  Trace_Exception_Kind(0) <= \<const0>\;
  Trace_Exception_Kind(1) <= \^trace_exception_kind\(1);
  Trace_Exception_Kind(2) <= \<const0>\;
  Trace_Exception_Kind(3) <= \<const0>\;
  Trace_Exception_Kind(4) <= \^trace_exception_kind\(4);
  Trace_Exception_Taken <= \^trace_exception_taken\;
  Trace_ICache_Hit <= \<const0>\;
  Trace_ICache_Rdy <= \<const0>\;
  Trace_ICache_Req <= \<const0>\;
  Trace_Instruction(0 to 31) <= \^trace_instruction\(0 to 31);
  Trace_Jump_Hit <= \<const0>\;
  Trace_Jump_Taken <= \^trace_jump_taken\;
  Trace_MB_Halted <= \^lockstep_master_out\(10);
  Trace_MEM_PipeRun <= \^trace_mem_piperun\;
  Trace_MSR_Reg(0) <= \<const0>\;
  Trace_MSR_Reg(1) <= \<const0>\;
  Trace_MSR_Reg(2) <= \<const0>\;
  Trace_MSR_Reg(3) <= \<const0>\;
  Trace_MSR_Reg(4) <= \<const0>\;
  Trace_MSR_Reg(5) <= \<const0>\;
  Trace_MSR_Reg(6) <= \<const0>\;
  Trace_MSR_Reg(7) <= \<const0>\;
  Trace_MSR_Reg(8) <= \<const0>\;
  Trace_MSR_Reg(9) <= \<const0>\;
  Trace_MSR_Reg(10) <= \<const0>\;
  Trace_MSR_Reg(11 to 13) <= \^trace_msr_reg\(11 to 13);
  Trace_MSR_Reg(14) <= \<const0>\;
  Trace_New_Reg_Value(0 to 31) <= \^trace_new_reg_value\(0 to 31);
  Trace_OF_PipeRun <= \^trace_of_piperun\;
  Trace_PC(0 to 31) <= \^trace_pc\(0 to 31);
  Trace_PID_Reg(0) <= \<const0>\;
  Trace_PID_Reg(1) <= \<const0>\;
  Trace_PID_Reg(2) <= \<const0>\;
  Trace_PID_Reg(3) <= \<const0>\;
  Trace_PID_Reg(4) <= \<const0>\;
  Trace_PID_Reg(5) <= \<const0>\;
  Trace_PID_Reg(6) <= \<const0>\;
  Trace_PID_Reg(7) <= \<const0>\;
  Trace_Reg_Addr(0 to 4) <= \^trace_reg_addr\(0 to 4);
  Trace_Reg_Write <= \^trace_reg_write\;
  Trace_Valid_Instr <= \^trace_valid_instr\;
  Write_Strobe <= \^write_strobe\;
  \^debug_rst\ <= Debug_Rst;
Dbg_TDO_INST_0_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000040"
    )
        port map (
      I0 => MicroBlaze_Core_I_n_411,
      I1 => Dbg_Reg_En(6),
      I2 => Dbg_Reg_En(7),
      I3 => Dbg_Reg_En(4),
      I4 => Dbg_Reg_En(5),
      O => \Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Status_Reg_En\
    );
Dbg_TDO_INST_0_i_11: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => Dbg_Reg_En(7),
      I1 => Dbg_Reg_En(4),
      I2 => Dbg_Reg_En(0),
      I3 => Dbg_Reg_En(2),
      O => Dbg_TDO_INST_0_i_11_n_0
    );
Dbg_TDO_INST_0_i_14: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00004000"
    )
        port map (
      I0 => Dbg_Reg_En(1),
      I1 => Dbg_Reg_En(6),
      I2 => Dbg_Reg_En(5),
      I3 => Dbg_Reg_En(7),
      I4 => Dbg_TDO_INST_0_i_26_n_0,
      O => Config_Reg_En
    );
Dbg_TDO_INST_0_i_26: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => Dbg_Reg_En(3),
      I1 => Dbg_Reg_En(4),
      I2 => Dbg_Reg_En(0),
      I3 => Dbg_Reg_En(2),
      O => Dbg_TDO_INST_0_i_26_n_0
    );
Dbg_TDO_INST_0_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => Dbg_Reg_En(1),
      I1 => Dbg_Reg_En(3),
      I2 => Dbg_Reg_En(5),
      I3 => Dbg_Reg_En(6),
      I4 => Dbg_TDO_INST_0_i_11_n_0,
      O => Data_Read_Reg_En
    );
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
\LOCKSTEP_Out_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^lockstep_master_out\(10),
      Q => \^lockstep_out\(3228),
      R => Reset
    );
\LOCKSTEP_Out_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(6),
      Q => \^lockstep_out\(10),
      R => Reset
    );
\LOCKSTEP_Out_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(7),
      Q => \^lockstep_out\(11),
      R => Reset
    );
\LOCKSTEP_Out_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(8),
      Q => \^lockstep_out\(12),
      R => Reset
    );
\LOCKSTEP_Out_reg[132]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(0),
      Q => \^lockstep_out\(132),
      R => Reset
    );
\LOCKSTEP_Out_reg[133]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(1),
      Q => \^lockstep_out\(133),
      R => Reset
    );
\LOCKSTEP_Out_reg[134]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(2),
      Q => \^lockstep_out\(134),
      R => Reset
    );
\LOCKSTEP_Out_reg[135]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(3),
      Q => \^lockstep_out\(135),
      R => Reset
    );
\LOCKSTEP_Out_reg[136]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(4),
      Q => \^lockstep_out\(136),
      R => Reset
    );
\LOCKSTEP_Out_reg[137]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(5),
      Q => \^lockstep_out\(137),
      R => Reset
    );
\LOCKSTEP_Out_reg[138]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(6),
      Q => \^lockstep_out\(138),
      R => Reset
    );
\LOCKSTEP_Out_reg[139]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(7),
      Q => \^lockstep_out\(139),
      R => Reset
    );
\LOCKSTEP_Out_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(9),
      Q => \^lockstep_out\(13),
      R => Reset
    );
\LOCKSTEP_Out_reg[140]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(8),
      Q => \^lockstep_out\(140),
      R => Reset
    );
\LOCKSTEP_Out_reg[141]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(9),
      Q => \^lockstep_out\(141),
      R => Reset
    );
\LOCKSTEP_Out_reg[142]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(10),
      Q => \^lockstep_out\(142),
      R => Reset
    );
\LOCKSTEP_Out_reg[143]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(11),
      Q => \^lockstep_out\(143),
      R => Reset
    );
\LOCKSTEP_Out_reg[144]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(12),
      Q => \^lockstep_out\(144),
      R => Reset
    );
\LOCKSTEP_Out_reg[145]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(13),
      Q => \^lockstep_out\(145),
      R => Reset
    );
\LOCKSTEP_Out_reg[146]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(14),
      Q => \^lockstep_out\(146),
      R => Reset
    );
\LOCKSTEP_Out_reg[147]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(15),
      Q => \^lockstep_out\(147),
      R => Reset
    );
\LOCKSTEP_Out_reg[148]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(16),
      Q => \^lockstep_out\(148),
      R => Reset
    );
\LOCKSTEP_Out_reg[149]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(17),
      Q => \^lockstep_out\(149),
      R => Reset
    );
\LOCKSTEP_Out_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(10),
      Q => \^lockstep_out\(14),
      R => Reset
    );
\LOCKSTEP_Out_reg[150]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(18),
      Q => \^lockstep_out\(150),
      R => Reset
    );
\LOCKSTEP_Out_reg[151]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(19),
      Q => \^lockstep_out\(151),
      R => Reset
    );
\LOCKSTEP_Out_reg[152]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(20),
      Q => \^lockstep_out\(152),
      R => Reset
    );
\LOCKSTEP_Out_reg[153]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(21),
      Q => \^lockstep_out\(153),
      R => Reset
    );
\LOCKSTEP_Out_reg[154]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(22),
      Q => \^lockstep_out\(154),
      R => Reset
    );
\LOCKSTEP_Out_reg[155]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(23),
      Q => \^lockstep_out\(155),
      R => Reset
    );
\LOCKSTEP_Out_reg[156]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(24),
      Q => \^lockstep_out\(156),
      R => Reset
    );
\LOCKSTEP_Out_reg[157]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(25),
      Q => \^lockstep_out\(157),
      R => Reset
    );
\LOCKSTEP_Out_reg[158]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(26),
      Q => \^lockstep_out\(158),
      R => Reset
    );
\LOCKSTEP_Out_reg[159]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(27),
      Q => \^lockstep_out\(159),
      R => Reset
    );
\LOCKSTEP_Out_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(11),
      Q => \^lockstep_out\(15),
      R => Reset
    );
\LOCKSTEP_Out_reg[160]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(28),
      Q => \^lockstep_out\(160),
      R => Reset
    );
\LOCKSTEP_Out_reg[161]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(29),
      Q => \^lockstep_out\(161),
      R => Reset
    );
\LOCKSTEP_Out_reg[162]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(30),
      Q => \^lockstep_out\(162),
      R => Reset
    );
\LOCKSTEP_Out_reg[163]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_write\(31),
      Q => \^lockstep_out\(163),
      R => Reset
    );
\LOCKSTEP_Out_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(12),
      Q => \^lockstep_out\(16),
      R => Reset
    );
\LOCKSTEP_Out_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(13),
      Q => \^lockstep_out\(17),
      R => Reset
    );
\LOCKSTEP_Out_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(14),
      Q => \^lockstep_out\(18),
      R => Reset
    );
\LOCKSTEP_Out_reg[196]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^d_as\,
      Q => \^lockstep_out\(196),
      R => Reset
    );
\LOCKSTEP_Out_reg[197]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^read_strobe\,
      Q => \^lockstep_out\(197),
      R => Reset
    );
\LOCKSTEP_Out_reg[198]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^write_strobe\,
      Q => \^lockstep_out\(198),
      R => Reset
    );
\LOCKSTEP_Out_reg[199]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^byte_enable\(0),
      Q => \^lockstep_out\(199),
      R => Reset
    );
\LOCKSTEP_Out_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(15),
      Q => \^lockstep_out\(19),
      R => Reset
    );
\LOCKSTEP_Out_reg[200]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^byte_enable\(1),
      Q => \^lockstep_out\(200),
      R => Reset
    );
\LOCKSTEP_Out_reg[201]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^byte_enable\(2),
      Q => \^lockstep_out\(201),
      R => Reset
    );
\LOCKSTEP_Out_reg[202]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^byte_enable\(3),
      Q => \^lockstep_out\(202),
      R => Reset
    );
\LOCKSTEP_Out_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(16),
      Q => \^lockstep_out\(20),
      R => Reset
    );
\LOCKSTEP_Out_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(17),
      Q => \^lockstep_out\(21),
      R => Reset
    );
\LOCKSTEP_Out_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(18),
      Q => \^lockstep_out\(22),
      R => Reset
    );
\LOCKSTEP_Out_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(19),
      Q => \^lockstep_out\(23),
      R => Reset
    );
\LOCKSTEP_Out_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(20),
      Q => \^lockstep_out\(24),
      R => Reset
    );
\LOCKSTEP_Out_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(21),
      Q => \^lockstep_out\(25),
      R => Reset
    );
\LOCKSTEP_Out_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(22),
      Q => \^lockstep_out\(26),
      R => Reset
    );
\LOCKSTEP_Out_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(23),
      Q => \^lockstep_out\(27),
      R => Reset
    );
\LOCKSTEP_Out_reg[2881]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(0),
      Q => \^lockstep_out\(2881),
      R => Reset
    );
\LOCKSTEP_Out_reg[2882]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(1),
      Q => \^lockstep_out\(2882),
      R => Reset
    );
\LOCKSTEP_Out_reg[2883]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(2),
      Q => \^lockstep_out\(2883),
      R => Reset
    );
\LOCKSTEP_Out_reg[2884]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(3),
      Q => \^lockstep_out\(2884),
      R => Reset
    );
\LOCKSTEP_Out_reg[2885]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(4),
      Q => \^lockstep_out\(2885),
      R => Reset
    );
\LOCKSTEP_Out_reg[2886]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(5),
      Q => \^lockstep_out\(2886),
      R => Reset
    );
\LOCKSTEP_Out_reg[2887]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(6),
      Q => \^lockstep_out\(2887),
      R => Reset
    );
\LOCKSTEP_Out_reg[2888]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(7),
      Q => \^lockstep_out\(2888),
      R => Reset
    );
\LOCKSTEP_Out_reg[2889]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(8),
      Q => \^lockstep_out\(2889),
      R => Reset
    );
\LOCKSTEP_Out_reg[2890]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(9),
      Q => \^lockstep_out\(2890),
      R => Reset
    );
\LOCKSTEP_Out_reg[2891]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(10),
      Q => \^lockstep_out\(2891),
      R => Reset
    );
\LOCKSTEP_Out_reg[2892]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(11),
      Q => \^lockstep_out\(2892),
      R => Reset
    );
\LOCKSTEP_Out_reg[2893]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(12),
      Q => \^lockstep_out\(2893),
      R => Reset
    );
\LOCKSTEP_Out_reg[2894]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(13),
      Q => \^lockstep_out\(2894),
      R => Reset
    );
\LOCKSTEP_Out_reg[2895]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(14),
      Q => \^lockstep_out\(2895),
      R => Reset
    );
\LOCKSTEP_Out_reg[2896]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(15),
      Q => \^lockstep_out\(2896),
      R => Reset
    );
\LOCKSTEP_Out_reg[2897]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(16),
      Q => \^lockstep_out\(2897),
      R => Reset
    );
\LOCKSTEP_Out_reg[2898]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(17),
      Q => \^lockstep_out\(2898),
      R => Reset
    );
\LOCKSTEP_Out_reg[2899]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(18),
      Q => \^lockstep_out\(2899),
      R => Reset
    );
\LOCKSTEP_Out_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(24),
      Q => \^lockstep_out\(28),
      R => Reset
    );
\LOCKSTEP_Out_reg[2900]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(19),
      Q => \^lockstep_out\(2900),
      R => Reset
    );
\LOCKSTEP_Out_reg[2901]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(20),
      Q => \^lockstep_out\(2901),
      R => Reset
    );
\LOCKSTEP_Out_reg[2902]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(21),
      Q => \^lockstep_out\(2902),
      R => Reset
    );
\LOCKSTEP_Out_reg[2903]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(22),
      Q => \^lockstep_out\(2903),
      R => Reset
    );
\LOCKSTEP_Out_reg[2904]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(23),
      Q => \^lockstep_out\(2904),
      R => Reset
    );
\LOCKSTEP_Out_reg[2905]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(24),
      Q => \^lockstep_out\(2905),
      R => Reset
    );
\LOCKSTEP_Out_reg[2906]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(25),
      Q => \^lockstep_out\(2906),
      R => Reset
    );
\LOCKSTEP_Out_reg[2907]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(26),
      Q => \^lockstep_out\(2907),
      R => Reset
    );
\LOCKSTEP_Out_reg[2908]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(27),
      Q => \^lockstep_out\(2908),
      R => Reset
    );
\LOCKSTEP_Out_reg[2909]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(28),
      Q => \^lockstep_out\(2909),
      R => Reset
    );
\LOCKSTEP_Out_reg[2910]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(29),
      Q => \^lockstep_out\(2910),
      R => Reset
    );
\LOCKSTEP_Out_reg[2911]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(30),
      Q => \^lockstep_out\(2911),
      R => Reset
    );
\LOCKSTEP_Out_reg[2912]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_instruction\(31),
      Q => \^lockstep_out\(2912),
      R => Reset
    );
\LOCKSTEP_Out_reg[2913]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_valid_instr\,
      Q => \^lockstep_out\(2913),
      R => Reset
    );
\LOCKSTEP_Out_reg[2914]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(0),
      Q => \^lockstep_out\(2914),
      R => Reset
    );
\LOCKSTEP_Out_reg[2915]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(1),
      Q => \^lockstep_out\(2915),
      R => Reset
    );
\LOCKSTEP_Out_reg[2916]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(2),
      Q => \^lockstep_out\(2916),
      R => Reset
    );
\LOCKSTEP_Out_reg[2917]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(3),
      Q => \^lockstep_out\(2917),
      R => Reset
    );
\LOCKSTEP_Out_reg[2918]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(4),
      Q => \^lockstep_out\(2918),
      R => Reset
    );
\LOCKSTEP_Out_reg[2919]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(5),
      Q => \^lockstep_out\(2919),
      R => Reset
    );
\LOCKSTEP_Out_reg[2920]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(6),
      Q => \^lockstep_out\(2920),
      R => Reset
    );
\LOCKSTEP_Out_reg[2921]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(7),
      Q => \^lockstep_out\(2921),
      R => Reset
    );
\LOCKSTEP_Out_reg[2922]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(8),
      Q => \^lockstep_out\(2922),
      R => Reset
    );
\LOCKSTEP_Out_reg[2923]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(9),
      Q => \^lockstep_out\(2923),
      R => Reset
    );
\LOCKSTEP_Out_reg[2924]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(10),
      Q => \^lockstep_out\(2924),
      R => Reset
    );
\LOCKSTEP_Out_reg[2925]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(11),
      Q => \^lockstep_out\(2925),
      R => Reset
    );
\LOCKSTEP_Out_reg[2926]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(12),
      Q => \^lockstep_out\(2926),
      R => Reset
    );
\LOCKSTEP_Out_reg[2927]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(13),
      Q => \^lockstep_out\(2927),
      R => Reset
    );
\LOCKSTEP_Out_reg[2928]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(14),
      Q => \^lockstep_out\(2928),
      R => Reset
    );
\LOCKSTEP_Out_reg[2929]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(15),
      Q => \^lockstep_out\(2929),
      R => Reset
    );
\LOCKSTEP_Out_reg[2930]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(16),
      Q => \^lockstep_out\(2930),
      R => Reset
    );
\LOCKSTEP_Out_reg[2931]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(17),
      Q => \^lockstep_out\(2931),
      R => Reset
    );
\LOCKSTEP_Out_reg[2932]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(18),
      Q => \^lockstep_out\(2932),
      R => Reset
    );
\LOCKSTEP_Out_reg[2933]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(19),
      Q => \^lockstep_out\(2933),
      R => Reset
    );
\LOCKSTEP_Out_reg[2934]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(20),
      Q => \^lockstep_out\(2934),
      R => Reset
    );
\LOCKSTEP_Out_reg[2935]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(21),
      Q => \^lockstep_out\(2935),
      R => Reset
    );
\LOCKSTEP_Out_reg[2936]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(22),
      Q => \^lockstep_out\(2936),
      R => Reset
    );
\LOCKSTEP_Out_reg[2937]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(23),
      Q => \^lockstep_out\(2937),
      R => Reset
    );
\LOCKSTEP_Out_reg[2938]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(24),
      Q => \^lockstep_out\(2938),
      R => Reset
    );
\LOCKSTEP_Out_reg[2939]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(25),
      Q => \^lockstep_out\(2939),
      R => Reset
    );
\LOCKSTEP_Out_reg[2940]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(26),
      Q => \^lockstep_out\(2940),
      R => Reset
    );
\LOCKSTEP_Out_reg[2941]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(27),
      Q => \^lockstep_out\(2941),
      R => Reset
    );
\LOCKSTEP_Out_reg[2942]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(28),
      Q => \^lockstep_out\(2942),
      R => Reset
    );
\LOCKSTEP_Out_reg[2943]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(29),
      Q => \^lockstep_out\(2943),
      R => Reset
    );
\LOCKSTEP_Out_reg[2944]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(30),
      Q => \^lockstep_out\(2944),
      R => Reset
    );
\LOCKSTEP_Out_reg[2945]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_pc\(31),
      Q => \^lockstep_out\(2945),
      R => Reset
    );
\LOCKSTEP_Out_reg[2978]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_reg_write\,
      Q => \^lockstep_out\(2978),
      R => Reset
    );
\LOCKSTEP_Out_reg[2979]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_reg_addr\(0),
      Q => \^lockstep_out\(2979),
      R => Reset
    );
\LOCKSTEP_Out_reg[2980]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_reg_addr\(1),
      Q => \^lockstep_out\(2980),
      R => Reset
    );
\LOCKSTEP_Out_reg[2981]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_reg_addr\(2),
      Q => \^lockstep_out\(2981),
      R => Reset
    );
\LOCKSTEP_Out_reg[2982]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_reg_addr\(3),
      Q => \^lockstep_out\(2982),
      R => Reset
    );
\LOCKSTEP_Out_reg[2983]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_reg_addr\(4),
      Q => \^lockstep_out\(2983),
      R => Reset
    );
\LOCKSTEP_Out_reg[2995]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_msr_reg\(11),
      Q => \^lockstep_out\(2995),
      R => Reset
    );
\LOCKSTEP_Out_reg[2996]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_msr_reg\(12),
      Q => \^lockstep_out\(2996),
      R => Reset
    );
\LOCKSTEP_Out_reg[2997]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_msr_reg\(13),
      Q => \^lockstep_out\(2997),
      R => Reset
    );
\LOCKSTEP_Out_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(25),
      Q => \^lockstep_out\(29),
      R => Reset
    );
\LOCKSTEP_Out_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^ifetch\,
      Q => \^lockstep_out\(2),
      R => Reset
    );
\LOCKSTEP_Out_reg[3007]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(0),
      Q => \^lockstep_out\(3007),
      R => Reset
    );
\LOCKSTEP_Out_reg[3008]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(1),
      Q => \^lockstep_out\(3008),
      R => Reset
    );
\LOCKSTEP_Out_reg[3009]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(2),
      Q => \^lockstep_out\(3009),
      R => Reset
    );
\LOCKSTEP_Out_reg[3010]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(3),
      Q => \^lockstep_out\(3010),
      R => Reset
    );
\LOCKSTEP_Out_reg[3011]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(4),
      Q => \^lockstep_out\(3011),
      R => Reset
    );
\LOCKSTEP_Out_reg[3012]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(5),
      Q => \^lockstep_out\(3012),
      R => Reset
    );
\LOCKSTEP_Out_reg[3013]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(6),
      Q => \^lockstep_out\(3013),
      R => Reset
    );
\LOCKSTEP_Out_reg[3014]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(7),
      Q => \^lockstep_out\(3014),
      R => Reset
    );
\LOCKSTEP_Out_reg[3015]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(8),
      Q => \^lockstep_out\(3015),
      R => Reset
    );
\LOCKSTEP_Out_reg[3016]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(9),
      Q => \^lockstep_out\(3016),
      R => Reset
    );
\LOCKSTEP_Out_reg[3017]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(10),
      Q => \^lockstep_out\(3017),
      R => Reset
    );
\LOCKSTEP_Out_reg[3018]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(11),
      Q => \^lockstep_out\(3018),
      R => Reset
    );
\LOCKSTEP_Out_reg[3019]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(12),
      Q => \^lockstep_out\(3019),
      R => Reset
    );
\LOCKSTEP_Out_reg[3020]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(13),
      Q => \^lockstep_out\(3020),
      R => Reset
    );
\LOCKSTEP_Out_reg[3021]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(14),
      Q => \^lockstep_out\(3021),
      R => Reset
    );
\LOCKSTEP_Out_reg[3022]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(15),
      Q => \^lockstep_out\(3022),
      R => Reset
    );
\LOCKSTEP_Out_reg[3023]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(16),
      Q => \^lockstep_out\(3023),
      R => Reset
    );
\LOCKSTEP_Out_reg[3024]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(17),
      Q => \^lockstep_out\(3024),
      R => Reset
    );
\LOCKSTEP_Out_reg[3025]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(18),
      Q => \^lockstep_out\(3025),
      R => Reset
    );
\LOCKSTEP_Out_reg[3026]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(19),
      Q => \^lockstep_out\(3026),
      R => Reset
    );
\LOCKSTEP_Out_reg[3027]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(20),
      Q => \^lockstep_out\(3027),
      R => Reset
    );
\LOCKSTEP_Out_reg[3028]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(21),
      Q => \^lockstep_out\(3028),
      R => Reset
    );
\LOCKSTEP_Out_reg[3029]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(22),
      Q => \^lockstep_out\(3029),
      R => Reset
    );
\LOCKSTEP_Out_reg[3030]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(23),
      Q => \^lockstep_out\(3030),
      R => Reset
    );
\LOCKSTEP_Out_reg[3031]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(24),
      Q => \^lockstep_out\(3031),
      R => Reset
    );
\LOCKSTEP_Out_reg[3032]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(25),
      Q => \^lockstep_out\(3032),
      R => Reset
    );
\LOCKSTEP_Out_reg[3033]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(26),
      Q => \^lockstep_out\(3033),
      R => Reset
    );
\LOCKSTEP_Out_reg[3034]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(27),
      Q => \^lockstep_out\(3034),
      R => Reset
    );
\LOCKSTEP_Out_reg[3035]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(28),
      Q => \^lockstep_out\(3035),
      R => Reset
    );
\LOCKSTEP_Out_reg[3036]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(29),
      Q => \^lockstep_out\(3036),
      R => Reset
    );
\LOCKSTEP_Out_reg[3037]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(30),
      Q => \^lockstep_out\(3037),
      R => Reset
    );
\LOCKSTEP_Out_reg[3038]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_new_reg_value\(31),
      Q => \^lockstep_out\(3038),
      R => Reset
    );
\LOCKSTEP_Out_reg[3071]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_exception_taken\,
      Q => \^lockstep_out\(3071),
      R => Reset
    );
\LOCKSTEP_Out_reg[3073]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_exception_kind\(1),
      Q => \^lockstep_out\(3073),
      R => Reset
    );
\LOCKSTEP_Out_reg[3076]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_exception_kind\(4),
      Q => \^lockstep_out\(3076),
      R => Reset
    );
\LOCKSTEP_Out_reg[3077]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_jump_taken\,
      Q => \^lockstep_out\(3077),
      R => Reset
    );
\LOCKSTEP_Out_reg[3078]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_delay_slot\,
      Q => \^lockstep_out\(3078),
      R => Reset
    );
\LOCKSTEP_Out_reg[3079]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(0),
      Q => \^lockstep_out\(3079),
      R => Reset
    );
\LOCKSTEP_Out_reg[3080]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(1),
      Q => \^lockstep_out\(3080),
      R => Reset
    );
\LOCKSTEP_Out_reg[3081]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(2),
      Q => \^lockstep_out\(3081),
      R => Reset
    );
\LOCKSTEP_Out_reg[3082]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(3),
      Q => \^lockstep_out\(3082),
      R => Reset
    );
\LOCKSTEP_Out_reg[3083]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(4),
      Q => \^lockstep_out\(3083),
      R => Reset
    );
\LOCKSTEP_Out_reg[3084]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(5),
      Q => \^lockstep_out\(3084),
      R => Reset
    );
\LOCKSTEP_Out_reg[3085]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(6),
      Q => \^lockstep_out\(3085),
      R => Reset
    );
\LOCKSTEP_Out_reg[3086]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(7),
      Q => \^lockstep_out\(3086),
      R => Reset
    );
\LOCKSTEP_Out_reg[3087]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(8),
      Q => \^lockstep_out\(3087),
      R => Reset
    );
\LOCKSTEP_Out_reg[3088]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(9),
      Q => \^lockstep_out\(3088),
      R => Reset
    );
\LOCKSTEP_Out_reg[3089]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(10),
      Q => \^lockstep_out\(3089),
      R => Reset
    );
\LOCKSTEP_Out_reg[3090]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(11),
      Q => \^lockstep_out\(3090),
      R => Reset
    );
\LOCKSTEP_Out_reg[3091]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(12),
      Q => \^lockstep_out\(3091),
      R => Reset
    );
\LOCKSTEP_Out_reg[3092]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(13),
      Q => \^lockstep_out\(3092),
      R => Reset
    );
\LOCKSTEP_Out_reg[3093]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(14),
      Q => \^lockstep_out\(3093),
      R => Reset
    );
\LOCKSTEP_Out_reg[3094]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(15),
      Q => \^lockstep_out\(3094),
      R => Reset
    );
\LOCKSTEP_Out_reg[3095]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(16),
      Q => \^lockstep_out\(3095),
      R => Reset
    );
\LOCKSTEP_Out_reg[3096]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(17),
      Q => \^lockstep_out\(3096),
      R => Reset
    );
\LOCKSTEP_Out_reg[3097]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(18),
      Q => \^lockstep_out\(3097),
      R => Reset
    );
\LOCKSTEP_Out_reg[3098]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(19),
      Q => \^lockstep_out\(3098),
      R => Reset
    );
\LOCKSTEP_Out_reg[3099]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(20),
      Q => \^lockstep_out\(3099),
      R => Reset
    );
\LOCKSTEP_Out_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(26),
      Q => \^lockstep_out\(30),
      R => Reset
    );
\LOCKSTEP_Out_reg[3100]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(21),
      Q => \^lockstep_out\(3100),
      R => Reset
    );
\LOCKSTEP_Out_reg[3101]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(22),
      Q => \^lockstep_out\(3101),
      R => Reset
    );
\LOCKSTEP_Out_reg[3102]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(23),
      Q => \^lockstep_out\(3102),
      R => Reset
    );
\LOCKSTEP_Out_reg[3103]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(24),
      Q => \^lockstep_out\(3103),
      R => Reset
    );
\LOCKSTEP_Out_reg[3104]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(25),
      Q => \^lockstep_out\(3104),
      R => Reset
    );
\LOCKSTEP_Out_reg[3105]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(26),
      Q => \^lockstep_out\(3105),
      R => Reset
    );
\LOCKSTEP_Out_reg[3106]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(27),
      Q => \^lockstep_out\(3106),
      R => Reset
    );
\LOCKSTEP_Out_reg[3107]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(28),
      Q => \^lockstep_out\(3107),
      R => Reset
    );
\LOCKSTEP_Out_reg[3108]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(29),
      Q => \^lockstep_out\(3108),
      R => Reset
    );
\LOCKSTEP_Out_reg[3109]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(30),
      Q => \^lockstep_out\(3109),
      R => Reset
    );
\LOCKSTEP_Out_reg[3110]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_address\(31),
      Q => \^lockstep_out\(3110),
      R => Reset
    );
\LOCKSTEP_Out_reg[3143]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(0),
      Q => \^lockstep_out\(3143),
      R => Reset
    );
\LOCKSTEP_Out_reg[3144]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(1),
      Q => \^lockstep_out\(3144),
      R => Reset
    );
\LOCKSTEP_Out_reg[3145]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(2),
      Q => \^lockstep_out\(3145),
      R => Reset
    );
\LOCKSTEP_Out_reg[3146]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(3),
      Q => \^lockstep_out\(3146),
      R => Reset
    );
\LOCKSTEP_Out_reg[3147]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(4),
      Q => \^lockstep_out\(3147),
      R => Reset
    );
\LOCKSTEP_Out_reg[3148]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(5),
      Q => \^lockstep_out\(3148),
      R => Reset
    );
\LOCKSTEP_Out_reg[3149]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(6),
      Q => \^lockstep_out\(3149),
      R => Reset
    );
\LOCKSTEP_Out_reg[3150]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(7),
      Q => \^lockstep_out\(3150),
      R => Reset
    );
\LOCKSTEP_Out_reg[3151]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(8),
      Q => \^lockstep_out\(3151),
      R => Reset
    );
\LOCKSTEP_Out_reg[3152]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(9),
      Q => \^lockstep_out\(3152),
      R => Reset
    );
\LOCKSTEP_Out_reg[3153]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(10),
      Q => \^lockstep_out\(3153),
      R => Reset
    );
\LOCKSTEP_Out_reg[3154]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(11),
      Q => \^lockstep_out\(3154),
      R => Reset
    );
\LOCKSTEP_Out_reg[3155]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(12),
      Q => \^lockstep_out\(3155),
      R => Reset
    );
\LOCKSTEP_Out_reg[3156]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(13),
      Q => \^lockstep_out\(3156),
      R => Reset
    );
\LOCKSTEP_Out_reg[3157]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(14),
      Q => \^lockstep_out\(3157),
      R => Reset
    );
\LOCKSTEP_Out_reg[3158]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(15),
      Q => \^lockstep_out\(3158),
      R => Reset
    );
\LOCKSTEP_Out_reg[3159]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(16),
      Q => \^lockstep_out\(3159),
      R => Reset
    );
\LOCKSTEP_Out_reg[3160]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(17),
      Q => \^lockstep_out\(3160),
      R => Reset
    );
\LOCKSTEP_Out_reg[3161]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(18),
      Q => \^lockstep_out\(3161),
      R => Reset
    );
\LOCKSTEP_Out_reg[3162]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(19),
      Q => \^lockstep_out\(3162),
      R => Reset
    );
\LOCKSTEP_Out_reg[3163]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(20),
      Q => \^lockstep_out\(3163),
      R => Reset
    );
\LOCKSTEP_Out_reg[3164]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(21),
      Q => \^lockstep_out\(3164),
      R => Reset
    );
\LOCKSTEP_Out_reg[3165]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(22),
      Q => \^lockstep_out\(3165),
      R => Reset
    );
\LOCKSTEP_Out_reg[3166]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(23),
      Q => \^lockstep_out\(3166),
      R => Reset
    );
\LOCKSTEP_Out_reg[3167]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(24),
      Q => \^lockstep_out\(3167),
      R => Reset
    );
\LOCKSTEP_Out_reg[3168]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(25),
      Q => \^lockstep_out\(3168),
      R => Reset
    );
\LOCKSTEP_Out_reg[3169]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(26),
      Q => \^lockstep_out\(3169),
      R => Reset
    );
\LOCKSTEP_Out_reg[3170]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(27),
      Q => \^lockstep_out\(3170),
      R => Reset
    );
\LOCKSTEP_Out_reg[3171]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(28),
      Q => \^lockstep_out\(3171),
      R => Reset
    );
\LOCKSTEP_Out_reg[3172]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(29),
      Q => \^lockstep_out\(3172),
      R => Reset
    );
\LOCKSTEP_Out_reg[3173]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(30),
      Q => \^lockstep_out\(3173),
      R => Reset
    );
\LOCKSTEP_Out_reg[3174]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write_value\(31),
      Q => \^lockstep_out\(3174),
      R => Reset
    );
\LOCKSTEP_Out_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(27),
      Q => \^lockstep_out\(31),
      R => Reset
    );
\LOCKSTEP_Out_reg[3207]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_byte_enable\(0),
      Q => \^lockstep_out\(3207),
      R => Reset
    );
\LOCKSTEP_Out_reg[3208]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_byte_enable\(1),
      Q => \^lockstep_out\(3208),
      R => Reset
    );
\LOCKSTEP_Out_reg[3209]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_byte_enable\(2),
      Q => \^lockstep_out\(3209),
      R => Reset
    );
\LOCKSTEP_Out_reg[3210]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_byte_enable\(3),
      Q => \^lockstep_out\(3210),
      R => Reset
    );
\LOCKSTEP_Out_reg[3215]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_access\,
      Q => \^lockstep_out\(3215),
      R => Reset
    );
\LOCKSTEP_Out_reg[3216]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_read\,
      Q => \^lockstep_out\(3216),
      R => Reset
    );
\LOCKSTEP_Out_reg[3217]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_data_write\,
      Q => \^lockstep_out\(3217),
      R => Reset
    );
\LOCKSTEP_Out_reg[3225]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_of_piperun\,
      Q => \^lockstep_out\(3225),
      R => Reset
    );
\LOCKSTEP_Out_reg[3226]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_ex_piperun\,
      Q => \^lockstep_out\(3226),
      R => Reset
    );
\LOCKSTEP_Out_reg[3227]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^trace_mem_piperun\,
      Q => \^lockstep_out\(3227),
      R => Reset
    );
\LOCKSTEP_Out_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(28),
      Q => \^lockstep_out\(32),
      R => Reset
    );
\LOCKSTEP_Out_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(29),
      Q => \^lockstep_out\(33),
      R => Reset
    );
\LOCKSTEP_Out_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(30),
      Q => \^lockstep_out\(34),
      R => Reset
    );
\LOCKSTEP_Out_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(31),
      Q => \^lockstep_out\(35),
      R => Reset
    );
\LOCKSTEP_Out_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^i_as\,
      Q => \^lockstep_out\(3),
      R => Reset
    );
\LOCKSTEP_Out_reg[466]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(31),
      Q => \^lockstep_out\(632),
      R => Reset
    );
\LOCKSTEP_Out_reg[467]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(30),
      Q => \^lockstep_out\(633),
      R => Reset
    );
\LOCKSTEP_Out_reg[468]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(29),
      Q => \^lockstep_out\(634),
      R => Reset
    );
\LOCKSTEP_Out_reg[469]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(28),
      Q => \^lockstep_out\(635),
      R => Reset
    );
\LOCKSTEP_Out_reg[470]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(27),
      Q => \^lockstep_out\(636),
      R => Reset
    );
\LOCKSTEP_Out_reg[471]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(26),
      Q => \^lockstep_out\(637),
      R => Reset
    );
\LOCKSTEP_Out_reg[472]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(25),
      Q => \^lockstep_out\(638),
      R => Reset
    );
\LOCKSTEP_Out_reg[473]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(24),
      Q => \^lockstep_out\(639),
      R => Reset
    );
\LOCKSTEP_Out_reg[474]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(23),
      Q => \^lockstep_out\(640),
      R => Reset
    );
\LOCKSTEP_Out_reg[475]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(22),
      Q => \^lockstep_out\(641),
      R => Reset
    );
\LOCKSTEP_Out_reg[476]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(21),
      Q => \^lockstep_out\(642),
      R => Reset
    );
\LOCKSTEP_Out_reg[477]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(20),
      Q => \^lockstep_out\(643),
      R => Reset
    );
\LOCKSTEP_Out_reg[478]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(19),
      Q => \^lockstep_out\(644),
      R => Reset
    );
\LOCKSTEP_Out_reg[479]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(18),
      Q => \^lockstep_out\(645),
      R => Reset
    );
\LOCKSTEP_Out_reg[480]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(17),
      Q => \^lockstep_out\(646),
      R => Reset
    );
\LOCKSTEP_Out_reg[481]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(16),
      Q => \^lockstep_out\(647),
      R => Reset
    );
\LOCKSTEP_Out_reg[482]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(15),
      Q => \^lockstep_out\(648),
      R => Reset
    );
\LOCKSTEP_Out_reg[483]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(14),
      Q => \^lockstep_out\(649),
      R => Reset
    );
\LOCKSTEP_Out_reg[484]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(13),
      Q => \^lockstep_out\(650),
      R => Reset
    );
\LOCKSTEP_Out_reg[485]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(12),
      Q => \^lockstep_out\(651),
      R => Reset
    );
\LOCKSTEP_Out_reg[486]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(11),
      Q => \^lockstep_out\(652),
      R => Reset
    );
\LOCKSTEP_Out_reg[487]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(10),
      Q => \^lockstep_out\(653),
      R => Reset
    );
\LOCKSTEP_Out_reg[488]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(9),
      Q => \^lockstep_out\(654),
      R => Reset
    );
\LOCKSTEP_Out_reg[489]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(8),
      Q => \^lockstep_out\(655),
      R => Reset
    );
\LOCKSTEP_Out_reg[490]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(7),
      Q => \^lockstep_out\(656),
      R => Reset
    );
\LOCKSTEP_Out_reg[491]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(6),
      Q => \^lockstep_out\(657),
      R => Reset
    );
\LOCKSTEP_Out_reg[492]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(5),
      Q => \^lockstep_out\(658),
      R => Reset
    );
\LOCKSTEP_Out_reg[493]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(4),
      Q => \^lockstep_out\(659),
      R => Reset
    );
\LOCKSTEP_Out_reg[494]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(3),
      Q => \^lockstep_out\(660),
      R => Reset
    );
\LOCKSTEP_Out_reg[495]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(2),
      Q => \^lockstep_out\(661),
      R => Reset
    );
\LOCKSTEP_Out_reg[496]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(1),
      Q => \^lockstep_out\(662),
      R => Reset
    );
\LOCKSTEP_Out_reg[497]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_araddr\(0),
      Q => \^lockstep_out\(663),
      R => Reset
    );
\LOCKSTEP_Out_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(0),
      Q => \^lockstep_out\(4),
      R => Reset
    );
\LOCKSTEP_Out_reg[539]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => '1',
      Q => \^lockstep_out\(542),
      R => Reset
    );
\LOCKSTEP_Out_reg[555]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_awvalid\,
      Q => \^lockstep_out\(555),
      R => Reset
    );
\LOCKSTEP_Out_reg[556]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(31),
      Q => \^lockstep_out\(556),
      R => Reset
    );
\LOCKSTEP_Out_reg[557]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(30),
      Q => \^lockstep_out\(557),
      R => Reset
    );
\LOCKSTEP_Out_reg[558]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(29),
      Q => \^lockstep_out\(558),
      R => Reset
    );
\LOCKSTEP_Out_reg[559]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(28),
      Q => \^lockstep_out\(559),
      R => Reset
    );
\LOCKSTEP_Out_reg[560]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(27),
      Q => \^lockstep_out\(560),
      R => Reset
    );
\LOCKSTEP_Out_reg[561]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(26),
      Q => \^lockstep_out\(561),
      R => Reset
    );
\LOCKSTEP_Out_reg[562]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(25),
      Q => \^lockstep_out\(562),
      R => Reset
    );
\LOCKSTEP_Out_reg[563]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(24),
      Q => \^lockstep_out\(563),
      R => Reset
    );
\LOCKSTEP_Out_reg[564]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(23),
      Q => \^lockstep_out\(564),
      R => Reset
    );
\LOCKSTEP_Out_reg[565]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(22),
      Q => \^lockstep_out\(565),
      R => Reset
    );
\LOCKSTEP_Out_reg[566]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(21),
      Q => \^lockstep_out\(566),
      R => Reset
    );
\LOCKSTEP_Out_reg[567]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(20),
      Q => \^lockstep_out\(567),
      R => Reset
    );
\LOCKSTEP_Out_reg[568]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(19),
      Q => \^lockstep_out\(568),
      R => Reset
    );
\LOCKSTEP_Out_reg[569]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(18),
      Q => \^lockstep_out\(569),
      R => Reset
    );
\LOCKSTEP_Out_reg[570]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(17),
      Q => \^lockstep_out\(570),
      R => Reset
    );
\LOCKSTEP_Out_reg[571]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(16),
      Q => \^lockstep_out\(571),
      R => Reset
    );
\LOCKSTEP_Out_reg[572]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(15),
      Q => \^lockstep_out\(572),
      R => Reset
    );
\LOCKSTEP_Out_reg[573]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(14),
      Q => \^lockstep_out\(573),
      R => Reset
    );
\LOCKSTEP_Out_reg[574]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(13),
      Q => \^lockstep_out\(574),
      R => Reset
    );
\LOCKSTEP_Out_reg[575]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(12),
      Q => \^lockstep_out\(575),
      R => Reset
    );
\LOCKSTEP_Out_reg[576]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(11),
      Q => \^lockstep_out\(576),
      R => Reset
    );
\LOCKSTEP_Out_reg[577]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(10),
      Q => \^lockstep_out\(577),
      R => Reset
    );
\LOCKSTEP_Out_reg[578]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(9),
      Q => \^lockstep_out\(578),
      R => Reset
    );
\LOCKSTEP_Out_reg[579]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(8),
      Q => \^lockstep_out\(579),
      R => Reset
    );
\LOCKSTEP_Out_reg[580]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(7),
      Q => \^lockstep_out\(580),
      R => Reset
    );
\LOCKSTEP_Out_reg[581]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(6),
      Q => \^lockstep_out\(581),
      R => Reset
    );
\LOCKSTEP_Out_reg[582]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(5),
      Q => \^lockstep_out\(582),
      R => Reset
    );
\LOCKSTEP_Out_reg[583]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(4),
      Q => \^lockstep_out\(583),
      R => Reset
    );
\LOCKSTEP_Out_reg[584]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(3),
      Q => \^lockstep_out\(584),
      R => Reset
    );
\LOCKSTEP_Out_reg[585]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(2),
      Q => \^lockstep_out\(585),
      R => Reset
    );
\LOCKSTEP_Out_reg[586]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(1),
      Q => \^lockstep_out\(586),
      R => Reset
    );
\LOCKSTEP_Out_reg[587]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wdata\(0),
      Q => \^lockstep_out\(587),
      R => Reset
    );
\LOCKSTEP_Out_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(1),
      Q => \^lockstep_out\(5),
      R => Reset
    );
\LOCKSTEP_Out_reg[620]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wstrb\(3),
      Q => \^lockstep_out\(620),
      R => Reset
    );
\LOCKSTEP_Out_reg[621]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wstrb\(2),
      Q => \^lockstep_out\(621),
      R => Reset
    );
\LOCKSTEP_Out_reg[622]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wstrb\(1),
      Q => \^lockstep_out\(622),
      R => Reset
    );
\LOCKSTEP_Out_reg[623]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wstrb\(0),
      Q => \^lockstep_out\(623),
      R => Reset
    );
\LOCKSTEP_Out_reg[629]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_wvalid\,
      Q => \^lockstep_out\(629),
      R => Reset
    );
\LOCKSTEP_Out_reg[68]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(0),
      Q => \^lockstep_out\(68),
      R => Reset
    );
\LOCKSTEP_Out_reg[69]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(1),
      Q => \^lockstep_out\(69),
      R => Reset
    );
\LOCKSTEP_Out_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(2),
      Q => \^lockstep_out\(6),
      R => Reset
    );
\LOCKSTEP_Out_reg[70]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(2),
      Q => \^lockstep_out\(70),
      R => Reset
    );
\LOCKSTEP_Out_reg[71]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(3),
      Q => \^lockstep_out\(71),
      R => Reset
    );
\LOCKSTEP_Out_reg[721]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^m_axi_dp_arvalid\,
      Q => \^lockstep_out\(721),
      R => Reset
    );
\LOCKSTEP_Out_reg[72]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(4),
      Q => \^lockstep_out\(72),
      R => Reset
    );
\LOCKSTEP_Out_reg[73]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(5),
      Q => \^lockstep_out\(73),
      R => Reset
    );
\LOCKSTEP_Out_reg[74]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(6),
      Q => \^lockstep_out\(74),
      R => Reset
    );
\LOCKSTEP_Out_reg[75]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(7),
      Q => \^lockstep_out\(75),
      R => Reset
    );
\LOCKSTEP_Out_reg[76]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(8),
      Q => \^lockstep_out\(76),
      R => Reset
    );
\LOCKSTEP_Out_reg[77]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(9),
      Q => \^lockstep_out\(77),
      R => Reset
    );
\LOCKSTEP_Out_reg[78]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(10),
      Q => \^lockstep_out\(78),
      R => Reset
    );
\LOCKSTEP_Out_reg[79]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(11),
      Q => \^lockstep_out\(79),
      R => Reset
    );
\LOCKSTEP_Out_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(3),
      Q => \^lockstep_out\(7),
      R => Reset
    );
\LOCKSTEP_Out_reg[80]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(12),
      Q => \^lockstep_out\(80),
      R => Reset
    );
\LOCKSTEP_Out_reg[81]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(13),
      Q => \^lockstep_out\(81),
      R => Reset
    );
\LOCKSTEP_Out_reg[82]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(14),
      Q => \^lockstep_out\(82),
      R => Reset
    );
\LOCKSTEP_Out_reg[83]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(15),
      Q => \^lockstep_out\(83),
      R => Reset
    );
\LOCKSTEP_Out_reg[84]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(16),
      Q => \^lockstep_out\(84),
      R => Reset
    );
\LOCKSTEP_Out_reg[85]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(17),
      Q => \^lockstep_out\(85),
      R => Reset
    );
\LOCKSTEP_Out_reg[86]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(18),
      Q => \^lockstep_out\(86),
      R => Reset
    );
\LOCKSTEP_Out_reg[87]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(19),
      Q => \^lockstep_out\(87),
      R => Reset
    );
\LOCKSTEP_Out_reg[88]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(20),
      Q => \^lockstep_out\(88),
      R => Reset
    );
\LOCKSTEP_Out_reg[89]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(21),
      Q => \^lockstep_out\(89),
      R => Reset
    );
\LOCKSTEP_Out_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(4),
      Q => \^lockstep_out\(8),
      R => Reset
    );
\LOCKSTEP_Out_reg[90]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(22),
      Q => \^lockstep_out\(90),
      R => Reset
    );
\LOCKSTEP_Out_reg[91]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(23),
      Q => \^lockstep_out\(91),
      R => Reset
    );
\LOCKSTEP_Out_reg[92]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(24),
      Q => \^lockstep_out\(92),
      R => Reset
    );
\LOCKSTEP_Out_reg[93]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(25),
      Q => \^lockstep_out\(93),
      R => Reset
    );
\LOCKSTEP_Out_reg[94]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(26),
      Q => \^lockstep_out\(94),
      R => Reset
    );
\LOCKSTEP_Out_reg[95]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(27),
      Q => \^lockstep_out\(95),
      R => Reset
    );
\LOCKSTEP_Out_reg[96]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(28),
      Q => \^lockstep_out\(96),
      R => Reset
    );
\LOCKSTEP_Out_reg[97]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(29),
      Q => \^lockstep_out\(97),
      R => Reset
    );
\LOCKSTEP_Out_reg[98]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(30),
      Q => \^lockstep_out\(98),
      R => Reset
    );
\LOCKSTEP_Out_reg[99]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^data_addr\(31),
      Q => \^lockstep_out\(99),
      R => Reset
    );
\LOCKSTEP_Out_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => Clk,
      CE => '1',
      D => \^instr_addr\(5),
      Q => \^lockstep_out\(9),
      R => Reset
    );
MicroBlaze_Core_I: entity work.design_1_microblaze_0_0_MicroBlaze_Core
     port map (
      Clk => Clk,
      Config_Reg_En => Config_Reg_En,
      D(358) => \^lockstep_master_out\(10),
      D(357) => \^ifetch\,
      D(356) => \^i_as\,
      D(355) => \^instr_addr\(0),
      D(354) => \^instr_addr\(1),
      D(353) => \^instr_addr\(2),
      D(352) => \^instr_addr\(3),
      D(351) => \^instr_addr\(4),
      D(350) => \^instr_addr\(5),
      D(349) => \^instr_addr\(6),
      D(348) => \^instr_addr\(7),
      D(347) => \^instr_addr\(8),
      D(346) => \^instr_addr\(9),
      D(345) => \^instr_addr\(10),
      D(344) => \^instr_addr\(11),
      D(343) => \^instr_addr\(12),
      D(342) => \^instr_addr\(13),
      D(341) => \^instr_addr\(14),
      D(340) => \^instr_addr\(15),
      D(339) => \^instr_addr\(16),
      D(338) => \^instr_addr\(17),
      D(337) => \^instr_addr\(18),
      D(336) => \^instr_addr\(19),
      D(335) => \^instr_addr\(20),
      D(334) => \^instr_addr\(21),
      D(333) => \^instr_addr\(22),
      D(332) => \^instr_addr\(23),
      D(331) => \^instr_addr\(24),
      D(330) => \^instr_addr\(25),
      D(329) => \^instr_addr\(26),
      D(328) => \^instr_addr\(27),
      D(327) => \^instr_addr\(28),
      D(326) => \^instr_addr\(29),
      D(325) => \^instr_addr\(30),
      D(324) => \^instr_addr\(31),
      D(323) => \^data_addr\(0),
      D(322) => \^data_addr\(1),
      D(321) => \^data_addr\(2),
      D(320) => \^data_addr\(3),
      D(319) => \^data_addr\(4),
      D(318) => \^data_addr\(5),
      D(317) => \^data_addr\(6),
      D(316) => \^data_addr\(7),
      D(315) => \^data_addr\(8),
      D(314) => \^data_addr\(9),
      D(313) => \^data_addr\(10),
      D(312) => \^data_addr\(11),
      D(311) => \^data_addr\(12),
      D(310) => \^data_addr\(13),
      D(309) => \^data_addr\(14),
      D(308) => \^data_addr\(15),
      D(307) => \^data_addr\(16),
      D(306) => \^data_addr\(17),
      D(305) => \^data_addr\(18),
      D(304) => \^data_addr\(19),
      D(303) => \^data_addr\(20),
      D(302) => \^data_addr\(21),
      D(301) => \^data_addr\(22),
      D(300) => \^data_addr\(23),
      D(299) => \^data_addr\(24),
      D(298) => \^data_addr\(25),
      D(297) => \^data_addr\(26),
      D(296) => \^data_addr\(27),
      D(295) => \^data_addr\(28),
      D(294) => \^data_addr\(29),
      D(293) => \^data_addr\(30),
      D(292) => \^data_addr\(31),
      D(291) => \^data_write\(0),
      D(290) => \^data_write\(1),
      D(289) => \^data_write\(2),
      D(288) => \^data_write\(3),
      D(287) => \^data_write\(4),
      D(286) => \^data_write\(5),
      D(285) => \^data_write\(6),
      D(284) => \^data_write\(7),
      D(283) => \^data_write\(8),
      D(282) => \^data_write\(9),
      D(281) => \^data_write\(10),
      D(280) => \^data_write\(11),
      D(279) => \^data_write\(12),
      D(278) => \^data_write\(13),
      D(277) => \^data_write\(14),
      D(276) => \^data_write\(15),
      D(275) => \^data_write\(16),
      D(274) => \^data_write\(17),
      D(273) => \^data_write\(18),
      D(272) => \^data_write\(19),
      D(271) => \^data_write\(20),
      D(270) => \^data_write\(21),
      D(269) => \^data_write\(22),
      D(268) => \^data_write\(23),
      D(267) => \^data_write\(24),
      D(266) => \^data_write\(25),
      D(265) => \^data_write\(26),
      D(264) => \^data_write\(27),
      D(263) => \^data_write\(28),
      D(262) => \^data_write\(29),
      D(261) => \^data_write\(30),
      D(260) => \^data_write\(31),
      D(259) => \^d_as\,
      D(258) => \^read_strobe\,
      D(257) => \^write_strobe\,
      D(256) => \^byte_enable\(0),
      D(255) => \^byte_enable\(1),
      D(254) => \^byte_enable\(2),
      D(253) => \^byte_enable\(3),
      D(252 downto 221) => \^m_axi_dp_araddr\(31 downto 0),
      D(220) => \^m_axi_dp_awvalid\,
      D(219 downto 188) => \^m_axi_dp_wdata\(31 downto 0),
      D(187 downto 184) => \^m_axi_dp_wstrb\(3 downto 0),
      D(183) => \^m_axi_dp_wvalid\,
      D(182) => \^m_axi_dp_arvalid\,
      D(181) => \^trace_instruction\(0),
      D(180) => \^trace_instruction\(1),
      D(179) => \^trace_instruction\(2),
      D(178) => \^trace_instruction\(3),
      D(177) => \^trace_instruction\(4),
      D(176) => \^trace_instruction\(5),
      D(175) => \^trace_instruction\(6),
      D(174) => \^trace_instruction\(7),
      D(173) => \^trace_instruction\(8),
      D(172) => \^trace_instruction\(9),
      D(171) => \^trace_instruction\(10),
      D(170) => \^trace_instruction\(11),
      D(169) => \^trace_instruction\(12),
      D(168) => \^trace_instruction\(13),
      D(167) => \^trace_instruction\(14),
      D(166) => \^trace_instruction\(15),
      D(165) => \^trace_instruction\(16),
      D(164) => \^trace_instruction\(17),
      D(163) => \^trace_instruction\(18),
      D(162) => \^trace_instruction\(19),
      D(161) => \^trace_instruction\(20),
      D(160) => \^trace_instruction\(21),
      D(159) => \^trace_instruction\(22),
      D(158) => \^trace_instruction\(23),
      D(157) => \^trace_instruction\(24),
      D(156) => \^trace_instruction\(25),
      D(155) => \^trace_instruction\(26),
      D(154) => \^trace_instruction\(27),
      D(153) => \^trace_instruction\(28),
      D(152) => \^trace_instruction\(29),
      D(151) => \^trace_instruction\(30),
      D(150) => \^trace_instruction\(31),
      D(149) => \^trace_valid_instr\,
      D(148) => \^trace_pc\(0),
      D(147) => \^trace_pc\(1),
      D(146) => \^trace_pc\(2),
      D(145) => \^trace_pc\(3),
      D(144) => \^trace_pc\(4),
      D(143) => \^trace_pc\(5),
      D(142) => \^trace_pc\(6),
      D(141) => \^trace_pc\(7),
      D(140) => \^trace_pc\(8),
      D(139) => \^trace_pc\(9),
      D(138) => \^trace_pc\(10),
      D(137) => \^trace_pc\(11),
      D(136) => \^trace_pc\(12),
      D(135) => \^trace_pc\(13),
      D(134) => \^trace_pc\(14),
      D(133) => \^trace_pc\(15),
      D(132) => \^trace_pc\(16),
      D(131) => \^trace_pc\(17),
      D(130) => \^trace_pc\(18),
      D(129) => \^trace_pc\(19),
      D(128) => \^trace_pc\(20),
      D(127) => \^trace_pc\(21),
      D(126) => \^trace_pc\(22),
      D(125) => \^trace_pc\(23),
      D(124) => \^trace_pc\(24),
      D(123) => \^trace_pc\(25),
      D(122) => \^trace_pc\(26),
      D(121) => \^trace_pc\(27),
      D(120) => \^trace_pc\(28),
      D(119) => \^trace_pc\(29),
      D(118) => \^trace_pc\(30),
      D(117) => \^trace_pc\(31),
      D(116) => \^trace_reg_write\,
      D(115) => \^trace_reg_addr\(0),
      D(114) => \^trace_reg_addr\(1),
      D(113) => \^trace_reg_addr\(2),
      D(112) => \^trace_reg_addr\(3),
      D(111) => \^trace_reg_addr\(4),
      D(110) => \^trace_msr_reg\(11),
      D(109) => \^trace_msr_reg\(12),
      D(108) => \^trace_msr_reg\(13),
      D(107) => \^trace_new_reg_value\(0),
      D(106) => \^trace_new_reg_value\(1),
      D(105) => \^trace_new_reg_value\(2),
      D(104) => \^trace_new_reg_value\(3),
      D(103) => \^trace_new_reg_value\(4),
      D(102) => \^trace_new_reg_value\(5),
      D(101) => \^trace_new_reg_value\(6),
      D(100) => \^trace_new_reg_value\(7),
      D(99) => \^trace_new_reg_value\(8),
      D(98) => \^trace_new_reg_value\(9),
      D(97) => \^trace_new_reg_value\(10),
      D(96) => \^trace_new_reg_value\(11),
      D(95) => \^trace_new_reg_value\(12),
      D(94) => \^trace_new_reg_value\(13),
      D(93) => \^trace_new_reg_value\(14),
      D(92) => \^trace_new_reg_value\(15),
      D(91) => \^trace_new_reg_value\(16),
      D(90) => \^trace_new_reg_value\(17),
      D(89) => \^trace_new_reg_value\(18),
      D(88) => \^trace_new_reg_value\(19),
      D(87) => \^trace_new_reg_value\(20),
      D(86) => \^trace_new_reg_value\(21),
      D(85) => \^trace_new_reg_value\(22),
      D(84) => \^trace_new_reg_value\(23),
      D(83) => \^trace_new_reg_value\(24),
      D(82) => \^trace_new_reg_value\(25),
      D(81) => \^trace_new_reg_value\(26),
      D(80) => \^trace_new_reg_value\(27),
      D(79) => \^trace_new_reg_value\(28),
      D(78) => \^trace_new_reg_value\(29),
      D(77) => \^trace_new_reg_value\(30),
      D(76) => \^trace_new_reg_value\(31),
      D(75) => \^trace_exception_taken\,
      D(74) => \^trace_exception_kind\(1),
      D(73) => \^trace_exception_kind\(4),
      D(72) => \^trace_jump_taken\,
      D(71) => \^trace_delay_slot\,
      D(70) => \^trace_data_address\(0),
      D(69) => \^trace_data_address\(1),
      D(68) => \^trace_data_address\(2),
      D(67) => \^trace_data_address\(3),
      D(66) => \^trace_data_address\(4),
      D(65) => \^trace_data_address\(5),
      D(64) => \^trace_data_address\(6),
      D(63) => \^trace_data_address\(7),
      D(62) => \^trace_data_address\(8),
      D(61) => \^trace_data_address\(9),
      D(60) => \^trace_data_address\(10),
      D(59) => \^trace_data_address\(11),
      D(58) => \^trace_data_address\(12),
      D(57) => \^trace_data_address\(13),
      D(56) => \^trace_data_address\(14),
      D(55) => \^trace_data_address\(15),
      D(54) => \^trace_data_address\(16),
      D(53) => \^trace_data_address\(17),
      D(52) => \^trace_data_address\(18),
      D(51) => \^trace_data_address\(19),
      D(50) => \^trace_data_address\(20),
      D(49) => \^trace_data_address\(21),
      D(48) => \^trace_data_address\(22),
      D(47) => \^trace_data_address\(23),
      D(46) => \^trace_data_address\(24),
      D(45) => \^trace_data_address\(25),
      D(44) => \^trace_data_address\(26),
      D(43) => \^trace_data_address\(27),
      D(42) => \^trace_data_address\(28),
      D(41) => \^trace_data_address\(29),
      D(40) => \^trace_data_address\(30),
      D(39) => \^trace_data_address\(31),
      D(38) => \^trace_data_write_value\(0),
      D(37) => \^trace_data_write_value\(1),
      D(36) => \^trace_data_write_value\(2),
      D(35) => \^trace_data_write_value\(3),
      D(34) => \^trace_data_write_value\(4),
      D(33) => \^trace_data_write_value\(5),
      D(32) => \^trace_data_write_value\(6),
      D(31) => \^trace_data_write_value\(7),
      D(30) => \^trace_data_write_value\(8),
      D(29) => \^trace_data_write_value\(9),
      D(28) => \^trace_data_write_value\(10),
      D(27) => \^trace_data_write_value\(11),
      D(26) => \^trace_data_write_value\(12),
      D(25) => \^trace_data_write_value\(13),
      D(24) => \^trace_data_write_value\(14),
      D(23) => \^trace_data_write_value\(15),
      D(22) => \^trace_data_write_value\(16),
      D(21) => \^trace_data_write_value\(17),
      D(20) => \^trace_data_write_value\(18),
      D(19) => \^trace_data_write_value\(19),
      D(18) => \^trace_data_write_value\(20),
      D(17) => \^trace_data_write_value\(21),
      D(16) => \^trace_data_write_value\(22),
      D(15) => \^trace_data_write_value\(23),
      D(14) => \^trace_data_write_value\(24),
      D(13) => \^trace_data_write_value\(25),
      D(12) => \^trace_data_write_value\(26),
      D(11) => \^trace_data_write_value\(27),
      D(10) => \^trace_data_write_value\(28),
      D(9) => \^trace_data_write_value\(29),
      D(8) => \^trace_data_write_value\(30),
      D(7) => \^trace_data_write_value\(31),
      D(6) => \^trace_data_byte_enable\(0),
      D(5) => \^trace_data_byte_enable\(1),
      D(4) => \^trace_data_byte_enable\(2),
      D(3) => \^trace_data_byte_enable\(3),
      D(2) => \^trace_data_access\,
      D(1) => \^trace_data_read\,
      D(0) => \^trace_data_write\,
      DReady => DReady,
      DWait => DWait,
      Data_Read(0 to 31) => Data_Read(0 to 31),
      Data_Read_Reg_En => Data_Read_Reg_En,
      Dbg_Capture => Dbg_Capture,
      Dbg_Clk => Dbg_Clk,
      Dbg_Reg_En(0 to 7) => Dbg_Reg_En(0 to 7),
      Dbg_Reg_En_0_sp_1 => MicroBlaze_Core_I_n_411,
      Dbg_Shift => Dbg_Shift,
      Dbg_Stop => Dbg_Stop,
      Dbg_TDI => Dbg_TDI,
      Dbg_TDO => Dbg_TDO,
      Dbg_Trig_Ack_In(1) => Dbg_Trig_Ack_In(0),
      Dbg_Trig_Ack_In(0) => Dbg_Trig_Ack_In(1),
      Dbg_Trig_Ack_Out(1) => \^dbg_trig_ack_out\(0),
      Dbg_Trig_Ack_Out(0) => \^dbg_trig_ack_out\(1),
      Dbg_Trig_In(1) => \^dbg_trig_in\(0),
      Dbg_Trig_In(0) => \^dbg_trig_in\(1),
      Dbg_Trig_Out(1) => Dbg_Trig_Out(0),
      Dbg_Trig_Out(0) => Dbg_Trig_Out(1),
      Dbg_Update => Dbg_Update,
      Debug_Rst => \^debug_rst\,
      Hibernate => Hibernate,
      IReady => IReady,
      Instr(0 to 31) => Instr(0 to 31),
      LOCKSTEP_Master_Out(40) => \^lockstep_master_out\(1),
      LOCKSTEP_Master_Out(39) => \^lockstep_master_out\(3),
      LOCKSTEP_Master_Out(38) => \^lockstep_master_out\(4),
      LOCKSTEP_Master_Out(37) => \^lockstep_master_out\(5),
      LOCKSTEP_Master_Out(36) => \^lockstep_master_out\(6),
      LOCKSTEP_Master_Out(35) => \^lockstep_master_out\(7),
      LOCKSTEP_Master_Out(34) => \^lockstep_master_out\(11),
      LOCKSTEP_Master_Out(33) => \^dbg_continue\,
      LOCKSTEP_Master_Out(32) => \^lockstep_master_out\(13),
      LOCKSTEP_Master_Out(31) => \^lockstep_master_out\(15),
      LOCKSTEP_Master_Out(30) => \^lockstep_master_out\(16),
      LOCKSTEP_Master_Out(29) => \^lockstep_master_out\(17),
      LOCKSTEP_Master_Out(28) => \^lockstep_master_out\(18),
      LOCKSTEP_Master_Out(27) => \^lockstep_master_out\(19),
      LOCKSTEP_Master_Out(26) => \^lockstep_master_out\(20),
      LOCKSTEP_Master_Out(25) => \^lockstep_master_out\(21),
      LOCKSTEP_Master_Out(24) => \^lockstep_master_out\(22),
      LOCKSTEP_Master_Out(23) => \^lockstep_master_out\(23),
      LOCKSTEP_Master_Out(22) => \^lockstep_master_out\(24),
      LOCKSTEP_Master_Out(21) => \^lockstep_master_out\(25),
      LOCKSTEP_Master_Out(20) => \^lockstep_master_out\(26),
      LOCKSTEP_Master_Out(19) => \^lockstep_master_out\(27),
      LOCKSTEP_Master_Out(18) => \^lockstep_master_out\(28),
      LOCKSTEP_Master_Out(17) => \^lockstep_master_out\(29),
      LOCKSTEP_Master_Out(16) => \^lockstep_master_out\(30),
      LOCKSTEP_Master_Out(15) => \^lockstep_master_out\(31),
      LOCKSTEP_Master_Out(14) => \^lockstep_master_out\(32),
      LOCKSTEP_Master_Out(13) => \^lockstep_master_out\(33),
      LOCKSTEP_Master_Out(12) => \^lockstep_master_out\(34),
      LOCKSTEP_Master_Out(11) => \^lockstep_master_out\(35),
      LOCKSTEP_Master_Out(10) => \^lockstep_master_out\(36),
      LOCKSTEP_Master_Out(9) => \^lockstep_master_out\(37),
      LOCKSTEP_Master_Out(8) => \^lockstep_master_out\(38),
      LOCKSTEP_Master_Out(7) => \^lockstep_master_out\(39),
      LOCKSTEP_Master_Out(6) => \^lockstep_master_out\(40),
      LOCKSTEP_Master_Out(5) => \^lockstep_master_out\(41),
      LOCKSTEP_Master_Out(4) => \^lockstep_master_out\(42),
      LOCKSTEP_Master_Out(3) => \^lockstep_master_out\(43),
      LOCKSTEP_Master_Out(2) => \^lockstep_master_out\(44),
      LOCKSTEP_Master_Out(1) => \^lockstep_master_out\(45),
      LOCKSTEP_Master_Out(0) => \^lockstep_master_out\(46),
      M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
      M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
      M_AXI_DP_BVALID => M_AXI_DP_BVALID,
      M_AXI_DP_RDATA(31 downto 0) => M_AXI_DP_RDATA(31 downto 0),
      M_AXI_DP_RVALID => M_AXI_DP_RVALID,
      M_AXI_DP_WREADY => M_AXI_DP_WREADY,
      Mb_Reset => Mb_Reset,
      Pause => Pause,
      Pause_Ack => Pause_Ack,
      Reset => Reset,
      Reset_Mode(0 to 1) => Reset_Mode(0 to 1),
      Scan_En => Scan_En,
      Scan_Reset => Scan_Reset,
      Scan_Reset_Sel => Scan_Reset_Sel,
      Sleep => Sleep,
      Status_Reg_En => \Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Status_Reg_En\,
      Suspend => Suspend,
      \Using_FPGA.Native\ => \^trace_mem_piperun\,
      \Using_FPGA.Native_0\ => \^trace_ex_piperun\,
      Wakeup(0 to 1) => Wakeup(0 to 1),
      of_pause_reg => \^trace_of_piperun\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_microblaze_0_0 is
  port (
    Clk : in STD_LOGIC;
    Reset : in STD_LOGIC;
    Interrupt : in STD_LOGIC;
    Interrupt_Address : in STD_LOGIC_VECTOR ( 0 to 31 );
    Interrupt_Ack : out STD_LOGIC_VECTOR ( 0 to 1 );
    Instr_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
    Instr : in STD_LOGIC_VECTOR ( 0 to 31 );
    IFetch : out STD_LOGIC;
    I_AS : out STD_LOGIC;
    IReady : in STD_LOGIC;
    IWAIT : in STD_LOGIC;
    ICE : in STD_LOGIC;
    IUE : in STD_LOGIC;
    Data_Addr : out STD_LOGIC_VECTOR ( 0 to 31 );
    Data_Read : in STD_LOGIC_VECTOR ( 0 to 31 );
    Data_Write : out STD_LOGIC_VECTOR ( 0 to 31 );
    D_AS : out STD_LOGIC;
    Read_Strobe : out STD_LOGIC;
    Write_Strobe : out STD_LOGIC;
    DReady : in STD_LOGIC;
    DWait : in STD_LOGIC;
    DCE : in STD_LOGIC;
    DUE : in STD_LOGIC;
    Byte_Enable : out STD_LOGIC_VECTOR ( 0 to 3 );
    M_AXI_DP_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DP_AWVALID : out STD_LOGIC;
    M_AXI_DP_AWREADY : in STD_LOGIC;
    M_AXI_DP_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
    M_AXI_DP_WVALID : out STD_LOGIC;
    M_AXI_DP_WREADY : in STD_LOGIC;
    M_AXI_DP_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DP_BVALID : in STD_LOGIC;
    M_AXI_DP_BREADY : out STD_LOGIC;
    M_AXI_DP_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
    M_AXI_DP_ARVALID : out STD_LOGIC;
    M_AXI_DP_ARREADY : in STD_LOGIC;
    M_AXI_DP_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
    M_AXI_DP_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
    M_AXI_DP_RVALID : in STD_LOGIC;
    M_AXI_DP_RREADY : out STD_LOGIC;
    Dbg_Clk : in STD_LOGIC;
    Dbg_TDI : in STD_LOGIC;
    Dbg_TDO : out STD_LOGIC;
    Dbg_Reg_En : in STD_LOGIC_VECTOR ( 0 to 7 );
    Dbg_Shift : in STD_LOGIC;
    Dbg_Capture : in STD_LOGIC;
    Dbg_Update : in STD_LOGIC;
    Debug_Rst : in STD_LOGIC;
    Dbg_Disable : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of design_1_microblaze_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of design_1_microblaze_0_0 : entity is "design_1_microblaze_0_0,MicroBlaze,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of design_1_microblaze_0_0 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of design_1_microblaze_0_0 : entity is "MicroBlaze,Vivado 2019.1";
end design_1_microblaze_0_0;

architecture STRUCTURE of design_1_microblaze_0_0 is
  signal NLW_U0_Dbg_ARREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_AWREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Continue_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Intr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_RVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Trace_Valid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_WREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_Wakeup_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Hibernate_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M0_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M0_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M10_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M10_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M11_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M11_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M12_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M12_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M13_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M13_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M14_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M14_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M15_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M15_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M1_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M1_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M2_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M2_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M3_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M3_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M4_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M4_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M5_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M5_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M6_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M6_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M7_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M7_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M8_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M8_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M9_AXIS_TLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M9_AXIS_TVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_MB_Error_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_MB_Halted_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_ACREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_ARLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_ARVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_AWLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_AWVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_BREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_CDLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_CDVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_CRVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_RACK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_RREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_WACK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_WLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DC_WVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DP_ARLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DP_AWLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_DP_WLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_ACREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_ARLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_ARVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_AWLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_AWVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_BREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_CDLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_CDVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_CRVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_RACK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_RREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_WACK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_WLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IC_WVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_ARLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_ARVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_AWLOCK_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_AWVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_BREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_RREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_WLAST_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_M_AXI_IP_WVALID_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Pause_Ack_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S0_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S10_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S11_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S12_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S13_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S14_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S15_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S1_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S2_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S3_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S4_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S5_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S6_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S7_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S8_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_S9_AXIS_TREADY_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Sleep_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Suspend_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_DCache_Hit_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_DCache_Rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_DCache_Read_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_DCache_Req_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Data_Access_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Data_Read_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Data_Write_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Delay_Slot_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_EX_PipeRun_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Exception_Taken_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_ICache_Hit_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_ICache_Rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_ICache_Req_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Jump_Hit_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Jump_Taken_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_MB_Halted_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_MEM_PipeRun_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_OF_PipeRun_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Reg_Write_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Trace_Valid_Instr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_Dbg_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_Dbg_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_Dbg_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_Dbg_Trace_Data_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 35 );
  signal NLW_U0_Dbg_Trig_Ack_Out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Dbg_Trig_In_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_LOCKSTEP_Master_Out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 4095 );
  signal NLW_U0_LOCKSTEP_Out_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 4095 );
  signal NLW_U0_M0_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M10_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M11_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M12_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M13_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M14_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M15_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M1_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M2_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M3_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M4_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M5_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M6_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M7_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M8_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M9_AXIS_TDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_DC_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_DC_ARBAR_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DC_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DC_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DC_ARDOMAIN_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DC_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_DC_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_DC_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_DC_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DC_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_DC_ARSNOOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DC_ARUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_M_AXI_DC_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_DC_AWBAR_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DC_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DC_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DC_AWDOMAIN_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DC_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_DC_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_DC_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_DC_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DC_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_DC_AWSNOOP_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_DC_AWUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_M_AXI_DC_CDDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_DC_CRRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_M_AXI_DC_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_DC_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DC_WUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_DP_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DP_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DP_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_DP_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_DP_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DP_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_DP_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_DP_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DP_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_DP_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_DP_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_DP_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IC_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_IC_ARBAR_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IC_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IC_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IC_ARDOMAIN_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IC_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_IC_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_IC_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IC_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IC_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IC_ARSNOOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IC_ARUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_M_AXI_IC_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_IC_AWBAR_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IC_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IC_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IC_AWDOMAIN_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IC_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_IC_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_IC_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IC_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IC_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IC_AWSNOOP_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IC_AWUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_M_AXI_IC_CDDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_IC_CRRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_M_AXI_IC_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_IC_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IC_WUSER_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_IP_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_IP_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IP_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IP_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_IP_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_IP_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IP_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IP_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IP_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_IP_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_M_AXI_IP_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IP_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_M_AXI_IP_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal NLW_U0_M_AXI_IP_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IP_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_M_AXI_IP_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal NLW_U0_M_AXI_IP_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_M_AXI_IP_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_RAM_From_UNCONNECTED : STD_LOGIC_VECTOR ( 255 downto 0 );
  signal NLW_U0_Trace_Data_Address_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_Trace_Data_Byte_Enable_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 3 );
  signal NLW_U0_Trace_Data_Write_Value_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_Trace_Exception_Kind_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 4 );
  signal NLW_U0_Trace_Instruction_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_Trace_MSR_Reg_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 14 );
  signal NLW_U0_Trace_New_Reg_Value_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_Trace_PC_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 31 );
  signal NLW_U0_Trace_PID_Reg_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 7 );
  signal NLW_U0_Trace_Reg_Addr_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 4 );
  attribute C_ADDR_TAG_BITS : integer;
  attribute C_ADDR_TAG_BITS of U0 : label is 17;
  attribute C_ALLOW_DCACHE_WR : integer;
  attribute C_ALLOW_DCACHE_WR of U0 : label is 1;
  attribute C_ALLOW_ICACHE_WR : integer;
  attribute C_ALLOW_ICACHE_WR of U0 : label is 1;
  attribute C_AREA_OPTIMIZED : integer;
  attribute C_AREA_OPTIMIZED of U0 : label is 0;
  attribute C_ASYNC_INTERRUPT : integer;
  attribute C_ASYNC_INTERRUPT of U0 : label is 1;
  attribute C_ASYNC_WAKEUP : integer;
  attribute C_ASYNC_WAKEUP of U0 : label is 3;
  attribute C_AVOID_PRIMITIVES : integer;
  attribute C_AVOID_PRIMITIVES of U0 : label is 0;
  attribute C_BASE_VECTORS : string;
  attribute C_BASE_VECTORS of U0 : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_BRANCH_TARGET_CACHE_SIZE : integer;
  attribute C_BRANCH_TARGET_CACHE_SIZE of U0 : label is 0;
  attribute C_CACHE_BYTE_SIZE : integer;
  attribute C_CACHE_BYTE_SIZE of U0 : label is 8192;
  attribute C_DADDR_SIZE : integer;
  attribute C_DADDR_SIZE of U0 : label is 32;
  attribute C_DATA_SIZE : integer;
  attribute C_DATA_SIZE of U0 : label is 32;
  attribute C_DCACHE_ADDR_TAG : integer;
  attribute C_DCACHE_ADDR_TAG of U0 : label is 17;
  attribute C_DCACHE_ALWAYS_USED : integer;
  attribute C_DCACHE_ALWAYS_USED of U0 : label is 0;
  attribute C_DCACHE_BASEADDR : string;
  attribute C_DCACHE_BASEADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_DCACHE_BYTE_SIZE : integer;
  attribute C_DCACHE_BYTE_SIZE of U0 : label is 8192;
  attribute C_DCACHE_DATA_WIDTH : integer;
  attribute C_DCACHE_DATA_WIDTH of U0 : label is 0;
  attribute C_DCACHE_FORCE_TAG_LUTRAM : integer;
  attribute C_DCACHE_FORCE_TAG_LUTRAM of U0 : label is 0;
  attribute C_DCACHE_HIGHADDR : string;
  attribute C_DCACHE_HIGHADDR of U0 : label is "64'b0000000000000000000000000000000000111111111111111111111111111111";
  attribute C_DCACHE_LINE_LEN : integer;
  attribute C_DCACHE_LINE_LEN of U0 : label is 4;
  attribute C_DCACHE_USE_WRITEBACK : integer;
  attribute C_DCACHE_USE_WRITEBACK of U0 : label is 0;
  attribute C_DCACHE_VICTIMS : integer;
  attribute C_DCACHE_VICTIMS of U0 : label is 0;
  attribute C_DEBUG_COUNTER_WIDTH : integer;
  attribute C_DEBUG_COUNTER_WIDTH of U0 : label is 32;
  attribute C_DEBUG_ENABLED : integer;
  attribute C_DEBUG_ENABLED of U0 : label is 1;
  attribute C_DEBUG_EVENT_COUNTERS : integer;
  attribute C_DEBUG_EVENT_COUNTERS of U0 : label is 5;
  attribute C_DEBUG_EXTERNAL_TRACE : integer;
  attribute C_DEBUG_EXTERNAL_TRACE of U0 : label is 0;
  attribute C_DEBUG_INTERFACE : integer;
  attribute C_DEBUG_INTERFACE of U0 : label is 0;
  attribute C_DEBUG_LATENCY_COUNTERS : integer;
  attribute C_DEBUG_LATENCY_COUNTERS of U0 : label is 1;
  attribute C_DEBUG_PROFILE_SIZE : integer;
  attribute C_DEBUG_PROFILE_SIZE of U0 : label is 0;
  attribute C_DEBUG_TRACE_ASYNC_RESET : integer;
  attribute C_DEBUG_TRACE_ASYNC_RESET of U0 : label is 0;
  attribute C_DEBUG_TRACE_SIZE : integer;
  attribute C_DEBUG_TRACE_SIZE of U0 : label is 8192;
  attribute C_DIV_ZERO_EXCEPTION : integer;
  attribute C_DIV_ZERO_EXCEPTION of U0 : label is 0;
  attribute C_DYNAMIC_BUS_SIZING : integer;
  attribute C_DYNAMIC_BUS_SIZING of U0 : label is 0;
  attribute C_D_AXI : integer;
  attribute C_D_AXI of U0 : label is 1;
  attribute C_D_LMB : integer;
  attribute C_D_LMB of U0 : label is 1;
  attribute C_ECC_USE_CE_EXCEPTION : integer;
  attribute C_ECC_USE_CE_EXCEPTION of U0 : label is 0;
  attribute C_EDGE_IS_POSITIVE : integer;
  attribute C_EDGE_IS_POSITIVE of U0 : label is 1;
  attribute C_ENDIANNESS : integer;
  attribute C_ENDIANNESS of U0 : label is 1;
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "kintexuplus";
  attribute C_FAULT_TOLERANT : integer;
  attribute C_FAULT_TOLERANT of U0 : label is 0;
  attribute C_FPU_EXCEPTION : integer;
  attribute C_FPU_EXCEPTION of U0 : label is 0;
  attribute C_FREQ : integer;
  attribute C_FREQ of U0 : label is 100000000;
  attribute C_FSL_EXCEPTION : integer;
  attribute C_FSL_EXCEPTION of U0 : label is 0;
  attribute C_FSL_LINKS : integer;
  attribute C_FSL_LINKS of U0 : label is 0;
  attribute C_IADDR_SIZE : integer;
  attribute C_IADDR_SIZE of U0 : label is 32;
  attribute C_ICACHE_ALWAYS_USED : integer;
  attribute C_ICACHE_ALWAYS_USED of U0 : label is 0;
  attribute C_ICACHE_BASEADDR : string;
  attribute C_ICACHE_BASEADDR of U0 : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
  attribute C_ICACHE_DATA_WIDTH : integer;
  attribute C_ICACHE_DATA_WIDTH of U0 : label is 0;
  attribute C_ICACHE_FORCE_TAG_LUTRAM : integer;
  attribute C_ICACHE_FORCE_TAG_LUTRAM of U0 : label is 0;
  attribute C_ICACHE_HIGHADDR : string;
  attribute C_ICACHE_HIGHADDR of U0 : label is "64'b0000000000000000000000000000000000111111111111111111111111111111";
  attribute C_ICACHE_LINE_LEN : integer;
  attribute C_ICACHE_LINE_LEN of U0 : label is 4;
  attribute C_ICACHE_STREAMS : integer;
  attribute C_ICACHE_STREAMS of U0 : label is 0;
  attribute C_ICACHE_VICTIMS : integer;
  attribute C_ICACHE_VICTIMS of U0 : label is 0;
  attribute C_ILL_OPCODE_EXCEPTION : integer;
  attribute C_ILL_OPCODE_EXCEPTION of U0 : label is 0;
  attribute C_IMPRECISE_EXCEPTIONS : integer;
  attribute C_IMPRECISE_EXCEPTIONS of U0 : label is 0;
  attribute C_INSTANCE : string;
  attribute C_INSTANCE of U0 : label is "design_1_microblaze_0_0";
  attribute C_INSTR_SIZE : integer;
  attribute C_INSTR_SIZE of U0 : label is 32;
  attribute C_INTERCONNECT : integer;
  attribute C_INTERCONNECT of U0 : label is 2;
  attribute C_INTERRUPT_IS_EDGE : integer;
  attribute C_INTERRUPT_IS_EDGE of U0 : label is 0;
  attribute C_I_AXI : integer;
  attribute C_I_AXI of U0 : label is 0;
  attribute C_I_LMB : integer;
  attribute C_I_LMB of U0 : label is 1;
  attribute C_LMB_DATA_SIZE : integer;
  attribute C_LMB_DATA_SIZE of U0 : label is 32;
  attribute C_LOCKSTEP_MASTER : integer;
  attribute C_LOCKSTEP_MASTER of U0 : label is 0;
  attribute C_LOCKSTEP_SLAVE : integer;
  attribute C_LOCKSTEP_SLAVE of U0 : label is 0;
  attribute C_M0_AXIS_DATA_WIDTH : integer;
  attribute C_M0_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M10_AXIS_DATA_WIDTH : integer;
  attribute C_M10_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M11_AXIS_DATA_WIDTH : integer;
  attribute C_M11_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M12_AXIS_DATA_WIDTH : integer;
  attribute C_M12_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M13_AXIS_DATA_WIDTH : integer;
  attribute C_M13_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M14_AXIS_DATA_WIDTH : integer;
  attribute C_M14_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M15_AXIS_DATA_WIDTH : integer;
  attribute C_M15_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M1_AXIS_DATA_WIDTH : integer;
  attribute C_M1_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M2_AXIS_DATA_WIDTH : integer;
  attribute C_M2_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M3_AXIS_DATA_WIDTH : integer;
  attribute C_M3_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M4_AXIS_DATA_WIDTH : integer;
  attribute C_M4_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M5_AXIS_DATA_WIDTH : integer;
  attribute C_M5_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M6_AXIS_DATA_WIDTH : integer;
  attribute C_M6_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M7_AXIS_DATA_WIDTH : integer;
  attribute C_M7_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M8_AXIS_DATA_WIDTH : integer;
  attribute C_M8_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_M9_AXIS_DATA_WIDTH : integer;
  attribute C_M9_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_MMU_DTLB_SIZE : integer;
  attribute C_MMU_DTLB_SIZE of U0 : label is 4;
  attribute C_MMU_ITLB_SIZE : integer;
  attribute C_MMU_ITLB_SIZE of U0 : label is 2;
  attribute C_MMU_PRIVILEGED_INSTR : integer;
  attribute C_MMU_PRIVILEGED_INSTR of U0 : label is 0;
  attribute C_MMU_TLB_ACCESS : integer;
  attribute C_MMU_TLB_ACCESS of U0 : label is 3;
  attribute C_MMU_ZONES : integer;
  attribute C_MMU_ZONES of U0 : label is 16;
  attribute C_M_AXI_DC_ADDR_WIDTH : integer;
  attribute C_M_AXI_DC_ADDR_WIDTH of U0 : label is 32;
  attribute C_M_AXI_DC_ARUSER_WIDTH : integer;
  attribute C_M_AXI_DC_ARUSER_WIDTH of U0 : label is 5;
  attribute C_M_AXI_DC_AWUSER_WIDTH : integer;
  attribute C_M_AXI_DC_AWUSER_WIDTH of U0 : label is 5;
  attribute C_M_AXI_DC_BUSER_WIDTH : integer;
  attribute C_M_AXI_DC_BUSER_WIDTH of U0 : label is 1;
  attribute C_M_AXI_DC_DATA_WIDTH : integer;
  attribute C_M_AXI_DC_DATA_WIDTH of U0 : label is 32;
  attribute C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
  attribute C_M_AXI_DC_EXCLUSIVE_ACCESS of U0 : label is 0;
  attribute C_M_AXI_DC_RUSER_WIDTH : integer;
  attribute C_M_AXI_DC_RUSER_WIDTH of U0 : label is 1;
  attribute C_M_AXI_DC_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_DC_THREAD_ID_WIDTH of U0 : label is 1;
  attribute C_M_AXI_DC_USER_VALUE : integer;
  attribute C_M_AXI_DC_USER_VALUE of U0 : label is 31;
  attribute C_M_AXI_DC_WUSER_WIDTH : integer;
  attribute C_M_AXI_DC_WUSER_WIDTH of U0 : label is 1;
  attribute C_M_AXI_DP_ADDR_WIDTH : integer;
  attribute C_M_AXI_DP_ADDR_WIDTH of U0 : label is 32;
  attribute C_M_AXI_DP_DATA_WIDTH : integer;
  attribute C_M_AXI_DP_DATA_WIDTH of U0 : label is 32;
  attribute C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
  attribute C_M_AXI_DP_EXCLUSIVE_ACCESS of U0 : label is 0;
  attribute C_M_AXI_DP_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_DP_THREAD_ID_WIDTH of U0 : label is 1;
  attribute C_M_AXI_D_BUS_EXCEPTION : integer;
  attribute C_M_AXI_D_BUS_EXCEPTION of U0 : label is 0;
  attribute C_M_AXI_IC_ADDR_WIDTH : integer;
  attribute C_M_AXI_IC_ADDR_WIDTH of U0 : label is 32;
  attribute C_M_AXI_IC_ARUSER_WIDTH : integer;
  attribute C_M_AXI_IC_ARUSER_WIDTH of U0 : label is 5;
  attribute C_M_AXI_IC_AWUSER_WIDTH : integer;
  attribute C_M_AXI_IC_AWUSER_WIDTH of U0 : label is 5;
  attribute C_M_AXI_IC_BUSER_WIDTH : integer;
  attribute C_M_AXI_IC_BUSER_WIDTH of U0 : label is 1;
  attribute C_M_AXI_IC_DATA_WIDTH : integer;
  attribute C_M_AXI_IC_DATA_WIDTH of U0 : label is 32;
  attribute C_M_AXI_IC_RUSER_WIDTH : integer;
  attribute C_M_AXI_IC_RUSER_WIDTH of U0 : label is 1;
  attribute C_M_AXI_IC_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_IC_THREAD_ID_WIDTH of U0 : label is 1;
  attribute C_M_AXI_IC_USER_VALUE : integer;
  attribute C_M_AXI_IC_USER_VALUE of U0 : label is 31;
  attribute C_M_AXI_IC_WUSER_WIDTH : integer;
  attribute C_M_AXI_IC_WUSER_WIDTH of U0 : label is 1;
  attribute C_M_AXI_IP_ADDR_WIDTH : integer;
  attribute C_M_AXI_IP_ADDR_WIDTH of U0 : label is 32;
  attribute C_M_AXI_IP_DATA_WIDTH : integer;
  attribute C_M_AXI_IP_DATA_WIDTH of U0 : label is 32;
  attribute C_M_AXI_IP_THREAD_ID_WIDTH : integer;
  attribute C_M_AXI_IP_THREAD_ID_WIDTH of U0 : label is 1;
  attribute C_M_AXI_I_BUS_EXCEPTION : integer;
  attribute C_M_AXI_I_BUS_EXCEPTION of U0 : label is 0;
  attribute C_NUMBER_OF_PC_BRK : integer;
  attribute C_NUMBER_OF_PC_BRK of U0 : label is 1;
  attribute C_NUMBER_OF_RD_ADDR_BRK : integer;
  attribute C_NUMBER_OF_RD_ADDR_BRK of U0 : label is 0;
  attribute C_NUMBER_OF_WR_ADDR_BRK : integer;
  attribute C_NUMBER_OF_WR_ADDR_BRK of U0 : label is 0;
  attribute C_NUM_SYNC_FF_CLK : integer;
  attribute C_NUM_SYNC_FF_CLK of U0 : label is 2;
  attribute C_NUM_SYNC_FF_CLK_DEBUG : integer;
  attribute C_NUM_SYNC_FF_CLK_DEBUG of U0 : label is 2;
  attribute C_NUM_SYNC_FF_CLK_IRQ : integer;
  attribute C_NUM_SYNC_FF_CLK_IRQ of U0 : label is 1;
  attribute C_NUM_SYNC_FF_DBG_CLK : integer;
  attribute C_NUM_SYNC_FF_DBG_CLK of U0 : label is 1;
  attribute C_NUM_SYNC_FF_DBG_TRACE_CLK : integer;
  attribute C_NUM_SYNC_FF_DBG_TRACE_CLK of U0 : label is 2;
  attribute C_OPCODE_0x0_ILLEGAL : integer;
  attribute C_OPCODE_0x0_ILLEGAL of U0 : label is 0;
  attribute C_OPTIMIZATION : integer;
  attribute C_OPTIMIZATION of U0 : label is 0;
  attribute C_PC_WIDTH : integer;
  attribute C_PC_WIDTH of U0 : label is 32;
  attribute C_PIADDR_SIZE : integer;
  attribute C_PIADDR_SIZE of U0 : label is 32;
  attribute C_PVR : integer;
  attribute C_PVR of U0 : label is 0;
  attribute C_PVR_USER1 : string;
  attribute C_PVR_USER1 of U0 : label is "8'b00000000";
  attribute C_PVR_USER2 : integer;
  attribute C_PVR_USER2 of U0 : label is 0;
  attribute C_RESET_MSR : integer;
  attribute C_RESET_MSR of U0 : label is 0;
  attribute C_S0_AXIS_DATA_WIDTH : integer;
  attribute C_S0_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S10_AXIS_DATA_WIDTH : integer;
  attribute C_S10_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S11_AXIS_DATA_WIDTH : integer;
  attribute C_S11_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S12_AXIS_DATA_WIDTH : integer;
  attribute C_S12_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S13_AXIS_DATA_WIDTH : integer;
  attribute C_S13_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S14_AXIS_DATA_WIDTH : integer;
  attribute C_S14_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S15_AXIS_DATA_WIDTH : integer;
  attribute C_S15_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S1_AXIS_DATA_WIDTH : integer;
  attribute C_S1_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S2_AXIS_DATA_WIDTH : integer;
  attribute C_S2_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S3_AXIS_DATA_WIDTH : integer;
  attribute C_S3_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S4_AXIS_DATA_WIDTH : integer;
  attribute C_S4_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S5_AXIS_DATA_WIDTH : integer;
  attribute C_S5_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S6_AXIS_DATA_WIDTH : integer;
  attribute C_S6_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S7_AXIS_DATA_WIDTH : integer;
  attribute C_S7_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S8_AXIS_DATA_WIDTH : integer;
  attribute C_S8_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_S9_AXIS_DATA_WIDTH : integer;
  attribute C_S9_AXIS_DATA_WIDTH of U0 : label is 32;
  attribute C_SCO : integer;
  attribute C_SCO of U0 : label is 0;
  attribute C_UNALIGNED_EXCEPTIONS : integer;
  attribute C_UNALIGNED_EXCEPTIONS of U0 : label is 0;
  attribute C_USE_BARREL : integer;
  attribute C_USE_BARREL of U0 : label is 0;
  attribute C_USE_BRANCH_TARGET_CACHE : integer;
  attribute C_USE_BRANCH_TARGET_CACHE of U0 : label is 0;
  attribute C_USE_CONFIG_RESET : integer;
  attribute C_USE_CONFIG_RESET of U0 : label is 0;
  attribute C_USE_DCACHE : integer;
  attribute C_USE_DCACHE of U0 : label is 0;
  attribute C_USE_DIV : integer;
  attribute C_USE_DIV of U0 : label is 0;
  attribute C_USE_EXTENDED_FSL_INSTR : integer;
  attribute C_USE_EXTENDED_FSL_INSTR of U0 : label is 0;
  attribute C_USE_EXT_BRK : integer;
  attribute C_USE_EXT_BRK of U0 : label is 0;
  attribute C_USE_EXT_NM_BRK : integer;
  attribute C_USE_EXT_NM_BRK of U0 : label is 0;
  attribute C_USE_FPU : integer;
  attribute C_USE_FPU of U0 : label is 0;
  attribute C_USE_HW_MUL : integer;
  attribute C_USE_HW_MUL of U0 : label is 0;
  attribute C_USE_ICACHE : integer;
  attribute C_USE_ICACHE of U0 : label is 0;
  attribute C_USE_INTERRUPT : integer;
  attribute C_USE_INTERRUPT of U0 : label is 0;
  attribute C_USE_MMU : integer;
  attribute C_USE_MMU of U0 : label is 0;
  attribute C_USE_MSR_INSTR : integer;
  attribute C_USE_MSR_INSTR of U0 : label is 0;
  attribute C_USE_NON_SECURE : integer;
  attribute C_USE_NON_SECURE of U0 : label is 0;
  attribute C_USE_PCMP_INSTR : integer;
  attribute C_USE_PCMP_INSTR of U0 : label is 0;
  attribute C_USE_REORDER_INSTR : integer;
  attribute C_USE_REORDER_INSTR of U0 : label is 1;
  attribute C_USE_STACK_PROTECTION : integer;
  attribute C_USE_STACK_PROTECTION of U0 : label is 0;
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute x_interface_info : string;
  attribute x_interface_info of Clk : signal is "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of Clk : signal is "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC, ASSOCIATED_RESET Reset, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_clk_wiz_1_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of DCE : signal is "xilinx.com:interface:lmb:1.0 DLMB CE";
  attribute x_interface_info of DReady : signal is "xilinx.com:interface:lmb:1.0 DLMB READY";
  attribute x_interface_info of DUE : signal is "xilinx.com:interface:lmb:1.0 DLMB UE";
  attribute x_interface_info of DWait : signal is "xilinx.com:interface:lmb:1.0 DLMB WAIT";
  attribute x_interface_info of D_AS : signal is "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
  attribute x_interface_info of Dbg_Capture : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
  attribute x_interface_info of Dbg_Clk : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
  attribute x_interface_info of Dbg_Disable : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG DISABLE";
  attribute x_interface_info of Dbg_Shift : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
  attribute x_interface_info of Dbg_TDI : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
  attribute x_interface_info of Dbg_TDO : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
  attribute x_interface_info of Dbg_Update : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
  attribute x_interface_info of Debug_Rst : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
  attribute x_interface_info of ICE : signal is "xilinx.com:interface:lmb:1.0 ILMB CE";
  attribute x_interface_info of IFetch : signal is "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
  attribute x_interface_info of IReady : signal is "xilinx.com:interface:lmb:1.0 ILMB READY";
  attribute x_interface_info of IUE : signal is "xilinx.com:interface:lmb:1.0 ILMB UE";
  attribute x_interface_info of IWAIT : signal is "xilinx.com:interface:lmb:1.0 ILMB WAIT";
  attribute x_interface_info of I_AS : signal is "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
  attribute x_interface_info of Interrupt : signal is "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
  attribute x_interface_parameter of Interrupt : signal is "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, LOW_LATENCY 0";
  attribute x_interface_info of M_AXI_DP_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
  attribute x_interface_info of M_AXI_DP_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
  attribute x_interface_info of M_AXI_DP_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
  attribute x_interface_info of M_AXI_DP_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
  attribute x_interface_info of M_AXI_DP_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
  attribute x_interface_info of M_AXI_DP_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
  attribute x_interface_info of M_AXI_DP_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
  attribute x_interface_info of M_AXI_DP_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
  attribute x_interface_info of M_AXI_DP_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
  attribute x_interface_info of M_AXI_DP_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
  attribute x_interface_info of Read_Strobe : signal is "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
  attribute x_interface_info of Reset : signal is "xilinx.com:signal:reset:1.0 RST.RESET RST";
  attribute x_interface_parameter of Reset : signal is "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
  attribute x_interface_info of Write_Strobe : signal is "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
  attribute x_interface_info of Byte_Enable : signal is "xilinx.com:interface:lmb:1.0 DLMB BE";
  attribute x_interface_info of Data_Addr : signal is "xilinx.com:interface:lmb:1.0 DLMB ABUS";
  attribute x_interface_parameter of Data_Addr : signal is "XIL_INTERFACENAME DLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
  attribute x_interface_info of Data_Read : signal is "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
  attribute x_interface_info of Data_Write : signal is "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
  attribute x_interface_info of Dbg_Reg_En : signal is "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
  attribute x_interface_info of Instr : signal is "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
  attribute x_interface_info of Instr_Addr : signal is "xilinx.com:interface:lmb:1.0 ILMB ABUS";
  attribute x_interface_parameter of Instr_Addr : signal is "XIL_INTERFACENAME ILMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_ONLY";
  attribute x_interface_info of Interrupt_Ack : signal is "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
  attribute x_interface_info of Interrupt_Address : signal is "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
  attribute x_interface_info of M_AXI_DP_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
  attribute x_interface_info of M_AXI_DP_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
  attribute x_interface_info of M_AXI_DP_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
  attribute x_interface_parameter of M_AXI_DP_AWADDR : signal is "XIL_INTERFACENAME M_AXI_DP, ID_WIDTH 0, READ_WRITE_MODE READ_WRITE, SUPPORTS_NARROW_BURST 0, HAS_BURST 0, HAS_LOCK 0, DATA_WIDTH 32, ADDR_WIDTH 32, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, MAX_BURST_LENGTH 1, PROTOCOL AXI4LITE, FREQ_HZ 100000000, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, PHASE 0.0, CLK_DOMAIN design_1_clk_wiz_1_0_clk_out1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
  attribute x_interface_info of M_AXI_DP_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
  attribute x_interface_info of M_AXI_DP_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
  attribute x_interface_info of M_AXI_DP_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
  attribute x_interface_info of M_AXI_DP_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
  attribute x_interface_info of M_AXI_DP_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
  attribute x_interface_info of M_AXI_DP_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
begin
U0: entity work.design_1_microblaze_0_0_MicroBlaze
     port map (
      Byte_Enable(0 to 3) => Byte_Enable(0 to 3),
      Clk => Clk,
      Config_Reset => '0',
      DCE => DCE,
      DEBUG_ACLK => '0',
      DEBUG_ARESETN => '0',
      DReady => DReady,
      DUE => DUE,
      DWait => DWait,
      D_AS => D_AS,
      Data_Addr(0 to 31) => Data_Addr(0 to 31),
      Data_Read(0 to 31) => Data_Read(0 to 31),
      Data_Write(0 to 31) => Data_Write(0 to 31),
      Dbg_ARADDR(14 downto 2) => B"0000000000000",
      Dbg_ARREADY => NLW_U0_Dbg_ARREADY_UNCONNECTED,
      Dbg_ARVALID => '0',
      Dbg_AWADDR(14 downto 2) => B"0000000000000",
      Dbg_AWREADY => NLW_U0_Dbg_AWREADY_UNCONNECTED,
      Dbg_AWVALID => '0',
      Dbg_BREADY => '0',
      Dbg_BRESP(1 downto 0) => NLW_U0_Dbg_BRESP_UNCONNECTED(1 downto 0),
      Dbg_BVALID => NLW_U0_Dbg_BVALID_UNCONNECTED,
      Dbg_Capture => Dbg_Capture,
      Dbg_Clk => Dbg_Clk,
      Dbg_Continue => NLW_U0_Dbg_Continue_UNCONNECTED,
      Dbg_Disable => Dbg_Disable,
      Dbg_Intr => NLW_U0_Dbg_Intr_UNCONNECTED,
      Dbg_RDATA(31 downto 0) => NLW_U0_Dbg_RDATA_UNCONNECTED(31 downto 0),
      Dbg_RREADY => '0',
      Dbg_RRESP(1 downto 0) => NLW_U0_Dbg_RRESP_UNCONNECTED(1 downto 0),
      Dbg_RVALID => NLW_U0_Dbg_RVALID_UNCONNECTED,
      Dbg_Reg_En(0 to 7) => Dbg_Reg_En(0 to 7),
      Dbg_Shift => Dbg_Shift,
      Dbg_Stop => '0',
      Dbg_TDI => Dbg_TDI,
      Dbg_TDO => Dbg_TDO,
      Dbg_Trace_Clk => '0',
      Dbg_Trace_Data(0 to 35) => NLW_U0_Dbg_Trace_Data_UNCONNECTED(0 to 35),
      Dbg_Trace_Ready => '0',
      Dbg_Trace_Valid => NLW_U0_Dbg_Trace_Valid_UNCONNECTED,
      Dbg_Trig_Ack_In(0 to 7) => B"00000000",
      Dbg_Trig_Ack_Out(0 to 7) => NLW_U0_Dbg_Trig_Ack_Out_UNCONNECTED(0 to 7),
      Dbg_Trig_In(0 to 7) => NLW_U0_Dbg_Trig_In_UNCONNECTED(0 to 7),
      Dbg_Trig_Out(0 to 7) => B"00000000",
      Dbg_Update => Dbg_Update,
      Dbg_WDATA(31 downto 0) => B"00000000000000000000000000000000",
      Dbg_WREADY => NLW_U0_Dbg_WREADY_UNCONNECTED,
      Dbg_WVALID => '0',
      Dbg_Wakeup => NLW_U0_Dbg_Wakeup_UNCONNECTED,
      Debug_Rst => Debug_Rst,
      Ext_BRK => '0',
      Ext_NM_BRK => '0',
      Hibernate => NLW_U0_Hibernate_UNCONNECTED,
      ICE => ICE,
      IFetch => IFetch,
      IReady => IReady,
      IUE => IUE,
      IWAIT => IWAIT,
      I_AS => I_AS,
      Instr(0 to 31) => Instr(0 to 31),
      Instr_Addr(0 to 31) => Instr_Addr(0 to 31),
      Interrupt => Interrupt,
      Interrupt_Ack(0 to 1) => Interrupt_Ack(0 to 1),
      Interrupt_Address(0 to 31) => Interrupt_Address(0 to 31),
      LOCKSTEP_Master_Out(0 to 4095) => NLW_U0_LOCKSTEP_Master_Out_UNCONNECTED(0 to 4095),
      LOCKSTEP_Out(0 to 4095) => NLW_U0_LOCKSTEP_Out_UNCONNECTED(0 to 4095),
      LOCKSTEP_Slave_In(0 to 4095) => B"[encoded data, 4096 characters]",
      M0_AXIS_TDATA(31 downto 0) => NLW_U0_M0_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M0_AXIS_TLAST => NLW_U0_M0_AXIS_TLAST_UNCONNECTED,
      M0_AXIS_TREADY => '0',
      M0_AXIS_TVALID => NLW_U0_M0_AXIS_TVALID_UNCONNECTED,
      M10_AXIS_TDATA(31 downto 0) => NLW_U0_M10_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M10_AXIS_TLAST => NLW_U0_M10_AXIS_TLAST_UNCONNECTED,
      M10_AXIS_TREADY => '0',
      M10_AXIS_TVALID => NLW_U0_M10_AXIS_TVALID_UNCONNECTED,
      M11_AXIS_TDATA(31 downto 0) => NLW_U0_M11_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M11_AXIS_TLAST => NLW_U0_M11_AXIS_TLAST_UNCONNECTED,
      M11_AXIS_TREADY => '0',
      M11_AXIS_TVALID => NLW_U0_M11_AXIS_TVALID_UNCONNECTED,
      M12_AXIS_TDATA(31 downto 0) => NLW_U0_M12_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M12_AXIS_TLAST => NLW_U0_M12_AXIS_TLAST_UNCONNECTED,
      M12_AXIS_TREADY => '0',
      M12_AXIS_TVALID => NLW_U0_M12_AXIS_TVALID_UNCONNECTED,
      M13_AXIS_TDATA(31 downto 0) => NLW_U0_M13_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M13_AXIS_TLAST => NLW_U0_M13_AXIS_TLAST_UNCONNECTED,
      M13_AXIS_TREADY => '0',
      M13_AXIS_TVALID => NLW_U0_M13_AXIS_TVALID_UNCONNECTED,
      M14_AXIS_TDATA(31 downto 0) => NLW_U0_M14_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M14_AXIS_TLAST => NLW_U0_M14_AXIS_TLAST_UNCONNECTED,
      M14_AXIS_TREADY => '0',
      M14_AXIS_TVALID => NLW_U0_M14_AXIS_TVALID_UNCONNECTED,
      M15_AXIS_TDATA(31 downto 0) => NLW_U0_M15_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M15_AXIS_TLAST => NLW_U0_M15_AXIS_TLAST_UNCONNECTED,
      M15_AXIS_TREADY => '0',
      M15_AXIS_TVALID => NLW_U0_M15_AXIS_TVALID_UNCONNECTED,
      M1_AXIS_TDATA(31 downto 0) => NLW_U0_M1_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M1_AXIS_TLAST => NLW_U0_M1_AXIS_TLAST_UNCONNECTED,
      M1_AXIS_TREADY => '0',
      M1_AXIS_TVALID => NLW_U0_M1_AXIS_TVALID_UNCONNECTED,
      M2_AXIS_TDATA(31 downto 0) => NLW_U0_M2_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M2_AXIS_TLAST => NLW_U0_M2_AXIS_TLAST_UNCONNECTED,
      M2_AXIS_TREADY => '0',
      M2_AXIS_TVALID => NLW_U0_M2_AXIS_TVALID_UNCONNECTED,
      M3_AXIS_TDATA(31 downto 0) => NLW_U0_M3_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M3_AXIS_TLAST => NLW_U0_M3_AXIS_TLAST_UNCONNECTED,
      M3_AXIS_TREADY => '0',
      M3_AXIS_TVALID => NLW_U0_M3_AXIS_TVALID_UNCONNECTED,
      M4_AXIS_TDATA(31 downto 0) => NLW_U0_M4_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M4_AXIS_TLAST => NLW_U0_M4_AXIS_TLAST_UNCONNECTED,
      M4_AXIS_TREADY => '0',
      M4_AXIS_TVALID => NLW_U0_M4_AXIS_TVALID_UNCONNECTED,
      M5_AXIS_TDATA(31 downto 0) => NLW_U0_M5_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M5_AXIS_TLAST => NLW_U0_M5_AXIS_TLAST_UNCONNECTED,
      M5_AXIS_TREADY => '0',
      M5_AXIS_TVALID => NLW_U0_M5_AXIS_TVALID_UNCONNECTED,
      M6_AXIS_TDATA(31 downto 0) => NLW_U0_M6_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M6_AXIS_TLAST => NLW_U0_M6_AXIS_TLAST_UNCONNECTED,
      M6_AXIS_TREADY => '0',
      M6_AXIS_TVALID => NLW_U0_M6_AXIS_TVALID_UNCONNECTED,
      M7_AXIS_TDATA(31 downto 0) => NLW_U0_M7_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M7_AXIS_TLAST => NLW_U0_M7_AXIS_TLAST_UNCONNECTED,
      M7_AXIS_TREADY => '0',
      M7_AXIS_TVALID => NLW_U0_M7_AXIS_TVALID_UNCONNECTED,
      M8_AXIS_TDATA(31 downto 0) => NLW_U0_M8_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M8_AXIS_TLAST => NLW_U0_M8_AXIS_TLAST_UNCONNECTED,
      M8_AXIS_TREADY => '0',
      M8_AXIS_TVALID => NLW_U0_M8_AXIS_TVALID_UNCONNECTED,
      M9_AXIS_TDATA(31 downto 0) => NLW_U0_M9_AXIS_TDATA_UNCONNECTED(31 downto 0),
      M9_AXIS_TLAST => NLW_U0_M9_AXIS_TLAST_UNCONNECTED,
      M9_AXIS_TREADY => '0',
      M9_AXIS_TVALID => NLW_U0_M9_AXIS_TVALID_UNCONNECTED,
      MB_Error => NLW_U0_MB_Error_UNCONNECTED,
      MB_Halted => NLW_U0_MB_Halted_UNCONNECTED,
      M_AXI_DC_ACADDR(31 downto 0) => B"00000000000000000000000000000000",
      M_AXI_DC_ACPROT(2 downto 0) => B"000",
      M_AXI_DC_ACREADY => NLW_U0_M_AXI_DC_ACREADY_UNCONNECTED,
      M_AXI_DC_ACSNOOP(3 downto 0) => B"0000",
      M_AXI_DC_ACVALID => '0',
      M_AXI_DC_ARADDR(31 downto 0) => NLW_U0_M_AXI_DC_ARADDR_UNCONNECTED(31 downto 0),
      M_AXI_DC_ARBAR(1 downto 0) => NLW_U0_M_AXI_DC_ARBAR_UNCONNECTED(1 downto 0),
      M_AXI_DC_ARBURST(1 downto 0) => NLW_U0_M_AXI_DC_ARBURST_UNCONNECTED(1 downto 0),
      M_AXI_DC_ARCACHE(3 downto 0) => NLW_U0_M_AXI_DC_ARCACHE_UNCONNECTED(3 downto 0),
      M_AXI_DC_ARDOMAIN(1 downto 0) => NLW_U0_M_AXI_DC_ARDOMAIN_UNCONNECTED(1 downto 0),
      M_AXI_DC_ARID(0) => NLW_U0_M_AXI_DC_ARID_UNCONNECTED(0),
      M_AXI_DC_ARLEN(7 downto 0) => NLW_U0_M_AXI_DC_ARLEN_UNCONNECTED(7 downto 0),
      M_AXI_DC_ARLOCK => NLW_U0_M_AXI_DC_ARLOCK_UNCONNECTED,
      M_AXI_DC_ARPROT(2 downto 0) => NLW_U0_M_AXI_DC_ARPROT_UNCONNECTED(2 downto 0),
      M_AXI_DC_ARQOS(3 downto 0) => NLW_U0_M_AXI_DC_ARQOS_UNCONNECTED(3 downto 0),
      M_AXI_DC_ARREADY => '0',
      M_AXI_DC_ARSIZE(2 downto 0) => NLW_U0_M_AXI_DC_ARSIZE_UNCONNECTED(2 downto 0),
      M_AXI_DC_ARSNOOP(3 downto 0) => NLW_U0_M_AXI_DC_ARSNOOP_UNCONNECTED(3 downto 0),
      M_AXI_DC_ARUSER(4 downto 0) => NLW_U0_M_AXI_DC_ARUSER_UNCONNECTED(4 downto 0),
      M_AXI_DC_ARVALID => NLW_U0_M_AXI_DC_ARVALID_UNCONNECTED,
      M_AXI_DC_AWADDR(31 downto 0) => NLW_U0_M_AXI_DC_AWADDR_UNCONNECTED(31 downto 0),
      M_AXI_DC_AWBAR(1 downto 0) => NLW_U0_M_AXI_DC_AWBAR_UNCONNECTED(1 downto 0),
      M_AXI_DC_AWBURST(1 downto 0) => NLW_U0_M_AXI_DC_AWBURST_UNCONNECTED(1 downto 0),
      M_AXI_DC_AWCACHE(3 downto 0) => NLW_U0_M_AXI_DC_AWCACHE_UNCONNECTED(3 downto 0),
      M_AXI_DC_AWDOMAIN(1 downto 0) => NLW_U0_M_AXI_DC_AWDOMAIN_UNCONNECTED(1 downto 0),
      M_AXI_DC_AWID(0) => NLW_U0_M_AXI_DC_AWID_UNCONNECTED(0),
      M_AXI_DC_AWLEN(7 downto 0) => NLW_U0_M_AXI_DC_AWLEN_UNCONNECTED(7 downto 0),
      M_AXI_DC_AWLOCK => NLW_U0_M_AXI_DC_AWLOCK_UNCONNECTED,
      M_AXI_DC_AWPROT(2 downto 0) => NLW_U0_M_AXI_DC_AWPROT_UNCONNECTED(2 downto 0),
      M_AXI_DC_AWQOS(3 downto 0) => NLW_U0_M_AXI_DC_AWQOS_UNCONNECTED(3 downto 0),
      M_AXI_DC_AWREADY => '0',
      M_AXI_DC_AWSIZE(2 downto 0) => NLW_U0_M_AXI_DC_AWSIZE_UNCONNECTED(2 downto 0),
      M_AXI_DC_AWSNOOP(2 downto 0) => NLW_U0_M_AXI_DC_AWSNOOP_UNCONNECTED(2 downto 0),
      M_AXI_DC_AWUSER(4 downto 0) => NLW_U0_M_AXI_DC_AWUSER_UNCONNECTED(4 downto 0),
      M_AXI_DC_AWVALID => NLW_U0_M_AXI_DC_AWVALID_UNCONNECTED,
      M_AXI_DC_BID(0) => '0',
      M_AXI_DC_BREADY => NLW_U0_M_AXI_DC_BREADY_UNCONNECTED,
      M_AXI_DC_BRESP(1 downto 0) => B"00",
      M_AXI_DC_BUSER(0) => '0',
      M_AXI_DC_BVALID => '0',
      M_AXI_DC_CDDATA(31 downto 0) => NLW_U0_M_AXI_DC_CDDATA_UNCONNECTED(31 downto 0),
      M_AXI_DC_CDLAST => NLW_U0_M_AXI_DC_CDLAST_UNCONNECTED,
      M_AXI_DC_CDREADY => '0',
      M_AXI_DC_CDVALID => NLW_U0_M_AXI_DC_CDVALID_UNCONNECTED,
      M_AXI_DC_CRREADY => '0',
      M_AXI_DC_CRRESP(4 downto 0) => NLW_U0_M_AXI_DC_CRRESP_UNCONNECTED(4 downto 0),
      M_AXI_DC_CRVALID => NLW_U0_M_AXI_DC_CRVALID_UNCONNECTED,
      M_AXI_DC_RACK => NLW_U0_M_AXI_DC_RACK_UNCONNECTED,
      M_AXI_DC_RDATA(31 downto 0) => B"00000000000000000000000000000000",
      M_AXI_DC_RID(0) => '0',
      M_AXI_DC_RLAST => '0',
      M_AXI_DC_RREADY => NLW_U0_M_AXI_DC_RREADY_UNCONNECTED,
      M_AXI_DC_RRESP(1 downto 0) => B"00",
      M_AXI_DC_RUSER(0) => '0',
      M_AXI_DC_RVALID => '0',
      M_AXI_DC_WACK => NLW_U0_M_AXI_DC_WACK_UNCONNECTED,
      M_AXI_DC_WDATA(31 downto 0) => NLW_U0_M_AXI_DC_WDATA_UNCONNECTED(31 downto 0),
      M_AXI_DC_WLAST => NLW_U0_M_AXI_DC_WLAST_UNCONNECTED,
      M_AXI_DC_WREADY => '0',
      M_AXI_DC_WSTRB(3 downto 0) => NLW_U0_M_AXI_DC_WSTRB_UNCONNECTED(3 downto 0),
      M_AXI_DC_WUSER(0) => NLW_U0_M_AXI_DC_WUSER_UNCONNECTED(0),
      M_AXI_DC_WVALID => NLW_U0_M_AXI_DC_WVALID_UNCONNECTED,
      M_AXI_DP_ARADDR(31 downto 0) => M_AXI_DP_ARADDR(31 downto 0),
      M_AXI_DP_ARBURST(1 downto 0) => NLW_U0_M_AXI_DP_ARBURST_UNCONNECTED(1 downto 0),
      M_AXI_DP_ARCACHE(3 downto 0) => NLW_U0_M_AXI_DP_ARCACHE_UNCONNECTED(3 downto 0),
      M_AXI_DP_ARID(0) => NLW_U0_M_AXI_DP_ARID_UNCONNECTED(0),
      M_AXI_DP_ARLEN(7 downto 0) => NLW_U0_M_AXI_DP_ARLEN_UNCONNECTED(7 downto 0),
      M_AXI_DP_ARLOCK => NLW_U0_M_AXI_DP_ARLOCK_UNCONNECTED,
      M_AXI_DP_ARPROT(2 downto 0) => M_AXI_DP_ARPROT(2 downto 0),
      M_AXI_DP_ARQOS(3 downto 0) => NLW_U0_M_AXI_DP_ARQOS_UNCONNECTED(3 downto 0),
      M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
      M_AXI_DP_ARSIZE(2 downto 0) => NLW_U0_M_AXI_DP_ARSIZE_UNCONNECTED(2 downto 0),
      M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
      M_AXI_DP_AWADDR(31 downto 0) => M_AXI_DP_AWADDR(31 downto 0),
      M_AXI_DP_AWBURST(1 downto 0) => NLW_U0_M_AXI_DP_AWBURST_UNCONNECTED(1 downto 0),
      M_AXI_DP_AWCACHE(3 downto 0) => NLW_U0_M_AXI_DP_AWCACHE_UNCONNECTED(3 downto 0),
      M_AXI_DP_AWID(0) => NLW_U0_M_AXI_DP_AWID_UNCONNECTED(0),
      M_AXI_DP_AWLEN(7 downto 0) => NLW_U0_M_AXI_DP_AWLEN_UNCONNECTED(7 downto 0),
      M_AXI_DP_AWLOCK => NLW_U0_M_AXI_DP_AWLOCK_UNCONNECTED,
      M_AXI_DP_AWPROT(2 downto 0) => M_AXI_DP_AWPROT(2 downto 0),
      M_AXI_DP_AWQOS(3 downto 0) => NLW_U0_M_AXI_DP_AWQOS_UNCONNECTED(3 downto 0),
      M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
      M_AXI_DP_AWSIZE(2 downto 0) => NLW_U0_M_AXI_DP_AWSIZE_UNCONNECTED(2 downto 0),
      M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
      M_AXI_DP_BID(0) => '0',
      M_AXI_DP_BREADY => M_AXI_DP_BREADY,
      M_AXI_DP_BRESP(1 downto 0) => M_AXI_DP_BRESP(1 downto 0),
      M_AXI_DP_BVALID => M_AXI_DP_BVALID,
      M_AXI_DP_RDATA(31 downto 0) => M_AXI_DP_RDATA(31 downto 0),
      M_AXI_DP_RID(0) => '0',
      M_AXI_DP_RLAST => '0',
      M_AXI_DP_RREADY => M_AXI_DP_RREADY,
      M_AXI_DP_RRESP(1 downto 0) => M_AXI_DP_RRESP(1 downto 0),
      M_AXI_DP_RVALID => M_AXI_DP_RVALID,
      M_AXI_DP_WDATA(31 downto 0) => M_AXI_DP_WDATA(31 downto 0),
      M_AXI_DP_WLAST => NLW_U0_M_AXI_DP_WLAST_UNCONNECTED,
      M_AXI_DP_WREADY => M_AXI_DP_WREADY,
      M_AXI_DP_WSTRB(3 downto 0) => M_AXI_DP_WSTRB(3 downto 0),
      M_AXI_DP_WVALID => M_AXI_DP_WVALID,
      M_AXI_IC_ACADDR(31 downto 0) => B"00000000000000000000000000000000",
      M_AXI_IC_ACPROT(2 downto 0) => B"000",
      M_AXI_IC_ACREADY => NLW_U0_M_AXI_IC_ACREADY_UNCONNECTED,
      M_AXI_IC_ACSNOOP(3 downto 0) => B"0000",
      M_AXI_IC_ACVALID => '0',
      M_AXI_IC_ARADDR(31 downto 0) => NLW_U0_M_AXI_IC_ARADDR_UNCONNECTED(31 downto 0),
      M_AXI_IC_ARBAR(1 downto 0) => NLW_U0_M_AXI_IC_ARBAR_UNCONNECTED(1 downto 0),
      M_AXI_IC_ARBURST(1 downto 0) => NLW_U0_M_AXI_IC_ARBURST_UNCONNECTED(1 downto 0),
      M_AXI_IC_ARCACHE(3 downto 0) => NLW_U0_M_AXI_IC_ARCACHE_UNCONNECTED(3 downto 0),
      M_AXI_IC_ARDOMAIN(1 downto 0) => NLW_U0_M_AXI_IC_ARDOMAIN_UNCONNECTED(1 downto 0),
      M_AXI_IC_ARID(0) => NLW_U0_M_AXI_IC_ARID_UNCONNECTED(0),
      M_AXI_IC_ARLEN(7 downto 0) => NLW_U0_M_AXI_IC_ARLEN_UNCONNECTED(7 downto 0),
      M_AXI_IC_ARLOCK => NLW_U0_M_AXI_IC_ARLOCK_UNCONNECTED,
      M_AXI_IC_ARPROT(2 downto 0) => NLW_U0_M_AXI_IC_ARPROT_UNCONNECTED(2 downto 0),
      M_AXI_IC_ARQOS(3 downto 0) => NLW_U0_M_AXI_IC_ARQOS_UNCONNECTED(3 downto 0),
      M_AXI_IC_ARREADY => '0',
      M_AXI_IC_ARSIZE(2 downto 0) => NLW_U0_M_AXI_IC_ARSIZE_UNCONNECTED(2 downto 0),
      M_AXI_IC_ARSNOOP(3 downto 0) => NLW_U0_M_AXI_IC_ARSNOOP_UNCONNECTED(3 downto 0),
      M_AXI_IC_ARUSER(4 downto 0) => NLW_U0_M_AXI_IC_ARUSER_UNCONNECTED(4 downto 0),
      M_AXI_IC_ARVALID => NLW_U0_M_AXI_IC_ARVALID_UNCONNECTED,
      M_AXI_IC_AWADDR(31 downto 0) => NLW_U0_M_AXI_IC_AWADDR_UNCONNECTED(31 downto 0),
      M_AXI_IC_AWBAR(1 downto 0) => NLW_U0_M_AXI_IC_AWBAR_UNCONNECTED(1 downto 0),
      M_AXI_IC_AWBURST(1 downto 0) => NLW_U0_M_AXI_IC_AWBURST_UNCONNECTED(1 downto 0),
      M_AXI_IC_AWCACHE(3 downto 0) => NLW_U0_M_AXI_IC_AWCACHE_UNCONNECTED(3 downto 0),
      M_AXI_IC_AWDOMAIN(1 downto 0) => NLW_U0_M_AXI_IC_AWDOMAIN_UNCONNECTED(1 downto 0),
      M_AXI_IC_AWID(0) => NLW_U0_M_AXI_IC_AWID_UNCONNECTED(0),
      M_AXI_IC_AWLEN(7 downto 0) => NLW_U0_M_AXI_IC_AWLEN_UNCONNECTED(7 downto 0),
      M_AXI_IC_AWLOCK => NLW_U0_M_AXI_IC_AWLOCK_UNCONNECTED,
      M_AXI_IC_AWPROT(2 downto 0) => NLW_U0_M_AXI_IC_AWPROT_UNCONNECTED(2 downto 0),
      M_AXI_IC_AWQOS(3 downto 0) => NLW_U0_M_AXI_IC_AWQOS_UNCONNECTED(3 downto 0),
      M_AXI_IC_AWREADY => '0',
      M_AXI_IC_AWSIZE(2 downto 0) => NLW_U0_M_AXI_IC_AWSIZE_UNCONNECTED(2 downto 0),
      M_AXI_IC_AWSNOOP(2 downto 0) => NLW_U0_M_AXI_IC_AWSNOOP_UNCONNECTED(2 downto 0),
      M_AXI_IC_AWUSER(4 downto 0) => NLW_U0_M_AXI_IC_AWUSER_UNCONNECTED(4 downto 0),
      M_AXI_IC_AWVALID => NLW_U0_M_AXI_IC_AWVALID_UNCONNECTED,
      M_AXI_IC_BID(0) => '0',
      M_AXI_IC_BREADY => NLW_U0_M_AXI_IC_BREADY_UNCONNECTED,
      M_AXI_IC_BRESP(1 downto 0) => B"00",
      M_AXI_IC_BUSER(0) => '0',
      M_AXI_IC_BVALID => '0',
      M_AXI_IC_CDDATA(31 downto 0) => NLW_U0_M_AXI_IC_CDDATA_UNCONNECTED(31 downto 0),
      M_AXI_IC_CDLAST => NLW_U0_M_AXI_IC_CDLAST_UNCONNECTED,
      M_AXI_IC_CDREADY => '0',
      M_AXI_IC_CDVALID => NLW_U0_M_AXI_IC_CDVALID_UNCONNECTED,
      M_AXI_IC_CRREADY => '0',
      M_AXI_IC_CRRESP(4 downto 0) => NLW_U0_M_AXI_IC_CRRESP_UNCONNECTED(4 downto 0),
      M_AXI_IC_CRVALID => NLW_U0_M_AXI_IC_CRVALID_UNCONNECTED,
      M_AXI_IC_RACK => NLW_U0_M_AXI_IC_RACK_UNCONNECTED,
      M_AXI_IC_RDATA(31 downto 0) => B"00000000000000000000000000000000",
      M_AXI_IC_RID(0) => '0',
      M_AXI_IC_RLAST => '0',
      M_AXI_IC_RREADY => NLW_U0_M_AXI_IC_RREADY_UNCONNECTED,
      M_AXI_IC_RRESP(1 downto 0) => B"00",
      M_AXI_IC_RUSER(0) => '0',
      M_AXI_IC_RVALID => '0',
      M_AXI_IC_WACK => NLW_U0_M_AXI_IC_WACK_UNCONNECTED,
      M_AXI_IC_WDATA(31 downto 0) => NLW_U0_M_AXI_IC_WDATA_UNCONNECTED(31 downto 0),
      M_AXI_IC_WLAST => NLW_U0_M_AXI_IC_WLAST_UNCONNECTED,
      M_AXI_IC_WREADY => '0',
      M_AXI_IC_WSTRB(3 downto 0) => NLW_U0_M_AXI_IC_WSTRB_UNCONNECTED(3 downto 0),
      M_AXI_IC_WUSER(0) => NLW_U0_M_AXI_IC_WUSER_UNCONNECTED(0),
      M_AXI_IC_WVALID => NLW_U0_M_AXI_IC_WVALID_UNCONNECTED,
      M_AXI_IP_ARADDR(31 downto 0) => NLW_U0_M_AXI_IP_ARADDR_UNCONNECTED(31 downto 0),
      M_AXI_IP_ARBURST(1 downto 0) => NLW_U0_M_AXI_IP_ARBURST_UNCONNECTED(1 downto 0),
      M_AXI_IP_ARCACHE(3 downto 0) => NLW_U0_M_AXI_IP_ARCACHE_UNCONNECTED(3 downto 0),
      M_AXI_IP_ARID(0) => NLW_U0_M_AXI_IP_ARID_UNCONNECTED(0),
      M_AXI_IP_ARLEN(7 downto 0) => NLW_U0_M_AXI_IP_ARLEN_UNCONNECTED(7 downto 0),
      M_AXI_IP_ARLOCK => NLW_U0_M_AXI_IP_ARLOCK_UNCONNECTED,
      M_AXI_IP_ARPROT(2 downto 0) => NLW_U0_M_AXI_IP_ARPROT_UNCONNECTED(2 downto 0),
      M_AXI_IP_ARQOS(3 downto 0) => NLW_U0_M_AXI_IP_ARQOS_UNCONNECTED(3 downto 0),
      M_AXI_IP_ARREADY => '0',
      M_AXI_IP_ARSIZE(2 downto 0) => NLW_U0_M_AXI_IP_ARSIZE_UNCONNECTED(2 downto 0),
      M_AXI_IP_ARVALID => NLW_U0_M_AXI_IP_ARVALID_UNCONNECTED,
      M_AXI_IP_AWADDR(31 downto 0) => NLW_U0_M_AXI_IP_AWADDR_UNCONNECTED(31 downto 0),
      M_AXI_IP_AWBURST(1 downto 0) => NLW_U0_M_AXI_IP_AWBURST_UNCONNECTED(1 downto 0),
      M_AXI_IP_AWCACHE(3 downto 0) => NLW_U0_M_AXI_IP_AWCACHE_UNCONNECTED(3 downto 0),
      M_AXI_IP_AWID(0) => NLW_U0_M_AXI_IP_AWID_UNCONNECTED(0),
      M_AXI_IP_AWLEN(7 downto 0) => NLW_U0_M_AXI_IP_AWLEN_UNCONNECTED(7 downto 0),
      M_AXI_IP_AWLOCK => NLW_U0_M_AXI_IP_AWLOCK_UNCONNECTED,
      M_AXI_IP_AWPROT(2 downto 0) => NLW_U0_M_AXI_IP_AWPROT_UNCONNECTED(2 downto 0),
      M_AXI_IP_AWQOS(3 downto 0) => NLW_U0_M_AXI_IP_AWQOS_UNCONNECTED(3 downto 0),
      M_AXI_IP_AWREADY => '0',
      M_AXI_IP_AWSIZE(2 downto 0) => NLW_U0_M_AXI_IP_AWSIZE_UNCONNECTED(2 downto 0),
      M_AXI_IP_AWVALID => NLW_U0_M_AXI_IP_AWVALID_UNCONNECTED,
      M_AXI_IP_BID(0) => '0',
      M_AXI_IP_BREADY => NLW_U0_M_AXI_IP_BREADY_UNCONNECTED,
      M_AXI_IP_BRESP(1 downto 0) => B"00",
      M_AXI_IP_BVALID => '0',
      M_AXI_IP_RDATA(31 downto 0) => B"00000000000000000000000000000000",
      M_AXI_IP_RID(0) => '0',
      M_AXI_IP_RLAST => '0',
      M_AXI_IP_RREADY => NLW_U0_M_AXI_IP_RREADY_UNCONNECTED,
      M_AXI_IP_RRESP(1 downto 0) => B"00",
      M_AXI_IP_RVALID => '0',
      M_AXI_IP_WDATA(31 downto 0) => NLW_U0_M_AXI_IP_WDATA_UNCONNECTED(31 downto 0),
      M_AXI_IP_WLAST => NLW_U0_M_AXI_IP_WLAST_UNCONNECTED,
      M_AXI_IP_WREADY => '0',
      M_AXI_IP_WSTRB(3 downto 0) => NLW_U0_M_AXI_IP_WSTRB_UNCONNECTED(3 downto 0),
      M_AXI_IP_WVALID => NLW_U0_M_AXI_IP_WVALID_UNCONNECTED,
      Mb_Reset => '0',
      Non_Secure(0 to 3) => B"0000",
      Pause => '0',
      Pause_Ack => NLW_U0_Pause_Ack_UNCONNECTED,
      RAM_From(255 downto 0) => NLW_U0_RAM_From_UNCONNECTED(255 downto 0),
      RAM_To(255 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
      Read_Strobe => Read_Strobe,
      Reset => Reset,
      Reset_Mode(0 to 1) => B"00",
      S0_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S0_AXIS_TLAST => '0',
      S0_AXIS_TREADY => NLW_U0_S0_AXIS_TREADY_UNCONNECTED,
      S0_AXIS_TVALID => '0',
      S10_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S10_AXIS_TLAST => '0',
      S10_AXIS_TREADY => NLW_U0_S10_AXIS_TREADY_UNCONNECTED,
      S10_AXIS_TVALID => '0',
      S11_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S11_AXIS_TLAST => '0',
      S11_AXIS_TREADY => NLW_U0_S11_AXIS_TREADY_UNCONNECTED,
      S11_AXIS_TVALID => '0',
      S12_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S12_AXIS_TLAST => '0',
      S12_AXIS_TREADY => NLW_U0_S12_AXIS_TREADY_UNCONNECTED,
      S12_AXIS_TVALID => '0',
      S13_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S13_AXIS_TLAST => '0',
      S13_AXIS_TREADY => NLW_U0_S13_AXIS_TREADY_UNCONNECTED,
      S13_AXIS_TVALID => '0',
      S14_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S14_AXIS_TLAST => '0',
      S14_AXIS_TREADY => NLW_U0_S14_AXIS_TREADY_UNCONNECTED,
      S14_AXIS_TVALID => '0',
      S15_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S15_AXIS_TLAST => '0',
      S15_AXIS_TREADY => NLW_U0_S15_AXIS_TREADY_UNCONNECTED,
      S15_AXIS_TVALID => '0',
      S1_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S1_AXIS_TLAST => '0',
      S1_AXIS_TREADY => NLW_U0_S1_AXIS_TREADY_UNCONNECTED,
      S1_AXIS_TVALID => '0',
      S2_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S2_AXIS_TLAST => '0',
      S2_AXIS_TREADY => NLW_U0_S2_AXIS_TREADY_UNCONNECTED,
      S2_AXIS_TVALID => '0',
      S3_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S3_AXIS_TLAST => '0',
      S3_AXIS_TREADY => NLW_U0_S3_AXIS_TREADY_UNCONNECTED,
      S3_AXIS_TVALID => '0',
      S4_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S4_AXIS_TLAST => '0',
      S4_AXIS_TREADY => NLW_U0_S4_AXIS_TREADY_UNCONNECTED,
      S4_AXIS_TVALID => '0',
      S5_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S5_AXIS_TLAST => '0',
      S5_AXIS_TREADY => NLW_U0_S5_AXIS_TREADY_UNCONNECTED,
      S5_AXIS_TVALID => '0',
      S6_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S6_AXIS_TLAST => '0',
      S6_AXIS_TREADY => NLW_U0_S6_AXIS_TREADY_UNCONNECTED,
      S6_AXIS_TVALID => '0',
      S7_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S7_AXIS_TLAST => '0',
      S7_AXIS_TREADY => NLW_U0_S7_AXIS_TREADY_UNCONNECTED,
      S7_AXIS_TVALID => '0',
      S8_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S8_AXIS_TLAST => '0',
      S8_AXIS_TREADY => NLW_U0_S8_AXIS_TREADY_UNCONNECTED,
      S8_AXIS_TVALID => '0',
      S9_AXIS_TDATA(31 downto 0) => B"00000000000000000000000000000000",
      S9_AXIS_TLAST => '0',
      S9_AXIS_TREADY => NLW_U0_S9_AXIS_TREADY_UNCONNECTED,
      S9_AXIS_TVALID => '0',
      Scan_En => '0',
      Scan_Reset => '0',
      Scan_Reset_Sel => '0',
      Sleep => NLW_U0_Sleep_UNCONNECTED,
      Suspend => NLW_U0_Suspend_UNCONNECTED,
      Trace_DCache_Hit => NLW_U0_Trace_DCache_Hit_UNCONNECTED,
      Trace_DCache_Rdy => NLW_U0_Trace_DCache_Rdy_UNCONNECTED,
      Trace_DCache_Read => NLW_U0_Trace_DCache_Read_UNCONNECTED,
      Trace_DCache_Req => NLW_U0_Trace_DCache_Req_UNCONNECTED,
      Trace_Data_Access => NLW_U0_Trace_Data_Access_UNCONNECTED,
      Trace_Data_Address(0 to 31) => NLW_U0_Trace_Data_Address_UNCONNECTED(0 to 31),
      Trace_Data_Byte_Enable(0 to 3) => NLW_U0_Trace_Data_Byte_Enable_UNCONNECTED(0 to 3),
      Trace_Data_Read => NLW_U0_Trace_Data_Read_UNCONNECTED,
      Trace_Data_Write => NLW_U0_Trace_Data_Write_UNCONNECTED,
      Trace_Data_Write_Value(0 to 31) => NLW_U0_Trace_Data_Write_Value_UNCONNECTED(0 to 31),
      Trace_Delay_Slot => NLW_U0_Trace_Delay_Slot_UNCONNECTED,
      Trace_EX_PipeRun => NLW_U0_Trace_EX_PipeRun_UNCONNECTED,
      Trace_Exception_Kind(0 to 4) => NLW_U0_Trace_Exception_Kind_UNCONNECTED(0 to 4),
      Trace_Exception_Taken => NLW_U0_Trace_Exception_Taken_UNCONNECTED,
      Trace_ICache_Hit => NLW_U0_Trace_ICache_Hit_UNCONNECTED,
      Trace_ICache_Rdy => NLW_U0_Trace_ICache_Rdy_UNCONNECTED,
      Trace_ICache_Req => NLW_U0_Trace_ICache_Req_UNCONNECTED,
      Trace_Instruction(0 to 31) => NLW_U0_Trace_Instruction_UNCONNECTED(0 to 31),
      Trace_Jump_Hit => NLW_U0_Trace_Jump_Hit_UNCONNECTED,
      Trace_Jump_Taken => NLW_U0_Trace_Jump_Taken_UNCONNECTED,
      Trace_MB_Halted => NLW_U0_Trace_MB_Halted_UNCONNECTED,
      Trace_MEM_PipeRun => NLW_U0_Trace_MEM_PipeRun_UNCONNECTED,
      Trace_MSR_Reg(0 to 14) => NLW_U0_Trace_MSR_Reg_UNCONNECTED(0 to 14),
      Trace_New_Reg_Value(0 to 31) => NLW_U0_Trace_New_Reg_Value_UNCONNECTED(0 to 31),
      Trace_OF_PipeRun => NLW_U0_Trace_OF_PipeRun_UNCONNECTED,
      Trace_PC(0 to 31) => NLW_U0_Trace_PC_UNCONNECTED(0 to 31),
      Trace_PID_Reg(0 to 7) => NLW_U0_Trace_PID_Reg_UNCONNECTED(0 to 7),
      Trace_Reg_Addr(0 to 4) => NLW_U0_Trace_Reg_Addr_UNCONNECTED(0 to 4),
      Trace_Reg_Write => NLW_U0_Trace_Reg_Write_UNCONNECTED,
      Trace_Valid_Instr => NLW_U0_Trace_Valid_Instr_UNCONNECTED,
      Wakeup(0 to 1) => B"00",
      Write_Strobe => Write_Strobe
    );
end STRUCTURE;
