{
	"version": "1.0",
	"modules": {
		"design_1": {
			"proto_instances": {
				"/axi_gpio_0/S_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "s_axi_aclk"},
						"ARADDR": { "actual": "s_axi_araddr"},
						"ARESETN": { "actual": "s_axi_aresetn"},
						"ARREADY": { "actual": "s_axi_arready"},
						"ARVALID": { "actual": "s_axi_arvalid"},
						"AWADDR": { "actual": "s_axi_awaddr"},
						"AWREADY": { "actual": "s_axi_awready"},
						"AWVALID": { "actual": "s_axi_awvalid"},
						"BREADY": { "actual": "s_axi_bready"},
						"BRESP": { "actual": "s_axi_bresp"},
						"BVALID": { "actual": "s_axi_bvalid"},
						"RDATA": { "actual": "s_axi_rdata"},
						"RREADY": { "actual": "s_axi_rready"},
						"RRESP": { "actual": "s_axi_rresp"},
						"RVALID": { "actual": "s_axi_rvalid"},
						"WDATA": { "actual": "s_axi_wdata"},
						"WREADY": { "actual": "s_axi_wready"},
						"WSTRB": { "actual": "s_axi_wstrb"},
						"WVALID": { "actual": "s_axi_wvalid"}
					}
				},
				"/microblaze_0/M_AXI_DP": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "Clk"},
						"ARADDR": { "actual": "M_AXI_DP_ARADDR"},
						"ARESET": { "actual": "Reset"},
						"ARPROT": { "actual": "M_AXI_DP_ARPROT"},
						"ARREADY": { "actual": "M_AXI_DP_ARREADY"},
						"ARVALID": { "actual": "M_AXI_DP_ARVALID"},
						"AWADDR": { "actual": "M_AXI_DP_AWADDR"},
						"AWPROT": { "actual": "M_AXI_DP_AWPROT"},
						"AWREADY": { "actual": "M_AXI_DP_AWREADY"},
						"AWVALID": { "actual": "M_AXI_DP_AWVALID"},
						"BREADY": { "actual": "M_AXI_DP_BREADY"},
						"BRESP": { "actual": "M_AXI_DP_BRESP"},
						"BVALID": { "actual": "M_AXI_DP_BVALID"},
						"RDATA": { "actual": "M_AXI_DP_RDATA"},
						"RREADY": { "actual": "M_AXI_DP_RREADY"},
						"RRESP": { "actual": "M_AXI_DP_RRESP"},
						"RVALID": { "actual": "M_AXI_DP_RVALID"},
						"WDATA": { "actual": "M_AXI_DP_WDATA"},
						"WREADY": { "actual": "M_AXI_DP_WREADY"},
						"WSTRB": { "actual": "M_AXI_DP_WSTRB"},
						"WVALID": { "actual": "M_AXI_DP_WVALID"}
					}
				},
				"/microblaze_0_axi_periph/M00_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M00_ACLK"},
						"ARADDR": { "actual": "M00_AXI_araddr"},
						"ARESETN": { "actual": "ARESETN"},
						"ARREADY": { "actual": "M00_AXI_arready"},
						"ARVALID": { "actual": "M00_AXI_arvalid"},
						"AWADDR": { "actual": "M00_AXI_awaddr"},
						"AWREADY": { "actual": "M00_AXI_awready"},
						"AWVALID": { "actual": "M00_AXI_awvalid"},
						"BREADY": { "actual": "M00_AXI_bready"},
						"BRESP": { "actual": "M00_AXI_bresp"},
						"BVALID": { "actual": "M00_AXI_bvalid"},
						"RDATA": { "actual": "M00_AXI_rdata"},
						"RREADY": { "actual": "M00_AXI_rready"},
						"RRESP": { "actual": "M00_AXI_rresp"},
						"RVALID": { "actual": "M00_AXI_rvalid"},
						"WDATA": { "actual": "M00_AXI_wdata"},
						"WREADY": { "actual": "M00_AXI_wready"},
						"WSTRB": { "actual": "M00_AXI_wstrb"},
						"WVALID": { "actual": "M00_AXI_wvalid"}
					}
				},
				"/microblaze_0_axi_periph/S00_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "S00_ACLK"},
						"ARADDR": { "actual": "S00_AXI_araddr"},
						"ARESETN": { "actual": "ARESETN"},
						"ARREADY": { "actual": "S00_AXI_arready"},
						"ARVALID": { "actual": "S00_AXI_arvalid"},
						"AWADDR": { "actual": "S00_AXI_awaddr"},
						"AWREADY": { "actual": "S00_AXI_awready"},
						"AWVALID": { "actual": "S00_AXI_awvalid"},
						"BREADY": { "actual": "S00_AXI_bready"},
						"BRESP": { "actual": "S00_AXI_bresp"},
						"BVALID": { "actual": "S00_AXI_bvalid"},
						"RDATA": { "actual": "S00_AXI_rdata"},
						"RREADY": { "actual": "S00_AXI_rready"},
						"RRESP": { "actual": "S00_AXI_rresp"},
						"RVALID": { "actual": "S00_AXI_rvalid"},
						"WDATA": { "actual": "S00_AXI_wdata"},
						"WREADY": { "actual": "S00_AXI_wready"},
						"WSTRB": { "actual": "S00_AXI_wstrb"},
						"WVALID": { "actual": "S00_AXI_wvalid"}
					}
				},
				"/microblaze_0_axi_periph/s00_couplers/M_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M_ACLK"},
						"ARADDR": { "actual": "M_AXI_araddr"},
						"ARESETN": { "actual": "M_ARESETN"},
						"ARREADY": { "actual": "M_AXI_arready"},
						"ARVALID": { "actual": "M_AXI_arvalid"},
						"AWADDR": { "actual": "M_AXI_awaddr"},
						"AWREADY": { "actual": "M_AXI_awready"},
						"AWVALID": { "actual": "M_AXI_awvalid"},
						"BREADY": { "actual": "M_AXI_bready"},
						"BRESP": { "actual": "M_AXI_bresp"},
						"BVALID": { "actual": "M_AXI_bvalid"},
						"RDATA": { "actual": "M_AXI_rdata"},
						"RREADY": { "actual": "M_AXI_rready"},
						"RRESP": { "actual": "M_AXI_rresp"},
						"RVALID": { "actual": "M_AXI_rvalid"},
						"WDATA": { "actual": "M_AXI_wdata"},
						"WREADY": { "actual": "M_AXI_wready"},
						"WSTRB": { "actual": "M_AXI_wstrb"},
						"WVALID": { "actual": "M_AXI_wvalid"}
					}
				},
				"/microblaze_0_axi_periph/s00_couplers/S_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "S_ACLK"},
						"ARADDR": { "actual": "S_AXI_araddr"},
						"ARESETN": { "actual": "S_ARESETN"},
						"ARREADY": { "actual": "S_AXI_arready"},
						"ARVALID": { "actual": "S_AXI_arvalid"},
						"AWADDR": { "actual": "S_AXI_awaddr"},
						"AWREADY": { "actual": "S_AXI_awready"},
						"AWVALID": { "actual": "S_AXI_awvalid"},
						"BREADY": { "actual": "S_AXI_bready"},
						"BRESP": { "actual": "S_AXI_bresp"},
						"BVALID": { "actual": "S_AXI_bvalid"},
						"RDATA": { "actual": "S_AXI_rdata"},
						"RREADY": { "actual": "S_AXI_rready"},
						"RRESP": { "actual": "S_AXI_rresp"},
						"RVALID": { "actual": "S_AXI_rvalid"},
						"WDATA": { "actual": "S_AXI_wdata"},
						"WREADY": { "actual": "S_AXI_wready"},
						"WSTRB": { "actual": "S_AXI_wstrb"},
						"WVALID": { "actual": "S_AXI_wvalid"}
					}
				}
			}
		}
	}
}
