
*** Running vivado
    with args -log design_1_rst_clk_wiz_1_100M_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_rst_clk_wiz_1_100M_0.tcl


****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source design_1_rst_clk_wiz_1_100M_0.tcl -notrace
Command: synth_design -top design_1_rst_clk_wiz_1_100M_0 -part xcku5p-ffvb676-2-e -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcku5p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcku5p'
INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-e
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 7012 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1448.227 ; gain = 58.766
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'design_1_rst_clk_wiz_1_100M_0' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/synth/design_1_rst_clk_wiz_1_100M_0.vhd:74]
	Parameter C_FAMILY bound to: kintexuplus - type: string 
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b1 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at 'c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/synth/design_1_rst_clk_wiz_1_100M_0.vhd:129]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
	Parameter C_FAMILY bound to: kintexuplus - type: string 
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b1 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
	Parameter C_NUM_BUS_RST bound to: 1 - type: integer 
	Parameter C_NUM_PERP_RST bound to: 1 - type: integer 
	Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer 
	Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
	Parameter INIT bound to: 1'b1 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
	Parameter INIT bound to: 1'b0 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
	Parameter INIT bound to: 1'b1 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
	Parameter INIT bound to: 1'b0 
	Parameter IS_C_INVERTED bound to: 1'b0 
	Parameter IS_D_INVERTED bound to: 1'b0 
	Parameter IS_R_INVERTED bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
INFO: [Synth 8-638] synthesizing module 'lpf' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
	Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer 
	Parameter C_EXT_RESET_HIGH bound to: 1'b1 
	Parameter C_AUX_RESET_HIGH bound to: 1'b0 
INFO: [Synth 8-3491] module 'SRL16' declared at 'C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684' bound to instance 'POR_SRL_I' of component 'SRL16' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
INFO: [Synth 8-6157] synthesizing module 'SRL16' [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (1#1) [C:/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77684]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
	Parameter C_CDC_TYPE bound to: 1 - type: integer 
	Parameter C_RESET_STATE bound to: 0 - type: integer 
	Parameter C_SINGLE_BIT bound to: 1 - type: integer 
	Parameter C_FLOP_INPUT bound to: 0 - type: integer 
	Parameter C_VECTOR_WIDTH bound to: 2 - type: integer 
	Parameter C_MTBF_STAGES bound to: 4 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (2#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'lpf' (3#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
	Parameter C_SIZE bound to: 6 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (4#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (5#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (6#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
INFO: [Synth 8-256] done synthesizing module 'design_1_rst_clk_wiz_1_100M_0' (7#1) [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/synth/design_1_rst_clk_wiz_1_100M_0.vhd:74]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_aclk
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_resetn
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[1]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port prmry_vect_in[0]
WARNING: [Synth 8-3331] design cdc_sync has unconnected port scndry_resetn
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1508.934 ; gain = 119.473
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1513.473 ; gain = 124.012
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1513.473 ; gain = 124.012
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_ooc.xdc] for cell 'U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_board.xdc] for cell 'U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_board.xdc] for cell 'U0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xdc] for cell 'U0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0.xdc] for cell 'U0'
Parsing XDC File [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_rst_clk_wiz_1_100M_0_synth_1/dont_touch.xdc]
Finished Parsing XDC File [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_rst_clk_wiz_1_100M_0_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1632.008 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 13 instances were transformed.
  FDR => FDRE: 12 instances
  SRL16 => SRL16E: 1 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1632.008 ; gain = 0.000
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1632.008 ; gain = 242.547
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcku5p-ffvb676-2-e
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1632.008 ; gain = 242.547
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for U0. (constraint file  C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_rst_clk_wiz_1_100M_0_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1632.008 ; gain = 242.547
---------------------------------------------------------------------------------
INFO: [Synth 8-4471] merging register 'seq_cnt_en_reg' into 'from_sys_reg' [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:377]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 1632.008 ; gain = 242.547
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	                6 Bit    Registers := 1     
	                3 Bit    Registers := 3     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module lpf 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 3     
Module upcnt_n 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	                6 Bit    Registers := 1     
+---Muxes : 
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module sequence_psr 
Detailed RTL Component Info : 
+---Registers : 
	                3 Bit    Registers := 3     
	                1 Bit    Registers := 5     
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 1824 (col length:96)
BRAMs: 960 (col length: RAMB18 96 RAMB36 48)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
INFO: [Synth 8-3886] merging instance 'U0/SEQ/pr_dec_reg[1]' (FD) to 'U0/SEQ/bsr_dec_reg[1]'
INFO: [Synth 8-3886] merging instance 'U0/SEQ/bsr_dec_reg[1]' (FD) to 'U0/SEQ/core_dec_reg[1]'
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1632.008 ; gain = 242.547
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2012.309 ; gain = 622.848
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2012.371 ; gain = 622.910
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2022.145 ; gain = 632.684
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+------+------+
|      |Cell  |Count |
+------+------+------+
|1     |LUT1  |     5|
|2     |LUT2  |     9|
|3     |LUT3  |     1|
|4     |LUT4  |     6|
|5     |LUT5  |     3|
|6     |LUT6  |     1|
|7     |SRL16 |     1|
|8     |FDR   |     8|
|9     |FDRE  |    28|
|10    |FDSE  |     4|
+------+------+------+

Report Instance Areas: 
+------+-----------------------------------+---------------+------+
|      |Instance                           |Module         |Cells |
+------+-----------------------------------+---------------+------+
|1     |top                                |               |    66|
|2     |  U0                               |proc_sys_reset |    66|
|3     |    EXT_LPF                        |lpf            |    23|
|4     |      \ACTIVE_HIGH_EXT.ACT_HI_EXT  |cdc_sync       |     6|
|5     |      \ACTIVE_LOW_AUX.ACT_LO_AUX   |cdc_sync_0     |     6|
|6     |    SEQ                            |sequence_psr   |    38|
|7     |      SEQ_COUNTER                  |upcnt_n        |    13|
+------+-----------------------------------+---------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2037.934 ; gain = 529.938
Synthesis Optimization Complete : Time (s): cpu = 00:00:38 ; elapsed = 00:00:38 . Memory (MB): peak = 2037.934 ; gain = 648.473
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 9 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2076.926 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 9 instances were transformed.
  FDR => FDRE: 8 instances
  SRL16 => SRL16E: 1 instances

INFO: [Common 17-83] Releasing license: Synthesis
44 Infos, 9 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:59 . Memory (MB): peak = 2076.926 ; gain = 1662.242
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2076.926 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_rst_clk_wiz_1_100M_0_synth_1/design_1_rst_clk_wiz_1_100M_0.dcp' has been generated.
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP design_1_rst_clk_wiz_1_100M_0, cache-ID = 72ab75db6daa4ca8
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2076.926 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/design_1_rst_clk_wiz_1_100M_0_synth_1/design_1_rst_clk_wiz_1_100M_0.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file design_1_rst_clk_wiz_1_100M_0_utilization_synth.rpt -pb design_1_rst_clk_wiz_1_100M_0_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Jan  8 11:02:50 2021...
