// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Fri Jan  8 11:03:33 2021
// Host        : Nemesys4 running 64-bit Service Pack 1  (build 7601)
// Command     : write_verilog -force -mode funcsim
//               c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0_sim_netlist.v
// Design      : design_1_microblaze_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xcku5p-ffvb676-2-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "design_1_microblaze_0_0,MicroBlaze,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "MicroBlaze,Vivado 2019.1" *) 
(* NotValidForBitStream *)
module design_1_microblaze_0_0
   (Clk,
    Reset,
    Interrupt,
    Interrupt_Address,
    Interrupt_Ack,
    Instr_Addr,
    Instr,
    IFetch,
    I_AS,
    IReady,
    IWAIT,
    ICE,
    IUE,
    Data_Addr,
    Data_Read,
    Data_Write,
    D_AS,
    Read_Strobe,
    Write_Strobe,
    DReady,
    DWait,
    DCE,
    DUE,
    Byte_Enable,
    M_AXI_DP_AWADDR,
    M_AXI_DP_AWPROT,
    M_AXI_DP_AWVALID,
    M_AXI_DP_AWREADY,
    M_AXI_DP_WDATA,
    M_AXI_DP_WSTRB,
    M_AXI_DP_WVALID,
    M_AXI_DP_WREADY,
    M_AXI_DP_BRESP,
    M_AXI_DP_BVALID,
    M_AXI_DP_BREADY,
    M_AXI_DP_ARADDR,
    M_AXI_DP_ARPROT,
    M_AXI_DP_ARVALID,
    M_AXI_DP_ARREADY,
    M_AXI_DP_RDATA,
    M_AXI_DP_RRESP,
    M_AXI_DP_RVALID,
    M_AXI_DP_RREADY,
    Dbg_Clk,
    Dbg_TDI,
    Dbg_TDO,
    Dbg_Reg_En,
    Dbg_Shift,
    Dbg_Capture,
    Dbg_Update,
    Debug_Rst,
    Dbg_Disable);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.CLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME CLK.CLK, ASSOCIATED_BUSIF M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC, ASSOCIATED_RESET Reset, FREQ_HZ 100000000, PHASE 0.0, CLK_DOMAIN design_1_clk_wiz_1_0_clk_out1, INSERT_VIP 0" *) input Clk;
  (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.RESET RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.RESET, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0" *) input Reset;
  (* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME INTERRUPT, SENSITIVITY LEVEL_HIGH, LOW_LATENCY 0" *) input Interrupt;
  (* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS" *) input [0:31]Interrupt_Address;
  (* x_interface_info = "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK" *) output [0:1]Interrupt_Ack;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME ILMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_ONLY" *) output [0:31]Instr_Addr;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB READDBUS" *) input [0:31]Instr;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB READSTROBE" *) output IFetch;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE" *) output I_AS;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB READY" *) input IReady;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB WAIT" *) input IWAIT;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB CE" *) input ICE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 ILMB UE" *) input IUE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB ABUS" *) (* x_interface_parameter = "XIL_INTERFACENAME DLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE" *) output [0:31]Data_Addr;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB READDBUS" *) input [0:31]Data_Read;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS" *) output [0:31]Data_Write;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE" *) output D_AS;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB READSTROBE" *) output Read_Strobe;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE" *) output Write_Strobe;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB READY" *) input DReady;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB WAIT" *) input DWait;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB CE" *) input DCE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB UE" *) input DUE;
  (* x_interface_info = "xilinx.com:interface:lmb:1.0 DLMB BE" *) output [0:3]Byte_Enable;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXI_DP, ID_WIDTH 0, READ_WRITE_MODE READ_WRITE, SUPPORTS_NARROW_BURST 0, HAS_BURST 0, HAS_LOCK 0, DATA_WIDTH 32, ADDR_WIDTH 32, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, MAX_BURST_LENGTH 1, PROTOCOL AXI4LITE, FREQ_HZ 100000000, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, PHASE 0.0, CLK_DOMAIN design_1_clk_wiz_1_0_clk_out1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output [31:0]M_AXI_DP_AWADDR;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT" *) output [2:0]M_AXI_DP_AWPROT;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID" *) output M_AXI_DP_AWVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY" *) input M_AXI_DP_AWREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA" *) output [31:0]M_AXI_DP_WDATA;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB" *) output [3:0]M_AXI_DP_WSTRB;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID" *) output M_AXI_DP_WVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY" *) input M_AXI_DP_WREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP" *) input [1:0]M_AXI_DP_BRESP;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID" *) input M_AXI_DP_BVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY" *) output M_AXI_DP_BREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR" *) output [31:0]M_AXI_DP_ARADDR;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT" *) output [2:0]M_AXI_DP_ARPROT;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID" *) output M_AXI_DP_ARVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY" *) input M_AXI_DP_ARREADY;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA" *) input [31:0]M_AXI_DP_RDATA;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP" *) input [1:0]M_AXI_DP_RRESP;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID" *) input M_AXI_DP_RVALID;
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY" *) output M_AXI_DP_RREADY;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG CLK" *) input Dbg_Clk;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TDI" *) input Dbg_TDI;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG TDO" *) output Dbg_TDO;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN" *) input [0:7]Dbg_Reg_En;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT" *) input Dbg_Shift;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE" *) input Dbg_Capture;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE" *) input Dbg_Update;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG RST" *) input Debug_Rst;
  (* x_interface_info = "xilinx.com:interface:mbdebug:3.0 DEBUG DISABLE" *) input Dbg_Disable;

  wire [0:3]Byte_Enable;
  wire Clk;
  wire DCE;
  wire DReady;
  wire DUE;
  wire DWait;
  wire D_AS;
  wire [0:31]Data_Addr;
  wire [0:31]Data_Read;
  wire [0:31]Data_Write;
  wire Dbg_Capture;
  wire Dbg_Clk;
  wire Dbg_Disable;
  wire [0:7]Dbg_Reg_En;
  wire Dbg_Shift;
  wire Dbg_TDI;
  wire Dbg_TDO;
  wire Dbg_Update;
  wire Debug_Rst;
  wire ICE;
  wire IFetch;
  wire IReady;
  wire IUE;
  wire IWAIT;
  wire I_AS;
  wire [0:31]Instr;
  wire [0:31]Instr_Addr;
  wire Interrupt;
  wire [0:1]Interrupt_Ack;
  wire [0:31]Interrupt_Address;
  wire [31:0]M_AXI_DP_ARADDR;
  wire [2:0]M_AXI_DP_ARPROT;
  wire M_AXI_DP_ARREADY;
  wire M_AXI_DP_ARVALID;
  wire [31:0]M_AXI_DP_AWADDR;
  wire [2:0]M_AXI_DP_AWPROT;
  wire M_AXI_DP_AWREADY;
  wire M_AXI_DP_AWVALID;
  wire M_AXI_DP_BREADY;
  wire [1:0]M_AXI_DP_BRESP;
  wire M_AXI_DP_BVALID;
  wire [31:0]M_AXI_DP_RDATA;
  wire M_AXI_DP_RREADY;
  wire [1:0]M_AXI_DP_RRESP;
  wire M_AXI_DP_RVALID;
  wire [31:0]M_AXI_DP_WDATA;
  wire M_AXI_DP_WREADY;
  wire [3:0]M_AXI_DP_WSTRB;
  wire M_AXI_DP_WVALID;
  wire Read_Strobe;
  wire Reset;
  wire Write_Strobe;
  wire NLW_U0_Dbg_ARREADY_UNCONNECTED;
  wire NLW_U0_Dbg_AWREADY_UNCONNECTED;
  wire NLW_U0_Dbg_BVALID_UNCONNECTED;
  wire NLW_U0_Dbg_Continue_UNCONNECTED;
  wire NLW_U0_Dbg_Intr_UNCONNECTED;
  wire NLW_U0_Dbg_RVALID_UNCONNECTED;
  wire NLW_U0_Dbg_Trace_Valid_UNCONNECTED;
  wire NLW_U0_Dbg_WREADY_UNCONNECTED;
  wire NLW_U0_Dbg_Wakeup_UNCONNECTED;
  wire NLW_U0_Hibernate_UNCONNECTED;
  wire NLW_U0_M0_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M0_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M10_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M10_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M11_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M11_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M12_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M12_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M13_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M13_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M14_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M14_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M15_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M15_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M1_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M1_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M2_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M2_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M3_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M3_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M4_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M4_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M5_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M5_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M6_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M6_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M7_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M7_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M8_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M8_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_M9_AXIS_TLAST_UNCONNECTED;
  wire NLW_U0_M9_AXIS_TVALID_UNCONNECTED;
  wire NLW_U0_MB_Error_UNCONNECTED;
  wire NLW_U0_MB_Halted_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_ACREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_ARVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_AWVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_BREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_CDLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_CDVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_CRVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_RACK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_RREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_WACK_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_DC_WVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_DP_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_ACREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_ARVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_AWVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_BREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_CDLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_CDVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_CRVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_RACK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_RREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_WACK_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_IC_WVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_ARLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_ARVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_AWLOCK_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_AWVALID_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_BREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_RREADY_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_WLAST_UNCONNECTED;
  wire NLW_U0_M_AXI_IP_WVALID_UNCONNECTED;
  wire NLW_U0_Pause_Ack_UNCONNECTED;
  wire NLW_U0_S0_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S10_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S11_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S12_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S13_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S14_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S15_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S1_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S2_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S3_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S4_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S5_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S6_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S7_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S8_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_S9_AXIS_TREADY_UNCONNECTED;
  wire NLW_U0_Sleep_UNCONNECTED;
  wire NLW_U0_Suspend_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Hit_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Rdy_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Read_UNCONNECTED;
  wire NLW_U0_Trace_DCache_Req_UNCONNECTED;
  wire NLW_U0_Trace_Data_Access_UNCONNECTED;
  wire NLW_U0_Trace_Data_Read_UNCONNECTED;
  wire NLW_U0_Trace_Data_Write_UNCONNECTED;
  wire NLW_U0_Trace_Delay_Slot_UNCONNECTED;
  wire NLW_U0_Trace_EX_PipeRun_UNCONNECTED;
  wire NLW_U0_Trace_Exception_Taken_UNCONNECTED;
  wire NLW_U0_Trace_ICache_Hit_UNCONNECTED;
  wire NLW_U0_Trace_ICache_Rdy_UNCONNECTED;
  wire NLW_U0_Trace_ICache_Req_UNCONNECTED;
  wire NLW_U0_Trace_Jump_Hit_UNCONNECTED;
  wire NLW_U0_Trace_Jump_Taken_UNCONNECTED;
  wire NLW_U0_Trace_MB_Halted_UNCONNECTED;
  wire NLW_U0_Trace_MEM_PipeRun_UNCONNECTED;
  wire NLW_U0_Trace_OF_PipeRun_UNCONNECTED;
  wire NLW_U0_Trace_Reg_Write_UNCONNECTED;
  wire NLW_U0_Trace_Valid_Instr_UNCONNECTED;
  wire [1:0]NLW_U0_Dbg_BRESP_UNCONNECTED;
  wire [31:0]NLW_U0_Dbg_RDATA_UNCONNECTED;
  wire [1:0]NLW_U0_Dbg_RRESP_UNCONNECTED;
  wire [0:35]NLW_U0_Dbg_Trace_Data_UNCONNECTED;
  wire [0:7]NLW_U0_Dbg_Trig_Ack_Out_UNCONNECTED;
  wire [0:7]NLW_U0_Dbg_Trig_In_UNCONNECTED;
  wire [0:4095]NLW_U0_LOCKSTEP_Master_Out_UNCONNECTED;
  wire [0:4095]NLW_U0_LOCKSTEP_Out_UNCONNECTED;
  wire [31:0]NLW_U0_M0_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M10_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M11_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M12_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M13_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M14_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M15_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M1_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M2_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M3_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M4_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M5_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M6_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M7_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M8_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M9_AXIS_TDATA_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_ARADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_ARBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_ARCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_ARDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DC_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DC_ARLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_ARPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_ARSIZE_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_ARSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_DC_ARUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_AWADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_AWBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_AWCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DC_AWDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DC_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DC_AWLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_AWPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_AWSIZE_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DC_AWSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_DC_AWUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_CDDATA_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_DC_CRRESP_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_DC_WDATA_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DC_WSTRB_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DC_WUSER_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DP_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_ARCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DP_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DP_ARLEN_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DP_ARSIZE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_DP_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_AWCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_DP_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_DP_AWLEN_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_DP_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_DP_AWSIZE_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_ARADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_ARBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_ARCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_ARDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IC_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IC_ARLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_ARPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_ARSIZE_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_ARSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_IC_ARUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_AWADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_AWBAR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_AWCACHE_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IC_AWDOMAIN_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IC_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IC_AWLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_AWPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_AWSIZE_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IC_AWSNOOP_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_IC_AWUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_CDDATA_UNCONNECTED;
  wire [4:0]NLW_U0_M_AXI_IC_CRRESP_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IC_WDATA_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IC_WSTRB_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IC_WUSER_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IP_ARADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IP_ARBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_ARCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IP_ARID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IP_ARLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_ARPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_ARQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_ARSIZE_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IP_AWADDR_UNCONNECTED;
  wire [1:0]NLW_U0_M_AXI_IP_AWBURST_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_AWCACHE_UNCONNECTED;
  wire [0:0]NLW_U0_M_AXI_IP_AWID_UNCONNECTED;
  wire [7:0]NLW_U0_M_AXI_IP_AWLEN_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_AWPROT_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_AWQOS_UNCONNECTED;
  wire [2:0]NLW_U0_M_AXI_IP_AWSIZE_UNCONNECTED;
  wire [31:0]NLW_U0_M_AXI_IP_WDATA_UNCONNECTED;
  wire [3:0]NLW_U0_M_AXI_IP_WSTRB_UNCONNECTED;
  wire [255:0]NLW_U0_RAM_From_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_Data_Address_UNCONNECTED;
  wire [0:3]NLW_U0_Trace_Data_Byte_Enable_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_Data_Write_Value_UNCONNECTED;
  wire [0:4]NLW_U0_Trace_Exception_Kind_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_Instruction_UNCONNECTED;
  wire [0:14]NLW_U0_Trace_MSR_Reg_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_New_Reg_Value_UNCONNECTED;
  wire [0:31]NLW_U0_Trace_PC_UNCONNECTED;
  wire [0:7]NLW_U0_Trace_PID_Reg_UNCONNECTED;
  wire [0:4]NLW_U0_Trace_Reg_Addr_UNCONNECTED;

  (* C_ADDR_TAG_BITS = "17" *) 
  (* C_ALLOW_DCACHE_WR = "1" *) 
  (* C_ALLOW_ICACHE_WR = "1" *) 
  (* C_AREA_OPTIMIZED = "0" *) 
  (* C_ASYNC_INTERRUPT = "1" *) 
  (* C_ASYNC_WAKEUP = "3" *) 
  (* C_AVOID_PRIMITIVES = "0" *) 
  (* C_BASE_VECTORS = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_BRANCH_TARGET_CACHE_SIZE = "0" *) 
  (* C_CACHE_BYTE_SIZE = "8192" *) 
  (* C_DADDR_SIZE = "32" *) 
  (* C_DATA_SIZE = "32" *) 
  (* C_DCACHE_ADDR_TAG = "17" *) 
  (* C_DCACHE_ALWAYS_USED = "0" *) 
  (* C_DCACHE_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_DCACHE_BYTE_SIZE = "8192" *) 
  (* C_DCACHE_DATA_WIDTH = "0" *) 
  (* C_DCACHE_FORCE_TAG_LUTRAM = "0" *) 
  (* C_DCACHE_HIGHADDR = "64'b0000000000000000000000000000000000111111111111111111111111111111" *) 
  (* C_DCACHE_LINE_LEN = "4" *) 
  (* C_DCACHE_USE_WRITEBACK = "0" *) 
  (* C_DCACHE_VICTIMS = "0" *) 
  (* C_DEBUG_COUNTER_WIDTH = "32" *) 
  (* C_DEBUG_ENABLED = "1" *) 
  (* C_DEBUG_EVENT_COUNTERS = "5" *) 
  (* C_DEBUG_EXTERNAL_TRACE = "0" *) 
  (* C_DEBUG_INTERFACE = "0" *) 
  (* C_DEBUG_LATENCY_COUNTERS = "1" *) 
  (* C_DEBUG_PROFILE_SIZE = "0" *) 
  (* C_DEBUG_TRACE_ASYNC_RESET = "0" *) 
  (* C_DEBUG_TRACE_SIZE = "8192" *) 
  (* C_DIV_ZERO_EXCEPTION = "0" *) 
  (* C_DYNAMIC_BUS_SIZING = "0" *) 
  (* C_D_AXI = "1" *) 
  (* C_D_LMB = "1" *) 
  (* C_ECC_USE_CE_EXCEPTION = "0" *) 
  (* C_EDGE_IS_POSITIVE = "1" *) 
  (* C_ENDIANNESS = "1" *) 
  (* C_FAMILY = "kintexuplus" *) 
  (* C_FAULT_TOLERANT = "0" *) 
  (* C_FPU_EXCEPTION = "0" *) 
  (* C_FREQ = "100000000" *) 
  (* C_FSL_EXCEPTION = "0" *) 
  (* C_FSL_LINKS = "0" *) 
  (* C_IADDR_SIZE = "32" *) 
  (* C_ICACHE_ALWAYS_USED = "0" *) 
  (* C_ICACHE_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
  (* C_ICACHE_DATA_WIDTH = "0" *) 
  (* C_ICACHE_FORCE_TAG_LUTRAM = "0" *) 
  (* C_ICACHE_HIGHADDR = "64'b0000000000000000000000000000000000111111111111111111111111111111" *) 
  (* C_ICACHE_LINE_LEN = "4" *) 
  (* C_ICACHE_STREAMS = "0" *) 
  (* C_ICACHE_VICTIMS = "0" *) 
  (* C_ILL_OPCODE_EXCEPTION = "0" *) 
  (* C_IMPRECISE_EXCEPTIONS = "0" *) 
  (* C_INSTANCE = "design_1_microblaze_0_0" *) 
  (* C_INSTR_SIZE = "32" *) 
  (* C_INTERCONNECT = "2" *) 
  (* C_INTERRUPT_IS_EDGE = "0" *) 
  (* C_I_AXI = "0" *) 
  (* C_I_LMB = "1" *) 
  (* C_LMB_DATA_SIZE = "32" *) 
  (* C_LOCKSTEP_MASTER = "0" *) 
  (* C_LOCKSTEP_SLAVE = "0" *) 
  (* C_M0_AXIS_DATA_WIDTH = "32" *) 
  (* C_M10_AXIS_DATA_WIDTH = "32" *) 
  (* C_M11_AXIS_DATA_WIDTH = "32" *) 
  (* C_M12_AXIS_DATA_WIDTH = "32" *) 
  (* C_M13_AXIS_DATA_WIDTH = "32" *) 
  (* C_M14_AXIS_DATA_WIDTH = "32" *) 
  (* C_M15_AXIS_DATA_WIDTH = "32" *) 
  (* C_M1_AXIS_DATA_WIDTH = "32" *) 
  (* C_M2_AXIS_DATA_WIDTH = "32" *) 
  (* C_M3_AXIS_DATA_WIDTH = "32" *) 
  (* C_M4_AXIS_DATA_WIDTH = "32" *) 
  (* C_M5_AXIS_DATA_WIDTH = "32" *) 
  (* C_M6_AXIS_DATA_WIDTH = "32" *) 
  (* C_M7_AXIS_DATA_WIDTH = "32" *) 
  (* C_M8_AXIS_DATA_WIDTH = "32" *) 
  (* C_M9_AXIS_DATA_WIDTH = "32" *) 
  (* C_MMU_DTLB_SIZE = "4" *) 
  (* C_MMU_ITLB_SIZE = "2" *) 
  (* C_MMU_PRIVILEGED_INSTR = "0" *) 
  (* C_MMU_TLB_ACCESS = "3" *) 
  (* C_MMU_ZONES = "16" *) 
  (* C_M_AXI_DC_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_DC_ARUSER_WIDTH = "5" *) 
  (* C_M_AXI_DC_AWUSER_WIDTH = "5" *) 
  (* C_M_AXI_DC_BUSER_WIDTH = "1" *) 
  (* C_M_AXI_DC_DATA_WIDTH = "32" *) 
  (* C_M_AXI_DC_EXCLUSIVE_ACCESS = "0" *) 
  (* C_M_AXI_DC_RUSER_WIDTH = "1" *) 
  (* C_M_AXI_DC_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_DC_USER_VALUE = "31" *) 
  (* C_M_AXI_DC_WUSER_WIDTH = "1" *) 
  (* C_M_AXI_DP_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_DP_DATA_WIDTH = "32" *) 
  (* C_M_AXI_DP_EXCLUSIVE_ACCESS = "0" *) 
  (* C_M_AXI_DP_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_D_BUS_EXCEPTION = "0" *) 
  (* C_M_AXI_IC_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_IC_ARUSER_WIDTH = "5" *) 
  (* C_M_AXI_IC_AWUSER_WIDTH = "5" *) 
  (* C_M_AXI_IC_BUSER_WIDTH = "1" *) 
  (* C_M_AXI_IC_DATA_WIDTH = "32" *) 
  (* C_M_AXI_IC_RUSER_WIDTH = "1" *) 
  (* C_M_AXI_IC_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_IC_USER_VALUE = "31" *) 
  (* C_M_AXI_IC_WUSER_WIDTH = "1" *) 
  (* C_M_AXI_IP_ADDR_WIDTH = "32" *) 
  (* C_M_AXI_IP_DATA_WIDTH = "32" *) 
  (* C_M_AXI_IP_THREAD_ID_WIDTH = "1" *) 
  (* C_M_AXI_I_BUS_EXCEPTION = "0" *) 
  (* C_NUMBER_OF_PC_BRK = "1" *) 
  (* C_NUMBER_OF_RD_ADDR_BRK = "0" *) 
  (* C_NUMBER_OF_WR_ADDR_BRK = "0" *) 
  (* C_NUM_SYNC_FF_CLK = "2" *) 
  (* C_NUM_SYNC_FF_CLK_DEBUG = "2" *) 
  (* C_NUM_SYNC_FF_CLK_IRQ = "1" *) 
  (* C_NUM_SYNC_FF_DBG_CLK = "1" *) 
  (* C_NUM_SYNC_FF_DBG_TRACE_CLK = "2" *) 
  (* C_OPCODE_0x0_ILLEGAL = "0" *) 
  (* C_OPTIMIZATION = "0" *) 
  (* C_PC_WIDTH = "32" *) 
  (* C_PIADDR_SIZE = "32" *) 
  (* C_PVR = "0" *) 
  (* C_PVR_USER1 = "8'b00000000" *) 
  (* C_PVR_USER2 = "0" *) 
  (* C_RESET_MSR = "0" *) 
  (* C_S0_AXIS_DATA_WIDTH = "32" *) 
  (* C_S10_AXIS_DATA_WIDTH = "32" *) 
  (* C_S11_AXIS_DATA_WIDTH = "32" *) 
  (* C_S12_AXIS_DATA_WIDTH = "32" *) 
  (* C_S13_AXIS_DATA_WIDTH = "32" *) 
  (* C_S14_AXIS_DATA_WIDTH = "32" *) 
  (* C_S15_AXIS_DATA_WIDTH = "32" *) 
  (* C_S1_AXIS_DATA_WIDTH = "32" *) 
  (* C_S2_AXIS_DATA_WIDTH = "32" *) 
  (* C_S3_AXIS_DATA_WIDTH = "32" *) 
  (* C_S4_AXIS_DATA_WIDTH = "32" *) 
  (* C_S5_AXIS_DATA_WIDTH = "32" *) 
  (* C_S6_AXIS_DATA_WIDTH = "32" *) 
  (* C_S7_AXIS_DATA_WIDTH = "32" *) 
  (* C_S8_AXIS_DATA_WIDTH = "32" *) 
  (* C_S9_AXIS_DATA_WIDTH = "32" *) 
  (* C_SCO = "0" *) 
  (* C_UNALIGNED_EXCEPTIONS = "0" *) 
  (* C_USE_BARREL = "0" *) 
  (* C_USE_BRANCH_TARGET_CACHE = "0" *) 
  (* C_USE_CONFIG_RESET = "0" *) 
  (* C_USE_DCACHE = "0" *) 
  (* C_USE_DIV = "0" *) 
  (* C_USE_EXTENDED_FSL_INSTR = "0" *) 
  (* C_USE_EXT_BRK = "0" *) 
  (* C_USE_EXT_NM_BRK = "0" *) 
  (* C_USE_FPU = "0" *) 
  (* C_USE_HW_MUL = "0" *) 
  (* C_USE_ICACHE = "0" *) 
  (* C_USE_INTERRUPT = "0" *) 
  (* C_USE_MMU = "0" *) 
  (* C_USE_MSR_INSTR = "0" *) 
  (* C_USE_NON_SECURE = "0" *) 
  (* C_USE_PCMP_INSTR = "0" *) 
  (* C_USE_REORDER_INSTR = "1" *) 
  (* C_USE_STACK_PROTECTION = "0" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  design_1_microblaze_0_0_MicroBlaze U0
       (.Byte_Enable(Byte_Enable),
        .Clk(Clk),
        .Config_Reset(1'b0),
        .DCE(DCE),
        .DEBUG_ACLK(1'b0),
        .DEBUG_ARESETN(1'b0),
        .DReady(DReady),
        .DUE(DUE),
        .DWait(DWait),
        .D_AS(D_AS),
        .Data_Addr(Data_Addr),
        .Data_Read(Data_Read),
        .Data_Write(Data_Write),
        .Dbg_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_ARREADY(NLW_U0_Dbg_ARREADY_UNCONNECTED),
        .Dbg_ARVALID(1'b0),
        .Dbg_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_AWREADY(NLW_U0_Dbg_AWREADY_UNCONNECTED),
        .Dbg_AWVALID(1'b0),
        .Dbg_BREADY(1'b0),
        .Dbg_BRESP(NLW_U0_Dbg_BRESP_UNCONNECTED[1:0]),
        .Dbg_BVALID(NLW_U0_Dbg_BVALID_UNCONNECTED),
        .Dbg_Capture(Dbg_Capture),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_Continue(NLW_U0_Dbg_Continue_UNCONNECTED),
        .Dbg_Disable(Dbg_Disable),
        .Dbg_Intr(NLW_U0_Dbg_Intr_UNCONNECTED),
        .Dbg_RDATA(NLW_U0_Dbg_RDATA_UNCONNECTED[31:0]),
        .Dbg_RREADY(1'b0),
        .Dbg_RRESP(NLW_U0_Dbg_RRESP_UNCONNECTED[1:0]),
        .Dbg_RVALID(NLW_U0_Dbg_RVALID_UNCONNECTED),
        .Dbg_Reg_En(Dbg_Reg_En),
        .Dbg_Shift(Dbg_Shift),
        .Dbg_Stop(1'b0),
        .Dbg_TDI(Dbg_TDI),
        .Dbg_TDO(Dbg_TDO),
        .Dbg_Trace_Clk(1'b0),
        .Dbg_Trace_Data(NLW_U0_Dbg_Trace_Data_UNCONNECTED[0:35]),
        .Dbg_Trace_Ready(1'b0),
        .Dbg_Trace_Valid(NLW_U0_Dbg_Trace_Valid_UNCONNECTED),
        .Dbg_Trig_Ack_In({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_Trig_Ack_Out(NLW_U0_Dbg_Trig_Ack_Out_UNCONNECTED[0:7]),
        .Dbg_Trig_In(NLW_U0_Dbg_Trig_In_UNCONNECTED[0:7]),
        .Dbg_Trig_Out({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_Update(Dbg_Update),
        .Dbg_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Dbg_WREADY(NLW_U0_Dbg_WREADY_UNCONNECTED),
        .Dbg_WVALID(1'b0),
        .Dbg_Wakeup(NLW_U0_Dbg_Wakeup_UNCONNECTED),
        .Debug_Rst(Debug_Rst),
        .Ext_BRK(1'b0),
        .Ext_NM_BRK(1'b0),
        .Hibernate(NLW_U0_Hibernate_UNCONNECTED),
        .ICE(ICE),
        .IFetch(IFetch),
        .IReady(IReady),
        .IUE(IUE),
        .IWAIT(IWAIT),
        .I_AS(I_AS),
        .Instr(Instr),
        .Instr_Addr(Instr_Addr),
        .Interrupt(Interrupt),
        .Interrupt_Ack(Interrupt_Ack),
        .Interrupt_Address(Interrupt_Address),
        .LOCKSTEP_Master_Out(NLW_U0_LOCKSTEP_Master_Out_UNCONNECTED[0:4095]),
        .LOCKSTEP_Out(NLW_U0_LOCKSTEP_Out_UNCONNECTED[0:4095]),
        .LOCKSTEP_Slave_In({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,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1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M0_AXIS_TDATA(NLW_U0_M0_AXIS_TDATA_UNCONNECTED[31:0]),
        .M0_AXIS_TLAST(NLW_U0_M0_AXIS_TLAST_UNCONNECTED),
        .M0_AXIS_TREADY(1'b0),
        .M0_AXIS_TVALID(NLW_U0_M0_AXIS_TVALID_UNCONNECTED),
        .M10_AXIS_TDATA(NLW_U0_M10_AXIS_TDATA_UNCONNECTED[31:0]),
        .M10_AXIS_TLAST(NLW_U0_M10_AXIS_TLAST_UNCONNECTED),
        .M10_AXIS_TREADY(1'b0),
        .M10_AXIS_TVALID(NLW_U0_M10_AXIS_TVALID_UNCONNECTED),
        .M11_AXIS_TDATA(NLW_U0_M11_AXIS_TDATA_UNCONNECTED[31:0]),
        .M11_AXIS_TLAST(NLW_U0_M11_AXIS_TLAST_UNCONNECTED),
        .M11_AXIS_TREADY(1'b0),
        .M11_AXIS_TVALID(NLW_U0_M11_AXIS_TVALID_UNCONNECTED),
        .M12_AXIS_TDATA(NLW_U0_M12_AXIS_TDATA_UNCONNECTED[31:0]),
        .M12_AXIS_TLAST(NLW_U0_M12_AXIS_TLAST_UNCONNECTED),
        .M12_AXIS_TREADY(1'b0),
        .M12_AXIS_TVALID(NLW_U0_M12_AXIS_TVALID_UNCONNECTED),
        .M13_AXIS_TDATA(NLW_U0_M13_AXIS_TDATA_UNCONNECTED[31:0]),
        .M13_AXIS_TLAST(NLW_U0_M13_AXIS_TLAST_UNCONNECTED),
        .M13_AXIS_TREADY(1'b0),
        .M13_AXIS_TVALID(NLW_U0_M13_AXIS_TVALID_UNCONNECTED),
        .M14_AXIS_TDATA(NLW_U0_M14_AXIS_TDATA_UNCONNECTED[31:0]),
        .M14_AXIS_TLAST(NLW_U0_M14_AXIS_TLAST_UNCONNECTED),
        .M14_AXIS_TREADY(1'b0),
        .M14_AXIS_TVALID(NLW_U0_M14_AXIS_TVALID_UNCONNECTED),
        .M15_AXIS_TDATA(NLW_U0_M15_AXIS_TDATA_UNCONNECTED[31:0]),
        .M15_AXIS_TLAST(NLW_U0_M15_AXIS_TLAST_UNCONNECTED),
        .M15_AXIS_TREADY(1'b0),
        .M15_AXIS_TVALID(NLW_U0_M15_AXIS_TVALID_UNCONNECTED),
        .M1_AXIS_TDATA(NLW_U0_M1_AXIS_TDATA_UNCONNECTED[31:0]),
        .M1_AXIS_TLAST(NLW_U0_M1_AXIS_TLAST_UNCONNECTED),
        .M1_AXIS_TREADY(1'b0),
        .M1_AXIS_TVALID(NLW_U0_M1_AXIS_TVALID_UNCONNECTED),
        .M2_AXIS_TDATA(NLW_U0_M2_AXIS_TDATA_UNCONNECTED[31:0]),
        .M2_AXIS_TLAST(NLW_U0_M2_AXIS_TLAST_UNCONNECTED),
        .M2_AXIS_TREADY(1'b0),
        .M2_AXIS_TVALID(NLW_U0_M2_AXIS_TVALID_UNCONNECTED),
        .M3_AXIS_TDATA(NLW_U0_M3_AXIS_TDATA_UNCONNECTED[31:0]),
        .M3_AXIS_TLAST(NLW_U0_M3_AXIS_TLAST_UNCONNECTED),
        .M3_AXIS_TREADY(1'b0),
        .M3_AXIS_TVALID(NLW_U0_M3_AXIS_TVALID_UNCONNECTED),
        .M4_AXIS_TDATA(NLW_U0_M4_AXIS_TDATA_UNCONNECTED[31:0]),
        .M4_AXIS_TLAST(NLW_U0_M4_AXIS_TLAST_UNCONNECTED),
        .M4_AXIS_TREADY(1'b0),
        .M4_AXIS_TVALID(NLW_U0_M4_AXIS_TVALID_UNCONNECTED),
        .M5_AXIS_TDATA(NLW_U0_M5_AXIS_TDATA_UNCONNECTED[31:0]),
        .M5_AXIS_TLAST(NLW_U0_M5_AXIS_TLAST_UNCONNECTED),
        .M5_AXIS_TREADY(1'b0),
        .M5_AXIS_TVALID(NLW_U0_M5_AXIS_TVALID_UNCONNECTED),
        .M6_AXIS_TDATA(NLW_U0_M6_AXIS_TDATA_UNCONNECTED[31:0]),
        .M6_AXIS_TLAST(NLW_U0_M6_AXIS_TLAST_UNCONNECTED),
        .M6_AXIS_TREADY(1'b0),
        .M6_AXIS_TVALID(NLW_U0_M6_AXIS_TVALID_UNCONNECTED),
        .M7_AXIS_TDATA(NLW_U0_M7_AXIS_TDATA_UNCONNECTED[31:0]),
        .M7_AXIS_TLAST(NLW_U0_M7_AXIS_TLAST_UNCONNECTED),
        .M7_AXIS_TREADY(1'b0),
        .M7_AXIS_TVALID(NLW_U0_M7_AXIS_TVALID_UNCONNECTED),
        .M8_AXIS_TDATA(NLW_U0_M8_AXIS_TDATA_UNCONNECTED[31:0]),
        .M8_AXIS_TLAST(NLW_U0_M8_AXIS_TLAST_UNCONNECTED),
        .M8_AXIS_TREADY(1'b0),
        .M8_AXIS_TVALID(NLW_U0_M8_AXIS_TVALID_UNCONNECTED),
        .M9_AXIS_TDATA(NLW_U0_M9_AXIS_TDATA_UNCONNECTED[31:0]),
        .M9_AXIS_TLAST(NLW_U0_M9_AXIS_TLAST_UNCONNECTED),
        .M9_AXIS_TREADY(1'b0),
        .M9_AXIS_TVALID(NLW_U0_M9_AXIS_TVALID_UNCONNECTED),
        .MB_Error(NLW_U0_MB_Error_UNCONNECTED),
        .MB_Halted(NLW_U0_MB_Halted_UNCONNECTED),
        .M_AXI_DC_ACADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_DC_ACPROT({1'b0,1'b0,1'b0}),
        .M_AXI_DC_ACREADY(NLW_U0_M_AXI_DC_ACREADY_UNCONNECTED),
        .M_AXI_DC_ACSNOOP({1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_DC_ACVALID(1'b0),
        .M_AXI_DC_ARADDR(NLW_U0_M_AXI_DC_ARADDR_UNCONNECTED[31:0]),
        .M_AXI_DC_ARBAR(NLW_U0_M_AXI_DC_ARBAR_UNCONNECTED[1:0]),
        .M_AXI_DC_ARBURST(NLW_U0_M_AXI_DC_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_DC_ARCACHE(NLW_U0_M_AXI_DC_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_DC_ARDOMAIN(NLW_U0_M_AXI_DC_ARDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_DC_ARID(NLW_U0_M_AXI_DC_ARID_UNCONNECTED[0]),
        .M_AXI_DC_ARLEN(NLW_U0_M_AXI_DC_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_DC_ARLOCK(NLW_U0_M_AXI_DC_ARLOCK_UNCONNECTED),
        .M_AXI_DC_ARPROT(NLW_U0_M_AXI_DC_ARPROT_UNCONNECTED[2:0]),
        .M_AXI_DC_ARQOS(NLW_U0_M_AXI_DC_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_DC_ARREADY(1'b0),
        .M_AXI_DC_ARSIZE(NLW_U0_M_AXI_DC_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_DC_ARSNOOP(NLW_U0_M_AXI_DC_ARSNOOP_UNCONNECTED[3:0]),
        .M_AXI_DC_ARUSER(NLW_U0_M_AXI_DC_ARUSER_UNCONNECTED[4:0]),
        .M_AXI_DC_ARVALID(NLW_U0_M_AXI_DC_ARVALID_UNCONNECTED),
        .M_AXI_DC_AWADDR(NLW_U0_M_AXI_DC_AWADDR_UNCONNECTED[31:0]),
        .M_AXI_DC_AWBAR(NLW_U0_M_AXI_DC_AWBAR_UNCONNECTED[1:0]),
        .M_AXI_DC_AWBURST(NLW_U0_M_AXI_DC_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_DC_AWCACHE(NLW_U0_M_AXI_DC_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_DC_AWDOMAIN(NLW_U0_M_AXI_DC_AWDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_DC_AWID(NLW_U0_M_AXI_DC_AWID_UNCONNECTED[0]),
        .M_AXI_DC_AWLEN(NLW_U0_M_AXI_DC_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_DC_AWLOCK(NLW_U0_M_AXI_DC_AWLOCK_UNCONNECTED),
        .M_AXI_DC_AWPROT(NLW_U0_M_AXI_DC_AWPROT_UNCONNECTED[2:0]),
        .M_AXI_DC_AWQOS(NLW_U0_M_AXI_DC_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_DC_AWREADY(1'b0),
        .M_AXI_DC_AWSIZE(NLW_U0_M_AXI_DC_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_DC_AWSNOOP(NLW_U0_M_AXI_DC_AWSNOOP_UNCONNECTED[2:0]),
        .M_AXI_DC_AWUSER(NLW_U0_M_AXI_DC_AWUSER_UNCONNECTED[4:0]),
        .M_AXI_DC_AWVALID(NLW_U0_M_AXI_DC_AWVALID_UNCONNECTED),
        .M_AXI_DC_BID(1'b0),
        .M_AXI_DC_BREADY(NLW_U0_M_AXI_DC_BREADY_UNCONNECTED),
        .M_AXI_DC_BRESP({1'b0,1'b0}),
        .M_AXI_DC_BUSER(1'b0),
        .M_AXI_DC_BVALID(1'b0),
        .M_AXI_DC_CDDATA(NLW_U0_M_AXI_DC_CDDATA_UNCONNECTED[31:0]),
        .M_AXI_DC_CDLAST(NLW_U0_M_AXI_DC_CDLAST_UNCONNECTED),
        .M_AXI_DC_CDREADY(1'b0),
        .M_AXI_DC_CDVALID(NLW_U0_M_AXI_DC_CDVALID_UNCONNECTED),
        .M_AXI_DC_CRREADY(1'b0),
        .M_AXI_DC_CRRESP(NLW_U0_M_AXI_DC_CRRESP_UNCONNECTED[4:0]),
        .M_AXI_DC_CRVALID(NLW_U0_M_AXI_DC_CRVALID_UNCONNECTED),
        .M_AXI_DC_RACK(NLW_U0_M_AXI_DC_RACK_UNCONNECTED),
        .M_AXI_DC_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_DC_RID(1'b0),
        .M_AXI_DC_RLAST(1'b0),
        .M_AXI_DC_RREADY(NLW_U0_M_AXI_DC_RREADY_UNCONNECTED),
        .M_AXI_DC_RRESP({1'b0,1'b0}),
        .M_AXI_DC_RUSER(1'b0),
        .M_AXI_DC_RVALID(1'b0),
        .M_AXI_DC_WACK(NLW_U0_M_AXI_DC_WACK_UNCONNECTED),
        .M_AXI_DC_WDATA(NLW_U0_M_AXI_DC_WDATA_UNCONNECTED[31:0]),
        .M_AXI_DC_WLAST(NLW_U0_M_AXI_DC_WLAST_UNCONNECTED),
        .M_AXI_DC_WREADY(1'b0),
        .M_AXI_DC_WSTRB(NLW_U0_M_AXI_DC_WSTRB_UNCONNECTED[3:0]),
        .M_AXI_DC_WUSER(NLW_U0_M_AXI_DC_WUSER_UNCONNECTED[0]),
        .M_AXI_DC_WVALID(NLW_U0_M_AXI_DC_WVALID_UNCONNECTED),
        .M_AXI_DP_ARADDR(M_AXI_DP_ARADDR),
        .M_AXI_DP_ARBURST(NLW_U0_M_AXI_DP_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_DP_ARCACHE(NLW_U0_M_AXI_DP_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_DP_ARID(NLW_U0_M_AXI_DP_ARID_UNCONNECTED[0]),
        .M_AXI_DP_ARLEN(NLW_U0_M_AXI_DP_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_DP_ARLOCK(NLW_U0_M_AXI_DP_ARLOCK_UNCONNECTED),
        .M_AXI_DP_ARPROT(M_AXI_DP_ARPROT),
        .M_AXI_DP_ARQOS(NLW_U0_M_AXI_DP_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_DP_ARREADY(M_AXI_DP_ARREADY),
        .M_AXI_DP_ARSIZE(NLW_U0_M_AXI_DP_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_DP_ARVALID(M_AXI_DP_ARVALID),
        .M_AXI_DP_AWADDR(M_AXI_DP_AWADDR),
        .M_AXI_DP_AWBURST(NLW_U0_M_AXI_DP_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_DP_AWCACHE(NLW_U0_M_AXI_DP_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_DP_AWID(NLW_U0_M_AXI_DP_AWID_UNCONNECTED[0]),
        .M_AXI_DP_AWLEN(NLW_U0_M_AXI_DP_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_DP_AWLOCK(NLW_U0_M_AXI_DP_AWLOCK_UNCONNECTED),
        .M_AXI_DP_AWPROT(M_AXI_DP_AWPROT),
        .M_AXI_DP_AWQOS(NLW_U0_M_AXI_DP_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_DP_AWREADY(M_AXI_DP_AWREADY),
        .M_AXI_DP_AWSIZE(NLW_U0_M_AXI_DP_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_DP_AWVALID(M_AXI_DP_AWVALID),
        .M_AXI_DP_BID(1'b0),
        .M_AXI_DP_BREADY(M_AXI_DP_BREADY),
        .M_AXI_DP_BRESP(M_AXI_DP_BRESP),
        .M_AXI_DP_BVALID(M_AXI_DP_BVALID),
        .M_AXI_DP_RDATA(M_AXI_DP_RDATA),
        .M_AXI_DP_RID(1'b0),
        .M_AXI_DP_RLAST(1'b0),
        .M_AXI_DP_RREADY(M_AXI_DP_RREADY),
        .M_AXI_DP_RRESP(M_AXI_DP_RRESP),
        .M_AXI_DP_RVALID(M_AXI_DP_RVALID),
        .M_AXI_DP_WDATA(M_AXI_DP_WDATA),
        .M_AXI_DP_WLAST(NLW_U0_M_AXI_DP_WLAST_UNCONNECTED),
        .M_AXI_DP_WREADY(M_AXI_DP_WREADY),
        .M_AXI_DP_WSTRB(M_AXI_DP_WSTRB),
        .M_AXI_DP_WVALID(M_AXI_DP_WVALID),
        .M_AXI_IC_ACADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IC_ACPROT({1'b0,1'b0,1'b0}),
        .M_AXI_IC_ACREADY(NLW_U0_M_AXI_IC_ACREADY_UNCONNECTED),
        .M_AXI_IC_ACSNOOP({1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IC_ACVALID(1'b0),
        .M_AXI_IC_ARADDR(NLW_U0_M_AXI_IC_ARADDR_UNCONNECTED[31:0]),
        .M_AXI_IC_ARBAR(NLW_U0_M_AXI_IC_ARBAR_UNCONNECTED[1:0]),
        .M_AXI_IC_ARBURST(NLW_U0_M_AXI_IC_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_IC_ARCACHE(NLW_U0_M_AXI_IC_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_IC_ARDOMAIN(NLW_U0_M_AXI_IC_ARDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_IC_ARID(NLW_U0_M_AXI_IC_ARID_UNCONNECTED[0]),
        .M_AXI_IC_ARLEN(NLW_U0_M_AXI_IC_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_IC_ARLOCK(NLW_U0_M_AXI_IC_ARLOCK_UNCONNECTED),
        .M_AXI_IC_ARPROT(NLW_U0_M_AXI_IC_ARPROT_UNCONNECTED[2:0]),
        .M_AXI_IC_ARQOS(NLW_U0_M_AXI_IC_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_IC_ARREADY(1'b0),
        .M_AXI_IC_ARSIZE(NLW_U0_M_AXI_IC_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_IC_ARSNOOP(NLW_U0_M_AXI_IC_ARSNOOP_UNCONNECTED[3:0]),
        .M_AXI_IC_ARUSER(NLW_U0_M_AXI_IC_ARUSER_UNCONNECTED[4:0]),
        .M_AXI_IC_ARVALID(NLW_U0_M_AXI_IC_ARVALID_UNCONNECTED),
        .M_AXI_IC_AWADDR(NLW_U0_M_AXI_IC_AWADDR_UNCONNECTED[31:0]),
        .M_AXI_IC_AWBAR(NLW_U0_M_AXI_IC_AWBAR_UNCONNECTED[1:0]),
        .M_AXI_IC_AWBURST(NLW_U0_M_AXI_IC_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_IC_AWCACHE(NLW_U0_M_AXI_IC_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_IC_AWDOMAIN(NLW_U0_M_AXI_IC_AWDOMAIN_UNCONNECTED[1:0]),
        .M_AXI_IC_AWID(NLW_U0_M_AXI_IC_AWID_UNCONNECTED[0]),
        .M_AXI_IC_AWLEN(NLW_U0_M_AXI_IC_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_IC_AWLOCK(NLW_U0_M_AXI_IC_AWLOCK_UNCONNECTED),
        .M_AXI_IC_AWPROT(NLW_U0_M_AXI_IC_AWPROT_UNCONNECTED[2:0]),
        .M_AXI_IC_AWQOS(NLW_U0_M_AXI_IC_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_IC_AWREADY(1'b0),
        .M_AXI_IC_AWSIZE(NLW_U0_M_AXI_IC_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_IC_AWSNOOP(NLW_U0_M_AXI_IC_AWSNOOP_UNCONNECTED[2:0]),
        .M_AXI_IC_AWUSER(NLW_U0_M_AXI_IC_AWUSER_UNCONNECTED[4:0]),
        .M_AXI_IC_AWVALID(NLW_U0_M_AXI_IC_AWVALID_UNCONNECTED),
        .M_AXI_IC_BID(1'b0),
        .M_AXI_IC_BREADY(NLW_U0_M_AXI_IC_BREADY_UNCONNECTED),
        .M_AXI_IC_BRESP({1'b0,1'b0}),
        .M_AXI_IC_BUSER(1'b0),
        .M_AXI_IC_BVALID(1'b0),
        .M_AXI_IC_CDDATA(NLW_U0_M_AXI_IC_CDDATA_UNCONNECTED[31:0]),
        .M_AXI_IC_CDLAST(NLW_U0_M_AXI_IC_CDLAST_UNCONNECTED),
        .M_AXI_IC_CDREADY(1'b0),
        .M_AXI_IC_CDVALID(NLW_U0_M_AXI_IC_CDVALID_UNCONNECTED),
        .M_AXI_IC_CRREADY(1'b0),
        .M_AXI_IC_CRRESP(NLW_U0_M_AXI_IC_CRRESP_UNCONNECTED[4:0]),
        .M_AXI_IC_CRVALID(NLW_U0_M_AXI_IC_CRVALID_UNCONNECTED),
        .M_AXI_IC_RACK(NLW_U0_M_AXI_IC_RACK_UNCONNECTED),
        .M_AXI_IC_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IC_RID(1'b0),
        .M_AXI_IC_RLAST(1'b0),
        .M_AXI_IC_RREADY(NLW_U0_M_AXI_IC_RREADY_UNCONNECTED),
        .M_AXI_IC_RRESP({1'b0,1'b0}),
        .M_AXI_IC_RUSER(1'b0),
        .M_AXI_IC_RVALID(1'b0),
        .M_AXI_IC_WACK(NLW_U0_M_AXI_IC_WACK_UNCONNECTED),
        .M_AXI_IC_WDATA(NLW_U0_M_AXI_IC_WDATA_UNCONNECTED[31:0]),
        .M_AXI_IC_WLAST(NLW_U0_M_AXI_IC_WLAST_UNCONNECTED),
        .M_AXI_IC_WREADY(1'b0),
        .M_AXI_IC_WSTRB(NLW_U0_M_AXI_IC_WSTRB_UNCONNECTED[3:0]),
        .M_AXI_IC_WUSER(NLW_U0_M_AXI_IC_WUSER_UNCONNECTED[0]),
        .M_AXI_IC_WVALID(NLW_U0_M_AXI_IC_WVALID_UNCONNECTED),
        .M_AXI_IP_ARADDR(NLW_U0_M_AXI_IP_ARADDR_UNCONNECTED[31:0]),
        .M_AXI_IP_ARBURST(NLW_U0_M_AXI_IP_ARBURST_UNCONNECTED[1:0]),
        .M_AXI_IP_ARCACHE(NLW_U0_M_AXI_IP_ARCACHE_UNCONNECTED[3:0]),
        .M_AXI_IP_ARID(NLW_U0_M_AXI_IP_ARID_UNCONNECTED[0]),
        .M_AXI_IP_ARLEN(NLW_U0_M_AXI_IP_ARLEN_UNCONNECTED[7:0]),
        .M_AXI_IP_ARLOCK(NLW_U0_M_AXI_IP_ARLOCK_UNCONNECTED),
        .M_AXI_IP_ARPROT(NLW_U0_M_AXI_IP_ARPROT_UNCONNECTED[2:0]),
        .M_AXI_IP_ARQOS(NLW_U0_M_AXI_IP_ARQOS_UNCONNECTED[3:0]),
        .M_AXI_IP_ARREADY(1'b0),
        .M_AXI_IP_ARSIZE(NLW_U0_M_AXI_IP_ARSIZE_UNCONNECTED[2:0]),
        .M_AXI_IP_ARVALID(NLW_U0_M_AXI_IP_ARVALID_UNCONNECTED),
        .M_AXI_IP_AWADDR(NLW_U0_M_AXI_IP_AWADDR_UNCONNECTED[31:0]),
        .M_AXI_IP_AWBURST(NLW_U0_M_AXI_IP_AWBURST_UNCONNECTED[1:0]),
        .M_AXI_IP_AWCACHE(NLW_U0_M_AXI_IP_AWCACHE_UNCONNECTED[3:0]),
        .M_AXI_IP_AWID(NLW_U0_M_AXI_IP_AWID_UNCONNECTED[0]),
        .M_AXI_IP_AWLEN(NLW_U0_M_AXI_IP_AWLEN_UNCONNECTED[7:0]),
        .M_AXI_IP_AWLOCK(NLW_U0_M_AXI_IP_AWLOCK_UNCONNECTED),
        .M_AXI_IP_AWPROT(NLW_U0_M_AXI_IP_AWPROT_UNCONNECTED[2:0]),
        .M_AXI_IP_AWQOS(NLW_U0_M_AXI_IP_AWQOS_UNCONNECTED[3:0]),
        .M_AXI_IP_AWREADY(1'b0),
        .M_AXI_IP_AWSIZE(NLW_U0_M_AXI_IP_AWSIZE_UNCONNECTED[2:0]),
        .M_AXI_IP_AWVALID(NLW_U0_M_AXI_IP_AWVALID_UNCONNECTED),
        .M_AXI_IP_BID(1'b0),
        .M_AXI_IP_BREADY(NLW_U0_M_AXI_IP_BREADY_UNCONNECTED),
        .M_AXI_IP_BRESP({1'b0,1'b0}),
        .M_AXI_IP_BVALID(1'b0),
        .M_AXI_IP_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .M_AXI_IP_RID(1'b0),
        .M_AXI_IP_RLAST(1'b0),
        .M_AXI_IP_RREADY(NLW_U0_M_AXI_IP_RREADY_UNCONNECTED),
        .M_AXI_IP_RRESP({1'b0,1'b0}),
        .M_AXI_IP_RVALID(1'b0),
        .M_AXI_IP_WDATA(NLW_U0_M_AXI_IP_WDATA_UNCONNECTED[31:0]),
        .M_AXI_IP_WLAST(NLW_U0_M_AXI_IP_WLAST_UNCONNECTED),
        .M_AXI_IP_WREADY(1'b0),
        .M_AXI_IP_WSTRB(NLW_U0_M_AXI_IP_WSTRB_UNCONNECTED[3:0]),
        .M_AXI_IP_WVALID(NLW_U0_M_AXI_IP_WVALID_UNCONNECTED),
        .Mb_Reset(1'b0),
        .Non_Secure({1'b0,1'b0,1'b0,1'b0}),
        .Pause(1'b0),
        .Pause_Ack(NLW_U0_Pause_Ack_UNCONNECTED),
        .RAM_From(NLW_U0_RAM_From_UNCONNECTED[255:0]),
        .RAM_To({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .Read_Strobe(Read_Strobe),
        .Reset(Reset),
        .Reset_Mode({1'b0,1'b0}),
        .S0_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S0_AXIS_TLAST(1'b0),
        .S0_AXIS_TREADY(NLW_U0_S0_AXIS_TREADY_UNCONNECTED),
        .S0_AXIS_TVALID(1'b0),
        .S10_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S10_AXIS_TLAST(1'b0),
        .S10_AXIS_TREADY(NLW_U0_S10_AXIS_TREADY_UNCONNECTED),
        .S10_AXIS_TVALID(1'b0),
        .S11_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S11_AXIS_TLAST(1'b0),
        .S11_AXIS_TREADY(NLW_U0_S11_AXIS_TREADY_UNCONNECTED),
        .S11_AXIS_TVALID(1'b0),
        .S12_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S12_AXIS_TLAST(1'b0),
        .S12_AXIS_TREADY(NLW_U0_S12_AXIS_TREADY_UNCONNECTED),
        .S12_AXIS_TVALID(1'b0),
        .S13_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S13_AXIS_TLAST(1'b0),
        .S13_AXIS_TREADY(NLW_U0_S13_AXIS_TREADY_UNCONNECTED),
        .S13_AXIS_TVALID(1'b0),
        .S14_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S14_AXIS_TLAST(1'b0),
        .S14_AXIS_TREADY(NLW_U0_S14_AXIS_TREADY_UNCONNECTED),
        .S14_AXIS_TVALID(1'b0),
        .S15_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S15_AXIS_TLAST(1'b0),
        .S15_AXIS_TREADY(NLW_U0_S15_AXIS_TREADY_UNCONNECTED),
        .S15_AXIS_TVALID(1'b0),
        .S1_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S1_AXIS_TLAST(1'b0),
        .S1_AXIS_TREADY(NLW_U0_S1_AXIS_TREADY_UNCONNECTED),
        .S1_AXIS_TVALID(1'b0),
        .S2_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S2_AXIS_TLAST(1'b0),
        .S2_AXIS_TREADY(NLW_U0_S2_AXIS_TREADY_UNCONNECTED),
        .S2_AXIS_TVALID(1'b0),
        .S3_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S3_AXIS_TLAST(1'b0),
        .S3_AXIS_TREADY(NLW_U0_S3_AXIS_TREADY_UNCONNECTED),
        .S3_AXIS_TVALID(1'b0),
        .S4_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S4_AXIS_TLAST(1'b0),
        .S4_AXIS_TREADY(NLW_U0_S4_AXIS_TREADY_UNCONNECTED),
        .S4_AXIS_TVALID(1'b0),
        .S5_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S5_AXIS_TLAST(1'b0),
        .S5_AXIS_TREADY(NLW_U0_S5_AXIS_TREADY_UNCONNECTED),
        .S5_AXIS_TVALID(1'b0),
        .S6_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S6_AXIS_TLAST(1'b0),
        .S6_AXIS_TREADY(NLW_U0_S6_AXIS_TREADY_UNCONNECTED),
        .S6_AXIS_TVALID(1'b0),
        .S7_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S7_AXIS_TLAST(1'b0),
        .S7_AXIS_TREADY(NLW_U0_S7_AXIS_TREADY_UNCONNECTED),
        .S7_AXIS_TVALID(1'b0),
        .S8_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S8_AXIS_TLAST(1'b0),
        .S8_AXIS_TREADY(NLW_U0_S8_AXIS_TREADY_UNCONNECTED),
        .S8_AXIS_TVALID(1'b0),
        .S9_AXIS_TDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .S9_AXIS_TLAST(1'b0),
        .S9_AXIS_TREADY(NLW_U0_S9_AXIS_TREADY_UNCONNECTED),
        .S9_AXIS_TVALID(1'b0),
        .Scan_En(1'b0),
        .Scan_Reset(1'b0),
        .Scan_Reset_Sel(1'b0),
        .Sleep(NLW_U0_Sleep_UNCONNECTED),
        .Suspend(NLW_U0_Suspend_UNCONNECTED),
        .Trace_DCache_Hit(NLW_U0_Trace_DCache_Hit_UNCONNECTED),
        .Trace_DCache_Rdy(NLW_U0_Trace_DCache_Rdy_UNCONNECTED),
        .Trace_DCache_Read(NLW_U0_Trace_DCache_Read_UNCONNECTED),
        .Trace_DCache_Req(NLW_U0_Trace_DCache_Req_UNCONNECTED),
        .Trace_Data_Access(NLW_U0_Trace_Data_Access_UNCONNECTED),
        .Trace_Data_Address(NLW_U0_Trace_Data_Address_UNCONNECTED[0:31]),
        .Trace_Data_Byte_Enable(NLW_U0_Trace_Data_Byte_Enable_UNCONNECTED[0:3]),
        .Trace_Data_Read(NLW_U0_Trace_Data_Read_UNCONNECTED),
        .Trace_Data_Write(NLW_U0_Trace_Data_Write_UNCONNECTED),
        .Trace_Data_Write_Value(NLW_U0_Trace_Data_Write_Value_UNCONNECTED[0:31]),
        .Trace_Delay_Slot(NLW_U0_Trace_Delay_Slot_UNCONNECTED),
        .Trace_EX_PipeRun(NLW_U0_Trace_EX_PipeRun_UNCONNECTED),
        .Trace_Exception_Kind(NLW_U0_Trace_Exception_Kind_UNCONNECTED[0:4]),
        .Trace_Exception_Taken(NLW_U0_Trace_Exception_Taken_UNCONNECTED),
        .Trace_ICache_Hit(NLW_U0_Trace_ICache_Hit_UNCONNECTED),
        .Trace_ICache_Rdy(NLW_U0_Trace_ICache_Rdy_UNCONNECTED),
        .Trace_ICache_Req(NLW_U0_Trace_ICache_Req_UNCONNECTED),
        .Trace_Instruction(NLW_U0_Trace_Instruction_UNCONNECTED[0:31]),
        .Trace_Jump_Hit(NLW_U0_Trace_Jump_Hit_UNCONNECTED),
        .Trace_Jump_Taken(NLW_U0_Trace_Jump_Taken_UNCONNECTED),
        .Trace_MB_Halted(NLW_U0_Trace_MB_Halted_UNCONNECTED),
        .Trace_MEM_PipeRun(NLW_U0_Trace_MEM_PipeRun_UNCONNECTED),
        .Trace_MSR_Reg(NLW_U0_Trace_MSR_Reg_UNCONNECTED[0:14]),
        .Trace_New_Reg_Value(NLW_U0_Trace_New_Reg_Value_UNCONNECTED[0:31]),
        .Trace_OF_PipeRun(NLW_U0_Trace_OF_PipeRun_UNCONNECTED),
        .Trace_PC(NLW_U0_Trace_PC_UNCONNECTED[0:31]),
        .Trace_PID_Reg(NLW_U0_Trace_PID_Reg_UNCONNECTED[0:7]),
        .Trace_Reg_Addr(NLW_U0_Trace_Reg_Addr_UNCONNECTED[0:4]),
        .Trace_Reg_Write(NLW_U0_Trace_Reg_Write_UNCONNECTED),
        .Trace_Valid_Instr(NLW_U0_Trace_Valid_Instr_UNCONNECTED),
        .Wakeup({1'b0,1'b0}),
        .Write_Strobe(Write_Strobe));
endmodule

(* ORIG_REF_NAME = "ALU" *) 
module design_1_microblaze_0_0_ALU
   (LO,
    \EX_Op2_reg[0] ,
    ex_databus_addr,
    ex_use_carry,
    DI_0,
    ex_alu_carryin,
    S,
    ex_unsigned_op,
    Q,
    \MEM_DataBus_Addr_reg[9] ,
    \Using_FPGA.Native ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    I2,
    I0,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output LO;
  output [29:0]\EX_Op2_reg[0] ;
  output [1:0]ex_databus_addr;
  input ex_use_carry;
  input DI_0;
  input ex_alu_carryin;
  input S;
  input ex_unsigned_op;
  input [31:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[9] ;
  input [31:0]\Using_FPGA.Native ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input I2;
  input I0;
  input lopt;
  input lopt_1;
  output lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  input lopt_6;
  input lopt_7;
  input lopt_8;
  input lopt_9;
  input lopt_10;
  input lopt_11;
  input lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  output lopt_20;

  wire DI_0;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [29:0]\EX_Op2_reg[0] ;
  wire I0;
  wire I2;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[9] ;
  wire [31:0]Q;
  wire S;
  wire [31:0]\Using_FPGA.Native ;
  wire alu_carry_1;
  wire alu_carry_10;
  wire alu_carry_11;
  wire alu_carry_12;
  wire alu_carry_13;
  wire alu_carry_14;
  wire alu_carry_15;
  wire alu_carry_16;
  wire alu_carry_17;
  wire alu_carry_18;
  wire alu_carry_19;
  wire alu_carry_2;
  wire alu_carry_20;
  wire alu_carry_21;
  wire alu_carry_22;
  wire alu_carry_23;
  wire alu_carry_24;
  wire alu_carry_25;
  wire alu_carry_26;
  wire alu_carry_27;
  wire alu_carry_28;
  wire alu_carry_29;
  wire alu_carry_3;
  wire alu_carry_30;
  wire alu_carry_31;
  wire alu_carry_4;
  wire alu_carry_5;
  wire alu_carry_6;
  wire alu_carry_7;
  wire alu_carry_8;
  wire alu_carry_9;
  wire alu_carry_in;
  wire ex_alu_carryin;
  wire [1:0]ex_databus_addr;
  wire ex_unsigned_op;
  wire ex_use_carry;
  wire lopt;
  wire lopt_1;
  wire \^lopt_10 ;
  wire lopt_100;
  wire lopt_101;
  wire lopt_102;
  wire lopt_103;
  wire lopt_104;
  wire lopt_105;
  wire lopt_106;
  wire lopt_107;
  wire lopt_108;
  wire lopt_109;
  wire \^lopt_11 ;
  wire lopt_110;
  wire lopt_111;
  wire lopt_112;
  wire lopt_113;
  wire lopt_114;
  wire lopt_115;
  wire lopt_116;
  wire lopt_117;
  wire lopt_118;
  wire lopt_119;
  wire \^lopt_12 ;
  wire lopt_120;
  wire lopt_121;
  wire lopt_122;
  wire lopt_123;
  wire lopt_124;
  wire lopt_125;
  wire lopt_126;
  wire lopt_127;
  wire lopt_128;
  wire lopt_129;
  wire \^lopt_13 ;
  wire lopt_130;
  wire lopt_131;
  wire lopt_132;
  wire lopt_133;
  wire lopt_134;
  wire lopt_135;
  wire lopt_136;
  wire lopt_137;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire lopt_2;
  wire \^lopt_20 ;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_27;
  wire lopt_28;
  wire lopt_29;
  wire lopt_3;
  wire lopt_30;
  wire lopt_31;
  wire lopt_32;
  wire lopt_33;
  wire lopt_34;
  wire lopt_35;
  wire lopt_36;
  wire lopt_37;
  wire lopt_38;
  wire lopt_39;
  wire lopt_4;
  wire lopt_40;
  wire lopt_41;
  wire lopt_42;
  wire lopt_43;
  wire lopt_44;
  wire lopt_45;
  wire lopt_46;
  wire lopt_47;
  wire lopt_48;
  wire lopt_49;
  wire \^lopt_5 ;
  wire lopt_50;
  wire lopt_51;
  wire lopt_52;
  wire lopt_53;
  wire lopt_54;
  wire lopt_55;
  wire lopt_56;
  wire lopt_57;
  wire lopt_58;
  wire lopt_59;
  wire \^lopt_6 ;
  wire lopt_60;
  wire lopt_61;
  wire lopt_62;
  wire lopt_63;
  wire lopt_64;
  wire lopt_65;
  wire lopt_66;
  wire lopt_67;
  wire lopt_68;
  wire lopt_69;
  wire \^lopt_7 ;
  wire lopt_70;
  wire lopt_71;
  wire lopt_72;
  wire lopt_73;
  wire lopt_74;
  wire lopt_75;
  wire lopt_76;
  wire lopt_77;
  wire lopt_78;
  wire lopt_79;
  wire \^lopt_8 ;
  wire lopt_80;
  wire lopt_81;
  wire lopt_82;
  wire lopt_83;
  wire lopt_84;
  wire lopt_85;
  wire lopt_86;
  wire lopt_87;
  wire lopt_88;
  wire lopt_89;
  wire \^lopt_9 ;
  wire lopt_90;
  wire lopt_91;
  wire lopt_92;
  wire lopt_93;
  wire lopt_94;
  wire lopt_95;
  wire lopt_96;
  wire lopt_97;
  wire lopt_98;
  wire lopt_99;

  assign lopt_100 = lopt_7;
  assign lopt_101 = lopt_8;
  assign lopt_102 = lopt_9;
  assign lopt_103 = lopt_10;
  assign lopt_104 = lopt_11;
  assign lopt_105 = lopt_12;
  assign lopt_13 = \^lopt_12 ;
  assign lopt_14 = \^lopt_9 ;
  assign lopt_15 = \^lopt_6 ;
  assign lopt_16 = lopt_106;
  assign lopt_17 = \^lopt_13 ;
  assign lopt_18 = \^lopt_10 ;
  assign lopt_19 = \^lopt_7 ;
  assign lopt_20 = lopt_107;
  assign lopt_98 = lopt_5;
  assign lopt_99 = lopt_6;
  design_1_microblaze_0_0_MB_MUXCY_488 \Use_Carry_Decoding.CarryIn_MUXCY 
       (.CI(alu_carry_in),
        .DI_0(DI_0),
        .ex_alu_carryin(ex_alu_carryin),
        .ex_use_carry(ex_use_carry),
        .lopt(lopt));
  design_1_microblaze_0_0_ALU_Bit__parameterized2 \Using_FPGA.ALL_Bits[0].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[0] (LO),
        .\EX_Op2_reg[0]_0 (\EX_Op2_reg[0] [29]),
        .I0(I0),
        .I2(I2),
        .LO(alu_carry_31),
        .\MEM_DataBus_Addr_reg[0] (\MEM_DataBus_Addr_reg[9] ),
        .Q(Q[31]),
        .S(S),
        .\Using_FPGA.Native (\Using_FPGA.Native [31]),
        .ex_unsigned_op(ex_unsigned_op),
        .lopt(lopt_92),
        .lopt_1(lopt_93),
        .lopt_2(lopt_94),
        .lopt_3(lopt_95),
        .lopt_4(lopt_97));
  design_1_microblaze_0_0_ALU_Bit \Using_FPGA.ALL_Bits[10].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_22),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[10] (\EX_Op2_reg[0] [19]),
        .LO(alu_carry_21),
        .\MEM_DataBus_Addr_reg[10] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[10]_0 (\Using_FPGA.Native [21]),
        .Q(Q[21]),
        .lopt(lopt_65),
        .lopt_1(lopt_66),
        .lopt_10(lopt_75),
        .lopt_11(lopt_76),
        .lopt_12(lopt_128),
        .lopt_13(lopt_129),
        .lopt_14(lopt_130),
        .lopt_15(lopt_131),
        .lopt_16(lopt_132),
        .lopt_17(lopt_133),
        .lopt_18(lopt_134),
        .lopt_19(lopt_135),
        .lopt_2(lopt_67),
        .lopt_20(lopt_84),
        .lopt_21(lopt_81),
        .lopt_22(lopt_78),
        .lopt_23(lopt_136),
        .lopt_24(lopt_85),
        .lopt_25(lopt_82),
        .lopt_26(lopt_79),
        .lopt_27(lopt_137),
        .lopt_3(lopt_68),
        .lopt_4(lopt_69),
        .lopt_5(lopt_70),
        .lopt_6(lopt_71),
        .lopt_7(lopt_72),
        .lopt_8(lopt_73),
        .lopt_9(lopt_74));
  design_1_microblaze_0_0_ALU_Bit_489 \Using_FPGA.ALL_Bits[11].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_21),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[11] (\EX_Op2_reg[0] [18]),
        .LO(alu_carry_20),
        .\MEM_DataBus_Addr_reg[11] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[11]_0 (\Using_FPGA.Native [20]),
        .Q(Q[20]),
        .lopt(lopt_59),
        .lopt_1(lopt_60),
        .lopt_2(lopt_61),
        .lopt_3(lopt_64));
  design_1_microblaze_0_0_ALU_Bit_490 \Using_FPGA.ALL_Bits[12].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_20),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[12] (\EX_Op2_reg[0] [17]),
        .LO(alu_carry_19),
        .\MEM_DataBus_Addr_reg[12] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[12]_0 (\Using_FPGA.Native [19]),
        .Q(Q[19]),
        .lopt(lopt_56),
        .lopt_1(lopt_57),
        .lopt_2(lopt_58),
        .lopt_3(lopt_63));
  design_1_microblaze_0_0_ALU_Bit_491 \Using_FPGA.ALL_Bits[13].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_19),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[13] (\EX_Op2_reg[0] [16]),
        .LO(alu_carry_18),
        .\MEM_DataBus_Addr_reg[13] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[13]_0 (\Using_FPGA.Native [18]),
        .Q(Q[18]),
        .lopt(lopt_53),
        .lopt_1(lopt_54),
        .lopt_2(lopt_55),
        .lopt_3(lopt_62));
  design_1_microblaze_0_0_ALU_Bit_492 \Using_FPGA.ALL_Bits[14].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_18),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[14] (\EX_Op2_reg[0] [15]),
        .LO(alu_carry_17),
        .\MEM_DataBus_Addr_reg[14] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[14]_0 (\Using_FPGA.Native [17]),
        .Q(Q[17]),
        .lopt(lopt_53),
        .lopt_1(lopt_54),
        .lopt_10(lopt_63),
        .lopt_11(lopt_64),
        .lopt_12(lopt_118),
        .lopt_13(lopt_119),
        .lopt_14(lopt_120),
        .lopt_15(lopt_121),
        .lopt_16(lopt_122),
        .lopt_17(lopt_123),
        .lopt_18(lopt_124),
        .lopt_19(lopt_125),
        .lopt_2(lopt_55),
        .lopt_20(lopt_126),
        .lopt_21(lopt_127),
        .lopt_3(lopt_56),
        .lopt_4(lopt_57),
        .lopt_5(lopt_58),
        .lopt_6(lopt_59),
        .lopt_7(lopt_60),
        .lopt_8(lopt_61),
        .lopt_9(lopt_62));
  design_1_microblaze_0_0_ALU_Bit_493 \Using_FPGA.ALL_Bits[15].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_17),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[15] (\EX_Op2_reg[0] [14]),
        .LO(alu_carry_16),
        .\MEM_DataBus_Addr_reg[15] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[15]_0 (\Using_FPGA.Native [16]),
        .Q(Q[16]),
        .lopt(lopt_47),
        .lopt_1(lopt_48),
        .lopt_2(lopt_49),
        .lopt_3(lopt_52));
  design_1_microblaze_0_0_ALU_Bit_494 \Using_FPGA.ALL_Bits[16].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_16),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[16] (\EX_Op2_reg[0] [13]),
        .LO(alu_carry_15),
        .\MEM_DataBus_Addr_reg[16] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[16]_0 (\Using_FPGA.Native [15]),
        .Q(Q[15]),
        .lopt(lopt_44),
        .lopt_1(lopt_45),
        .lopt_2(lopt_46),
        .lopt_3(lopt_51));
  design_1_microblaze_0_0_ALU_Bit_495 \Using_FPGA.ALL_Bits[17].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_15),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[17] (\EX_Op2_reg[0] [12]),
        .LO(alu_carry_14),
        .\MEM_DataBus_Addr_reg[17] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[17]_0 (\Using_FPGA.Native [14]),
        .Q(Q[14]),
        .lopt(lopt_41),
        .lopt_1(lopt_42),
        .lopt_2(lopt_43),
        .lopt_3(lopt_50));
  design_1_microblaze_0_0_ALU_Bit_496 \Using_FPGA.ALL_Bits[18].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_14),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[18] (\EX_Op2_reg[0] [11]),
        .LO(alu_carry_13),
        .\MEM_DataBus_Addr_reg[18] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[18]_0 (\Using_FPGA.Native [13]),
        .Q(Q[13]),
        .lopt(lopt_41),
        .lopt_1(lopt_42),
        .lopt_10(lopt_51),
        .lopt_11(lopt_52),
        .lopt_12(lopt_118),
        .lopt_13(lopt_119),
        .lopt_14(lopt_120),
        .lopt_15(lopt_121),
        .lopt_16(lopt_122),
        .lopt_17(lopt_123),
        .lopt_18(lopt_124),
        .lopt_19(lopt_125),
        .lopt_2(lopt_43),
        .lopt_20(lopt_60),
        .lopt_21(lopt_57),
        .lopt_22(lopt_54),
        .lopt_23(lopt_126),
        .lopt_24(lopt_61),
        .lopt_25(lopt_58),
        .lopt_26(lopt_55),
        .lopt_27(lopt_127),
        .lopt_3(lopt_44),
        .lopt_4(lopt_45),
        .lopt_5(lopt_46),
        .lopt_6(lopt_47),
        .lopt_7(lopt_48),
        .lopt_8(lopt_49),
        .lopt_9(lopt_50));
  design_1_microblaze_0_0_ALU_Bit_497 \Using_FPGA.ALL_Bits[19].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_13),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[19] (\EX_Op2_reg[0] [10]),
        .LO(alu_carry_12),
        .\MEM_DataBus_Addr_reg[19] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[19]_0 (\Using_FPGA.Native [12]),
        .Q(Q[12]),
        .lopt(lopt_35),
        .lopt_1(lopt_36),
        .lopt_2(lopt_37),
        .lopt_3(lopt_40));
  design_1_microblaze_0_0_ALU_Bit_498 \Using_FPGA.ALL_Bits[1].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_31),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[1] (\EX_Op2_reg[0] [28]),
        .LO(alu_carry_30),
        .\MEM_DataBus_Addr_reg[1] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[1]_0 (\Using_FPGA.Native [30]),
        .Q(Q[30]),
        .lopt(lopt_89),
        .lopt_1(lopt_90),
        .lopt_2(lopt_91),
        .lopt_3(lopt_96));
  design_1_microblaze_0_0_ALU_Bit_499 \Using_FPGA.ALL_Bits[20].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_12),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[20] (\EX_Op2_reg[0] [9]),
        .LO(alu_carry_11),
        .\MEM_DataBus_Addr_reg[20] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[20]_0 (\Using_FPGA.Native [11]),
        .Q(Q[11]),
        .lopt(lopt_32),
        .lopt_1(lopt_33),
        .lopt_2(lopt_34),
        .lopt_3(lopt_39));
  design_1_microblaze_0_0_ALU_Bit_500 \Using_FPGA.ALL_Bits[21].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_11),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[21] (\EX_Op2_reg[0] [8]),
        .LO(alu_carry_10),
        .\MEM_DataBus_Addr_reg[21] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[21]_0 (\Using_FPGA.Native [10]),
        .Q(Q[10]),
        .lopt(lopt_29),
        .lopt_1(lopt_30),
        .lopt_2(lopt_31),
        .lopt_3(lopt_38));
  design_1_microblaze_0_0_ALU_Bit_501 \Using_FPGA.ALL_Bits[22].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_10),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[22] (\EX_Op2_reg[0] [7]),
        .LO(alu_carry_9),
        .\MEM_DataBus_Addr_reg[22] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[22]_0 (\Using_FPGA.Native [9]),
        .Q(Q[9]),
        .lopt(lopt_29),
        .lopt_1(lopt_30),
        .lopt_10(lopt_39),
        .lopt_11(lopt_40),
        .lopt_12(lopt_108),
        .lopt_13(lopt_109),
        .lopt_14(lopt_110),
        .lopt_15(lopt_111),
        .lopt_16(lopt_112),
        .lopt_17(lopt_113),
        .lopt_18(lopt_114),
        .lopt_19(lopt_115),
        .lopt_2(lopt_31),
        .lopt_20(lopt_116),
        .lopt_21(lopt_117),
        .lopt_3(lopt_32),
        .lopt_4(lopt_33),
        .lopt_5(lopt_34),
        .lopt_6(lopt_35),
        .lopt_7(lopt_36),
        .lopt_8(lopt_37),
        .lopt_9(lopt_38));
  design_1_microblaze_0_0_ALU_Bit_502 \Using_FPGA.ALL_Bits[23].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_9),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[23] (\EX_Op2_reg[0] [6]),
        .LO(alu_carry_8),
        .\MEM_DataBus_Addr_reg[23] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[23]_0 (\Using_FPGA.Native [8]),
        .Q(Q[8]),
        .lopt(lopt_23),
        .lopt_1(lopt_24),
        .lopt_2(lopt_25),
        .lopt_3(lopt_28));
  design_1_microblaze_0_0_ALU_Bit_503 \Using_FPGA.ALL_Bits[24].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_8),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[24] (\EX_Op2_reg[0] [5]),
        .LO(alu_carry_7),
        .\MEM_DataBus_Addr_reg[24] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[24]_0 (\Using_FPGA.Native [7]),
        .Q(Q[7]),
        .lopt(\^lopt_20 ),
        .lopt_1(lopt_21),
        .lopt_2(lopt_22),
        .lopt_3(lopt_27));
  design_1_microblaze_0_0_ALU_Bit_504 \Using_FPGA.ALL_Bits[25].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_7),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[25] (\EX_Op2_reg[0] [4]),
        .LO(alu_carry_6),
        .\MEM_DataBus_Addr_reg[25] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[25]_0 (\Using_FPGA.Native [6]),
        .Q(Q[6]),
        .lopt(\^lopt_17 ),
        .lopt_1(\^lopt_18 ),
        .lopt_2(\^lopt_19 ),
        .lopt_3(lopt_26));
  design_1_microblaze_0_0_ALU_Bit_505 \Using_FPGA.ALL_Bits[26].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_6),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[26] (\EX_Op2_reg[0] [3]),
        .LO(alu_carry_5),
        .\MEM_DataBus_Addr_reg[26] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[26]_0 (\Using_FPGA.Native [5]),
        .Q(Q[5]),
        .lopt(\^lopt_17 ),
        .lopt_1(\^lopt_18 ),
        .lopt_10(lopt_27),
        .lopt_11(lopt_28),
        .lopt_12(lopt_108),
        .lopt_13(lopt_109),
        .lopt_14(lopt_110),
        .lopt_15(lopt_111),
        .lopt_16(lopt_112),
        .lopt_17(lopt_113),
        .lopt_18(lopt_114),
        .lopt_19(lopt_115),
        .lopt_2(\^lopt_19 ),
        .lopt_20(lopt_36),
        .lopt_21(lopt_33),
        .lopt_22(lopt_30),
        .lopt_23(lopt_116),
        .lopt_24(lopt_37),
        .lopt_25(lopt_34),
        .lopt_26(lopt_31),
        .lopt_27(lopt_117),
        .lopt_3(\^lopt_20 ),
        .lopt_4(lopt_21),
        .lopt_5(lopt_22),
        .lopt_6(lopt_23),
        .lopt_7(lopt_24),
        .lopt_8(lopt_25),
        .lopt_9(lopt_26));
  design_1_microblaze_0_0_ALU_Bit_506 \Using_FPGA.ALL_Bits[27].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_5),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[27] (\EX_Op2_reg[0] [2]),
        .LO(alu_carry_4),
        .\MEM_DataBus_Addr_reg[27] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[27]_0 (\Using_FPGA.Native [4]),
        .Q(Q[4]),
        .lopt(\^lopt_11 ),
        .lopt_1(\^lopt_12 ),
        .lopt_2(\^lopt_13 ),
        .lopt_3(\^lopt_16 ));
  design_1_microblaze_0_0_ALU_Bit_507 \Using_FPGA.ALL_Bits[28].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_4),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[28] (\EX_Op2_reg[0] [1]),
        .LO(alu_carry_3),
        .\MEM_DataBus_Addr_reg[28] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[28]_0 (\Using_FPGA.Native [3]),
        .Q(Q[3]),
        .lopt(\^lopt_8 ),
        .lopt_1(\^lopt_9 ),
        .lopt_2(\^lopt_10 ),
        .lopt_3(\^lopt_15 ));
  design_1_microblaze_0_0_ALU_Bit_508 \Using_FPGA.ALL_Bits[29].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_3),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[29] (\EX_Op2_reg[0] [0]),
        .LO(alu_carry_2),
        .\MEM_DataBus_Addr_reg[29] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[29]_0 (\Using_FPGA.Native [2]),
        .Q(Q[2]),
        .lopt(\^lopt_5 ),
        .lopt_1(\^lopt_6 ),
        .lopt_2(\^lopt_7 ),
        .lopt_3(\^lopt_14 ));
  design_1_microblaze_0_0_ALU_Bit_509 \Using_FPGA.ALL_Bits[2].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_30),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[2] (\EX_Op2_reg[0] [27]),
        .LO(alu_carry_29),
        .\MEM_DataBus_Addr_reg[2] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[2]_0 (\Using_FPGA.Native [29]),
        .Q(Q[29]),
        .lopt(lopt_89),
        .lopt_1(lopt_90),
        .lopt_10(lopt_97),
        .lopt_2(lopt_91),
        .lopt_3(lopt_92),
        .lopt_4(ex_unsigned_op),
        .lopt_5(S),
        .lopt_6(lopt_93),
        .lopt_7(lopt_94),
        .lopt_8(lopt_95),
        .lopt_9(lopt_96));
  design_1_microblaze_0_0_ALU_Bit_510 \Using_FPGA.ALL_Bits[30].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_2),
        .EX_Enable_ALU(EX_Enable_ALU),
        .LO(alu_carry_1),
        .Q(Q[1]),
        .\Using_FPGA.Native_I2 (\MEM_DataBus_Addr_reg[9] ),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native [1]),
        .ex_databus_addr(ex_databus_addr[1]),
        .lopt(\^lopt_5 ),
        .lopt_1(\^lopt_6 ),
        .lopt_10(\^lopt_15 ),
        .lopt_11(\^lopt_16 ),
        .lopt_12(lopt_98),
        .lopt_13(lopt_99),
        .lopt_14(lopt_100),
        .lopt_15(lopt_101),
        .lopt_16(lopt_102),
        .lopt_17(lopt_103),
        .lopt_18(lopt_104),
        .lopt_19(lopt_105),
        .lopt_2(\^lopt_7 ),
        .lopt_20(lopt_106),
        .lopt_21(lopt_107),
        .lopt_3(\^lopt_8 ),
        .lopt_4(\^lopt_9 ),
        .lopt_5(\^lopt_10 ),
        .lopt_6(\^lopt_11 ),
        .lopt_7(\^lopt_12 ),
        .lopt_8(\^lopt_13 ),
        .lopt_9(\^lopt_14 ));
  design_1_microblaze_0_0_ALU_Bit_511 \Using_FPGA.ALL_Bits[31].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryIn(alu_carry_in),
        .EX_CarryOut(alu_carry_1),
        .EX_Enable_ALU(EX_Enable_ALU),
        .Q(Q[0]),
        .\Using_FPGA.Native_I2 (\MEM_DataBus_Addr_reg[9] ),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native [0]),
        .ex_databus_addr(ex_databus_addr[0]),
        .lopt(lopt_1),
        .lopt_1(lopt_2),
        .lopt_2(lopt_3),
        .lopt_3(lopt_4));
  design_1_microblaze_0_0_ALU_Bit_512 \Using_FPGA.ALL_Bits[3].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_29),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[3] (\EX_Op2_reg[0] [26]),
        .LO(alu_carry_28),
        .\MEM_DataBus_Addr_reg[3] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[3]_0 (\Using_FPGA.Native [28]),
        .Q(Q[28]),
        .lopt(lopt_83),
        .lopt_1(lopt_84),
        .lopt_2(lopt_85),
        .lopt_3(lopt_88));
  design_1_microblaze_0_0_ALU_Bit_513 \Using_FPGA.ALL_Bits[4].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_28),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[4] (\EX_Op2_reg[0] [25]),
        .LO(alu_carry_27),
        .\MEM_DataBus_Addr_reg[4] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[4]_0 (\Using_FPGA.Native [27]),
        .Q(Q[27]),
        .lopt(lopt_80),
        .lopt_1(lopt_81),
        .lopt_2(lopt_82),
        .lopt_3(lopt_87));
  design_1_microblaze_0_0_ALU_Bit_514 \Using_FPGA.ALL_Bits[5].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_27),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[5] (\EX_Op2_reg[0] [24]),
        .LO(alu_carry_26),
        .\MEM_DataBus_Addr_reg[5] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[5]_0 (\Using_FPGA.Native [26]),
        .Q(Q[26]),
        .lopt(lopt_77),
        .lopt_1(lopt_78),
        .lopt_2(lopt_79),
        .lopt_3(lopt_86));
  design_1_microblaze_0_0_ALU_Bit_515 \Using_FPGA.ALL_Bits[6].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_26),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[6] (\EX_Op2_reg[0] [23]),
        .LO(alu_carry_25),
        .\MEM_DataBus_Addr_reg[6] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[6]_0 (\Using_FPGA.Native [25]),
        .Q(Q[25]),
        .lopt(lopt_77),
        .lopt_1(lopt_78),
        .lopt_10(lopt_87),
        .lopt_11(lopt_88),
        .lopt_12(lopt_128),
        .lopt_13(lopt_129),
        .lopt_14(lopt_130),
        .lopt_15(lopt_131),
        .lopt_16(lopt_132),
        .lopt_17(lopt_133),
        .lopt_18(lopt_134),
        .lopt_19(lopt_135),
        .lopt_2(lopt_79),
        .lopt_20(lopt_136),
        .lopt_21(lopt_137),
        .lopt_3(lopt_80),
        .lopt_4(lopt_81),
        .lopt_5(lopt_82),
        .lopt_6(lopt_83),
        .lopt_7(lopt_84),
        .lopt_8(lopt_85),
        .lopt_9(lopt_86));
  design_1_microblaze_0_0_ALU_Bit_516 \Using_FPGA.ALL_Bits[7].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_25),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[7] (\EX_Op2_reg[0] [22]),
        .LO(alu_carry_24),
        .\MEM_DataBus_Addr_reg[7] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[7]_0 (\Using_FPGA.Native [24]),
        .Q(Q[24]),
        .lopt(lopt_71),
        .lopt_1(lopt_72),
        .lopt_2(lopt_73),
        .lopt_3(lopt_76));
  design_1_microblaze_0_0_ALU_Bit_517 \Using_FPGA.ALL_Bits[8].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryOut(alu_carry_24),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[8] (\EX_Op2_reg[0] [21]),
        .LO(alu_carry_23),
        .\MEM_DataBus_Addr_reg[8] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[8]_0 (\Using_FPGA.Native [23]),
        .Q(Q[23]),
        .lopt(lopt_68),
        .lopt_1(lopt_69),
        .lopt_2(lopt_70),
        .lopt_3(lopt_75));
  design_1_microblaze_0_0_ALU_Bit_518 \Using_FPGA.ALL_Bits[9].ALU_Bit_I1 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_CarryIn(alu_carry_22),
        .EX_CarryOut(alu_carry_23),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[9] (\EX_Op2_reg[0] [20]),
        .\MEM_DataBus_Addr_reg[9] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[9]_0 (\Using_FPGA.Native [22]),
        .Q(Q[22]),
        .lopt(lopt_65),
        .lopt_1(lopt_66),
        .lopt_2(lopt_67),
        .lopt_3(lopt_74));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit
   (EX_CarryOut,
    \EX_Op2_reg[10] ,
    Q,
    \MEM_DataBus_Addr_reg[10] ,
    \MEM_DataBus_Addr_reg[10]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[10] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[10] ;
  input [0:0]\MEM_DataBus_Addr_reg[10]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[10] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[10] ;
  wire [0:0]\MEM_DataBus_Addr_reg[10]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_27;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  design_1_microblaze_0_0_MB_LUT6_2_578 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[10] (\MEM_DataBus_Addr_reg[10] ),
        .\MEM_DataBus_Addr_reg[10]_0 (\MEM_DataBus_Addr_reg[10]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_579 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[10] (\EX_Op2_reg[10] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_20(lopt_20),
        .lopt_21(lopt_21),
        .lopt_22(lopt_22),
        .lopt_23(lopt_23),
        .lopt_24(lopt_24),
        .lopt_25(lopt_25),
        .lopt_26(lopt_26),
        .lopt_27(lopt_27),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_489
   (EX_CarryOut,
    \EX_Op2_reg[11] ,
    Q,
    \MEM_DataBus_Addr_reg[11] ,
    \MEM_DataBus_Addr_reg[11]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[11] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[11] ;
  input [0:0]\MEM_DataBus_Addr_reg[11]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[11] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[11] ;
  wire [0:0]\MEM_DataBus_Addr_reg[11]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_576 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[11] (\MEM_DataBus_Addr_reg[11] ),
        .\MEM_DataBus_Addr_reg[11]_0 (\MEM_DataBus_Addr_reg[11]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_577 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[11] (\EX_Op2_reg[11] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_490
   (EX_CarryOut,
    \EX_Op2_reg[12] ,
    Q,
    \MEM_DataBus_Addr_reg[12] ,
    \MEM_DataBus_Addr_reg[12]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[12] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[12] ;
  input [0:0]\MEM_DataBus_Addr_reg[12]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[12] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[12] ;
  wire [0:0]\MEM_DataBus_Addr_reg[12]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_574 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[12] (\MEM_DataBus_Addr_reg[12] ),
        .\MEM_DataBus_Addr_reg[12]_0 (\MEM_DataBus_Addr_reg[12]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_575 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[12] (\EX_Op2_reg[12] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_491
   (EX_CarryOut,
    \EX_Op2_reg[13] ,
    Q,
    \MEM_DataBus_Addr_reg[13] ,
    \MEM_DataBus_Addr_reg[13]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[13] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[13] ;
  input [0:0]\MEM_DataBus_Addr_reg[13]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[13] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[13] ;
  wire [0:0]\MEM_DataBus_Addr_reg[13]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_572 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[13] (\MEM_DataBus_Addr_reg[13] ),
        .\MEM_DataBus_Addr_reg[13]_0 (\MEM_DataBus_Addr_reg[13]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_573 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[13] (\EX_Op2_reg[13] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_492
   (EX_CarryOut,
    \EX_Op2_reg[14] ,
    Q,
    \MEM_DataBus_Addr_reg[14] ,
    \MEM_DataBus_Addr_reg[14]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[14] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[14] ;
  input [0:0]\MEM_DataBus_Addr_reg[14]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;
  output lopt_21;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[14] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[14] ;
  wire [0:0]\MEM_DataBus_Addr_reg[14]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  assign lopt_20 = op2_is_1;
  assign lopt_21 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_570 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[14] (\MEM_DataBus_Addr_reg[14] ),
        .\MEM_DataBus_Addr_reg[14]_0 (\MEM_DataBus_Addr_reg[14]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_571 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[14] (\EX_Op2_reg[14] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_493
   (EX_CarryOut,
    \EX_Op2_reg[15] ,
    Q,
    \MEM_DataBus_Addr_reg[15] ,
    \MEM_DataBus_Addr_reg[15]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[15] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[15] ;
  input [0:0]\MEM_DataBus_Addr_reg[15]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[15] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[15] ;
  wire [0:0]\MEM_DataBus_Addr_reg[15]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_568 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[15] (\MEM_DataBus_Addr_reg[15] ),
        .\MEM_DataBus_Addr_reg[15]_0 (\MEM_DataBus_Addr_reg[15]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_569 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[15] (\EX_Op2_reg[15] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_494
   (EX_CarryOut,
    \EX_Op2_reg[16] ,
    Q,
    \MEM_DataBus_Addr_reg[16] ,
    \MEM_DataBus_Addr_reg[16]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[16] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[16] ;
  input [0:0]\MEM_DataBus_Addr_reg[16]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[16] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[16] ;
  wire [0:0]\MEM_DataBus_Addr_reg[16]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_566 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[16] (\MEM_DataBus_Addr_reg[16] ),
        .\MEM_DataBus_Addr_reg[16]_0 (\MEM_DataBus_Addr_reg[16]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_567 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[16] (\EX_Op2_reg[16] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_495
   (EX_CarryOut,
    \EX_Op2_reg[17] ,
    Q,
    \MEM_DataBus_Addr_reg[17] ,
    \MEM_DataBus_Addr_reg[17]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[17] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[17] ;
  input [0:0]\MEM_DataBus_Addr_reg[17]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[17] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[17] ;
  wire [0:0]\MEM_DataBus_Addr_reg[17]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_564 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[17] (\MEM_DataBus_Addr_reg[17] ),
        .\MEM_DataBus_Addr_reg[17]_0 (\MEM_DataBus_Addr_reg[17]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_565 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[17] (\EX_Op2_reg[17] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_496
   (EX_CarryOut,
    \EX_Op2_reg[18] ,
    Q,
    \MEM_DataBus_Addr_reg[18] ,
    \MEM_DataBus_Addr_reg[18]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[18] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[18] ;
  input [0:0]\MEM_DataBus_Addr_reg[18]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[18] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[18] ;
  wire [0:0]\MEM_DataBus_Addr_reg[18]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_27;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  design_1_microblaze_0_0_MB_LUT6_2_562 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[18] (\MEM_DataBus_Addr_reg[18] ),
        .\MEM_DataBus_Addr_reg[18]_0 (\MEM_DataBus_Addr_reg[18]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_563 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[18] (\EX_Op2_reg[18] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_20(lopt_20),
        .lopt_21(lopt_21),
        .lopt_22(lopt_22),
        .lopt_23(lopt_23),
        .lopt_24(lopt_24),
        .lopt_25(lopt_25),
        .lopt_26(lopt_26),
        .lopt_27(lopt_27),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_497
   (EX_CarryOut,
    \EX_Op2_reg[19] ,
    Q,
    \MEM_DataBus_Addr_reg[19] ,
    \MEM_DataBus_Addr_reg[19]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[19] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[19] ;
  input [0:0]\MEM_DataBus_Addr_reg[19]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[19] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[19] ;
  wire [0:0]\MEM_DataBus_Addr_reg[19]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_560 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[19] (\MEM_DataBus_Addr_reg[19] ),
        .\MEM_DataBus_Addr_reg[19]_0 (\MEM_DataBus_Addr_reg[19]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_561 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[19] (\EX_Op2_reg[19] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_498
   (EX_CarryOut,
    \EX_Op2_reg[1] ,
    Q,
    \MEM_DataBus_Addr_reg[1] ,
    \MEM_DataBus_Addr_reg[1]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[1] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[1] ;
  input [0:0]\MEM_DataBus_Addr_reg[1]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[1] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[1] ;
  wire [0:0]\MEM_DataBus_Addr_reg[1]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_558 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[1] (\MEM_DataBus_Addr_reg[1] ),
        .\MEM_DataBus_Addr_reg[1]_0 (\MEM_DataBus_Addr_reg[1]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_559 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[1] (\EX_Op2_reg[1] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_499
   (EX_CarryOut,
    \EX_Op2_reg[20] ,
    Q,
    \MEM_DataBus_Addr_reg[20] ,
    \MEM_DataBus_Addr_reg[20]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[20] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[20] ;
  input [0:0]\MEM_DataBus_Addr_reg[20]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[20] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[20] ;
  wire [0:0]\MEM_DataBus_Addr_reg[20]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_556 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[20] (\MEM_DataBus_Addr_reg[20] ),
        .\MEM_DataBus_Addr_reg[20]_0 (\MEM_DataBus_Addr_reg[20]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_557 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[20] (\EX_Op2_reg[20] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_500
   (EX_CarryOut,
    \EX_Op2_reg[21] ,
    Q,
    \MEM_DataBus_Addr_reg[21] ,
    \MEM_DataBus_Addr_reg[21]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[21] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[21] ;
  input [0:0]\MEM_DataBus_Addr_reg[21]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[21] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[21] ;
  wire [0:0]\MEM_DataBus_Addr_reg[21]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_554 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[21] (\MEM_DataBus_Addr_reg[21] ),
        .\MEM_DataBus_Addr_reg[21]_0 (\MEM_DataBus_Addr_reg[21]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_555 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[21] (\EX_Op2_reg[21] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_501
   (EX_CarryOut,
    \EX_Op2_reg[22] ,
    Q,
    \MEM_DataBus_Addr_reg[22] ,
    \MEM_DataBus_Addr_reg[22]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[22] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[22] ;
  input [0:0]\MEM_DataBus_Addr_reg[22]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;
  output lopt_21;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[22] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[22] ;
  wire [0:0]\MEM_DataBus_Addr_reg[22]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  assign lopt_20 = op2_is_1;
  assign lopt_21 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_552 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[22] (\MEM_DataBus_Addr_reg[22] ),
        .\MEM_DataBus_Addr_reg[22]_0 (\MEM_DataBus_Addr_reg[22]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_553 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[22] (\EX_Op2_reg[22] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_502
   (EX_CarryOut,
    \EX_Op2_reg[23] ,
    Q,
    \MEM_DataBus_Addr_reg[23] ,
    \MEM_DataBus_Addr_reg[23]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[23] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[23] ;
  input [0:0]\MEM_DataBus_Addr_reg[23]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[23] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[23] ;
  wire [0:0]\MEM_DataBus_Addr_reg[23]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_550 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[23] (\MEM_DataBus_Addr_reg[23] ),
        .\MEM_DataBus_Addr_reg[23]_0 (\MEM_DataBus_Addr_reg[23]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_551 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[23] (\EX_Op2_reg[23] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_503
   (EX_CarryOut,
    \EX_Op2_reg[24] ,
    Q,
    \MEM_DataBus_Addr_reg[24] ,
    \MEM_DataBus_Addr_reg[24]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[24] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[24] ;
  input [0:0]\MEM_DataBus_Addr_reg[24]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[24] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[24] ;
  wire [0:0]\MEM_DataBus_Addr_reg[24]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_548 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[24] (\MEM_DataBus_Addr_reg[24] ),
        .\MEM_DataBus_Addr_reg[24]_0 (\MEM_DataBus_Addr_reg[24]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_549 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[24] (\EX_Op2_reg[24] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_504
   (EX_CarryOut,
    \EX_Op2_reg[25] ,
    Q,
    \MEM_DataBus_Addr_reg[25] ,
    \MEM_DataBus_Addr_reg[25]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[25] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[25] ;
  input [0:0]\MEM_DataBus_Addr_reg[25]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[25] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[25] ;
  wire [0:0]\MEM_DataBus_Addr_reg[25]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_546 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[25] (\MEM_DataBus_Addr_reg[25] ),
        .\MEM_DataBus_Addr_reg[25]_0 (\MEM_DataBus_Addr_reg[25]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_547 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[25] (\EX_Op2_reg[25] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_505
   (EX_CarryOut,
    \EX_Op2_reg[26] ,
    Q,
    \MEM_DataBus_Addr_reg[26] ,
    \MEM_DataBus_Addr_reg[26]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[26] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[26] ;
  input [0:0]\MEM_DataBus_Addr_reg[26]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[26] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[26] ;
  wire [0:0]\MEM_DataBus_Addr_reg[26]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_27;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  design_1_microblaze_0_0_MB_LUT6_2_544 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[26] (\MEM_DataBus_Addr_reg[26] ),
        .\MEM_DataBus_Addr_reg[26]_0 (\MEM_DataBus_Addr_reg[26]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_545 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[26] (\EX_Op2_reg[26] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_20(lopt_20),
        .lopt_21(lopt_21),
        .lopt_22(lopt_22),
        .lopt_23(lopt_23),
        .lopt_24(lopt_24),
        .lopt_25(lopt_25),
        .lopt_26(lopt_26),
        .lopt_27(lopt_27),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_506
   (EX_CarryOut,
    \EX_Op2_reg[27] ,
    Q,
    \MEM_DataBus_Addr_reg[27] ,
    \MEM_DataBus_Addr_reg[27]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[27] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[27] ;
  input [0:0]\MEM_DataBus_Addr_reg[27]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[27] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[27] ;
  wire [0:0]\MEM_DataBus_Addr_reg[27]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_542 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[27] (\MEM_DataBus_Addr_reg[27] ),
        .\MEM_DataBus_Addr_reg[27]_0 (\MEM_DataBus_Addr_reg[27]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_543 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[27] (\EX_Op2_reg[27] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_507
   (EX_CarryOut,
    \EX_Op2_reg[28] ,
    Q,
    \MEM_DataBus_Addr_reg[28] ,
    \MEM_DataBus_Addr_reg[28]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[28] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[28] ;
  input [0:0]\MEM_DataBus_Addr_reg[28]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[28] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[28] ;
  wire [0:0]\MEM_DataBus_Addr_reg[28]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_540 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[28] (\MEM_DataBus_Addr_reg[28] ),
        .\MEM_DataBus_Addr_reg[28]_0 (\MEM_DataBus_Addr_reg[28]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_541 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[28] (\EX_Op2_reg[28] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_508
   (EX_CarryOut,
    \EX_Op2_reg[29] ,
    Q,
    \MEM_DataBus_Addr_reg[29] ,
    \MEM_DataBus_Addr_reg[29]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[29] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[29] ;
  input [0:0]\MEM_DataBus_Addr_reg[29]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[29] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[29] ;
  wire [0:0]\MEM_DataBus_Addr_reg[29]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_538 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[29] (\MEM_DataBus_Addr_reg[29] ),
        .\MEM_DataBus_Addr_reg[29]_0 (\MEM_DataBus_Addr_reg[29]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_539 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[29] (\EX_Op2_reg[29] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_509
   (EX_CarryOut,
    \EX_Op2_reg[2] ,
    Q,
    \MEM_DataBus_Addr_reg[2] ,
    \MEM_DataBus_Addr_reg[2]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[2] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[2] ;
  input [0:0]\MEM_DataBus_Addr_reg[2]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[2] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[2] ;
  wire [0:0]\MEM_DataBus_Addr_reg[2]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  design_1_microblaze_0_0_MB_LUT6_2_536 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[2] (\MEM_DataBus_Addr_reg[2] ),
        .\MEM_DataBus_Addr_reg[2]_0 (\MEM_DataBus_Addr_reg[2]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_537 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[2] (\EX_Op2_reg[2] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_2(lopt_2),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_510
   (EX_CarryOut,
    ex_databus_addr,
    Q,
    \Using_FPGA.Native_I2 ,
    \Using_FPGA.Native_I2_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21);
  output EX_CarryOut;
  output [0:0]ex_databus_addr;
  input [0:0]Q;
  input [1:0]\Using_FPGA.Native_I2 ;
  input [0:0]\Using_FPGA.Native_I2_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;
  output lopt_21;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire LO;
  wire [0:0]Q;
  wire [1:0]\Using_FPGA.Native_I2 ;
  wire [0:0]\Using_FPGA.Native_I2_0 ;
  wire alu_AddSub;
  wire [0:0]ex_databus_addr;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  assign lopt_20 = op2_is_1;
  assign lopt_21 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_534 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .Q(Q),
        .S(alu_AddSub),
        .\Using_FPGA.Native_I2 (\Using_FPGA.Native_I2 ),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_I2_0 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_535 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .LO(LO),
        .S(alu_AddSub),
        .ex_databus_addr(ex_databus_addr),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_511
   (EX_CarryOut,
    ex_databus_addr,
    Q,
    \Using_FPGA.Native_I2 ,
    \Using_FPGA.Native_I2_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    EX_CarryIn,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]ex_databus_addr;
  input [0:0]Q;
  input [1:0]\Using_FPGA.Native_I2 ;
  input [0:0]\Using_FPGA.Native_I2_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input EX_CarryIn;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryIn;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]Q;
  wire [1:0]\Using_FPGA.Native_I2 ;
  wire [0:0]\Using_FPGA.Native_I2_0 ;
  wire alu_AddSub;
  wire [0:0]ex_databus_addr;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_532 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .Q(Q),
        .S(alu_AddSub),
        .\Using_FPGA.Native_I2 (\Using_FPGA.Native_I2 ),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_I2_0 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_533 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryIn(EX_CarryIn),
        .EX_CarryOut(EX_CarryOut),
        .S(alu_AddSub),
        .ex_databus_addr(ex_databus_addr),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_512
   (EX_CarryOut,
    \EX_Op2_reg[3] ,
    Q,
    \MEM_DataBus_Addr_reg[3] ,
    \MEM_DataBus_Addr_reg[3]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[3] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[3] ;
  input [0:0]\MEM_DataBus_Addr_reg[3]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[3] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[3] ;
  wire [0:0]\MEM_DataBus_Addr_reg[3]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_530 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[3] (\MEM_DataBus_Addr_reg[3] ),
        .\MEM_DataBus_Addr_reg[3]_0 (\MEM_DataBus_Addr_reg[3]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_531 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[3] (\EX_Op2_reg[3] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_513
   (EX_CarryOut,
    \EX_Op2_reg[4] ,
    Q,
    \MEM_DataBus_Addr_reg[4] ,
    \MEM_DataBus_Addr_reg[4]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[4] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[4] ;
  input [0:0]\MEM_DataBus_Addr_reg[4]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[4] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[4] ;
  wire [0:0]\MEM_DataBus_Addr_reg[4]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_528 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[4] (\MEM_DataBus_Addr_reg[4] ),
        .\MEM_DataBus_Addr_reg[4]_0 (\MEM_DataBus_Addr_reg[4]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_529 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[4] (\EX_Op2_reg[4] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_514
   (EX_CarryOut,
    \EX_Op2_reg[5] ,
    Q,
    \MEM_DataBus_Addr_reg[5] ,
    \MEM_DataBus_Addr_reg[5]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[5] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[5] ;
  input [0:0]\MEM_DataBus_Addr_reg[5]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[5] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[5] ;
  wire [0:0]\MEM_DataBus_Addr_reg[5]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_526 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[5] (\MEM_DataBus_Addr_reg[5] ),
        .\MEM_DataBus_Addr_reg[5]_0 (\MEM_DataBus_Addr_reg[5]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_527 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[5] (\EX_Op2_reg[5] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_515
   (EX_CarryOut,
    \EX_Op2_reg[6] ,
    Q,
    \MEM_DataBus_Addr_reg[6] ,
    \MEM_DataBus_Addr_reg[6]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[6] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[6] ;
  input [0:0]\MEM_DataBus_Addr_reg[6]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;
  output lopt_21;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[6] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[6] ;
  wire [0:0]\MEM_DataBus_Addr_reg[6]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire op2_is_1;

  assign lopt_20 = op2_is_1;
  assign lopt_21 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_524 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[6] (\MEM_DataBus_Addr_reg[6] ),
        .\MEM_DataBus_Addr_reg[6]_0 (\MEM_DataBus_Addr_reg[6]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_525 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[6] (\EX_Op2_reg[6] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_516
   (EX_CarryOut,
    \EX_Op2_reg[7] ,
    Q,
    \MEM_DataBus_Addr_reg[7] ,
    \MEM_DataBus_Addr_reg[7]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[7] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[7] ;
  input [0:0]\MEM_DataBus_Addr_reg[7]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[7] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[7] ;
  wire [0:0]\MEM_DataBus_Addr_reg[7]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_522 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[7] (\MEM_DataBus_Addr_reg[7] ),
        .\MEM_DataBus_Addr_reg[7]_0 (\MEM_DataBus_Addr_reg[7]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_523 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[7] (\EX_Op2_reg[7] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_517
   (EX_CarryOut,
    \EX_Op2_reg[8] ,
    Q,
    \MEM_DataBus_Addr_reg[8] ,
    \MEM_DataBus_Addr_reg[8]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[8] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[8] ;
  input [0:0]\MEM_DataBus_Addr_reg[8]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input LO;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[8] ;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[8] ;
  wire [0:0]\MEM_DataBus_Addr_reg[8]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2_520 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[8] (\MEM_DataBus_Addr_reg[8] ),
        .\MEM_DataBus_Addr_reg[8]_0 (\MEM_DataBus_Addr_reg[8]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_521 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[8] (\EX_Op2_reg[8] ),
        .LO(LO),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit_518
   (EX_CarryOut,
    \EX_Op2_reg[9] ,
    Q,
    \MEM_DataBus_Addr_reg[9] ,
    \MEM_DataBus_Addr_reg[9]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    EX_CarryIn,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[9] ;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[9] ;
  input [0:0]\MEM_DataBus_Addr_reg[9]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input EX_CarryIn;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;

  wire EX_ALU_Sel_Logic;
  wire EX_CarryIn;
  wire EX_CarryOut;
  wire EX_Enable_ALU;
  wire [0:0]\EX_Op2_reg[9] ;
  wire [1:0]\MEM_DataBus_Addr_reg[9] ;
  wire [0:0]\MEM_DataBus_Addr_reg[9]_0 ;
  wire [0:0]Q;
  wire alu_AddSub;
  wire lopt;
  wire \^lopt_1 ;
  wire op2_is_1;

  assign \^lopt_1  = lopt_3;
  assign lopt_1 = op2_is_1;
  assign lopt_2 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT6_2 \Not_Last_Bit.I_ALU_LUT_V5 
       (.DI(op2_is_1),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\MEM_DataBus_Addr_reg[9] (\MEM_DataBus_Addr_reg[9] ),
        .\MEM_DataBus_Addr_reg[9]_0 (\MEM_DataBus_Addr_reg[9]_0 ),
        .Q(Q),
        .S(alu_AddSub));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_519 \Not_Last_Bit.MUXCY_XOR_I 
       (.DI(op2_is_1),
        .EX_CarryIn(EX_CarryIn),
        .EX_CarryOut(EX_CarryOut),
        .\EX_Op2_reg[9] (\EX_Op2_reg[9] ),
        .S(alu_AddSub),
        .lopt(lopt),
        .lopt_1(\^lopt_1 ));
endmodule

(* ORIG_REF_NAME = "ALU_Bit" *) 
module design_1_microblaze_0_0_ALU_Bit__parameterized2
   (\EX_Op2_reg[0] ,
    \EX_Op2_reg[0]_0 ,
    S,
    ex_unsigned_op,
    LO,
    Q,
    \MEM_DataBus_Addr_reg[0] ,
    \Using_FPGA.Native ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    I2,
    I0,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4);
  output \EX_Op2_reg[0] ;
  output [0:0]\EX_Op2_reg[0]_0 ;
  input S;
  input ex_unsigned_op;
  input LO;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[0] ;
  input [0:0]\Using_FPGA.Native ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input I2;
  input I0;
  input lopt;
  input lopt_1;
  output lopt_2;
  output lopt_3;
  input lopt_4;

  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire \EX_Op2_reg[0] ;
  wire [0:0]\EX_Op2_reg[0]_0 ;
  wire I0;
  wire I2;
  wire LO;
  wire [1:0]\MEM_DataBus_Addr_reg[0] ;
  wire [0:0]Q;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire alu_AddSub;
  wire alu_AddSub_1;
  wire ex_unsigned_op;
  wire invert_result;
  wire lopt;
  wire lopt_1;
  wire \^lopt_2 ;
  wire op2_is_1;

  assign \^lopt_2  = lopt_4;
  assign lopt_2 = op2_is_1;
  assign lopt_3 = alu_AddSub;
  design_1_microblaze_0_0_MB_LUT4 \Last_Bit.I_ALU_LUT_2 
       (.I2(I2),
        .\MEM_DataBus_Addr_reg[0] (\MEM_DataBus_Addr_reg[0] [1]),
        .Q(Q),
        .S(alu_AddSub),
        .alu_AddSub_1(alu_AddSub_1));
  design_1_microblaze_0_0_MB_LUT6__parameterized12 \Last_Bit.I_ALU_LUT_V5 
       (.EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .Q(Q),
        .\Using_FPGA.Native_0 (\MEM_DataBus_Addr_reg[0] ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .alu_AddSub_1(alu_AddSub_1));
  design_1_microblaze_0_0_MB_MULT_AND \Last_Bit.MULT_AND_I 
       (.DI(op2_is_1),
        .I0(I0),
        .\Using_FPGA.Native_I1 (\MEM_DataBus_Addr_reg[0] [1]));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_580 \Last_Bit.MUXCY_XOR_I 
       (.CI(invert_result),
        .DI(op2_is_1),
        .\EX_Op2_reg[0] (\EX_Op2_reg[0] ),
        .\EX_Op2_reg[0]_0 (\EX_Op2_reg[0]_0 ),
        .S(alu_AddSub),
        .lopt(lopt_1),
        .lopt_1(\^lopt_2 ));
  design_1_microblaze_0_0_MB_MUXCY_581 \Last_Bit.Pre_MUXCY_I 
       (.CI(invert_result),
        .LO(LO),
        .S(S),
        .ex_unsigned_op(ex_unsigned_op),
        .lopt(lopt));
endmodule

(* ORIG_REF_NAME = "Byte_Doublet_Handle_gti" *) 
module design_1_microblaze_0_0_Byte_Doublet_Handle_gti
   (\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0 ,
    wb_read_msb_doublet_sel,
    \MEM_DataBus_Write_Data_reg[0]_0 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0 ,
    sync_reset,
    mem_reverse_byteorder_reg_0,
    ex_reverse_mem_access,
    Clk,
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 ,
    D,
    \MEM_DataBus_Byte_Enable_reg[0]_0 ,
    \mem_byte_selects_reg[0]_0 ,
    \mem_byte_selects_reg[1]_0 ,
    mem_byte_access,
    mem_doublet_access);
  output \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0 ;
  output wb_read_msb_doublet_sel;
  output [35:0]\MEM_DataBus_Write_Data_reg[0]_0 ;
  output [1:0]\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0 ;
  input sync_reset;
  input mem_reverse_byteorder_reg_0;
  input ex_reverse_mem_access;
  input Clk;
  input \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 ;
  input [31:0]D;
  input [3:0]\MEM_DataBus_Byte_Enable_reg[0]_0 ;
  input \mem_byte_selects_reg[0]_0 ;
  input [0:0]\mem_byte_selects_reg[1]_0 ;
  input mem_byte_access;
  input mem_doublet_access;

  wire Clk;
  wire [31:0]D;
  wire [3:0]\MEM_DataBus_Byte_Enable_reg[0]_0 ;
  wire [35:0]\MEM_DataBus_Write_Data_reg[0]_0 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1_n_0 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1_n_0 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1_n_0 ;
  wire [1:0]\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 ;
  wire ex_reverse_mem_access;
  wire mem_byte_access;
  wire \mem_byte_selects_reg[0]_0 ;
  wire [0:0]\mem_byte_selects_reg[1]_0 ;
  wire \mem_byte_selects_reg_n_0_[1] ;
  wire mem_doublet_access;
  wire mem_reverse_byteorder;
  wire mem_reverse_byteorder_reg_0;
  wire p_0_in;
  wire sync_reset;
  wire wb_read_msb_doublet_sel;

  FDRE \MEM_DataBus_Byte_Enable_reg[0] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(\MEM_DataBus_Byte_Enable_reg[0]_0 [3]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [3]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Byte_Enable_reg[1] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(\MEM_DataBus_Byte_Enable_reg[0]_0 [2]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [2]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Byte_Enable_reg[2] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(\MEM_DataBus_Byte_Enable_reg[0]_0 [1]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [1]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Byte_Enable_reg[3] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(\MEM_DataBus_Byte_Enable_reg[0]_0 [0]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [0]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[0] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[31]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [35]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[10] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[21]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [25]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[11] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[20]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [24]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[12] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[19]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [23]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[13] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[18]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [22]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[14] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[17]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [21]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[15] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[16]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [20]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[16] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[15]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [19]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[17] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[14]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [18]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[18] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[13]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [17]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[19] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[12]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [16]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[1] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[30]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [34]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[20] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[11]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [15]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[21] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[10]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [14]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[22] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[9]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [13]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[23] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[8]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [12]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[24] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[7]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [11]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[25] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[6]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [10]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[26] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[5]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [9]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[27] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[4]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [8]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[28] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[3]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [7]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[29] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[2]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [6]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[2] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[29]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [33]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[30] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[1]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [5]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[31] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[0]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [4]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[3] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[28]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [32]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[4] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[27]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [31]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[5] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[26]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [30]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[6] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[25]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [29]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[7] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[24]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [28]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[8] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[23]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [27]),
        .R(sync_reset));
  FDRE \MEM_DataBus_Write_Data_reg[9] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(D[22]),
        .Q(\MEM_DataBus_Write_Data_reg[0]_0 [26]),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'h8B)) 
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1 
       (.I0(p_0_in),
        .I1(mem_doublet_access),
        .I2(mem_reverse_byteorder),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1_n_0 ));
  FDRE \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0] 
       (.C(Clk),
        .CE(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 ),
        .D(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel[0]_i_1_n_0 ),
        .Q(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0 ),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hC8CD)) 
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1 
       (.I0(mem_byte_access),
        .I1(p_0_in),
        .I2(mem_doublet_access),
        .I3(mem_reverse_byteorder),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h8B)) 
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1 
       (.I0(\mem_byte_selects_reg_n_0_[1] ),
        .I1(mem_byte_access),
        .I2(mem_reverse_byteorder),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1_n_0 ));
  FDRE \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0] 
       (.C(Clk),
        .CE(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 ),
        .D(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[0]_i_1_n_0 ),
        .Q(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0 [1]),
        .R(sync_reset));
  FDRE \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1] 
       (.C(Clk),
        .CE(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 ),
        .D(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel[1]_i_1_n_0 ),
        .Q(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0 [0]),
        .R(sync_reset));
  FDRE \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg 
       (.C(Clk),
        .CE(\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 ),
        .D(mem_reverse_byteorder),
        .Q(wb_read_msb_doublet_sel),
        .R(sync_reset));
  FDRE \mem_byte_selects_reg[0] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(\mem_byte_selects_reg[0]_0 ),
        .Q(p_0_in),
        .R(sync_reset));
  FDRE \mem_byte_selects_reg[1] 
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(\mem_byte_selects_reg[1]_0 ),
        .Q(\mem_byte_selects_reg_n_0_[1] ),
        .R(sync_reset));
  FDRE mem_reverse_byteorder_reg
       (.C(Clk),
        .CE(mem_reverse_byteorder_reg_0),
        .D(ex_reverse_mem_access),
        .Q(mem_reverse_byteorder),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "DAXI_interface" *) 
module design_1_microblaze_0_0_DAXI_interface
   (active_access_d1,
    active_access,
    D,
    MEM_DataBus_Ready,
    wb_databus_steered_read_data,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg ,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6 ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[23] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[22] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[21] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[20] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[19] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[18] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[17] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[16] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[31] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[30] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[29] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[28] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[27] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[26] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[25] ,
    \Use_DLMB.wb_dlmb_valid_read_data_reg[24] ,
    sync_reset,
    Clk,
    active_access_reg_0,
    M_AXI_DP_AWVALID_i_reg_0,
    M_AXI_DP_WVALID_i_reg_0,
    M_AXI_DP_ARVALID_i_reg_0,
    DReady,
    \LOCKSTEP_Out_reg[3031] ,
    wb_read_msb_doublet_sel,
    \LOCKSTEP_Out_reg[3023] ,
    Q,
    M_AXI_DP_RVALID,
    M_AXI_DP_BVALID,
    M_AXI_DP_RDATA);
  output active_access_d1;
  output active_access;
  output [2:0]D;
  output MEM_DataBus_Ready;
  output [7:0]wb_databus_steered_read_data;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0 ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1 ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2 ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3 ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4 ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5 ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6 ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[23] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[22] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[21] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[20] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[19] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[18] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[17] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[16] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[31] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[30] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[29] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[28] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[27] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[26] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[25] ;
  output \Use_DLMB.wb_dlmb_valid_read_data_reg[24] ;
  input sync_reset;
  input Clk;
  input active_access_reg_0;
  input M_AXI_DP_AWVALID_i_reg_0;
  input M_AXI_DP_WVALID_i_reg_0;
  input M_AXI_DP_ARVALID_i_reg_0;
  input DReady;
  input [1:0]\LOCKSTEP_Out_reg[3031] ;
  input wb_read_msb_doublet_sel;
  input \LOCKSTEP_Out_reg[3023] ;
  input [31:0]Q;
  input M_AXI_DP_RVALID;
  input M_AXI_DP_BVALID;
  input [31:0]M_AXI_DP_RDATA;

  wire Clk;
  wire [2:0]D;
  wire DReady;
  wire \LOCKSTEP_Out_reg[3023] ;
  wire [1:0]\LOCKSTEP_Out_reg[3031] ;
  wire MEM_DAXI_Data_Strobe;
  wire MEM_DataBus_Ready;
  wire M_AXI_DP_ARVALID_i_reg_0;
  wire M_AXI_DP_AWVALID_i_reg_0;
  wire M_AXI_DP_BVALID;
  wire [31:0]M_AXI_DP_RDATA;
  wire M_AXI_DP_RVALID;
  wire M_AXI_DP_WVALID_i_reg_0;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5 ;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6 ;
  wire [31:0]Q;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[16] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[17] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[18] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[19] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[20] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[21] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[22] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[23] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[24] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[25] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[26] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[27] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[28] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[29] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[30] ;
  wire \Use_DLMB.wb_dlmb_valid_read_data_reg[31] ;
  wire active_access;
  wire active_access_d1;
  wire active_access_reg_0;
  wire mem_access_completed0;
  wire sync_reset;
  wire [0:31]wb_databus_read_data;
  wire [7:0]wb_databus_steered_read_data;
  wire wb_dext_Data_Strobe;
  wire [0:31]wb_dext_read_data;
  wire wb_read_msb_doublet_sel;

  FDRE #(
    .INIT(1'b0)) 
    M_AXI_DP_ARVALID_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARVALID_i_reg_0),
        .Q(D[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    M_AXI_DP_AWVALID_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_AWVALID_i_reg_0),
        .Q(D[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    M_AXI_DP_WVALID_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WVALID_i_reg_0),
        .Q(D[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[0]_INST_0_i_1 
       (.I0(Q[7]),
        .I1(wb_dext_read_data[24]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[31]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[0]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[24] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[10]_INST_0_i_1 
       (.I0(Q[13]),
        .I1(wb_dext_read_data[18]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[21]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[10]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[18] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[11]_INST_0_i_1 
       (.I0(Q[12]),
        .I1(wb_dext_read_data[19]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[20]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[11]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[19] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[12]_INST_0_i_1 
       (.I0(Q[11]),
        .I1(wb_dext_read_data[20]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[19]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[12]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[20] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[13]_INST_0_i_1 
       (.I0(Q[10]),
        .I1(wb_dext_read_data[21]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[18]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[13]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[21] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[14]_INST_0_i_1 
       (.I0(Q[9]),
        .I1(wb_dext_read_data[22]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[17]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[14]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[22] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[15]_INST_0_i_1 
       (.I0(Q[8]),
        .I1(wb_dext_read_data[23]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[16]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[15]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[23] ));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[16]_INST_0_i_1 
       (.I0(wb_databus_read_data[8]),
        .I1(wb_databus_read_data[0]),
        .I2(wb_databus_read_data[24]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[16]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[16]_INST_0_i_2 
       (.I0(Q[23]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[8]),
        .O(wb_databus_read_data[8]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[16]_INST_0_i_3 
       (.I0(Q[31]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[0]),
        .O(wb_databus_read_data[0]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[16]_INST_0_i_4 
       (.I0(Q[7]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[24]),
        .O(wb_databus_read_data[24]));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[16]_INST_0_i_5 
       (.I0(Q[15]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[16]),
        .O(wb_databus_read_data[16]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[17]_INST_0_i_1 
       (.I0(wb_databus_read_data[9]),
        .I1(wb_databus_read_data[1]),
        .I2(wb_databus_read_data[25]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[17]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[17]_INST_0_i_2 
       (.I0(Q[22]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[9]),
        .O(wb_databus_read_data[9]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[17]_INST_0_i_3 
       (.I0(Q[30]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[1]),
        .O(wb_databus_read_data[1]));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[17]_INST_0_i_4 
       (.I0(Q[6]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[25]),
        .O(wb_databus_read_data[25]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[17]_INST_0_i_5 
       (.I0(Q[14]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[17]),
        .O(wb_databus_read_data[17]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[18]_INST_0_i_1 
       (.I0(wb_databus_read_data[10]),
        .I1(wb_databus_read_data[2]),
        .I2(wb_databus_read_data[26]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[18]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1 ));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[18]_INST_0_i_2 
       (.I0(Q[21]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[10]),
        .O(wb_databus_read_data[10]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[18]_INST_0_i_3 
       (.I0(Q[29]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[2]),
        .O(wb_databus_read_data[2]));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[18]_INST_0_i_4 
       (.I0(Q[5]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[26]),
        .O(wb_databus_read_data[26]));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[18]_INST_0_i_5 
       (.I0(Q[13]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[18]),
        .O(wb_databus_read_data[18]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[19]_INST_0_i_1 
       (.I0(wb_databus_read_data[11]),
        .I1(wb_databus_read_data[3]),
        .I2(wb_databus_read_data[27]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[19]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[19]_INST_0_i_2 
       (.I0(Q[20]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[11]),
        .O(wb_databus_read_data[11]));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[19]_INST_0_i_3 
       (.I0(Q[28]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[3]),
        .O(wb_databus_read_data[3]));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[19]_INST_0_i_4 
       (.I0(Q[4]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[27]),
        .O(wb_databus_read_data[27]));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[19]_INST_0_i_5 
       (.I0(Q[12]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[19]),
        .O(wb_databus_read_data[19]));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[1]_INST_0_i_1 
       (.I0(Q[6]),
        .I1(wb_dext_read_data[25]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[30]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[1]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[25] ));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[20]_INST_0_i_1 
       (.I0(wb_databus_read_data[12]),
        .I1(wb_databus_read_data[4]),
        .I2(wb_databus_read_data[28]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[20]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[20]_INST_0_i_2 
       (.I0(Q[19]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[12]),
        .O(wb_databus_read_data[12]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[20]_INST_0_i_3 
       (.I0(Q[27]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[4]),
        .O(wb_databus_read_data[4]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[20]_INST_0_i_4 
       (.I0(Q[3]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[28]),
        .O(wb_databus_read_data[28]));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[20]_INST_0_i_5 
       (.I0(Q[11]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[20]),
        .O(wb_databus_read_data[20]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[21]_INST_0_i_1 
       (.I0(wb_databus_read_data[13]),
        .I1(wb_databus_read_data[5]),
        .I2(wb_databus_read_data[29]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[21]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[21]_INST_0_i_2 
       (.I0(Q[18]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[13]),
        .O(wb_databus_read_data[13]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[21]_INST_0_i_3 
       (.I0(Q[26]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[5]),
        .O(wb_databus_read_data[5]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[21]_INST_0_i_4 
       (.I0(Q[2]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[29]),
        .O(wb_databus_read_data[29]));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[21]_INST_0_i_5 
       (.I0(Q[10]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[21]),
        .O(wb_databus_read_data[21]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[22]_INST_0_i_1 
       (.I0(wb_databus_read_data[14]),
        .I1(wb_databus_read_data[6]),
        .I2(wb_databus_read_data[30]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[22]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[22]_INST_0_i_2 
       (.I0(Q[17]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[14]),
        .O(wb_databus_read_data[14]));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[22]_INST_0_i_3 
       (.I0(Q[25]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[6]),
        .O(wb_databus_read_data[6]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[22]_INST_0_i_4 
       (.I0(Q[1]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[30]),
        .O(wb_databus_read_data[30]));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[22]_INST_0_i_5 
       (.I0(Q[9]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[22]),
        .O(wb_databus_read_data[22]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[23]_INST_0_i_1 
       (.I0(wb_databus_read_data[15]),
        .I1(wb_databus_read_data[7]),
        .I2(wb_databus_read_data[31]),
        .I3(wb_read_msb_doublet_sel),
        .I4(\LOCKSTEP_Out_reg[3023] ),
        .I5(wb_databus_read_data[23]),
        .O(\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[23]_INST_0_i_2 
       (.I0(Q[16]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[15]),
        .O(wb_databus_read_data[15]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[23]_INST_0_i_3 
       (.I0(Q[24]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[7]),
        .O(wb_databus_read_data[7]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[23]_INST_0_i_4 
       (.I0(Q[0]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[31]),
        .O(wb_databus_read_data[31]));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \Trace_New_Reg_Value[23]_INST_0_i_5 
       (.I0(Q[8]),
        .I1(wb_dext_Data_Strobe),
        .I2(wb_dext_read_data[23]),
        .O(wb_databus_read_data[23]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[24]_INST_0_i_1 
       (.I0(wb_databus_read_data[8]),
        .I1(wb_databus_read_data[0]),
        .I2(wb_databus_read_data[24]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[16]),
        .O(wb_databus_steered_read_data[7]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[25]_INST_0_i_1 
       (.I0(wb_databus_read_data[9]),
        .I1(wb_databus_read_data[1]),
        .I2(wb_databus_read_data[25]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[17]),
        .O(wb_databus_steered_read_data[6]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[26]_INST_0_i_1 
       (.I0(wb_databus_read_data[10]),
        .I1(wb_databus_read_data[2]),
        .I2(wb_databus_read_data[26]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[18]),
        .O(wb_databus_steered_read_data[5]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[27]_INST_0_i_1 
       (.I0(wb_databus_read_data[11]),
        .I1(wb_databus_read_data[3]),
        .I2(wb_databus_read_data[27]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[19]),
        .O(wb_databus_steered_read_data[4]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[28]_INST_0_i_1 
       (.I0(wb_databus_read_data[12]),
        .I1(wb_databus_read_data[4]),
        .I2(wb_databus_read_data[28]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[20]),
        .O(wb_databus_steered_read_data[3]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[29]_INST_0_i_1 
       (.I0(wb_databus_read_data[13]),
        .I1(wb_databus_read_data[5]),
        .I2(wb_databus_read_data[29]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[21]),
        .O(wb_databus_steered_read_data[2]));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[2]_INST_0_i_1 
       (.I0(Q[5]),
        .I1(wb_dext_read_data[26]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[29]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[2]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[26] ));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[30]_INST_0_i_1 
       (.I0(wb_databus_read_data[14]),
        .I1(wb_databus_read_data[6]),
        .I2(wb_databus_read_data[30]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[22]),
        .O(wb_databus_steered_read_data[1]));
  LUT6 #(
    .INIT(64'hF0FFAACCF000AACC)) 
    \Trace_New_Reg_Value[31]_INST_0_i_1 
       (.I0(wb_databus_read_data[15]),
        .I1(wb_databus_read_data[7]),
        .I2(wb_databus_read_data[31]),
        .I3(\LOCKSTEP_Out_reg[3031] [0]),
        .I4(\LOCKSTEP_Out_reg[3031] [1]),
        .I5(wb_databus_read_data[23]),
        .O(wb_databus_steered_read_data[0]));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[3]_INST_0_i_1 
       (.I0(Q[4]),
        .I1(wb_dext_read_data[27]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[28]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[3]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[27] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[4]_INST_0_i_1 
       (.I0(Q[3]),
        .I1(wb_dext_read_data[28]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[27]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[4]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[28] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[5]_INST_0_i_1 
       (.I0(Q[2]),
        .I1(wb_dext_read_data[29]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[26]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[5]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[29] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[6]_INST_0_i_1 
       (.I0(Q[1]),
        .I1(wb_dext_read_data[30]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[25]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[6]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[30] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[7]_INST_0_i_1 
       (.I0(Q[0]),
        .I1(wb_dext_read_data[31]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[24]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[7]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[31] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[8]_INST_0_i_1 
       (.I0(Q[15]),
        .I1(wb_dext_read_data[16]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[23]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[8]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[16] ));
  LUT6 #(
    .INIT(64'hEFEFAFA0EFE0AFA0)) 
    \Trace_New_Reg_Value[9]_INST_0_i_1 
       (.I0(Q[14]),
        .I1(wb_dext_read_data[17]),
        .I2(wb_read_msb_doublet_sel),
        .I3(Q[22]),
        .I4(wb_dext_Data_Strobe),
        .I5(wb_dext_read_data[9]),
        .O(\Use_DLMB.wb_dlmb_valid_read_data_reg[17] ));
  LUT2 #(
    .INIT(4'hE)) 
    \Using_FPGA.Native_i_2__25 
       (.I0(DReady),
        .I1(MEM_DAXI_Data_Strobe),
        .O(MEM_DataBus_Ready));
  FDRE WB_DAXI_Data_Strobe_reg
       (.C(Clk),
        .CE(1'b1),
        .D(MEM_DAXI_Data_Strobe),
        .Q(wb_dext_Data_Strobe),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[0] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[31]),
        .Q(wb_dext_read_data[0]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[10] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[21]),
        .Q(wb_dext_read_data[10]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[11] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[20]),
        .Q(wb_dext_read_data[11]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[12] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[19]),
        .Q(wb_dext_read_data[12]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[13] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[18]),
        .Q(wb_dext_read_data[13]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[14] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[17]),
        .Q(wb_dext_read_data[14]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[15] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[16]),
        .Q(wb_dext_read_data[15]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[16] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[15]),
        .Q(wb_dext_read_data[16]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[17] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[14]),
        .Q(wb_dext_read_data[17]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[18] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[13]),
        .Q(wb_dext_read_data[18]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[19] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[12]),
        .Q(wb_dext_read_data[19]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[1] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[30]),
        .Q(wb_dext_read_data[1]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[20] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[11]),
        .Q(wb_dext_read_data[20]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[21] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[10]),
        .Q(wb_dext_read_data[21]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[22] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[9]),
        .Q(wb_dext_read_data[22]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[23] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[8]),
        .Q(wb_dext_read_data[23]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[24] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[7]),
        .Q(wb_dext_read_data[24]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[25] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[6]),
        .Q(wb_dext_read_data[25]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[26] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[5]),
        .Q(wb_dext_read_data[26]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[27] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[4]),
        .Q(wb_dext_read_data[27]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[28] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[3]),
        .Q(wb_dext_read_data[28]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[29] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[2]),
        .Q(wb_dext_read_data[29]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[2] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[29]),
        .Q(wb_dext_read_data[2]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[30] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[1]),
        .Q(wb_dext_read_data[30]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[31] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[0]),
        .Q(wb_dext_read_data[31]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[3] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[28]),
        .Q(wb_dext_read_data[3]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[4] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[27]),
        .Q(wb_dext_read_data[4]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[5] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[26]),
        .Q(wb_dext_read_data[5]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[6] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[25]),
        .Q(wb_dext_read_data[6]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[7] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[24]),
        .Q(wb_dext_read_data[7]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[8] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[23]),
        .Q(wb_dext_read_data[8]),
        .R(sync_reset));
  FDRE \WB_DAXI_Read_Data_reg[9] 
       (.C(Clk),
        .CE(M_AXI_DP_RVALID),
        .D(M_AXI_DP_RDATA[22]),
        .Q(wb_dext_read_data[9]),
        .R(sync_reset));
  FDRE active_access_d1_reg
       (.C(Clk),
        .CE(1'b1),
        .D(active_access),
        .Q(active_access_d1),
        .R(sync_reset));
  FDRE active_access_reg
       (.C(Clk),
        .CE(1'b1),
        .D(active_access_reg_0),
        .Q(active_access),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hE0)) 
    mem_access_completed_i_1
       (.I0(M_AXI_DP_RVALID),
        .I1(M_AXI_DP_BVALID),
        .I2(active_access),
        .O(mem_access_completed0));
  FDRE mem_access_completed_reg
       (.C(Clk),
        .CE(1'b1),
        .D(mem_access_completed0),
        .Q(MEM_DAXI_Data_Strobe),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "Data_Flow_Logic" *) 
module design_1_microblaze_0_0_Data_Flow_Logic
   (\Using_FPGA.Native ,
    MEM_Fwd,
    Q,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr,
    SR,
    \WB_MEM_Result_reg[0]_0 ,
    \WB_MEM_Result_reg[0]_1 );
  output [3:0]\Using_FPGA.Native ;
  output [27:0]MEM_Fwd;
  output [31:0]Q;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:31]EX_Fwd;
  input Clk;
  input mem_sel_msr;
  input [0:0]SR;
  input \WB_MEM_Result_reg[0]_0 ;
  input [3:0]\WB_MEM_Result_reg[0]_1 ;

  wire Clk;
  wire [0:31]EX_Fwd;
  wire [27:0]MEM_Fwd;
  wire [31:0]Q;
  wire R;
  wire [0:0]SR;
  wire [3:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire \WB_MEM_Result_reg[0]_0 ;
  wire [3:0]\WB_MEM_Result_reg[0]_1 ;
  wire mem_sel_msr;

  design_1_microblaze_0_0_MB_FDRE_456 \Gen_Bits[0].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[0]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [3]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ));
  design_1_microblaze_0_0_MB_FDRE_457 \Gen_Bits[10].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[10]),
        .MEM_Fwd(MEM_Fwd[18]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_458 \Gen_Bits[11].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[11]),
        .MEM_Fwd(MEM_Fwd[17]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_459 \Gen_Bits[12].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[12]),
        .MEM_Fwd(MEM_Fwd[16]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_460 \Gen_Bits[13].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[13]),
        .MEM_Fwd(MEM_Fwd[15]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_461 \Gen_Bits[14].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[14]),
        .MEM_Fwd(MEM_Fwd[14]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_462 \Gen_Bits[15].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[15]),
        .MEM_Fwd(MEM_Fwd[13]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_463 \Gen_Bits[16].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[16]),
        .MEM_Fwd(MEM_Fwd[12]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_464 \Gen_Bits[17].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[17]),
        .MEM_Fwd(MEM_Fwd[11]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_465 \Gen_Bits[18].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[18]),
        .MEM_Fwd(MEM_Fwd[10]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_466 \Gen_Bits[19].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[19]),
        .MEM_Fwd(MEM_Fwd[9]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_467 \Gen_Bits[1].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[1]),
        .MEM_Fwd(MEM_Fwd[27]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_468 \Gen_Bits[20].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[20]),
        .MEM_Fwd(MEM_Fwd[8]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_469 \Gen_Bits[21].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[21]),
        .MEM_Fwd(MEM_Fwd[7]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_470 \Gen_Bits[22].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[22]),
        .MEM_Fwd(MEM_Fwd[6]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_471 \Gen_Bits[23].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[23]),
        .MEM_Fwd(MEM_Fwd[5]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_472 \Gen_Bits[24].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[24]),
        .MEM_Fwd(MEM_Fwd[4]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_473 \Gen_Bits[25].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[25]),
        .MEM_Fwd(MEM_Fwd[3]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_474 \Gen_Bits[26].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[26]),
        .MEM_Fwd(MEM_Fwd[2]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_475 \Gen_Bits[27].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[27]),
        .MEM_Fwd(MEM_Fwd[1]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_476 \Gen_Bits[28].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[28]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [2]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ));
  design_1_microblaze_0_0_MB_FDRE_477 \Gen_Bits[29].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[29]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [1]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ));
  design_1_microblaze_0_0_MB_FDRE_478 \Gen_Bits[2].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[2]),
        .MEM_Fwd(MEM_Fwd[26]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_479 \Gen_Bits[30].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[30]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [0]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ));
  design_1_microblaze_0_0_MB_FDRE_480 \Gen_Bits[31].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[31]),
        .MEM_Fwd(MEM_Fwd[0]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_481 \Gen_Bits[3].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[3]),
        .MEM_Fwd(MEM_Fwd[25]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_482 \Gen_Bits[4].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[4]),
        .MEM_Fwd(MEM_Fwd[24]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_483 \Gen_Bits[5].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[5]),
        .MEM_Fwd(MEM_Fwd[23]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_484 \Gen_Bits[6].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[6]),
        .MEM_Fwd(MEM_Fwd[22]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_485 \Gen_Bits[7].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[7]),
        .MEM_Fwd(MEM_Fwd[21]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_486 \Gen_Bits[8].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[8]),
        .MEM_Fwd(MEM_Fwd[20]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_MB_FDRE_487 \Gen_Bits[9].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd[9]),
        .MEM_Fwd(MEM_Fwd[19]),
        .R(R),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .mem_sel_msr(mem_sel_msr));
  FDRE \WB_MEM_Result_reg[0] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(\WB_MEM_Result_reg[0]_1 [3]),
        .Q(Q[31]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[10] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[18]),
        .Q(Q[21]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[11] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[17]),
        .Q(Q[20]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[12] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[16]),
        .Q(Q[19]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[13] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[15]),
        .Q(Q[18]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[14] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[14]),
        .Q(Q[17]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[15] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[13]),
        .Q(Q[16]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[16] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[12]),
        .Q(Q[15]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[17] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[11]),
        .Q(Q[14]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[18] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[10]),
        .Q(Q[13]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[19] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[9]),
        .Q(Q[12]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[1] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[27]),
        .Q(Q[30]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[20] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[8]),
        .Q(Q[11]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[21] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[7]),
        .Q(Q[10]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[22] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[6]),
        .Q(Q[9]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[23] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[5]),
        .Q(Q[8]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[24] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[4]),
        .Q(Q[7]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[25] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[3]),
        .Q(Q[6]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[26] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[2]),
        .Q(Q[5]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[27] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[1]),
        .Q(Q[4]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[28] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(\WB_MEM_Result_reg[0]_1 [2]),
        .Q(Q[3]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[29] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(\WB_MEM_Result_reg[0]_1 [1]),
        .Q(Q[2]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[2] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[26]),
        .Q(Q[29]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[30] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(\WB_MEM_Result_reg[0]_1 [0]),
        .Q(Q[1]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[31] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[0]),
        .Q(Q[0]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[3] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[25]),
        .Q(Q[28]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[4] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[24]),
        .Q(Q[27]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[5] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[23]),
        .Q(Q[26]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[6] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[22]),
        .Q(Q[25]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[7] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[21]),
        .Q(Q[24]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[8] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[20]),
        .Q(Q[23]),
        .R(SR));
  FDRE \WB_MEM_Result_reg[9] 
       (.C(Clk),
        .CE(\WB_MEM_Result_reg[0]_0 ),
        .D(MEM_Fwd[19]),
        .Q(Q[22]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "Data_Flow_gti" *) 
module design_1_microblaze_0_0_Data_Flow_gti
   (\EX_Op1_reg[0] ,
    out,
    \EX_Op1_reg[24] ,
    ex_op1_zero,
    ex_MSR,
    DI,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    \Using_FPGA.Native_5 ,
    \Using_FPGA.Native_6 ,
    \Using_FPGA.Native_7 ,
    \Using_FPGA.Native_8 ,
    \Using_FPGA.Native_9 ,
    \Using_FPGA.Native_10 ,
    \Using_FPGA.Native_11 ,
    \Using_FPGA.Native_12 ,
    \Using_FPGA.Native_13 ,
    \Using_FPGA.Native_14 ,
    \Using_FPGA.Native_15 ,
    \Using_FPGA.Native_16 ,
    \Using_FPGA.Native_17 ,
    \Using_FPGA.Native_18 ,
    \Using_FPGA.Native_19 ,
    \Using_FPGA.Native_20 ,
    \Using_FPGA.Native_21 ,
    \Using_FPGA.Native_22 ,
    \Using_FPGA.Native_23 ,
    \Using_FPGA.Native_24 ,
    \Using_FPGA.Native_25 ,
    \Using_FPGA.Native_26 ,
    \Using_FPGA.Native_27 ,
    \Using_FPGA.Native_28 ,
    \EX_Op2_reg[0] ,
    \Using_FPGA.Native_29 ,
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0] ,
    wb_read_msb_doublet_sel,
    \EX_Branch_CMP_Op1_reg[0] ,
    \EX_Op1_reg[28] ,
    wb_gpr_write_dbg_reg,
    \WB_MEM_Result_reg[0] ,
    swap_result,
    swap_result_reg,
    MEM_Fwd,
    \EX_Op3_reg[0] ,
    GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    \imm_reg_reg[0] ,
    \No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0] ,
    ex_databus_addr,
    of_op1_sel_spr,
    D,
    I1,
    \EX_Op1_reg[1] ,
    \EX_Op1_reg[2] ,
    \EX_Op1_reg[3] ,
    \EX_Op1_reg[4] ,
    \EX_Op1_reg[5] ,
    \EX_Op1_reg[6] ,
    \EX_Op1_reg[7] ,
    \EX_Op1_reg[8] ,
    \EX_Op1_reg[9] ,
    \EX_Op1_reg[10] ,
    \EX_Op1_reg[11] ,
    \EX_Op1_reg[12] ,
    \EX_Op1_reg[13] ,
    \EX_Op1_reg[14] ,
    \EX_Op1_reg[15] ,
    \EX_Op1_reg[16] ,
    \EX_Op1_reg[17] ,
    \EX_Op1_reg[18] ,
    \EX_Op1_reg[19] ,
    \EX_Op1_reg[20] ,
    \EX_Op1_reg[21] ,
    \EX_Op1_reg[22] ,
    \EX_Op1_reg[23] ,
    \EX_Op1_reg[24]_0 ,
    \EX_Op1_reg[25] ,
    \EX_Op1_reg[26] ,
    \EX_Op1_reg[27] ,
    \EX_Op1_reg[28]_0 ,
    \EX_Op1_reg[29] ,
    \EX_Op1_reg[30] ,
    \EX_Op1_reg[31] ,
    ex_use_carry,
    DI_0,
    ex_unsigned_op,
    Q,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU,
    in0,
    ex_op1_cmp_equal,
    ex_op1_cmp_equal_n,
    R,
    \Using_FPGA.Native_30 ,
    EX_Fwd,
    Clk,
    sync_reset,
    \Using_FPGA.Native_31 ,
    \Using_FPGA.Native_32 ,
    \Using_FPGA.Native_33 ,
    \Using_FPGA.Native_34 ,
    \Using_FPGA.Native_35 ,
    I1_1,
    ex_reverse_mem_access,
    p_231_in,
    \Using_FPGA.Native_36 ,
    ex_MSR_Load_ALU_C,
    ex_swx_access__0,
    ex_MSR_Load_Shift_C,
    ex_MSR_Load_LWX_SWX_C,
    ex_move_to_MSR_instr,
    \Using_FPGA.Native_37 ,
    \Using_FPGA.Native_38 ,
    ex_valid,
    ex_cmp_op,
    ex_byte_access,
    ex_doublet_access,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[23] ,
    \data_rd_reg_reg[23]_0 ,
    \LOCKSTEP_Out_reg[3030] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3024] ,
    \LOCKSTEP_Out_reg[3026] ,
    \LOCKSTEP_Out_reg[3028] ,
    \LOCKSTEP_Out_reg[3030]_0 ,
    \LOCKSTEP_Out_reg[3029] ,
    \LOCKSTEP_Out_reg[3027] ,
    \LOCKSTEP_Out_reg[3025] ,
    \LOCKSTEP_Out_reg[3023] ,
    \Using_FPGA.Native_i_3__31 ,
    ex_swap_byte_instr,
    mem_sel_msr,
    \EX_Branch_CMP_Op1_reg[18] ,
    \EX_Branch_CMP_Op1_reg[0]_0 ,
    \EX_Branch_CMP_Op1_reg[0]_1 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[18]_0 ,
    \EX_Branch_CMP_Op1_reg[2] ,
    \EX_Branch_CMP_Op1_reg[2]_0 ,
    \EX_Branch_CMP_Op1_reg[4] ,
    \EX_Branch_CMP_Op1_reg[4]_0 ,
    \EX_Branch_CMP_Op1_reg[6] ,
    \EX_Branch_CMP_Op1_reg[6]_0 ,
    \EX_Branch_CMP_Op1_reg[8] ,
    \EX_Branch_CMP_Op1_reg[8]_0 ,
    \EX_Branch_CMP_Op1_reg[10] ,
    \EX_Branch_CMP_Op1_reg[10]_0 ,
    \EX_Branch_CMP_Op1_reg[12] ,
    \EX_Branch_CMP_Op1_reg[12]_0 ,
    \EX_Branch_CMP_Op1_reg[14] ,
    \EX_Branch_CMP_Op1_reg[14]_0 ,
    \EX_Branch_CMP_Op1_reg[24] ,
    \EX_Branch_CMP_Op1_reg[24]_0 ,
    \EX_Branch_CMP_Op1_reg[26] ,
    \EX_Branch_CMP_Op1_reg[26]_0 ,
    \EX_Branch_CMP_Op1_reg[28] ,
    \EX_Branch_CMP_Op1_reg[28]_0 ,
    \EX_Branch_CMP_Op1_reg[30] ,
    \EX_Branch_CMP_Op1_reg[30]_0 ,
    E,
    \EX_Op3_reg[31] ,
    \EX_Op2_reg[0]_0 ,
    \EX_Op3_reg[0]_0 ,
    \MEM_DataBus_Write_Data_reg[0] ,
    SR,
    \wb_MSR_i_reg[30] ,
    mem_byte_access,
    mem_doublet_access,
    lopt,
    lopt_1,
    lopt_2);
  output [31:0]\EX_Op1_reg[0] ;
  output out;
  output \EX_Op1_reg[24] ;
  output ex_op1_zero;
  output [2:0]ex_MSR;
  output DI;
  output \Using_FPGA.Native ;
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  output \Using_FPGA.Native_3 ;
  output \Using_FPGA.Native_4 ;
  output \Using_FPGA.Native_5 ;
  output \Using_FPGA.Native_6 ;
  output \Using_FPGA.Native_7 ;
  output \Using_FPGA.Native_8 ;
  output \Using_FPGA.Native_9 ;
  output \Using_FPGA.Native_10 ;
  output \Using_FPGA.Native_11 ;
  output \Using_FPGA.Native_12 ;
  output \Using_FPGA.Native_13 ;
  output \Using_FPGA.Native_14 ;
  output \Using_FPGA.Native_15 ;
  output \Using_FPGA.Native_16 ;
  output \Using_FPGA.Native_17 ;
  output \Using_FPGA.Native_18 ;
  output \Using_FPGA.Native_19 ;
  output \Using_FPGA.Native_20 ;
  output \Using_FPGA.Native_21 ;
  output \Using_FPGA.Native_22 ;
  output \Using_FPGA.Native_23 ;
  output \Using_FPGA.Native_24 ;
  output \Using_FPGA.Native_25 ;
  output \Using_FPGA.Native_26 ;
  output \Using_FPGA.Native_27 ;
  output \Using_FPGA.Native_28 ;
  output [91:0]\EX_Op2_reg[0] ;
  output [23:0]\Using_FPGA.Native_29 ;
  output \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0] ;
  output wb_read_msb_doublet_sel;
  output [0:0]\EX_Branch_CMP_Op1_reg[0] ;
  output \EX_Op1_reg[28] ;
  output [7:0]wb_gpr_write_dbg_reg;
  output [23:0]\WB_MEM_Result_reg[0] ;
  output [23:0]swap_result;
  output [0:7]swap_result_reg;
  output [0:31]MEM_Fwd;
  output [31:0]\EX_Op3_reg[0] ;
  output [0:31]GPR_Op1;
  output [0:31]GPR_Op2;
  output [0:31]GPR_Op3;
  output [15:0]\imm_reg_reg[0] ;
  output [1:0]\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0] ;
  output [1:0]ex_databus_addr;
  input of_op1_sel_spr;
  input [31:0]D;
  input I1;
  input \EX_Op1_reg[1] ;
  input \EX_Op1_reg[2] ;
  input \EX_Op1_reg[3] ;
  input \EX_Op1_reg[4] ;
  input \EX_Op1_reg[5] ;
  input \EX_Op1_reg[6] ;
  input \EX_Op1_reg[7] ;
  input \EX_Op1_reg[8] ;
  input \EX_Op1_reg[9] ;
  input \EX_Op1_reg[10] ;
  input \EX_Op1_reg[11] ;
  input \EX_Op1_reg[12] ;
  input \EX_Op1_reg[13] ;
  input \EX_Op1_reg[14] ;
  input \EX_Op1_reg[15] ;
  input \EX_Op1_reg[16] ;
  input \EX_Op1_reg[17] ;
  input \EX_Op1_reg[18] ;
  input \EX_Op1_reg[19] ;
  input \EX_Op1_reg[20] ;
  input \EX_Op1_reg[21] ;
  input \EX_Op1_reg[22] ;
  input \EX_Op1_reg[23] ;
  input \EX_Op1_reg[24]_0 ;
  input \EX_Op1_reg[25] ;
  input \EX_Op1_reg[26] ;
  input \EX_Op1_reg[27] ;
  input \EX_Op1_reg[28]_0 ;
  input \EX_Op1_reg[29] ;
  input \EX_Op1_reg[30] ;
  input \EX_Op1_reg[31] ;
  input ex_use_carry;
  input DI_0;
  input ex_unsigned_op;
  input [1:0]Q;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;
  input in0;
  input ex_op1_cmp_equal;
  input ex_op1_cmp_equal_n;
  input R;
  input \Using_FPGA.Native_30 ;
  input [0:31]EX_Fwd;
  input Clk;
  input sync_reset;
  input \Using_FPGA.Native_31 ;
  input [0:0]\Using_FPGA.Native_32 ;
  input [31:0]\Using_FPGA.Native_33 ;
  input \Using_FPGA.Native_34 ;
  input \Using_FPGA.Native_35 ;
  input I1_1;
  input ex_reverse_mem_access;
  input p_231_in;
  input \Using_FPGA.Native_36 ;
  input ex_MSR_Load_ALU_C;
  input ex_swx_access__0;
  input ex_MSR_Load_Shift_C;
  input ex_MSR_Load_LWX_SWX_C;
  input ex_move_to_MSR_instr;
  input \Using_FPGA.Native_37 ;
  input \Using_FPGA.Native_38 ;
  input ex_valid;
  input ex_cmp_op;
  input ex_byte_access;
  input ex_doublet_access;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[23] ;
  input \data_rd_reg_reg[23]_0 ;
  input \LOCKSTEP_Out_reg[3030] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3024] ;
  input \LOCKSTEP_Out_reg[3026] ;
  input \LOCKSTEP_Out_reg[3028] ;
  input \LOCKSTEP_Out_reg[3030]_0 ;
  input \LOCKSTEP_Out_reg[3029] ;
  input \LOCKSTEP_Out_reg[3027] ;
  input \LOCKSTEP_Out_reg[3025] ;
  input \LOCKSTEP_Out_reg[3023] ;
  input [1:0]\Using_FPGA.Native_i_3__31 ;
  input ex_swap_byte_instr;
  input mem_sel_msr;
  input \EX_Branch_CMP_Op1_reg[18] ;
  input \EX_Branch_CMP_Op1_reg[0]_0 ;
  input \EX_Branch_CMP_Op1_reg[0]_1 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [0:15]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[18]_0 ;
  input \EX_Branch_CMP_Op1_reg[2] ;
  input \EX_Branch_CMP_Op1_reg[2]_0 ;
  input \EX_Branch_CMP_Op1_reg[4] ;
  input \EX_Branch_CMP_Op1_reg[4]_0 ;
  input \EX_Branch_CMP_Op1_reg[6] ;
  input \EX_Branch_CMP_Op1_reg[6]_0 ;
  input \EX_Branch_CMP_Op1_reg[8] ;
  input \EX_Branch_CMP_Op1_reg[8]_0 ;
  input \EX_Branch_CMP_Op1_reg[10] ;
  input \EX_Branch_CMP_Op1_reg[10]_0 ;
  input \EX_Branch_CMP_Op1_reg[12] ;
  input \EX_Branch_CMP_Op1_reg[12]_0 ;
  input \EX_Branch_CMP_Op1_reg[14] ;
  input \EX_Branch_CMP_Op1_reg[14]_0 ;
  input \EX_Branch_CMP_Op1_reg[24] ;
  input \EX_Branch_CMP_Op1_reg[24]_0 ;
  input \EX_Branch_CMP_Op1_reg[26] ;
  input \EX_Branch_CMP_Op1_reg[26]_0 ;
  input \EX_Branch_CMP_Op1_reg[28] ;
  input \EX_Branch_CMP_Op1_reg[28]_0 ;
  input \EX_Branch_CMP_Op1_reg[30] ;
  input \EX_Branch_CMP_Op1_reg[30]_0 ;
  input [0:0]E;
  input \EX_Op3_reg[31] ;
  input [31:0]\EX_Op2_reg[0]_0 ;
  input [31:0]\EX_Op3_reg[0]_0 ;
  input [23:0]\MEM_DataBus_Write_Data_reg[0] ;
  input [0:0]SR;
  input [0:0]\wb_MSR_i_reg[30] ;
  input mem_byte_access;
  input mem_doublet_access;
  output lopt;
  input lopt_1;
  input lopt_2;

  wire Clk;
  wire [31:0]D;
  wire DI;
  wire DI_0;
  wire [0:0]E;
  wire EX_ALU_Sel_Logic;
  wire [0:0]\EX_Branch_CMP_Op1_reg[0] ;
  wire \EX_Branch_CMP_Op1_reg[0]_0 ;
  wire \EX_Branch_CMP_Op1_reg[0]_1 ;
  wire \EX_Branch_CMP_Op1_reg[10] ;
  wire \EX_Branch_CMP_Op1_reg[10]_0 ;
  wire \EX_Branch_CMP_Op1_reg[12] ;
  wire \EX_Branch_CMP_Op1_reg[12]_0 ;
  wire \EX_Branch_CMP_Op1_reg[14] ;
  wire \EX_Branch_CMP_Op1_reg[14]_0 ;
  wire \EX_Branch_CMP_Op1_reg[18] ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[18]_0 ;
  wire \EX_Branch_CMP_Op1_reg[24] ;
  wire \EX_Branch_CMP_Op1_reg[24]_0 ;
  wire \EX_Branch_CMP_Op1_reg[26] ;
  wire \EX_Branch_CMP_Op1_reg[26]_0 ;
  wire \EX_Branch_CMP_Op1_reg[28] ;
  wire \EX_Branch_CMP_Op1_reg[28]_0 ;
  wire \EX_Branch_CMP_Op1_reg[2] ;
  wire \EX_Branch_CMP_Op1_reg[2]_0 ;
  wire \EX_Branch_CMP_Op1_reg[30] ;
  wire \EX_Branch_CMP_Op1_reg[30]_0 ;
  wire \EX_Branch_CMP_Op1_reg[4] ;
  wire \EX_Branch_CMP_Op1_reg[4]_0 ;
  wire \EX_Branch_CMP_Op1_reg[6] ;
  wire \EX_Branch_CMP_Op1_reg[6]_0 ;
  wire \EX_Branch_CMP_Op1_reg[8] ;
  wire \EX_Branch_CMP_Op1_reg[8]_0 ;
  wire EX_Enable_ALU;
  wire [0:31]EX_Fwd;
  wire [31:0]\EX_Op1_reg[0] ;
  wire \EX_Op1_reg[10] ;
  wire \EX_Op1_reg[11] ;
  wire \EX_Op1_reg[12] ;
  wire \EX_Op1_reg[13] ;
  wire \EX_Op1_reg[14] ;
  wire \EX_Op1_reg[15] ;
  wire \EX_Op1_reg[16] ;
  wire \EX_Op1_reg[17] ;
  wire \EX_Op1_reg[18] ;
  wire \EX_Op1_reg[19] ;
  wire \EX_Op1_reg[1] ;
  wire \EX_Op1_reg[20] ;
  wire \EX_Op1_reg[21] ;
  wire \EX_Op1_reg[22] ;
  wire \EX_Op1_reg[23] ;
  wire \EX_Op1_reg[24] ;
  wire \EX_Op1_reg[24]_0 ;
  wire \EX_Op1_reg[25] ;
  wire \EX_Op1_reg[26] ;
  wire \EX_Op1_reg[27] ;
  wire \EX_Op1_reg[28] ;
  wire \EX_Op1_reg[28]_0 ;
  wire \EX_Op1_reg[29] ;
  wire \EX_Op1_reg[2] ;
  wire \EX_Op1_reg[30] ;
  wire \EX_Op1_reg[31] ;
  wire \EX_Op1_reg[3] ;
  wire \EX_Op1_reg[4] ;
  wire \EX_Op1_reg[5] ;
  wire \EX_Op1_reg[6] ;
  wire \EX_Op1_reg[7] ;
  wire \EX_Op1_reg[8] ;
  wire \EX_Op1_reg[9] ;
  wire [91:0]\EX_Op2_reg[0] ;
  wire [31:0]\EX_Op2_reg[0]_0 ;
  wire [31:0]\EX_Op3_reg[0] ;
  wire [31:0]\EX_Op3_reg[0]_0 ;
  wire \EX_Op3_reg[31] ;
  wire [0:31]GPR_Op1;
  wire [0:31]GPR_Op2;
  wire [0:31]GPR_Op3;
  wire I1;
  wire I1_1;
  wire \LOCKSTEP_Out_reg[3023] ;
  wire \LOCKSTEP_Out_reg[3024] ;
  wire \LOCKSTEP_Out_reg[3025] ;
  wire \LOCKSTEP_Out_reg[3026] ;
  wire \LOCKSTEP_Out_reg[3027] ;
  wire \LOCKSTEP_Out_reg[3028] ;
  wire \LOCKSTEP_Out_reg[3029] ;
  wire \LOCKSTEP_Out_reg[3030] ;
  wire \LOCKSTEP_Out_reg[3030]_0 ;
  wire [23:0]\MEM_DataBus_Write_Data_reg[0] ;
  wire [0:30]MEM_EX_Result;
  wire [0:31]MEM_Fwd;
  wire \No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0] ;
  wire [1:0]\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0] ;
  wire Operand_Select_I_n_0;
  wire Operand_Select_I_n_150;
  wire Operand_Select_I_n_181;
  wire Operand_Select_I_n_33;
  wire Operand_Select_I_n_64;
  wire Operand_Select_I_n_65;
  wire Operand_Select_I_n_66;
  wire Operand_Select_I_n_67;
  wire Operand_Select_I_n_83;
  wire Operand_Select_I_n_85;
  wire [1:0]Q;
  wire R;
  wire [0:0]SR;
  wire \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I0 ;
  wire \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I2 ;
  wire \Using_FPGA.ALL_Bits[0].ALU_Bit_I1/S ;
  wire \Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_10 ;
  wire \Using_FPGA.Native_11 ;
  wire \Using_FPGA.Native_12 ;
  wire \Using_FPGA.Native_13 ;
  wire \Using_FPGA.Native_14 ;
  wire \Using_FPGA.Native_15 ;
  wire \Using_FPGA.Native_16 ;
  wire \Using_FPGA.Native_17 ;
  wire \Using_FPGA.Native_18 ;
  wire \Using_FPGA.Native_19 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_20 ;
  wire \Using_FPGA.Native_21 ;
  wire \Using_FPGA.Native_22 ;
  wire \Using_FPGA.Native_23 ;
  wire \Using_FPGA.Native_24 ;
  wire \Using_FPGA.Native_25 ;
  wire \Using_FPGA.Native_26 ;
  wire \Using_FPGA.Native_27 ;
  wire \Using_FPGA.Native_28 ;
  wire [23:0]\Using_FPGA.Native_29 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_30 ;
  wire \Using_FPGA.Native_31 ;
  wire [0:0]\Using_FPGA.Native_32 ;
  wire [31:0]\Using_FPGA.Native_33 ;
  wire \Using_FPGA.Native_34 ;
  wire \Using_FPGA.Native_35 ;
  wire \Using_FPGA.Native_36 ;
  wire \Using_FPGA.Native_37 ;
  wire \Using_FPGA.Native_38 ;
  wire \Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_7 ;
  wire \Using_FPGA.Native_8 ;
  wire \Using_FPGA.Native_9 ;
  wire [1:0]\Using_FPGA.Native_i_3__31 ;
  wire [23:0]\WB_MEM_Result_reg[0] ;
  wire \data_rd_reg_reg[23] ;
  wire \data_rd_reg_reg[23]_0 ;
  wire [2:0]ex_MSR;
  wire ex_MSR_Load_ALU_C;
  wire ex_MSR_Load_LWX_SWX_C;
  wire ex_MSR_Load_Shift_C;
  wire ex_alu_carry_32;
  wire ex_alu_carryin;
  wire [1:29]ex_branch_cmp_op1;
  wire ex_byte_access;
  wire ex_cmp_op;
  wire [1:0]ex_databus_addr;
  wire ex_doublet_access;
  wire ex_move_to_MSR_instr;
  wire ex_op1_cmp_equal;
  wire ex_op1_cmp_equal_n;
  wire ex_op1_zero;
  wire [0:27]ex_op2;
  wire ex_pre_alu_carry;
  wire ex_reverse_mem_access;
  wire ex_swap_byte_instr;
  wire ex_swx_access__0;
  wire ex_unsigned_op;
  wire ex_use_carry;
  wire ex_valid;
  wire [15:0]\imm_reg_reg[0] ;
  wire in0;
  wire \^lopt ;
  wire \^lopt_1 ;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire \^lopt_2 ;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire mem_byte_access;
  wire mem_doublet_access;
  wire mem_sel_msr;
  wire muxcy_di;
  wire muxcy_sel;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [0:15]of_imm_data;
  wire of_op1_sel_spr;
  wire out;
  wire p_231_in;
  wire [23:0]swap_result;
  wire [0:7]swap_result_reg;
  wire sync_reset;
  wire [0:0]\wb_MSR_i_reg[30] ;
  wire wb_byte_access;
  wire wb_gpr_wr_dbg;
  wire [7:0]wb_gpr_write_dbg_reg;
  wire [16:23]wb_mem_result;
  wire wb_read_msb_doublet_sel;

  assign lopt = lopt_8;
  assign lopt_10 = lopt_2;
  assign lopt_9 = lopt_1;
  design_1_microblaze_0_0_ALU ALU_I
       (.DI_0(DI_0),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .\EX_Op2_reg[0] (\EX_Op2_reg[0] [91:62]),
        .I0(\Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I0 ),
        .I2(\Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I2 ),
        .LO(ex_alu_carry_32),
        .\MEM_DataBus_Addr_reg[9] (Q),
        .Q({ex_op2[0],ex_op2[1],ex_op2[2],ex_op2[3],ex_op2[4],ex_op2[5],ex_op2[6],ex_op2[7],ex_op2[8],ex_op2[9],ex_op2[10],ex_op2[11],ex_op2[12],ex_op2[13],ex_op2[14],ex_op2[15],ex_op2[16],ex_op2[17],ex_op2[18],ex_op2[19],ex_op2[20],ex_op2[21],ex_op2[22],ex_op2[23],ex_op2[24],ex_op2[25],ex_op2[26],ex_op2[27],Operand_Select_I_n_64,Operand_Select_I_n_65,Operand_Select_I_n_66,Operand_Select_I_n_67}),
        .S(\Using_FPGA.ALL_Bits[0].ALU_Bit_I1/S ),
        .\Using_FPGA.Native (\EX_Op1_reg[0] ),
        .ex_alu_carryin(ex_alu_carryin),
        .ex_databus_addr(ex_databus_addr),
        .ex_unsigned_op(ex_unsigned_op),
        .ex_use_carry(ex_use_carry),
        .lopt(lopt_3),
        .lopt_1(lopt_4),
        .lopt_10(lopt_16),
        .lopt_11(lopt_17),
        .lopt_12(lopt_18),
        .lopt_13(lopt_19),
        .lopt_14(lopt_20),
        .lopt_15(lopt_21),
        .lopt_16(lopt_22),
        .lopt_17(lopt_23),
        .lopt_18(lopt_24),
        .lopt_19(lopt_25),
        .lopt_2(lopt_5),
        .lopt_20(lopt_26),
        .lopt_3(lopt_6),
        .lopt_4(lopt_7),
        .lopt_5(lopt_11),
        .lopt_6(lopt_12),
        .lopt_7(lopt_13),
        .lopt_8(lopt_14),
        .lopt_9(lopt_15));
  design_1_microblaze_0_0_Byte_Doublet_Handle_gti Byte_Doublet_Handle_gti_I
       (.Clk(Clk),
        .D({\MEM_DataBus_Write_Data_reg[0] [23:8],\EX_Op2_reg[0] [59:52],\MEM_DataBus_Write_Data_reg[0] [7:0]}),
        .\MEM_DataBus_Byte_Enable_reg[0]_0 (\EX_Op2_reg[0] [51:48]),
        .\MEM_DataBus_Write_Data_reg[0]_0 (\EX_Op2_reg[0] [47:12]),
        .\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0]_0 (\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0] ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0]_0 (\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0] ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[1]_0 (\Using_FPGA.Native_35 ),
        .ex_reverse_mem_access(ex_reverse_mem_access),
        .mem_byte_access(mem_byte_access),
        .\mem_byte_selects_reg[0]_0 (Operand_Select_I_n_83),
        .\mem_byte_selects_reg[1]_0 (Operand_Select_I_n_181),
        .mem_doublet_access(mem_doublet_access),
        .mem_reverse_byteorder_reg_0(\Using_FPGA.Native_30 ),
        .sync_reset(sync_reset),
        .wb_read_msb_doublet_sel(wb_read_msb_doublet_sel));
  design_1_microblaze_0_0_Data_Flow_Logic Data_Flow_Logic_I
       (.Clk(Clk),
        .EX_Fwd(EX_Fwd),
        .MEM_Fwd({MEM_Fwd[1],MEM_Fwd[2],MEM_Fwd[3],MEM_Fwd[4],MEM_Fwd[5],MEM_Fwd[6],MEM_Fwd[7],MEM_Fwd[8],MEM_Fwd[9],MEM_Fwd[10],MEM_Fwd[11],MEM_Fwd[12],MEM_Fwd[13],MEM_Fwd[14],MEM_Fwd[15],MEM_Fwd[16],MEM_Fwd[17],MEM_Fwd[18],MEM_Fwd[19],MEM_Fwd[20],MEM_Fwd[21],MEM_Fwd[22],MEM_Fwd[23],MEM_Fwd[24],MEM_Fwd[25],MEM_Fwd[26],MEM_Fwd[27],MEM_Fwd[31]}),
        .Q({\WB_MEM_Result_reg[0] [23:8],wb_mem_result[16],wb_mem_result[17],wb_mem_result[18],wb_mem_result[19],wb_mem_result[20],wb_mem_result[21],wb_mem_result[22],wb_mem_result[23],\WB_MEM_Result_reg[0] [7:0]}),
        .R(R),
        .SR(SR),
        .\Using_FPGA.Native ({MEM_EX_Result[0],MEM_EX_Result[28],MEM_EX_Result[29],MEM_EX_Result[30]}),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_30 ),
        .\WB_MEM_Result_reg[0]_0 (\Using_FPGA.Native_35 ),
        .\WB_MEM_Result_reg[0]_1 ({MEM_Fwd[0],MEM_Fwd[28],MEM_Fwd[29],MEM_Fwd[30]}),
        .mem_sel_msr(mem_sel_msr));
  design_1_microblaze_0_0_Operand_Select_gti Operand_Select_I
       (.Clk(Clk),
        .D(D),
        .E(E),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .\EX_Branch_CMP_Op1_reg[0]_0 ({\EX_Branch_CMP_Op1_reg[0] ,ex_branch_cmp_op1[1],ex_branch_cmp_op1[2],ex_branch_cmp_op1[3],ex_branch_cmp_op1[4],ex_branch_cmp_op1[5],ex_branch_cmp_op1[6],ex_branch_cmp_op1[7],ex_branch_cmp_op1[8],ex_branch_cmp_op1[9],ex_branch_cmp_op1[10],ex_branch_cmp_op1[11],ex_branch_cmp_op1[12],ex_branch_cmp_op1[13],ex_branch_cmp_op1[14],ex_branch_cmp_op1[15],ex_branch_cmp_op1[16],ex_branch_cmp_op1[17],ex_branch_cmp_op1[18],ex_branch_cmp_op1[19],ex_branch_cmp_op1[20],ex_branch_cmp_op1[21],ex_branch_cmp_op1[22],ex_branch_cmp_op1[23],ex_branch_cmp_op1[24],ex_branch_cmp_op1[25],ex_branch_cmp_op1[26],ex_branch_cmp_op1[27],ex_branch_cmp_op1[28],ex_branch_cmp_op1[29]}),
        .\EX_Branch_CMP_Op1_reg[30]_0 (Operand_Select_I_n_150),
        .\EX_Op1_reg[10]_0 (\EX_Op1_reg[10] ),
        .\EX_Op1_reg[11]_0 (\EX_Op1_reg[11] ),
        .\EX_Op1_reg[12]_0 (\EX_Op1_reg[12] ),
        .\EX_Op1_reg[13]_0 (\EX_Op1_reg[13] ),
        .\EX_Op1_reg[14]_0 (\EX_Op1_reg[14] ),
        .\EX_Op1_reg[15]_0 (\EX_Op1_reg[15] ),
        .\EX_Op1_reg[16]_0 (\EX_Op1_reg[16] ),
        .\EX_Op1_reg[17]_0 (\EX_Op1_reg[17] ),
        .\EX_Op1_reg[18]_0 (\EX_Op1_reg[18] ),
        .\EX_Op1_reg[19]_0 (\EX_Op1_reg[19] ),
        .\EX_Op1_reg[1]_0 (\EX_Op1_reg[1] ),
        .\EX_Op1_reg[20]_0 (\EX_Op1_reg[20] ),
        .\EX_Op1_reg[21]_0 (\EX_Op1_reg[21] ),
        .\EX_Op1_reg[22]_0 (\EX_Op1_reg[22] ),
        .\EX_Op1_reg[23]_0 (\EX_Op1_reg[23] ),
        .\EX_Op1_reg[24]_0 (\EX_Op1_reg[24]_0 ),
        .\EX_Op1_reg[25]_0 (\EX_Op1_reg[25] ),
        .\EX_Op1_reg[26]_0 (\EX_Op1_reg[26] ),
        .\EX_Op1_reg[27]_0 (\EX_Op1_reg[27] ),
        .\EX_Op1_reg[28]_0 (\EX_Op1_reg[28] ),
        .\EX_Op1_reg[28]_1 (\EX_Op1_reg[28]_0 ),
        .\EX_Op1_reg[29]_0 (\EX_Op1_reg[29] ),
        .\EX_Op1_reg[2]_0 (\EX_Op1_reg[2] ),
        .\EX_Op1_reg[30]_0 (Operand_Select_I_n_33),
        .\EX_Op1_reg[30]_1 (\EX_Op1_reg[30] ),
        .\EX_Op1_reg[31]_0 (\EX_Op1_reg[31] ),
        .\EX_Op1_reg[3]_0 (\EX_Op1_reg[3] ),
        .\EX_Op1_reg[4]_0 (\EX_Op1_reg[4] ),
        .\EX_Op1_reg[5]_0 (\EX_Op1_reg[5] ),
        .\EX_Op1_reg[6]_0 (\EX_Op1_reg[6] ),
        .\EX_Op1_reg[7]_0 (\EX_Op1_reg[7] ),
        .\EX_Op1_reg[8]_0 (\EX_Op1_reg[8] ),
        .\EX_Op1_reg[9]_0 (\EX_Op1_reg[9] ),
        .\EX_Op2_reg[0]_0 ({ex_op2[0],ex_op2[1],ex_op2[2],ex_op2[3],ex_op2[4],ex_op2[5],ex_op2[6],ex_op2[7],ex_op2[8],ex_op2[9],ex_op2[10],ex_op2[11],ex_op2[12],ex_op2[13],ex_op2[14],ex_op2[15],ex_op2[16],ex_op2[17],ex_op2[18],ex_op2[19],ex_op2[20],ex_op2[21],ex_op2[22],ex_op2[23],ex_op2[24],ex_op2[25],ex_op2[26],ex_op2[27],Operand_Select_I_n_64,Operand_Select_I_n_65,Operand_Select_I_n_66,Operand_Select_I_n_67}),
        .\EX_Op2_reg[0]_1 (\EX_Op2_reg[0]_0 ),
        .\EX_Op3_reg[0]_0 (\EX_Op3_reg[0] ),
        .\EX_Op3_reg[0]_1 (\EX_Op3_reg[0]_0 ),
        .\EX_Op3_reg[31]_0 (\EX_Op3_reg[31] ),
        .I0(\Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I0 ),
        .I1(I1),
        .I2(\Using_FPGA.ALL_Bits[0].ALU_Bit_I1/I2 ),
        .LO(ex_alu_carry_32),
        .Q(\EX_Op1_reg[0] ),
        .S(\Using_FPGA.ALL_Bits[0].ALU_Bit_I1/S ),
        .\Using_FPGA.Native (\EX_Op2_reg[0] [61:48]),
        .\Using_FPGA.Native_0 (Operand_Select_I_n_83),
        .\Using_FPGA.Native_1 (Operand_Select_I_n_181),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_36 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_30 ),
        .\Using_FPGA.Native_4 (ex_MSR[1]),
        .\Using_FPGA.Native_5 (\Using_FPGA.Native_37 ),
        .\Using_FPGA.Native_6 (\Using_FPGA.Native_38 ),
        .\Using_FPGA.Native_i_3__31 (\Using_FPGA.Native_i_3__31 ),
        .ex_MSR({ex_MSR[2],ex_MSR[0]}),
        .ex_MSR_Load_ALU_C(ex_MSR_Load_ALU_C),
        .ex_MSR_Load_LWX_SWX_C(ex_MSR_Load_LWX_SWX_C),
        .ex_MSR_Load_Shift_C(ex_MSR_Load_Shift_C),
        .ex_byte_access(ex_byte_access),
        .ex_cmp_op(ex_cmp_op),
        .ex_doublet_access(ex_doublet_access),
        .ex_load_alu_carry_reg(Operand_Select_I_n_0),
        .ex_move_to_MSR_instr(ex_move_to_MSR_instr),
        .ex_reverse_mem_access(ex_reverse_mem_access),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .ex_swx_access__0(ex_swx_access__0),
        .ex_valid(ex_valid),
        .\imm_reg_reg[0]_0 (\imm_reg_reg[0] ),
        .in0(Operand_Select_I_n_85),
        .of_imm_data(of_imm_data),
        .of_op1_sel_spr(of_op1_sel_spr),
        .p_231_in(p_231_in),
        .swap_result(swap_result),
        .swap_result_reg(swap_result_reg),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_Register_File_gti Register_File_I
       (.Clk(Clk),
        .DID({\EX_Branch_CMP_Op1_reg[0]_0 ,\EX_Branch_CMP_Op1_reg[0]_1 }),
        .\EX_Branch_CMP_Op1_reg[10] ({\EX_Branch_CMP_Op1_reg[10] ,\EX_Branch_CMP_Op1_reg[10]_0 }),
        .\EX_Branch_CMP_Op1_reg[12] ({\EX_Branch_CMP_Op1_reg[12] ,\EX_Branch_CMP_Op1_reg[12]_0 }),
        .\EX_Branch_CMP_Op1_reg[14] ({\EX_Branch_CMP_Op1_reg[14] ,\EX_Branch_CMP_Op1_reg[14]_0 }),
        .\EX_Branch_CMP_Op1_reg[16] (\EX_Op2_reg[0] [7:6]),
        .\EX_Branch_CMP_Op1_reg[18] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[18]_0 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .\EX_Branch_CMP_Op1_reg[18]_1 (\EX_Op2_reg[0] [5:4]),
        .\EX_Branch_CMP_Op1_reg[20] (\EX_Op2_reg[0] [3:2]),
        .\EX_Branch_CMP_Op1_reg[22] (\EX_Op2_reg[0] [1:0]),
        .\EX_Branch_CMP_Op1_reg[24] ({\EX_Branch_CMP_Op1_reg[24] ,\EX_Branch_CMP_Op1_reg[24]_0 }),
        .\EX_Branch_CMP_Op1_reg[26] ({\EX_Branch_CMP_Op1_reg[26] ,\EX_Branch_CMP_Op1_reg[26]_0 }),
        .\EX_Branch_CMP_Op1_reg[28] ({\EX_Branch_CMP_Op1_reg[28] ,\EX_Branch_CMP_Op1_reg[28]_0 }),
        .\EX_Branch_CMP_Op1_reg[2] ({\EX_Branch_CMP_Op1_reg[2] ,\EX_Branch_CMP_Op1_reg[2]_0 }),
        .\EX_Branch_CMP_Op1_reg[30] ({\EX_Branch_CMP_Op1_reg[30] ,\EX_Branch_CMP_Op1_reg[30]_0 }),
        .\EX_Branch_CMP_Op1_reg[4] ({\EX_Branch_CMP_Op1_reg[4] ,\EX_Branch_CMP_Op1_reg[4]_0 }),
        .\EX_Branch_CMP_Op1_reg[6] ({\EX_Branch_CMP_Op1_reg[6] ,\EX_Branch_CMP_Op1_reg[6]_0 }),
        .\EX_Branch_CMP_Op1_reg[8] ({\EX_Branch_CMP_Op1_reg[8] ,\EX_Branch_CMP_Op1_reg[8]_0 }),
        .GPR_Op1(GPR_Op1),
        .GPR_Op2(GPR_Op2),
        .GPR_Op3(GPR_Op3),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data({of_imm_data[0],of_imm_data[1],of_imm_data[2],of_imm_data[3],of_imm_data[4]}));
  design_1_microblaze_0_0_Shift_Logic_Module_gti Shift_Logic_Module_I
       (.\EX_Op1_reg[24] (\EX_Op1_reg[24] ),
        .\Using_FPGA.Native (Operand_Select_I_n_85),
        .in0(in0),
        .out(out));
  design_1_microblaze_0_0_MB_MUXCY_299 \Using_DAXI_ALU_Carry.Direct_MUXCY_I 
       (.\Using_FPGA.Native_0 (ex_MSR[1]),
        .ex_pre_alu_carry(ex_pre_alu_carry),
        .lopt(\^lopt ),
        .lopt_1(\^lopt_1 ),
        .lopt_10(lopt_11),
        .lopt_11(lopt_12),
        .lopt_12(lopt_13),
        .lopt_13(lopt_14),
        .lopt_14(lopt_15),
        .lopt_15(lopt_16),
        .lopt_16(lopt_17),
        .lopt_17(lopt_18),
        .lopt_18(lopt_19),
        .lopt_19(lopt_20),
        .lopt_2(\^lopt_2 ),
        .lopt_20(lopt_21),
        .lopt_21(lopt_22),
        .lopt_22(lopt_23),
        .lopt_23(lopt_24),
        .lopt_24(lopt_25),
        .lopt_25(lopt_26),
        .lopt_3(lopt_3),
        .lopt_4(DI_0),
        .lopt_5(ex_use_carry),
        .lopt_6(lopt_4),
        .lopt_7(lopt_5),
        .lopt_8(lopt_6),
        .lopt_9(lopt_7),
        .muxcy_di(muxcy_di),
        .muxcy_sel(muxcy_sel));
  design_1_microblaze_0_0_MB_MUXCY_300 \Using_DAXI_ALU_Carry.Post_MUXCY_I 
       (.ex_alu_carryin(ex_alu_carryin),
        .ex_pre_alu_carry(ex_pre_alu_carry),
        .lopt(\^lopt ),
        .lopt_1(\^lopt_1 ),
        .lopt_2(\^lopt_2 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized1 \Using_DAXI_ALU_Carry.direct_lut_INST 
       (.muxcy_di(muxcy_di),
        .muxcy_sel(muxcy_sel));
  design_1_microblaze_0_0_Zero_Detect_gti Zero_Detect_I
       (.\Using_FPGA.Native (Operand_Select_I_n_150),
        .\Using_FPGA.Native_0 ({\EX_Branch_CMP_Op1_reg[0] ,ex_branch_cmp_op1[1],ex_branch_cmp_op1[2],ex_branch_cmp_op1[3],ex_branch_cmp_op1[4],ex_branch_cmp_op1[5],ex_branch_cmp_op1[6],ex_branch_cmp_op1[7],ex_branch_cmp_op1[8],ex_branch_cmp_op1[9],ex_branch_cmp_op1[10],ex_branch_cmp_op1[11],ex_branch_cmp_op1[12],ex_branch_cmp_op1[13],ex_branch_cmp_op1[14],ex_branch_cmp_op1[15],ex_branch_cmp_op1[16],ex_branch_cmp_op1[17],ex_branch_cmp_op1[18],ex_branch_cmp_op1[19],ex_branch_cmp_op1[20],ex_branch_cmp_op1[21],ex_branch_cmp_op1[22],ex_branch_cmp_op1[23],ex_branch_cmp_op1[24],ex_branch_cmp_op1[25],ex_branch_cmp_op1[26],ex_branch_cmp_op1[27],ex_branch_cmp_op1[28],ex_branch_cmp_op1[29]}),
        .ex_op1_cmp_equal(ex_op1_cmp_equal),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .ex_op1_zero(ex_op1_zero),
        .lopt(lopt_8),
        .lopt_1(lopt_9),
        .lopt_2(lopt_10));
  design_1_microblaze_0_0_exception_registers_gti exception_registers_I1
       (.Clk(Clk),
        .DI(DI),
        .I1_1(I1_1),
        .\LOCKSTEP_Out_reg[3023] (\LOCKSTEP_Out_reg[3023] ),
        .\LOCKSTEP_Out_reg[3024] (\LOCKSTEP_Out_reg[3024] ),
        .\LOCKSTEP_Out_reg[3025] (\LOCKSTEP_Out_reg[3025] ),
        .\LOCKSTEP_Out_reg[3026] (\LOCKSTEP_Out_reg[3026] ),
        .\LOCKSTEP_Out_reg[3027] (\LOCKSTEP_Out_reg[3027] ),
        .\LOCKSTEP_Out_reg[3028] (\LOCKSTEP_Out_reg[3028] ),
        .\LOCKSTEP_Out_reg[3029] (\LOCKSTEP_Out_reg[3029] ),
        .\LOCKSTEP_Out_reg[3030] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3030]_0 (\LOCKSTEP_Out_reg[3030]_0 ),
        .Q({wb_mem_result[16],wb_mem_result[17],wb_mem_result[18],wb_mem_result[19],wb_mem_result[20],wb_mem_result[21],wb_mem_result[22],wb_mem_result[23]}),
        .\Using_FPGA.Native (\Using_FPGA.Native ),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native_10 (\Using_FPGA.Native_10 ),
        .\Using_FPGA.Native_11 (\Using_FPGA.Native_11 ),
        .\Using_FPGA.Native_12 (\Using_FPGA.Native_12 ),
        .\Using_FPGA.Native_13 (\Using_FPGA.Native_13 ),
        .\Using_FPGA.Native_14 (\Using_FPGA.Native_14 ),
        .\Using_FPGA.Native_15 (\Using_FPGA.Native_15 ),
        .\Using_FPGA.Native_16 (\Using_FPGA.Native_16 ),
        .\Using_FPGA.Native_17 (\Using_FPGA.Native_17 ),
        .\Using_FPGA.Native_18 (\Using_FPGA.Native_18 ),
        .\Using_FPGA.Native_19 (\Using_FPGA.Native_19 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_2 ),
        .\Using_FPGA.Native_20 (\Using_FPGA.Native_20 ),
        .\Using_FPGA.Native_21 (\Using_FPGA.Native_21 ),
        .\Using_FPGA.Native_22 (\Using_FPGA.Native_22 ),
        .\Using_FPGA.Native_23 (\Using_FPGA.Native_23 ),
        .\Using_FPGA.Native_24 (\Using_FPGA.Native_24 ),
        .\Using_FPGA.Native_25 (\Using_FPGA.Native_25 ),
        .\Using_FPGA.Native_26 (\Using_FPGA.Native_26 ),
        .\Using_FPGA.Native_27 (\Using_FPGA.Native_27 ),
        .\Using_FPGA.Native_28 (\Using_FPGA.Native_28 ),
        .\Using_FPGA.Native_29 ({\EX_Op2_reg[0] [11],\EX_Op2_reg[0] [7:0]}),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_3 ),
        .\Using_FPGA.Native_30 (\Using_FPGA.Native_29 ),
        .\Using_FPGA.Native_31 (\Using_FPGA.Native_32 ),
        .\Using_FPGA.Native_32 (\Using_FPGA.Native_33 ),
        .\Using_FPGA.Native_33 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_34 (\Using_FPGA.Native_35 ),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_4 ),
        .\Using_FPGA.Native_5 (\Using_FPGA.Native_5 ),
        .\Using_FPGA.Native_6 (\Using_FPGA.Native_6 ),
        .\Using_FPGA.Native_7 (\Using_FPGA.Native_7 ),
        .\Using_FPGA.Native_8 (\Using_FPGA.Native_8 ),
        .\Using_FPGA.Native_9 (\Using_FPGA.Native_9 ),
        .\data_rd_reg_reg[23] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[23]_0 (\data_rd_reg_reg[23]_0 ),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg));
  design_1_microblaze_0_0_msr_reg_gti msr_reg_i
       (.Clk(Clk),
        .MEM_Fwd({MEM_Fwd[0],MEM_Fwd[28],MEM_Fwd[29],MEM_Fwd[30]}),
        .\Using_FPGA.Native (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_0 (Operand_Select_I_n_0),
        .\Using_FPGA.Native_1 (Operand_Select_I_n_33),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_35 ),
        .\WB_MEM_Result_reg[0] ({MEM_EX_Result[0],MEM_EX_Result[28],MEM_EX_Result[29],MEM_EX_Result[30]}),
        .ex_MSR(ex_MSR),
        .mem_sel_msr(mem_sel_msr),
        .sync_reset(sync_reset),
        .\wb_MSR_i_reg[28]_0 (\EX_Op2_reg[0] [10:8]),
        .\wb_MSR_i_reg[30]_0 (\wb_MSR_i_reg[30] ));
endmodule

(* ORIG_REF_NAME = "Debug" *) 
module design_1_microblaze_0_0_Debug
   (LOCKSTEP_Master_Out,
    \Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ,
    read_register_MSR_1_reg_0,
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ,
    Sleep_Out,
    dbg_halt_reset_mode_reg_0,
    \Performance_Debug_Control.dbg_state_nohalt_reg_0 ,
    \Performance_Debug_Control.dbg_freeze_nohalt_reg_0 ,
    exception_reg_0,
    Dbg_Trig_In,
    Dbg_Trig_Ack_Out,
    \Performance_Debug_Control.dbg_stop_if_delay_i_reg_0 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ,
    ex_MSR_Load_Shift_C,
    ex_MSR_Load_ALU_C,
    ex_MSR_Set_SW_BIP,
    p_231_in,
    ex_Exception_Taken,
    ex_exception_no_load_store_mask,
    \Performance_Debug_Control.dbg_stop_if_delay_i_reg_1 ,
    Q,
    Dbg_Reg_En_0_sp_1,
    Dbg_TDO,
    Dbg_Clk,
    sync_reset,
    \Performance_Debug_Control.wb_dbg_hit_reg[0]_0 ,
    \Performance_Debug_Control.m0_dbg_hit_reg[0]_0 ,
    single_Step_N_reg_0,
    Dbg_Trig_Ack_In,
    Clk,
    Dbg_Trig_Out,
    Pause,
    Sleep,
    \Performance_Debug_Control.ex_brki_hit_reg_0 ,
    wb_Halted,
    Dbg_Update,
    wb_read_imm_reg_1,
    D,
    wb_read_imm_reg,
    Dbg_Stop,
    Dbg_Capture,
    dbg_stop_i,
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1 ,
    exception_reg_1,
    executing_reg_0,
    ex_valid,
    ex_is_load_instr_s,
    ex_load_shift_carry,
    \Using_FPGA.Native_i_2__21 ,
    \Using_LWX_SWX_instr.ex_reservation_i_3 ,
    p_4_out__0,
    Reset_Mode,
    wb_pc_valid,
    Data_Read_Reg_En,
    Config_Reg_En,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ,
    Dbg_Shift,
    Dbg_Reg_En,
    wb_gpr_wr_dbg,
    Status_Reg_En,
    wakeup_i,
    of_pause,
    mem_Exception_Taken,
    Scan_Reset_Sel,
    Sleep_Decode,
    Scan_Reset,
    Scan_En,
    dbg_clean_stop,
    Dbg_TDI,
    Address,
    \data_rd_reg_reg[0]_0 ,
    \Serial_Dbg_Intf.status_reg_reg[22]_0 );
  output [37:0]LOCKSTEP_Master_Out;
  output \Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ;
  output read_register_MSR_1_reg_0;
  output \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ;
  output Sleep_Out;
  output dbg_halt_reset_mode_reg_0;
  output \Performance_Debug_Control.dbg_state_nohalt_reg_0 ;
  output \Performance_Debug_Control.dbg_freeze_nohalt_reg_0 ;
  output [0:0]exception_reg_0;
  output [1:0]Dbg_Trig_In;
  output [1:0]Dbg_Trig_Ack_Out;
  output \Performance_Debug_Control.dbg_stop_if_delay_i_reg_0 ;
  output [0:0]\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ;
  output ex_MSR_Load_Shift_C;
  output ex_MSR_Load_ALU_C;
  output ex_MSR_Set_SW_BIP;
  output p_231_in;
  output ex_Exception_Taken;
  output ex_exception_no_load_store_mask;
  output \Performance_Debug_Control.dbg_stop_if_delay_i_reg_1 ;
  output [0:0]Q;
  output Dbg_Reg_En_0_sp_1;
  output Dbg_TDO;
  input Dbg_Clk;
  input sync_reset;
  input \Performance_Debug_Control.wb_dbg_hit_reg[0]_0 ;
  input \Performance_Debug_Control.m0_dbg_hit_reg[0]_0 ;
  input single_Step_N_reg_0;
  input [1:0]Dbg_Trig_Ack_In;
  input Clk;
  input [1:0]Dbg_Trig_Out;
  input Pause;
  input Sleep;
  input \Performance_Debug_Control.ex_brki_hit_reg_0 ;
  input wb_Halted;
  input Dbg_Update;
  input wb_read_imm_reg_1;
  input [2:0]D;
  input wb_read_imm_reg;
  input Dbg_Stop;
  input Dbg_Capture;
  input dbg_stop_i;
  input \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1 ;
  input exception_reg_1;
  input executing_reg_0;
  input ex_valid;
  input ex_is_load_instr_s;
  input ex_load_shift_carry;
  input \Using_FPGA.Native_i_2__21 ;
  input \Using_LWX_SWX_instr.ex_reservation_i_3 ;
  input p_4_out__0;
  input [0:1]Reset_Mode;
  input wb_pc_valid;
  input Data_Read_Reg_En;
  input Config_Reg_En;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ;
  input Dbg_Shift;
  input [0:7]Dbg_Reg_En;
  input wb_gpr_wr_dbg;
  input Status_Reg_En;
  input [0:1]wakeup_i;
  input of_pause;
  input mem_Exception_Taken;
  input Scan_Reset_Sel;
  input Sleep_Decode;
  input Scan_Reset;
  input Scan_En;
  input dbg_clean_stop;
  input Dbg_TDI;
  input [0:31]Address;
  input [31:0]\data_rd_reg_reg[0]_0 ;
  input [0:0]\Serial_Dbg_Intf.status_reg_reg[22]_0 ;

  wire A1;
  wire A2;
  wire A3;
  wire [0:31]Address;
  wire Clk;
  wire Command_Reg_En;
  wire Config_Reg_En;
  wire Control_Reg_En;
  wire [2:0]D;
  wire Data_Read_Reg_En;
  wire Dbg_Capture;
  wire Dbg_Clk;
  wire [0:7]Dbg_Reg_En;
  wire Dbg_Reg_En_0_sn_1;
  wire Dbg_Shift;
  wire Dbg_Stop;
  wire Dbg_TDI;
  wire Dbg_TDO;
  wire Dbg_TDO_INST_0_i_10_n_0;
  wire Dbg_TDO_INST_0_i_16_n_0;
  wire Dbg_TDO_INST_0_i_17_n_0;
  wire Dbg_TDO_INST_0_i_18_n_0;
  wire Dbg_TDO_INST_0_i_19_n_0;
  wire Dbg_TDO_INST_0_i_20_n_0;
  wire Dbg_TDO_INST_0_i_21_n_0;
  wire Dbg_TDO_INST_0_i_22_n_0;
  wire Dbg_TDO_INST_0_i_27_n_0;
  wire Dbg_TDO_INST_0_i_28_n_0;
  wire Dbg_TDO_INST_0_i_29_n_0;
  wire Dbg_TDO_INST_0_i_30_n_0;
  wire Dbg_TDO_INST_0_i_31_n_0;
  wire Dbg_TDO_INST_0_i_32_n_0;
  wire Dbg_TDO_INST_0_i_33_n_0;
  wire Dbg_TDO_INST_0_i_34_n_0;
  wire Dbg_TDO_INST_0_i_35_n_0;
  wire Dbg_TDO_INST_0_i_36_n_0;
  wire Dbg_TDO_INST_0_i_7_n_0;
  wire Dbg_TDO_INST_0_i_8_n_0;
  wire Dbg_TDO_INST_0_i_9_n_0;
  wire [1:0]Dbg_Trig_Ack_In;
  wire [1:0]Dbg_Trig_Ack_Out;
  wire [1:0]Dbg_Trig_In;
  wire [1:0]Dbg_Trig_Out;
  wire Dbg_Update;
  wire Full_32_bit;
  wire Full_32_bit_1;
  wire Instr_Insert_Reg_En;
  wire Instr_Insert_Reg_En_1;
  wire [37:0]LOCKSTEP_Master_Out;
  wire New_Dbg_Instr_TCK;
  wire Pause;
  wire \Performance_Debug_Control.dbg_freeze_nohalt_i_1_n_0 ;
  wire \Performance_Debug_Control.dbg_freeze_nohalt_i_3_n_0 ;
  wire \Performance_Debug_Control.dbg_freeze_nohalt_reg_0 ;
  wire \Performance_Debug_Control.dbg_state_nohalt_i_1_n_0 ;
  wire \Performance_Debug_Control.dbg_state_nohalt_i_3_n_0 ;
  wire \Performance_Debug_Control.dbg_state_nohalt_i_4_n_0 ;
  wire \Performance_Debug_Control.dbg_state_nohalt_reg_0 ;
  wire \Performance_Debug_Control.dbg_stop_i_reg_n_0 ;
  wire \Performance_Debug_Control.dbg_stop_if_delay_i_i_1_n_0 ;
  wire \Performance_Debug_Control.dbg_stop_if_delay_i_reg_0 ;
  wire \Performance_Debug_Control.dbg_stop_if_delay_i_reg_1 ;
  wire \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1_n_0 ;
  wire \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2_n_0 ;
  wire \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ;
  wire \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_4_n_0 ;
  wire [0:0]\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_n_0 ;
  wire \Performance_Debug_Control.force_stop_i_i_1_n_0 ;
  wire \Performance_Debug_Control.m0_dbg_hit[0]_i_1_n_0 ;
  wire \Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0] ;
  wire \Performance_Debug_Control.normal_stop_i_i_1_n_0 ;
  wire \Performance_Debug_Control.step_continue_hold_i_1_n_0 ;
  wire \Performance_Debug_Control.step_continue_hold_reg_n_0 ;
  wire [0:0]Q;
  wire Q0_out;
  wire Q11_in;
  wire Q2_in;
  wire Q2_out;
  wire Q3_in;
  wire Q3_out;
  wire Q4_out;
  wire Q6_out;
  wire Q_0;
  wire [0:1]Reset_Mode;
  wire Scan_En;
  wire Scan_Reset;
  wire Scan_Reset_Sel;
  wire \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ;
  wire \Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector_n_0 ;
  wire \Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I_n_0 ;
  wire \Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I_n_0 ;
  wire \Serial_Dbg_Intf.command_reg[0]_i_2_n_0 ;
  wire \Serial_Dbg_Intf.continue_from_brk_TClk_i_1_n_0 ;
  wire \Serial_Dbg_Intf.continue_from_brk_reg_n_0 ;
  wire \Serial_Dbg_Intf.control_reg_reg_n_0_[0] ;
  wire \Serial_Dbg_Intf.control_reg_reg_n_0_[3] ;
  wire \Serial_Dbg_Intf.control_reg_reg_n_0_[4] ;
  wire \Serial_Dbg_Intf.control_reg_reg_n_0_[5] ;
  wire \Serial_Dbg_Intf.dbg_wakeup_i_i_2_n_0 ;
  wire \Serial_Dbg_Intf.force_stop_TClk_i_1_n_0 ;
  wire \Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ;
  wire \Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0 ;
  wire \Serial_Dbg_Intf.normal_stop_TClk_i_1_n_0 ;
  wire \Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0 ;
  wire \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[0] ;
  wire \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[1] ;
  wire \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[2] ;
  wire \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[3] ;
  wire \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[4] ;
  wire \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[6] ;
  wire \Serial_Dbg_Intf.sample_synced_1_reg_n_0_[8] ;
  wire \Serial_Dbg_Intf.shift_count[0]_i_1_n_0 ;
  wire \Serial_Dbg_Intf.shift_count[5]_i_2_n_0 ;
  wire \Serial_Dbg_Intf.shift_count[7]_i_2_n_0 ;
  wire \Serial_Dbg_Intf.shift_count_reg_n_0_[0] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[10] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[11] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[12] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[13] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[14] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[15] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[16] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[17] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[18] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[19] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[1] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[20] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[21] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[22] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[23] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[24] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[25] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[26] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[27] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[28] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[29] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[2] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[30] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[31] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[3] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[4] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[5] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[6] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[7] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[8] ;
  wire \Serial_Dbg_Intf.shift_datain_reg_n_0_[9] ;
  wire \Serial_Dbg_Intf.single_Step_TClk_i_1_n_0 ;
  wire [0:0]\Serial_Dbg_Intf.status_reg_reg[22]_0 ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[0] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[16] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[17] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[18] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[19] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[20] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[22] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[23] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[24] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[25] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[27] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[28] ;
  wire \Serial_Dbg_Intf.status_reg_reg_n_0_[29] ;
  wire \Serial_Dbg_Intf.sync_dbg_wakeup_n_0 ;
  wire \Serial_Dbg_Intf.sync_pause_n_1 ;
  wire \Serial_Dbg_Intf.sync_sample_n_10 ;
  wire \Serial_Dbg_Intf.sync_sample_n_12 ;
  wire \Serial_Dbg_Intf.sync_stop_CPU_n_0 ;
  wire \Serial_Dbg_Intf.unchanged_i_1_n_0 ;
  wire Sleep;
  wire Sleep_Decode;
  wire Sleep_Out;
  wire Status_Reg_En;
  wire TDO_Data_Reg__31;
  wire TDO_Instr_Reg__0;
  wire TDO_Status_Reg__17;
  wire \Using_FPGA.Native_i_2__21 ;
  wire \Using_LWX_SWX_instr.ex_reservation_i_3 ;
  wire \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_0 ;
  wire \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_1 ;
  wire \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_2 ;
  wire capture_1;
  wire command_reg_clear;
  wire command_reg_clear_i_1_n_0;
  wire \data_rd_reg[0]_i_1_n_0 ;
  wire \data_rd_reg[32]_i_1_n_0 ;
  wire \data_rd_reg[32]_i_2_n_0 ;
  wire \data_rd_reg[32]_i_3_n_0 ;
  wire [31:0]\data_rd_reg_reg[0]_0 ;
  wire \data_rd_reg_reg_n_0_[0] ;
  wire \data_rd_reg_reg_n_0_[10] ;
  wire \data_rd_reg_reg_n_0_[11] ;
  wire \data_rd_reg_reg_n_0_[12] ;
  wire \data_rd_reg_reg_n_0_[13] ;
  wire \data_rd_reg_reg_n_0_[14] ;
  wire \data_rd_reg_reg_n_0_[15] ;
  wire \data_rd_reg_reg_n_0_[16] ;
  wire \data_rd_reg_reg_n_0_[17] ;
  wire \data_rd_reg_reg_n_0_[18] ;
  wire \data_rd_reg_reg_n_0_[19] ;
  wire \data_rd_reg_reg_n_0_[1] ;
  wire \data_rd_reg_reg_n_0_[20] ;
  wire \data_rd_reg_reg_n_0_[21] ;
  wire \data_rd_reg_reg_n_0_[22] ;
  wire \data_rd_reg_reg_n_0_[23] ;
  wire \data_rd_reg_reg_n_0_[24] ;
  wire \data_rd_reg_reg_n_0_[25] ;
  wire \data_rd_reg_reg_n_0_[26] ;
  wire \data_rd_reg_reg_n_0_[27] ;
  wire \data_rd_reg_reg_n_0_[28] ;
  wire \data_rd_reg_reg_n_0_[29] ;
  wire \data_rd_reg_reg_n_0_[2] ;
  wire \data_rd_reg_reg_n_0_[30] ;
  wire \data_rd_reg_reg_n_0_[31] ;
  wire \data_rd_reg_reg_n_0_[32] ;
  wire \data_rd_reg_reg_n_0_[3] ;
  wire \data_rd_reg_reg_n_0_[4] ;
  wire \data_rd_reg_reg_n_0_[5] ;
  wire \data_rd_reg_reg_n_0_[6] ;
  wire \data_rd_reg_reg_n_0_[7] ;
  wire \data_rd_reg_reg_n_0_[8] ;
  wire \data_rd_reg_reg_n_0_[9] ;
  wire [0:32]data_read_reg;
  wire dbg_brki_hit;
  wire dbg_brki_hit_synced;
  wire dbg_clean_stop;
  wire dbg_continue_i_i_2_n_0;
  wire dbg_freeze_nohalt0_in;
  wire dbg_halt_reset_mode_i_1_n_0;
  wire dbg_halt_reset_mode_reg_0;
  wire [0:0]dbg_hit;
  wire dbg_stop_1;
  wire dbg_stop_i;
  wire delay_slot_instr;
  wire ex_Exception_Taken;
  wire ex_MSR_Load_ALU_C;
  wire ex_MSR_Load_Shift_C;
  wire ex_MSR_Set_SW_BIP;
  wire ex_brki_hit;
  wire ex_exception_no_load_store_mask;
  wire ex_is_load_instr_s;
  wire ex_load_shift_carry;
  wire ex_pc_brk;
  (* DIRECT_ENABLE *) wire ex_piperun_for_ce;
  wire ex_step_continue_hold;
  wire ex_valid;
  wire exception_i_1_n_0;
  wire [0:0]exception_reg_0;
  wire exception_reg_1;
  wire executing_i_1_n_0;
  wire executing_reg_0;
  wire force_stop_cmd_1;
  wire force_stop_i;
  wire force_stop_overrun;
  wire [0:0]instr_rd_reg;
  wire [0:1]instr_read_reg;
  wire m0_brki_hit;
  (* DIRECT_ENABLE *) wire m3_piperun_for_ce;
  wire mb_halted_1;
  wire mem_Exception_Taken;
  wire normal_stop_cmd_1;
  wire normal_stop_i;
  wire of_pause;
  (* DIRECT_ENABLE *) wire of_piperun_for_ce;
  wire [7:1]p_0_in;
  wire p_0_in71_in;
  wire p_0_in_1;
  wire p_11_out;
  wire [1:1]p_1_out;
  wire [1:1]p_1_out__0;
  wire [1:1]p_1_out__1;
  wire [1:1]p_1_out__2;
  wire [1:1]p_1_out__3;
  wire [1:1]p_1_out__4;
  wire [1:1]p_1_out__5;
  wire p_231_in;
  wire p_37_out__0;
  wire p_4_out__0;
  wire p_56_out;
  wire p_76_out;
  wire p_83_out;
  wire p_86_out;
  wire p_88_out;
  wire p_91_out;
  wire p_94_out;
  wire p_95_in;
  wire p_97_out;
  wire pause_synced;
  wire read_register_MSR;
  wire read_register_MSR_1_reg_0;
  wire read_register_PC;
  wire read_register_PC_1_reg_n_0;
  (* DIRECT_RESET *) wire reset_bool_for_rst;
  wire running_clock;
  wire running_clock_i_1_n_0;
  wire running_clock_synced;
  wire [0:9]sample_synced;
  wire saved_reset_mode_dbg_halt;
  wire saved_reset_mode_dbg_halt_i_1_n_0;
  wire saved_reset_mode_sleep;
  wire saved_reset_mode_sleep_i_1_n_0;
  wire [0:0]sel0;
  wire [3:1]sel0__0;
  wire single_Step_N;
  wire single_Step_N_i_1_n_0;
  wire [0:1]single_step_count;
  wire \single_step_count[0]_i_1_n_0 ;
  wire \single_step_count[0]_i_2_n_0 ;
  wire \single_step_count[1]_i_1_n_0 ;
  wire sleep_reset_mode;
  wire sleep_reset_mode_i_1_n_0;
  wire sleep_synced;
  wire start_dbg_exec_reg_n_0;
  wire start_single_cmd;
  wire start_single_step_i_1_n_0;
  wire start_single_step_reg_n_0;
  wire step_continue__0;
  wire sync;
  wire sync_trig_ack_in_0_n_1;
  wire sync_trig_out_0_n_1;
  wire sync_trig_out_0_n_2;
  wire tdo_config_word1_0;
  wire trig_ack_in_0_synced;
  wire trig_ack_in_0_synced_1;
  wire trig_out_0_synced;
  wire trig_out_0_synced_1;
  wire unchanged;
  wire [0:1]wakeup_i;
  wire wb_Halted;
  wire wb_brki_hit;
  wire wb_dbg_hit;
  wire wb_gpr_wr_dbg;
  wire wb_pc_valid;
  wire wb_read_imm_reg;
  wire wb_read_imm_reg_1;

  assign Dbg_Reg_En_0_sp_1 = Dbg_Reg_En_0_sn_1;
  assign ex_piperun_for_ce = \Performance_Debug_Control.m0_dbg_hit_reg[0]_0 ;
  assign m3_piperun_for_ce = \Performance_Debug_Control.wb_dbg_hit_reg[0]_0 ;
  assign of_piperun_for_ce = single_Step_N_reg_0;
  assign reset_bool_for_rst = sync_reset;
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT5 #(
    .INIT(32'h20000002)) 
    Dbg_TDO_INST_0_i_10
       (.I0(\Serial_Dbg_Intf.status_reg_reg_n_0_[0] ),
        .I1(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I2(A3),
        .I3(A1),
        .I4(A2),
        .O(Dbg_TDO_INST_0_i_10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    Dbg_TDO_INST_0_i_15
       (.I0(instr_read_reg[1]),
        .I1(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I2(instr_read_reg[0]),
        .O(TDO_Instr_Reg__0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    Dbg_TDO_INST_0_i_16
       (.I0(Dbg_TDO_INST_0_i_27_n_0),
        .I1(Dbg_TDO_INST_0_i_28_n_0),
        .I2(Dbg_TDO_INST_0_i_29_n_0),
        .I3(Dbg_TDO_INST_0_i_30_n_0),
        .I4(Dbg_TDO_INST_0_i_31_n_0),
        .I5(Dbg_TDO_INST_0_i_32_n_0),
        .O(Dbg_TDO_INST_0_i_16_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    Dbg_TDO_INST_0_i_17
       (.I0(Dbg_TDO_INST_0_i_33_n_0),
        .I1(Dbg_TDO_INST_0_i_34_n_0),
        .I2(Dbg_TDO_INST_0_i_29_n_0),
        .I3(Dbg_TDO_INST_0_i_35_n_0),
        .I4(Dbg_TDO_INST_0_i_31_n_0),
        .I5(Dbg_TDO_INST_0_i_36_n_0),
        .O(Dbg_TDO_INST_0_i_17_n_0));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    Dbg_TDO_INST_0_i_18
       (.I0(A2),
        .I1(A1),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A3),
        .O(Dbg_TDO_INST_0_i_18_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    Dbg_TDO_INST_0_i_19
       (.I0(A1),
        .I1(A2),
        .O(Dbg_TDO_INST_0_i_19_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    Dbg_TDO_INST_0_i_20
       (.I0(\Serial_Dbg_Intf.status_reg_reg_n_0_[23] ),
        .I1(\Serial_Dbg_Intf.status_reg_reg_n_0_[22] ),
        .I2(A1),
        .I3(\Serial_Dbg_Intf.status_reg_reg_n_0_[25] ),
        .I4(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I5(\Serial_Dbg_Intf.status_reg_reg_n_0_[24] ),
        .O(Dbg_TDO_INST_0_i_20_n_0));
  LUT5 #(
    .INIT(32'hB833B800)) 
    Dbg_TDO_INST_0_i_21
       (.I0(\Serial_Dbg_Intf.status_reg_reg_n_0_[27] ),
        .I1(A1),
        .I2(\Serial_Dbg_Intf.status_reg_reg_n_0_[29] ),
        .I3(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I4(\Serial_Dbg_Intf.status_reg_reg_n_0_[28] ),
        .O(Dbg_TDO_INST_0_i_21_n_0));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    Dbg_TDO_INST_0_i_22
       (.I0(\Serial_Dbg_Intf.status_reg_reg_n_0_[19] ),
        .I1(\Serial_Dbg_Intf.status_reg_reg_n_0_[18] ),
        .I2(A1),
        .I3(\Serial_Dbg_Intf.status_reg_reg_n_0_[20] ),
        .I4(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .O(Dbg_TDO_INST_0_i_22_n_0));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_27
       (.I0(data_read_reg[1]),
        .I1(data_read_reg[2]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[3]),
        .I5(data_read_reg[4]),
        .O(Dbg_TDO_INST_0_i_27_n_0));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_28
       (.I0(data_read_reg[5]),
        .I1(data_read_reg[6]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[7]),
        .I5(data_read_reg[8]),
        .O(Dbg_TDO_INST_0_i_28_n_0));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT4 #(
    .INIT(16'h01FE)) 
    Dbg_TDO_INST_0_i_29
       (.I0(A2),
        .I1(A1),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A3),
        .O(Dbg_TDO_INST_0_i_29_n_0));
  LUT6 #(
    .INIT(64'hACFAFFCFAC0A00C0)) 
    Dbg_TDO_INST_0_i_3
       (.I0(Dbg_TDO_INST_0_i_7_n_0),
        .I1(Dbg_TDO_INST_0_i_8_n_0),
        .I2(A3),
        .I3(Dbg_TDO_INST_0_i_9_n_0),
        .I4(sel0),
        .I5(Dbg_TDO_INST_0_i_10_n_0),
        .O(TDO_Status_Reg__17));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_30
       (.I0(data_read_reg[9]),
        .I1(data_read_reg[10]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[11]),
        .I5(data_read_reg[12]),
        .O(Dbg_TDO_INST_0_i_30_n_0));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT3 #(
    .INIT(8'h1E)) 
    Dbg_TDO_INST_0_i_31
       (.I0(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I1(A1),
        .I2(A2),
        .O(Dbg_TDO_INST_0_i_31_n_0));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_32
       (.I0(data_read_reg[13]),
        .I1(data_read_reg[14]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[15]),
        .I5(data_read_reg[16]),
        .O(Dbg_TDO_INST_0_i_32_n_0));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_33
       (.I0(data_read_reg[17]),
        .I1(data_read_reg[18]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[19]),
        .I5(data_read_reg[20]),
        .O(Dbg_TDO_INST_0_i_33_n_0));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_34
       (.I0(data_read_reg[21]),
        .I1(data_read_reg[22]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[23]),
        .I5(data_read_reg[24]),
        .O(Dbg_TDO_INST_0_i_34_n_0));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_35
       (.I0(data_read_reg[25]),
        .I1(data_read_reg[26]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[27]),
        .I5(data_read_reg[28]),
        .O(Dbg_TDO_INST_0_i_35_n_0));
  LUT6 #(
    .INIT(64'hFCAF0CAFFCA00CA0)) 
    Dbg_TDO_INST_0_i_36
       (.I0(data_read_reg[29]),
        .I1(data_read_reg[30]),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(data_read_reg[31]),
        .I5(data_read_reg[32]),
        .O(Dbg_TDO_INST_0_i_36_n_0));
  LUT6 #(
    .INIT(64'hFCFFAFCA0C00A0CA)) 
    Dbg_TDO_INST_0_i_6
       (.I0(Dbg_TDO_INST_0_i_16_n_0),
        .I1(Dbg_TDO_INST_0_i_17_n_0),
        .I2(sel0),
        .I3(Dbg_TDO_INST_0_i_18_n_0),
        .I4(sel0__0[1]),
        .I5(data_read_reg[0]),
        .O(TDO_Data_Reg__31));
  MUXF7 Dbg_TDO_INST_0_i_7
       (.I0(Dbg_TDO_INST_0_i_20_n_0),
        .I1(Dbg_TDO_INST_0_i_21_n_0),
        .O(Dbg_TDO_INST_0_i_7_n_0),
        .S(Dbg_TDO_INST_0_i_19_n_0));
  LUT6 #(
    .INIT(64'h2B2B2B2828282B28)) 
    Dbg_TDO_INST_0_i_8
       (.I0(Dbg_TDO_INST_0_i_22_n_0),
        .I1(A1),
        .I2(A2),
        .I3(\Serial_Dbg_Intf.status_reg_reg_n_0_[16] ),
        .I4(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I5(\Serial_Dbg_Intf.status_reg_reg_n_0_[17] ),
        .O(Dbg_TDO_INST_0_i_8_n_0));
  LUT2 #(
    .INIT(4'h7)) 
    Dbg_TDO_INST_0_i_9
       (.I0(A1),
        .I1(A2),
        .O(Dbg_TDO_INST_0_i_9_n_0));
  FDRE Full_32_bit_1_reg
       (.C(Clk),
        .CE(wb_Halted),
        .D(wb_read_imm_reg_1),
        .Q(Full_32_bit_1),
        .R(reset_bool_for_rst));
  FDRE Full_32_bit_reg
       (.C(Clk),
        .CE(wb_Halted),
        .D(wb_read_imm_reg),
        .Q(Full_32_bit),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.dbg_brki_hit_reg 
       (.C(Clk),
        .CE(wb_Halted),
        .D(wb_brki_hit),
        .Q(dbg_brki_hit),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \Performance_Debug_Control.dbg_freeze_nohalt_i_1 
       (.I0(dbg_freeze_nohalt0_in),
        .I1(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .I2(p_4_out__0),
        .I3(\Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0 ),
        .I4(\Performance_Debug_Control.dbg_freeze_nohalt_i_3_n_0 ),
        .I5(\Performance_Debug_Control.dbg_freeze_nohalt_reg_0 ),
        .O(\Performance_Debug_Control.dbg_freeze_nohalt_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFD00)) 
    \Performance_Debug_Control.dbg_freeze_nohalt_i_3 
       (.I0(\Serial_Dbg_Intf.control_reg_reg_n_0_[0] ),
        .I1(start_single_step_reg_n_0),
        .I2(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg_0 ),
        .I4(reset_bool_for_rst),
        .O(\Performance_Debug_Control.dbg_freeze_nohalt_i_3_n_0 ));
  FDRE \Performance_Debug_Control.dbg_freeze_nohalt_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Performance_Debug_Control.dbg_freeze_nohalt_i_1_n_0 ),
        .Q(\Performance_Debug_Control.dbg_freeze_nohalt_reg_0 ),
        .R(1'b0));
  FDRE \Performance_Debug_Control.dbg_hit_reg[0] 
       (.C(Clk),
        .CE(wb_Halted),
        .D(wb_dbg_hit),
        .Q(dbg_hit),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'hA888FFFFA8880000)) 
    \Performance_Debug_Control.dbg_state_nohalt_i_1 
       (.I0(dbg_freeze_nohalt0_in),
        .I1(\Serial_Dbg_Intf.control_reg_reg_n_0_[0] ),
        .I2(saved_reset_mode_dbg_halt),
        .I3(dbg_halt_reset_mode_reg_0),
        .I4(\Performance_Debug_Control.dbg_state_nohalt_i_3_n_0 ),
        .I5(\Performance_Debug_Control.dbg_state_nohalt_reg_0 ),
        .O(\Performance_Debug_Control.dbg_state_nohalt_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000054FE5454)) 
    \Performance_Debug_Control.dbg_state_nohalt_i_2 
       (.I0(reset_bool_for_rst),
        .I1(dbg_halt_reset_mode_reg_0),
        .I2(wb_Halted),
        .I3(Reset_Mode[1]),
        .I4(Reset_Mode[0]),
        .I5(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .O(dbg_freeze_nohalt0_in));
  LUT6 #(
    .INIT(64'hFFFFFFFFFEFFFEFE)) 
    \Performance_Debug_Control.dbg_state_nohalt_i_3 
       (.I0(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .I1(reset_bool_for_rst),
        .I2(p_4_out__0),
        .I3(\Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0 ),
        .I4(p_37_out__0),
        .I5(\Performance_Debug_Control.dbg_state_nohalt_i_4_n_0 ),
        .O(\Performance_Debug_Control.dbg_state_nohalt_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h07)) 
    \Performance_Debug_Control.dbg_state_nohalt_i_4 
       (.I0(dbg_halt_reset_mode_reg_0),
        .I1(saved_reset_mode_dbg_halt),
        .I2(\Serial_Dbg_Intf.control_reg_reg_n_0_[0] ),
        .O(\Performance_Debug_Control.dbg_state_nohalt_i_4_n_0 ));
  FDRE \Performance_Debug_Control.dbg_state_nohalt_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Performance_Debug_Control.dbg_state_nohalt_i_1_n_0 ),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg_0 ),
        .R(1'b0));
  FDRE \Performance_Debug_Control.dbg_stop_1_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(Dbg_Stop),
        .Q(dbg_stop_1),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.dbg_stop_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(sync_trig_out_0_n_2),
        .Q(\Performance_Debug_Control.dbg_stop_i_reg_n_0 ),
        .R(dbg_stop_i));
  LUT6 #(
    .INIT(64'h00000000000000FE)) 
    \Performance_Debug_Control.dbg_stop_if_delay_i_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg_0 ),
        .I1(wb_Halted),
        .I2(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .I3(reset_bool_for_rst),
        .I4(saved_reset_mode_sleep),
        .I5(dbg_halt_reset_mode_reg_0),
        .O(\Performance_Debug_Control.dbg_stop_if_delay_i_i_1_n_0 ));
  FDRE \Performance_Debug_Control.dbg_stop_if_delay_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Performance_Debug_Control.dbg_stop_if_delay_i_i_1_n_0 ),
        .Q(LOCKSTEP_Master_Out[32]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000FE02)) 
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1 
       (.I0(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .I1(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2_n_0 ),
        .I2(reset_bool_for_rst),
        .I3(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1 ),
        .I4(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .O(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFEFEFEFEEEFEEEE)) 
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2 
       (.I0(dbg_halt_reset_mode_reg_0),
        .I1(wb_Halted),
        .I2(\Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0 ),
        .I3(Sleep_Out),
        .I4(saved_reset_mode_sleep),
        .I5(p_37_out__0),
        .O(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hAAA8AAAA)) 
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_4 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg_0 ),
        .I1(reset_bool_for_rst),
        .I2(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .I3(start_single_step_reg_n_0),
        .I4(\Serial_Dbg_Intf.control_reg_reg_n_0_[0] ),
        .O(p_37_out__0));
  FDRE \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_1_n_0 ),
        .Q(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .R(1'b0));
  FDRE \Performance_Debug_Control.ex_brki_hit_reg 
       (.C(Clk),
        .CE(of_piperun_for_ce),
        .D(\Performance_Debug_Control.ex_brki_hit_reg_0 ),
        .Q(ex_brki_hit),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.ex_dbg_hit_reg[0] 
       (.C(Clk),
        .CE(of_piperun_for_ce),
        .D(\Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_0 ),
        .Q(ex_pc_brk),
        .R(reset_bool_for_rst));
  LUT3 #(
    .INIT(8'h8F)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_4 
       (.I0(normal_stop_i),
        .I1(dbg_clean_stop),
        .I2(single_Step_N),
        .O(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_4_n_0 ));
  FDRE \Performance_Debug_Control.ex_dbg_pc_hit_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_2 ),
        .Q(LOCKSTEP_Master_Out[35]),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_1 ),
        .Q(\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_n_0 ),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.ex_step_continue_hold_reg 
       (.C(Clk),
        .CE(of_piperun_for_ce),
        .D(\Performance_Debug_Control.step_continue_hold_reg_n_0 ),
        .Q(ex_step_continue_hold),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.force_stop_cmd_1_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ),
        .Q(force_stop_cmd_1),
        .R(reset_bool_for_rst));
  LUT5 #(
    .INIT(32'hFFFF0010)) 
    \Performance_Debug_Control.force_stop_i_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg_0 ),
        .I1(wb_Halted),
        .I2(force_stop_cmd_1),
        .I3(\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ),
        .I4(force_stop_i),
        .O(\Performance_Debug_Control.force_stop_i_i_1_n_0 ));
  FDRE \Performance_Debug_Control.force_stop_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Performance_Debug_Control.force_stop_i_i_1_n_0 ),
        .Q(force_stop_i),
        .R(dbg_stop_i));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Performance_Debug_Control.force_stop_overrun_i_1 
       (.I0(force_stop_cmd_1),
        .I1(\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ),
        .O(p_56_out));
  FDRE \Performance_Debug_Control.force_stop_overrun_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_56_out),
        .Q(force_stop_overrun),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.m0_brki_hit_reg 
       (.C(Clk),
        .CE(ex_piperun_for_ce),
        .D(ex_brki_hit),
        .Q(m0_brki_hit),
        .R(reset_bool_for_rst));
  LUT3 #(
    .INIT(8'hBA)) 
    \Performance_Debug_Control.m0_dbg_hit[0]_i_1 
       (.I0(ex_pc_brk),
        .I1(ex_step_continue_hold),
        .I2(\Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0] ),
        .O(\Performance_Debug_Control.m0_dbg_hit[0]_i_1_n_0 ));
  FDRE \Performance_Debug_Control.m0_dbg_hit_reg[0] 
       (.C(Clk),
        .CE(ex_piperun_for_ce),
        .D(\Performance_Debug_Control.m0_dbg_hit[0]_i_1_n_0 ),
        .Q(\Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0] ),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.normal_stop_cmd_1_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0 ),
        .Q(normal_stop_cmd_1),
        .R(reset_bool_for_rst));
  LUT5 #(
    .INIT(32'hFFFF0100)) 
    \Performance_Debug_Control.normal_stop_i_i_1 
       (.I0(\Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0 ),
        .I1(wb_Halted),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg_0 ),
        .I3(normal_stop_cmd_1),
        .I4(normal_stop_i),
        .O(\Performance_Debug_Control.normal_stop_i_i_1_n_0 ));
  FDRE \Performance_Debug_Control.normal_stop_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Performance_Debug_Control.normal_stop_i_i_1_n_0 ),
        .Q(normal_stop_i),
        .R(dbg_stop_i));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT4 #(
    .INIT(16'h0F0E)) 
    \Performance_Debug_Control.step_continue_hold_i_1 
       (.I0(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .I1(start_single_step_reg_n_0),
        .I2(of_piperun_for_ce),
        .I3(\Performance_Debug_Control.step_continue_hold_reg_n_0 ),
        .O(\Performance_Debug_Control.step_continue_hold_i_1_n_0 ));
  FDRE \Performance_Debug_Control.step_continue_hold_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Performance_Debug_Control.step_continue_hold_i_1_n_0 ),
        .Q(\Performance_Debug_Control.step_continue_hold_reg_n_0 ),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.trig_ack_out_0_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(sync_trig_out_0_n_1),
        .Q(Dbg_Trig_Ack_Out[1]),
        .R(1'b0));
  FDRE \Performance_Debug_Control.trig_out_0_synced_1_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(trig_out_0_synced),
        .Q(trig_out_0_synced_1),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.wb_brki_hit_reg 
       (.C(Clk),
        .CE(m3_piperun_for_ce),
        .D(m0_brki_hit),
        .Q(wb_brki_hit),
        .R(reset_bool_for_rst));
  FDRE \Performance_Debug_Control.wb_dbg_hit_reg[0] 
       (.C(Clk),
        .CE(m3_piperun_for_ce),
        .D(\Performance_Debug_Control.m0_dbg_hit_reg_n_0_[0] ),
        .Q(wb_dbg_hit),
        .R(reset_bool_for_rst));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'hD000)) 
    Read_Strobe_INST_0
       (.I0(LOCKSTEP_Master_Out[35]),
        .I1(LOCKSTEP_Master_Out[32]),
        .I2(ex_valid),
        .I3(ex_is_load_instr_s),
        .O(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ));
  LUT5 #(
    .INIT(32'h00000010)) 
    \Serial_Dbg_Intf.Instr_Insert_Reg_En_1_i_1 
       (.I0(Dbg_Reg_En_0_sn_1),
        .I1(Dbg_Reg_En[6]),
        .I2(Dbg_Reg_En[5]),
        .I3(Dbg_Reg_En[4]),
        .I4(Dbg_Reg_En[7]),
        .O(Instr_Insert_Reg_En));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.Instr_Insert_Reg_En_1_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(Instr_Insert_Reg_En),
        .Q(Instr_Insert_Reg_En_1));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Dbg_Instr2_TCK_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(New_Dbg_Instr_TCK),
        .Q(p_1_out__5));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \Serial_Dbg_Intf.New_Dbg_Instr_TCK_i_1 
       (.I0(p_95_in),
        .I1(Instr_Insert_Reg_En),
        .I2(instr_read_reg[1]),
        .I3(instr_read_reg[0]),
        .O(p_97_out));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    \Serial_Dbg_Intf.New_Dbg_Instr_TCK_i_2 
       (.I0(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I1(A1),
        .I2(sel0),
        .I3(A3),
        .I4(A2),
        .O(p_95_in));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Dbg_Instr_TCK_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_97_out),
        .Q(New_Dbg_Instr_TCK));
  LUT3 #(
    .INIT(8'h08)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1 
       (.I0(Scan_Reset_Sel),
        .I1(Scan_Reset),
        .I2(Scan_En),
        .O(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[0] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[1] ),
        .Q(LOCKSTEP_Master_Out[31]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[10] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[11] ),
        .Q(LOCKSTEP_Master_Out[21]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[11] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[12] ),
        .Q(LOCKSTEP_Master_Out[20]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[12] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[13] ),
        .Q(LOCKSTEP_Master_Out[19]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[13] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[14] ),
        .Q(LOCKSTEP_Master_Out[18]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[14] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[15] ),
        .Q(LOCKSTEP_Master_Out[17]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[15] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[16] ),
        .Q(LOCKSTEP_Master_Out[16]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[16] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[17] ),
        .Q(LOCKSTEP_Master_Out[15]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[17] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[18] ),
        .Q(LOCKSTEP_Master_Out[14]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[18] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[19] ),
        .Q(LOCKSTEP_Master_Out[13]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[19] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[20] ),
        .Q(LOCKSTEP_Master_Out[12]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[1] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[2] ),
        .Q(LOCKSTEP_Master_Out[30]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[20] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[21] ),
        .Q(LOCKSTEP_Master_Out[11]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[21] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[22] ),
        .Q(LOCKSTEP_Master_Out[10]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[22] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[23] ),
        .Q(LOCKSTEP_Master_Out[9]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[23] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[24] ),
        .Q(LOCKSTEP_Master_Out[8]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[24] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[25] ),
        .Q(LOCKSTEP_Master_Out[7]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[25] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[26] ),
        .Q(LOCKSTEP_Master_Out[6]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[26] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[27] ),
        .Q(LOCKSTEP_Master_Out[5]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[27] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[28] ),
        .Q(LOCKSTEP_Master_Out[4]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[28] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[29] ),
        .Q(LOCKSTEP_Master_Out[3]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[29] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[30] ),
        .Q(LOCKSTEP_Master_Out[2]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[2] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[3] ),
        .Q(LOCKSTEP_Master_Out[29]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[30] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[31] ),
        .Q(LOCKSTEP_Master_Out[1]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[31] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(Dbg_TDI),
        .Q(LOCKSTEP_Master_Out[0]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[3] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[4] ),
        .Q(LOCKSTEP_Master_Out[28]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[4] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[5] ),
        .Q(LOCKSTEP_Master_Out[27]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[5] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[6] ),
        .Q(LOCKSTEP_Master_Out[26]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[6] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[7] ),
        .Q(LOCKSTEP_Master_Out[25]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[7] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[8] ),
        .Q(LOCKSTEP_Master_Out[24]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[8] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[9] ),
        .Q(LOCKSTEP_Master_Out[23]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.New_Instr_Reg_TCK_reg[9] 
       (.C(Dbg_Clk),
        .CE(New_Dbg_Instr_TCK),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[10] ),
        .Q(LOCKSTEP_Master_Out[22]));
  design_1_microblaze_0_0_MB_SRL16E \Serial_Dbg_Intf.SRL16E_1 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q_0(Q_0));
  design_1_microblaze_0_0_MB_SRL16E__parameterized1 \Serial_Dbg_Intf.SRL16E_2 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q11_in(Q11_in));
  design_1_microblaze_0_0_MB_SRL16E__parameterized7 \Serial_Dbg_Intf.SRL16E_3 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q2_in(Q2_in));
  design_1_microblaze_0_0_MB_SRL16E__parameterized9 \Serial_Dbg_Intf.SRL16E_4 
       (.Config_Reg_En(Config_Reg_En),
        .Data_Read_Reg_En(Data_Read_Reg_En),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_TDO(Dbg_TDO),
        .Dbg_TDO_INST_0_i_2_0(\Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I_n_0 ),
        .Dbg_TDO_INST_0_i_5_0(\Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector_n_0 ),
        .Instr_Insert_Reg_En(Instr_Insert_Reg_En),
        .Q({sel0__0,sel0,A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q0_out(Q0_out),
        .Q2_in(Q2_in),
        .Q3_in(Q3_in),
        .Status_Reg_En(Status_Reg_En),
        .TDO_Data_Reg__31(TDO_Data_Reg__31),
        .TDO_Instr_Reg__0(TDO_Instr_Reg__0),
        .TDO_Status_Reg__17(TDO_Status_Reg__17),
        .tdo_config_word1_0(tdo_config_word1_0));
  design_1_microblaze_0_0_MB_SRL16E__parameterized1_17 \Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .\Serial_Dbg_Intf.shift_count_reg[0] (\Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector_n_0 ));
  design_1_microblaze_0_0_MB_SRL16E__parameterized1_18 \Serial_Dbg_Intf.The_Base_Vector[2].SRL16E_Base_Vector 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .tdo_config_word1_0(tdo_config_word1_0));
  design_1_microblaze_0_0_MB_SRL16E__parameterized3 \Serial_Dbg_Intf.The_Cache_Addresses[1].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q6_out(Q6_out));
  design_1_microblaze_0_0_MB_SRL16E__parameterized5 \Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Dbg_TDO_INST_0_i_5(\Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I_n_0 ),
        .Q({sel0__0[2:1],sel0,A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q11_in(Q11_in),
        .Q6_out(Q6_out),
        .Q_0(Q_0),
        .\Serial_Dbg_Intf.shift_count_reg[6] (\Serial_Dbg_Intf.The_Cache_Addresses[2].SRL16E_Cache_I_n_0 ));
  design_1_microblaze_0_0_MB_SRL16E__parameterized1_19 \Serial_Dbg_Intf.The_Cache_Addresses[3].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q4_out(Q4_out));
  design_1_microblaze_0_0_MB_SRL16E__parameterized1_20 \Serial_Dbg_Intf.The_Cache_Addresses[4].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q3_out(Q3_out));
  design_1_microblaze_0_0_MB_SRL16E__parameterized3_21 \Serial_Dbg_Intf.The_Cache_Addresses[5].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q2_out(Q2_out));
  design_1_microblaze_0_0_MB_SRL16E__parameterized5_22 \Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Q({sel0__0[1],sel0,A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q2_out(Q2_out),
        .Q3_out(Q3_out),
        .Q4_out(Q4_out),
        .\Serial_Dbg_Intf.shift_count_reg[5] (\Serial_Dbg_Intf.The_Cache_Addresses[6].SRL16E_Cache_I_n_0 ));
  design_1_microblaze_0_0_MB_SRL16E__parameterized1_23 \Serial_Dbg_Intf.The_Cache_Addresses[7].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q0_out(Q0_out));
  design_1_microblaze_0_0_MB_SRL16E__parameterized1_24 \Serial_Dbg_Intf.The_Cache_Addresses[8].SRL16E_Cache_I 
       (.Dbg_Clk(Dbg_Clk),
        .Q({A3,A2,A1,\Serial_Dbg_Intf.shift_count_reg_n_0_[0] }),
        .Q3_in(Q3_in));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.capture_1_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(Dbg_Capture),
        .Q(capture_1));
  LUT5 #(
    .INIT(32'h00000010)) 
    \Serial_Dbg_Intf.command_reg[0]_i_1 
       (.I0(Dbg_Reg_En_0_sn_1),
        .I1(Dbg_Reg_En[7]),
        .I2(Dbg_Reg_En[6]),
        .I3(Dbg_Reg_En[4]),
        .I4(Dbg_Reg_En[5]),
        .O(Command_Reg_En));
  LUT4 #(
    .INIT(16'h00E4)) 
    \Serial_Dbg_Intf.command_reg[0]_i_2 
       (.I0(Scan_Reset_Sel),
        .I1(command_reg_clear),
        .I2(Scan_Reset),
        .I3(Scan_En),
        .O(\Serial_Dbg_Intf.command_reg[0]_i_2_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.command_reg_reg[0] 
       (.C(Dbg_Update),
        .CE(Command_Reg_En),
        .CLR(\Serial_Dbg_Intf.command_reg[0]_i_2_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[30] ),
        .Q(p_1_out__2));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.command_reg_reg[1] 
       (.C(Dbg_Update),
        .CE(Command_Reg_En),
        .CLR(\Serial_Dbg_Intf.command_reg[0]_i_2_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[31] ),
        .Q(p_1_out__3));
  LUT4 #(
    .INIT(16'h00E4)) 
    \Serial_Dbg_Intf.continue_from_brk_TClk_i_1 
       (.I0(Scan_Reset_Sel),
        .I1(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .I2(Scan_Reset),
        .I3(Scan_En),
        .O(\Serial_Dbg_Intf.continue_from_brk_TClk_i_1_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.continue_from_brk_TClk_reg 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.continue_from_brk_TClk_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[24] ),
        .Q(p_1_out__4));
  FDRE \Serial_Dbg_Intf.continue_from_brk_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_11_out),
        .Q(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .R(reset_bool_for_rst));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.control_reg_reg[0] 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[22] ),
        .Q(\Serial_Dbg_Intf.control_reg_reg_n_0_[0] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.control_reg_reg[3] 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[25] ),
        .Q(\Serial_Dbg_Intf.control_reg_reg_n_0_[3] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.control_reg_reg[4] 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[26] ),
        .Q(\Serial_Dbg_Intf.control_reg_reg_n_0_[4] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.control_reg_reg[5] 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[27] ),
        .Q(\Serial_Dbg_Intf.control_reg_reg_n_0_[5] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.control_reg_reg[8] 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[30] ),
        .Q(Q));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[0] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[0] ),
        .Q(data_read_reg[0]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[10] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[10] ),
        .Q(data_read_reg[10]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[11] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[11] ),
        .Q(data_read_reg[11]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[12] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[12] ),
        .Q(data_read_reg[12]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[13] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[13] ),
        .Q(data_read_reg[13]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[14] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[14] ),
        .Q(data_read_reg[14]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[15] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[15] ),
        .Q(data_read_reg[15]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[16] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[16] ),
        .Q(data_read_reg[16]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[17] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[17] ),
        .Q(data_read_reg[17]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[18] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[18] ),
        .Q(data_read_reg[18]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[19] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[19] ),
        .Q(data_read_reg[19]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[1] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[1] ),
        .Q(data_read_reg[1]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[20] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[20] ),
        .Q(data_read_reg[20]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[21] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[21] ),
        .Q(data_read_reg[21]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[22] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[22] ),
        .Q(data_read_reg[22]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[23] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[23] ),
        .Q(data_read_reg[23]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[24] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[24] ),
        .Q(data_read_reg[24]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[25] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[25] ),
        .Q(data_read_reg[25]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[26] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[26] ),
        .Q(data_read_reg[26]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[27] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[27] ),
        .Q(data_read_reg[27]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[28] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[28] ),
        .Q(data_read_reg[28]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[29] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[29] ),
        .Q(data_read_reg[29]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[2] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[2] ),
        .Q(data_read_reg[2]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[30] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[30] ),
        .Q(data_read_reg[30]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[31] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[31] ),
        .Q(data_read_reg[31]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[32] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[32] ),
        .Q(data_read_reg[32]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[3] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[3] ),
        .Q(data_read_reg[3]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[4] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[4] ),
        .Q(data_read_reg[4]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[5] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[5] ),
        .Q(data_read_reg[5]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[6] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[6] ),
        .Q(data_read_reg[6]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[7] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[7] ),
        .Q(data_read_reg[7]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[8] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[8] ),
        .Q(data_read_reg[8]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.data_read_reg_reg[9] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg_n_0_[9] ),
        .Q(data_read_reg[9]));
  FDRE \Serial_Dbg_Intf.dbg_disable_interrupt_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[9]),
        .Q(LOCKSTEP_Master_Out[37]),
        .R(reset_bool_for_rst));
  LUT5 #(
    .INIT(32'h00000010)) 
    \Serial_Dbg_Intf.dbg_wakeup_i_i_1 
       (.I0(Dbg_Reg_En_0_sn_1),
        .I1(Dbg_Reg_En[6]),
        .I2(Dbg_Reg_En[7]),
        .I3(Dbg_Reg_En[4]),
        .I4(Dbg_Reg_En[5]),
        .O(Control_Reg_En));
  LUT5 #(
    .INIT(32'h0000AB01)) 
    \Serial_Dbg_Intf.dbg_wakeup_i_i_2 
       (.I0(Scan_Reset_Sel),
        .I1(Sleep_Out),
        .I2(Sleep_Decode),
        .I3(Scan_Reset),
        .I4(Scan_En),
        .O(\Serial_Dbg_Intf.dbg_wakeup_i_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Serial_Dbg_Intf.dbg_wakeup_i_i_3 
       (.I0(Dbg_Reg_En[0]),
        .I1(Dbg_Reg_En[1]),
        .I2(Dbg_Reg_En[3]),
        .I3(Dbg_Reg_En[2]),
        .O(Dbg_Reg_En_0_sn_1));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.dbg_wakeup_i_reg 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.dbg_wakeup_i_i_2_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[31] ),
        .Q(LOCKSTEP_Master_Out[34]));
  LUT4 #(
    .INIT(16'h00E4)) 
    \Serial_Dbg_Intf.force_stop_TClk_i_1 
       (.I0(Scan_Reset_Sel),
        .I1(\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ),
        .I2(Scan_Reset),
        .I3(Scan_En),
        .O(\Serial_Dbg_Intf.force_stop_TClk_i_1_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.force_stop_TClk_reg 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.force_stop_TClk_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[29] ),
        .Q(p_1_out__0));
  FDRE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.force_stop_cmd_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_91_out),
        .Q(\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ),
        .R(reset_bool_for_rst));
  FDRE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.if_debug_ready_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_76_out),
        .Q(LOCKSTEP_Master_Out[36]),
        .R(reset_bool_for_rst));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.instr_read_reg_reg[0] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(instr_rd_reg),
        .Q(instr_read_reg[0]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.instr_read_reg_reg[1] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(exception_reg_0),
        .Q(instr_read_reg[1]));
  FDRE \Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Insert_Reg_En_1),
        .Q(\Serial_Dbg_Intf.new_dbg_instr_shifting_CLK_reg_n_0 ),
        .R(reset_bool_for_rst));
  LUT4 #(
    .INIT(16'h00E4)) 
    \Serial_Dbg_Intf.normal_stop_TClk_i_1 
       (.I0(Scan_Reset_Sel),
        .I1(\Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0 ),
        .I2(Scan_Reset),
        .I3(Scan_En),
        .O(\Serial_Dbg_Intf.normal_stop_TClk_i_1_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.normal_stop_TClk_reg 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.normal_stop_TClk_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[28] ),
        .Q(p_1_out));
  FDRE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.normal_stop_cmd_i_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_94_out),
        .Q(\Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0 ),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.read_register_MSR_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_86_out),
        .Q(read_register_MSR),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.read_register_PC_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_83_out),
        .Q(read_register_PC),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[0] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[0]),
        .Q(\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[0] ),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[1]),
        .Q(\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[1] ),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[2]),
        .Q(\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[2] ),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[3] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[3]),
        .Q(\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[3] ),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[4] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[4]),
        .Q(\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[4] ),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[5] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[5]),
        .Q(p_0_in_1),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[6] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[6]),
        .Q(\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[6] ),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[7] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[7]),
        .Q(p_0_in71_in),
        .R(reset_bool_for_rst));
  FDRE \Serial_Dbg_Intf.sample_synced_1_reg[8] 
       (.C(Clk),
        .CE(1'b1),
        .D(sample_synced[8]),
        .Q(\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[8] ),
        .R(reset_bool_for_rst));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Serial_Dbg_Intf.shift_count[0]_i_1 
       (.I0(Dbg_Shift),
        .I1(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .O(\Serial_Dbg_Intf.shift_count[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \Serial_Dbg_Intf.shift_count[1]_i_1 
       (.I0(A1),
        .I1(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I2(Dbg_Shift),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \Serial_Dbg_Intf.shift_count[2]_i_1 
       (.I0(A2),
        .I1(A1),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(Dbg_Shift),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \Serial_Dbg_Intf.shift_count[3]_i_1 
       (.I0(A3),
        .I1(A2),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(Dbg_Shift),
        .O(p_0_in[3]));
  LUT6 #(
    .INIT(64'h6AAAAAAA00000000)) 
    \Serial_Dbg_Intf.shift_count[4]_i_1 
       (.I0(sel0),
        .I1(A3),
        .I2(A1),
        .I3(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I4(A2),
        .I5(Dbg_Shift),
        .O(p_0_in[4]));
  LUT3 #(
    .INIT(8'h60)) 
    \Serial_Dbg_Intf.shift_count[5]_i_1 
       (.I0(sel0__0[1]),
        .I1(\Serial_Dbg_Intf.shift_count[5]_i_2_n_0 ),
        .I2(Dbg_Shift),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \Serial_Dbg_Intf.shift_count[5]_i_2 
       (.I0(sel0),
        .I1(A2),
        .I2(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I3(A1),
        .I4(A3),
        .O(\Serial_Dbg_Intf.shift_count[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \Serial_Dbg_Intf.shift_count[6]_i_1 
       (.I0(sel0__0[2]),
        .I1(\Serial_Dbg_Intf.shift_count[7]_i_2_n_0 ),
        .I2(Dbg_Shift),
        .O(p_0_in[6]));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \Serial_Dbg_Intf.shift_count[7]_i_1 
       (.I0(sel0__0[3]),
        .I1(sel0__0[2]),
        .I2(\Serial_Dbg_Intf.shift_count[7]_i_2_n_0 ),
        .I3(Dbg_Shift),
        .O(p_0_in[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \Serial_Dbg_Intf.shift_count[7]_i_2 
       (.I0(sel0__0[1]),
        .I1(A3),
        .I2(A1),
        .I3(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ),
        .I4(A2),
        .I5(sel0),
        .O(\Serial_Dbg_Intf.shift_count[7]_i_2_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[0] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_count[0]_i_1_n_0 ),
        .Q(\Serial_Dbg_Intf.shift_count_reg_n_0_[0] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[1] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_0_in[1]),
        .Q(A1));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[2] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_0_in[2]),
        .Q(A2));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[3] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_0_in[3]),
        .Q(A3));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[4] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_0_in[4]),
        .Q(sel0));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[5] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_0_in[5]),
        .Q(sel0__0[1]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[6] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_0_in[6]),
        .Q(sel0__0[2]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_count_reg[7] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(p_0_in[7]),
        .Q(sel0__0[3]));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[10] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[11] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[10] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[11] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[12] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[11] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[12] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[13] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[12] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[13] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[14] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[13] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[14] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[15] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[14] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[15] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[16] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[15] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[16] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[17] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[16] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[17] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[18] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[17] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[18] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[19] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[18] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[19] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[20] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[19] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[1] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[2] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[1] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[20] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[21] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[20] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[21] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[22] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[21] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[22] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[23] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[22] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[23] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[24] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[23] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[24] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[25] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[24] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[25] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[26] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[25] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[26] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[27] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[26] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[27] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[28] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[27] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[28] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[29] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[28] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[29] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[30] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[29] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[2] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[3] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[2] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[30] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[31] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[30] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[31] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(Dbg_TDI),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[31] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[3] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[4] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[3] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[4] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[5] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[4] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[5] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[6] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[5] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[6] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[7] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[6] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[7] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[8] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[7] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[8] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[9] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[8] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.shift_datain_reg[9] 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[10] ),
        .Q(\Serial_Dbg_Intf.shift_datain_reg_n_0_[9] ));
  LUT4 #(
    .INIT(16'h00E4)) 
    \Serial_Dbg_Intf.single_Step_TClk_i_1 
       (.I0(Scan_Reset_Sel),
        .I1(start_single_step_reg_n_0),
        .I2(Scan_Reset),
        .I3(Scan_En),
        .O(\Serial_Dbg_Intf.single_Step_TClk_i_1_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.single_Step_TClk_reg 
       (.C(Dbg_Update),
        .CE(Control_Reg_En),
        .CLR(\Serial_Dbg_Intf.single_Step_TClk_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.shift_datain_reg_n_0_[23] ),
        .Q(p_1_out__1));
  FDRE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.start_single_cmd_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(p_88_out),
        .Q(start_single_cmd),
        .R(reset_bool_for_rst));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[0] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(sync),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[0] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[16] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.sync_stop_CPU_n_0 ),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[16] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[17] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(reset_bool_for_rst),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[17] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[18] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(Full_32_bit),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[18] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[19] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(delay_slot_instr),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[19] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[20] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(Full_32_bit_1),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[20] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[22] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.status_reg_reg[22]_0 ),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[22] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[23] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(dbg_brki_hit_synced),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[23] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[24] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(running_clock_synced),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[24] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[25] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(D[1]),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[25] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[27] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(sleep_synced),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[27] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[28] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(pause_synced),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[28] ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.status_reg_reg[29] 
       (.C(Dbg_Clk),
        .CE(Dbg_Capture),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(unchanged),
        .Q(\Serial_Dbg_Intf.status_reg_reg_n_0_[29] ));
  design_1_microblaze_0_0_mb_sync_bit__parameterized2 \Serial_Dbg_Intf.sync_dbg_brk_hit 
       (.D(dbg_brki_hit_synced),
        .Dbg_Clk(Dbg_Clk),
        .\Single_Synchronize.use_async_reset.sync_reg_0 (\Serial_Dbg_Intf.sync_pause_n_1 ),
        .dbg_brki_hit(dbg_brki_hit));
  design_1_microblaze_0_0_mb_sync_vec \Serial_Dbg_Intf.sync_dbg_hit 
       (.D(sync),
        .Dbg_Clk(Dbg_Clk),
        .\Single_Synchronize.use_async_reset.sync_reg (\Serial_Dbg_Intf.sync_pause_n_1 ),
        .dbg_hit(dbg_hit));
  design_1_microblaze_0_0_mb_sync_bit__parameterized4 \Serial_Dbg_Intf.sync_dbg_wakeup 
       (.Clk(Clk),
        .LOCKSTEP_Master_Out(LOCKSTEP_Master_Out[34:33]),
        .\Performance_Debug_Control.dbg_stop_i_reg (\Serial_Dbg_Intf.sync_dbg_wakeup_n_0 ),
        .dbg_continue_i_reg(\Performance_Debug_Control.dbg_stop_i_reg_n_0 ),
        .dbg_continue_i_reg_0(\Serial_Dbg_Intf.normal_stop_cmd_i_reg_n_0 ),
        .dbg_continue_i_reg_1(dbg_continue_i_i_2_n_0),
        .of_pause(of_pause),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_mb_sync_bit__parameterized2_25 \Serial_Dbg_Intf.sync_pause 
       (.D(pause_synced),
        .Dbg_Clk(Dbg_Clk),
        .Pause(Pause),
        .Scan_En(Scan_En),
        .Scan_Reset(Scan_Reset),
        .Scan_Reset_Sel(Scan_Reset_Sel),
        .\Single_Synchronize.use_async_reset.sync_i_1_0 (\Serial_Dbg_Intf.sync_pause_n_1 ));
  design_1_microblaze_0_0_mb_sync_bit__parameterized2_26 \Serial_Dbg_Intf.sync_running_clock 
       (.D(running_clock_synced),
        .Dbg_Clk(Dbg_Clk),
        .\Single_Synchronize.use_async_reset.sync_reg_0 (\Serial_Dbg_Intf.sync_pause_n_1 ),
        .running_clock(running_clock));
  design_1_microblaze_0_0_mb_sync_vec__parameterized1 \Serial_Dbg_Intf.sync_sample 
       (.Clk(Clk),
        .D(p_1_out),
        .Dbg_Trig_Ack_In(Dbg_Trig_Ack_In[0]),
        .Dbg_Trig_Ack_Out(Dbg_Trig_Ack_Out[0]),
        .Dbg_Trig_In(Dbg_Trig_In[0]),
        .Dbg_Trig_Out(Dbg_Trig_Out[0]),
        .Q({\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[0] ,\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[1] ,\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[2] ,\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[3] ,\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[4] ,p_0_in_1,\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[6] ,p_0_in71_in,\Serial_Dbg_Intf.sample_synced_1_reg_n_0_[8] }),
        .\Serial_Dbg_Intf.trig_ack_out_1_reg (\Serial_Dbg_Intf.sync_sample_n_12 ),
        .\Synchronize.use_sync_reset.sync_reg[1] (p_1_out__0),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (p_1_out__1),
        .\Synchronize.use_sync_reset.sync_reg[1]_1 ({p_1_out__2,p_1_out__3}),
        .\Synchronize.use_sync_reset.sync_reg[1]_2 (p_1_out__4),
        .\Synchronize.use_sync_reset.sync_reg[1]_3 (p_1_out__5),
        .\Synchronize.use_sync_reset.sync_reg[1]_4 (\Serial_Dbg_Intf.control_reg_reg_n_0_[3] ),
        .\Use_Async_Reset.sync_reset_reg (\Serial_Dbg_Intf.sync_sample_n_10 ),
        .p_11_out(p_11_out),
        .p_76_out(p_76_out),
        .p_83_out(p_83_out),
        .p_86_out(p_86_out),
        .p_88_out(p_88_out),
        .p_91_out(p_91_out),
        .p_94_out(p_94_out),
        .sample_synced(sample_synced),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_mb_sync_bit__parameterized2_27 \Serial_Dbg_Intf.sync_sleep 
       (.D(sleep_synced),
        .Dbg_Clk(Dbg_Clk),
        .\Single_Synchronize.use_async_reset.sync_reg_0 (\Serial_Dbg_Intf.sync_pause_n_1 ),
        .Sleep(Sleep));
  design_1_microblaze_0_0_mb_sync_bit__parameterized2_28 \Serial_Dbg_Intf.sync_stop_CPU 
       (.D(\Serial_Dbg_Intf.sync_stop_CPU_n_0 ),
        .Dbg_Clk(Dbg_Clk),
        .\Single_Synchronize.use_async_reset.sync_reg_0 (\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .\Single_Synchronize.use_async_reset.sync_reg_1 (\Serial_Dbg_Intf.sync_pause_n_1 ));
  FDRE \Serial_Dbg_Intf.trig_ack_out_1_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Serial_Dbg_Intf.sync_sample_n_12 ),
        .Q(Dbg_Trig_Ack_Out[0]),
        .R(1'b0));
  FDRE \Serial_Dbg_Intf.trig_in_1_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Serial_Dbg_Intf.sync_sample_n_10 ),
        .Q(Dbg_Trig_In[0]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00001000)) 
    \Serial_Dbg_Intf.unchanged_i_1 
       (.I0(Dbg_Reg_En[5]),
        .I1(Dbg_Reg_En[4]),
        .I2(Dbg_Reg_En[7]),
        .I3(Dbg_Reg_En[6]),
        .I4(Dbg_Reg_En_0_sn_1),
        .I5(unchanged),
        .O(\Serial_Dbg_Intf.unchanged_i_1_n_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Serial_Dbg_Intf.unchanged_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Serial_Dbg_Intf.New_Instr_Reg_TCK[0]_i_1_n_0 ),
        .D(\Serial_Dbg_Intf.unchanged_i_1_n_0 ),
        .Q(unchanged));
  LUT2 #(
    .INIT(4'hB)) 
    \Using_FPGA.Native_i_1__2 
       (.I0(LOCKSTEP_Master_Out[32]),
        .I1(LOCKSTEP_Master_Out[35]),
        .O(\Performance_Debug_Control.dbg_stop_if_delay_i_reg_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \Using_FPGA.Native_i_1__49 
       (.I0(LOCKSTEP_Master_Out[32]),
        .O(\Performance_Debug_Control.dbg_stop_if_delay_i_reg_1 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Using_FPGA.Native_i_1__8 
       (.I0(LOCKSTEP_Master_Out[35]),
        .I1(LOCKSTEP_Master_Out[32]),
        .O(ex_exception_no_load_store_mask));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT4 #(
    .INIT(16'hD000)) 
    \Using_FPGA.Native_i_4 
       (.I0(LOCKSTEP_Master_Out[35]),
        .I1(LOCKSTEP_Master_Out[32]),
        .I2(ex_valid),
        .I3(\Using_FPGA.Native_i_2__21 ),
        .O(ex_MSR_Load_ALU_C));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT4 #(
    .INIT(16'hD000)) 
    \Using_FPGA.Native_i_5 
       (.I0(LOCKSTEP_Master_Out[35]),
        .I1(LOCKSTEP_Master_Out[32]),
        .I2(ex_valid),
        .I3(ex_load_shift_carry),
        .O(ex_MSR_Load_Shift_C));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT4 #(
    .INIT(16'hD000)) 
    \Using_LWX_SWX_instr.ex_reservation_i_4 
       (.I0(LOCKSTEP_Master_Out[35]),
        .I1(LOCKSTEP_Master_Out[32]),
        .I2(ex_valid),
        .I3(\Using_LWX_SWX_instr.ex_reservation_i_3 ),
        .O(ex_MSR_Set_SW_BIP));
  design_1_microblaze_0_0_address_hit \Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I 
       (.Address(Address),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_Reg_En(Dbg_Reg_En),
        .Dbg_TDI(Dbg_TDI),
        .Hit(\Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_0 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 (\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg (\Performance_Debug_Control.dbg_stop_i_reg_n_0 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 (\Performance_Debug_Control.ex_dbg_pc_hit_i_i_4_n_0 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 (of_piperun_for_ce),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 (\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_n_0 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 (LOCKSTEP_Master_Out[35]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg (\Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_2 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 (ex_piperun_for_ce),
        .Q({\Serial_Dbg_Intf.control_reg_reg_n_0_[0] ,Q}),
        .ex_Exception_Taken(ex_Exception_Taken),
        .force_stop_i(force_stop_i),
        .mem_Exception_Taken(mem_Exception_Taken),
        .single_Step_N(single_Step_N),
        .single_Step_N_reg(\Using_PC_Breakpoints.All_PC_Brks[0].Serial_Interface_1.address_hit_I_n_1 ));
  LUT3 #(
    .INIT(8'h8A)) 
    Write_Strobe_INST_0_i_1
       (.I0(ex_valid),
        .I1(LOCKSTEP_Master_Out[32]),
        .I2(LOCKSTEP_Master_Out[35]),
        .O(p_231_in));
  LUT2 #(
    .INIT(4'hE)) 
    command_reg_clear_i_1
       (.I0(read_register_PC_1_reg_n_0),
        .I1(read_register_MSR_1_reg_0),
        .O(command_reg_clear_i_1_n_0));
  FDRE command_reg_clear_reg
       (.C(Clk),
        .CE(1'b1),
        .D(command_reg_clear_i_1_n_0),
        .Q(command_reg_clear),
        .R(reset_bool_for_rst));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \data_rd_reg[0]_i_1 
       (.I0(wb_gpr_wr_dbg),
        .I1(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .I2(read_register_MSR_1_reg_0),
        .I3(read_register_PC_1_reg_n_0),
        .O(\data_rd_reg[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCEAACFFFCEAACC00)) 
    \data_rd_reg[32]_i_1 
       (.I0(\data_rd_reg[32]_i_2_n_0 ),
        .I1(wb_gpr_wr_dbg),
        .I2(LOCKSTEP_Master_Out[36]),
        .I3(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .I4(\data_rd_reg[32]_i_3_n_0 ),
        .I5(\data_rd_reg_reg_n_0_[32] ),
        .O(\data_rd_reg[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \data_rd_reg[32]_i_2 
       (.I0(read_register_MSR_1_reg_0),
        .I1(\Performance_Debug_Control.dbg_freeze_nohalt_reg_0 ),
        .I2(wb_pc_valid),
        .O(\data_rd_reg[32]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \data_rd_reg[32]_i_3 
       (.I0(read_register_MSR_1_reg_0),
        .I1(read_register_PC_1_reg_n_0),
        .O(\data_rd_reg[32]_i_3_n_0 ));
  FDRE \data_rd_reg_reg[0] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [31]),
        .Q(\data_rd_reg_reg_n_0_[0] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[10] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [21]),
        .Q(\data_rd_reg_reg_n_0_[10] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[11] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [20]),
        .Q(\data_rd_reg_reg_n_0_[11] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[12] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [19]),
        .Q(\data_rd_reg_reg_n_0_[12] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[13] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [18]),
        .Q(\data_rd_reg_reg_n_0_[13] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[14] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [17]),
        .Q(\data_rd_reg_reg_n_0_[14] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[15] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [16]),
        .Q(\data_rd_reg_reg_n_0_[15] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[16] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [15]),
        .Q(\data_rd_reg_reg_n_0_[16] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[17] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [14]),
        .Q(\data_rd_reg_reg_n_0_[17] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[18] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [13]),
        .Q(\data_rd_reg_reg_n_0_[18] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[19] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [12]),
        .Q(\data_rd_reg_reg_n_0_[19] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[1] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [30]),
        .Q(\data_rd_reg_reg_n_0_[1] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[20] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [11]),
        .Q(\data_rd_reg_reg_n_0_[20] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[21] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [10]),
        .Q(\data_rd_reg_reg_n_0_[21] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[22] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [9]),
        .Q(\data_rd_reg_reg_n_0_[22] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[23] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [8]),
        .Q(\data_rd_reg_reg_n_0_[23] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[24] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [7]),
        .Q(\data_rd_reg_reg_n_0_[24] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[25] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [6]),
        .Q(\data_rd_reg_reg_n_0_[25] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[26] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [5]),
        .Q(\data_rd_reg_reg_n_0_[26] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[27] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [4]),
        .Q(\data_rd_reg_reg_n_0_[27] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[28] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [3]),
        .Q(\data_rd_reg_reg_n_0_[28] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[29] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [2]),
        .Q(\data_rd_reg_reg_n_0_[29] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[2] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [29]),
        .Q(\data_rd_reg_reg_n_0_[2] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[30] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [1]),
        .Q(\data_rd_reg_reg_n_0_[30] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[31] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [0]),
        .Q(\data_rd_reg_reg_n_0_[31] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[32] 
       (.C(Clk),
        .CE(1'b1),
        .D(\data_rd_reg[32]_i_1_n_0 ),
        .Q(\data_rd_reg_reg_n_0_[32] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[3] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [28]),
        .Q(\data_rd_reg_reg_n_0_[3] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[4] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [27]),
        .Q(\data_rd_reg_reg_n_0_[4] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[5] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [26]),
        .Q(\data_rd_reg_reg_n_0_[5] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[6] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [25]),
        .Q(\data_rd_reg_reg_n_0_[6] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[7] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [24]),
        .Q(\data_rd_reg_reg_n_0_[7] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[8] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [23]),
        .Q(\data_rd_reg_reg_n_0_[8] ),
        .R(reset_bool_for_rst));
  FDRE \data_rd_reg_reg[9] 
       (.C(Clk),
        .CE(\data_rd_reg[0]_i_1_n_0 ),
        .D(\data_rd_reg_reg[0]_0 [22]),
        .Q(\data_rd_reg_reg_n_0_[9] ),
        .R(reset_bool_for_rst));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    dbg_continue_i_i_2
       (.I0(LOCKSTEP_Master_Out[36]),
        .I1(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .I2(\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 ),
        .I3(start_single_cmd),
        .O(dbg_continue_i_i_2_n_0));
  FDRE dbg_continue_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(\Serial_Dbg_Intf.sync_dbg_wakeup_n_0 ),
        .Q(LOCKSTEP_Master_Out[33]),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'h22222222000000F0)) 
    dbg_halt_reset_mode_i_1
       (.I0(Reset_Mode[0]),
        .I1(Reset_Mode[1]),
        .I2(dbg_halt_reset_mode_reg_0),
        .I3(\Serial_Dbg_Intf.control_reg_reg_n_0_[0] ),
        .I4(step_continue__0),
        .I5(reset_bool_for_rst),
        .O(dbg_halt_reset_mode_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT2 #(
    .INIT(4'hE)) 
    dbg_halt_reset_mode_i_2
       (.I0(start_single_step_reg_n_0),
        .I1(\Serial_Dbg_Intf.continue_from_brk_reg_n_0 ),
        .O(step_continue__0));
  FDRE dbg_halt_reset_mode_reg
       (.C(Clk),
        .CE(1'b1),
        .D(dbg_halt_reset_mode_i_1_n_0),
        .Q(dbg_halt_reset_mode_reg_0),
        .R(1'b0));
  FDRE delay_slot_instr_reg
       (.C(Clk),
        .CE(wb_Halted),
        .D(D[0]),
        .Q(delay_slot_instr),
        .R(reset_bool_for_rst));
  LUT4 #(
    .INIT(16'h0002)) 
    exception_i_1
       (.I0(exception_reg_1),
        .I1(force_stop_overrun),
        .I2(start_dbg_exec_reg_n_0),
        .I3(reset_bool_for_rst),
        .O(exception_i_1_n_0));
  FDRE exception_reg
       (.C(Clk),
        .CE(1'b1),
        .D(exception_i_1_n_0),
        .Q(exception_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000EECE)) 
    executing_i_1
       (.I0(instr_rd_reg),
        .I1(start_dbg_exec_reg_n_0),
        .I2(executing_reg_0),
        .I3(wb_Halted),
        .I4(reset_bool_for_rst),
        .I5(force_stop_overrun),
        .O(executing_i_1_n_0));
  FDRE executing_reg
       (.C(Clk),
        .CE(1'b1),
        .D(executing_i_1_n_0),
        .Q(instr_rd_reg),
        .R(1'b0));
  FDRE mb_halted_1_reg
       (.C(Clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(mb_halted_1),
        .R(reset_bool_for_rst));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'h40)) 
    mem_exception_from_ex_i_1
       (.I0(LOCKSTEP_Master_Out[32]),
        .I1(LOCKSTEP_Master_Out[35]),
        .I2(ex_valid),
        .O(ex_Exception_Taken));
  FDRE read_register_MSR_1_reg
       (.C(Clk),
        .CE(1'b1),
        .D(read_register_MSR),
        .Q(read_register_MSR_1_reg_0),
        .R(reset_bool_for_rst));
  FDRE read_register_PC_1_reg
       (.C(Clk),
        .CE(1'b1),
        .D(read_register_PC),
        .Q(read_register_PC_1_reg_n_0),
        .R(reset_bool_for_rst));
  LUT4 #(
    .INIT(16'h00E4)) 
    running_clock_i_1
       (.I0(Scan_Reset_Sel),
        .I1(capture_1),
        .I2(Scan_Reset),
        .I3(Scan_En),
        .O(running_clock_i_1_n_0));
  FDCE #(
    .INIT(1'b0)) 
    running_clock_reg
       (.C(Clk),
        .CE(1'b1),
        .CLR(running_clock_i_1_n_0),
        .D(1'b1),
        .Q(running_clock));
  LUT4 #(
    .INIT(16'h2F20)) 
    saved_reset_mode_dbg_halt_i_1
       (.I0(Reset_Mode[0]),
        .I1(Reset_Mode[1]),
        .I2(reset_bool_for_rst),
        .I3(saved_reset_mode_dbg_halt),
        .O(saved_reset_mode_dbg_halt_i_1_n_0));
  FDRE saved_reset_mode_dbg_halt_reg
       (.C(Clk),
        .CE(1'b1),
        .D(saved_reset_mode_dbg_halt_i_1_n_0),
        .Q(saved_reset_mode_dbg_halt),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT4 #(
    .INIT(16'h22F0)) 
    saved_reset_mode_sleep_i_1
       (.I0(Reset_Mode[1]),
        .I1(Reset_Mode[0]),
        .I2(Sleep_Out),
        .I3(reset_bool_for_rst),
        .O(saved_reset_mode_sleep_i_1_n_0));
  FDRE saved_reset_mode_sleep_reg
       (.C(Clk),
        .CE(1'b1),
        .D(saved_reset_mode_sleep_i_1_n_0),
        .Q(saved_reset_mode_sleep),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFD)) 
    single_Step_N_i_1
       (.I0(start_single_step_reg_n_0),
        .I1(single_step_count[1]),
        .I2(single_step_count[0]),
        .O(single_Step_N_i_1_n_0));
  FDSE single_Step_N_reg
       (.C(Clk),
        .CE(of_piperun_for_ce),
        .D(single_Step_N_i_1_n_0),
        .Q(single_Step_N),
        .S(reset_bool_for_rst));
  LUT2 #(
    .INIT(4'hE)) 
    \single_step_count[0]_i_1 
       (.I0(start_single_cmd),
        .I1(of_piperun_for_ce),
        .O(\single_step_count[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h9F90)) 
    \single_step_count[0]_i_2 
       (.I0(single_step_count[1]),
        .I1(single_step_count[0]),
        .I2(of_piperun_for_ce),
        .I3(\Serial_Dbg_Intf.control_reg_reg_n_0_[4] ),
        .O(\single_step_count[0]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \single_step_count[1]_i_1 
       (.I0(single_step_count[1]),
        .I1(of_piperun_for_ce),
        .I2(\Serial_Dbg_Intf.control_reg_reg_n_0_[5] ),
        .O(\single_step_count[1]_i_1_n_0 ));
  FDRE \single_step_count_reg[0] 
       (.C(Clk),
        .CE(\single_step_count[0]_i_1_n_0 ),
        .D(\single_step_count[0]_i_2_n_0 ),
        .Q(single_step_count[0]),
        .R(reset_bool_for_rst));
  FDRE \single_step_count_reg[1] 
       (.C(Clk),
        .CE(\single_step_count[0]_i_1_n_0 ),
        .D(\single_step_count[1]_i_1_n_0 ),
        .Q(single_step_count[1]),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'hAAAABBBFAAAA8880)) 
    sleep_reset_mode_i_1
       (.I0(sleep_reset_mode),
        .I1(saved_reset_mode_sleep),
        .I2(wakeup_i[0]),
        .I3(wakeup_i[1]),
        .I4(reset_bool_for_rst),
        .I5(Sleep_Out),
        .O(sleep_reset_mode_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'h20)) 
    sleep_reset_mode_i_2
       (.I0(reset_bool_for_rst),
        .I1(Reset_Mode[0]),
        .I2(Reset_Mode[1]),
        .O(sleep_reset_mode));
  FDRE sleep_reset_mode_reg
       (.C(Clk),
        .CE(1'b1),
        .D(sleep_reset_mode_i_1_n_0),
        .Q(Sleep_Out),
        .R(1'b0));
  FDRE start_dbg_exec_reg
       (.C(Clk),
        .CE(1'b1),
        .D(LOCKSTEP_Master_Out[36]),
        .Q(start_dbg_exec_reg_n_0),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'h3232320232323232)) 
    start_single_step_i_1
       (.I0(start_single_cmd),
        .I1(reset_bool_for_rst),
        .I2(start_single_step_reg_n_0),
        .I3(single_step_count[1]),
        .I4(single_step_count[0]),
        .I5(of_piperun_for_ce),
        .O(start_single_step_i_1_n_0));
  FDRE start_single_step_reg
       (.C(Clk),
        .CE(1'b1),
        .D(start_single_step_i_1_n_0),
        .Q(start_single_step_reg_n_0),
        .R(1'b0));
  design_1_microblaze_0_0_mb_sync_bit__parameterized4_29 sync_trig_ack_in_0
       (.Clk(Clk),
        .D(D[2]),
        .Dbg_Trig_Ack_In(Dbg_Trig_Ack_In[1]),
        .Dbg_Trig_In(Dbg_Trig_In[1]),
        .mb_halted_1(mb_halted_1),
        .sync_reset(reset_bool_for_rst),
        .trig_ack_in_0_synced(trig_ack_in_0_synced),
        .trig_ack_in_0_synced_1(trig_ack_in_0_synced_1),
        .trig_in_0_reg(sync_trig_ack_in_0_n_1));
  design_1_microblaze_0_0_mb_sync_bit__parameterized4_30 sync_trig_out_0
       (.Clk(Clk),
        .D(D[2]),
        .Dbg_Stop(Dbg_Stop),
        .Dbg_Trig_Ack_Out(Dbg_Trig_Ack_Out[1]),
        .Dbg_Trig_Out(Dbg_Trig_Out[1]),
        .\Performance_Debug_Control.dbg_stop_i_reg (\Performance_Debug_Control.dbg_stop_i_reg_n_0 ),
        .\Performance_Debug_Control.trig_ack_out_0_reg (sync_trig_out_0_n_1),
        .\Performance_Debug_Control.trig_out_0_synced_1_reg (sync_trig_out_0_n_2),
        .dbg_stop_1(dbg_stop_1),
        .sync_reset(reset_bool_for_rst),
        .trig_out_0_synced(trig_out_0_synced),
        .trig_out_0_synced_1(trig_out_0_synced_1));
  FDRE trig_ack_in_0_synced_1_reg
       (.C(Clk),
        .CE(1'b1),
        .D(trig_ack_in_0_synced),
        .Q(trig_ack_in_0_synced_1),
        .R(reset_bool_for_rst));
  FDRE trig_in_0_reg
       (.C(Clk),
        .CE(1'b1),
        .D(sync_trig_ack_in_0_n_1),
        .Q(Dbg_Trig_In[1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "Decode_gti" *) 
module design_1_microblaze_0_0_Decode_gti
   (of_pause_reg_0,
    D,
    \Using_FPGA.Native ,
    of_gpr_op3_rd_addr,
    of_gpr_op1_rd_addr,
    of_imm_data,
    \Using_FPGA.Native_0 ,
    ex_valid,
    ex_is_load_instr_s,
    ex_byte_access,
    ex_doublet_access,
    ex_reverse_mem_access,
    \Using_FPGA.Native_1 ,
    ex_op1_cmp_equal,
    ex_op1_cmp_equal_n,
    mem_Exception_Taken,
    Hibernate,
    Suspend,
    Sleep_Decode,
    Pause_Ack,
    ex_set_bip_reg_0,
    mem_databus_read,
    mem_databus_write,
    \Performance_Debug_Control.dbg_state_nohalt_reg ,
    mem_byte_access,
    mem_doublet_access,
    wb_byte_access,
    wb_PipeRun_i_reg_0,
    ex_cmp_op,
    ex_unsigned_op,
    ex_use_carry,
    EX_Enable_ALU,
    EX_ALU_Sel_Logic,
    ex_swap_byte_instr,
    ex_load_alu_carry_reg_0,
    ex_load_shift_carry,
    ex_move_to_MSR_instr,
    mem_sel_msr,
    wb_gpr_wr_dbg,
    wb_read_imm_reg,
    wb_read_imm_reg_1,
    wb_pc_valid,
    dbg_clean_stop,
    of_pause,
    mem_databus_access,
    wb_valid_reg_0,
    wb_Halted,
    ex_swx_access__0,
    ex_MSR_Load_LWX_SWX_C,
    SRI,
    ex_set_bip_reg_1,
    LOCKSTEP_Master_Out,
    ex_sel_alu_i_reg_0,
    EX_Fwd,
    ex_sel_alu_i_reg_1,
    ex_sel_alu_i_reg_2,
    E,
    wb_gpr_write_dbg_reg_0,
    SR,
    R,
    I1,
    M_AXI_DP_BVALID_0,
    MEM_DataBus_Write_reg_0,
    MEM_DataBus_Write_reg_1,
    MEM_DataBus_Write_reg_2,
    dbg_halt_reset_mode_reg,
    p_4_out__0,
    dbg_stop_i,
    \Serial_Dbg_Intf.control_reg_reg[8] ,
    Sleep,
    DI,
    \EX_ALU_Op_reg[0]_0 ,
    \EX_Sext_Op_reg[0]_0 ,
    in0,
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg ,
    \Performance_Debug_Control.dbg_freeze_nohalt_reg ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    \Using_FPGA.Native_5 ,
    \Using_FPGA.Native_6 ,
    \Using_FPGA.Native_7 ,
    \Using_FPGA.Native_8 ,
    \Using_FPGA.Native_9 ,
    \Using_FPGA.Native_10 ,
    \Using_FPGA.Native_11 ,
    \Using_FPGA.Native_12 ,
    \Using_FPGA.Native_13 ,
    \Using_FPGA.Native_14 ,
    \Using_FPGA.Native_15 ,
    \Using_FPGA.Native_16 ,
    \Using_FPGA.Native_17 ,
    \Using_FPGA.Native_18 ,
    \Using_FPGA.Native_19 ,
    \Using_FPGA.Native_20 ,
    \Using_FPGA.Native_21 ,
    \Using_FPGA.Native_22 ,
    \Using_FPGA.Native_23 ,
    \Using_FPGA.Native_24 ,
    \Using_FPGA.Native_25 ,
    \Using_FPGA.Native_26 ,
    \Using_FPGA.Native_27 ,
    \Using_FPGA.Native_28 ,
    \Using_FPGA.Native_29 ,
    \Using_FPGA.Native_30 ,
    \Using_FPGA.Native_31 ,
    \Using_FPGA.Native_32 ,
    \Using_FPGA.Native_33 ,
    I1_0,
    of_op1_sel_spr,
    \Using_FPGA.Native_34 ,
    \mem_pc_i_reg[0] ,
    sync_reset,
    Clk,
    I139_out,
    ex_op1_zero,
    \Using_FPGA.Native_35 ,
    MEM_DataBus_Ready,
    \Using_FPGA.Native_36 ,
    ex_exception_no_load_store_mask,
    ex_Exception_Taken,
    \MEM_DataBus_Addr_reg[0]_0 ,
    Pause,
    \Using_FPGA.Native_37 ,
    Y,
    p_231_in,
    ex_MSR_Set_SW_BIP,
    \Using_FPGA.Native_38 ,
    ex_MSR,
    \Using_FPGA.Native_39 ,
    \Using_FPGA.Native_40 ,
    if_missed_fetch_reg_0,
    if_missed_fetch_reg_1,
    MEM_Fwd,
    GPR_Op2,
    \EX_Op2_reg[0] ,
    GPR_Op3,
    GPR_Op1,
    \mem_pc_i_reg[0]_0 ,
    \data_rd_reg_reg[0] ,
    \LOCKSTEP_Out_reg[3007] ,
    \LOCKSTEP_Out_reg[3007]_0 ,
    \LOCKSTEP_Out_reg[3007]_1 ,
    \LOCKSTEP_Out_reg[3008] ,
    \LOCKSTEP_Out_reg[3009] ,
    \LOCKSTEP_Out_reg[3010] ,
    \LOCKSTEP_Out_reg[3011] ,
    \LOCKSTEP_Out_reg[3012] ,
    \LOCKSTEP_Out_reg[3013] ,
    \LOCKSTEP_Out_reg[3014] ,
    \LOCKSTEP_Out_reg[3015] ,
    \LOCKSTEP_Out_reg[3016] ,
    \LOCKSTEP_Out_reg[3017] ,
    \LOCKSTEP_Out_reg[3018] ,
    \LOCKSTEP_Out_reg[3019] ,
    \LOCKSTEP_Out_reg[3020] ,
    \LOCKSTEP_Out_reg[3021] ,
    \LOCKSTEP_Out_reg[3022] ,
    M_AXI_DP_BVALID,
    active_access,
    M_AXI_DP_RVALID,
    M_AXI_DP_WREADY,
    M_AXI_DP_AWREADY,
    M_AXI_DP_ARREADY,
    Reset_Mode,
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ,
    active_access_reg,
    Q,
    \Using_FPGA.Native_41 ,
    IReady,
    DReady,
    DWait,
    active_access_d1,
    Sleep_Out,
    wakeup_i,
    wb_databus_steered_read_data,
    ex_databus_addr,
    swap_result,
    \Using_FPGA.Native_42 ,
    out,
    \Using_FPGA.Native_43 ,
    swap_result_reg,
    \MEM_DataBus_Write_Data_reg[0] ,
    exception_reg,
    in,
    lopt,
    lopt_1,
    lopt_2);
  output of_pause_reg_0;
  output [31:0]D;
  output [0:0]\Using_FPGA.Native ;
  output [0:4]of_gpr_op3_rd_addr;
  output [0:4]of_gpr_op1_rd_addr;
  output [0:15]of_imm_data;
  output \Using_FPGA.Native_0 ;
  output ex_valid;
  output ex_is_load_instr_s;
  output ex_byte_access;
  output ex_doublet_access;
  output ex_reverse_mem_access;
  output \Using_FPGA.Native_1 ;
  output ex_op1_cmp_equal;
  output ex_op1_cmp_equal_n;
  output mem_Exception_Taken;
  output Hibernate;
  output Suspend;
  output Sleep_Decode;
  output Pause_Ack;
  output ex_set_bip_reg_0;
  output mem_databus_read;
  output mem_databus_write;
  output [159:0]\Performance_Debug_Control.dbg_state_nohalt_reg ;
  output mem_byte_access;
  output mem_doublet_access;
  output wb_byte_access;
  output [0:0]wb_PipeRun_i_reg_0;
  output ex_cmp_op;
  output ex_unsigned_op;
  output ex_use_carry;
  output EX_Enable_ALU;
  output EX_ALU_Sel_Logic;
  output ex_swap_byte_instr;
  output ex_load_alu_carry_reg_0;
  output ex_load_shift_carry;
  output ex_move_to_MSR_instr;
  output mem_sel_msr;
  output wb_gpr_wr_dbg;
  output wb_read_imm_reg;
  output wb_read_imm_reg_1;
  output wb_pc_valid;
  output dbg_clean_stop;
  output of_pause;
  output mem_databus_access;
  output wb_valid_reg_0;
  output wb_Halted;
  output ex_swx_access__0;
  output ex_MSR_Load_LWX_SWX_C;
  output SRI;
  output ex_set_bip_reg_1;
  output [2:0]LOCKSTEP_Master_Out;
  output [31:0]ex_sel_alu_i_reg_0;
  output [0:31]EX_Fwd;
  output [31:0]ex_sel_alu_i_reg_1;
  output [31:0]ex_sel_alu_i_reg_2;
  output [0:0]E;
  output [23:0]wb_gpr_write_dbg_reg_0;
  output [0:0]SR;
  output R;
  output I1;
  output M_AXI_DP_BVALID_0;
  output MEM_DataBus_Write_reg_0;
  output MEM_DataBus_Write_reg_1;
  output MEM_DataBus_Write_reg_2;
  output dbg_halt_reset_mode_reg;
  output p_4_out__0;
  output dbg_stop_i;
  output \Serial_Dbg_Intf.control_reg_reg[8] ;
  output Sleep;
  output DI;
  output [1:0]\EX_ALU_Op_reg[0]_0 ;
  output [1:0]\EX_Sext_Op_reg[0]_0 ;
  output in0;
  output \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg ;
  output \Performance_Debug_Control.dbg_freeze_nohalt_reg ;
  output \Using_FPGA.Native_2 ;
  output \Using_FPGA.Native_3 ;
  output \Using_FPGA.Native_4 ;
  output \Using_FPGA.Native_5 ;
  output \Using_FPGA.Native_6 ;
  output \Using_FPGA.Native_7 ;
  output \Using_FPGA.Native_8 ;
  output \Using_FPGA.Native_9 ;
  output \Using_FPGA.Native_10 ;
  output \Using_FPGA.Native_11 ;
  output \Using_FPGA.Native_12 ;
  output \Using_FPGA.Native_13 ;
  output \Using_FPGA.Native_14 ;
  output \Using_FPGA.Native_15 ;
  output \Using_FPGA.Native_16 ;
  output \Using_FPGA.Native_17 ;
  output \Using_FPGA.Native_18 ;
  output \Using_FPGA.Native_19 ;
  output \Using_FPGA.Native_20 ;
  output \Using_FPGA.Native_21 ;
  output \Using_FPGA.Native_22 ;
  output \Using_FPGA.Native_23 ;
  output \Using_FPGA.Native_24 ;
  output \Using_FPGA.Native_25 ;
  output \Using_FPGA.Native_26 ;
  output \Using_FPGA.Native_27 ;
  output \Using_FPGA.Native_28 ;
  output \Using_FPGA.Native_29 ;
  output \Using_FPGA.Native_30 ;
  output \Using_FPGA.Native_31 ;
  output \Using_FPGA.Native_32 ;
  output \Using_FPGA.Native_33 ;
  output I1_0;
  output of_op1_sel_spr;
  output [0:0]\Using_FPGA.Native_34 ;
  output [31:0]\mem_pc_i_reg[0] ;
  input sync_reset;
  input Clk;
  input I139_out;
  input ex_op1_zero;
  input \Using_FPGA.Native_35 ;
  input MEM_DataBus_Ready;
  input \Using_FPGA.Native_36 ;
  input ex_exception_no_load_store_mask;
  input ex_Exception_Taken;
  input [70:0]\MEM_DataBus_Addr_reg[0]_0 ;
  input Pause;
  input [0:0]\Using_FPGA.Native_37 ;
  input [0:31]Y;
  input p_231_in;
  input ex_MSR_Set_SW_BIP;
  input \Using_FPGA.Native_38 ;
  input [2:0]ex_MSR;
  input \Using_FPGA.Native_39 ;
  input \Using_FPGA.Native_40 ;
  input if_missed_fetch_reg_0;
  input if_missed_fetch_reg_1;
  input [0:31]MEM_Fwd;
  input [0:31]GPR_Op2;
  input [15:0]\EX_Op2_reg[0] ;
  input [0:31]GPR_Op3;
  input [0:31]GPR_Op1;
  input \mem_pc_i_reg[0]_0 ;
  input \data_rd_reg_reg[0] ;
  input [23:0]\LOCKSTEP_Out_reg[3007] ;
  input \LOCKSTEP_Out_reg[3007]_0 ;
  input [23:0]\LOCKSTEP_Out_reg[3007]_1 ;
  input \LOCKSTEP_Out_reg[3008] ;
  input \LOCKSTEP_Out_reg[3009] ;
  input \LOCKSTEP_Out_reg[3010] ;
  input \LOCKSTEP_Out_reg[3011] ;
  input \LOCKSTEP_Out_reg[3012] ;
  input \LOCKSTEP_Out_reg[3013] ;
  input \LOCKSTEP_Out_reg[3014] ;
  input \LOCKSTEP_Out_reg[3015] ;
  input \LOCKSTEP_Out_reg[3016] ;
  input \LOCKSTEP_Out_reg[3017] ;
  input \LOCKSTEP_Out_reg[3018] ;
  input \LOCKSTEP_Out_reg[3019] ;
  input \LOCKSTEP_Out_reg[3020] ;
  input \LOCKSTEP_Out_reg[3021] ;
  input \LOCKSTEP_Out_reg[3022] ;
  input M_AXI_DP_BVALID;
  input active_access;
  input M_AXI_DP_RVALID;
  input M_AXI_DP_WREADY;
  input M_AXI_DP_AWREADY;
  input M_AXI_DP_ARREADY;
  input [0:1]Reset_Mode;
  input \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ;
  input active_access_reg;
  input [0:0]Q;
  input \Using_FPGA.Native_41 ;
  input IReady;
  input DReady;
  input DWait;
  input active_access_d1;
  input Sleep_Out;
  input [0:1]wakeup_i;
  input [7:0]wb_databus_steered_read_data;
  input [1:0]ex_databus_addr;
  input [23:0]swap_result;
  input [31:0]\Using_FPGA.Native_42 ;
  input out;
  input \Using_FPGA.Native_43 ;
  input [0:7]swap_result_reg;
  input [31:0]\MEM_DataBus_Write_Data_reg[0] ;
  input [0:0]exception_reg;
  input [0:0]in;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire A;
  wire Clk;
  wire [31:0]D;
  wire D224_out;
  wire DI;
  wire DReady;
  wire DWait;
  wire \Data_Flow_I/Shift_Logic_Module_I/O ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O0_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O10_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O11_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O12_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O13_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O14_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O15_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O17_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O18_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O19_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O1_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O20_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O21_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O22_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O23_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O24_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O26_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O27_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O28_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O29_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O2_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O30_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O31_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O3_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O4_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O5_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O6_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O7_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O8_out ;
  wire \Data_Flow_I/Shift_Logic_Module_I/O9_out ;
  wire Dbg_Clean_Stop0;
  wire [0:0]E;
  wire [1:0]\EX_ALU_Op_reg[0]_0 ;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [0:31]EX_Fwd;
  wire EX_Is_Div_Instr;
  wire EX_MBAR_Stall__1;
  wire [15:0]\EX_Op2_reg[0] ;
  wire [1:0]\EX_Sext_Op_reg[0]_0 ;
  wire [0:31]GPR_Op1;
  wire [0:31]GPR_Op2;
  wire [0:31]GPR_Op3;
  wire Hibernate;
  wire I0;
  wire I1;
  wire I139_out;
  wire I1_0;
  wire I2;
  wire I4;
  wire I5;
  wire IB_Ready;
  wire IF_PC_Write;
  wire IReady;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [23:0]\LOCKSTEP_Out_reg[3007] ;
  wire \LOCKSTEP_Out_reg[3007]_0 ;
  wire [23:0]\LOCKSTEP_Out_reg[3007]_1 ;
  wire \LOCKSTEP_Out_reg[3008] ;
  wire \LOCKSTEP_Out_reg[3009] ;
  wire \LOCKSTEP_Out_reg[3010] ;
  wire \LOCKSTEP_Out_reg[3011] ;
  wire \LOCKSTEP_Out_reg[3012] ;
  wire \LOCKSTEP_Out_reg[3013] ;
  wire \LOCKSTEP_Out_reg[3014] ;
  wire \LOCKSTEP_Out_reg[3015] ;
  wire \LOCKSTEP_Out_reg[3016] ;
  wire \LOCKSTEP_Out_reg[3017] ;
  wire \LOCKSTEP_Out_reg[3018] ;
  wire \LOCKSTEP_Out_reg[3019] ;
  wire \LOCKSTEP_Out_reg[3020] ;
  wire \LOCKSTEP_Out_reg[3021] ;
  wire \LOCKSTEP_Out_reg[3022] ;
  wire [70:0]\MEM_DataBus_Addr_reg[0]_0 ;
  wire MEM_DataBus_Ready;
  wire [31:0]\MEM_DataBus_Write_Data_reg[0] ;
  wire MEM_DataBus_Write_reg_0;
  wire MEM_DataBus_Write_reg_1;
  wire MEM_DataBus_Write_reg_2;
  wire [0:31]MEM_Fwd;
  wire M_AXI_DP_ARREADY;
  wire M_AXI_DP_AWREADY;
  wire M_AXI_DP_BVALID;
  wire M_AXI_DP_BVALID_0;
  wire M_AXI_DP_RVALID;
  wire M_AXI_DP_WREADY;
  wire O;
  wire O31_out;
  wire O33_out;
  wire O35_out;
  wire O37_out;
  wire O39_out;
  wire O41_out;
  wire O43_out;
  wire O45_out;
  wire O47_out;
  wire O49_out;
  wire O51_out;
  wire O53_out;
  wire O55_out;
  wire O56_out;
  wire O57_out;
  wire O59_out;
  wire O61_out;
  wire O63_out;
  wire O65_out;
  wire O67_out;
  wire O69_out;
  wire O71_out;
  wire O73_out;
  wire O75_out;
  wire O77_out;
  wire O79_out;
  wire O81_out;
  wire O83_out;
  wire O85_out;
  wire O87_out;
  wire PC_Module_I_n_35;
  wire Pause;
  wire Pause_Ack;
  wire Pause_Ack0;
  wire \Performance_Debug_Control.dbg_freeze_nohalt_reg ;
  wire [159:0]\Performance_Debug_Control.dbg_state_nohalt_reg ;
  wire \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg ;
  wire \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ;
  wire PreFetch_Buffer_I1_n_169;
  wire PreFetch_Buffer_I1_n_173;
  wire PreFetch_Buffer_I1_n_176;
  wire PreFetch_Buffer_I1_n_177;
  wire PreFetch_Buffer_I1_n_178;
  wire PreFetch_Buffer_I1_n_179;
  wire PreFetch_Buffer_I1_n_182;
  wire PreFetch_Buffer_I1_n_183;
  wire PreFetch_Buffer_I1_n_184;
  wire PreFetch_Buffer_I1_n_185;
  wire PreFetch_Buffer_I1_n_186;
  wire PreFetch_Buffer_I1_n_187;
  wire PreFetch_Buffer_I1_n_188;
  wire PreFetch_Buffer_I1_n_189;
  wire PreFetch_Buffer_I1_n_190;
  wire PreFetch_Buffer_I1_n_191;
  wire PreFetch_Buffer_I1_n_193;
  wire PreFetch_Buffer_I1_n_194;
  wire PreFetch_Buffer_I1_n_195;
  wire PreFetch_Buffer_I1_n_3;
  wire PreFetch_Buffer_I1_n_48;
  wire PreFetch_Buffer_I1_n_49;
  wire PreFetch_Buffer_I1_n_50;
  wire PreFetch_Buffer_I1_n_56;
  wire PreFetch_Buffer_I1_n_59;
  wire PreFetch_Buffer_I1_n_64;
  wire PreFetch_Buffer_I1_n_65;
  wire PreFetch_Buffer_I1_n_66;
  wire [0:0]Q;
  wire R;
  wire [0:1]Reset_Mode;
  wire [0:0]SR;
  wire SRI;
  wire \Serial_Dbg_Intf.control_reg_reg[8] ;
  wire Sleep;
  wire Sleep_Decode;
  wire Sleep_Out;
  wire Suspend;
  wire \Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1 ;
  wire \Use_MuxCy[11].OF_Piperun_Stage_n_1 ;
  wire \Use_MuxCy[11].OF_Piperun_Stage_n_2 ;
  wire \Use_MuxCy[11].OF_Piperun_Stage_n_3 ;
  wire \Use_MuxCy[11].OF_Piperun_Stage_n_4 ;
  wire \Use_MuxCy[3].OF_Piperun_Stage_n_1 ;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_10 ;
  wire \Using_FPGA.Native_11 ;
  wire \Using_FPGA.Native_12 ;
  wire \Using_FPGA.Native_13 ;
  wire \Using_FPGA.Native_14 ;
  wire \Using_FPGA.Native_15 ;
  wire \Using_FPGA.Native_16 ;
  wire \Using_FPGA.Native_17 ;
  wire \Using_FPGA.Native_18 ;
  wire \Using_FPGA.Native_19 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_20 ;
  wire \Using_FPGA.Native_21 ;
  wire \Using_FPGA.Native_22 ;
  wire \Using_FPGA.Native_23 ;
  wire \Using_FPGA.Native_24 ;
  wire \Using_FPGA.Native_25 ;
  wire \Using_FPGA.Native_26 ;
  wire \Using_FPGA.Native_27 ;
  wire \Using_FPGA.Native_28 ;
  wire \Using_FPGA.Native_29 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_30 ;
  wire \Using_FPGA.Native_31 ;
  wire \Using_FPGA.Native_32 ;
  wire \Using_FPGA.Native_33 ;
  wire [0:0]\Using_FPGA.Native_34 ;
  wire \Using_FPGA.Native_35 ;
  wire \Using_FPGA.Native_36 ;
  wire [0:0]\Using_FPGA.Native_37 ;
  wire \Using_FPGA.Native_38 ;
  wire \Using_FPGA.Native_39 ;
  wire \Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_40 ;
  wire \Using_FPGA.Native_41 ;
  wire [31:0]\Using_FPGA.Native_42 ;
  wire \Using_FPGA.Native_43 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_7 ;
  wire \Using_FPGA.Native_8 ;
  wire \Using_FPGA.Native_9 ;
  wire \Using_FPGA.Native_i_5__1_n_0 ;
  wire \Using_FPGA_2.ex_is_load_instr_Inst_n_3 ;
  wire \Using_FPGA_2.ex_is_lwx_instr_Inst_n_1 ;
  wire \Using_FPGA_2.ex_is_swx_instr_Inst_n_1 ;
  wire \Using_FPGA_2.ex_is_swx_instr_Inst_n_4 ;
  wire \Using_FPGA_3.of_clear_MSR_BIP_hold_Inst_n_0 ;
  wire \Using_FPGA_4.of_read_ex_write_op2_conflict_INST2_n_0 ;
  wire \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0 ;
  wire \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0 ;
  wire \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0 ;
  wire \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0 ;
  wire [0:31]Y;
  wire active_access;
  wire active_access_d1;
  wire active_access_reg;
  wire active_wakeup;
  wire active_wakeup0;
  wire \data_rd_reg_reg[0] ;
  wire dbg_clean_stop;
  wire dbg_halt_reset_mode_reg;
  wire dbg_stop_i;
  wire ex_Enable_Sext_Shift;
  wire ex_Exception_Taken;
  wire [2:0]ex_MSR;
  wire ex_MSR_Load_LWX_SWX_C;
  wire ex_MSR_Set_SW_BIP;
  wire ex_Sel_SPR_BTR;
  wire ex_Sel_SPR_EAR;
  wire ex_Sel_SPR_EDR;
  wire ex_Sel_SPR_ESR;
  wire ex_Sel_SPR_FSR;
  wire ex_Sel_SPR_PVR;
  wire ex_Sel_SPR_SHR;
  wire ex_Sel_SPR_SLR;
  (* RTL_KEEP = "true" *) wire ex_Write_DCache_decode_cmb;
  wire ex_Write_ICache_i;
  (* RTL_KEEP = "true" *) wire ex_Write_ICache_i_cmb;
  wire ex_branch_with_delayslot;
  wire ex_byte_access;
  wire ex_cmp_op;
  wire [1:0]ex_databus_addr;
  wire ex_delayslot_Instr;
  wire ex_delayslot_Instr0;
  wire ex_doublet_access;
  wire ex_enable_sext_shift_i0;
  wire ex_exception_no_load_store_mask;
  wire ex_first_cycle;
  wire \ex_gpr_write_addr_reg_n_0_[0] ;
  wire \ex_gpr_write_addr_reg_n_0_[4] ;
  wire ex_gpr_write_dbg__0;
  wire ex_gpr_write_reg_n_0;
  wire ex_hibernate_i_i_1_n_0;
  wire \ex_instr_reg_n_0_[0] ;
  wire \ex_instr_reg_n_0_[10] ;
  wire \ex_instr_reg_n_0_[11] ;
  wire \ex_instr_reg_n_0_[12] ;
  wire \ex_instr_reg_n_0_[13] ;
  wire \ex_instr_reg_n_0_[14] ;
  wire \ex_instr_reg_n_0_[15] ;
  wire \ex_instr_reg_n_0_[16] ;
  wire \ex_instr_reg_n_0_[17] ;
  wire \ex_instr_reg_n_0_[18] ;
  wire \ex_instr_reg_n_0_[19] ;
  wire \ex_instr_reg_n_0_[1] ;
  wire \ex_instr_reg_n_0_[20] ;
  wire \ex_instr_reg_n_0_[21] ;
  wire \ex_instr_reg_n_0_[22] ;
  wire \ex_instr_reg_n_0_[23] ;
  wire \ex_instr_reg_n_0_[24] ;
  wire \ex_instr_reg_n_0_[25] ;
  wire \ex_instr_reg_n_0_[26] ;
  wire \ex_instr_reg_n_0_[27] ;
  wire \ex_instr_reg_n_0_[28] ;
  wire \ex_instr_reg_n_0_[29] ;
  wire \ex_instr_reg_n_0_[2] ;
  wire \ex_instr_reg_n_0_[30] ;
  wire \ex_instr_reg_n_0_[31] ;
  wire \ex_instr_reg_n_0_[3] ;
  wire \ex_instr_reg_n_0_[4] ;
  wire \ex_instr_reg_n_0_[5] ;
  wire \ex_instr_reg_n_0_[8] ;
  wire \ex_instr_reg_n_0_[9] ;
  wire ex_is_load_instr_s;
  wire ex_is_multi_instr2;
  wire ex_is_multi_or_load_instr;
  wire ex_is_multi_or_load_instr0;
  wire ex_is_swx_instr_s;
  wire ex_jump;
  wire ex_jump_hold;
  wire ex_jump_nodelay;
  wire ex_jump_q;
  wire ex_load_alu_carry_reg_0;
  wire ex_load_shift_carry;
  wire ex_load_shift_carry0;
  wire ex_load_store_instr_s;
  wire ex_mbar_decode;
  (* RTL_KEEP = "true" *) wire ex_mbar_decode_cmb;
  wire ex_mbar_is_sleep;
  (* RTL_KEEP = "true" *) wire ex_mbar_is_sleep_cmb;
  wire ex_mbar_sleep;
  wire ex_mbar_sleep_i_1_n_0;
  wire ex_mbar_stall_no_sleep_1;
  wire ex_mbar_stall_no_sleep_10;
  wire ex_mbar_stall_no_sleep__0;
  wire ex_mfsmsr_i;
  wire ex_move_to_MSR_instr;
  wire ex_move_to_MSR_instr93_out;
  wire ex_op1_cmp_eq1;
  wire ex_op1_cmp_eq_n5_out;
  wire ex_op1_cmp_equal;
  wire ex_op1_cmp_equal_n;
  wire ex_op1_zero;
  wire [0:5]ex_opcode;
  wire ex_read_imm_reg;
  wire ex_read_imm_reg_1;
  wire ex_read_imm_reg_i_1_n_0;
  wire ex_reservation;
  wire ex_reverse_mem_access;
  wire ex_sel_alu;
  wire ex_sel_alu_i0;
  wire [31:0]ex_sel_alu_i_reg_0;
  wire [31:0]ex_sel_alu_i_reg_1;
  wire [31:0]ex_sel_alu_i_reg_2;
  wire ex_set_bip;
  wire ex_set_bip_reg_0;
  wire ex_set_bip_reg_1;
  wire [0:0]ex_shift_logic_result;
  wire [0:1]ex_shift_op;
  wire ex_sleep_i0;
  wire ex_sleep_i_i_1_n_0;
  wire ex_suspend_i0;
  wire ex_swap_byte_instr;
  wire ex_swap_instr;
  wire ex_swx_access__0;
  wire ex_unsigned_op;
  wire ex_use_carry;
  wire ex_valid;
  (* RTL_KEEP = "true" *) wire ex_valid_jump;
  wire ex_write_dcache_instr;
  wire [0:0]exception_reg;
  wire flush_pipe;
  wire force12_out;
  wire force_Val10_out;
  wire if_fetch_for_timing_optimization1;
  wire if_fetch_in_progress;
  wire if_fetch_in_progress_i_1_n_0;
  (* RTL_KEEP = "true" *) wire if_fetch_without_full_or_jump;
  wire if_missed_fetch;
  wire if_missed_fetch_reg_0;
  wire if_missed_fetch_reg_1;
  wire if_pc_incr_carry0;
  wire if_pc_incr_carry1;
  wire if_pc_incr_carry3;
  wire [1:1]if_pre_buffer_addr;
  wire [0:4]if_sel_input;
  wire [0:0]in;
  wire in0;
  wire jump_logic_I1_n_42;
  wire jump_logic_I1_n_6;
  wire jump_logic_I1_n_8;
  wire keep_jump_taken_with_ds;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_27;
  wire lopt_28;
  wire lopt_29;
  wire lopt_3;
  wire lopt_30;
  wire lopt_31;
  wire lopt_32;
  wire lopt_33;
  wire lopt_34;
  wire lopt_35;
  wire lopt_36;
  wire lopt_37;
  wire lopt_38;
  wire lopt_39;
  wire lopt_4;
  wire lopt_40;
  wire lopt_41;
  wire lopt_42;
  wire lopt_43;
  wire lopt_44;
  wire lopt_45;
  wire lopt_46;
  wire lopt_47;
  wire lopt_48;
  wire lopt_49;
  wire lopt_5;
  wire lopt_50;
  wire lopt_51;
  wire lopt_52;
  wire lopt_53;
  wire lopt_54;
  wire lopt_55;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire mem_Exception_Taken;
  wire mem_PipeRun_carry_and_n_1;
  wire mem_PipeRun_carry_and_n_2;
  wire mem_Sel_MEM_Res;
  wire mem_Write_DCache;
  wire mem_Write_DCache_i_1_n_0;
  wire mem_byte_access;
  wire mem_databus_access;
  wire mem_databus_read;
  wire mem_databus_write;
  wire mem_delayslot_instr;
  wire mem_doublet_access;
  wire mem_exception_from_ex;
  wire [28:31]mem_exception_kind;
  wire mem_gpr_write;
  wire [0:4]mem_gpr_write_addr;
  wire mem_gpr_write_dbg;
  wire [0:31]mem_instr;
  wire mem_is_multi_or_load_instr;
  wire mem_is_multi_or_load_instr0;
  wire mem_jump_taken;
  wire mem_jump_taken0;
  wire mem_load_store_access;
  wire mem_load_store_access0;
  wire [31:0]\mem_pc_i_reg[0] ;
  wire \mem_pc_i_reg[0]_0 ;
  wire mem_read_imm_reg;
  wire mem_read_imm_reg_1;
  wire mem_sel_msr;
  wire mem_valid_instr;
  wire mem_wait_on_ready_N;
  (* RTL_KEEP = "true" *) wire [0:3]of_PVR_Select;
  wire of_PipeRun_carry_1;
  wire of_PipeRun_carry_10;
  wire of_PipeRun_carry_2;
  wire of_PipeRun_carry_3;
  wire of_PipeRun_carry_4;
  wire of_PipeRun_carry_5;
  wire of_PipeRun_carry_6;
  wire of_PipeRun_carry_7;
  wire of_PipeRun_carry_9;
  (* DIRECT_ENABLE *) wire of_PipeRun_for_ce;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_BTR;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_EAR;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_EDR;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_ESR;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_FSR;
  wire of_Sel_SPR_MSR1;
  wire of_Sel_SPR_MSR88_out;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_PVR;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_SHR;
  (* RTL_KEEP = "true" *) wire of_Sel_SPR_SLR;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [0:15]of_imm_data;
  wire [0:5]of_instr;
  wire of_next_ex_valid;
  wire of_op1_sel_spr;
  wire of_pause;
  wire [0:10]of_predecode;
  wire of_read_ex_write_op2_conflict_part1;
  wire of_read_ex_write_op3_conflict_part1;
  wire of_read_imm_reg_ii;
  wire of_read_imm_reg_ii_i_2_n_0;
  wire of_read_mem_write_op1_conflict_part2;
  wire of_read_mem_write_op2_conflict_part1;
  wire of_read_mem_write_op3_conflict_part1;
  wire of_use_op2_s;
  wire of_valid;
  wire out;
  wire p_0_in123_in;
  wire p_1_in;
  wire p_1_in124_in;
  wire p_1_in3_in;
  wire p_213_in;
  wire p_216_in;
  wire p_227_in;
  wire p_231_in;
  wire p_232_in;
  wire p_2_in;
  wire p_4_out__0;
  wire p_9_in;
  (* DIRECT_RESET *) wire reset_bool_for_rst;
  wire [23:0]swap_result;
  wire [0:7]swap_result_reg;
  wire use_Reg_Neg_DI1_out;
  wire use_Reg_Neg_S3_out;
  wire [0:1]wakeup_i;
  wire wb_Halted;
  wire [0:0]wb_PipeRun_i_reg_0;
  wire wb_byte_access;
  wire [7:0]wb_databus_steered_read_data;
  wire wb_doublet_access;
  wire wb_exception;
  wire wb_gpr_wr_dbg;
  wire wb_gpr_write_dbg0;
  wire [23:0]wb_gpr_write_dbg_reg_0;
  wire wb_gpr_write_i;
  wire wb_gpr_write_i0;
  wire wb_pc_valid;
  wire wb_read_imm_reg;
  wire wb_read_imm_reg_1;
  wire wb_reset;
  wire wb_valid_reg_0;

  assign of_pause_reg_0 = of_PipeRun_for_ce;
  assign reset_bool_for_rst = sync_reset;
  FDRE Dbg_Clean_Stop_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(Dbg_Clean_Stop0),
        .Q(dbg_clean_stop),
        .R(reset_bool_for_rst));
  FDRE \EX_ALU_Op_reg[0] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_64),
        .Q(\EX_ALU_Op_reg[0]_0 [1]),
        .R(reset_bool_for_rst));
  FDRE \EX_ALU_Op_reg[1] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_65),
        .Q(\EX_ALU_Op_reg[0]_0 [0]),
        .R(reset_bool_for_rst));
  FDRE EX_CMP_Op_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_186),
        .Q(ex_cmp_op),
        .R(reset_bool_for_rst));
  FDRE EX_SWAP_BYTE_Instr_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(p_2_in),
        .Q(ex_swap_byte_instr),
        .R(reset_bool_for_rst));
  FDRE EX_SWAP_Instr_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_169),
        .Q(ex_swap_instr),
        .R(reset_bool_for_rst));
  FDRE \EX_Sext_Op_reg[0] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_176),
        .Q(\EX_Sext_Op_reg[0]_0 [1]),
        .R(reset_bool_for_rst));
  FDRE \EX_Sext_Op_reg[1] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_177),
        .Q(\EX_Sext_Op_reg[0]_0 [0]),
        .R(reset_bool_for_rst));
  FDRE \EX_Shift_Op_reg[0] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[9]),
        .Q(ex_shift_op[0]),
        .R(reset_bool_for_rst));
  FDRE \EX_Shift_Op_reg[1] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[10]),
        .Q(ex_shift_op[1]),
        .R(reset_bool_for_rst));
  FDRE EX_Unsigned_Op_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_187),
        .Q(ex_unsigned_op),
        .R(reset_bool_for_rst));
  FDRE EX_Use_Carry_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_188),
        .Q(ex_use_carry),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    IFetch_INST_0_i_1
       (.I0(reset_bool_for_rst),
        .I1(ex_mbar_stall_no_sleep__0),
        .I2(ex_mbar_sleep),
        .I3(if_missed_fetch_reg_0),
        .I4(wb_Halted),
        .I5(if_missed_fetch_reg_1),
        .O(if_fetch_without_full_or_jump));
  LUT5 #(
    .INIT(32'h54000000)) 
    IFetch_INST_0_i_2
       (.I0(ex_jump_hold),
        .I1(ex_mbar_stall_no_sleep_1),
        .I2(ex_first_cycle),
        .I3(p_231_in),
        .I4(ex_mbar_decode),
        .O(ex_mbar_stall_no_sleep__0));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \LOCKSTEP_Master_Out[1]_INST_0 
       (.I0(mem_databus_access),
        .I1(active_access_reg),
        .O(LOCKSTEP_Master_Out[2]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT5 #(
    .INIT(32'hFFFFEAAA)) 
    \LOCKSTEP_Master_Out[5]_INST_0 
       (.I0(if_missed_fetch_reg_1),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I3(wb_exception),
        .I4(if_missed_fetch_reg_0),
        .O(LOCKSTEP_Master_Out[1]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    \LOCKSTEP_Master_Out[7]_INST_0 
       (.I0(\mem_pc_i_reg[0]_0 ),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .O(LOCKSTEP_Master_Out[0]));
  FDRE MEM_DataBus_Access_reg
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA_2.ex_is_swx_instr_Inst_n_1 ),
        .Q(mem_databus_access),
        .R(1'b0));
  FDRE \MEM_DataBus_Addr_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [70]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [99]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[10] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [60]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [89]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[11] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [59]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [88]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[12] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [58]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [87]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[13] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [57]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [86]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[14] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [56]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [85]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[15] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [55]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [84]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[16] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [54]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [83]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[17] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [53]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [82]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[18] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [52]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [81]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[19] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [51]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [80]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [69]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [98]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[20] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [50]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [79]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[21] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [49]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [78]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[22] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [48]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [77]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[23] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [47]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [76]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[24] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [46]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [75]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[25] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [45]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [74]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[26] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [44]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [73]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[27] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [43]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [72]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[28] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [42]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [71]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[29] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [41]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [70]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [68]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [97]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[30] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [40]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [69]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[31] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [39]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [68]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [67]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [96]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[4] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [66]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [95]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[5] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [65]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [94]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[6] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [64]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [93]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[7] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [63]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [92]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[8] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [62]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [91]),
        .R(reset_bool_for_rst));
  FDRE \MEM_DataBus_Addr_reg[9] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [61]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [90]),
        .R(reset_bool_for_rst));
  FDRE MEM_DataBus_Read_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\MEM_DataBus_Addr_reg[0]_0 [38]),
        .Q(mem_databus_read),
        .R(reset_bool_for_rst));
  FDRE MEM_DataBus_Write_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Performance_Debug_Control.dbg_state_nohalt_reg [100]),
        .Q(mem_databus_write),
        .R(reset_bool_for_rst));
  FDSE MEM_Sel_MEM_Res_I_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA_2.ex_is_load_instr_Inst_n_3 ),
        .Q(mem_Sel_MEM_Res),
        .S(reset_bool_for_rst));
  LUT5 #(
    .INIT(32'h00000F22)) 
    M_AXI_DP_ARVALID_i_i_1
       (.I0(\Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1 ),
        .I1(mem_databus_write),
        .I2(M_AXI_DP_ARREADY),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [35]),
        .I4(reset_bool_for_rst),
        .O(MEM_DataBus_Write_reg_2));
  LUT5 #(
    .INIT(32'h00000F88)) 
    M_AXI_DP_AWVALID_i_i_1
       (.I0(\Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1 ),
        .I1(mem_databus_write),
        .I2(M_AXI_DP_AWREADY),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [37]),
        .I4(reset_bool_for_rst),
        .O(MEM_DataBus_Write_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    M_AXI_DP_AWVALID_i_i_2
       (.I0(mem_databus_access),
        .I1(DReady),
        .I2(DWait),
        .I3(active_access_d1),
        .O(\Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1 ));
  LUT5 #(
    .INIT(32'h00000F88)) 
    M_AXI_DP_WVALID_i_i_1
       (.I0(\Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1 ),
        .I1(mem_databus_write),
        .I2(M_AXI_DP_WREADY),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [36]),
        .I4(reset_bool_for_rst),
        .O(MEM_DataBus_Write_reg_0));
  design_1_microblaze_0_0_PC_Module_gti PC_Module_I
       (.CI(if_pc_incr_carry3),
        .Clk(Clk),
        .D(D),
        .E(\Use_MuxCy[3].OF_Piperun_Stage_n_1 ),
        .IB_Ready(IB_Ready),
        .IReady(IReady),
        .O(O87_out),
        .O56_out(O56_out),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [3:2]),
        .\Using_FPGA.Native (\Using_FPGA.Native ),
        .\Using_FPGA.Native_0 (PreFetch_Buffer_I1_n_3),
        .ex_jump_nodelay_reg(\Using_FPGA.Native_41 ),
        .ex_jump_nodelay_reg_0(\mem_pc_i_reg[0]_0 ),
        .\ex_pc_i_reg[31]_0 (of_PipeRun_for_ce),
        .\if_pc_reg[0]_0 (IF_PC_Write),
        .\if_pc_reg[0]_1 (\Performance_Debug_Control.dbg_state_nohalt_reg [156:125]),
        .\if_pc_reg[10]_0 (O49_out),
        .\if_pc_reg[11]_0 (O51_out),
        .\if_pc_reg[12]_0 (O53_out),
        .\if_pc_reg[13]_0 (O55_out),
        .\if_pc_reg[14]_0 (O57_out),
        .\if_pc_reg[15]_0 (O59_out),
        .\if_pc_reg[16]_0 (O61_out),
        .\if_pc_reg[17]_0 (O63_out),
        .\if_pc_reg[18]_0 (O65_out),
        .\if_pc_reg[19]_0 (O67_out),
        .\if_pc_reg[1]_0 (O31_out),
        .\if_pc_reg[20]_0 (O69_out),
        .\if_pc_reg[21]_0 (O71_out),
        .\if_pc_reg[22]_0 (O73_out),
        .\if_pc_reg[23]_0 (O75_out),
        .\if_pc_reg[24]_0 (O77_out),
        .\if_pc_reg[25]_0 (O79_out),
        .\if_pc_reg[26]_0 (O81_out),
        .\if_pc_reg[27]_0 (O83_out),
        .\if_pc_reg[28]_0 (O85_out),
        .\if_pc_reg[2]_0 (O33_out),
        .\if_pc_reg[30]_0 ({p_1_in3_in,PC_Module_I_n_35}),
        .\if_pc_reg[3]_0 (O35_out),
        .\if_pc_reg[4]_0 (O37_out),
        .\if_pc_reg[5]_0 (O39_out),
        .\if_pc_reg[6]_0 (O41_out),
        .\if_pc_reg[7]_0 (O43_out),
        .\if_pc_reg[8]_0 (O45_out),
        .\if_pc_reg[9]_0 (O47_out),
        .if_pre_buffer_addr(if_pre_buffer_addr),
        .if_sel_input({if_sel_input[0],if_sel_input[4]}),
        .lopt(lopt_7),
        .lopt_1(lopt_8),
        .lopt_10(lopt_37),
        .lopt_11(lopt_38),
        .lopt_12(lopt_39),
        .lopt_13(lopt_40),
        .lopt_14(lopt_41),
        .lopt_15(lopt_42),
        .lopt_16(lopt_43),
        .lopt_17(lopt_44),
        .lopt_18(lopt_45),
        .lopt_19(lopt_46),
        .lopt_2(lopt_9),
        .lopt_3(lopt_10),
        .lopt_4(lopt_31),
        .lopt_5(lopt_32),
        .lopt_6(lopt_33),
        .lopt_7(lopt_34),
        .lopt_8(lopt_35),
        .lopt_9(lopt_36),
        .\mem_pc_i_reg[0]_0 (\mem_pc_i_reg[0] ),
        .sync_reset(reset_bool_for_rst),
        .wb_exception(wb_exception));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'h02)) 
    Pause_Ack_i_1
       (.I0(of_pause),
        .I1(mem_valid_instr),
        .I2(if_fetch_in_progress),
        .O(Pause_Ack0));
  FDRE Pause_Ack_reg
       (.C(Clk),
        .CE(1'b1),
        .D(Pause_Ack0),
        .Q(Pause_Ack),
        .R(reset_bool_for_rst));
  LUT3 #(
    .INIT(8'h80)) 
    \Performance_Debug_Control.dbg_brki_hit_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I2(wb_exception),
        .O(wb_Halted));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'hFF80)) 
    \Performance_Debug_Control.dbg_freeze_nohalt_i_2 
       (.I0(wb_exception),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .O(p_4_out__0));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'hFF80)) 
    \Performance_Debug_Control.dbg_stop_i_i_1 
       (.I0(wb_exception),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(reset_bool_for_rst),
        .O(dbg_stop_i));
  LUT5 #(
    .INIT(32'h6666FFF0)) 
    \Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_i_3 
       (.I0(Reset_Mode[0]),
        .I1(Reset_Mode[1]),
        .I2(wb_Halted),
        .I3(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 ),
        .I4(reset_bool_for_rst),
        .O(dbg_halt_reset_mode_reg));
  design_1_microblaze_0_0_PreFetch_Buffer_gti PreFetch_Buffer_I1
       (.Clk(Clk),
        .D({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1]}),
        .D224_out(D224_out),
        .Dbg_Clean_Stop0(Dbg_Clean_Stop0),
        .E(\Using_FPGA.Native_1 ),
        .EX_Is_Div_Instr(EX_Is_Div_Instr),
        .\EX_Op1_reg[0] (D),
        .\EX_Op2_reg[0] (\EX_Op2_reg[0] ),
        .\EX_Op2_reg[0]_0 (ex_read_imm_reg_i_1_n_0),
        .\EX_Op2_reg[0]_1 (EX_Fwd[0]),
        .\EX_Op2_reg[0]_2 (\Performance_Debug_Control.dbg_state_nohalt_reg [28]),
        .\EX_Op2_reg[10] (EX_Fwd[10]),
        .\EX_Op2_reg[10]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [18]),
        .\EX_Op2_reg[11] (EX_Fwd[11]),
        .\EX_Op2_reg[11]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [17]),
        .\EX_Op2_reg[12] (EX_Fwd[12]),
        .\EX_Op2_reg[12]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [16]),
        .\EX_Op2_reg[13] (EX_Fwd[13]),
        .\EX_Op2_reg[13]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [15]),
        .\EX_Op2_reg[14] (EX_Fwd[14]),
        .\EX_Op2_reg[14]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [14]),
        .\EX_Op2_reg[15] (EX_Fwd[15]),
        .\EX_Op2_reg[15]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [13]),
        .\EX_Op2_reg[16] (\MEM_DataBus_Addr_reg[0]_0 [7:0]),
        .\EX_Op2_reg[16]_0 (EX_Fwd[16]),
        .\EX_Op2_reg[17] (EX_Fwd[17]),
        .\EX_Op2_reg[18] (EX_Fwd[18]),
        .\EX_Op2_reg[19] (EX_Fwd[19]),
        .\EX_Op2_reg[1] (EX_Fwd[1]),
        .\EX_Op2_reg[1]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [27]),
        .\EX_Op2_reg[20] (EX_Fwd[20]),
        .\EX_Op2_reg[21] (EX_Fwd[21]),
        .\EX_Op2_reg[22] (EX_Fwd[22]),
        .\EX_Op2_reg[23] (EX_Fwd[23]),
        .\EX_Op2_reg[24] (EX_Fwd[24]),
        .\EX_Op2_reg[24]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [12]),
        .\EX_Op2_reg[25] (EX_Fwd[25]),
        .\EX_Op2_reg[25]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [11]),
        .\EX_Op2_reg[26] (EX_Fwd[26]),
        .\EX_Op2_reg[26]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [10]),
        .\EX_Op2_reg[27] (EX_Fwd[27]),
        .\EX_Op2_reg[27]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [9]),
        .\EX_Op2_reg[28] (EX_Fwd[28]),
        .\EX_Op2_reg[28]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [8]),
        .\EX_Op2_reg[29] (EX_Fwd[29]),
        .\EX_Op2_reg[29]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [7]),
        .\EX_Op2_reg[2] (EX_Fwd[2]),
        .\EX_Op2_reg[2]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [26]),
        .\EX_Op2_reg[30] (EX_Fwd[30]),
        .\EX_Op2_reg[30]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [6]),
        .\EX_Op2_reg[31] (EX_Fwd[31]),
        .\EX_Op2_reg[31]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [5]),
        .\EX_Op2_reg[3] (EX_Fwd[3]),
        .\EX_Op2_reg[3]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [25]),
        .\EX_Op2_reg[4] (EX_Fwd[4]),
        .\EX_Op2_reg[4]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [24]),
        .\EX_Op2_reg[5] (EX_Fwd[5]),
        .\EX_Op2_reg[5]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [23]),
        .\EX_Op2_reg[6] (EX_Fwd[6]),
        .\EX_Op2_reg[6]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [22]),
        .\EX_Op2_reg[7] (EX_Fwd[7]),
        .\EX_Op2_reg[7]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [21]),
        .\EX_Op2_reg[8] (EX_Fwd[8]),
        .\EX_Op2_reg[8]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [20]),
        .\EX_Op2_reg[9] (EX_Fwd[9]),
        .\EX_Op2_reg[9]_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [19]),
        .\EX_Op3[0]_i_2 (\Performance_Debug_Control.dbg_state_nohalt_reg [34]),
        .\EX_Op3[0]_i_6 (\ex_gpr_write_addr_reg_n_0_[4] ),
        .GPR_Op1(GPR_Op1),
        .GPR_Op2(GPR_Op2),
        .GPR_Op3(GPR_Op3),
        .I0(I0),
        .I139_out(I139_out),
        .I1_0(I1_0),
        .I4(I4),
        .I5(I5),
        .IB_Ready(IB_Ready),
        .IReady(IReady),
        .IReady_0(PreFetch_Buffer_I1_n_3),
        .MEM_Fwd(MEM_Fwd),
        .\Performance_Debug_Control.ex_brki_hit_reg (Q),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [3:2]),
        .\Serial_Dbg_Intf.control_reg_reg[8] (\Serial_Dbg_Intf.control_reg_reg[8] ),
        .\Using_FPGA.Native ({if_sel_input[0],if_sel_input[4]}),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_1 (of_gpr_op3_rd_addr[2]),
        .\Using_FPGA.Native_10 (PreFetch_Buffer_I1_n_66),
        .\Using_FPGA.Native_11 (E),
        .\Using_FPGA.Native_12 (PreFetch_Buffer_I1_n_169),
        .\Using_FPGA.Native_13 (PreFetch_Buffer_I1_n_173),
        .\Using_FPGA.Native_14 ({PreFetch_Buffer_I1_n_176,PreFetch_Buffer_I1_n_177}),
        .\Using_FPGA.Native_15 (PreFetch_Buffer_I1_n_178),
        .\Using_FPGA.Native_16 (PreFetch_Buffer_I1_n_179),
        .\Using_FPGA.Native_17 (PreFetch_Buffer_I1_n_182),
        .\Using_FPGA.Native_18 (PreFetch_Buffer_I1_n_185),
        .\Using_FPGA.Native_19 (PreFetch_Buffer_I1_n_186),
        .\Using_FPGA.Native_2 (of_gpr_op3_rd_addr[3]),
        .\Using_FPGA.Native_20 (PreFetch_Buffer_I1_n_187),
        .\Using_FPGA.Native_21 (PreFetch_Buffer_I1_n_188),
        .\Using_FPGA.Native_22 (PreFetch_Buffer_I1_n_189),
        .\Using_FPGA.Native_23 (PreFetch_Buffer_I1_n_191),
        .\Using_FPGA.Native_24 (\Using_FPGA.Native_2 ),
        .\Using_FPGA.Native_25 (PreFetch_Buffer_I1_n_193),
        .\Using_FPGA.Native_26 (PreFetch_Buffer_I1_n_194),
        .\Using_FPGA.Native_27 (PreFetch_Buffer_I1_n_195),
        .\Using_FPGA.Native_28 (\Using_FPGA.Native_3 ),
        .\Using_FPGA.Native_29 (\Using_FPGA.Native_4 ),
        .\Using_FPGA.Native_3 (of_gpr_op3_rd_addr[4]),
        .\Using_FPGA.Native_30 (\Using_FPGA.Native_5 ),
        .\Using_FPGA.Native_31 (\Using_FPGA.Native_6 ),
        .\Using_FPGA.Native_32 (\Using_FPGA.Native_7 ),
        .\Using_FPGA.Native_33 (\Using_FPGA.Native_8 ),
        .\Using_FPGA.Native_34 (\Using_FPGA.Native_9 ),
        .\Using_FPGA.Native_35 (\Using_FPGA.Native_10 ),
        .\Using_FPGA.Native_36 (\Using_FPGA.Native_11 ),
        .\Using_FPGA.Native_37 (\Using_FPGA.Native_12 ),
        .\Using_FPGA.Native_38 (\Using_FPGA.Native_13 ),
        .\Using_FPGA.Native_39 (\Using_FPGA.Native_14 ),
        .\Using_FPGA.Native_4 ({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4],of_imm_data[0],of_imm_data[1],of_imm_data[2],of_imm_data[3],of_imm_data[4],of_imm_data[5],of_imm_data[6],of_imm_data[7],of_imm_data[8],of_imm_data[9],of_imm_data[10],of_imm_data[11],of_imm_data[12],of_imm_data[13],of_imm_data[14],of_imm_data[15]}),
        .\Using_FPGA.Native_40 (\Using_FPGA.Native_15 ),
        .\Using_FPGA.Native_41 (\Using_FPGA.Native_16 ),
        .\Using_FPGA.Native_42 (\Using_FPGA.Native_17 ),
        .\Using_FPGA.Native_43 (\Using_FPGA.Native_18 ),
        .\Using_FPGA.Native_44 (\Using_FPGA.Native_19 ),
        .\Using_FPGA.Native_45 (\Using_FPGA.Native_20 ),
        .\Using_FPGA.Native_46 (\Using_FPGA.Native_21 ),
        .\Using_FPGA.Native_47 (\Using_FPGA.Native_22 ),
        .\Using_FPGA.Native_48 (\Using_FPGA.Native_23 ),
        .\Using_FPGA.Native_49 (\Using_FPGA.Native_24 ),
        .\Using_FPGA.Native_5 (PreFetch_Buffer_I1_n_48),
        .\Using_FPGA.Native_50 (\Using_FPGA.Native_25 ),
        .\Using_FPGA.Native_51 (\Using_FPGA.Native_26 ),
        .\Using_FPGA.Native_52 (\Using_FPGA.Native_27 ),
        .\Using_FPGA.Native_53 (\Using_FPGA.Native_28 ),
        .\Using_FPGA.Native_54 (\Using_FPGA.Native_29 ),
        .\Using_FPGA.Native_55 (\Using_FPGA.Native_30 ),
        .\Using_FPGA.Native_56 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_57 (\Using_FPGA.Native_32 ),
        .\Using_FPGA.Native_58 (\Using_FPGA.Native_33 ),
        .\Using_FPGA.Native_59 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_6 (\Performance_Debug_Control.dbg_state_nohalt_reg [158:157]),
        .\Using_FPGA.Native_60 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_61 (\mem_pc_i_reg[0]_0 ),
        .\Using_FPGA.Native_62 (\Using_FPGA.Native_41 ),
        .\Using_FPGA.Native_7 (PreFetch_Buffer_I1_n_56),
        .\Using_FPGA.Native_8 (PreFetch_Buffer_I1_n_59),
        .\Using_FPGA.Native_9 ({PreFetch_Buffer_I1_n_64,PreFetch_Buffer_I1_n_65}),
        .\Using_FPGA.Native_i_5__0 ({mem_gpr_write_addr[0],mem_gpr_write_addr[1],mem_gpr_write_addr[2],mem_gpr_write_addr[3],mem_gpr_write_addr[4]}),
        .\Using_FPGA.Native_i_5__0_0 (\Performance_Debug_Control.dbg_state_nohalt_reg [33:29]),
        .\Using_FPGA.Native_i_5__0_1 ({\ex_gpr_write_addr_reg_n_0_[0] ,I2}),
        .ex_MSR(ex_MSR),
        .ex_branch_with_delayslot(ex_branch_with_delayslot),
        .ex_branch_with_delayslot_i_reg_0(wb_Halted),
        .ex_branch_with_delayslot_reg(PreFetch_Buffer_I1_n_190),
        .ex_enable_sext_shift_i0(ex_enable_sext_shift_i0),
        .ex_gpr_write_dbg__0(ex_gpr_write_dbg__0),
        .ex_gpr_write_reg(PreFetch_Buffer_I1_n_49),
        .ex_gpr_write_reg_0(ex_gpr_write_reg_n_0),
        .ex_is_div_instr_I_reg(PreFetch_Buffer_I1_n_50),
        .ex_is_multi_or_load_instr0(ex_is_multi_or_load_instr0),
        .ex_jump(ex_jump),
        .ex_jump_nodelay(ex_jump_nodelay),
        .ex_jump_q(ex_jump_q),
        .ex_load_shift_carry0(ex_load_shift_carry0),
        .ex_mbar_decode(ex_mbar_decode),
        .ex_mbar_decode_cmb(ex_mbar_decode_cmb),
        .ex_mbar_is_sleep(ex_mbar_is_sleep),
        .ex_mbar_is_sleep_cmb(ex_mbar_is_sleep_cmb),
        .ex_move_to_MSR_instr93_out(ex_move_to_MSR_instr93_out),
        .ex_op1_cmp_eq1(ex_op1_cmp_eq1),
        .ex_op1_cmp_eq_n5_out(ex_op1_cmp_eq_n5_out),
        .ex_sel_alu_i0(ex_sel_alu_i0),
        .ex_sel_alu_i_reg(ex_sel_alu_i_reg_0),
        .ex_sel_alu_i_reg_0(ex_sel_alu_i_reg_1),
        .ex_sel_alu_i_reg_1(ex_sel_alu_i_reg_2),
        .ex_set_bip(ex_set_bip),
        .force12_out(force12_out),
        .force_Val10_out(force_Val10_out),
        .if_fetch_for_timing_optimization1(if_fetch_for_timing_optimization1),
        .if_fetch_in_progress(if_fetch_in_progress),
        .if_fetch_in_progress_reg(IF_PC_Write),
        .if_missed_fetch(if_missed_fetch),
        .if_missed_fetch_reg(PreFetch_Buffer_I1_n_183),
        .if_pre_buffer_addr(if_pre_buffer_addr),
        .in({Y[0],Y[1],Y[2],Y[3],Y[4],Y[5],Y[6],Y[7],Y[8],Y[9],Y[10],Y[21],Y[22],Y[23],Y[24],Y[25],Y[26],Y[27],Y[28],Y[29],Y[30],Y[31],in,Y[11],Y[12],Y[13],Y[14],Y[15],Y[16],Y[17],Y[18],Y[19],Y[20]}),
        .in0(if_fetch_without_full_or_jump),
        .mem_gpr_write(mem_gpr_write),
        .mem_valid_instr(mem_valid_instr),
        .of_Sel_SPR_MSR1(of_Sel_SPR_MSR1),
        .of_Sel_SPR_MSR88_out(of_Sel_SPR_MSR88_out),
        .of_instr({of_instr[0],of_instr[1],of_instr[2],of_instr[3],of_instr[4],of_instr[5]}),
        .of_op1_sel_spr(of_op1_sel_spr),
        .of_predecode(of_predecode),
        .of_use_op2_s(of_use_op2_s),
        .of_valid(of_valid),
        .out(if_fetch_without_full_or_jump),
        .p_213_in(p_213_in),
        .p_216_in(p_216_in),
        .p_2_in(p_2_in),
        .p_9_in(p_9_in),
        .sync_reset(reset_bool_for_rst),
        .use_Reg_Neg_DI1_out(use_Reg_Neg_DI1_out),
        .use_Reg_Neg_S3_out(use_Reg_Neg_S3_out),
        .wb_exception(wb_exception),
        .wb_exception_i_reg(PreFetch_Buffer_I1_n_184));
  LUT2 #(
    .INIT(4'hE)) 
    Sleep_INST_0
       (.I0(Sleep_Decode),
        .I1(Sleep_Out),
        .O(Sleep));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    Trace_Exception_Taken_INST_0
       (.I0(wb_exception),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [4]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    Trace_MB_Halted_INST_0
       (.I0(if_missed_fetch_reg_0),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [159]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[0]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [23]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3007]_0 ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [23]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [28]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[10]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [13]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3017] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [13]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [18]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[11]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [12]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3018] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [12]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [17]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[12]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [11]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3019] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [11]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [16]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[13]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [10]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3020] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [10]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [15]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[14]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [9]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3021] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [9]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [14]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[15]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [8]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3022] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [8]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [13]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[1]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [22]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3008] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [22]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [27]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[24]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [7]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[7]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [7]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [12]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[25]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [6]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[6]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [6]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [11]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[26]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [5]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[5]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [5]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [10]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[27]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [4]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[4]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [4]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [9]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[28]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [3]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[3]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [3]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [8]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[29]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [2]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[2]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [2]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [7]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[2]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [21]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3009] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [21]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [26]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[30]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [1]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[1]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [1]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [6]));
  LUT6 #(
    .INIT(64'hFBBBFBBBFBBB0888)) 
    \Trace_New_Reg_Value[31]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [0]),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(wb_databus_steered_read_data[0]),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [0]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [5]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[3]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [20]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3010] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [20]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [25]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[4]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [19]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3011] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [19]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [24]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[5]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [18]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3012] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [18]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [23]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[6]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [17]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3013] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [17]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [22]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[7]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [16]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3014] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [16]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [21]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[8]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [15]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3015] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [15]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [20]));
  LUT6 #(
    .INIT(64'hBBBBBBBB888B8888)) 
    \Trace_New_Reg_Value[9]_INST_0 
       (.I0(\LOCKSTEP_Out_reg[3007] [14]),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [4]),
        .I2(wb_doublet_access),
        .I3(wb_byte_access),
        .I4(\LOCKSTEP_Out_reg[3016] ),
        .I5(\LOCKSTEP_Out_reg[3007]_1 [14]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [19]));
  LUT4 #(
    .INIT(16'hAEAA)) 
    Trace_Reg_Write_INST_0
       (.I0(wb_reset),
        .I1(wb_valid_reg_0),
        .I2(wb_exception),
        .I3(wb_gpr_write_i),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [34]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h2AAA)) 
    Trace_Valid_Instr_INST_0
       (.I0(wb_valid_reg_0),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .O(\Performance_Debug_Control.dbg_state_nohalt_reg [35]));
  FDRE Trace_WB_Jump_Taken_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_jump_taken),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [1]),
        .R(reset_bool_for_rst));
  design_1_microblaze_0_0_carry_and \Use_MuxCy[10].OF_Piperun_Stage 
       (.lopt(lopt_29),
        .lopt_1(lopt_30),
        .of_PipeRun_carry_1(of_PipeRun_carry_1),
        .of_PipeRun_carry_2(of_PipeRun_carry_2),
        .use_Reg_Neg_S_reg(\Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0 ));
  design_1_microblaze_0_0_carry_and_57 \Use_MuxCy[11].OF_Piperun_Stage 
       (.E(\Using_FPGA.Native_1 ),
        .IB_Ready(IB_Ready),
        .ex_jump(ex_jump),
        .ex_jump_nodelay(ex_jump_nodelay),
        .ex_jump_nodelay_reg(\Use_MuxCy[11].OF_Piperun_Stage_n_1 ),
        .ex_jump_nodelay_reg_0(PreFetch_Buffer_I1_n_48),
        .if_missed_fetch(if_missed_fetch),
        .lopt(lopt_53),
        .lopt_1(lopt_54),
        .lopt_2(lopt_55),
        .of_PipeRun_carry_1(of_PipeRun_carry_1),
        .of_PipeRun_for_ce(of_PipeRun_for_ce),
        .of_pause(of_pause),
        .of_read_imm_reg_ii(of_read_imm_reg_ii),
        .of_read_imm_reg_ii_reg(\Use_MuxCy[11].OF_Piperun_Stage_n_2 ),
        .of_read_imm_reg_ii_reg_0(of_read_imm_reg_ii_i_2_n_0),
        .p_9_in(p_9_in),
        .sync_reset(reset_bool_for_rst),
        .wb_exception(wb_exception),
        .wb_exception_i_reg(\Use_MuxCy[11].OF_Piperun_Stage_n_3 ),
        .wb_exception_i_reg_0(\Use_MuxCy[11].OF_Piperun_Stage_n_4 ));
  design_1_microblaze_0_0_carry_and_58 \Use_MuxCy[1].OF_Piperun_Stage 
       (.\Using_FPGA.Native (\Using_FPGA.Native_0 ),
        .lopt(lopt_14),
        .lopt_1(lopt_15),
        .lopt_2(lopt_16),
        .of_PipeRun_carry_10(of_PipeRun_carry_10));
  design_1_microblaze_0_0_carry_and_59 \Use_MuxCy[2].OF_Piperun_Stage 
       (.EX_MBAR_Stall__1(EX_MBAR_Stall__1),
        .\Using_FPGA.Native (jump_logic_I1_n_42),
        .ex_first_cycle(ex_first_cycle),
        .ex_jump_hold(ex_jump_hold),
        .ex_mbar_decode(ex_mbar_decode),
        .ex_mbar_sleep(ex_mbar_sleep),
        .ex_mbar_stall_no_sleep_1(ex_mbar_stall_no_sleep_1),
        .lopt(lopt_17),
        .lopt_1(lopt_18),
        .of_PipeRun_carry_10(of_PipeRun_carry_10),
        .of_PipeRun_carry_9(of_PipeRun_carry_9));
  design_1_microblaze_0_0_carry_and_60 \Use_MuxCy[3].OF_Piperun_Stage 
       (.E(\Using_FPGA.Native_1 ),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [3:2]),
        .ex_Write_DCache_decode_reg(of_PipeRun_for_ce),
        .ex_Write_ICache_i(ex_Write_ICache_i),
        .ex_Write_ICache_i_cmb(ex_Write_ICache_i_cmb),
        .ex_write_dcache_instr(ex_write_dcache_instr),
        .in0(ex_Write_DCache_decode_cmb),
        .lopt(lopt_19),
        .lopt_1(lopt_20),
        .lopt_10(lopt_48),
        .lopt_11(lopt_49),
        .lopt_12(lopt_50),
        .lopt_13(lopt_51),
        .lopt_14(lopt_52),
        .lopt_2(PreFetch_Buffer_I1_n_191),
        .lopt_3(lopt_21),
        .lopt_4(lopt_22),
        .lopt_5(A),
        .lopt_6(lopt_23),
        .lopt_7(lopt_24),
        .lopt_8(\Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0 ),
        .lopt_9(lopt_47),
        .\mem_pc_i_reg[0] (\mem_pc_i_reg[0]_0 ),
        .of_PipeRun_carry_9(of_PipeRun_carry_9),
        .wb_exception(wb_exception),
        .\wb_exception_kind_i_reg[28] (\Use_MuxCy[3].OF_Piperun_Stage_n_1 ));
  design_1_microblaze_0_0_carry_and_61 \Use_MuxCy[4].OF_Piperun_Stage 
       (.E(\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native (PreFetch_Buffer_I1_n_191),
        .lopt(lopt_19),
        .lopt_1(lopt_20),
        .of_PipeRun_carry_7(of_PipeRun_carry_7));
  design_1_microblaze_0_0_carry_and_62 \Use_MuxCy[5].OF_Piperun_Stage 
       (.A(A),
        .lopt(lopt_21),
        .lopt_1(lopt_22),
        .of_PipeRun_carry_6(of_PipeRun_carry_6),
        .of_PipeRun_carry_7(of_PipeRun_carry_7));
  design_1_microblaze_0_0_carry_and_63 \Use_MuxCy[6].OF_Piperun_Stage 
       (.\Using_FPGA.Native (\Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0 ),
        .lopt(lopt_23),
        .lopt_1(lopt_24),
        .of_PipeRun_carry_5(of_PipeRun_carry_5),
        .of_PipeRun_carry_6(of_PipeRun_carry_6));
  design_1_microblaze_0_0_carry_and_64 \Use_MuxCy[7].OF_Piperun_Stage 
       (.\Using_FPGA.Native (\Using_FPGA_4.of_read_ex_write_op2_conflict_INST2_n_0 ),
        .lopt(lopt_25),
        .lopt_1(lopt_26),
        .lopt_10(lopt_54),
        .lopt_11(lopt_55),
        .lopt_2(\Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0 ),
        .lopt_3(lopt_27),
        .lopt_4(lopt_28),
        .lopt_5(\Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0 ),
        .lopt_6(lopt_29),
        .lopt_7(lopt_30),
        .lopt_8(\Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0 ),
        .lopt_9(lopt_53),
        .of_PipeRun_carry_4(of_PipeRun_carry_4),
        .of_PipeRun_carry_5(of_PipeRun_carry_5));
  design_1_microblaze_0_0_carry_and_65 \Use_MuxCy[8].OF_Piperun_Stage 
       (.\Using_FPGA.Native (\Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0 ),
        .lopt(lopt_25),
        .lopt_1(lopt_26),
        .of_PipeRun_carry_3(of_PipeRun_carry_3),
        .of_PipeRun_carry_4(of_PipeRun_carry_4));
  design_1_microblaze_0_0_carry_and_66 \Use_MuxCy[9].OF_Piperun_Stage 
       (.\Using_FPGA.Native (\Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0 ),
        .lopt(lopt_27),
        .lopt_1(lopt_28),
        .of_PipeRun_carry_2(of_PipeRun_carry_2),
        .of_PipeRun_carry_3(of_PipeRun_carry_3));
  design_1_microblaze_0_0_MB_FDRE \Using_FPGA.Gen_Bits[28].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .D(mem_exception_kind[28]),
        .E(\Using_FPGA.Native_1 ),
        .ex_exception_no_load_store_mask(ex_exception_no_load_store_mask),
        .mem_exception_from_ex(mem_exception_from_ex),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_MB_FDRE_67 \Using_FPGA.Gen_Bits[31].MEM_EX_Result_Inst 
       (.Clk(Clk),
        .D(mem_exception_kind[31]),
        .E(\Using_FPGA.Native_1 ),
        .ex_exception_no_load_store_mask(ex_exception_no_load_store_mask),
        .mem_exception_from_ex(mem_exception_from_ex),
        .sync_reset(reset_bool_for_rst));
  LUT2 #(
    .INIT(4'h8)) 
    \Using_FPGA.Native_i_11 
       (.I0(mem_gpr_write),
        .I1(mem_valid_instr),
        .O(p_213_in));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \Using_FPGA.Native_i_14 
       (.I0(ex_gpr_write_reg_n_0),
        .I1(ex_valid),
        .O(p_216_in));
  LUT2 #(
    .INIT(4'hE)) 
    \Using_FPGA.Native_i_1__52 
       (.I0(reset_bool_for_rst),
        .I1(EX_Is_Div_Instr),
        .O(R));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \Using_FPGA.Native_i_1__53 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .O(I1));
  LUT4 #(
    .INIT(16'h0020)) 
    \Using_FPGA.Native_i_1__59 
       (.I0(\EX_ALU_Op_reg[0]_0 [0]),
        .I1(EX_ALU_Sel_Logic),
        .I2(\EX_ALU_Op_reg[0]_0 [1]),
        .I3(ex_use_carry),
        .O(DI));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__60 
       (.I0(ex_databus_addr[0]),
        .I1(ex_sel_alu),
        .I2(swap_result[0]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O ),
        .O(EX_Fwd[31]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__61 
       (.I0(ex_databus_addr[1]),
        .I1(ex_sel_alu),
        .I2(swap_result[1]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O31_out ),
        .O(EX_Fwd[30]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__62 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [41]),
        .I1(ex_sel_alu),
        .I2(swap_result[2]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O30_out ),
        .O(EX_Fwd[29]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__63 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [42]),
        .I1(ex_sel_alu),
        .I2(swap_result[3]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O29_out ),
        .O(EX_Fwd[28]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__64 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [43]),
        .I1(ex_sel_alu),
        .I2(swap_result[4]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O28_out ),
        .O(EX_Fwd[27]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__65 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [44]),
        .I1(ex_sel_alu),
        .I2(swap_result[5]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O27_out ),
        .O(EX_Fwd[26]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__66 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [45]),
        .I1(ex_sel_alu),
        .I2(swap_result[6]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O26_out ),
        .O(EX_Fwd[25]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__67 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [46]),
        .I1(ex_sel_alu),
        .I2(swap_result[7]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O24_out ),
        .O(EX_Fwd[24]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__68 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [47]),
        .I1(ex_sel_alu),
        .I2(swap_result[8]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O23_out ),
        .O(EX_Fwd[23]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__69 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [48]),
        .I1(ex_sel_alu),
        .I2(swap_result[9]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O22_out ),
        .O(EX_Fwd[22]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__70 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [49]),
        .I1(ex_sel_alu),
        .I2(swap_result[10]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O21_out ),
        .O(EX_Fwd[21]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__71 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [50]),
        .I1(ex_sel_alu),
        .I2(swap_result[11]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O20_out ),
        .O(EX_Fwd[20]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__72 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [51]),
        .I1(ex_sel_alu),
        .I2(swap_result[12]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O19_out ),
        .O(EX_Fwd[19]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__73 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [52]),
        .I1(ex_sel_alu),
        .I2(swap_result[13]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O18_out ),
        .O(EX_Fwd[18]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__74 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [53]),
        .I1(ex_sel_alu),
        .I2(swap_result[14]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O17_out ),
        .O(EX_Fwd[17]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__75 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [54]),
        .I1(ex_sel_alu),
        .I2(swap_result[15]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O15_out ),
        .O(EX_Fwd[16]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__76 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [55]),
        .I1(ex_sel_alu),
        .I2(swap_result[16]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O14_out ),
        .O(EX_Fwd[15]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__77 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [56]),
        .I1(ex_sel_alu),
        .I2(swap_result[17]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O13_out ),
        .O(EX_Fwd[14]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__78 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [57]),
        .I1(ex_sel_alu),
        .I2(swap_result[18]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O12_out ),
        .O(EX_Fwd[13]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__79 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [58]),
        .I1(ex_sel_alu),
        .I2(swap_result[19]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O11_out ),
        .O(EX_Fwd[12]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__80 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [59]),
        .I1(ex_sel_alu),
        .I2(swap_result[20]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O10_out ),
        .O(EX_Fwd[11]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__81 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [60]),
        .I1(ex_sel_alu),
        .I2(swap_result[21]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O9_out ),
        .O(EX_Fwd[10]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__82 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [61]),
        .I1(ex_sel_alu),
        .I2(swap_result[22]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O8_out ),
        .O(EX_Fwd[9]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__83 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [62]),
        .I1(ex_sel_alu),
        .I2(swap_result[23]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O7_out ),
        .O(EX_Fwd[8]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__84 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [63]),
        .I1(ex_sel_alu),
        .I2(swap_result_reg[7]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O6_out ),
        .O(EX_Fwd[7]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__85 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [64]),
        .I1(ex_sel_alu),
        .I2(swap_result_reg[6]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O5_out ),
        .O(EX_Fwd[6]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__86 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [65]),
        .I1(ex_sel_alu),
        .I2(swap_result_reg[5]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O4_out ),
        .O(EX_Fwd[5]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__87 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [66]),
        .I1(ex_sel_alu),
        .I2(swap_result_reg[4]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O3_out ),
        .O(EX_Fwd[4]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__88 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [67]),
        .I1(ex_sel_alu),
        .I2(swap_result_reg[3]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O2_out ),
        .O(EX_Fwd[3]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__89 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [68]),
        .I1(ex_sel_alu),
        .I2(swap_result_reg[2]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O1_out ),
        .O(EX_Fwd[2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Using_FPGA.Native_i_1__90 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [69]),
        .I1(ex_sel_alu),
        .I2(swap_result_reg[1]),
        .I3(ex_swap_instr),
        .I4(\Data_Flow_I/Shift_Logic_Module_I/O0_out ),
        .O(EX_Fwd[1]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'h1555)) 
    \Using_FPGA.Native_i_1__98 
       (.I0(\mem_pc_i_reg[0]_0 ),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .O(\Performance_Debug_Control.dbg_freeze_nohalt_reg ));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__85 
       (.I0(\MEM_DataBus_Addr_reg[0]_0 [70]),
        .I1(ex_sel_alu),
        .I2(ex_shift_logic_result),
        .O(EX_Fwd[0]));
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__0 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [0]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [1]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O ));
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__1 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [1]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [2]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O31_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__10 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [10]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [11]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O21_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__11 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [11]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [12]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O20_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__12 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [12]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [13]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O19_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__13 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [13]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [14]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O18_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__14 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [14]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [15]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O17_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__15 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [15]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [16]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O15_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__16 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [17]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [16]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O14_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__17 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [18]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [17]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O13_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__18 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [19]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [18]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O12_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__19 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [20]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [19]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O11_out ));
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__2 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [2]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [3]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O30_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__20 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [21]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [20]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O10_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__21 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [22]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [21]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O9_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__22 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [23]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [22]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O8_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__23 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [24]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [23]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O7_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__24 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [25]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [24]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O6_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__25 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [26]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [25]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O5_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__26 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [27]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [26]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O4_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__27 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [28]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [27]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O3_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__28 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [29]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [28]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O2_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__29 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [30]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [29]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O1_out ));
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__3 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [3]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [4]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O29_out ));
  LUT6 #(
    .INIT(64'h8A80AAAA8A800000)) 
    \Using_FPGA.Native_i_3__30 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [31]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\Using_FPGA.Native_42 [30]),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O0_out ));
  LUT6 #(
    .INIT(64'hB888B8B8B8888888)) 
    \Using_FPGA.Native_i_3__31 
       (.I0(swap_result_reg[0]),
        .I1(ex_swap_instr),
        .I2(ex_Enable_Sext_Shift),
        .I3(\Using_FPGA.Native_i_5__1_n_0 ),
        .I4(\EX_Sext_Op_reg[0]_0 [1]),
        .I5(\Using_FPGA.Native_43 ),
        .O(ex_shift_logic_result));
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__4 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [4]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [5]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O28_out ));
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__5 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [5]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [6]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O27_out ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__6 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [6]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [7]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O26_out ));
  LUT5 #(
    .INIT(32'hA8880888)) 
    \Using_FPGA.Native_i_3__7 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [7]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [8]),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O24_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__8 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [8]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [9]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O23_out ));
  LUT6 #(
    .INIT(64'hA88A088AA8800880)) 
    \Using_FPGA.Native_i_3__9 
       (.I0(ex_Enable_Sext_Shift),
        .I1(\Using_FPGA.Native_42 [9]),
        .I2(\EX_Sext_Op_reg[0]_0 [0]),
        .I3(\EX_Sext_Op_reg[0]_0 [1]),
        .I4(\Using_FPGA.Native_42 [10]),
        .I5(out),
        .O(\Data_Flow_I/Shift_Logic_Module_I/O22_out ));
  LUT5 #(
    .INIT(32'h0DFF0800)) 
    \Using_FPGA.Native_i_5__1 
       (.I0(ex_shift_op[1]),
        .I1(ex_MSR[1]),
        .I2(ex_shift_op[0]),
        .I3(\EX_Sext_Op_reg[0]_0 [0]),
        .I4(\Using_FPGA.Native_42 [31]),
        .O(\Using_FPGA.Native_i_5__1_n_0 ));
  design_1_microblaze_0_0_MB_FDRE_68 \Using_FPGA_2.ex_byte_access_i_Inst 
       (.Clk(Clk),
        .\MEM_DataBus_Write_Data_reg[0] (\MEM_DataBus_Write_Data_reg[0] ),
        .\MEM_DataBus_Write_Data_reg[0]_0 (ex_reverse_mem_access),
        .\MEM_DataBus_Write_Data_reg[0]_1 (ex_doublet_access),
        .\Using_FPGA.Native_0 (ex_byte_access),
        .\Using_FPGA.Native_1 (\Performance_Debug_Control.dbg_state_nohalt_reg [124:101]),
        .\Using_FPGA.Native_2 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_3 (PreFetch_Buffer_I1_n_178),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_MB_FDRE_69 \Using_FPGA_2.ex_doublet_access_i_Inst 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_1 (PreFetch_Buffer_I1_n_179),
        .ex_doublet_access(ex_doublet_access),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_MB_FDRE_70 \Using_FPGA_2.ex_is_load_instr_Inst 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (ex_is_load_instr_s),
        .\Using_FPGA.Native_1 (\Performance_Debug_Control.dbg_state_nohalt_reg [100]),
        .\Using_FPGA.Native_2 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_3 (PreFetch_Buffer_I1_n_193),
        .ex_Sel_SPR_BTR(ex_Sel_SPR_BTR),
        .ex_Sel_SPR_EAR(ex_Sel_SPR_EAR),
        .ex_Sel_SPR_EDR(ex_Sel_SPR_EDR),
        .ex_Sel_SPR_ESR(ex_Sel_SPR_ESR),
        .ex_Sel_SPR_FSR(ex_Sel_SPR_FSR),
        .ex_Sel_SPR_PVR(ex_Sel_SPR_PVR),
        .ex_Sel_SPR_PVR_reg(\Using_FPGA_2.ex_is_load_instr_Inst_n_3 ),
        .ex_Sel_SPR_SHR(ex_Sel_SPR_SHR),
        .ex_Sel_SPR_SLR(ex_Sel_SPR_SLR),
        .ex_is_multi_instr2(ex_is_multi_instr2),
        .ex_is_swx_instr_s(ex_is_swx_instr_s),
        .ex_load_store_instr_s(ex_load_store_instr_s),
        .ex_reservation(ex_reservation),
        .mem_is_multi_or_load_instr0(mem_is_multi_or_load_instr0),
        .p_231_in(p_231_in),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_MB_FDRE_71 \Using_FPGA_2.ex_is_lwx_instr_Inst 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_1 (PreFetch_Buffer_I1_n_173),
        .\Using_FPGA.Native_i_2__21 (mem_Exception_Taken),
        .\Using_LWX_SWX_instr.ex_reservation_reg (\Using_FPGA_2.ex_is_lwx_instr_Inst_n_1 ),
        .\Using_LWX_SWX_instr.ex_reservation_reg_0 (\Using_FPGA_2.ex_is_swx_instr_Inst_n_4 ),
        .ex_MSR_Load_LWX_SWX_C(ex_MSR_Load_LWX_SWX_C),
        .ex_is_swx_instr_s(ex_is_swx_instr_s),
        .ex_load_store_instr_s(ex_load_store_instr_s),
        .ex_reservation(ex_reservation),
        .p_227_in(p_227_in),
        .p_231_in(p_231_in),
        .sync_reset(reset_bool_for_rst),
        .wb_exception(wb_exception));
  design_1_microblaze_0_0_MB_FDRE_72 \Using_FPGA_2.ex_is_swx_instr_Inst 
       (.Clk(Clk),
        .D224_out(D224_out),
        .D_AS(mem_Exception_Taken),
        .E(\Using_FPGA.Native_1 ),
        .MEM_DataBus_Access_reg(\Using_FPGA_2.ex_is_swx_instr_Inst_n_1 ),
        .MEM_DataBus_Access_reg_0(mem_databus_access),
        .MEM_DataBus_Access_reg_1(\Using_FPGA.Native_0 ),
        .SRI(SRI),
        .\Using_FPGA.Native_0 (of_PipeRun_for_ce),
        .\Using_LWX_SWX_instr.ex_reservation_reg (wb_Halted),
        .ex_MSR_Set_SW_BIP(ex_MSR_Set_SW_BIP),
        .ex_is_swx_instr_s(ex_is_swx_instr_s),
        .ex_load_store_instr_s(ex_load_store_instr_s),
        .ex_reservation(ex_reservation),
        .ex_swx_access__0(ex_swx_access__0),
        .p_227_in(p_227_in),
        .p_231_in(p_231_in),
        .sync_reset(reset_bool_for_rst),
        .wb_exception(wb_exception),
        .wb_exception_i_reg(\Using_FPGA_2.ex_is_swx_instr_Inst_n_4 ));
  design_1_microblaze_0_0_MB_FDRE_73 \Using_FPGA_2.ex_load_store_instr_Inst 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_1 (PreFetch_Buffer_I1_n_185),
        .ex_is_swx_instr_s(ex_is_swx_instr_s),
        .ex_load_store_instr_s(ex_load_store_instr_s),
        .ex_reservation(ex_reservation),
        .mem_exception_from_ex(mem_exception_from_ex),
        .mem_load_store_access0(mem_load_store_access0),
        .mem_load_store_access_reg(ex_valid),
        .mem_load_store_access_reg_0(\Using_FPGA.Native_39 ),
        .mem_load_store_access_reg_1(\Using_FPGA.Native_40 ),
        .mem_valid_instr(mem_valid_instr),
        .p_227_in(p_227_in),
        .p_231_in(p_231_in),
        .sync_reset(reset_bool_for_rst),
        .wb_exception(wb_exception));
  design_1_microblaze_0_0_MB_FDRE_74 \Using_FPGA_2.ex_reverse_mem_access_inst 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_1 (PreFetch_Buffer_I1_n_194),
        .ex_reverse_mem_access(ex_reverse_mem_access),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_MB_FDRE_75 \Using_FPGA_3.ex_clear_MSR_BIP_instr_Inst 
       (.Clk(Clk),
        .E(\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native_0 (of_PipeRun_for_ce),
        .\Using_FPGA.Native_1 (\Using_FPGA_3.of_clear_MSR_BIP_hold_Inst_n_0 ),
        .\Using_FPGA.Native_2 (ex_set_bip_reg_0),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_38 ),
        .ex_MSR(ex_MSR[2]),
        .ex_set_bip_reg(ex_set_bip_reg_1),
        .p_231_in(p_231_in),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_MB_FDR \Using_FPGA_3.of_clear_MSR_BIP_hold_Inst 
       (.Clk(Clk),
        .E(\Using_FPGA.Native_1 ),
        .I0(I0),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg (\Using_FPGA_3.of_clear_MSR_BIP_hold_Inst_n_0 ),
        .Q({ex_opcode[0],ex_opcode[1],ex_opcode[2],ex_opcode[3],ex_opcode[4],ex_opcode[5]}),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_39 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_40 ),
        .\Using_FPGA.Native_2 (ex_valid),
        .\Using_FPGA.Native_3 (of_PipeRun_for_ce),
        .sync_reset(reset_bool_for_rst));
  design_1_microblaze_0_0_MB_LUT6__parameterized8 \Using_FPGA_4.of_read_ex_write_op1_conflict_INST1 
       (.D({\ex_gpr_write_addr_reg_n_0_[0] ,I2,I4}),
        .O(O),
        .of_predecode({of_predecode[1],of_predecode[2],of_predecode[3]}));
  design_1_microblaze_0_0_MB_LUT6__parameterized10 \Using_FPGA_4.of_read_ex_write_op1_conflict_INST2 
       (.A(A),
        .D(\ex_gpr_write_addr_reg_n_0_[4] ),
        .I0(I0),
        .O(O),
        .\Using_FPGA.Native_i_1__58_0 (ex_gpr_write_reg_n_0),
        .\Using_FPGA.Native_i_1__58_1 (ex_valid),
        .ex_is_multi_or_load_instr(ex_is_multi_or_load_instr),
        .of_predecode({of_predecode[4],of_predecode[5]}));
  design_1_microblaze_0_0_MB_LUT6__parameterized8_76 \Using_FPGA_4.of_read_ex_write_op2_conflict_INST1 
       (.D({\ex_gpr_write_addr_reg_n_0_[0] ,I2,I4}),
        .of_predecode({of_predecode[6],of_predecode[7],of_predecode[8]}),
        .of_read_ex_write_op2_conflict_part1(of_read_ex_write_op2_conflict_part1));
  design_1_microblaze_0_0_MB_LUT6__parameterized10_77 \Using_FPGA_4.of_read_ex_write_op2_conflict_INST2 
       (.D(\ex_gpr_write_addr_reg_n_0_[4] ),
        .I0(I0),
        .\Using_FPGA.Native_i_1__9_0 (ex_gpr_write_reg_n_0),
        .\Using_FPGA.Native_i_1__9_1 (ex_valid),
        .ex_is_multi_or_load_instr(ex_is_multi_or_load_instr),
        .ex_is_multi_or_load_instr_reg(\Using_FPGA_4.of_read_ex_write_op2_conflict_INST2_n_0 ),
        .of_predecode({of_predecode[9],of_predecode[10]}),
        .of_read_ex_write_op2_conflict_part1(of_read_ex_write_op2_conflict_part1),
        .of_use_op2_s(of_use_op2_s));
  design_1_microblaze_0_0_MB_LUT6__parameterized8_78 \Using_FPGA_4.of_read_ex_write_op3_conflict_INST1 
       (.D({\ex_gpr_write_addr_reg_n_0_[0] ,I2,I4}),
        .\Using_FPGA.Native_i_1__56 ({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1]}),
        .\Using_FPGA.Native_i_1__56_0 (of_gpr_op3_rd_addr[2]),
        .of_read_ex_write_op3_conflict_part1(of_read_ex_write_op3_conflict_part1));
  design_1_microblaze_0_0_MB_LUT6__parameterized10_79 \Using_FPGA_4.of_read_ex_write_op3_conflict_INST2 
       (.D(\ex_gpr_write_addr_reg_n_0_[4] ),
        .I0(I0),
        .\Using_FPGA.Native_i_1__56_0 (of_gpr_op3_rd_addr[3]),
        .\Using_FPGA.Native_i_1__56_1 (of_gpr_op3_rd_addr[4]),
        .\Using_FPGA.Native_i_1__56_2 (ex_gpr_write_reg_n_0),
        .\Using_FPGA.Native_i_1__56_3 (ex_valid),
        .ex_is_multi_or_load_instr(ex_is_multi_or_load_instr),
        .ex_is_multi_or_load_instr_reg(\Using_FPGA_4.of_read_ex_write_op3_conflict_INST2_n_0 ),
        .of_predecode(of_predecode[0]),
        .of_read_ex_write_op3_conflict_part1(of_read_ex_write_op3_conflict_part1));
  design_1_microblaze_0_0_MB_LUT6__parameterized8_80 \Using_FPGA_4.of_read_mem_write_op1_conflict_INST1 
       (.Q({mem_gpr_write_addr[0],mem_gpr_write_addr[1],mem_gpr_write_addr[2]}),
        .mem_is_multi_or_load_instr(mem_is_multi_or_load_instr),
        .mem_is_multi_or_load_instr_reg(\Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0 ),
        .of_predecode({of_predecode[1],of_predecode[2],of_predecode[3]}),
        .of_read_mem_write_op1_conflict_part2(of_read_mem_write_op1_conflict_part2));
  design_1_microblaze_0_0_MB_LUT6__parameterized10_81 \Using_FPGA_4.of_read_mem_write_op1_conflict_INST2 
       (.Q({mem_gpr_write_addr[3],mem_gpr_write_addr[4]}),
        .mem_gpr_write(mem_gpr_write),
        .mem_valid_instr(mem_valid_instr),
        .of_predecode({of_predecode[4],of_predecode[5]}),
        .of_read_mem_write_op1_conflict_part2(of_read_mem_write_op1_conflict_part2));
  design_1_microblaze_0_0_MB_LUT6__parameterized8_82 \Using_FPGA_4.of_read_mem_write_op2_conflict_INST1 
       (.Q({mem_gpr_write_addr[0],mem_gpr_write_addr[1],mem_gpr_write_addr[2]}),
        .of_predecode({of_predecode[6],of_predecode[7],of_predecode[8]}),
        .of_read_mem_write_op2_conflict_part1(of_read_mem_write_op2_conflict_part1));
  design_1_microblaze_0_0_MB_LUT6__parameterized10_83 \Using_FPGA_4.of_read_mem_write_op2_conflict_INST2 
       (.Q({mem_gpr_write_addr[3],mem_gpr_write_addr[4]}),
        .mem_gpr_write(mem_gpr_write),
        .mem_is_multi_or_load_instr(mem_is_multi_or_load_instr),
        .mem_is_multi_or_load_instr_reg(\Using_FPGA_4.of_read_mem_write_op2_conflict_INST2_n_0 ),
        .mem_valid_instr(mem_valid_instr),
        .of_predecode({of_predecode[9],of_predecode[10]}),
        .of_read_mem_write_op2_conflict_part1(of_read_mem_write_op2_conflict_part1),
        .of_use_op2_s(of_use_op2_s));
  design_1_microblaze_0_0_MB_LUT6__parameterized8_84 \Using_FPGA_4.of_read_mem_write_op3_conflict_INST1 
       (.D({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1]}),
        .Q({mem_gpr_write_addr[0],mem_gpr_write_addr[1],mem_gpr_write_addr[2]}),
        .\Using_FPGA.Native_i_1__55 (of_gpr_op3_rd_addr[2]),
        .of_read_mem_write_op3_conflict_part1(of_read_mem_write_op3_conflict_part1));
  design_1_microblaze_0_0_MB_LUT6__parameterized10_85 \Using_FPGA_4.of_read_mem_write_op3_conflict_INST2 
       (.Q({mem_gpr_write_addr[3],mem_gpr_write_addr[4]}),
        .\Using_FPGA.Native_i_1__55_0 (of_gpr_op3_rd_addr[3]),
        .\Using_FPGA.Native_i_1__55_1 (of_gpr_op3_rd_addr[4]),
        .mem_gpr_write(mem_gpr_write),
        .mem_is_multi_or_load_instr(mem_is_multi_or_load_instr),
        .mem_is_multi_or_load_instr_reg(\Using_FPGA_4.of_read_mem_write_op3_conflict_INST2_n_0 ),
        .mem_valid_instr(mem_valid_instr),
        .of_predecode(of_predecode[0]),
        .of_read_mem_write_op3_conflict_part1(of_read_mem_write_op3_conflict_part1));
  FDRE \Using_LWX_SWX_instr.ex_reservation_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA_2.ex_is_lwx_instr_Inst_n_1 ),
        .Q(ex_reservation),
        .R(1'b0));
  design_1_microblaze_0_0_carry_and_86 \Using_PC_Incr_Dbg_or_Prot.if_pc_incr_carry_and_1 
       (.\Using_FPGA.Native (\Using_FPGA.Native_36 ),
        .if_pc_incr_carry0(if_pc_incr_carry0),
        .if_pc_incr_carry1(if_pc_incr_carry1),
        .lopt(lopt_3),
        .lopt_1(lopt_4));
  FDRE WB_Byte_Access_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_byte_access),
        .Q(wb_byte_access),
        .R(reset_bool_for_rst));
  FDRE WB_DelaySlot_Instr_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_delayslot_instr),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [0]),
        .R(reset_bool_for_rst));
  FDRE WB_Doublet_Access_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_doublet_access),
        .Q(wb_doublet_access),
        .R(reset_bool_for_rst));
  LUT2 #(
    .INIT(4'hB)) 
    \WB_MEM_Result[0]_i_1 
       (.I0(reset_bool_for_rst),
        .I1(mem_Sel_MEM_Res),
        .O(SR));
  FDRE WB_PC_Valid_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_valid_instr),
        .Q(wb_pc_valid),
        .R(reset_bool_for_rst));
  FDRE WB_Read_Imm_Reg_1_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_read_imm_reg_1),
        .Q(wb_read_imm_reg_1),
        .R(reset_bool_for_rst));
  FDRE WB_Read_Imm_Reg_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_read_imm_reg),
        .Q(wb_read_imm_reg),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'h0000000000220322)) 
    active_access_i_1
       (.I0(\Use_DBUS.DAXI_Interface_I1/M_AXI_DP_AWVALID_i1 ),
        .I1(LOCKSTEP_Master_Out[2]),
        .I2(M_AXI_DP_BVALID),
        .I3(active_access),
        .I4(M_AXI_DP_RVALID),
        .I5(reset_bool_for_rst),
        .O(M_AXI_DP_BVALID_0));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    active_wakeup_i_1
       (.I0(wakeup_i[0]),
        .I1(wakeup_i[1]),
        .I2(Sleep_Decode),
        .I3(Hibernate),
        .I4(Suspend),
        .O(active_wakeup0));
  FDRE active_wakeup_reg
       (.C(Clk),
        .CE(1'b1),
        .D(active_wakeup0),
        .Q(active_wakeup),
        .R(reset_bool_for_rst));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[0]_i_2 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [28]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [34]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[23]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[10]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [18]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [24]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[13]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[11]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [17]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [23]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[12]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[12]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [16]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [22]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[11]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[13]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [15]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [21]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[10]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[14]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [14]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [20]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[9]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[15]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [13]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [19]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[8]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[1]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [27]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [33]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[22]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[24]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [12]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [18]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[7]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[25]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [11]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [17]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[6]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[26]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [10]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [16]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[5]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[27]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [9]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [15]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[4]));
  LUT6 #(
    .INIT(64'hBF80BFBFBF808080)) 
    \data_rd_reg[28]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [8]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [10]),
        .I4(\data_rd_reg_reg[0] ),
        .I5(\MEM_DataBus_Addr_reg[0]_0 [14]),
        .O(wb_gpr_write_dbg_reg_0[3]));
  LUT6 #(
    .INIT(64'hBF80BFBFBF808080)) 
    \data_rd_reg[29]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [7]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [9]),
        .I4(\data_rd_reg_reg[0] ),
        .I5(\MEM_DataBus_Addr_reg[0]_0 [13]),
        .O(wb_gpr_write_dbg_reg_0[2]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[2]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [26]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [32]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[21]));
  LUT6 #(
    .INIT(64'hBF80BFBFBF808080)) 
    \data_rd_reg[30]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [6]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [8]),
        .I4(\data_rd_reg_reg[0] ),
        .I5(\MEM_DataBus_Addr_reg[0]_0 [12]),
        .O(wb_gpr_write_dbg_reg_0[1]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[31]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [5]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [11]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[0]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[3]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [25]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [31]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[20]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[4]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [24]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [30]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[19]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[5]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [23]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [29]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[18]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[6]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [22]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [28]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[17]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[7]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [21]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [27]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[16]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[8]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [20]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [26]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[15]));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[9]_i_1 
       (.I0(\Performance_Debug_Control.dbg_state_nohalt_reg [19]),
        .I1(wb_gpr_wr_dbg),
        .I2(if_missed_fetch_reg_1),
        .I3(\MEM_DataBus_Addr_reg[0]_0 [25]),
        .I4(\data_rd_reg_reg[0] ),
        .O(wb_gpr_write_dbg_reg_0[14]));
  FDRE ex_Sel_SPR_BTR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_BTR),
        .Q(ex_Sel_SPR_BTR),
        .R(reset_bool_for_rst));
  FDRE ex_Sel_SPR_EAR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_EAR),
        .Q(ex_Sel_SPR_EAR),
        .R(reset_bool_for_rst));
  FDRE ex_Sel_SPR_EDR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_EDR),
        .Q(ex_Sel_SPR_EDR),
        .R(reset_bool_for_rst));
  FDRE ex_Sel_SPR_ESR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_ESR),
        .Q(ex_Sel_SPR_ESR),
        .R(reset_bool_for_rst));
  FDRE ex_Sel_SPR_FSR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_FSR),
        .Q(ex_Sel_SPR_FSR),
        .R(reset_bool_for_rst));
  FDRE ex_Sel_SPR_PVR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_PVR),
        .Q(ex_Sel_SPR_PVR),
        .R(reset_bool_for_rst));
  FDRE ex_Sel_SPR_SHR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_SHR),
        .Q(ex_Sel_SPR_SHR),
        .R(reset_bool_for_rst));
  FDRE ex_Sel_SPR_SLR_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_SLR),
        .Q(ex_Sel_SPR_SLR),
        .R(reset_bool_for_rst));
  FDRE ex_Write_DCache_decode_reg
       (.C(Clk),
        .CE(1'b1),
        .D(ex_Write_DCache_decode_cmb),
        .Q(ex_write_dcache_instr),
        .R(reset_bool_for_rst));
  FDRE ex_Write_ICache_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(ex_Write_ICache_i_cmb),
        .Q(ex_Write_ICache_i),
        .R(reset_bool_for_rst));
  FDSE ex_alu_sel_logic_i_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_195),
        .Q(EX_ALU_Sel_Logic),
        .S(reset_bool_for_rst));
  FDRE ex_branch_with_delayslot_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_48),
        .Q(ex_branch_with_delayslot),
        .R(reset_bool_for_rst));
  FDRE ex_delayslot_Instr_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_delayslot_Instr0),
        .Q(ex_delayslot_Instr),
        .R(reset_bool_for_rst));
  FDRE ex_enable_alu_i_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_66),
        .Q(EX_Enable_ALU),
        .R(reset_bool_for_rst));
  FDRE ex_enable_sext_shift_i_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_enable_sext_shift_i0),
        .Q(ex_Enable_Sext_Shift),
        .R(reset_bool_for_rst));
  FDRE ex_first_cycle_reg
       (.C(Clk),
        .CE(1'b1),
        .D(\Use_MuxCy[11].OF_Piperun_Stage_n_4 ),
        .Q(ex_first_cycle),
        .R(1'b0));
  FDRE \ex_gpr_write_addr_reg[0] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[0]),
        .Q(\ex_gpr_write_addr_reg_n_0_[0] ),
        .R(reset_bool_for_rst));
  FDRE \ex_gpr_write_addr_reg[1] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[1]),
        .Q(I2),
        .R(reset_bool_for_rst));
  FDRE \ex_gpr_write_addr_reg[2] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[2]),
        .Q(I4),
        .R(reset_bool_for_rst));
  FDRE \ex_gpr_write_addr_reg[3] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[3]),
        .Q(I0),
        .R(reset_bool_for_rst));
  FDRE \ex_gpr_write_addr_reg[4] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[4]),
        .Q(\ex_gpr_write_addr_reg_n_0_[4] ),
        .R(reset_bool_for_rst));
  FDRE ex_gpr_write_dbg_reg
       (.C(Clk),
        .CE(1'b1),
        .D(PreFetch_Buffer_I1_n_184),
        .Q(ex_gpr_write_dbg__0),
        .R(1'b0));
  FDRE ex_gpr_write_reg
       (.C(Clk),
        .CE(1'b1),
        .D(PreFetch_Buffer_I1_n_49),
        .Q(ex_gpr_write_reg_n_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    ex_hibernate_i_i_1
       (.I0(active_wakeup),
        .I1(reset_bool_for_rst),
        .O(ex_hibernate_i_i_1_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAA2A2A2AAA)) 
    ex_hibernate_i_i_2
       (.I0(ex_mbar_sleep),
        .I1(ex_mbar_decode),
        .I2(p_231_in),
        .I3(ex_first_cycle),
        .I4(ex_mbar_stall_no_sleep_1),
        .I5(ex_jump_hold),
        .O(ex_sleep_i0));
  LUT1 #(
    .INIT(2'h1)) 
    ex_hibernate_i_i_3
       (.I0(p_1_in124_in),
        .O(p_1_in));
  FDRE ex_hibernate_i_reg
       (.C(Clk),
        .CE(ex_sleep_i0),
        .D(p_1_in),
        .Q(Hibernate),
        .R(ex_hibernate_i_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[0] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[0]),
        .Q(\ex_instr_reg_n_0_[0] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[10] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[4]),
        .Q(\ex_instr_reg_n_0_[10] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[11] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op1_rd_addr[0]),
        .Q(\ex_instr_reg_n_0_[11] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[12] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op1_rd_addr[1]),
        .Q(\ex_instr_reg_n_0_[12] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[13] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op1_rd_addr[2]),
        .Q(\ex_instr_reg_n_0_[13] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[14] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op1_rd_addr[3]),
        .Q(\ex_instr_reg_n_0_[14] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[15] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op1_rd_addr[4]),
        .Q(\ex_instr_reg_n_0_[15] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[16] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[0]),
        .Q(\ex_instr_reg_n_0_[16] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[17] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[1]),
        .Q(\ex_instr_reg_n_0_[17] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[18] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[2]),
        .Q(\ex_instr_reg_n_0_[18] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[19] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[3]),
        .Q(\ex_instr_reg_n_0_[19] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[1] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[1]),
        .Q(\ex_instr_reg_n_0_[1] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[20] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[4]),
        .Q(\ex_instr_reg_n_0_[20] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[21] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[5]),
        .Q(\ex_instr_reg_n_0_[21] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[22] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[6]),
        .Q(\ex_instr_reg_n_0_[22] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[23] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[7]),
        .Q(\ex_instr_reg_n_0_[23] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[24] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[8]),
        .Q(\ex_instr_reg_n_0_[24] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[25] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[9]),
        .Q(\ex_instr_reg_n_0_[25] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[26] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[10]),
        .Q(\ex_instr_reg_n_0_[26] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[27] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[11]),
        .Q(\ex_instr_reg_n_0_[27] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[28] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[12]),
        .Q(\ex_instr_reg_n_0_[28] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[29] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[13]),
        .Q(\ex_instr_reg_n_0_[29] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[2] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[2]),
        .Q(\ex_instr_reg_n_0_[2] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[30] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[14]),
        .Q(\ex_instr_reg_n_0_[30] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[31] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_imm_data[15]),
        .Q(\ex_instr_reg_n_0_[31] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[3] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[3]),
        .Q(\ex_instr_reg_n_0_[3] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[4] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[4]),
        .Q(\ex_instr_reg_n_0_[4] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[5] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[5]),
        .Q(\ex_instr_reg_n_0_[5] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[6] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[0]),
        .Q(p_1_in124_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[7] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[1]),
        .Q(p_0_in123_in),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[8] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[2]),
        .Q(\ex_instr_reg_n_0_[8] ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \ex_instr_reg[9] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_gpr_op3_rd_addr[3]),
        .Q(\ex_instr_reg_n_0_[9] ),
        .R(1'b0));
  FDRE ex_is_div_instr_I_reg
       (.C(Clk),
        .CE(1'b1),
        .D(PreFetch_Buffer_I1_n_50),
        .Q(EX_Is_Div_Instr),
        .R(1'b0));
  FDRE ex_is_multi_instr2_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_MSR1),
        .Q(ex_is_multi_instr2),
        .R(reset_bool_for_rst));
  FDRE ex_is_multi_or_load_instr_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_is_multi_or_load_instr0),
        .Q(ex_is_multi_or_load_instr),
        .R(reset_bool_for_rst));
  FDRE ex_jump_hold_reg
       (.C(Clk),
        .CE(1'b1),
        .D(jump_logic_I1_n_6),
        .Q(ex_jump_hold),
        .R(1'b0));
  FDRE ex_jump_nodelay_reg
       (.C(Clk),
        .CE(1'b1),
        .D(\Use_MuxCy[11].OF_Piperun_Stage_n_1 ),
        .Q(ex_jump_nodelay),
        .R(1'b0));
  FDRE ex_load_alu_carry_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(PreFetch_Buffer_I1_n_189),
        .Q(ex_load_alu_carry_reg_0),
        .R(reset_bool_for_rst));
  FDRE ex_load_shift_carry_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_load_shift_carry0),
        .Q(ex_load_shift_carry),
        .R(reset_bool_for_rst));
  FDRE ex_mbar_decode_reg
       (.C(Clk),
        .CE(1'b1),
        .D(ex_mbar_decode_cmb),
        .Q(ex_mbar_decode),
        .R(reset_bool_for_rst));
  FDRE ex_mbar_is_sleep_reg
       (.C(Clk),
        .CE(1'b1),
        .D(ex_mbar_is_sleep_cmb),
        .Q(ex_mbar_is_sleep),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'h000000000000EAAA)) 
    ex_mbar_sleep_i_1
       (.I0(ex_mbar_sleep),
        .I1(ex_mbar_is_sleep),
        .I2(p_232_in),
        .I3(ex_first_cycle),
        .I4(active_wakeup),
        .I5(reset_bool_for_rst),
        .O(ex_mbar_sleep_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT4 #(
    .INIT(16'hA200)) 
    ex_mbar_sleep_i_2
       (.I0(ex_mbar_decode),
        .I1(\Using_FPGA.Native_39 ),
        .I2(\Using_FPGA.Native_40 ),
        .I3(ex_valid),
        .O(p_232_in));
  FDRE ex_mbar_sleep_reg
       (.C(Clk),
        .CE(1'b1),
        .D(ex_mbar_sleep_i_1_n_0),
        .Q(ex_mbar_sleep),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'h4F44)) 
    ex_mbar_stall_no_sleep_1_i_1
       (.I0(\ex_gpr_write_addr_reg_n_0_[4] ),
        .I1(if_fetch_in_progress),
        .I2(I0),
        .I3(mem_valid_instr),
        .O(ex_mbar_stall_no_sleep_10));
  FDRE ex_mbar_stall_no_sleep_1_reg
       (.C(Clk),
        .CE(1'b1),
        .D(ex_mbar_stall_no_sleep_10),
        .Q(ex_mbar_stall_no_sleep_1),
        .R(reset_bool_for_rst));
  FDRE ex_mfsmsr_i_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_Sel_SPR_MSR88_out),
        .Q(ex_mfsmsr_i),
        .R(reset_bool_for_rst));
  FDRE ex_move_to_MSR_instr_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_move_to_MSR_instr93_out),
        .Q(ex_move_to_MSR_instr),
        .R(reset_bool_for_rst));
  FDRE \ex_opcode_reg[0] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[0]),
        .Q(ex_opcode[0]),
        .R(reset_bool_for_rst));
  FDRE \ex_opcode_reg[1] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[1]),
        .Q(ex_opcode[1]),
        .R(reset_bool_for_rst));
  FDRE \ex_opcode_reg[2] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[2]),
        .Q(ex_opcode[2]),
        .R(reset_bool_for_rst));
  FDRE \ex_opcode_reg[3] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[3]),
        .Q(ex_opcode[3]),
        .R(reset_bool_for_rst));
  FDRE \ex_opcode_reg[4] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[4]),
        .Q(ex_opcode[4]),
        .R(reset_bool_for_rst));
  FDRE \ex_opcode_reg[5] 
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_instr[5]),
        .Q(ex_opcode[5]),
        .R(reset_bool_for_rst));
  FDRE ex_read_imm_reg_1_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_read_imm_reg),
        .Q(ex_read_imm_reg_1),
        .R(reset_bool_for_rst));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT5 #(
    .INIT(32'h00002AAA)) 
    ex_read_imm_reg_i_1
       (.I0(of_read_imm_reg_ii),
        .I1(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I3(wb_exception),
        .I4(\mem_pc_i_reg[0]_0 ),
        .O(ex_read_imm_reg_i_1_n_0));
  FDRE ex_read_imm_reg_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_read_imm_reg_i_1_n_0),
        .Q(ex_read_imm_reg),
        .R(reset_bool_for_rst));
  FDSE ex_sel_alu_i_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_sel_alu_i0),
        .Q(ex_sel_alu),
        .S(reset_bool_for_rst));
  FDRE ex_set_bip_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_set_bip),
        .Q(ex_set_bip_reg_0),
        .R(reset_bool_for_rst));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT1 #(
    .INIT(2'h1)) 
    ex_sleep_i_i_1
       (.I0(p_0_in123_in),
        .O(ex_sleep_i_i_1_n_0));
  FDRE ex_sleep_i_reg
       (.C(Clk),
        .CE(ex_sleep_i0),
        .D(ex_sleep_i_i_1_n_0),
        .Q(Sleep_Decode),
        .R(ex_hibernate_i_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT2 #(
    .INIT(4'h8)) 
    ex_suspend_i_i_1
       (.I0(p_0_in123_in),
        .I1(p_1_in124_in),
        .O(ex_suspend_i0));
  FDRE ex_suspend_i_reg
       (.C(Clk),
        .CE(ex_sleep_i0),
        .D(ex_suspend_i0),
        .Q(Suspend),
        .R(ex_hibernate_i_i_1_n_0));
  (* KEEP = "yes" *) 
  (* equivalent_register_removal = "no" *) 
  FDRE ex_valid_jump_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_next_ex_valid),
        .Q(ex_valid_jump),
        .R(\Use_MuxCy[11].OF_Piperun_Stage_n_3 ));
  FDRE ex_valid_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(of_next_ex_valid),
        .Q(ex_valid),
        .R(\Use_MuxCy[11].OF_Piperun_Stage_n_3 ));
  LUT6 #(
    .INIT(64'hF3B3B3B300808080)) 
    exception_i_2
       (.I0(if_missed_fetch_reg_1),
        .I1(wb_valid_reg_0),
        .I2(wb_exception),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I4(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I5(exception_reg),
        .O(\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg ));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(of_Sel_SPR_FSR));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(of_Sel_SPR_SHR));
  LUT1 #(
    .INIT(2'h2)) 
    i_10
       (.I0(1'b0),
        .O(of_PVR_Select[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_11
       (.I0(1'b0),
        .O(of_PVR_Select[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(of_Sel_SPR_EAR));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(of_Sel_SPR_SLR));
  LUT1 #(
    .INIT(2'h2)) 
    i_4
       (.I0(1'b0),
        .O(of_Sel_SPR_EDR));
  LUT1 #(
    .INIT(2'h2)) 
    i_5
       (.I0(1'b0),
        .O(of_Sel_SPR_ESR));
  LUT1 #(
    .INIT(2'h2)) 
    i_6
       (.I0(1'b0),
        .O(of_Sel_SPR_PVR));
  LUT1 #(
    .INIT(2'h2)) 
    i_7
       (.I0(1'b0),
        .O(of_Sel_SPR_BTR));
  LUT1 #(
    .INIT(2'h2)) 
    i_8
       (.I0(1'b0),
        .O(of_PVR_Select[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_9
       (.I0(1'b0),
        .O(of_PVR_Select[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFEAAA)) 
    if_fetch_in_progress_i_1
       (.I0(if_missed_fetch_reg_0),
        .I1(wb_exception),
        .I2(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .I3(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .I4(if_missed_fetch_reg_1),
        .I5(reset_bool_for_rst),
        .O(if_fetch_in_progress_i_1_n_0));
  FDRE if_fetch_in_progress_reg
       (.C(Clk),
        .CE(1'b1),
        .D(PreFetch_Buffer_I1_n_182),
        .Q(if_fetch_in_progress),
        .R(if_fetch_in_progress_i_1_n_0));
  FDRE if_missed_fetch_reg
       (.C(Clk),
        .CE(1'b1),
        .D(PreFetch_Buffer_I1_n_183),
        .Q(if_missed_fetch),
        .R(if_fetch_in_progress_i_1_n_0));
  design_1_microblaze_0_0_carry_and_87 if_pc_incr_carry_and_0
       (.if_missed_fetch(if_missed_fetch),
        .if_pc_incr_carry0(if_pc_incr_carry0),
        .lopt(lopt_3),
        .lopt_1(lopt_4),
        .lopt_10(lopt_31),
        .lopt_11(lopt_32),
        .lopt_12(lopt_33),
        .lopt_13(lopt_34),
        .lopt_14(lopt_35),
        .lopt_15(lopt_36),
        .lopt_16(lopt_37),
        .lopt_17(lopt_38),
        .lopt_18(lopt_39),
        .lopt_19(lopt_40),
        .lopt_2(\Using_FPGA.Native_36 ),
        .lopt_20(lopt_41),
        .lopt_21(lopt_42),
        .lopt_22(lopt_43),
        .lopt_23(lopt_44),
        .lopt_24(lopt_45),
        .lopt_25(lopt_46),
        .lopt_3(lopt_5),
        .lopt_4(lopt_6),
        .lopt_5(if_fetch_for_timing_optimization1),
        .lopt_6(lopt_7),
        .lopt_7(lopt_8),
        .lopt_8(lopt_9),
        .lopt_9(lopt_10));
  design_1_microblaze_0_0_carry_and_88 if_pc_incr_carry_and_3
       (.CI(if_pc_incr_carry3),
        .if_fetch_for_timing_optimization1(if_fetch_for_timing_optimization1),
        .if_pc_incr_carry1(if_pc_incr_carry1),
        .lopt(lopt_5),
        .lopt_1(lopt_6));
  design_1_microblaze_0_0_jump_logic jump_logic_I1
       (.Clk(Clk),
        .E(\Using_FPGA.Native_1 ),
        .EX_MBAR_Stall__1(EX_MBAR_Stall__1),
        .I5(I5),
        .O(O87_out),
        .O56_out(O56_out),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [3:2]),
        .\Using_FPGA.Native (jump_logic_I1_n_42),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_35 ),
        .\Using_FPGA.Native_1 (PreFetch_Buffer_I1_n_190),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_37 ),
        .ex_Exception_Taken(ex_Exception_Taken),
        .ex_branch_with_delayslot(ex_branch_with_delayslot),
        .ex_databus_addr(ex_databus_addr),
        .ex_delayslot_Instr0(ex_delayslot_Instr0),
        .ex_first_cycle(ex_first_cycle),
        .ex_jump(ex_jump),
        .ex_jump_hold(ex_jump_hold),
        .ex_jump_hold_reg(jump_logic_I1_n_6),
        .ex_jump_nodelay(ex_jump_nodelay),
        .ex_jump_q(ex_jump_q),
        .ex_mbar_decode(ex_mbar_decode),
        .ex_mbar_sleep(ex_mbar_sleep),
        .ex_mbar_stall_no_sleep_1(ex_mbar_stall_no_sleep_1),
        .ex_op1_cmp_eq1(ex_op1_cmp_eq1),
        .ex_op1_cmp_eq_n5_out(ex_op1_cmp_eq_n5_out),
        .ex_op1_cmp_eq_reg_0(PreFetch_Buffer_I1_n_56),
        .ex_op1_cmp_equal(ex_op1_cmp_equal),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .ex_op1_zero(ex_op1_zero),
        .force12_out(force12_out),
        .force_Val10_out(force_Val10_out),
        .force_Val2_N_reg_0(PreFetch_Buffer_I1_n_59),
        .\if_pc_reg[0] (\Performance_Debug_Control.dbg_state_nohalt_reg [156:125]),
        .\if_pc_reg[0]_0 (\MEM_DataBus_Addr_reg[0]_0 [70:41]),
        .\if_pc_reg[10] (O49_out),
        .\if_pc_reg[11] (O51_out),
        .\if_pc_reg[12] (O53_out),
        .\if_pc_reg[13] (O55_out),
        .\if_pc_reg[14] (O57_out),
        .\if_pc_reg[15] (O59_out),
        .\if_pc_reg[16] (O61_out),
        .\if_pc_reg[17] (O63_out),
        .\if_pc_reg[18] (O65_out),
        .\if_pc_reg[19] (O67_out),
        .\if_pc_reg[1] (O31_out),
        .\if_pc_reg[20] (O69_out),
        .\if_pc_reg[21] (O71_out),
        .\if_pc_reg[22] (O73_out),
        .\if_pc_reg[23] (O75_out),
        .\if_pc_reg[24] (O77_out),
        .\if_pc_reg[25] (O79_out),
        .\if_pc_reg[26] (O81_out),
        .\if_pc_reg[27] (O83_out),
        .\if_pc_reg[28] (O85_out),
        .\if_pc_reg[2] (O33_out),
        .\if_pc_reg[30] ({p_1_in3_in,PC_Module_I_n_35}),
        .\if_pc_reg[3] (O35_out),
        .\if_pc_reg[4] (O37_out),
        .\if_pc_reg[5] (O39_out),
        .\if_pc_reg[6] (O41_out),
        .\if_pc_reg[7] (O43_out),
        .\if_pc_reg[8] (O45_out),
        .\if_pc_reg[9] (O47_out),
        .keep_jump_taken_with_ds(keep_jump_taken_with_ds),
        .keep_jump_taken_with_ds_reg(jump_logic_I1_n_8),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_2(lopt_2),
        .mem_exception_from_ex(mem_exception_from_ex),
        .mem_jump_taken0(mem_jump_taken0),
        .mem_valid_instr(mem_valid_instr),
        .of_next_ex_valid(of_next_ex_valid),
        .of_valid(of_valid),
        .out(ex_valid_jump),
        .sync_reset(reset_bool_for_rst),
        .use_Reg_Neg_DI1_out(use_Reg_Neg_DI1_out),
        .use_Reg_Neg_S3_out(use_Reg_Neg_S3_out),
        .use_Reg_Neg_S_reg_0(of_PipeRun_for_ce),
        .wb_exception(wb_exception));
  FDRE keep_jump_taken_with_ds_reg
       (.C(Clk),
        .CE(1'b1),
        .D(jump_logic_I1_n_8),
        .Q(keep_jump_taken_with_ds),
        .R(1'b0));
  design_1_microblaze_0_0_carry_and_89 mem_PipeRun_carry_and
       (.E(\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native (\Using_FPGA.Native_0 ),
        .flush_pipe(flush_pipe),
        .lopt(lopt_11),
        .lopt_1(lopt_12),
        .lopt_2(lopt_13),
        .mem_exception_from_ex(mem_exception_from_ex),
        .mem_gpr_write(mem_gpr_write),
        .mem_gpr_write_dbg(mem_gpr_write_dbg),
        .mem_valid_instr(mem_valid_instr),
        .mem_valid_reg(mem_PipeRun_carry_and_n_1),
        .mem_valid_reg_0(ex_valid),
        .mem_wait_on_ready_N(mem_wait_on_ready_N),
        .sync_reset(reset_bool_for_rst),
        .wb_exception(wb_exception),
        .wb_gpr_write_dbg0(wb_gpr_write_dbg0),
        .wb_gpr_write_i0(wb_gpr_write_i0),
        .wb_valid_reg(mem_PipeRun_carry_and_n_2),
        .wb_valid_reg_0(wb_valid_reg_0),
        .wb_valid_reg_1(wb_PipeRun_i_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT5 #(
    .INIT(32'h00000888)) 
    mem_Write_DCache_i_1
       (.I0(ex_write_dcache_instr),
        .I1(p_231_in),
        .I2(mem_exception_from_ex),
        .I3(mem_valid_instr),
        .I4(wb_exception),
        .O(mem_Write_DCache_i_1_n_0));
  FDRE mem_Write_DCache_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(mem_Write_DCache_i_1_n_0),
        .Q(mem_Write_DCache),
        .R(reset_bool_for_rst));
  FDRE mem_byte_access_i_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_byte_access),
        .Q(mem_byte_access),
        .R(reset_bool_for_rst));
  FDRE mem_delayslot_instr_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_delayslot_Instr),
        .Q(mem_delayslot_instr),
        .R(reset_bool_for_rst));
  FDRE mem_doublet_access_i_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_doublet_access),
        .Q(mem_doublet_access),
        .R(reset_bool_for_rst));
  FDRE mem_exception_from_ex_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_Exception_Taken),
        .Q(mem_exception_from_ex),
        .R(reset_bool_for_rst));
  FDRE \mem_gpr_write_addr_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_gpr_write_addr_reg_n_0_[0] ),
        .Q(mem_gpr_write_addr[0]),
        .R(reset_bool_for_rst));
  FDRE \mem_gpr_write_addr_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(I2),
        .Q(mem_gpr_write_addr[1]),
        .R(reset_bool_for_rst));
  FDRE \mem_gpr_write_addr_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(I4),
        .Q(mem_gpr_write_addr[2]),
        .R(reset_bool_for_rst));
  FDRE \mem_gpr_write_addr_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(I0),
        .Q(mem_gpr_write_addr[3]),
        .R(reset_bool_for_rst));
  FDRE \mem_gpr_write_addr_reg[4] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_gpr_write_addr_reg_n_0_[4] ),
        .Q(mem_gpr_write_addr[4]),
        .R(reset_bool_for_rst));
  FDRE mem_gpr_write_dbg_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_gpr_write_dbg__0),
        .Q(mem_gpr_write_dbg),
        .R(flush_pipe));
  LUT2 #(
    .INIT(4'hE)) 
    mem_gpr_write_i_1
       (.I0(reset_bool_for_rst),
        .I1(wb_exception),
        .O(flush_pipe));
  FDRE mem_gpr_write_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_gpr_write_reg_n_0),
        .Q(mem_gpr_write),
        .R(flush_pipe));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[0] ),
        .Q(mem_instr[0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[10] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[10] ),
        .Q(mem_instr[10]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[11] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[11] ),
        .Q(mem_instr[11]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[12] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[12] ),
        .Q(mem_instr[12]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[13] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[13] ),
        .Q(mem_instr[13]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[14] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[14] ),
        .Q(mem_instr[14]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[15] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[15] ),
        .Q(mem_instr[15]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[16] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[16] ),
        .Q(mem_instr[16]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[17] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[17] ),
        .Q(mem_instr[17]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[18] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[18] ),
        .Q(mem_instr[18]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[19] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[19] ),
        .Q(mem_instr[19]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[1] ),
        .Q(mem_instr[1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[20] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[20] ),
        .Q(mem_instr[20]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[21] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[21] ),
        .Q(mem_instr[21]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[22] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[22] ),
        .Q(mem_instr[22]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[23] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[23] ),
        .Q(mem_instr[23]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[24] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[24] ),
        .Q(mem_instr[24]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[25] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[25] ),
        .Q(mem_instr[25]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[26] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[26] ),
        .Q(mem_instr[26]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[27] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[27] ),
        .Q(mem_instr[27]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[28] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[28] ),
        .Q(mem_instr[28]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[29] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[29] ),
        .Q(mem_instr[29]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[2] ),
        .Q(mem_instr[2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[30] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[30] ),
        .Q(mem_instr[30]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[31] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[31] ),
        .Q(mem_instr[31]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[3] ),
        .Q(mem_instr[3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[4] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[4] ),
        .Q(mem_instr[4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[5] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[5] ),
        .Q(mem_instr[5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[6] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(p_1_in124_in),
        .Q(mem_instr[6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[7] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(p_0_in123_in),
        .Q(mem_instr[7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[8] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[8] ),
        .Q(mem_instr[8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \mem_instr_reg[9] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\ex_instr_reg_n_0_[9] ),
        .Q(mem_instr[9]),
        .R(1'b0));
  FDRE mem_is_msr_instr_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_mfsmsr_i),
        .Q(mem_sel_msr),
        .R(reset_bool_for_rst));
  FDRE mem_is_multi_or_load_instr_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(mem_is_multi_or_load_instr0),
        .Q(mem_is_multi_or_load_instr),
        .R(reset_bool_for_rst));
  FDRE mem_jump_taken_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(mem_jump_taken0),
        .Q(mem_jump_taken),
        .R(reset_bool_for_rst));
  FDRE mem_load_store_access_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(mem_load_store_access0),
        .Q(mem_load_store_access),
        .R(reset_bool_for_rst));
  FDRE mem_read_imm_reg_1_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_read_imm_reg_1),
        .Q(mem_read_imm_reg_1),
        .R(reset_bool_for_rst));
  FDRE mem_read_imm_reg_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(ex_read_imm_reg),
        .Q(mem_read_imm_reg),
        .R(reset_bool_for_rst));
  FDRE mem_valid_reg
       (.C(Clk),
        .CE(1'b1),
        .D(mem_PipeRun_carry_and_n_1),
        .Q(mem_valid_instr),
        .R(1'b0));
  design_1_microblaze_0_0_carry_or mem_wait_on_ready_N_carry_or
       (.MEM_DataBus_Ready(MEM_DataBus_Ready),
        .lopt(lopt_11),
        .lopt_1(lopt_12),
        .lopt_10(lopt_48),
        .lopt_11(lopt_49),
        .lopt_12(lopt_50),
        .lopt_13(lopt_24),
        .lopt_14(lopt_22),
        .lopt_15(lopt_20),
        .lopt_16(lopt_51),
        .lopt_17(\Using_FPGA_4.of_read_mem_write_op1_conflict_INST1_n_0 ),
        .lopt_18(A),
        .lopt_19(PreFetch_Buffer_I1_n_191),
        .lopt_2(lopt_13),
        .lopt_20(lopt_52),
        .lopt_3(lopt_14),
        .lopt_4(lopt_15),
        .lopt_5(lopt_16),
        .lopt_6(lopt_17),
        .lopt_7(lopt_18),
        .lopt_8(jump_logic_I1_n_42),
        .lopt_9(lopt_47),
        .mem_Write_DCache(mem_Write_DCache),
        .mem_load_store_access(mem_load_store_access),
        .mem_valid_instr(mem_valid_instr),
        .mem_wait_on_ready_N(mem_wait_on_ready_N));
  FDRE of_pause_reg
       (.C(Clk),
        .CE(1'b1),
        .D(Pause),
        .Q(of_pause),
        .R(reset_bool_for_rst));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFEA)) 
    of_read_imm_reg_ii_i_2
       (.I0(LOCKSTEP_Master_Out[0]),
        .I1(mem_valid_instr),
        .I2(mem_exception_from_ex),
        .I3(wb_exception),
        .I4(reset_bool_for_rst),
        .I5(ex_Exception_Taken),
        .O(of_read_imm_reg_ii_i_2_n_0));
  FDRE of_read_imm_reg_ii_reg
       (.C(Clk),
        .CE(1'b1),
        .D(\Use_MuxCy[11].OF_Piperun_Stage_n_2 ),
        .Q(of_read_imm_reg_ii),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'h02)) 
    sign_byte_inferred_i_1
       (.I0(\Using_FPGA.Native_42 [7]),
        .I1(\EX_Sext_Op_reg[0]_0 [0]),
        .I2(\EX_Sext_Op_reg[0]_0 [1]),
        .O(in0));
  FDRE wb_PipeRun_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_0 ),
        .Q(wb_PipeRun_i_reg_0),
        .R(reset_bool_for_rst));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT2 #(
    .INIT(4'h8)) 
    wb_exception_i_i_1
       (.I0(mem_exception_from_ex),
        .I1(mem_valid_instr),
        .O(mem_Exception_Taken));
  FDRE wb_exception_i_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_Exception_Taken),
        .Q(wb_exception),
        .R(reset_bool_for_rst));
  FDRE \wb_exception_kind_i_reg[28] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_exception_kind[28]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [3]),
        .R(reset_bool_for_rst));
  FDRE \wb_exception_kind_i_reg[31] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_exception_kind[31]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [2]),
        .R(reset_bool_for_rst));
  FDRE \wb_gpr_write_addr_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_gpr_write_addr[0]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [33]),
        .R(reset_bool_for_rst));
  FDRE \wb_gpr_write_addr_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_gpr_write_addr[1]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [32]),
        .R(reset_bool_for_rst));
  FDRE \wb_gpr_write_addr_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_gpr_write_addr[2]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [31]),
        .R(reset_bool_for_rst));
  FDRE \wb_gpr_write_addr_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_gpr_write_addr[3]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [30]),
        .R(reset_bool_for_rst));
  FDRE \wb_gpr_write_addr_reg[4] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_gpr_write_addr[4]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [29]),
        .R(reset_bool_for_rst));
  FDRE wb_gpr_write_dbg_reg
       (.C(Clk),
        .CE(1'b1),
        .D(wb_gpr_write_dbg0),
        .Q(wb_gpr_wr_dbg),
        .R(1'b0));
  FDRE wb_gpr_write_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(wb_gpr_write_i0),
        .Q(wb_gpr_write_i),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[0]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [67]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[10] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[10]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [57]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[11] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[11]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [56]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[12] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[12]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [55]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[13] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[13]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [54]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[14] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[14]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [53]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[15] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[15]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [52]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[16] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[16]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [51]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[17] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[17]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [50]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[18] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[18]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [49]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[19] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[19]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [48]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[1]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [66]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[20] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[20]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [47]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[21] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[21]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [46]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[22] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[22]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [45]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[23] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[23]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [44]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[24] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[24]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [43]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[25] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[25]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [42]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[26] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[26]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [41]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[27] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[27]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [40]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[28] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[28]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [39]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[29] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[29]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [38]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[2]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [65]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[30] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[30]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [37]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[31] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[31]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [36]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[3]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [64]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[4] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[4]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [63]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[5] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[5]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [62]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[6] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[6]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [61]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[7] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[7]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [60]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[8] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[8]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [59]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \wb_instr_reg[9] 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(mem_instr[9]),
        .Q(\Performance_Debug_Control.dbg_state_nohalt_reg [58]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    wb_reset_reg
       (.C(Clk),
        .CE(1'b1),
        .D(reset_bool_for_rst),
        .Q(wb_reset),
        .R(1'b0));
  FDRE wb_valid_reg
       (.C(Clk),
        .CE(1'b1),
        .D(mem_PipeRun_carry_and_n_2),
        .Q(wb_valid_reg_0),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_AND2B1L" *) 
module design_1_microblaze_0_0_MB_AND2B1L
   (D,
    E,
    SRI);
  output [0:0]D;
  input [0:0]E;
  input SRI;

  wire [0:0]D;
  wire [0:0]E;
  wire SRI;

  (* box_type = "PRIMITIVE" *) 
  AND2B1L #(
    .IS_SRI_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.DI(E),
        .O(D),
        .SRI(SRI));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output [0:0]\Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_311
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_314
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_317
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_320
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_323
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_326
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_329
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_332
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_335
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_338
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_341
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_344
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_347
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_350
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_353
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_356
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_359
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_362
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_365
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_368
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_371
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_374
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_377
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_380
   (DI,
    \Using_FPGA.Native_0 ,
    O5,
    Clk);
  output DI;
  input \Using_FPGA.Native_0 ;
  input O5;
  input Clk;

  wire Clk;
  wire DI;
  wire O5;
  wire \Using_FPGA.Native_0 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(O5),
        .Q(DI),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_383
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_386
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_389
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_392
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_395
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_398
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDE" *) 
module design_1_microblaze_0_0_MB_FDE_401
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    Clk);
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* XILINX_LEGACY_PRIM = "FDE" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(\Using_FPGA.Native_2 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR
   (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg ,
    sync_reset,
    Clk,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    I0,
    Q,
    E,
    \Using_FPGA.Native_3 );
  output \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ;
  input sync_reset;
  input Clk;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input I0;
  input [5:0]Q;
  input [0:0]E;
  input \Using_FPGA.Native_3 ;

  wire Clk;
  wire [0:0]E;
  wire I0;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ;
  wire [5:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_i_1__95_n_0 ;
  wire of_clear_MSR_BIP__0;
  wire of_clear_MSR_BIP_hold_s;
  wire of_set_MSR_EE1;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_i_1__95_n_0 ),
        .Q(of_clear_MSR_BIP_hold_s),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'hFFFFFFFFA2000000)) 
    \Using_FPGA.Native_i_1__7 
       (.I0(of_set_MSR_EE1),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(I0),
        .I5(of_clear_MSR_BIP_hold_s),
        .O(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg ));
  LUT4 #(
    .INIT(16'h00EA)) 
    \Using_FPGA.Native_i_1__95 
       (.I0(of_clear_MSR_BIP_hold_s),
        .I1(of_clear_MSR_BIP__0),
        .I2(E),
        .I3(\Using_FPGA.Native_3 ),
        .O(\Using_FPGA.Native_i_1__95_n_0 ));
  LUT5 #(
    .INIT(32'h80880000)) 
    \Using_FPGA.Native_i_2__23 
       (.I0(I0),
        .I1(\Using_FPGA.Native_2 ),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_0 ),
        .I4(of_set_MSR_EE1),
        .O(of_clear_MSR_BIP__0));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    \Using_FPGA.Native_i_2__82 
       (.I0(Q[1]),
        .I1(Q[4]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[5]),
        .I5(Q[2]),
        .O(of_set_MSR_EE1));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE
   (D,
    sync_reset,
    E,
    ex_exception_no_load_store_mask,
    Clk,
    mem_exception_from_ex);
  output [0:0]D;
  input sync_reset;
  input [0:0]E;
  input ex_exception_no_load_store_mask;
  input Clk;
  input mem_exception_from_ex;

  wire Clk;
  wire [0:0]D;
  wire [0:0]E;
  wire Q2_out;
  wire ex_exception_no_load_store_mask;
  wire mem_exception_from_ex;
  wire sync_reset;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(E),
        .D(ex_exception_no_load_store_mask),
        .Q(Q2_out),
        .R(sync_reset));
  LUT2 #(
    .INIT(4'h8)) 
    \wb_exception_kind_i[28]_i_1 
       (.I0(mem_exception_from_ex),
        .I1(Q2_out),
        .O(D));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_456
   (\Using_FPGA.Native_0 ,
    R,
    \Using_FPGA.Native_1 ,
    EX_Fwd,
    Clk);
  output [0:0]\Using_FPGA.Native_0 ;
  input R;
  input \Using_FPGA.Native_1 ;
  input [0:0]EX_Fwd;
  input Clk;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire R;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(EX_Fwd),
        .Q(\Using_FPGA.Native_0 ),
        .R(R));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_457
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [10:10]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[10]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_458
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [11:11]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[11]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_459
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [12:12]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[12]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_460
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [13:13]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[13]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_461
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [14:14]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[14]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_462
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [15:15]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[15]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_463
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [16:16]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[16]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_464
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [17:17]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[17]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_465
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [18:18]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[18]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_466
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [19:19]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[19]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_467
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [1:1]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[1]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_468
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [20:20]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[20]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_469
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [21:21]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[21]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_470
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [22:22]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[22]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_471
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [23:23]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[23]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_472
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [24:24]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[24]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_473
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [25:25]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[25]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_474
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [26:26]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[26]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_475
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [27:27]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[27]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_476
   (\Using_FPGA.Native_0 ,
    R,
    \Using_FPGA.Native_1 ,
    EX_Fwd,
    Clk);
  output [0:0]\Using_FPGA.Native_0 ;
  input R;
  input \Using_FPGA.Native_1 ;
  input [0:0]EX_Fwd;
  input Clk;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire R;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(EX_Fwd),
        .Q(\Using_FPGA.Native_0 ),
        .R(R));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_477
   (\Using_FPGA.Native_0 ,
    R,
    \Using_FPGA.Native_1 ,
    EX_Fwd,
    Clk);
  output [0:0]\Using_FPGA.Native_0 ;
  input R;
  input \Using_FPGA.Native_1 ;
  input [0:0]EX_Fwd;
  input Clk;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire R;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(EX_Fwd),
        .Q(\Using_FPGA.Native_0 ),
        .R(R));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_478
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [2:2]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[2]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_479
   (\Using_FPGA.Native_0 ,
    R,
    \Using_FPGA.Native_1 ,
    EX_Fwd,
    Clk);
  output [0:0]\Using_FPGA.Native_0 ;
  input R;
  input \Using_FPGA.Native_1 ;
  input [0:0]EX_Fwd;
  input Clk;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire R;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_1 ),
        .D(EX_Fwd),
        .Q(\Using_FPGA.Native_0 ),
        .R(R));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_480
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [31:31]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[31]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_481
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [3:3]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[3]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_482
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [4:4]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[4]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_483
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [5:5]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[5]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_484
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [6:6]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[6]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_485
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [7:7]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[7]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_486
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [8:8]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[8]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_487
   (MEM_Fwd,
    R,
    \Using_FPGA.Native_0 ,
    EX_Fwd,
    Clk,
    mem_sel_msr);
  output [0:0]MEM_Fwd;
  input R;
  input \Using_FPGA.Native_0 ;
  input [0:0]EX_Fwd;
  input Clk;
  input mem_sel_msr;

  wire Clk;
  wire [0:0]EX_Fwd;
  wire [9:9]MEM_EX_Result;
  wire [0:0]MEM_Fwd;
  wire R;
  wire \Using_FPGA.Native_0 ;
  wire mem_sel_msr;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(EX_Fwd),
        .Q(MEM_EX_Result),
        .R(R));
  LUT2 #(
    .INIT(4'h2)) 
    \WB_MEM_Result[9]_i_1 
       (.I0(MEM_EX_Result),
        .I1(mem_sel_msr),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_67
   (D,
    sync_reset,
    E,
    ex_exception_no_load_store_mask,
    Clk,
    mem_exception_from_ex);
  output [0:0]D;
  input sync_reset;
  input [0:0]E;
  input ex_exception_no_load_store_mask;
  input Clk;
  input mem_exception_from_ex;

  wire Clk;
  wire [0:0]D;
  wire [0:0]E;
  wire \Using_FPGA.Native_n_0 ;
  wire ex_exception_no_load_store_mask;
  wire mem_exception_from_ex;
  wire sync_reset;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(E),
        .D(ex_exception_no_load_store_mask),
        .Q(\Using_FPGA.Native_n_0 ),
        .R(sync_reset));
  LUT2 #(
    .INIT(4'h8)) 
    \wb_exception_kind_i[31]_i_1 
       (.I0(mem_exception_from_ex),
        .I1(\Using_FPGA.Native_n_0 ),
        .O(D));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_68
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    Clk,
    \MEM_DataBus_Write_Data_reg[0] ,
    \MEM_DataBus_Write_Data_reg[0]_0 ,
    \MEM_DataBus_Write_Data_reg[0]_1 );
  output \Using_FPGA.Native_0 ;
  output [23:0]\Using_FPGA.Native_1 ;
  input sync_reset;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input Clk;
  input [31:0]\MEM_DataBus_Write_Data_reg[0] ;
  input \MEM_DataBus_Write_Data_reg[0]_0 ;
  input \MEM_DataBus_Write_Data_reg[0]_1 ;

  wire Clk;
  wire [31:0]\MEM_DataBus_Write_Data_reg[0] ;
  wire \MEM_DataBus_Write_Data_reg[0]_0 ;
  wire \MEM_DataBus_Write_Data_reg[0]_1 ;
  wire \Using_FPGA.Native_0 ;
  wire [23:0]\Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire sync_reset;

  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[0]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [15]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [7]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [31]),
        .O(\Using_FPGA.Native_1 [23]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[10]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [5]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [13]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [21]),
        .O(\Using_FPGA.Native_1 [13]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[11]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [4]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [12]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [20]),
        .O(\Using_FPGA.Native_1 [12]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[12]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [3]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [11]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [19]),
        .O(\Using_FPGA.Native_1 [11]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[13]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [2]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [10]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [18]),
        .O(\Using_FPGA.Native_1 [10]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[14]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [1]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [9]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [17]),
        .O(\Using_FPGA.Native_1 [9]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[15]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [0]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [8]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [16]),
        .O(\Using_FPGA.Native_1 [8]));
  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[1]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [14]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [6]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [30]),
        .O(\Using_FPGA.Native_1 [22]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[24]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [31]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [7]),
        .O(\Using_FPGA.Native_1 [7]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[25]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [30]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [6]),
        .O(\Using_FPGA.Native_1 [6]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[26]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [29]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [5]),
        .O(\Using_FPGA.Native_1 [5]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[27]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [28]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [4]),
        .O(\Using_FPGA.Native_1 [4]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[28]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [27]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [3]),
        .O(\Using_FPGA.Native_1 [3]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[29]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [26]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [2]),
        .O(\Using_FPGA.Native_1 [2]));
  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[2]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [13]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [5]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [29]),
        .O(\Using_FPGA.Native_1 [21]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[30]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [25]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [1]),
        .O(\Using_FPGA.Native_1 [1]));
  LUT4 #(
    .INIT(16'hEF40)) 
    \Data_Write[31]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [24]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [0]),
        .O(\Using_FPGA.Native_1 [0]));
  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[3]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [12]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [4]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [28]),
        .O(\Using_FPGA.Native_1 [20]));
  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[4]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [11]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [3]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [27]),
        .O(\Using_FPGA.Native_1 [19]));
  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[5]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [10]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [2]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [26]),
        .O(\Using_FPGA.Native_1 [18]));
  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[6]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [9]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [1]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [25]),
        .O(\Using_FPGA.Native_1 [17]));
  LUT6 #(
    .INIT(64'hFF00EF45FF00EA40)) 
    \Data_Write[7]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [8]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [0]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [24]),
        .O(\Using_FPGA.Native_1 [16]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[8]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [7]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [15]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [23]),
        .O(\Using_FPGA.Native_1 [15]));
  LUT6 #(
    .INIT(64'hDD88CDCDDD88C8C8)) 
    \Data_Write[9]_INST_0 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\MEM_DataBus_Write_Data_reg[0] [6]),
        .I2(\MEM_DataBus_Write_Data_reg[0]_1 ),
        .I3(\MEM_DataBus_Write_Data_reg[0] [14]),
        .I4(\MEM_DataBus_Write_Data_reg[0]_0 ),
        .I5(\MEM_DataBus_Write_Data_reg[0] [22]),
        .O(\Using_FPGA.Native_1 [14]));
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_2 ),
        .D(\Using_FPGA.Native_3 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_69
   (ex_doublet_access,
    sync_reset,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    Clk);
  output ex_doublet_access;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_doublet_access;
  wire sync_reset;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_doublet_access),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_70
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    mem_is_multi_or_load_instr0,
    ex_Sel_SPR_PVR_reg,
    sync_reset,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    Clk,
    ex_load_store_instr_s,
    ex_reservation,
    ex_is_swx_instr_s,
    p_231_in,
    ex_is_multi_instr2,
    ex_Sel_SPR_PVR,
    ex_Sel_SPR_BTR,
    ex_Sel_SPR_EDR,
    ex_Sel_SPR_ESR,
    ex_Sel_SPR_FSR,
    ex_Sel_SPR_SLR,
    ex_Sel_SPR_SHR,
    ex_Sel_SPR_EAR);
  output \Using_FPGA.Native_0 ;
  output [0:0]\Using_FPGA.Native_1 ;
  output mem_is_multi_or_load_instr0;
  output ex_Sel_SPR_PVR_reg;
  input sync_reset;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input Clk;
  input ex_load_store_instr_s;
  input ex_reservation;
  input ex_is_swx_instr_s;
  input p_231_in;
  input ex_is_multi_instr2;
  input ex_Sel_SPR_PVR;
  input ex_Sel_SPR_BTR;
  input ex_Sel_SPR_EDR;
  input ex_Sel_SPR_ESR;
  input ex_Sel_SPR_FSR;
  input ex_Sel_SPR_SLR;
  input ex_Sel_SPR_SHR;
  input ex_Sel_SPR_EAR;

  wire Clk;
  wire MEM_Sel_MEM_Res_I_i_2_n_0;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire ex_Sel_SPR_BTR;
  wire ex_Sel_SPR_EAR;
  wire ex_Sel_SPR_EDR;
  wire ex_Sel_SPR_ESR;
  wire ex_Sel_SPR_FSR;
  wire ex_Sel_SPR_PVR;
  wire ex_Sel_SPR_PVR_reg;
  wire ex_Sel_SPR_SHR;
  wire ex_Sel_SPR_SLR;
  wire ex_is_multi_instr2;
  wire ex_is_swx_instr_s;
  wire ex_load_store_instr_s;
  wire ex_reservation;
  wire mem_is_multi_or_load_instr0;
  wire p_231_in;
  wire sync_reset;

  LUT6 #(
    .INIT(64'h0000000000000001)) 
    MEM_Sel_MEM_Res_I_i_1
       (.I0(ex_Sel_SPR_PVR),
        .I1(ex_Sel_SPR_BTR),
        .I2(MEM_Sel_MEM_Res_I_i_2_n_0),
        .I3(ex_Sel_SPR_EDR),
        .I4(ex_Sel_SPR_ESR),
        .I5(ex_Sel_SPR_FSR),
        .O(ex_Sel_SPR_PVR_reg));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    MEM_Sel_MEM_Res_I_i_2
       (.I0(ex_Sel_SPR_SLR),
        .I1(\Using_FPGA.Native_0 ),
        .I2(ex_Sel_SPR_SHR),
        .I3(ex_Sel_SPR_EAR),
        .O(MEM_Sel_MEM_Res_I_i_2_n_0));
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_2 ),
        .D(\Using_FPGA.Native_3 ),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT5 #(
    .INIT(32'h40440000)) 
    Write_Strobe_INST_0
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_load_store_instr_s),
        .I2(ex_reservation),
        .I3(ex_is_swx_instr_s),
        .I4(p_231_in),
        .O(\Using_FPGA.Native_1 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'hE)) 
    mem_is_multi_or_load_instr_i_1
       (.I0(ex_is_multi_instr2),
        .I1(\Using_FPGA.Native_0 ),
        .O(mem_is_multi_or_load_instr0));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_71
   (ex_MSR_Load_LWX_SWX_C,
    \Using_LWX_SWX_instr.ex_reservation_reg ,
    sync_reset,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    Clk,
    ex_is_swx_instr_s,
    ex_load_store_instr_s,
    wb_exception,
    \Using_FPGA.Native_i_2__21 ,
    p_231_in,
    ex_reservation,
    p_227_in,
    \Using_LWX_SWX_instr.ex_reservation_reg_0 );
  output ex_MSR_Load_LWX_SWX_C;
  output \Using_LWX_SWX_instr.ex_reservation_reg ;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input Clk;
  input ex_is_swx_instr_s;
  input ex_load_store_instr_s;
  input wb_exception;
  input \Using_FPGA.Native_i_2__21 ;
  input p_231_in;
  input ex_reservation;
  input p_227_in;
  input \Using_LWX_SWX_instr.ex_reservation_reg_0 ;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_i_2__21 ;
  wire \Using_LWX_SWX_instr.ex_reservation_reg ;
  wire \Using_LWX_SWX_instr.ex_reservation_reg_0 ;
  wire ex_MSR_Load_LWX_SWX_C;
  wire ex_is_lwx_instr_s;
  wire ex_is_swx_instr_s;
  wire ex_load_store_instr_s;
  wire ex_reservation;
  wire p_227_in;
  wire p_231_in;
  wire sync_reset;
  wire wb_exception;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_is_lwx_instr_s),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'h000000E000000000)) 
    \Using_FPGA.Native_i_6 
       (.I0(ex_is_lwx_instr_s),
        .I1(ex_is_swx_instr_s),
        .I2(ex_load_store_instr_s),
        .I3(wb_exception),
        .I4(\Using_FPGA.Native_i_2__21 ),
        .I5(p_231_in),
        .O(ex_MSR_Load_LWX_SWX_C));
  LUT5 #(
    .INIT(32'h000000EA)) 
    \Using_LWX_SWX_instr.ex_reservation_i_1 
       (.I0(ex_reservation),
        .I1(ex_is_lwx_instr_s),
        .I2(p_227_in),
        .I3(\Using_LWX_SWX_instr.ex_reservation_reg_0 ),
        .I4(sync_reset),
        .O(\Using_LWX_SWX_instr.ex_reservation_reg ));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_72
   (ex_is_swx_instr_s,
    MEM_DataBus_Access_reg,
    ex_swx_access__0,
    SRI,
    wb_exception_i_reg,
    sync_reset,
    \Using_FPGA.Native_0 ,
    D224_out,
    Clk,
    MEM_DataBus_Access_reg_0,
    p_227_in,
    MEM_DataBus_Access_reg_1,
    E,
    ex_reservation,
    p_231_in,
    D_AS,
    wb_exception,
    ex_load_store_instr_s,
    \Using_LWX_SWX_instr.ex_reservation_reg ,
    ex_MSR_Set_SW_BIP);
  output ex_is_swx_instr_s;
  output MEM_DataBus_Access_reg;
  output ex_swx_access__0;
  output SRI;
  output wb_exception_i_reg;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input D224_out;
  input Clk;
  input MEM_DataBus_Access_reg_0;
  input p_227_in;
  input MEM_DataBus_Access_reg_1;
  input [0:0]E;
  input ex_reservation;
  input p_231_in;
  input D_AS;
  input wb_exception;
  input ex_load_store_instr_s;
  input \Using_LWX_SWX_instr.ex_reservation_reg ;
  input ex_MSR_Set_SW_BIP;

  wire Clk;
  wire D224_out;
  wire D_AS;
  wire [0:0]E;
  wire MEM_DataBus_Access_reg;
  wire MEM_DataBus_Access_reg_0;
  wire MEM_DataBus_Access_reg_1;
  wire SRI;
  wire \Using_FPGA.Native_0 ;
  wire \Using_LWX_SWX_instr.ex_reservation_reg ;
  wire ex_MSR_Set_SW_BIP;
  wire ex_is_swx_instr_s;
  wire ex_load_store_instr_s;
  wire ex_reservation;
  wire ex_swx_access__0;
  wire p_227_in;
  wire p_231_in;
  wire sync_reset;
  wire wb_exception;
  wire wb_exception_i_reg;

  LUT6 #(
    .INIT(64'h00000000C0C000AA)) 
    MEM_DataBus_Access_i_1
       (.I0(MEM_DataBus_Access_reg_0),
        .I1(ex_swx_access__0),
        .I2(p_227_in),
        .I3(MEM_DataBus_Access_reg_1),
        .I4(E),
        .I5(sync_reset),
        .O(MEM_DataBus_Access_reg));
  LUT2 #(
    .INIT(4'hB)) 
    MEM_DataBus_Access_i_2
       (.I0(ex_reservation),
        .I1(ex_is_swx_instr_s),
        .O(ex_swx_access__0));
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(D224_out),
        .Q(ex_is_swx_instr_s),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'hFFFFFF4FFFFFFFFF)) 
    \Using_FPGA.Native_i_1__4 
       (.I0(ex_reservation),
        .I1(ex_is_swx_instr_s),
        .I2(p_231_in),
        .I3(D_AS),
        .I4(wb_exception),
        .I5(ex_load_store_instr_s),
        .O(SRI));
  LUT6 #(
    .INIT(64'hFFF2F2F2F2F2F2F2)) 
    \Using_LWX_SWX_instr.ex_reservation_i_3 
       (.I0(wb_exception),
        .I1(\Using_LWX_SWX_instr.ex_reservation_reg ),
        .I2(ex_MSR_Set_SW_BIP),
        .I3(ex_is_swx_instr_s),
        .I4(E),
        .I5(p_227_in),
        .O(wb_exception_i_reg));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_73
   (ex_load_store_instr_s,
    p_227_in,
    mem_load_store_access0,
    sync_reset,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    Clk,
    p_231_in,
    mem_valid_instr,
    mem_exception_from_ex,
    wb_exception,
    ex_reservation,
    ex_is_swx_instr_s,
    mem_load_store_access_reg,
    mem_load_store_access_reg_0,
    mem_load_store_access_reg_1);
  output ex_load_store_instr_s;
  output p_227_in;
  output mem_load_store_access0;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input Clk;
  input p_231_in;
  input mem_valid_instr;
  input mem_exception_from_ex;
  input wb_exception;
  input ex_reservation;
  input ex_is_swx_instr_s;
  input mem_load_store_access_reg;
  input mem_load_store_access_reg_0;
  input mem_load_store_access_reg_1;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_is_swx_instr_s;
  wire ex_load_store_instr_s;
  wire ex_reservation;
  wire mem_exception_from_ex;
  wire mem_load_store_access0;
  wire mem_load_store_access_reg;
  wire mem_load_store_access_reg_0;
  wire mem_load_store_access_reg_1;
  wire mem_valid_instr;
  wire p_227_in;
  wire p_231_in;
  wire sync_reset;
  wire wb_exception;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_load_store_instr_s),
        .R(sync_reset));
  LUT5 #(
    .INIT(32'h002A0000)) 
    \Using_LWX_SWX_instr.ex_reservation_i_2 
       (.I0(p_231_in),
        .I1(mem_valid_instr),
        .I2(mem_exception_from_ex),
        .I3(wb_exception),
        .I4(ex_load_store_instr_s),
        .O(p_227_in));
  LUT6 #(
    .INIT(64'h8A8A8A8A008A8A8A)) 
    mem_load_store_access_i_1
       (.I0(ex_load_store_instr_s),
        .I1(ex_reservation),
        .I2(ex_is_swx_instr_s),
        .I3(mem_load_store_access_reg),
        .I4(mem_load_store_access_reg_0),
        .I5(mem_load_store_access_reg_1),
        .O(mem_load_store_access0));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_74
   (ex_reverse_mem_access,
    sync_reset,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    Clk);
  output ex_reverse_mem_access;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_reverse_mem_access;
  wire sync_reset;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_reverse_mem_access),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDRE" *) 
module design_1_microblaze_0_0_MB_FDRE_75
   (ex_set_bip_reg,
    sync_reset,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    Clk,
    \Using_FPGA.Native_2 ,
    p_231_in,
    \Using_FPGA.Native_3 ,
    E,
    ex_MSR);
  output ex_set_bip_reg;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input Clk;
  input \Using_FPGA.Native_2 ;
  input p_231_in;
  input \Using_FPGA.Native_3 ;
  input [0:0]E;
  input [0:0]ex_MSR;

  wire Clk;
  wire [0:0]E;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire [0:0]ex_MSR;
  wire ex_clear_MSR_BIP_instr_s;
  wire ex_set_bip_reg;
  wire p_231_in;
  wire sync_reset;

  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(\Using_FPGA.Native_0 ),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_clear_MSR_BIP_instr_s),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'hBFA0FFFFBFA00000)) 
    \Using_FPGA.Native_i_1__6 
       (.I0(\Using_FPGA.Native_2 ),
        .I1(ex_clear_MSR_BIP_instr_s),
        .I2(p_231_in),
        .I3(\Using_FPGA.Native_3 ),
        .I4(E),
        .I5(ex_MSR),
        .O(ex_set_bip_reg));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_112
   (addr,
    \Using_FPGA.Native_0 ,
    sync_reset,
    sel_input_iii_3,
    Clk,
    if_sel_input,
    ex_jump,
    out,
    IB_Ready,
    if_fetch_in_progress);
  output [0:0]addr;
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input sel_input_iii_3;
  input Clk;
  input [0:0]if_sel_input;
  input ex_jump;
  input out;
  input IB_Ready;
  input if_fetch_in_progress;

  wire Clk;
  wire IB_Ready;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]addr;
  wire ex_jump;
  wire if_fetch_in_progress;
  wire [0:0]if_sel_input;
  wire out;
  wire sel_input_iii_3;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(sel_input_iii_3),
        .Q(addr),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'hF100FFFFF100F100)) 
    if_fetch_in_progress_i_2
       (.I0(addr),
        .I1(if_sel_input),
        .I2(ex_jump),
        .I3(out),
        .I4(IB_Ready),
        .I5(if_fetch_in_progress),
        .O(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_113
   (if_sel_input,
    addr,
    if_fetch_in_progress_reg,
    \Using_FPGA.Native_0 ,
    if_fetch_for_timing_optimization1,
    if_missed_fetch_reg,
    sync_reset,
    sel_input_iii_2,
    Clk,
    \Serial_Dbg_Intf.status_reg_reg[25] ,
    ex_jump,
    out,
    if_fetch_in_progress,
    IB_Ready,
    in0,
    if_missed_fetch);
  output [0:0]if_sel_input;
  output [0:0]addr;
  output [0:0]if_fetch_in_progress_reg;
  output [1:0]\Using_FPGA.Native_0 ;
  output if_fetch_for_timing_optimization1;
  output if_missed_fetch_reg;
  input sync_reset;
  input sel_input_iii_2;
  input Clk;
  input [0:0]\Serial_Dbg_Intf.status_reg_reg[25] ;
  input ex_jump;
  input out;
  input if_fetch_in_progress;
  input IB_Ready;
  input in0;
  input if_missed_fetch;

  wire Clk;
  wire IB_Ready;
  wire [0:0]\Serial_Dbg_Intf.status_reg_reg[25] ;
  wire [1:0]\Using_FPGA.Native_0 ;
  wire [0:0]addr;
  wire ex_jump;
  wire if_fetch_for_timing_optimization1;
  wire if_fetch_in_progress;
  wire [0:0]if_fetch_in_progress_reg;
  wire if_missed_fetch;
  wire if_missed_fetch_reg;
  wire [0:0]if_sel_input;
  wire in0;
  wire out;
  wire sel_input_iii_2;
  wire sync_reset;

  LUT5 #(
    .INIT(32'hFFFFAB00)) 
    IFetch_INST_0
       (.I0(ex_jump),
        .I1(if_sel_input),
        .I2(\Serial_Dbg_Intf.status_reg_reg[25] ),
        .I3(in0),
        .I4(if_fetch_in_progress),
        .O(\Using_FPGA.Native_0 [1]));
  LUT6 #(
    .INIT(64'hA200A200A200A2A2)) 
    I_AS_INST_0
       (.I0(out),
        .I1(if_fetch_in_progress),
        .I2(IB_Ready),
        .I3(ex_jump),
        .I4(if_sel_input),
        .I5(\Serial_Dbg_Intf.status_reg_reg[25] ),
        .O(\Using_FPGA.Native_0 [0]));
  LUT2 #(
    .INIT(4'h2)) 
    \PC_Buffer_reg[3][31]_srl4_i_2 
       (.I0(if_sel_input),
        .I1(\Serial_Dbg_Intf.status_reg_reg[25] ),
        .O(addr));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(sel_input_iii_2),
        .Q(if_sel_input),
        .R(sync_reset));
  LUT2 #(
    .INIT(4'h1)) 
    \Using_FPGA.Native_i_1 
       (.I0(if_sel_input),
        .I1(\Serial_Dbg_Intf.status_reg_reg[25] ),
        .O(if_fetch_for_timing_optimization1));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h1310)) 
    if_missed_fetch_i_1
       (.I0(IB_Ready),
        .I1(\Using_FPGA.Native_0 [0]),
        .I2(if_missed_fetch),
        .I3(ex_jump),
        .O(if_missed_fetch_reg));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \if_pc[0]_i_1 
       (.I0(\Using_FPGA.Native_0 [0]),
        .I1(ex_jump),
        .O(if_fetch_in_progress_reg));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_115
   (if_sel_input,
    sync_reset,
    sel_input_iii_1,
    Clk);
  output [0:0]if_sel_input;
  input sync_reset;
  input sel_input_iii_1;
  input Clk;

  wire Clk;
  wire [0:0]if_sel_input;
  wire sel_input_iii_1;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(sel_input_iii_1),
        .Q(if_sel_input),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_117
   (\Using_FPGA.Native_0 ,
    I187_out,
    I1,
    I191_out,
    I13_out,
    I195_out,
    I17_out,
    I199_out,
    I111_out,
    I1103_out,
    I115_out,
    I1107_out,
    I119_out,
    I1111_out,
    I123_out,
    I1115_out,
    I127_out,
    I1119_out,
    I131_out,
    I1123_out,
    I135_out,
    I143_out,
    I147_out,
    I151_out,
    I155_out,
    I159_out,
    I163_out,
    I167_out,
    I171_out,
    I175_out,
    I179_out,
    I183_out,
    I1127_out,
    I1131_out,
    I1135_out,
    I1139_out,
    I1143_out,
    I1147_out,
    I1151_out,
    I1155_out,
    I1159_out,
    I1163_out,
    I1167_out,
    sync_reset,
    sel_input_i_1,
    Clk,
    out,
    in);
  output \Using_FPGA.Native_0 ;
  output I187_out;
  output I1;
  output I191_out;
  output I13_out;
  output I195_out;
  output I17_out;
  output I199_out;
  output I111_out;
  output I1103_out;
  output I115_out;
  output I1107_out;
  output I119_out;
  output I1111_out;
  output I123_out;
  output I1115_out;
  output I127_out;
  output I1119_out;
  output I131_out;
  output I1123_out;
  output I135_out;
  output I143_out;
  output I147_out;
  output I151_out;
  output I155_out;
  output I159_out;
  output I163_out;
  output I167_out;
  output I171_out;
  output I175_out;
  output I179_out;
  output I183_out;
  output I1127_out;
  output I1131_out;
  output I1135_out;
  output I1139_out;
  output I1143_out;
  output I1147_out;
  output I1151_out;
  output I1155_out;
  output I1159_out;
  output I1163_out;
  output I1167_out;
  input sync_reset;
  input sel_input_i_1;
  input Clk;
  input [41:0]out;
  input [31:0]in;

  wire Clk;
  wire I1;
  wire I1103_out;
  wire I1107_out;
  wire I1111_out;
  wire I1115_out;
  wire I1119_out;
  wire I111_out;
  wire I1123_out;
  wire I1127_out;
  wire I1131_out;
  wire I1135_out;
  wire I1139_out;
  wire I1143_out;
  wire I1147_out;
  wire I1151_out;
  wire I1155_out;
  wire I1159_out;
  wire I115_out;
  wire I1163_out;
  wire I1167_out;
  wire I119_out;
  wire I123_out;
  wire I127_out;
  wire I131_out;
  wire I135_out;
  wire I13_out;
  wire I143_out;
  wire I147_out;
  wire I151_out;
  wire I155_out;
  wire I159_out;
  wire I163_out;
  wire I167_out;
  wire I171_out;
  wire I175_out;
  wire I179_out;
  wire I17_out;
  wire I183_out;
  wire I187_out;
  wire I191_out;
  wire I195_out;
  wire I199_out;
  wire \Using_FPGA.Native_0 ;
  wire [31:0]in;
  wire [41:0]out;
  wire sel_input_i_1;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(sel_input_i_1),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__0 
       (.I0(out[21]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[0]),
        .O(I187_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__1 
       (.I0(out[0]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[0]),
        .O(I1));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__10 
       (.I0(out[26]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[5]),
        .O(I1107_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__11 
       (.I0(out[5]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[5]),
        .O(I119_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__12 
       (.I0(out[27]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[6]),
        .O(I1111_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__13 
       (.I0(out[6]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[6]),
        .O(I123_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__14 
       (.I0(out[28]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[7]),
        .O(I1115_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__15 
       (.I0(out[7]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[7]),
        .O(I127_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__16 
       (.I0(out[29]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[8]),
        .O(I1119_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__17 
       (.I0(out[8]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[8]),
        .O(I131_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__18 
       (.I0(out[30]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[9]),
        .O(I1123_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__19 
       (.I0(out[9]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[9]),
        .O(I135_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__2 
       (.I0(out[22]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[1]),
        .O(I191_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__3 
       (.I0(out[1]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[1]),
        .O(I13_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__4 
       (.I0(out[23]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[2]),
        .O(I195_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__5 
       (.I0(out[2]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[2]),
        .O(I17_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__59 
       (.I0(out[10]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[10]),
        .O(I143_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__6 
       (.I0(out[24]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[3]),
        .O(I199_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__60 
       (.I0(out[11]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[11]),
        .O(I147_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__61 
       (.I0(out[12]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[12]),
        .O(I151_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__62 
       (.I0(out[13]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[13]),
        .O(I155_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__63 
       (.I0(out[14]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[14]),
        .O(I159_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__64 
       (.I0(out[15]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[15]),
        .O(I163_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__65 
       (.I0(out[16]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[16]),
        .O(I167_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__66 
       (.I0(out[17]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[17]),
        .O(I171_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__67 
       (.I0(out[18]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[18]),
        .O(I175_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__68 
       (.I0(out[19]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[19]),
        .O(I179_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__69 
       (.I0(out[20]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[20]),
        .O(I183_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__7 
       (.I0(out[3]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[3]),
        .O(I111_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__70 
       (.I0(out[31]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[21]),
        .O(I1127_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__71 
       (.I0(out[32]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[22]),
        .O(I1131_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__72 
       (.I0(out[33]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[23]),
        .O(I1135_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__73 
       (.I0(out[34]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[24]),
        .O(I1139_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__74 
       (.I0(out[35]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[25]),
        .O(I1143_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__75 
       (.I0(out[36]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[26]),
        .O(I1147_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__76 
       (.I0(out[37]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[27]),
        .O(I1151_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__77 
       (.I0(out[38]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[28]),
        .O(I1155_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__78 
       (.I0(out[39]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[29]),
        .O(I1159_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__79 
       (.I0(out[40]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[30]),
        .O(I1163_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__8 
       (.I0(out[25]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[4]),
        .O(I1103_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__80 
       (.I0(out[41]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[31]),
        .O(I1167_out));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__9 
       (.I0(out[4]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(in[4]),
        .O(I115_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_119
   (\Using_FPGA.Native_0 ,
    OF_Op1_Sel_SPR_PC0__0,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    \Using_FPGA.Native_5 ,
    sync_reset,
    of_instr_ii_42,
    Clk,
    \Using_FPGA.Native_6 ,
    EX_Use_Carry_reg,
    \Using_FPGA.Native_7 ,
    ex_jump_nodelay,
    ex_jump,
    EX_CMP_Op_reg,
    EX_Unsigned_Op_reg,
    EX_ALU_Op1142_out__0,
    EX_Unsigned_Op_reg_0);
  output \Using_FPGA.Native_0 ;
  output OF_Op1_Sel_SPR_PC0__0;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  output \Using_FPGA.Native_3 ;
  output \Using_FPGA.Native_4 ;
  output \Using_FPGA.Native_5 ;
  input sync_reset;
  input of_instr_ii_42;
  input Clk;
  input \Using_FPGA.Native_6 ;
  input EX_Use_Carry_reg;
  input \Using_FPGA.Native_7 ;
  input ex_jump_nodelay;
  input ex_jump;
  input EX_CMP_Op_reg;
  input EX_Unsigned_Op_reg;
  input EX_ALU_Op1142_out__0;
  input EX_Unsigned_Op_reg_0;

  wire Clk;
  wire EX_ALU_Op1142_out__0;
  wire EX_CMP_Op_reg;
  wire EX_Unsigned_Op_reg;
  wire EX_Unsigned_Op_reg_0;
  wire EX_Use_Carry_reg;
  wire OF_Op1_Sel_SPR_PC0__0;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_7 ;
  wire ex_jump;
  wire ex_jump_nodelay;
  wire of_instr_ii_42;
  wire sync_reset;

  LUT5 #(
    .INIT(32'h00000010)) 
    EX_CMP_Op_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_7 ),
        .I2(EX_CMP_Op_reg),
        .I3(EX_Unsigned_Op_reg),
        .I4(EX_ALU_Op1142_out__0),
        .O(\Using_FPGA.Native_2 ));
  LUT5 #(
    .INIT(32'h00000010)) 
    EX_Unsigned_Op_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_7 ),
        .I2(EX_Unsigned_Op_reg_0),
        .I3(EX_Unsigned_Op_reg),
        .I4(EX_ALU_Op1142_out__0),
        .O(\Using_FPGA.Native_3 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    EX_Use_Carry_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_7 ),
        .I2(EX_Use_Carry_reg),
        .I3(EX_ALU_Op1142_out__0),
        .O(\Using_FPGA.Native_4 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_42),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \Using_FPGA.Native_i_1__102 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_7 ),
        .I2(\Using_FPGA.Native_6 ),
        .O(\Using_FPGA.Native_5 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h0888)) 
    \Using_FPGA.Native_i_1__96 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_7 ),
        .I2(ex_jump_nodelay),
        .I3(ex_jump),
        .O(\Using_FPGA.Native_1 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \Using_FPGA.Native_i_4__1 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_6 ),
        .I2(EX_Use_Carry_reg),
        .I3(\Using_FPGA.Native_7 ),
        .O(OF_Op1_Sel_SPR_PC0__0));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_121
   (\Using_FPGA.Native_0 ,
    \mem_gpr_write_addr_reg[4] ,
    \wb_gpr_write_addr_reg[4] ,
    \ex_gpr_write_addr_reg[4] ,
    sync_reset,
    of_instr_ii_32,
    Clk,
    \EX_Op3[0]_i_4 ,
    \EX_Op3[0]_i_6 ,
    \EX_Op3[0]_i_6_0 ,
    \EX_Op3[0]_i_5 ,
    \EX_Op3[0]_i_6_1 ,
    I4,
    I0);
  output \Using_FPGA.Native_0 ;
  output \mem_gpr_write_addr_reg[4] ;
  output \wb_gpr_write_addr_reg[4] ;
  output \ex_gpr_write_addr_reg[4] ;
  input sync_reset;
  input of_instr_ii_32;
  input Clk;
  input [2:0]\EX_Op3[0]_i_4 ;
  input \EX_Op3[0]_i_6 ;
  input \EX_Op3[0]_i_6_0 ;
  input [2:0]\EX_Op3[0]_i_5 ;
  input \EX_Op3[0]_i_6_1 ;
  input I4;
  input I0;

  wire Clk;
  wire [2:0]\EX_Op3[0]_i_4 ;
  wire [2:0]\EX_Op3[0]_i_5 ;
  wire \EX_Op3[0]_i_6 ;
  wire \EX_Op3[0]_i_6_0 ;
  wire \EX_Op3[0]_i_6_1 ;
  wire I0;
  wire I4;
  wire \Using_FPGA.Native_0 ;
  wire \ex_gpr_write_addr_reg[4] ;
  wire \mem_gpr_write_addr_reg[4] ;
  wire of_instr_ii_32;
  wire sync_reset;
  wire \wb_gpr_write_addr_reg[4] ;

  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \EX_Op3[0]_i_11 
       (.I0(\EX_Op3[0]_i_6_1 ),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op3[0]_i_6 ),
        .I3(I4),
        .I4(\EX_Op3[0]_i_6_0 ),
        .I5(I0),
        .O(\ex_gpr_write_addr_reg[4] ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \EX_Op3[0]_i_7 
       (.I0(\EX_Op3[0]_i_4 [0]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op3[0]_i_6 ),
        .I3(\EX_Op3[0]_i_4 [2]),
        .I4(\EX_Op3[0]_i_6_0 ),
        .I5(\EX_Op3[0]_i_4 [1]),
        .O(\mem_gpr_write_addr_reg[4] ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \EX_Op3[0]_i_9 
       (.I0(\EX_Op3[0]_i_5 [0]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op3[0]_i_6 ),
        .I3(\EX_Op3[0]_i_5 [2]),
        .I4(\EX_Op3[0]_i_6_0 ),
        .I5(\EX_Op3[0]_i_5 [1]),
        .O(\wb_gpr_write_addr_reg[4] ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_32),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_123
   (\Using_FPGA.Native_0 ,
    ex_set_bip0__1,
    sync_reset,
    of_instr_ii_31,
    Clk,
    ex_set_bip_reg,
    ex_set_bip_reg_0);
  output \Using_FPGA.Native_0 ;
  output ex_set_bip0__1;
  input sync_reset;
  input of_instr_ii_31;
  input Clk;
  input ex_set_bip_reg;
  input ex_set_bip_reg_0;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire ex_set_bip0__1;
  wire ex_set_bip_reg;
  wire ex_set_bip_reg_0;
  wire of_instr_ii_31;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_31),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'h40)) 
    ex_set_bip_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_set_bip_reg),
        .I2(ex_set_bip_reg_0),
        .O(ex_set_bip0__1));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_125
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    EX_ALU_Op1142_out__0,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_30,
    Clk,
    \EX_ALU_Op_reg[1] ,
    ex_enable_alu_i_reg,
    \EX_ALU_Op_reg[1]_0 ,
    ex_enable_alu_i_reg_0,
    ex_enable_alu_i_reg_1,
    ex_enable_alu_i_reg_2,
    ex_enable_alu_i_reg_3,
    p_28_in);
  output \Using_FPGA.Native_0 ;
  output [0:0]\Using_FPGA.Native_1 ;
  output EX_ALU_Op1142_out__0;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_30;
  input Clk;
  input \EX_ALU_Op_reg[1] ;
  input ex_enable_alu_i_reg;
  input \EX_ALU_Op_reg[1]_0 ;
  input ex_enable_alu_i_reg_0;
  input ex_enable_alu_i_reg_1;
  input ex_enable_alu_i_reg_2;
  input ex_enable_alu_i_reg_3;
  input p_28_in;

  wire Clk;
  wire EX_ALU_Op1142_out__0;
  wire \EX_ALU_Op_reg[1] ;
  wire \EX_ALU_Op_reg[1]_0 ;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire ex_enable_alu_i_reg;
  wire ex_enable_alu_i_reg_0;
  wire ex_enable_alu_i_reg_1;
  wire ex_enable_alu_i_reg_2;
  wire ex_enable_alu_i_reg_3;
  wire of_instr_ii_30;
  wire p_28_in;
  wire sync_reset;

  LUT6 #(
    .INIT(64'hAAAAAAAEAEAEAEEE)) 
    \EX_ALU_Op[1]_i_1 
       (.I0(EX_ALU_Op1142_out__0),
        .I1(\EX_ALU_Op_reg[1] ),
        .I2(ex_enable_alu_i_reg),
        .I3(\EX_ALU_Op_reg[1]_0 ),
        .I4(ex_enable_alu_i_reg_0),
        .I5(ex_enable_alu_i_reg_1),
        .O(\Using_FPGA.Native_1 ));
  LUT2 #(
    .INIT(4'h8)) 
    EX_CMP_Op_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(p_28_in),
        .O(EX_ALU_Op1142_out__0));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_30),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFEBFFFF)) 
    ex_enable_alu_i_i_1
       (.I0(EX_ALU_Op1142_out__0),
        .I1(ex_enable_alu_i_reg_1),
        .I2(ex_enable_alu_i_reg),
        .I3(ex_enable_alu_i_reg_2),
        .I4(ex_enable_alu_i_reg_3),
        .I5(ex_enable_alu_i_reg_0),
        .O(\Using_FPGA.Native_2 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_127
   (\Using_FPGA.Native_0 ,
    sync_reset,
    of_instr_ii_29,
    Clk);
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input of_instr_ii_29;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_29;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_29),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_129
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_28,
    Clk,
    p_1_in26_in,
    ex_mbar_decode_reg,
    ex_mbar_decode,
    E);
  output [0:0]\Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_28;
  input Clk;
  input p_1_in26_in;
  input ex_mbar_decode_reg;
  input ex_mbar_decode;
  input [0:0]E;

  wire Clk;
  wire [0:0]E;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_mbar_decode;
  wire ex_mbar_decode_reg;
  wire of_instr_ii_28;
  wire p_1_in26_in;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_28),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT5 #(
    .INIT(32'h80808F80)) 
    ex_mbar_decode_cmb_inferred_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(p_1_in26_in),
        .I2(ex_mbar_decode_reg),
        .I3(ex_mbar_decode),
        .I4(E),
        .O(\Using_FPGA.Native_1 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_131
   (\Using_FPGA.Native_0 ,
    sync_reset,
    of_instr_ii_27,
    Clk);
  output [0:0]\Using_FPGA.Native_0 ;
  input sync_reset;
  input of_instr_ii_27;
  input Clk;

  wire Clk;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire of_instr_ii_27;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_27),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_133
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \imm_reg_reg[15] ,
    \imm_reg_reg[14] ,
    \imm_reg_reg[13] ,
    \imm_reg_reg[12] ,
    \imm_reg_reg[11] ,
    \imm_reg_reg[10] ,
    \imm_reg_reg[9] ,
    \imm_reg_reg[8] ,
    \imm_reg_reg[7] ,
    \imm_reg_reg[6] ,
    \imm_reg_reg[5] ,
    \imm_reg_reg[4] ,
    \imm_reg_reg[3] ,
    \imm_reg_reg[2] ,
    \imm_reg_reg[1] ,
    \imm_reg_reg[0] ,
    sync_reset,
    of_instr_ii_26,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \EX_Op2_reg[0] ,
    \EX_Op2_reg[0]_0 );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \imm_reg_reg[15] ;
  output \imm_reg_reg[14] ;
  output \imm_reg_reg[13] ;
  output \imm_reg_reg[12] ;
  output \imm_reg_reg[11] ;
  output \imm_reg_reg[10] ;
  output \imm_reg_reg[9] ;
  output \imm_reg_reg[8] ;
  output \imm_reg_reg[7] ;
  output \imm_reg_reg[6] ;
  output \imm_reg_reg[5] ;
  output \imm_reg_reg[4] ;
  output \imm_reg_reg[3] ;
  output \imm_reg_reg[2] ;
  output \imm_reg_reg[1] ;
  output \imm_reg_reg[0] ;
  input sync_reset;
  input of_instr_ii_26;
  input Clk;
  input of_op2_sel_imm;
  input [16:0]GPR_Op2;
  input [15:0]\EX_Op2_reg[0] ;
  input \EX_Op2_reg[0]_0 ;

  wire Clk;
  wire [15:0]\EX_Op2_reg[0] ;
  wire \EX_Op2_reg[0]_0 ;
  wire [16:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \imm_reg_reg[0] ;
  wire \imm_reg_reg[10] ;
  wire \imm_reg_reg[11] ;
  wire \imm_reg_reg[12] ;
  wire \imm_reg_reg[13] ;
  wire \imm_reg_reg[14] ;
  wire \imm_reg_reg[15] ;
  wire \imm_reg_reg[1] ;
  wire \imm_reg_reg[2] ;
  wire \imm_reg_reg[3] ;
  wire \imm_reg_reg[4] ;
  wire \imm_reg_reg[5] ;
  wire \imm_reg_reg[6] ;
  wire \imm_reg_reg[7] ;
  wire \imm_reg_reg[8] ;
  wire \imm_reg_reg[9] ;
  wire of_instr_ii_26;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[0]_i_2 
       (.I0(\EX_Op2_reg[0] [15]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[16]),
        .O(\imm_reg_reg[0] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[10]_i_2 
       (.I0(\EX_Op2_reg[0] [5]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[6]),
        .O(\imm_reg_reg[10] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[11]_i_2 
       (.I0(\EX_Op2_reg[0] [4]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[5]),
        .O(\imm_reg_reg[11] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[12]_i_2 
       (.I0(\EX_Op2_reg[0] [3]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[4]),
        .O(\imm_reg_reg[12] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[13]_i_2 
       (.I0(\EX_Op2_reg[0] [2]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[3]),
        .O(\imm_reg_reg[13] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[14]_i_2 
       (.I0(\EX_Op2_reg[0] [1]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[2]),
        .O(\imm_reg_reg[14] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[15]_i_2 
       (.I0(\EX_Op2_reg[0] [0]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[1]),
        .O(\imm_reg_reg[15] ));
  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[16]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2[0]),
        .O(\Using_FPGA.Native_1 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[1]_i_2 
       (.I0(\EX_Op2_reg[0] [14]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[15]),
        .O(\imm_reg_reg[1] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[2]_i_2 
       (.I0(\EX_Op2_reg[0] [13]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[14]),
        .O(\imm_reg_reg[2] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[3]_i_2 
       (.I0(\EX_Op2_reg[0] [12]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[13]),
        .O(\imm_reg_reg[3] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[4]_i_2 
       (.I0(\EX_Op2_reg[0] [11]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[12]),
        .O(\imm_reg_reg[4] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[5]_i_2 
       (.I0(\EX_Op2_reg[0] [10]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[11]),
        .O(\imm_reg_reg[5] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[6]_i_2 
       (.I0(\EX_Op2_reg[0] [9]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[10]),
        .O(\imm_reg_reg[6] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[7]_i_2 
       (.I0(\EX_Op2_reg[0] [8]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[9]),
        .O(\imm_reg_reg[7] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[8]_i_2 
       (.I0(\EX_Op2_reg[0] [7]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[8]),
        .O(\imm_reg_reg[8] ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \EX_Op2[9]_i_2 
       (.I0(\EX_Op2_reg[0] [6]),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\Using_FPGA.Native_0 ),
        .I3(of_op2_sel_imm),
        .I4(GPR_Op2[7]),
        .O(\imm_reg_reg[9] ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_26),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_135
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_25,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_25;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire of_instr_ii_25;
  wire of_op2_sel_imm;
  wire sync_reset;

  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[17]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_7 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ),
        .I2(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ),
        .O(\Using_FPGA.Native_2 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_25),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_137
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_24,
    Clk,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_24;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_instr_ii_24;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[18]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_24),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_139
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_23,
    Clk,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_23;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_instr_ii_23;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[19]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_23),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_141
   (\Using_FPGA.Native_0 ,
    ex_gpr_write_reg,
    \Using_FPGA.Native_1 ,
    p_28_in,
    of_op2_sel_imm,
    of_use_op2_s,
    wb_exception_i_reg,
    \Using_FPGA.Native_2 ,
    ex_set_bip,
    sync_reset,
    of_instr_ii_41,
    Clk,
    ex_gpr_write_reg_0,
    ex_gpr_write_reg_1,
    ex_gpr_write111_out__0,
    wb_exception,
    ex_set_bip_reg,
    \EX_ALU_Op_reg[0] ,
    ex_set_bip_reg_0,
    ex_set_bip_reg_1,
    EX_ALU_Op1142_out__0,
    p_0_in30_in,
    ex_gpr_write_dbg_reg,
    ex_gpr_write_dbg_reg_0,
    ex_gpr_write_i_2_0,
    ex_gpr_write_i_2_1,
    ex_gpr_write_i_2_2,
    ex_gpr_write_i_2_3,
    ex_set_bip_reg_2,
    \EX_Op2[0]_i_2 ,
    E,
    ex_gpr_write_dbg__0,
    ex_set_bip0__1);
  output \Using_FPGA.Native_0 ;
  output ex_gpr_write_reg;
  output [0:0]\Using_FPGA.Native_1 ;
  output p_28_in;
  output of_op2_sel_imm;
  output of_use_op2_s;
  output wb_exception_i_reg;
  output \Using_FPGA.Native_2 ;
  output ex_set_bip;
  input sync_reset;
  input of_instr_ii_41;
  input Clk;
  input ex_gpr_write_reg_0;
  input ex_gpr_write_reg_1;
  input ex_gpr_write111_out__0;
  input wb_exception;
  input ex_set_bip_reg;
  input \EX_ALU_Op_reg[0] ;
  input ex_set_bip_reg_0;
  input ex_set_bip_reg_1;
  input EX_ALU_Op1142_out__0;
  input p_0_in30_in;
  input ex_gpr_write_dbg_reg;
  input ex_gpr_write_dbg_reg_0;
  input ex_gpr_write_i_2_0;
  input ex_gpr_write_i_2_1;
  input ex_gpr_write_i_2_2;
  input ex_gpr_write_i_2_3;
  input ex_set_bip_reg_2;
  input \EX_Op2[0]_i_2 ;
  input [0:0]E;
  input ex_gpr_write_dbg__0;
  input ex_set_bip0__1;

  wire Clk;
  wire [0:0]E;
  wire EX_ALU_Op1142_out__0;
  wire \EX_ALU_Op_reg[0] ;
  wire \EX_Op2[0]_i_2 ;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire ex_gpr_write;
  wire ex_gpr_write111_out__0;
  wire ex_gpr_write_dbg108_in;
  wire ex_gpr_write_dbg__0;
  wire ex_gpr_write_dbg_reg;
  wire ex_gpr_write_dbg_reg_0;
  wire ex_gpr_write_i_2_0;
  wire ex_gpr_write_i_2_1;
  wire ex_gpr_write_i_2_2;
  wire ex_gpr_write_i_2_3;
  wire ex_gpr_write_i_5_n_0;
  wire ex_gpr_write_reg;
  wire ex_gpr_write_reg_0;
  wire ex_gpr_write_reg_1;
  wire ex_set_bip;
  wire ex_set_bip0__1;
  wire ex_set_bip_reg;
  wire ex_set_bip_reg_0;
  wire ex_set_bip_reg_1;
  wire ex_set_bip_reg_2;
  wire of_instr_ii_41;
  wire of_op2_sel_imm;
  wire of_use_op2_s;
  wire p_0_in30_in;
  wire p_28_in;
  wire sync_reset;
  wire wb_exception;
  wire wb_exception_i_reg;

  LUT6 #(
    .INIT(64'h00000000FFFFFFF9)) 
    \EX_ALU_Op[0]_i_1 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_set_bip_reg),
        .I2(\EX_ALU_Op_reg[0] ),
        .I3(ex_set_bip_reg_0),
        .I4(ex_set_bip_reg_1),
        .I5(EX_ALU_Op1142_out__0),
        .O(\Using_FPGA.Native_1 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'h00004000)) 
    EX_CMP_Op_i_3
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_set_bip_reg_0),
        .I2(ex_set_bip_reg_1),
        .I3(ex_set_bip_reg),
        .I4(ex_set_bip_reg_2),
        .O(p_28_in));
  LUT6 #(
    .INIT(64'hFFFFFFFF00004000)) 
    \EX_Op2[0]_i_5 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_set_bip_reg),
        .I2(ex_set_bip_reg_2),
        .I3(ex_set_bip_reg_1),
        .I4(ex_set_bip_reg_0),
        .I5(\EX_Op2[0]_i_2 ),
        .O(of_op2_sel_imm));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_41),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT5 #(
    .INIT(32'h33332333)) 
    \Using_FPGA.Native_i_2__117 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\EX_Op2[0]_i_2 ),
        .I2(ex_set_bip_reg),
        .I3(ex_set_bip_reg_1),
        .I4(ex_set_bip_reg_0),
        .O(of_use_op2_s));
  LUT4 #(
    .INIT(16'h0006)) 
    ex_alu_sel_logic_i_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_set_bip_reg),
        .I2(ex_set_bip_reg_1),
        .I3(EX_ALU_Op1142_out__0),
        .O(\Using_FPGA.Native_2 ));
  LUT6 #(
    .INIT(64'h0200020302000200)) 
    ex_gpr_write_dbg_i_1
       (.I0(ex_gpr_write),
        .I1(wb_exception),
        .I2(sync_reset),
        .I3(ex_gpr_write_reg_1),
        .I4(E),
        .I5(ex_gpr_write_dbg__0),
        .O(wb_exception_i_reg));
  LUT6 #(
    .INIT(64'h00000000000000E2)) 
    ex_gpr_write_i_1
       (.I0(ex_gpr_write_reg_0),
        .I1(ex_gpr_write_reg_1),
        .I2(ex_gpr_write),
        .I3(ex_gpr_write111_out__0),
        .I4(sync_reset),
        .I5(wb_exception),
        .O(ex_gpr_write_reg));
  LUT4 #(
    .INIT(16'h222A)) 
    ex_gpr_write_i_2
       (.I0(ex_gpr_write_dbg108_in),
        .I1(p_0_in30_in),
        .I2(ex_gpr_write_dbg_reg),
        .I3(ex_gpr_write_dbg_reg_0),
        .O(ex_gpr_write));
  LUT6 #(
    .INIT(64'h8888888888888BBB)) 
    ex_gpr_write_i_4
       (.I0(ex_gpr_write_i_2_0),
        .I1(p_28_in),
        .I2(ex_gpr_write_i_2_1),
        .I3(ex_gpr_write_i_2_2),
        .I4(ex_gpr_write_i_5_n_0),
        .I5(ex_gpr_write_i_2_3),
        .O(ex_gpr_write_dbg108_in));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    ex_gpr_write_i_5
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_set_bip_reg_0),
        .I2(ex_set_bip_reg_1),
        .I3(ex_set_bip_reg_2),
        .I4(ex_set_bip_reg),
        .O(ex_gpr_write_i_5_n_0));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    ex_set_bip_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_set_bip_reg_2),
        .I2(ex_set_bip0__1),
        .I3(ex_set_bip_reg_0),
        .I4(ex_set_bip_reg_1),
        .I5(ex_set_bip_reg),
        .O(ex_set_bip));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_143
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_22,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ,
    ex_set_bip0__1,
    p_1_in26_in,
    of_Imm180);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_22;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ;
  input ex_set_bip0__1;
  input p_1_in26_in;
  input of_Imm180;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_6_n_0 ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire ex_set_bip0__1;
  wire of_Imm180;
  wire of_instr_ii_22;
  wire of_op2_sel_imm;
  wire p_1_in26_in;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[20]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  LUT6 #(
    .INIT(64'h0100000000000000)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 
       (.I0(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_6_n_0 ),
        .I1(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ),
        .I2(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ),
        .I3(ex_set_bip0__1),
        .I4(p_1_in26_in),
        .I5(of_Imm180),
        .O(\Using_FPGA.Native_2 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_6 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ),
        .I2(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ),
        .I3(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 ),
        .O(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_6_n_0 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_22),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_145
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_21,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \Performance_Debug_Control.ex_brki_hit_reg ,
    \Performance_Debug_Control.ex_brki_hit_reg_0 ,
    \Performance_Debug_Control.ex_brki_hit_reg_1 ,
    \Performance_Debug_Control.ex_brki_hit_reg_2 );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_21;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;
  input \Performance_Debug_Control.ex_brki_hit_reg ;
  input \Performance_Debug_Control.ex_brki_hit_reg_0 ;
  input [0:0]\Performance_Debug_Control.ex_brki_hit_reg_1 ;
  input \Performance_Debug_Control.ex_brki_hit_reg_2 ;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Performance_Debug_Control.ex_brki_hit_reg ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_0 ;
  wire [0:0]\Performance_Debug_Control.ex_brki_hit_reg_1 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_2 ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire of_instr_ii_21;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[21]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \Performance_Debug_Control.ex_brki_hit_i_3 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Performance_Debug_Control.ex_brki_hit_reg ),
        .I2(\Performance_Debug_Control.ex_brki_hit_reg_0 ),
        .I3(\Performance_Debug_Control.ex_brki_hit_reg_1 ),
        .I4(\Performance_Debug_Control.ex_brki_hit_reg_2 ),
        .O(\Using_FPGA.Native_2 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_21),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_147
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_20,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_20;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;
  input \Using_FPGA.Native_3 ;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire of_instr_ii_20;
  wire of_op2_sel_imm;
  wire sync_reset;

  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[22]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_20),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Using_FPGA.Native_i_1__103 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_3 ),
        .O(\Using_FPGA.Native_2 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_149
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_19,
    Clk,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_19;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_instr_ii_19;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[23]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_19),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_151
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_18,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_18;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire of_instr_ii_18;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[24]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \Performance_Debug_Control.ex_brki_hit_i_5 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ),
        .I2(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ),
        .I3(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ),
        .O(\Using_FPGA.Native_2 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_18),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_153
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_17,
    Clk,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_17;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_instr_ii_17;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[25]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_17),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_155
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_16,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \EX_Sext_Op_reg[0] );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_16;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;
  input \EX_Sext_Op_reg[0] ;

  wire Clk;
  wire \EX_Sext_Op_reg[0] ;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire of_instr_ii_16;
  wire of_op2_sel_imm;
  wire sync_reset;

  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[26]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \EX_Sext_Op[0]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\EX_Sext_Op_reg[0] ),
        .O(\Using_FPGA.Native_2 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_16),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_157
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Serial_Dbg_Intf.control_reg_reg[8] ,
    of_Imm180,
    sync_reset,
    of_instr_ii_15,
    Clk,
    of_op2_sel_imm,
    GPR_Op2,
    \Performance_Debug_Control.ex_brki_hit_reg ,
    \Performance_Debug_Control.ex_brki_hit_reg_0 ,
    \Performance_Debug_Control.ex_brki_hit_reg_1 ,
    \Performance_Debug_Control.ex_brki_hit_reg_2 ,
    \Performance_Debug_Control.ex_brki_hit_reg_3 ,
    p_1_in26_in,
    \Performance_Debug_Control.ex_brki_hit_reg_4 ,
    \Performance_Debug_Control.ex_brki_hit_reg_5 ,
    \Performance_Debug_Control.ex_brki_hit_reg_6 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Serial_Dbg_Intf.control_reg_reg[8] ;
  output of_Imm180;
  input sync_reset;
  input of_instr_ii_15;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;
  input [0:0]\Performance_Debug_Control.ex_brki_hit_reg ;
  input \Performance_Debug_Control.ex_brki_hit_reg_0 ;
  input \Performance_Debug_Control.ex_brki_hit_reg_1 ;
  input \Performance_Debug_Control.ex_brki_hit_reg_2 ;
  input \Performance_Debug_Control.ex_brki_hit_reg_3 ;
  input p_1_in26_in;
  input \Performance_Debug_Control.ex_brki_hit_reg_4 ;
  input \Performance_Debug_Control.ex_brki_hit_reg_5 ;
  input \Performance_Debug_Control.ex_brki_hit_reg_6 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 ;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Performance_Debug_Control.ex_brki_hit_i_2_n_0 ;
  wire [0:0]\Performance_Debug_Control.ex_brki_hit_reg ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_0 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_1 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_2 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_3 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_4 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_5 ;
  wire \Performance_Debug_Control.ex_brki_hit_reg_6 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 ;
  wire \Serial_Dbg_Intf.control_reg_reg[8] ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_Imm180;
  wire of_instr_ii_15;
  wire of_op2_sel_imm;
  wire p_1_in26_in;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[27]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \Performance_Debug_Control.ex_brki_hit_i_1 
       (.I0(\Performance_Debug_Control.ex_brki_hit_reg ),
        .I1(\Performance_Debug_Control.ex_brki_hit_i_2_n_0 ),
        .I2(\Performance_Debug_Control.ex_brki_hit_reg_0 ),
        .I3(\Performance_Debug_Control.ex_brki_hit_reg_1 ),
        .I4(\Performance_Debug_Control.ex_brki_hit_reg_2 ),
        .I5(\Performance_Debug_Control.ex_brki_hit_reg_3 ),
        .O(\Serial_Dbg_Intf.control_reg_reg[8] ));
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    \Performance_Debug_Control.ex_brki_hit_i_2 
       (.I0(of_Imm180),
        .I1(p_1_in26_in),
        .I2(\Performance_Debug_Control.ex_brki_hit_reg_4 ),
        .I3(\Performance_Debug_Control.ex_brki_hit_reg_5 ),
        .I4(\Performance_Debug_Control.ex_brki_hit_reg_6 ),
        .O(\Performance_Debug_Control.ex_brki_hit_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \Performance_Debug_Control.ex_brki_hit_i_4 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 ),
        .I2(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 ),
        .I3(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 ),
        .I4(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 ),
        .O(of_Imm180));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_15),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_159
   (\Using_FPGA.Native_0 ,
    ex_move_to_MSR_instr93_out,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_14,
    Clk,
    ex_move_to_MSR_instr_reg,
    ex_move_to_MSR_instr_reg_0,
    ex_move_to_MSR_instr_reg_1,
    ex_move_to_MSR_instr_reg_2,
    ex_move_to_MSR_instr_reg_3,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output ex_move_to_MSR_instr93_out;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_14;
  input Clk;
  input ex_move_to_MSR_instr_reg;
  input ex_move_to_MSR_instr_reg_0;
  input ex_move_to_MSR_instr_reg_1;
  input ex_move_to_MSR_instr_reg_2;
  input ex_move_to_MSR_instr_reg_3;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_move_to_MSR_instr93_out;
  wire ex_move_to_MSR_instr_reg;
  wire ex_move_to_MSR_instr_reg_0;
  wire ex_move_to_MSR_instr_reg_1;
  wire ex_move_to_MSR_instr_reg_2;
  wire ex_move_to_MSR_instr_reg_3;
  wire of_instr_ii_14;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[28]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_14),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'h0100000000000000)) 
    ex_move_to_MSR_instr_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_move_to_MSR_instr_reg),
        .I2(ex_move_to_MSR_instr_reg_0),
        .I3(ex_move_to_MSR_instr_reg_1),
        .I4(ex_move_to_MSR_instr_reg_2),
        .I5(ex_move_to_MSR_instr_reg_3),
        .O(ex_move_to_MSR_instr93_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_161
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_13,
    Clk,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_13;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_instr_ii_13;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[29]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_13),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_163
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    p_1_in26_in,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    sync_reset,
    of_instr_ii_40,
    Clk,
    ex_mbar_decode_reg,
    \Using_FPGA.Native_5 ,
    \Using_FPGA.Native_6 ,
    ex_mbar_decode_reg_0,
    ex_mbar_decode_reg_1,
    \EX_ALU_Op_reg[0] );
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output p_1_in26_in;
  output \Using_FPGA.Native_2 ;
  output \Using_FPGA.Native_3 ;
  output \Using_FPGA.Native_4 ;
  input sync_reset;
  input of_instr_ii_40;
  input Clk;
  input ex_mbar_decode_reg;
  input \Using_FPGA.Native_5 ;
  input \Using_FPGA.Native_6 ;
  input ex_mbar_decode_reg_0;
  input ex_mbar_decode_reg_1;
  input \EX_ALU_Op_reg[0] ;

  wire Clk;
  wire \EX_ALU_Op_reg[0] ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire ex_mbar_decode_reg;
  wire ex_mbar_decode_reg_0;
  wire ex_mbar_decode_reg_1;
  wire of_instr_ii_40;
  wire p_1_in26_in;
  wire sync_reset;

  LUT3 #(
    .INIT(8'h04)) 
    \EX_ALU_Op[0]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\EX_ALU_Op_reg[0] ),
        .I2(ex_mbar_decode_reg),
        .O(\Using_FPGA.Native_3 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT4 #(
    .INIT(16'hEFFF)) 
    \EX_Sext_Op[1]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_mbar_decode_reg_1),
        .I2(\Using_FPGA.Native_6 ),
        .I3(ex_mbar_decode_reg),
        .O(\Using_FPGA.Native_4 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_40),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \Using_FPGA.Native_i_2__84 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_5 ),
        .I2(\Using_FPGA.Native_6 ),
        .O(\Using_FPGA.Native_2 ));
  LUT6 #(
    .INIT(64'h0C00CC0000008800)) 
    ex_gpr_write_i_6
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_mbar_decode_reg),
        .I2(\Using_FPGA.Native_5 ),
        .I3(\Using_FPGA.Native_6 ),
        .I4(ex_mbar_decode_reg_0),
        .I5(ex_mbar_decode_reg_1),
        .O(\Using_FPGA.Native_1 ));
  LUT6 #(
    .INIT(64'h0000000008000000)) 
    ex_mbar_decode_cmb_inferred_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_mbar_decode_reg),
        .I2(\Using_FPGA.Native_5 ),
        .I3(\Using_FPGA.Native_6 ),
        .I4(ex_mbar_decode_reg_0),
        .I5(ex_mbar_decode_reg_1),
        .O(p_1_in26_in));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_165
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    p_2_in,
    sync_reset,
    of_instr_ii_12,
    Clk,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output p_2_in;
  input sync_reset;
  input of_instr_ii_12;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_instr_ii_12;
  wire of_op2_sel_imm;
  wire p_2_in;
  wire sync_reset;

  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[30]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT1 #(
    .INIT(2'h1)) 
    EX_SWAP_BYTE_Instr_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .O(p_2_in));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_12),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_167
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_11,
    Clk,
    of_op2_sel_imm,
    GPR_Op2);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_11;
  input Clk;
  input of_op2_sel_imm;
  input [0:0]GPR_Op2;

  wire Clk;
  wire [0:0]GPR_Op2;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_instr_ii_11;
  wire of_op2_sel_imm;
  wire sync_reset;

  LUT3 #(
    .INIT(8'hB8)) 
    \EX_Op2[31]_i_2 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(of_op2_sel_imm),
        .I2(GPR_Op2),
        .O(\Using_FPGA.Native_1 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_11),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_169
   (\Using_FPGA.Native_0 ,
    ex_sel_alu_i_reg,
    mem_valid_reg,
    sync_reset,
    of_instr_ii_10,
    Clk,
    \EX_Op3_reg[0] ,
    GPR_Op3,
    \EX_Op3_reg[0]_0 ,
    MEM_Fwd,
    \EX_Op3_reg[1] ,
    \EX_Op3_reg[1]_0 ,
    \EX_Op3_reg[2] ,
    \EX_Op3_reg[2]_0 ,
    \EX_Op3_reg[3] ,
    \EX_Op3_reg[3]_0 ,
    \EX_Op3_reg[4] ,
    \EX_Op3_reg[4]_0 ,
    \EX_Op3_reg[5] ,
    \EX_Op3_reg[5]_0 ,
    \EX_Op3_reg[6] ,
    \EX_Op3_reg[6]_0 ,
    \EX_Op3_reg[7] ,
    \EX_Op3_reg[7]_0 ,
    \EX_Op3_reg[8] ,
    \EX_Op3_reg[8]_0 ,
    \EX_Op3_reg[9] ,
    \EX_Op3_reg[9]_0 ,
    \EX_Op3_reg[10] ,
    \EX_Op3_reg[10]_0 ,
    \EX_Op3_reg[11] ,
    \EX_Op3_reg[11]_0 ,
    \EX_Op3_reg[12] ,
    \EX_Op3_reg[12]_0 ,
    \EX_Op3_reg[13] ,
    \EX_Op3_reg[13]_0 ,
    \EX_Op3_reg[14] ,
    \EX_Op3_reg[14]_0 ,
    \EX_Op3_reg[15] ,
    \EX_Op3_reg[15]_0 ,
    \EX_Op3_reg[16] ,
    \EX_Op3_reg[16]_0 ,
    \EX_Op3_reg[17] ,
    \EX_Op3_reg[18] ,
    \EX_Op3_reg[19] ,
    \EX_Op3_reg[20] ,
    \EX_Op3_reg[21] ,
    \EX_Op3_reg[22] ,
    \EX_Op3_reg[23] ,
    \EX_Op3_reg[24] ,
    \EX_Op3_reg[24]_0 ,
    \EX_Op3_reg[25] ,
    \EX_Op3_reg[25]_0 ,
    \EX_Op3_reg[26] ,
    \EX_Op3_reg[26]_0 ,
    \EX_Op3_reg[27] ,
    \EX_Op3_reg[27]_0 ,
    \EX_Op3_reg[28] ,
    \EX_Op3_reg[28]_0 ,
    \EX_Op3_reg[29] ,
    \EX_Op3_reg[29]_0 ,
    \EX_Op3_reg[30] ,
    \EX_Op3_reg[30]_0 ,
    \EX_Op3_reg[31] ,
    \EX_Op3_reg[31]_0 ,
    of_read_mem_write_op3_conflict__1,
    mem_valid_instr,
    mem_gpr_write,
    p_216_in,
    \EX_Op3[0]_i_2_0 ,
    \EX_Op3[0]_i_2_1 ,
    \EX_Op3[0]_i_2_2 ,
    \EX_Op3[0]_i_2_3 ,
    \EX_Op3[0]_i_2_4 ,
    \EX_Op3[0]_i_2_5 ,
    \EX_Op3[0]_i_2_6 ,
    \EX_Op3[0]_i_2_7 );
  output \Using_FPGA.Native_0 ;
  output [31:0]ex_sel_alu_i_reg;
  output mem_valid_reg;
  input sync_reset;
  input of_instr_ii_10;
  input Clk;
  input \EX_Op3_reg[0] ;
  input [0:31]GPR_Op3;
  input \EX_Op3_reg[0]_0 ;
  input [0:31]MEM_Fwd;
  input \EX_Op3_reg[1] ;
  input \EX_Op3_reg[1]_0 ;
  input \EX_Op3_reg[2] ;
  input \EX_Op3_reg[2]_0 ;
  input \EX_Op3_reg[3] ;
  input \EX_Op3_reg[3]_0 ;
  input \EX_Op3_reg[4] ;
  input \EX_Op3_reg[4]_0 ;
  input \EX_Op3_reg[5] ;
  input \EX_Op3_reg[5]_0 ;
  input \EX_Op3_reg[6] ;
  input \EX_Op3_reg[6]_0 ;
  input \EX_Op3_reg[7] ;
  input \EX_Op3_reg[7]_0 ;
  input \EX_Op3_reg[8] ;
  input \EX_Op3_reg[8]_0 ;
  input \EX_Op3_reg[9] ;
  input \EX_Op3_reg[9]_0 ;
  input \EX_Op3_reg[10] ;
  input \EX_Op3_reg[10]_0 ;
  input \EX_Op3_reg[11] ;
  input \EX_Op3_reg[11]_0 ;
  input \EX_Op3_reg[12] ;
  input \EX_Op3_reg[12]_0 ;
  input \EX_Op3_reg[13] ;
  input \EX_Op3_reg[13]_0 ;
  input \EX_Op3_reg[14] ;
  input \EX_Op3_reg[14]_0 ;
  input \EX_Op3_reg[15] ;
  input \EX_Op3_reg[15]_0 ;
  input \EX_Op3_reg[16] ;
  input [7:0]\EX_Op3_reg[16]_0 ;
  input \EX_Op3_reg[17] ;
  input \EX_Op3_reg[18] ;
  input \EX_Op3_reg[19] ;
  input \EX_Op3_reg[20] ;
  input \EX_Op3_reg[21] ;
  input \EX_Op3_reg[22] ;
  input \EX_Op3_reg[23] ;
  input \EX_Op3_reg[24] ;
  input \EX_Op3_reg[24]_0 ;
  input \EX_Op3_reg[25] ;
  input \EX_Op3_reg[25]_0 ;
  input \EX_Op3_reg[26] ;
  input \EX_Op3_reg[26]_0 ;
  input \EX_Op3_reg[27] ;
  input \EX_Op3_reg[27]_0 ;
  input \EX_Op3_reg[28] ;
  input \EX_Op3_reg[28]_0 ;
  input \EX_Op3_reg[29] ;
  input \EX_Op3_reg[29]_0 ;
  input \EX_Op3_reg[30] ;
  input \EX_Op3_reg[30]_0 ;
  input \EX_Op3_reg[31] ;
  input \EX_Op3_reg[31]_0 ;
  input of_read_mem_write_op3_conflict__1;
  input mem_valid_instr;
  input mem_gpr_write;
  input p_216_in;
  input [0:0]\EX_Op3[0]_i_2_0 ;
  input \EX_Op3[0]_i_2_1 ;
  input \EX_Op3[0]_i_2_2 ;
  input \EX_Op3[0]_i_2_3 ;
  input \EX_Op3[0]_i_2_4 ;
  input [0:0]\EX_Op3[0]_i_2_5 ;
  input \EX_Op3[0]_i_2_6 ;
  input \EX_Op3[0]_i_2_7 ;

  wire Clk;
  wire [0:0]\EX_Op3[0]_i_2_0 ;
  wire \EX_Op3[0]_i_2_1 ;
  wire \EX_Op3[0]_i_2_2 ;
  wire \EX_Op3[0]_i_2_3 ;
  wire \EX_Op3[0]_i_2_4 ;
  wire [0:0]\EX_Op3[0]_i_2_5 ;
  wire \EX_Op3[0]_i_2_6 ;
  wire \EX_Op3[0]_i_2_7 ;
  wire \EX_Op3_reg[0] ;
  wire \EX_Op3_reg[0]_0 ;
  wire \EX_Op3_reg[10] ;
  wire \EX_Op3_reg[10]_0 ;
  wire \EX_Op3_reg[11] ;
  wire \EX_Op3_reg[11]_0 ;
  wire \EX_Op3_reg[12] ;
  wire \EX_Op3_reg[12]_0 ;
  wire \EX_Op3_reg[13] ;
  wire \EX_Op3_reg[13]_0 ;
  wire \EX_Op3_reg[14] ;
  wire \EX_Op3_reg[14]_0 ;
  wire \EX_Op3_reg[15] ;
  wire \EX_Op3_reg[15]_0 ;
  wire \EX_Op3_reg[16] ;
  wire [7:0]\EX_Op3_reg[16]_0 ;
  wire \EX_Op3_reg[17] ;
  wire \EX_Op3_reg[18] ;
  wire \EX_Op3_reg[19] ;
  wire \EX_Op3_reg[1] ;
  wire \EX_Op3_reg[1]_0 ;
  wire \EX_Op3_reg[20] ;
  wire \EX_Op3_reg[21] ;
  wire \EX_Op3_reg[22] ;
  wire \EX_Op3_reg[23] ;
  wire \EX_Op3_reg[24] ;
  wire \EX_Op3_reg[24]_0 ;
  wire \EX_Op3_reg[25] ;
  wire \EX_Op3_reg[25]_0 ;
  wire \EX_Op3_reg[26] ;
  wire \EX_Op3_reg[26]_0 ;
  wire \EX_Op3_reg[27] ;
  wire \EX_Op3_reg[27]_0 ;
  wire \EX_Op3_reg[28] ;
  wire \EX_Op3_reg[28]_0 ;
  wire \EX_Op3_reg[29] ;
  wire \EX_Op3_reg[29]_0 ;
  wire \EX_Op3_reg[2] ;
  wire \EX_Op3_reg[2]_0 ;
  wire \EX_Op3_reg[30] ;
  wire \EX_Op3_reg[30]_0 ;
  wire \EX_Op3_reg[31] ;
  wire \EX_Op3_reg[31]_0 ;
  wire \EX_Op3_reg[3] ;
  wire \EX_Op3_reg[3]_0 ;
  wire \EX_Op3_reg[4] ;
  wire \EX_Op3_reg[4]_0 ;
  wire \EX_Op3_reg[5] ;
  wire \EX_Op3_reg[5]_0 ;
  wire \EX_Op3_reg[6] ;
  wire \EX_Op3_reg[6]_0 ;
  wire \EX_Op3_reg[7] ;
  wire \EX_Op3_reg[7]_0 ;
  wire \EX_Op3_reg[8] ;
  wire \EX_Op3_reg[8]_0 ;
  wire \EX_Op3_reg[9] ;
  wire \EX_Op3_reg[9]_0 ;
  wire [0:31]GPR_Op3;
  wire [0:31]MEM_Fwd;
  wire \Using_FPGA.Native_0 ;
  wire [31:0]ex_sel_alu_i_reg;
  wire mem_gpr_write;
  wire mem_valid_instr;
  wire mem_valid_reg;
  wire of_instr_ii_10;
  wire [0:1]of_op3_sel;
  wire of_read_ex_write_op3_conflict__1;
  wire of_read_mem_write_op3_conflict__1;
  wire of_read_wb_write_op3_conflict__1;
  wire p_216_in;
  wire sync_reset;

  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[0]_i_1 
       (.I0(\EX_Op3_reg[0] ),
        .I1(GPR_Op3[0]),
        .I2(\EX_Op3_reg[0]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[0]),
        .O(ex_sel_alu_i_reg[31]));
  LUT3 #(
    .INIT(8'h0E)) 
    \EX_Op3[0]_i_2 
       (.I0(of_read_mem_write_op3_conflict__1),
        .I1(of_read_wb_write_op3_conflict__1),
        .I2(of_read_ex_write_op3_conflict__1),
        .O(of_op3_sel[0]));
  LUT3 #(
    .INIT(8'hF4)) 
    \EX_Op3[0]_i_3 
       (.I0(of_read_mem_write_op3_conflict__1),
        .I1(of_read_wb_write_op3_conflict__1),
        .I2(of_read_ex_write_op3_conflict__1),
        .O(of_op3_sel[1]));
  LUT6 #(
    .INIT(64'h8008000000000000)) 
    \EX_Op3[0]_i_5 
       (.I0(\EX_Op3[0]_i_2_4 ),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op3[0]_i_2_5 ),
        .I3(\EX_Op3[0]_i_2_1 ),
        .I4(\EX_Op3[0]_i_2_6 ),
        .I5(\EX_Op3[0]_i_2_7 ),
        .O(of_read_wb_write_op3_conflict__1));
  LUT6 #(
    .INIT(64'h8008000000000000)) 
    \EX_Op3[0]_i_6 
       (.I0(p_216_in),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op3[0]_i_2_0 ),
        .I3(\EX_Op3[0]_i_2_1 ),
        .I4(\EX_Op3[0]_i_2_2 ),
        .I5(\EX_Op3[0]_i_2_3 ),
        .O(of_read_ex_write_op3_conflict__1));
  LUT3 #(
    .INIT(8'h80)) 
    \EX_Op3[0]_i_8 
       (.I0(mem_valid_instr),
        .I1(mem_gpr_write),
        .I2(\Using_FPGA.Native_0 ),
        .O(mem_valid_reg));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[10]_i_1 
       (.I0(\EX_Op3_reg[10] ),
        .I1(GPR_Op3[10]),
        .I2(\EX_Op3_reg[10]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[10]),
        .O(ex_sel_alu_i_reg[21]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[11]_i_1 
       (.I0(\EX_Op3_reg[11] ),
        .I1(GPR_Op3[11]),
        .I2(\EX_Op3_reg[11]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[11]),
        .O(ex_sel_alu_i_reg[20]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[12]_i_1 
       (.I0(\EX_Op3_reg[12] ),
        .I1(GPR_Op3[12]),
        .I2(\EX_Op3_reg[12]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[12]),
        .O(ex_sel_alu_i_reg[19]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[13]_i_1 
       (.I0(\EX_Op3_reg[13] ),
        .I1(GPR_Op3[13]),
        .I2(\EX_Op3_reg[13]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[13]),
        .O(ex_sel_alu_i_reg[18]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[14]_i_1 
       (.I0(\EX_Op3_reg[14] ),
        .I1(GPR_Op3[14]),
        .I2(\EX_Op3_reg[14]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[14]),
        .O(ex_sel_alu_i_reg[17]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[15]_i_1 
       (.I0(\EX_Op3_reg[15] ),
        .I1(GPR_Op3[15]),
        .I2(\EX_Op3_reg[15]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[15]),
        .O(ex_sel_alu_i_reg[16]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[16]_i_1 
       (.I0(\EX_Op3_reg[16] ),
        .I1(GPR_Op3[16]),
        .I2(\EX_Op3_reg[16]_0 [7]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[16]),
        .O(ex_sel_alu_i_reg[15]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[17]_i_1 
       (.I0(\EX_Op3_reg[17] ),
        .I1(GPR_Op3[17]),
        .I2(\EX_Op3_reg[16]_0 [6]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[17]),
        .O(ex_sel_alu_i_reg[14]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[18]_i_1 
       (.I0(\EX_Op3_reg[18] ),
        .I1(GPR_Op3[18]),
        .I2(\EX_Op3_reg[16]_0 [5]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[18]),
        .O(ex_sel_alu_i_reg[13]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[19]_i_1 
       (.I0(\EX_Op3_reg[19] ),
        .I1(GPR_Op3[19]),
        .I2(\EX_Op3_reg[16]_0 [4]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[19]),
        .O(ex_sel_alu_i_reg[12]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[1]_i_1 
       (.I0(\EX_Op3_reg[1] ),
        .I1(GPR_Op3[1]),
        .I2(\EX_Op3_reg[1]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[1]),
        .O(ex_sel_alu_i_reg[30]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[20]_i_1 
       (.I0(\EX_Op3_reg[20] ),
        .I1(GPR_Op3[20]),
        .I2(\EX_Op3_reg[16]_0 [3]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[20]),
        .O(ex_sel_alu_i_reg[11]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[21]_i_1 
       (.I0(\EX_Op3_reg[21] ),
        .I1(GPR_Op3[21]),
        .I2(\EX_Op3_reg[16]_0 [2]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[21]),
        .O(ex_sel_alu_i_reg[10]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[22]_i_1 
       (.I0(\EX_Op3_reg[22] ),
        .I1(GPR_Op3[22]),
        .I2(\EX_Op3_reg[16]_0 [1]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[22]),
        .O(ex_sel_alu_i_reg[9]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[23]_i_1 
       (.I0(\EX_Op3_reg[23] ),
        .I1(GPR_Op3[23]),
        .I2(\EX_Op3_reg[16]_0 [0]),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[23]),
        .O(ex_sel_alu_i_reg[8]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[24]_i_1 
       (.I0(\EX_Op3_reg[24] ),
        .I1(GPR_Op3[24]),
        .I2(\EX_Op3_reg[24]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[24]),
        .O(ex_sel_alu_i_reg[7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[25]_i_1 
       (.I0(\EX_Op3_reg[25] ),
        .I1(GPR_Op3[25]),
        .I2(\EX_Op3_reg[25]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[25]),
        .O(ex_sel_alu_i_reg[6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[26]_i_1 
       (.I0(\EX_Op3_reg[26] ),
        .I1(GPR_Op3[26]),
        .I2(\EX_Op3_reg[26]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[26]),
        .O(ex_sel_alu_i_reg[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[27]_i_1 
       (.I0(\EX_Op3_reg[27] ),
        .I1(GPR_Op3[27]),
        .I2(\EX_Op3_reg[27]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[27]),
        .O(ex_sel_alu_i_reg[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[28]_i_1 
       (.I0(\EX_Op3_reg[28] ),
        .I1(GPR_Op3[28]),
        .I2(\EX_Op3_reg[28]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[28]),
        .O(ex_sel_alu_i_reg[3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[29]_i_1 
       (.I0(\EX_Op3_reg[29] ),
        .I1(GPR_Op3[29]),
        .I2(\EX_Op3_reg[29]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[29]),
        .O(ex_sel_alu_i_reg[2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[2]_i_1 
       (.I0(\EX_Op3_reg[2] ),
        .I1(GPR_Op3[2]),
        .I2(\EX_Op3_reg[2]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[2]),
        .O(ex_sel_alu_i_reg[29]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[30]_i_1 
       (.I0(\EX_Op3_reg[30] ),
        .I1(GPR_Op3[30]),
        .I2(\EX_Op3_reg[30]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[30]),
        .O(ex_sel_alu_i_reg[1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[31]_i_1 
       (.I0(\EX_Op3_reg[31] ),
        .I1(GPR_Op3[31]),
        .I2(\EX_Op3_reg[31]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[31]),
        .O(ex_sel_alu_i_reg[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[3]_i_1 
       (.I0(\EX_Op3_reg[3] ),
        .I1(GPR_Op3[3]),
        .I2(\EX_Op3_reg[3]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[3]),
        .O(ex_sel_alu_i_reg[28]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[4]_i_1 
       (.I0(\EX_Op3_reg[4] ),
        .I1(GPR_Op3[4]),
        .I2(\EX_Op3_reg[4]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[4]),
        .O(ex_sel_alu_i_reg[27]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[5]_i_1 
       (.I0(\EX_Op3_reg[5] ),
        .I1(GPR_Op3[5]),
        .I2(\EX_Op3_reg[5]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[5]),
        .O(ex_sel_alu_i_reg[26]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[6]_i_1 
       (.I0(\EX_Op3_reg[6] ),
        .I1(GPR_Op3[6]),
        .I2(\EX_Op3_reg[6]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[6]),
        .O(ex_sel_alu_i_reg[25]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[7]_i_1 
       (.I0(\EX_Op3_reg[7] ),
        .I1(GPR_Op3[7]),
        .I2(\EX_Op3_reg[7]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[7]),
        .O(ex_sel_alu_i_reg[24]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[8]_i_1 
       (.I0(\EX_Op3_reg[8] ),
        .I1(GPR_Op3[8]),
        .I2(\EX_Op3_reg[8]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[8]),
        .O(ex_sel_alu_i_reg[23]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op3[9]_i_1 
       (.I0(\EX_Op3_reg[9] ),
        .I1(GPR_Op3[9]),
        .I2(\EX_Op3_reg[9]_0 ),
        .I3(of_op3_sel[0]),
        .I4(of_op3_sel[1]),
        .I5(MEM_Fwd[9]),
        .O(ex_sel_alu_i_reg[22]));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_10),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_171
   (\Using_FPGA.Native_0 ,
    ex_sel_alu_i_reg,
    sync_reset,
    of_instr_ii_9,
    Clk,
    \EX_Branch_CMP_Op1_reg[0] ,
    GPR_Op1,
    \EX_Branch_CMP_Op1_reg[0]_0 ,
    MEM_Fwd,
    \EX_Branch_CMP_Op1_reg[1] ,
    \EX_Branch_CMP_Op1_reg[1]_0 ,
    \EX_Branch_CMP_Op1_reg[2] ,
    \EX_Branch_CMP_Op1_reg[2]_0 ,
    \EX_Branch_CMP_Op1_reg[3] ,
    \EX_Branch_CMP_Op1_reg[3]_0 ,
    \EX_Branch_CMP_Op1_reg[4] ,
    \EX_Branch_CMP_Op1_reg[4]_0 ,
    \EX_Branch_CMP_Op1_reg[5] ,
    \EX_Branch_CMP_Op1_reg[5]_0 ,
    \EX_Branch_CMP_Op1_reg[6] ,
    \EX_Branch_CMP_Op1_reg[6]_0 ,
    \EX_Branch_CMP_Op1_reg[7] ,
    \EX_Branch_CMP_Op1_reg[7]_0 ,
    \EX_Branch_CMP_Op1_reg[8] ,
    \EX_Branch_CMP_Op1_reg[8]_0 ,
    \EX_Branch_CMP_Op1_reg[9] ,
    \EX_Branch_CMP_Op1_reg[9]_0 ,
    \EX_Branch_CMP_Op1_reg[10] ,
    \EX_Branch_CMP_Op1_reg[10]_0 ,
    \EX_Branch_CMP_Op1_reg[11] ,
    \EX_Branch_CMP_Op1_reg[11]_0 ,
    \EX_Branch_CMP_Op1_reg[12] ,
    \EX_Branch_CMP_Op1_reg[12]_0 ,
    \EX_Branch_CMP_Op1_reg[13] ,
    \EX_Branch_CMP_Op1_reg[13]_0 ,
    \EX_Branch_CMP_Op1_reg[14] ,
    \EX_Branch_CMP_Op1_reg[14]_0 ,
    \EX_Branch_CMP_Op1_reg[15] ,
    \EX_Branch_CMP_Op1_reg[15]_0 ,
    \EX_Branch_CMP_Op1_reg[16] ,
    \EX_Branch_CMP_Op1_reg[16]_0 ,
    \EX_Branch_CMP_Op1_reg[17] ,
    \EX_Branch_CMP_Op1_reg[18] ,
    \EX_Branch_CMP_Op1_reg[19] ,
    \EX_Branch_CMP_Op1_reg[20] ,
    \EX_Branch_CMP_Op1_reg[21] ,
    \EX_Branch_CMP_Op1_reg[22] ,
    \EX_Branch_CMP_Op1_reg[23] ,
    \EX_Branch_CMP_Op1_reg[24] ,
    \EX_Branch_CMP_Op1_reg[24]_0 ,
    \EX_Branch_CMP_Op1_reg[25] ,
    \EX_Branch_CMP_Op1_reg[25]_0 ,
    \EX_Branch_CMP_Op1_reg[26] ,
    \EX_Branch_CMP_Op1_reg[26]_0 ,
    \EX_Branch_CMP_Op1_reg[27] ,
    \EX_Branch_CMP_Op1_reg[27]_0 ,
    \EX_Branch_CMP_Op1_reg[28] ,
    \EX_Branch_CMP_Op1_reg[28]_0 ,
    \EX_Branch_CMP_Op1_reg[29] ,
    \EX_Branch_CMP_Op1_reg[29]_0 ,
    \EX_Branch_CMP_Op1_reg[30] ,
    \EX_Branch_CMP_Op1_reg[30]_0 ,
    \EX_Branch_CMP_Op1_reg[31] ,
    \EX_Branch_CMP_Op1_reg[31]_0 ,
    \Using_FPGA.Native_i_5__0_0 ,
    \Using_FPGA.Native_i_5__0_1 ,
    \Using_FPGA.Native_i_5__0_2 ,
    p_213_in,
    \Using_FPGA.Native_i_5__0_3 ,
    \Using_FPGA.Native_i_5__0_4 ,
    \Using_FPGA.Native_i_5__0_5 ,
    \Using_FPGA.Native_i_5__0_6 ,
    \Using_FPGA.Native_i_5__0_7 ,
    p_216_in);
  output \Using_FPGA.Native_0 ;
  output [31:0]ex_sel_alu_i_reg;
  input sync_reset;
  input of_instr_ii_9;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[0] ;
  input [0:31]GPR_Op1;
  input \EX_Branch_CMP_Op1_reg[0]_0 ;
  input [0:31]MEM_Fwd;
  input \EX_Branch_CMP_Op1_reg[1] ;
  input \EX_Branch_CMP_Op1_reg[1]_0 ;
  input \EX_Branch_CMP_Op1_reg[2] ;
  input \EX_Branch_CMP_Op1_reg[2]_0 ;
  input \EX_Branch_CMP_Op1_reg[3] ;
  input \EX_Branch_CMP_Op1_reg[3]_0 ;
  input \EX_Branch_CMP_Op1_reg[4] ;
  input \EX_Branch_CMP_Op1_reg[4]_0 ;
  input \EX_Branch_CMP_Op1_reg[5] ;
  input \EX_Branch_CMP_Op1_reg[5]_0 ;
  input \EX_Branch_CMP_Op1_reg[6] ;
  input \EX_Branch_CMP_Op1_reg[6]_0 ;
  input \EX_Branch_CMP_Op1_reg[7] ;
  input \EX_Branch_CMP_Op1_reg[7]_0 ;
  input \EX_Branch_CMP_Op1_reg[8] ;
  input \EX_Branch_CMP_Op1_reg[8]_0 ;
  input \EX_Branch_CMP_Op1_reg[9] ;
  input \EX_Branch_CMP_Op1_reg[9]_0 ;
  input \EX_Branch_CMP_Op1_reg[10] ;
  input \EX_Branch_CMP_Op1_reg[10]_0 ;
  input \EX_Branch_CMP_Op1_reg[11] ;
  input \EX_Branch_CMP_Op1_reg[11]_0 ;
  input \EX_Branch_CMP_Op1_reg[12] ;
  input \EX_Branch_CMP_Op1_reg[12]_0 ;
  input \EX_Branch_CMP_Op1_reg[13] ;
  input \EX_Branch_CMP_Op1_reg[13]_0 ;
  input \EX_Branch_CMP_Op1_reg[14] ;
  input \EX_Branch_CMP_Op1_reg[14]_0 ;
  input \EX_Branch_CMP_Op1_reg[15] ;
  input \EX_Branch_CMP_Op1_reg[15]_0 ;
  input \EX_Branch_CMP_Op1_reg[16] ;
  input [7:0]\EX_Branch_CMP_Op1_reg[16]_0 ;
  input \EX_Branch_CMP_Op1_reg[17] ;
  input \EX_Branch_CMP_Op1_reg[18] ;
  input \EX_Branch_CMP_Op1_reg[19] ;
  input \EX_Branch_CMP_Op1_reg[20] ;
  input \EX_Branch_CMP_Op1_reg[21] ;
  input \EX_Branch_CMP_Op1_reg[22] ;
  input \EX_Branch_CMP_Op1_reg[23] ;
  input \EX_Branch_CMP_Op1_reg[24] ;
  input \EX_Branch_CMP_Op1_reg[24]_0 ;
  input \EX_Branch_CMP_Op1_reg[25] ;
  input \EX_Branch_CMP_Op1_reg[25]_0 ;
  input \EX_Branch_CMP_Op1_reg[26] ;
  input \EX_Branch_CMP_Op1_reg[26]_0 ;
  input \EX_Branch_CMP_Op1_reg[27] ;
  input \EX_Branch_CMP_Op1_reg[27]_0 ;
  input \EX_Branch_CMP_Op1_reg[28] ;
  input \EX_Branch_CMP_Op1_reg[28]_0 ;
  input \EX_Branch_CMP_Op1_reg[29] ;
  input \EX_Branch_CMP_Op1_reg[29]_0 ;
  input \EX_Branch_CMP_Op1_reg[30] ;
  input \EX_Branch_CMP_Op1_reg[30]_0 ;
  input \EX_Branch_CMP_Op1_reg[31] ;
  input \EX_Branch_CMP_Op1_reg[31]_0 ;
  input [1:0]\Using_FPGA.Native_i_5__0_0 ;
  input \Using_FPGA.Native_i_5__0_1 ;
  input \Using_FPGA.Native_i_5__0_2 ;
  input p_213_in;
  input \Using_FPGA.Native_i_5__0_3 ;
  input [1:0]\Using_FPGA.Native_i_5__0_4 ;
  input \Using_FPGA.Native_i_5__0_5 ;
  input [1:0]\Using_FPGA.Native_i_5__0_6 ;
  input \Using_FPGA.Native_i_5__0_7 ;
  input p_216_in;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[0] ;
  wire \EX_Branch_CMP_Op1_reg[0]_0 ;
  wire \EX_Branch_CMP_Op1_reg[10] ;
  wire \EX_Branch_CMP_Op1_reg[10]_0 ;
  wire \EX_Branch_CMP_Op1_reg[11] ;
  wire \EX_Branch_CMP_Op1_reg[11]_0 ;
  wire \EX_Branch_CMP_Op1_reg[12] ;
  wire \EX_Branch_CMP_Op1_reg[12]_0 ;
  wire \EX_Branch_CMP_Op1_reg[13] ;
  wire \EX_Branch_CMP_Op1_reg[13]_0 ;
  wire \EX_Branch_CMP_Op1_reg[14] ;
  wire \EX_Branch_CMP_Op1_reg[14]_0 ;
  wire \EX_Branch_CMP_Op1_reg[15] ;
  wire \EX_Branch_CMP_Op1_reg[15]_0 ;
  wire \EX_Branch_CMP_Op1_reg[16] ;
  wire [7:0]\EX_Branch_CMP_Op1_reg[16]_0 ;
  wire \EX_Branch_CMP_Op1_reg[17] ;
  wire \EX_Branch_CMP_Op1_reg[18] ;
  wire \EX_Branch_CMP_Op1_reg[19] ;
  wire \EX_Branch_CMP_Op1_reg[1] ;
  wire \EX_Branch_CMP_Op1_reg[1]_0 ;
  wire \EX_Branch_CMP_Op1_reg[20] ;
  wire \EX_Branch_CMP_Op1_reg[21] ;
  wire \EX_Branch_CMP_Op1_reg[22] ;
  wire \EX_Branch_CMP_Op1_reg[23] ;
  wire \EX_Branch_CMP_Op1_reg[24] ;
  wire \EX_Branch_CMP_Op1_reg[24]_0 ;
  wire \EX_Branch_CMP_Op1_reg[25] ;
  wire \EX_Branch_CMP_Op1_reg[25]_0 ;
  wire \EX_Branch_CMP_Op1_reg[26] ;
  wire \EX_Branch_CMP_Op1_reg[26]_0 ;
  wire \EX_Branch_CMP_Op1_reg[27] ;
  wire \EX_Branch_CMP_Op1_reg[27]_0 ;
  wire \EX_Branch_CMP_Op1_reg[28] ;
  wire \EX_Branch_CMP_Op1_reg[28]_0 ;
  wire \EX_Branch_CMP_Op1_reg[29] ;
  wire \EX_Branch_CMP_Op1_reg[29]_0 ;
  wire \EX_Branch_CMP_Op1_reg[2] ;
  wire \EX_Branch_CMP_Op1_reg[2]_0 ;
  wire \EX_Branch_CMP_Op1_reg[30] ;
  wire \EX_Branch_CMP_Op1_reg[30]_0 ;
  wire \EX_Branch_CMP_Op1_reg[31] ;
  wire \EX_Branch_CMP_Op1_reg[31]_0 ;
  wire \EX_Branch_CMP_Op1_reg[3] ;
  wire \EX_Branch_CMP_Op1_reg[3]_0 ;
  wire \EX_Branch_CMP_Op1_reg[4] ;
  wire \EX_Branch_CMP_Op1_reg[4]_0 ;
  wire \EX_Branch_CMP_Op1_reg[5] ;
  wire \EX_Branch_CMP_Op1_reg[5]_0 ;
  wire \EX_Branch_CMP_Op1_reg[6] ;
  wire \EX_Branch_CMP_Op1_reg[6]_0 ;
  wire \EX_Branch_CMP_Op1_reg[7] ;
  wire \EX_Branch_CMP_Op1_reg[7]_0 ;
  wire \EX_Branch_CMP_Op1_reg[8] ;
  wire \EX_Branch_CMP_Op1_reg[8]_0 ;
  wire \EX_Branch_CMP_Op1_reg[9] ;
  wire \EX_Branch_CMP_Op1_reg[9]_0 ;
  wire [0:31]GPR_Op1;
  wire [0:31]MEM_Fwd;
  wire \Using_FPGA.Native_0 ;
  wire [1:0]\Using_FPGA.Native_i_5__0_0 ;
  wire \Using_FPGA.Native_i_5__0_1 ;
  wire \Using_FPGA.Native_i_5__0_2 ;
  wire \Using_FPGA.Native_i_5__0_3 ;
  wire [1:0]\Using_FPGA.Native_i_5__0_4 ;
  wire \Using_FPGA.Native_i_5__0_5 ;
  wire [1:0]\Using_FPGA.Native_i_5__0_6 ;
  wire \Using_FPGA.Native_i_5__0_7 ;
  wire [31:0]ex_sel_alu_i_reg;
  wire of_instr_ii_9;
  wire [0:1]of_op1_sel;
  wire of_read_ex_write_op1_conflict__0;
  wire of_read_mem_write_op1_conflict__0;
  wire of_read_wb_write_op1_conflict__0;
  wire p_213_in;
  wire p_216_in;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_9),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__11 
       (.I0(\EX_Branch_CMP_Op1_reg[1] ),
        .I1(GPR_Op1[1]),
        .I2(\EX_Branch_CMP_Op1_reg[1]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[1]),
        .O(ex_sel_alu_i_reg[30]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__12 
       (.I0(\EX_Branch_CMP_Op1_reg[2] ),
        .I1(GPR_Op1[2]),
        .I2(\EX_Branch_CMP_Op1_reg[2]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[2]),
        .O(ex_sel_alu_i_reg[29]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__13 
       (.I0(\EX_Branch_CMP_Op1_reg[3] ),
        .I1(GPR_Op1[3]),
        .I2(\EX_Branch_CMP_Op1_reg[3]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[3]),
        .O(ex_sel_alu_i_reg[28]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__14 
       (.I0(\EX_Branch_CMP_Op1_reg[4] ),
        .I1(GPR_Op1[4]),
        .I2(\EX_Branch_CMP_Op1_reg[4]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[4]),
        .O(ex_sel_alu_i_reg[27]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__15 
       (.I0(\EX_Branch_CMP_Op1_reg[5] ),
        .I1(GPR_Op1[5]),
        .I2(\EX_Branch_CMP_Op1_reg[5]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[5]),
        .O(ex_sel_alu_i_reg[26]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__16 
       (.I0(\EX_Branch_CMP_Op1_reg[6] ),
        .I1(GPR_Op1[6]),
        .I2(\EX_Branch_CMP_Op1_reg[6]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[6]),
        .O(ex_sel_alu_i_reg[25]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__17 
       (.I0(\EX_Branch_CMP_Op1_reg[7] ),
        .I1(GPR_Op1[7]),
        .I2(\EX_Branch_CMP_Op1_reg[7]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[7]),
        .O(ex_sel_alu_i_reg[24]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__18 
       (.I0(\EX_Branch_CMP_Op1_reg[8] ),
        .I1(GPR_Op1[8]),
        .I2(\EX_Branch_CMP_Op1_reg[8]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[8]),
        .O(ex_sel_alu_i_reg[23]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__19 
       (.I0(\EX_Branch_CMP_Op1_reg[9] ),
        .I1(GPR_Op1[9]),
        .I2(\EX_Branch_CMP_Op1_reg[9]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[9]),
        .O(ex_sel_alu_i_reg[22]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__20 
       (.I0(\EX_Branch_CMP_Op1_reg[10] ),
        .I1(GPR_Op1[10]),
        .I2(\EX_Branch_CMP_Op1_reg[10]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[10]),
        .O(ex_sel_alu_i_reg[21]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__21 
       (.I0(\EX_Branch_CMP_Op1_reg[11] ),
        .I1(GPR_Op1[11]),
        .I2(\EX_Branch_CMP_Op1_reg[11]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[11]),
        .O(ex_sel_alu_i_reg[20]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__22 
       (.I0(\EX_Branch_CMP_Op1_reg[12] ),
        .I1(GPR_Op1[12]),
        .I2(\EX_Branch_CMP_Op1_reg[12]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[12]),
        .O(ex_sel_alu_i_reg[19]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__23 
       (.I0(\EX_Branch_CMP_Op1_reg[13] ),
        .I1(GPR_Op1[13]),
        .I2(\EX_Branch_CMP_Op1_reg[13]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[13]),
        .O(ex_sel_alu_i_reg[18]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__24 
       (.I0(\EX_Branch_CMP_Op1_reg[14] ),
        .I1(GPR_Op1[14]),
        .I2(\EX_Branch_CMP_Op1_reg[14]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[14]),
        .O(ex_sel_alu_i_reg[17]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__25 
       (.I0(\EX_Branch_CMP_Op1_reg[15] ),
        .I1(GPR_Op1[15]),
        .I2(\EX_Branch_CMP_Op1_reg[15]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[15]),
        .O(ex_sel_alu_i_reg[16]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__26 
       (.I0(\EX_Branch_CMP_Op1_reg[16] ),
        .I1(GPR_Op1[16]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [7]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[16]),
        .O(ex_sel_alu_i_reg[15]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__27 
       (.I0(\EX_Branch_CMP_Op1_reg[17] ),
        .I1(GPR_Op1[17]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [6]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[17]),
        .O(ex_sel_alu_i_reg[14]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__28 
       (.I0(\EX_Branch_CMP_Op1_reg[18] ),
        .I1(GPR_Op1[18]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [5]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[18]),
        .O(ex_sel_alu_i_reg[13]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__29 
       (.I0(\EX_Branch_CMP_Op1_reg[19] ),
        .I1(GPR_Op1[19]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [4]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[19]),
        .O(ex_sel_alu_i_reg[12]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__30 
       (.I0(\EX_Branch_CMP_Op1_reg[20] ),
        .I1(GPR_Op1[20]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [3]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[20]),
        .O(ex_sel_alu_i_reg[11]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__31 
       (.I0(\EX_Branch_CMP_Op1_reg[21] ),
        .I1(GPR_Op1[21]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [2]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[21]),
        .O(ex_sel_alu_i_reg[10]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__32 
       (.I0(\EX_Branch_CMP_Op1_reg[22] ),
        .I1(GPR_Op1[22]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [1]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[22]),
        .O(ex_sel_alu_i_reg[9]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__33 
       (.I0(\EX_Branch_CMP_Op1_reg[23] ),
        .I1(GPR_Op1[23]),
        .I2(\EX_Branch_CMP_Op1_reg[16]_0 [0]),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[23]),
        .O(ex_sel_alu_i_reg[8]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__34 
       (.I0(\EX_Branch_CMP_Op1_reg[24] ),
        .I1(GPR_Op1[24]),
        .I2(\EX_Branch_CMP_Op1_reg[24]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[24]),
        .O(ex_sel_alu_i_reg[7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__35 
       (.I0(\EX_Branch_CMP_Op1_reg[25] ),
        .I1(GPR_Op1[25]),
        .I2(\EX_Branch_CMP_Op1_reg[25]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[25]),
        .O(ex_sel_alu_i_reg[6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__36 
       (.I0(\EX_Branch_CMP_Op1_reg[26] ),
        .I1(GPR_Op1[26]),
        .I2(\EX_Branch_CMP_Op1_reg[26]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[26]),
        .O(ex_sel_alu_i_reg[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__37 
       (.I0(\EX_Branch_CMP_Op1_reg[27] ),
        .I1(GPR_Op1[27]),
        .I2(\EX_Branch_CMP_Op1_reg[27]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[27]),
        .O(ex_sel_alu_i_reg[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__38 
       (.I0(\EX_Branch_CMP_Op1_reg[28] ),
        .I1(GPR_Op1[28]),
        .I2(\EX_Branch_CMP_Op1_reg[28]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[28]),
        .O(ex_sel_alu_i_reg[3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__39 
       (.I0(\EX_Branch_CMP_Op1_reg[29] ),
        .I1(GPR_Op1[29]),
        .I2(\EX_Branch_CMP_Op1_reg[29]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[29]),
        .O(ex_sel_alu_i_reg[2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__40 
       (.I0(\EX_Branch_CMP_Op1_reg[30] ),
        .I1(GPR_Op1[30]),
        .I2(\EX_Branch_CMP_Op1_reg[30]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[30]),
        .O(ex_sel_alu_i_reg[1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_1__41 
       (.I0(\EX_Branch_CMP_Op1_reg[31] ),
        .I1(GPR_Op1[31]),
        .I2(\EX_Branch_CMP_Op1_reg[31]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[31]),
        .O(ex_sel_alu_i_reg[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \Using_FPGA.Native_i_2__24 
       (.I0(\EX_Branch_CMP_Op1_reg[0] ),
        .I1(GPR_Op1[0]),
        .I2(\EX_Branch_CMP_Op1_reg[0]_0 ),
        .I3(of_op1_sel[0]),
        .I4(of_op1_sel[1]),
        .I5(MEM_Fwd[0]),
        .O(ex_sel_alu_i_reg[31]));
  LUT3 #(
    .INIT(8'h0E)) 
    \Using_FPGA.Native_i_5__0 
       (.I0(of_read_mem_write_op1_conflict__0),
        .I1(of_read_wb_write_op1_conflict__0),
        .I2(of_read_ex_write_op1_conflict__0),
        .O(of_op1_sel[0]));
  LUT3 #(
    .INIT(8'hF4)) 
    \Using_FPGA.Native_i_6__0 
       (.I0(of_read_mem_write_op1_conflict__0),
        .I1(of_read_wb_write_op1_conflict__0),
        .I2(of_read_ex_write_op1_conflict__0),
        .O(of_op1_sel[1]));
  LUT6 #(
    .INIT(64'h9000009000000000)) 
    \Using_FPGA.Native_i_7 
       (.I0(\Using_FPGA.Native_i_5__0_0 [1]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\Using_FPGA.Native_i_5__0_1 ),
        .I3(\Using_FPGA.Native_i_5__0_2 ),
        .I4(\Using_FPGA.Native_i_5__0_0 [0]),
        .I5(p_213_in),
        .O(of_read_mem_write_op1_conflict__0));
  LUT6 #(
    .INIT(64'h8200000000008200)) 
    \Using_FPGA.Native_i_8 
       (.I0(\Using_FPGA.Native_i_5__0_3 ),
        .I1(\Using_FPGA.Native_i_5__0_4 [1]),
        .I2(\Using_FPGA.Native_0 ),
        .I3(\Using_FPGA.Native_i_5__0_5 ),
        .I4(\Using_FPGA.Native_i_5__0_2 ),
        .I5(\Using_FPGA.Native_i_5__0_4 [0]),
        .O(of_read_wb_write_op1_conflict__0));
  LUT6 #(
    .INIT(64'h9000009000000000)) 
    \Using_FPGA.Native_i_9 
       (.I0(\Using_FPGA.Native_i_5__0_6 [1]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\Using_FPGA.Native_i_5__0_7 ),
        .I3(\Using_FPGA.Native_i_5__0_2 ),
        .I4(\Using_FPGA.Native_i_5__0_6 [0]),
        .I5(p_216_in),
        .O(of_read_ex_write_op1_conflict__0));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_173
   (of_predecode,
    sync_reset,
    of_instr_ii_8,
    Clk);
  output [0:0]of_predecode;
  input sync_reset;
  input of_instr_ii_8;
  input Clk;

  wire Clk;
  wire of_instr_ii_8;
  wire [0:0]of_predecode;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_8),
        .Q(of_predecode),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_175
   (\Using_FPGA.Native_0 ,
    sync_reset,
    of_instr_ii_7,
    Clk);
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input of_instr_ii_7;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_7;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_7),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_177
   (\Using_FPGA.Native_0 ,
    sync_reset,
    of_instr_ii_6,
    Clk);
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input of_instr_ii_6;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_6;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_6),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_179
   (\Using_FPGA.Native_0 ,
    \mem_gpr_write_addr_reg[4] ,
    \wb_gpr_write_addr_reg[4] ,
    \ex_gpr_write_addr_reg[4] ,
    sync_reset,
    of_instr_ii_5,
    Clk,
    \Using_FPGA.Native_i_7 ,
    \Using_FPGA.Native_i_7_0 ,
    \Using_FPGA.Native_i_7_1 ,
    \Using_FPGA.Native_i_8 ,
    \Using_FPGA.Native_i_9 ,
    I4,
    I0);
  output \Using_FPGA.Native_0 ;
  output \mem_gpr_write_addr_reg[4] ;
  output \wb_gpr_write_addr_reg[4] ;
  output \ex_gpr_write_addr_reg[4] ;
  input sync_reset;
  input of_instr_ii_5;
  input Clk;
  input [2:0]\Using_FPGA.Native_i_7 ;
  input \Using_FPGA.Native_i_7_0 ;
  input \Using_FPGA.Native_i_7_1 ;
  input [2:0]\Using_FPGA.Native_i_8 ;
  input \Using_FPGA.Native_i_9 ;
  input I4;
  input I0;

  wire Clk;
  wire I0;
  wire I4;
  wire \Using_FPGA.Native_0 ;
  wire [2:0]\Using_FPGA.Native_i_7 ;
  wire \Using_FPGA.Native_i_7_0 ;
  wire \Using_FPGA.Native_i_7_1 ;
  wire [2:0]\Using_FPGA.Native_i_8 ;
  wire \Using_FPGA.Native_i_9 ;
  wire \ex_gpr_write_addr_reg[4] ;
  wire \mem_gpr_write_addr_reg[4] ;
  wire of_instr_ii_5;
  wire sync_reset;
  wire \wb_gpr_write_addr_reg[4] ;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_5),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native_i_10 
       (.I0(\Using_FPGA.Native_i_7 [0]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\Using_FPGA.Native_i_7_0 ),
        .I3(\Using_FPGA.Native_i_7 [2]),
        .I4(\Using_FPGA.Native_i_7_1 ),
        .I5(\Using_FPGA.Native_i_7 [1]),
        .O(\mem_gpr_write_addr_reg[4] ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native_i_12 
       (.I0(\Using_FPGA.Native_i_8 [0]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\Using_FPGA.Native_i_7_0 ),
        .I3(\Using_FPGA.Native_i_8 [2]),
        .I4(\Using_FPGA.Native_i_7_1 ),
        .I5(\Using_FPGA.Native_i_8 [1]),
        .O(\wb_gpr_write_addr_reg[4] ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native_i_13 
       (.I0(\Using_FPGA.Native_i_9 ),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\Using_FPGA.Native_i_7_0 ),
        .I3(I4),
        .I4(\Using_FPGA.Native_i_7_1 ),
        .I5(I0),
        .O(\ex_gpr_write_addr_reg[4] ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_181
   (\Using_FPGA.Native_0 ,
    ex_sel_alu_i_reg,
    sync_reset,
    of_instr_ii_4,
    Clk,
    \EX_Op2_reg[31] ,
    \EX_Op2_reg[31]_0 ,
    \EX_Op2_reg[31]_1 ,
    MEM_Fwd,
    \EX_Op2_reg[30] ,
    \EX_Op2_reg[30]_0 ,
    \EX_Op2_reg[30]_1 ,
    \EX_Op2_reg[29] ,
    \EX_Op2_reg[29]_0 ,
    \EX_Op2_reg[29]_1 ,
    \EX_Op2_reg[28] ,
    \EX_Op2_reg[28]_0 ,
    \EX_Op2_reg[28]_1 ,
    \EX_Op2_reg[27] ,
    \EX_Op2_reg[27]_0 ,
    \EX_Op2_reg[27]_1 ,
    \EX_Op2_reg[26] ,
    \EX_Op2_reg[26]_0 ,
    \EX_Op2_reg[26]_1 ,
    \EX_Op2_reg[25] ,
    \EX_Op2_reg[25]_0 ,
    \EX_Op2_reg[25]_1 ,
    \EX_Op2_reg[24] ,
    \EX_Op2_reg[24]_0 ,
    \EX_Op2_reg[24]_1 ,
    \EX_Op2_reg[23] ,
    \EX_Op2_reg[23]_0 ,
    \EX_Op2_reg[16] ,
    \EX_Op2_reg[22] ,
    \EX_Op2_reg[22]_0 ,
    \EX_Op2_reg[21] ,
    \EX_Op2_reg[21]_0 ,
    \EX_Op2_reg[20] ,
    \EX_Op2_reg[20]_0 ,
    \EX_Op2_reg[19] ,
    \EX_Op2_reg[19]_0 ,
    \EX_Op2_reg[18] ,
    \EX_Op2_reg[18]_0 ,
    \EX_Op2_reg[17] ,
    \EX_Op2_reg[17]_0 ,
    \EX_Op2_reg[16]_0 ,
    \EX_Op2_reg[16]_1 ,
    \EX_Op2_reg[15] ,
    \EX_Op2_reg[15]_0 ,
    \EX_Op2_reg[15]_1 ,
    \EX_Op2_reg[14] ,
    \EX_Op2_reg[14]_0 ,
    \EX_Op2_reg[14]_1 ,
    \EX_Op2_reg[13] ,
    \EX_Op2_reg[13]_0 ,
    \EX_Op2_reg[13]_1 ,
    \EX_Op2_reg[12] ,
    \EX_Op2_reg[12]_0 ,
    \EX_Op2_reg[12]_1 ,
    \EX_Op2_reg[11] ,
    \EX_Op2_reg[11]_0 ,
    \EX_Op2_reg[11]_1 ,
    \EX_Op2_reg[10] ,
    \EX_Op2_reg[10]_0 ,
    \EX_Op2_reg[10]_1 ,
    \EX_Op2_reg[9] ,
    \EX_Op2_reg[9]_0 ,
    \EX_Op2_reg[9]_1 ,
    \EX_Op2_reg[8] ,
    \EX_Op2_reg[8]_0 ,
    \EX_Op2_reg[8]_1 ,
    \EX_Op2_reg[7] ,
    \EX_Op2_reg[7]_0 ,
    \EX_Op2_reg[7]_1 ,
    \EX_Op2_reg[6] ,
    \EX_Op2_reg[6]_0 ,
    \EX_Op2_reg[6]_1 ,
    \EX_Op2_reg[5] ,
    \EX_Op2_reg[5]_0 ,
    \EX_Op2_reg[5]_1 ,
    \EX_Op2_reg[4] ,
    \EX_Op2_reg[4]_0 ,
    \EX_Op2_reg[4]_1 ,
    \EX_Op2_reg[3] ,
    \EX_Op2_reg[3]_0 ,
    \EX_Op2_reg[3]_1 ,
    \EX_Op2_reg[2] ,
    \EX_Op2_reg[2]_0 ,
    \EX_Op2_reg[2]_1 ,
    \EX_Op2_reg[1] ,
    \EX_Op2_reg[1]_0 ,
    \EX_Op2_reg[1]_1 ,
    \EX_Op2_reg[0] ,
    \EX_Op2_reg[0]_0 ,
    \EX_Op2_reg[0]_1 ,
    of_use_op2_s,
    \EX_Op2[0]_i_3_0 ,
    \EX_Op2[0]_i_3_1 ,
    \EX_Op2[0]_i_3_2 ,
    p_213_in,
    \EX_Op2[0]_i_3_3 ,
    \EX_Op2[0]_i_3_4 ,
    p_216_in,
    \EX_Op2[0]_i_3_5 ,
    \EX_Op2[0]_i_3_6 ,
    \EX_Op2[0]_i_3_7 );
  output \Using_FPGA.Native_0 ;
  output [31:0]ex_sel_alu_i_reg;
  input sync_reset;
  input of_instr_ii_4;
  input Clk;
  input \EX_Op2_reg[31] ;
  input \EX_Op2_reg[31]_0 ;
  input \EX_Op2_reg[31]_1 ;
  input [0:31]MEM_Fwd;
  input \EX_Op2_reg[30] ;
  input \EX_Op2_reg[30]_0 ;
  input \EX_Op2_reg[30]_1 ;
  input \EX_Op2_reg[29] ;
  input \EX_Op2_reg[29]_0 ;
  input \EX_Op2_reg[29]_1 ;
  input \EX_Op2_reg[28] ;
  input \EX_Op2_reg[28]_0 ;
  input \EX_Op2_reg[28]_1 ;
  input \EX_Op2_reg[27] ;
  input \EX_Op2_reg[27]_0 ;
  input \EX_Op2_reg[27]_1 ;
  input \EX_Op2_reg[26] ;
  input \EX_Op2_reg[26]_0 ;
  input \EX_Op2_reg[26]_1 ;
  input \EX_Op2_reg[25] ;
  input \EX_Op2_reg[25]_0 ;
  input \EX_Op2_reg[25]_1 ;
  input \EX_Op2_reg[24] ;
  input \EX_Op2_reg[24]_0 ;
  input \EX_Op2_reg[24]_1 ;
  input \EX_Op2_reg[23] ;
  input \EX_Op2_reg[23]_0 ;
  input [7:0]\EX_Op2_reg[16] ;
  input \EX_Op2_reg[22] ;
  input \EX_Op2_reg[22]_0 ;
  input \EX_Op2_reg[21] ;
  input \EX_Op2_reg[21]_0 ;
  input \EX_Op2_reg[20] ;
  input \EX_Op2_reg[20]_0 ;
  input \EX_Op2_reg[19] ;
  input \EX_Op2_reg[19]_0 ;
  input \EX_Op2_reg[18] ;
  input \EX_Op2_reg[18]_0 ;
  input \EX_Op2_reg[17] ;
  input \EX_Op2_reg[17]_0 ;
  input \EX_Op2_reg[16]_0 ;
  input \EX_Op2_reg[16]_1 ;
  input \EX_Op2_reg[15] ;
  input \EX_Op2_reg[15]_0 ;
  input \EX_Op2_reg[15]_1 ;
  input \EX_Op2_reg[14] ;
  input \EX_Op2_reg[14]_0 ;
  input \EX_Op2_reg[14]_1 ;
  input \EX_Op2_reg[13] ;
  input \EX_Op2_reg[13]_0 ;
  input \EX_Op2_reg[13]_1 ;
  input \EX_Op2_reg[12] ;
  input \EX_Op2_reg[12]_0 ;
  input \EX_Op2_reg[12]_1 ;
  input \EX_Op2_reg[11] ;
  input \EX_Op2_reg[11]_0 ;
  input \EX_Op2_reg[11]_1 ;
  input \EX_Op2_reg[10] ;
  input \EX_Op2_reg[10]_0 ;
  input \EX_Op2_reg[10]_1 ;
  input \EX_Op2_reg[9] ;
  input \EX_Op2_reg[9]_0 ;
  input \EX_Op2_reg[9]_1 ;
  input \EX_Op2_reg[8] ;
  input \EX_Op2_reg[8]_0 ;
  input \EX_Op2_reg[8]_1 ;
  input \EX_Op2_reg[7] ;
  input \EX_Op2_reg[7]_0 ;
  input \EX_Op2_reg[7]_1 ;
  input \EX_Op2_reg[6] ;
  input \EX_Op2_reg[6]_0 ;
  input \EX_Op2_reg[6]_1 ;
  input \EX_Op2_reg[5] ;
  input \EX_Op2_reg[5]_0 ;
  input \EX_Op2_reg[5]_1 ;
  input \EX_Op2_reg[4] ;
  input \EX_Op2_reg[4]_0 ;
  input \EX_Op2_reg[4]_1 ;
  input \EX_Op2_reg[3] ;
  input \EX_Op2_reg[3]_0 ;
  input \EX_Op2_reg[3]_1 ;
  input \EX_Op2_reg[2] ;
  input \EX_Op2_reg[2]_0 ;
  input \EX_Op2_reg[2]_1 ;
  input \EX_Op2_reg[1] ;
  input \EX_Op2_reg[1]_0 ;
  input \EX_Op2_reg[1]_1 ;
  input \EX_Op2_reg[0] ;
  input \EX_Op2_reg[0]_0 ;
  input \EX_Op2_reg[0]_1 ;
  input of_use_op2_s;
  input [1:0]\EX_Op2[0]_i_3_0 ;
  input \EX_Op2[0]_i_3_1 ;
  input \EX_Op2[0]_i_3_2 ;
  input p_213_in;
  input [1:0]\EX_Op2[0]_i_3_3 ;
  input \EX_Op2[0]_i_3_4 ;
  input p_216_in;
  input \EX_Op2[0]_i_3_5 ;
  input [1:0]\EX_Op2[0]_i_3_6 ;
  input \EX_Op2[0]_i_3_7 ;

  wire Clk;
  wire [1:0]\EX_Op2[0]_i_3_0 ;
  wire \EX_Op2[0]_i_3_1 ;
  wire \EX_Op2[0]_i_3_2 ;
  wire [1:0]\EX_Op2[0]_i_3_3 ;
  wire \EX_Op2[0]_i_3_4 ;
  wire \EX_Op2[0]_i_3_5 ;
  wire [1:0]\EX_Op2[0]_i_3_6 ;
  wire \EX_Op2[0]_i_3_7 ;
  wire \EX_Op2_reg[0] ;
  wire \EX_Op2_reg[0]_0 ;
  wire \EX_Op2_reg[0]_1 ;
  wire \EX_Op2_reg[10] ;
  wire \EX_Op2_reg[10]_0 ;
  wire \EX_Op2_reg[10]_1 ;
  wire \EX_Op2_reg[11] ;
  wire \EX_Op2_reg[11]_0 ;
  wire \EX_Op2_reg[11]_1 ;
  wire \EX_Op2_reg[12] ;
  wire \EX_Op2_reg[12]_0 ;
  wire \EX_Op2_reg[12]_1 ;
  wire \EX_Op2_reg[13] ;
  wire \EX_Op2_reg[13]_0 ;
  wire \EX_Op2_reg[13]_1 ;
  wire \EX_Op2_reg[14] ;
  wire \EX_Op2_reg[14]_0 ;
  wire \EX_Op2_reg[14]_1 ;
  wire \EX_Op2_reg[15] ;
  wire \EX_Op2_reg[15]_0 ;
  wire \EX_Op2_reg[15]_1 ;
  wire [7:0]\EX_Op2_reg[16] ;
  wire \EX_Op2_reg[16]_0 ;
  wire \EX_Op2_reg[16]_1 ;
  wire \EX_Op2_reg[17] ;
  wire \EX_Op2_reg[17]_0 ;
  wire \EX_Op2_reg[18] ;
  wire \EX_Op2_reg[18]_0 ;
  wire \EX_Op2_reg[19] ;
  wire \EX_Op2_reg[19]_0 ;
  wire \EX_Op2_reg[1] ;
  wire \EX_Op2_reg[1]_0 ;
  wire \EX_Op2_reg[1]_1 ;
  wire \EX_Op2_reg[20] ;
  wire \EX_Op2_reg[20]_0 ;
  wire \EX_Op2_reg[21] ;
  wire \EX_Op2_reg[21]_0 ;
  wire \EX_Op2_reg[22] ;
  wire \EX_Op2_reg[22]_0 ;
  wire \EX_Op2_reg[23] ;
  wire \EX_Op2_reg[23]_0 ;
  wire \EX_Op2_reg[24] ;
  wire \EX_Op2_reg[24]_0 ;
  wire \EX_Op2_reg[24]_1 ;
  wire \EX_Op2_reg[25] ;
  wire \EX_Op2_reg[25]_0 ;
  wire \EX_Op2_reg[25]_1 ;
  wire \EX_Op2_reg[26] ;
  wire \EX_Op2_reg[26]_0 ;
  wire \EX_Op2_reg[26]_1 ;
  wire \EX_Op2_reg[27] ;
  wire \EX_Op2_reg[27]_0 ;
  wire \EX_Op2_reg[27]_1 ;
  wire \EX_Op2_reg[28] ;
  wire \EX_Op2_reg[28]_0 ;
  wire \EX_Op2_reg[28]_1 ;
  wire \EX_Op2_reg[29] ;
  wire \EX_Op2_reg[29]_0 ;
  wire \EX_Op2_reg[29]_1 ;
  wire \EX_Op2_reg[2] ;
  wire \EX_Op2_reg[2]_0 ;
  wire \EX_Op2_reg[2]_1 ;
  wire \EX_Op2_reg[30] ;
  wire \EX_Op2_reg[30]_0 ;
  wire \EX_Op2_reg[30]_1 ;
  wire \EX_Op2_reg[31] ;
  wire \EX_Op2_reg[31]_0 ;
  wire \EX_Op2_reg[31]_1 ;
  wire \EX_Op2_reg[3] ;
  wire \EX_Op2_reg[3]_0 ;
  wire \EX_Op2_reg[3]_1 ;
  wire \EX_Op2_reg[4] ;
  wire \EX_Op2_reg[4]_0 ;
  wire \EX_Op2_reg[4]_1 ;
  wire \EX_Op2_reg[5] ;
  wire \EX_Op2_reg[5]_0 ;
  wire \EX_Op2_reg[5]_1 ;
  wire \EX_Op2_reg[6] ;
  wire \EX_Op2_reg[6]_0 ;
  wire \EX_Op2_reg[6]_1 ;
  wire \EX_Op2_reg[7] ;
  wire \EX_Op2_reg[7]_0 ;
  wire \EX_Op2_reg[7]_1 ;
  wire \EX_Op2_reg[8] ;
  wire \EX_Op2_reg[8]_0 ;
  wire \EX_Op2_reg[8]_1 ;
  wire \EX_Op2_reg[9] ;
  wire \EX_Op2_reg[9]_0 ;
  wire \EX_Op2_reg[9]_1 ;
  wire [0:31]MEM_Fwd;
  wire \Using_FPGA.Native_0 ;
  wire [31:0]ex_sel_alu_i_reg;
  wire of_instr_ii_4;
  wire [0:1]of_op2_sel;
  wire of_read_ex_write_op2_conflict__0;
  wire of_read_mem_write_op2_conflict__0;
  wire of_read_wb_write_op2_conflict__0;
  wire of_use_op2_s;
  wire p_213_in;
  wire p_216_in;
  wire sync_reset;

  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[0]_i_1 
       (.I0(\EX_Op2_reg[0] ),
        .I1(\EX_Op2_reg[0]_0 ),
        .I2(\EX_Op2_reg[0]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[0]),
        .O(ex_sel_alu_i_reg[31]));
  LUT4 #(
    .INIT(16'h2220)) 
    \EX_Op2[0]_i_3 
       (.I0(of_use_op2_s),
        .I1(of_read_ex_write_op2_conflict__0),
        .I2(of_read_wb_write_op2_conflict__0),
        .I3(of_read_mem_write_op2_conflict__0),
        .O(of_op2_sel[0]));
  LUT4 #(
    .INIT(16'h88A8)) 
    \EX_Op2[0]_i_4 
       (.I0(of_use_op2_s),
        .I1(of_read_ex_write_op2_conflict__0),
        .I2(of_read_wb_write_op2_conflict__0),
        .I3(of_read_mem_write_op2_conflict__0),
        .O(of_op2_sel[1]));
  LUT6 #(
    .INIT(64'h9000009000000000)) 
    \EX_Op2[0]_i_6 
       (.I0(\EX_Op2[0]_i_3_3 [1]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op2[0]_i_3_4 ),
        .I3(\EX_Op2[0]_i_3_2 ),
        .I4(\EX_Op2[0]_i_3_3 [0]),
        .I5(p_216_in),
        .O(of_read_ex_write_op2_conflict__0));
  LUT6 #(
    .INIT(64'h8200000000008200)) 
    \EX_Op2[0]_i_7 
       (.I0(\EX_Op2[0]_i_3_5 ),
        .I1(\EX_Op2[0]_i_3_6 [1]),
        .I2(\Using_FPGA.Native_0 ),
        .I3(\EX_Op2[0]_i_3_7 ),
        .I4(\EX_Op2[0]_i_3_2 ),
        .I5(\EX_Op2[0]_i_3_6 [0]),
        .O(of_read_wb_write_op2_conflict__0));
  LUT6 #(
    .INIT(64'h9000009000000000)) 
    \EX_Op2[0]_i_8 
       (.I0(\EX_Op2[0]_i_3_0 [1]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op2[0]_i_3_1 ),
        .I3(\EX_Op2[0]_i_3_2 ),
        .I4(\EX_Op2[0]_i_3_0 [0]),
        .I5(p_213_in),
        .O(of_read_mem_write_op2_conflict__0));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[10]_i_1 
       (.I0(\EX_Op2_reg[10] ),
        .I1(\EX_Op2_reg[10]_0 ),
        .I2(\EX_Op2_reg[10]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[10]),
        .O(ex_sel_alu_i_reg[21]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[11]_i_1 
       (.I0(\EX_Op2_reg[11] ),
        .I1(\EX_Op2_reg[11]_0 ),
        .I2(\EX_Op2_reg[11]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[11]),
        .O(ex_sel_alu_i_reg[20]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[12]_i_1 
       (.I0(\EX_Op2_reg[12] ),
        .I1(\EX_Op2_reg[12]_0 ),
        .I2(\EX_Op2_reg[12]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[12]),
        .O(ex_sel_alu_i_reg[19]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[13]_i_1 
       (.I0(\EX_Op2_reg[13] ),
        .I1(\EX_Op2_reg[13]_0 ),
        .I2(\EX_Op2_reg[13]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[13]),
        .O(ex_sel_alu_i_reg[18]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[14]_i_1 
       (.I0(\EX_Op2_reg[14] ),
        .I1(\EX_Op2_reg[14]_0 ),
        .I2(\EX_Op2_reg[14]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[14]),
        .O(ex_sel_alu_i_reg[17]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[15]_i_1 
       (.I0(\EX_Op2_reg[15] ),
        .I1(\EX_Op2_reg[15]_0 ),
        .I2(\EX_Op2_reg[15]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[15]),
        .O(ex_sel_alu_i_reg[16]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[16]_i_1 
       (.I0(\EX_Op2_reg[16]_0 ),
        .I1(\EX_Op2_reg[16]_1 ),
        .I2(\EX_Op2_reg[16] [7]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[16]),
        .O(ex_sel_alu_i_reg[15]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[17]_i_1 
       (.I0(\EX_Op2_reg[17] ),
        .I1(\EX_Op2_reg[17]_0 ),
        .I2(\EX_Op2_reg[16] [6]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[17]),
        .O(ex_sel_alu_i_reg[14]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[18]_i_1 
       (.I0(\EX_Op2_reg[18] ),
        .I1(\EX_Op2_reg[18]_0 ),
        .I2(\EX_Op2_reg[16] [5]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[18]),
        .O(ex_sel_alu_i_reg[13]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[19]_i_1 
       (.I0(\EX_Op2_reg[19] ),
        .I1(\EX_Op2_reg[19]_0 ),
        .I2(\EX_Op2_reg[16] [4]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[19]),
        .O(ex_sel_alu_i_reg[12]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[1]_i_1 
       (.I0(\EX_Op2_reg[1] ),
        .I1(\EX_Op2_reg[1]_0 ),
        .I2(\EX_Op2_reg[1]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[1]),
        .O(ex_sel_alu_i_reg[30]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[20]_i_1 
       (.I0(\EX_Op2_reg[20] ),
        .I1(\EX_Op2_reg[20]_0 ),
        .I2(\EX_Op2_reg[16] [3]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[20]),
        .O(ex_sel_alu_i_reg[11]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[21]_i_1 
       (.I0(\EX_Op2_reg[21] ),
        .I1(\EX_Op2_reg[21]_0 ),
        .I2(\EX_Op2_reg[16] [2]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[21]),
        .O(ex_sel_alu_i_reg[10]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[22]_i_1 
       (.I0(\EX_Op2_reg[22] ),
        .I1(\EX_Op2_reg[22]_0 ),
        .I2(\EX_Op2_reg[16] [1]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[22]),
        .O(ex_sel_alu_i_reg[9]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[23]_i_1 
       (.I0(\EX_Op2_reg[23] ),
        .I1(\EX_Op2_reg[23]_0 ),
        .I2(\EX_Op2_reg[16] [0]),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[23]),
        .O(ex_sel_alu_i_reg[8]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[24]_i_1 
       (.I0(\EX_Op2_reg[24] ),
        .I1(\EX_Op2_reg[24]_0 ),
        .I2(\EX_Op2_reg[24]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[24]),
        .O(ex_sel_alu_i_reg[7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[25]_i_1 
       (.I0(\EX_Op2_reg[25] ),
        .I1(\EX_Op2_reg[25]_0 ),
        .I2(\EX_Op2_reg[25]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[25]),
        .O(ex_sel_alu_i_reg[6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[26]_i_1 
       (.I0(\EX_Op2_reg[26] ),
        .I1(\EX_Op2_reg[26]_0 ),
        .I2(\EX_Op2_reg[26]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[26]),
        .O(ex_sel_alu_i_reg[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[27]_i_1 
       (.I0(\EX_Op2_reg[27] ),
        .I1(\EX_Op2_reg[27]_0 ),
        .I2(\EX_Op2_reg[27]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[27]),
        .O(ex_sel_alu_i_reg[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[28]_i_1 
       (.I0(\EX_Op2_reg[28] ),
        .I1(\EX_Op2_reg[28]_0 ),
        .I2(\EX_Op2_reg[28]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[28]),
        .O(ex_sel_alu_i_reg[3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[29]_i_1 
       (.I0(\EX_Op2_reg[29] ),
        .I1(\EX_Op2_reg[29]_0 ),
        .I2(\EX_Op2_reg[29]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[29]),
        .O(ex_sel_alu_i_reg[2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[2]_i_1 
       (.I0(\EX_Op2_reg[2] ),
        .I1(\EX_Op2_reg[2]_0 ),
        .I2(\EX_Op2_reg[2]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[2]),
        .O(ex_sel_alu_i_reg[29]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[30]_i_1 
       (.I0(\EX_Op2_reg[30] ),
        .I1(\EX_Op2_reg[30]_0 ),
        .I2(\EX_Op2_reg[30]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[30]),
        .O(ex_sel_alu_i_reg[1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[31]_i_1 
       (.I0(\EX_Op2_reg[31] ),
        .I1(\EX_Op2_reg[31]_0 ),
        .I2(\EX_Op2_reg[31]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[31]),
        .O(ex_sel_alu_i_reg[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[3]_i_1 
       (.I0(\EX_Op2_reg[3] ),
        .I1(\EX_Op2_reg[3]_0 ),
        .I2(\EX_Op2_reg[3]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[3]),
        .O(ex_sel_alu_i_reg[28]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[4]_i_1 
       (.I0(\EX_Op2_reg[4] ),
        .I1(\EX_Op2_reg[4]_0 ),
        .I2(\EX_Op2_reg[4]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[4]),
        .O(ex_sel_alu_i_reg[27]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[5]_i_1 
       (.I0(\EX_Op2_reg[5] ),
        .I1(\EX_Op2_reg[5]_0 ),
        .I2(\EX_Op2_reg[5]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[5]),
        .O(ex_sel_alu_i_reg[26]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[6]_i_1 
       (.I0(\EX_Op2_reg[6] ),
        .I1(\EX_Op2_reg[6]_0 ),
        .I2(\EX_Op2_reg[6]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[6]),
        .O(ex_sel_alu_i_reg[25]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[7]_i_1 
       (.I0(\EX_Op2_reg[7] ),
        .I1(\EX_Op2_reg[7]_0 ),
        .I2(\EX_Op2_reg[7]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[7]),
        .O(ex_sel_alu_i_reg[24]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[8]_i_1 
       (.I0(\EX_Op2_reg[8] ),
        .I1(\EX_Op2_reg[8]_0 ),
        .I2(\EX_Op2_reg[8]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[8]),
        .O(ex_sel_alu_i_reg[23]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \EX_Op2[9]_i_1 
       (.I0(\EX_Op2_reg[9] ),
        .I1(\EX_Op2_reg[9]_0 ),
        .I2(\EX_Op2_reg[9]_1 ),
        .I3(of_op2_sel[0]),
        .I4(of_op2_sel[1]),
        .I5(MEM_Fwd[9]),
        .O(ex_sel_alu_i_reg[22]));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_4),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_183
   (of_predecode,
    sync_reset,
    of_instr_ii_3,
    Clk);
  output [0:0]of_predecode;
  input sync_reset;
  input of_instr_ii_3;
  input Clk;

  wire Clk;
  wire of_instr_ii_3;
  wire [0:0]of_predecode;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_3),
        .Q(of_predecode),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_185
   (\Using_FPGA.Native_0 ,
    ex_branch_with_delayslot_i_reg,
    \Using_FPGA.Native_1 ,
    ex_op1_cmp_eq_n5_out,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    use_Reg_Neg_DI1_out,
    force_Val10_out,
    use_Reg_Neg_S3_out,
    force12_out,
    ex_sel_alu_i0,
    \Using_FPGA.Native_4 ,
    ex_enable_sext_shift_i0,
    \Using_FPGA.Native_5 ,
    \Using_FPGA.Native_6 ,
    sync_reset,
    of_instr_ii_39,
    Clk,
    ex_branch_with_delayslot_i,
    ex_branch_with_delayslot_i_reg_0,
    ex_branch_with_delayslot_i_reg_1,
    ex_op1_cmp_eq_n_reg,
    ex_op1_cmp_eq_n_reg_0,
    ex_op1_cmp_eq_n_reg_1,
    force2_reg,
    force2_reg_0,
    force2_reg_1,
    force2_reg_2,
    \EX_Sext_Op_reg[0] ,
    ex_sel_alu_i_reg,
    \EX_Sext_Op_reg[0]_0 ,
    \EX_Sext_Op_reg[0]_1 ,
    ex_branch_with_delayslot_reg,
    ex_branch_with_delayslot_reg_0,
    EX_ALU_Op1142_out__0);
  output \Using_FPGA.Native_0 ;
  output ex_branch_with_delayslot_i_reg;
  output \Using_FPGA.Native_1 ;
  output ex_op1_cmp_eq_n5_out;
  output \Using_FPGA.Native_2 ;
  output \Using_FPGA.Native_3 ;
  output use_Reg_Neg_DI1_out;
  output force_Val10_out;
  output use_Reg_Neg_S3_out;
  output force12_out;
  output ex_sel_alu_i0;
  output [0:0]\Using_FPGA.Native_4 ;
  output ex_enable_sext_shift_i0;
  output \Using_FPGA.Native_5 ;
  output \Using_FPGA.Native_6 ;
  input sync_reset;
  input of_instr_ii_39;
  input Clk;
  input ex_branch_with_delayslot_i;
  input ex_branch_with_delayslot_i_reg_0;
  input ex_branch_with_delayslot_i_reg_1;
  input ex_op1_cmp_eq_n_reg;
  input ex_op1_cmp_eq_n_reg_0;
  input ex_op1_cmp_eq_n_reg_1;
  input force2_reg;
  input force2_reg_0;
  input force2_reg_1;
  input force2_reg_2;
  input \EX_Sext_Op_reg[0] ;
  input ex_sel_alu_i_reg;
  input \EX_Sext_Op_reg[0]_0 ;
  input \EX_Sext_Op_reg[0]_1 ;
  input ex_branch_with_delayslot_reg;
  input ex_branch_with_delayslot_reg_0;
  input EX_ALU_Op1142_out__0;

  wire Clk;
  wire EX_ALU_Op1142_out__0;
  wire \EX_Sext_Op_reg[0] ;
  wire \EX_Sext_Op_reg[0]_0 ;
  wire \EX_Sext_Op_reg[0]_1 ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire [0:0]\Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire ex_branch_with_delayslot_i;
  wire ex_branch_with_delayslot_i_2_n_0;
  wire ex_branch_with_delayslot_i_reg;
  wire ex_branch_with_delayslot_i_reg_0;
  wire ex_branch_with_delayslot_i_reg_1;
  wire ex_branch_with_delayslot_reg;
  wire ex_branch_with_delayslot_reg_0;
  wire ex_enable_sext_shift_i0;
  wire ex_op1_cmp_eq_n5_out;
  wire ex_op1_cmp_eq_n_reg;
  wire ex_op1_cmp_eq_n_reg_0;
  wire ex_op1_cmp_eq_n_reg_1;
  wire ex_sel_alu_i0;
  wire ex_sel_alu_i_reg;
  wire force12_out;
  wire force2_reg;
  wire force2_reg_0;
  wire force2_reg_1;
  wire force2_reg_2;
  wire force_Val10_out;
  wire of_instr_ii_39;
  wire sync_reset;
  wire use_Reg_Neg_DI1_out;
  wire use_Reg_Neg_S3_out;

  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7FFF)) 
    \EX_Sext_Op[0]_i_1 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\EX_Sext_Op_reg[0]_0 ),
        .I2(force2_reg),
        .I3(\EX_Sext_Op_reg[0]_1 ),
        .I4(force2_reg_1),
        .I5(\EX_Sext_Op_reg[0] ),
        .O(\Using_FPGA.Native_4 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_39),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \Using_FPGA.Native_i_2__83 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(force2_reg),
        .I2(force2_reg_0),
        .I3(\EX_Sext_Op_reg[0] ),
        .O(\Using_FPGA.Native_5 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h08)) 
    ex_branch_with_delayslot_i_1
       (.I0(ex_branch_with_delayslot_i_2_n_0),
        .I1(force2_reg),
        .I2(force2_reg_1),
        .O(\Using_FPGA.Native_1 ));
  LUT6 #(
    .INIT(64'hAA80A0800A800080)) 
    ex_branch_with_delayslot_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_branch_with_delayslot_reg),
        .I2(force2_reg_2),
        .I3(force2_reg_0),
        .I4(\EX_Sext_Op_reg[0] ),
        .I5(ex_branch_with_delayslot_reg_0),
        .O(ex_branch_with_delayslot_i_2_n_0));
  LUT5 #(
    .INIT(32'h000000E2)) 
    ex_branch_with_delayslot_i_i_1
       (.I0(ex_branch_with_delayslot_i),
        .I1(ex_branch_with_delayslot_i_reg_0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(ex_branch_with_delayslot_i_reg_1),
        .I4(sync_reset),
        .O(ex_branch_with_delayslot_i_reg));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'h20)) 
    ex_enable_sext_shift_i_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(force2_reg_1),
        .I2(force2_reg),
        .O(ex_enable_sext_shift_i0));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    ex_load_alu_carry_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(force2_reg),
        .I2(force2_reg_1),
        .I3(EX_ALU_Op1142_out__0),
        .O(\Using_FPGA.Native_6 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'h0220)) 
    ex_op1_cmp_eq_n_i_1
       (.I0(\Using_FPGA.Native_2 ),
        .I1(ex_op1_cmp_eq_n_reg),
        .I2(ex_op1_cmp_eq_n_reg_0),
        .I3(ex_op1_cmp_eq_n_reg_1),
        .O(ex_op1_cmp_eq_n5_out));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'h51FF)) 
    ex_sel_alu_i_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_sel_alu_i_reg),
        .I2(\EX_Sext_Op_reg[0] ),
        .I3(force2_reg),
        .O(ex_sel_alu_i0));
  LUT3 #(
    .INIT(8'h02)) 
    force1_i_1
       (.I0(\Using_FPGA.Native_2 ),
        .I1(ex_op1_cmp_eq_n_reg_1),
        .I2(ex_op1_cmp_eq_n_reg),
        .O(force12_out));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'h08000000)) 
    force2_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(force2_reg_2),
        .I2(force2_reg_1),
        .I3(force2_reg_0),
        .I4(force2_reg),
        .O(\Using_FPGA.Native_2 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'h20)) 
    force_Val1_i_1
       (.I0(\Using_FPGA.Native_2 ),
        .I1(ex_op1_cmp_eq_n_reg_1),
        .I2(ex_op1_cmp_eq_n_reg),
        .O(force_Val10_out));
  LUT6 #(
    .INIT(64'hFFF7FF7FFFF7FFFF)) 
    force_Val2_N_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(force2_reg),
        .I2(force2_reg_0),
        .I3(force2_reg_1),
        .I4(force2_reg_2),
        .I5(\EX_Sext_Op_reg[0] ),
        .O(\Using_FPGA.Native_3 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'h0820)) 
    use_Reg_Neg_DI_i_1
       (.I0(\Using_FPGA.Native_2 ),
        .I1(ex_op1_cmp_eq_n_reg_1),
        .I2(ex_op1_cmp_eq_n_reg),
        .I3(ex_op1_cmp_eq_n_reg_0),
        .O(use_Reg_Neg_DI1_out));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h0820)) 
    use_Reg_Neg_S_i_1
       (.I0(\Using_FPGA.Native_2 ),
        .I1(ex_op1_cmp_eq_n_reg),
        .I2(ex_op1_cmp_eq_n_reg_1),
        .I3(ex_op1_cmp_eq_n_reg_0),
        .O(use_Reg_Neg_S3_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_187
   (\Using_FPGA.Native_0 ,
    sync_reset,
    of_instr_ii_2,
    Clk);
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input of_instr_ii_2;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_2;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_2),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_189
   (\Using_FPGA.Native_0 ,
    sync_reset,
    of_instr_ii_1,
    Clk);
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input of_instr_ii_1;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_1;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_1),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_191
   (\Using_FPGA.Native_0 ,
    \mem_gpr_write_addr_reg[4] ,
    \wb_gpr_write_addr_reg[4] ,
    \ex_gpr_write_addr_reg[4] ,
    sync_reset,
    of_instr_ii_0,
    Clk,
    \EX_Op2[0]_i_8 ,
    \EX_Op2[0]_i_8_0 ,
    \EX_Op2[0]_i_8_1 ,
    \EX_Op2[0]_i_7 ,
    \EX_Op2[0]_i_6 ,
    I4,
    I0);
  output \Using_FPGA.Native_0 ;
  output \mem_gpr_write_addr_reg[4] ;
  output \wb_gpr_write_addr_reg[4] ;
  output \ex_gpr_write_addr_reg[4] ;
  input sync_reset;
  input of_instr_ii_0;
  input Clk;
  input [2:0]\EX_Op2[0]_i_8 ;
  input \EX_Op2[0]_i_8_0 ;
  input \EX_Op2[0]_i_8_1 ;
  input [2:0]\EX_Op2[0]_i_7 ;
  input \EX_Op2[0]_i_6 ;
  input I4;
  input I0;

  wire Clk;
  wire \EX_Op2[0]_i_6 ;
  wire [2:0]\EX_Op2[0]_i_7 ;
  wire [2:0]\EX_Op2[0]_i_8 ;
  wire \EX_Op2[0]_i_8_0 ;
  wire \EX_Op2[0]_i_8_1 ;
  wire I0;
  wire I4;
  wire \Using_FPGA.Native_0 ;
  wire \ex_gpr_write_addr_reg[4] ;
  wire \mem_gpr_write_addr_reg[4] ;
  wire of_instr_ii_0;
  wire sync_reset;
  wire \wb_gpr_write_addr_reg[4] ;

  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \EX_Op2[0]_i_10 
       (.I0(\EX_Op2[0]_i_7 [0]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op2[0]_i_8_0 ),
        .I3(\EX_Op2[0]_i_7 [2]),
        .I4(\EX_Op2[0]_i_8_1 ),
        .I5(\EX_Op2[0]_i_7 [1]),
        .O(\wb_gpr_write_addr_reg[4] ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \EX_Op2[0]_i_11 
       (.I0(\EX_Op2[0]_i_8 [0]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op2[0]_i_8_0 ),
        .I3(\EX_Op2[0]_i_8 [2]),
        .I4(\EX_Op2[0]_i_8_1 ),
        .I5(\EX_Op2[0]_i_8 [1]),
        .O(\mem_gpr_write_addr_reg[4] ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \EX_Op2[0]_i_9 
       (.I0(\EX_Op2[0]_i_6 ),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op2[0]_i_8_0 ),
        .I3(I4),
        .I4(\EX_Op2[0]_i_8_1 ),
        .I5(I0),
        .O(\ex_gpr_write_addr_reg[4] ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_0),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_193
   (\Using_FPGA.Native_0 ,
    of_Sel_SPR_MSR1,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    ex_load_shift_carry0,
    p_0_in30_in,
    \Using_FPGA.Native_3 ,
    D224_out,
    \Using_FPGA.Native_4 ,
    \Using_FPGA.Native_5 ,
    p_9_in,
    \Using_FPGA.Native_6 ,
    \Using_FPGA.Native_7 ,
    \Using_FPGA.Native_8 ,
    \Using_FPGA.Native_9 ,
    \Using_FPGA.Native_10 ,
    \Using_FPGA.Native_11 ,
    \Using_FPGA.Native_12 ,
    \Using_FPGA.Native_13 ,
    \Using_FPGA.Native_14 ,
    \Using_FPGA.Native_15 ,
    \Using_FPGA.Native_16 ,
    \Using_FPGA.Native_17 ,
    \Using_FPGA.Native_18 ,
    \Using_FPGA.Native_19 ,
    \Using_FPGA.Native_20 ,
    \Using_FPGA.Native_21 ,
    \Using_FPGA.Native_22 ,
    \Using_FPGA.Native_23 ,
    \Using_FPGA.Native_24 ,
    \Using_FPGA.Native_25 ,
    \Using_FPGA.Native_26 ,
    \Using_FPGA.Native_27 ,
    \Using_FPGA.Native_28 ,
    \Using_FPGA.Native_29 ,
    \Using_FPGA.Native_30 ,
    \Using_FPGA.Native_31 ,
    \Using_FPGA.Native_32 ,
    \Using_FPGA.Native_33 ,
    \Using_FPGA.Native_34 ,
    \Using_FPGA.Native_35 ,
    \Using_FPGA.Native_36 ,
    I1_0,
    of_Sel_SPR_MSR88_out,
    ex_is_multi_or_load_instr0,
    of_op1_sel_spr,
    sync_reset,
    of_instr_ii_38,
    Clk,
    ex_is_multi_instr2_reg,
    \Using_FPGA.Native_37 ,
    EX_SWAP_Instr_reg,
    EX_SWAP_Instr_reg_0,
    EX_SWAP_Instr_reg_1,
    EX_SWAP_Instr_reg_2,
    ex_is_multi_or_load_instr_reg,
    ex_is_multi_or_load_instr_reg_0,
    \Using_FPGA.Native_38 ,
    \Using_FPGA.Native_39 ,
    \Using_FPGA.Native_40 ,
    \EX_Sext_Op_reg[1] ,
    ex_load_shift_carry_reg,
    ex_is_multi_or_load_instr_reg_1,
    OF_Op1_Sel_SPR_PC0__0,
    \EX_Op1_reg[0] ,
    ex_MSR,
    ex_mfsmsr_i_reg,
    ex_mfsmsr_i_reg_0,
    ex_mfsmsr_i_reg_1);
  output \Using_FPGA.Native_0 ;
  output of_Sel_SPR_MSR1;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  output ex_load_shift_carry0;
  output p_0_in30_in;
  output \Using_FPGA.Native_3 ;
  output D224_out;
  output [0:0]\Using_FPGA.Native_4 ;
  output \Using_FPGA.Native_5 ;
  output p_9_in;
  output \Using_FPGA.Native_6 ;
  output \Using_FPGA.Native_7 ;
  output \Using_FPGA.Native_8 ;
  output \Using_FPGA.Native_9 ;
  output \Using_FPGA.Native_10 ;
  output \Using_FPGA.Native_11 ;
  output \Using_FPGA.Native_12 ;
  output \Using_FPGA.Native_13 ;
  output \Using_FPGA.Native_14 ;
  output \Using_FPGA.Native_15 ;
  output \Using_FPGA.Native_16 ;
  output \Using_FPGA.Native_17 ;
  output \Using_FPGA.Native_18 ;
  output \Using_FPGA.Native_19 ;
  output \Using_FPGA.Native_20 ;
  output \Using_FPGA.Native_21 ;
  output \Using_FPGA.Native_22 ;
  output \Using_FPGA.Native_23 ;
  output \Using_FPGA.Native_24 ;
  output \Using_FPGA.Native_25 ;
  output \Using_FPGA.Native_26 ;
  output \Using_FPGA.Native_27 ;
  output \Using_FPGA.Native_28 ;
  output \Using_FPGA.Native_29 ;
  output \Using_FPGA.Native_30 ;
  output \Using_FPGA.Native_31 ;
  output \Using_FPGA.Native_32 ;
  output \Using_FPGA.Native_33 ;
  output \Using_FPGA.Native_34 ;
  output \Using_FPGA.Native_35 ;
  output \Using_FPGA.Native_36 ;
  output I1_0;
  output of_Sel_SPR_MSR88_out;
  output ex_is_multi_or_load_instr0;
  output of_op1_sel_spr;
  input sync_reset;
  input of_instr_ii_38;
  input Clk;
  input ex_is_multi_instr2_reg;
  input \Using_FPGA.Native_37 ;
  input EX_SWAP_Instr_reg;
  input EX_SWAP_Instr_reg_0;
  input EX_SWAP_Instr_reg_1;
  input EX_SWAP_Instr_reg_2;
  input ex_is_multi_or_load_instr_reg;
  input ex_is_multi_or_load_instr_reg_0;
  input \Using_FPGA.Native_38 ;
  input \Using_FPGA.Native_39 ;
  input \Using_FPGA.Native_40 ;
  input \EX_Sext_Op_reg[1] ;
  input ex_load_shift_carry_reg;
  input ex_is_multi_or_load_instr_reg_1;
  input OF_Op1_Sel_SPR_PC0__0;
  input [31:0]\EX_Op1_reg[0] ;
  input [2:0]ex_MSR;
  input ex_mfsmsr_i_reg;
  input ex_mfsmsr_i_reg_0;
  input ex_mfsmsr_i_reg_1;

  wire Clk;
  wire D224_out;
  wire [31:0]\EX_Op1_reg[0] ;
  wire EX_SWAP_Instr_reg;
  wire EX_SWAP_Instr_reg_0;
  wire EX_SWAP_Instr_reg_1;
  wire EX_SWAP_Instr_reg_2;
  wire \EX_Sext_Op_reg[1] ;
  wire I1_0;
  wire OF_Op1_Sel_SPR_PC0__0;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_10 ;
  wire \Using_FPGA.Native_11 ;
  wire \Using_FPGA.Native_12 ;
  wire \Using_FPGA.Native_13 ;
  wire \Using_FPGA.Native_14 ;
  wire \Using_FPGA.Native_15 ;
  wire \Using_FPGA.Native_16 ;
  wire \Using_FPGA.Native_17 ;
  wire \Using_FPGA.Native_18 ;
  wire \Using_FPGA.Native_19 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_20 ;
  wire \Using_FPGA.Native_21 ;
  wire \Using_FPGA.Native_22 ;
  wire \Using_FPGA.Native_23 ;
  wire \Using_FPGA.Native_24 ;
  wire \Using_FPGA.Native_25 ;
  wire \Using_FPGA.Native_26 ;
  wire \Using_FPGA.Native_27 ;
  wire \Using_FPGA.Native_28 ;
  wire \Using_FPGA.Native_29 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_30 ;
  wire \Using_FPGA.Native_31 ;
  wire \Using_FPGA.Native_32 ;
  wire \Using_FPGA.Native_33 ;
  wire \Using_FPGA.Native_34 ;
  wire \Using_FPGA.Native_35 ;
  wire \Using_FPGA.Native_36 ;
  wire \Using_FPGA.Native_37 ;
  wire \Using_FPGA.Native_38 ;
  wire \Using_FPGA.Native_39 ;
  wire [0:0]\Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_40 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_7 ;
  wire \Using_FPGA.Native_8 ;
  wire \Using_FPGA.Native_9 ;
  wire [2:0]ex_MSR;
  wire ex_is_multi_instr2_reg;
  wire ex_is_multi_or_load_instr0;
  wire ex_is_multi_or_load_instr_reg;
  wire ex_is_multi_or_load_instr_reg_0;
  wire ex_is_multi_or_load_instr_reg_1;
  wire ex_load_shift_carry0;
  wire ex_load_shift_carry_reg;
  wire ex_mfsmsr_i_reg;
  wire ex_mfsmsr_i_reg_0;
  wire ex_mfsmsr_i_reg_1;
  wire of_Sel_SPR_MSR1;
  wire of_Sel_SPR_MSR88_out;
  wire of_instr_ii_38;
  wire of_op1_sel_spr;
  wire p_0_in30_in;
  wire p_9_in;
  wire sync_reset;

  LUT6 #(
    .INIT(64'h0000000000400000)) 
    Dbg_Clean_Stop_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_load_shift_carry_reg),
        .I2(ex_is_multi_or_load_instr_reg_0),
        .I3(\Using_FPGA.Native_37 ),
        .I4(ex_is_multi_or_load_instr_reg_1),
        .I5(ex_is_multi_or_load_instr_reg),
        .O(p_9_in));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    EX_SWAP_Instr_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_37 ),
        .I2(EX_SWAP_Instr_reg),
        .I3(EX_SWAP_Instr_reg_0),
        .I4(EX_SWAP_Instr_reg_1),
        .I5(EX_SWAP_Instr_reg_2),
        .O(\Using_FPGA.Native_2 ));
  LUT6 #(
    .INIT(64'h0000000010111111)) 
    \EX_Sext_Op[1]_i_1 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_37 ),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(EX_SWAP_Instr_reg_0),
        .I4(EX_SWAP_Instr_reg_1),
        .I5(EX_SWAP_Instr_reg_2),
        .O(\Using_FPGA.Native_4 ));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_38),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'hF2)) 
    \Using_FPGA.Native_i_1__179 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(OF_Op1_Sel_SPR_PC0__0),
        .O(of_op1_sel_spr));
  LUT5 #(
    .INIT(32'h00080000)) 
    \Using_FPGA.Native_i_1__42 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_is_multi_or_load_instr_reg),
        .I2(ex_is_multi_or_load_instr_reg_0),
        .I3(\Using_FPGA.Native_38 ),
        .I4(\Using_FPGA.Native_39 ),
        .O(\Using_FPGA.Native_3 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \Using_FPGA.Native_i_1__43 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_40 ),
        .I2(ex_is_multi_or_load_instr_reg),
        .I3(\Using_FPGA.Native_39 ),
        .O(D224_out));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \Using_FPGA.Native_i_1__47 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_37 ),
        .O(\Using_FPGA.Native_5 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__118 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [0]),
        .O(\Using_FPGA.Native_6 ));
  LUT6 #(
    .INIT(64'hFFFF00FDFF020000)) 
    \Using_FPGA.Native_i_2__119 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [1]),
        .I5(ex_MSR[0]),
        .O(\Using_FPGA.Native_7 ));
  LUT6 #(
    .INIT(64'hFFFF00FDFF020000)) 
    \Using_FPGA.Native_i_2__120 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [2]),
        .I5(ex_MSR[1]),
        .O(\Using_FPGA.Native_8 ));
  LUT6 #(
    .INIT(64'hFFFF00FDFF020000)) 
    \Using_FPGA.Native_i_2__121 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [3]),
        .I5(ex_MSR[2]),
        .O(\Using_FPGA.Native_9 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__122 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [4]),
        .O(\Using_FPGA.Native_10 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__123 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [5]),
        .O(\Using_FPGA.Native_11 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__124 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [6]),
        .O(\Using_FPGA.Native_12 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__125 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [7]),
        .O(\Using_FPGA.Native_13 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__126 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [8]),
        .O(\Using_FPGA.Native_14 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__127 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [9]),
        .O(\Using_FPGA.Native_15 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__128 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [10]),
        .O(\Using_FPGA.Native_16 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__129 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [11]),
        .O(\Using_FPGA.Native_17 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__130 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [12]),
        .O(\Using_FPGA.Native_18 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__131 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [13]),
        .O(\Using_FPGA.Native_19 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__132 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [14]),
        .O(\Using_FPGA.Native_20 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__133 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [15]),
        .O(\Using_FPGA.Native_21 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__134 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [16]),
        .O(\Using_FPGA.Native_22 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__135 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [17]),
        .O(\Using_FPGA.Native_23 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__136 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [18]),
        .O(\Using_FPGA.Native_24 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__137 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [19]),
        .O(\Using_FPGA.Native_25 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__138 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [20]),
        .O(\Using_FPGA.Native_26 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__139 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [21]),
        .O(\Using_FPGA.Native_27 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__140 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [22]),
        .O(\Using_FPGA.Native_28 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__141 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [23]),
        .O(\Using_FPGA.Native_29 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__142 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [24]),
        .O(\Using_FPGA.Native_30 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__143 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [25]),
        .O(\Using_FPGA.Native_31 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__144 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [26]),
        .O(\Using_FPGA.Native_32 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__145 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [27]),
        .O(\Using_FPGA.Native_33 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__146 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [28]),
        .O(\Using_FPGA.Native_34 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__147 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [29]),
        .O(\Using_FPGA.Native_35 ));
  LUT5 #(
    .INIT(32'hFF020000)) 
    \Using_FPGA.Native_i_2__148 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [30]),
        .O(\Using_FPGA.Native_36 ));
  LUT6 #(
    .INIT(64'hFFFF00FDFF020000)) 
    \Using_FPGA.Native_i_3__32 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(\EX_Sext_Op_reg[1] ),
        .I3(OF_Op1_Sel_SPR_PC0__0),
        .I4(\EX_Op1_reg[0] [31]),
        .I5(ex_MSR[1]),
        .O(I1_0));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h2)) 
    ex_is_multi_instr2_i_1
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .O(of_Sel_SPR_MSR1));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'h2F22FF22)) 
    ex_is_multi_or_load_instr_i_1
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(ex_is_multi_or_load_instr_reg_1),
        .I3(ex_is_multi_or_load_instr_reg),
        .I4(ex_is_multi_or_load_instr_reg_0),
        .O(ex_is_multi_or_load_instr0));
  LUT3 #(
    .INIT(8'h2A)) 
    ex_load_shift_carry_i_1
       (.I0(p_0_in30_in),
        .I1(EX_SWAP_Instr_reg_0),
        .I2(EX_SWAP_Instr_reg_1),
        .O(ex_load_shift_carry0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    ex_load_shift_carry_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_is_multi_or_load_instr_reg_0),
        .I2(ex_is_multi_or_load_instr_reg_1),
        .I3(\Using_FPGA.Native_37 ),
        .I4(ex_load_shift_carry_reg),
        .I5(ex_is_multi_or_load_instr_reg),
        .O(p_0_in30_in));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    ex_mfsmsr_i_i_1
       (.I0(\Using_FPGA.Native_1 ),
        .I1(ex_is_multi_instr2_reg),
        .I2(ex_mfsmsr_i_reg),
        .I3(ex_mfsmsr_i_reg_0),
        .I4(ex_mfsmsr_i_reg_1),
        .I5(\EX_Sext_Op_reg[1] ),
        .O(of_Sel_SPR_MSR88_out));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    ex_move_to_MSR_instr_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_load_shift_carry_reg),
        .I2(ex_is_multi_or_load_instr_reg_0),
        .I3(\Using_FPGA.Native_37 ),
        .I4(ex_is_multi_or_load_instr_reg_1),
        .I5(ex_is_multi_or_load_instr_reg),
        .O(\Using_FPGA.Native_1 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_195
   (\Using_FPGA.Native_0 ,
    ex_is_div_instr_I_reg,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_37,
    Clk,
    EX_Is_Div_Instr,
    E,
    ex_is_div_instr_I_reg_0,
    ex_is_div_instr_I_reg_1,
    \Using_FPGA.Native_2 ,
    ex_is_div_instr_I_reg_2,
    ex_is_div_instr_I_reg_3);
  output \Using_FPGA.Native_0 ;
  output ex_is_div_instr_I_reg;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_37;
  input Clk;
  input EX_Is_Div_Instr;
  input [0:0]E;
  input ex_is_div_instr_I_reg_0;
  input ex_is_div_instr_I_reg_1;
  input \Using_FPGA.Native_2 ;
  input ex_is_div_instr_I_reg_2;
  input ex_is_div_instr_I_reg_3;

  wire Clk;
  wire [0:0]E;
  wire EX_Is_Div_Instr;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire ex_is_div_instr_I0;
  wire ex_is_div_instr_I_reg;
  wire ex_is_div_instr_I_reg_0;
  wire ex_is_div_instr_I_reg_1;
  wire ex_is_div_instr_I_reg_2;
  wire ex_is_div_instr_I_reg_3;
  wire of_instr_ii_37;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_37),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Using_FPGA.Native_i_1__48 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_2 ),
        .O(\Using_FPGA.Native_1 ));
  LUT5 #(
    .INIT(32'h0000CC0A)) 
    ex_is_div_instr_I_i_1
       (.I0(EX_Is_Div_Instr),
        .I1(ex_is_div_instr_I0),
        .I2(E),
        .I3(ex_is_div_instr_I_reg_0),
        .I4(sync_reset),
        .O(ex_is_div_instr_I_reg));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'h00100000)) 
    ex_is_div_instr_I_i_2
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_is_div_instr_I_reg_1),
        .I2(\Using_FPGA.Native_2 ),
        .I3(ex_is_div_instr_I_reg_2),
        .I4(ex_is_div_instr_I_reg_3),
        .O(ex_is_div_instr_I0));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_197
   (\Using_FPGA.Native_0 ,
    of_read_mem_write_op3_conflict__1,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    sync_reset,
    of_instr_ii_36,
    Clk,
    \EX_Op3[0]_i_3 ,
    \EX_Op3[0]_i_3_0 ,
    \EX_Op3[0]_i_3_1 ,
    \EX_Op3[0]_i_3_2 ,
    \EX_Op3[0]_i_5 ,
    \EX_Op3[0]_i_6 );
  output \Using_FPGA.Native_0 ;
  output of_read_mem_write_op3_conflict__1;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  input sync_reset;
  input of_instr_ii_36;
  input Clk;
  input [1:0]\EX_Op3[0]_i_3 ;
  input \EX_Op3[0]_i_3_0 ;
  input \EX_Op3[0]_i_3_1 ;
  input \EX_Op3[0]_i_3_2 ;
  input [0:0]\EX_Op3[0]_i_5 ;
  input [0:0]\EX_Op3[0]_i_6 ;

  wire Clk;
  wire [1:0]\EX_Op3[0]_i_3 ;
  wire \EX_Op3[0]_i_3_0 ;
  wire \EX_Op3[0]_i_3_1 ;
  wire \EX_Op3[0]_i_3_2 ;
  wire [0:0]\EX_Op3[0]_i_5 ;
  wire [0:0]\EX_Op3[0]_i_6 ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire of_instr_ii_36;
  wire of_read_mem_write_op3_conflict__1;
  wire sync_reset;

  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \EX_Op3[0]_i_10 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\EX_Op3[0]_i_5 ),
        .O(\Using_FPGA.Native_1 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \EX_Op3[0]_i_12 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\EX_Op3[0]_i_6 ),
        .O(\Using_FPGA.Native_2 ));
  LUT6 #(
    .INIT(64'h9000009000000000)) 
    \EX_Op3[0]_i_4 
       (.I0(\EX_Op3[0]_i_3 [1]),
        .I1(\Using_FPGA.Native_0 ),
        .I2(\EX_Op3[0]_i_3_0 ),
        .I3(\EX_Op3[0]_i_3_1 ),
        .I4(\EX_Op3[0]_i_3 [0]),
        .I5(\EX_Op3[0]_i_3_2 ),
        .O(of_read_mem_write_op3_conflict__1));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_36),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_199
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    of_instr_ii_35,
    Clk,
    ex_mbar_is_sleep_reg,
    ex_mbar_is_sleep_reg_0,
    ex_mbar_is_sleep);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  input sync_reset;
  input of_instr_ii_35;
  input Clk;
  input ex_mbar_is_sleep_reg;
  input ex_mbar_is_sleep_reg_0;
  input ex_mbar_is_sleep;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_mbar_is_sleep;
  wire ex_mbar_is_sleep_reg;
  wire ex_mbar_is_sleep_reg_0;
  wire of_instr_ii_35;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_35),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hEFE0)) 
    ex_mbar_is_sleep_cmb_inferred_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_mbar_is_sleep_reg),
        .I2(ex_mbar_is_sleep_reg_0),
        .I3(ex_mbar_is_sleep),
        .O(\Using_FPGA.Native_1 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_201
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    ex_gpr_write111_out__0,
    sync_reset,
    of_instr_ii_34,
    Clk,
    ex_op1_cmp_eq_reg,
    ex_op1_cmp_eq_reg_0,
    ex_op1_cmp_eq1,
    ex_gpr_write_reg,
    ex_gpr_write_reg_0,
    ex_gpr_write_reg_1);
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output ex_gpr_write111_out__0;
  input sync_reset;
  input of_instr_ii_34;
  input Clk;
  input ex_op1_cmp_eq_reg;
  input ex_op1_cmp_eq_reg_0;
  input ex_op1_cmp_eq1;
  input ex_gpr_write_reg;
  input ex_gpr_write_reg_0;
  input ex_gpr_write_reg_1;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_gpr_write111_out__0;
  wire ex_gpr_write_reg;
  wire ex_gpr_write_reg_0;
  wire ex_gpr_write_reg_1;
  wire ex_op1_cmp_eq1;
  wire ex_op1_cmp_eq_reg;
  wire ex_op1_cmp_eq_reg_0;
  wire of_instr_ii_34;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_34),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    ex_gpr_write_i_3
       (.I0(ex_gpr_write_reg),
        .I1(\Using_FPGA.Native_0 ),
        .I2(ex_op1_cmp_eq_reg_0),
        .I3(ex_op1_cmp_eq_reg),
        .I4(ex_gpr_write_reg_0),
        .I5(ex_gpr_write_reg_1),
        .O(ex_gpr_write111_out__0));
  LUT4 #(
    .INIT(16'hF9FF)) 
    ex_op1_cmp_eq_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_op1_cmp_eq_reg),
        .I2(ex_op1_cmp_eq_reg_0),
        .I3(ex_op1_cmp_eq1),
        .O(\Using_FPGA.Native_1 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_203
   (\Using_FPGA.Native_0 ,
    sync_reset,
    of_instr_ii_33,
    Clk);
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input of_instr_ii_33;
  input Clk;

  wire Clk;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_33;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_instr_ii_33),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_205
   (\Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    ex_branch_with_delayslot_reg,
    \Using_FPGA.Native_2 ,
    Dbg_Clean_Stop0,
    sync_reset,
    of_Valid_II,
    Clk,
    p_9_in,
    ex_branch_with_delayslot,
    ex_jump_q,
    wb_exception,
    Q,
    ex_jump_nodelay,
    ex_jump,
    Dbg_Clean_Stop_reg);
  output \Using_FPGA.Native_0 ;
  output [0:0]\Using_FPGA.Native_1 ;
  output ex_branch_with_delayslot_reg;
  output \Using_FPGA.Native_2 ;
  output Dbg_Clean_Stop0;
  input sync_reset;
  input of_Valid_II;
  input Clk;
  input p_9_in;
  input ex_branch_with_delayslot;
  input ex_jump_q;
  input wb_exception;
  input [1:0]Q;
  input ex_jump_nodelay;
  input ex_jump;
  input Dbg_Clean_Stop_reg;

  wire Clk;
  wire Dbg_Clean_Stop0;
  wire Dbg_Clean_Stop_reg;
  wire [1:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire ex_branch_with_delayslot;
  wire ex_branch_with_delayslot_reg;
  wire ex_jump;
  wire ex_jump_nodelay;
  wire ex_jump_q;
  wire of_Valid_II;
  wire p_9_in;
  wire sync_reset;
  wire wb_exception;

  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'hF000F777)) 
    Dbg_Clean_Stop_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(p_9_in),
        .I2(ex_jump_nodelay),
        .I3(ex_jump),
        .I4(Dbg_Clean_Stop_reg),
        .O(Dbg_Clean_Stop0));
  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_Valid_II),
        .Q(\Using_FPGA.Native_0 ),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'h2AAA)) 
    \Using_FPGA.Native_i_1__101 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(wb_exception),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\Using_FPGA.Native_2 ));
  LUT3 #(
    .INIT(8'h0D)) 
    \Using_FPGA.Native_i_1__99 
       (.I0(ex_branch_with_delayslot),
        .I1(\Using_FPGA.Native_0 ),
        .I2(ex_jump_q),
        .O(ex_branch_with_delayslot_reg));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \imm_reg[0]_i_1 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(p_9_in),
        .O(\Using_FPGA.Native_1 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_206
   (D,
    I0125_out,
    sync_reset,
    of_pc_ii_31,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0125_out;
  input sync_reset;
  input of_pc_ii_31;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0125_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_31;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_31),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__127 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0125_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_208
   (D,
    I085_out,
    sync_reset,
    of_pc_ii_21,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I085_out;
  input sync_reset;
  input of_pc_ii_21;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I085_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_21;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_21),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__137 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I085_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_210
   (D,
    I081_out,
    sync_reset,
    of_pc_ii_20,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I081_out;
  input sync_reset;
  input of_pc_ii_20;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I081_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_20;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_20),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__138 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I081_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_212
   (D,
    I077_out,
    sync_reset,
    of_pc_ii_19,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I077_out;
  input sync_reset;
  input of_pc_ii_19;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I077_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_19;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_19),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__139 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I077_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_214
   (D,
    I073_out,
    sync_reset,
    of_pc_ii_18,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I073_out;
  input sync_reset;
  input of_pc_ii_18;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I073_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_18;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_18),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__140 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I073_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_216
   (D,
    I069_out,
    sync_reset,
    of_pc_ii_17,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I069_out;
  input sync_reset;
  input of_pc_ii_17;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I069_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_17;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_17),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__141 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I069_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_218
   (D,
    I065_out,
    sync_reset,
    of_pc_ii_16,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I065_out;
  input sync_reset;
  input of_pc_ii_16;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I065_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_16;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_16),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__142 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I065_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_220
   (D,
    I061_out,
    sync_reset,
    of_pc_ii_15,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I061_out;
  input sync_reset;
  input of_pc_ii_15;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I061_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_15;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_15),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__143 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I061_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_222
   (D,
    I057_out,
    sync_reset,
    of_pc_ii_14,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I057_out;
  input sync_reset;
  input of_pc_ii_14;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I057_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_14;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_14),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__144 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I057_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_224
   (D,
    I053_out,
    sync_reset,
    of_pc_ii_13,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I053_out;
  input sync_reset;
  input of_pc_ii_13;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I053_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_13;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_13),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__145 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I053_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_226
   (D,
    I049_out,
    sync_reset,
    of_pc_ii_12,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I049_out;
  input sync_reset;
  input of_pc_ii_12;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I049_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_12;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_12),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__146 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I049_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_228
   (D,
    I0121_out,
    sync_reset,
    of_pc_ii_30,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0121_out;
  input sync_reset;
  input of_pc_ii_30;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0121_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_30;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_30),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__128 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0121_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_230
   (D,
    I045_out,
    sync_reset,
    of_pc_ii_11,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I045_out;
  input sync_reset;
  input of_pc_ii_11;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I045_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_11;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_11),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__147 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I045_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_232
   (D,
    I041_out,
    sync_reset,
    of_pc_ii_10,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I041_out;
  input sync_reset;
  input of_pc_ii_10;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I041_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_10;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_10),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__148 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I041_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_234
   (D,
    I037_out,
    sync_reset,
    of_pc_ii_9,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I037_out;
  input sync_reset;
  input of_pc_ii_9;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I037_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_9;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_9),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__149 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I037_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_236
   (D,
    I033_out,
    sync_reset,
    of_pc_ii_8,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I033_out;
  input sync_reset;
  input of_pc_ii_8;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I033_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_8;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_8),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__150 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I033_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_238
   (D,
    I029_out,
    sync_reset,
    of_pc_ii_7,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I029_out;
  input sync_reset;
  input of_pc_ii_7;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I029_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_7;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_7),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__151 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I029_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_240
   (D,
    I025_out,
    sync_reset,
    of_pc_ii_6,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I025_out;
  input sync_reset;
  input of_pc_ii_6;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I025_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_6;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_6),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__152 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I025_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_242
   (D,
    I021_out,
    sync_reset,
    of_pc_ii_5,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I021_out;
  input sync_reset;
  input of_pc_ii_5;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I021_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_5;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_5),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__153 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I021_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_244
   (D,
    I017_out,
    sync_reset,
    of_pc_ii_4,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I017_out;
  input sync_reset;
  input of_pc_ii_4;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I017_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_4;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_4),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__154 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I017_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_246
   (D,
    I013_out,
    sync_reset,
    of_pc_ii_3,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I013_out;
  input sync_reset;
  input of_pc_ii_3;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I013_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_3;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_3),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__155 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I013_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_248
   (D,
    I09_out,
    sync_reset,
    of_pc_ii_2,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I09_out;
  input sync_reset;
  input of_pc_ii_2;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I09_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_2;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_2),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__156 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I09_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_250
   (D,
    I0117_out,
    sync_reset,
    of_pc_ii_29,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0117_out;
  input sync_reset;
  input of_pc_ii_29;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0117_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_29;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_29),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__129 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0117_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_252
   (D,
    I05_out,
    sync_reset,
    of_pc_ii_1,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I05_out;
  input sync_reset;
  input of_pc_ii_1;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I05_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_1;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_1),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__157 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I05_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_254
   (D,
    I0,
    sync_reset,
    of_pc_ii_0,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0;
  input sync_reset;
  input of_pc_ii_0;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_0;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_0),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__158 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_256
   (D,
    I0113_out,
    sync_reset,
    of_pc_ii_28,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0113_out;
  input sync_reset;
  input of_pc_ii_28;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0113_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_28;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_28),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__130 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0113_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_258
   (D,
    I0109_out,
    sync_reset,
    of_pc_ii_27,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0109_out;
  input sync_reset;
  input of_pc_ii_27;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0109_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_27;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_27),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__131 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0109_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_260
   (D,
    I0105_out,
    sync_reset,
    of_pc_ii_26,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0105_out;
  input sync_reset;
  input of_pc_ii_26;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0105_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_26;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_26),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__132 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0105_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_262
   (D,
    I0101_out,
    sync_reset,
    of_pc_ii_25,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I0101_out;
  input sync_reset;
  input of_pc_ii_25;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I0101_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_25;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_25),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__133 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I0101_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_264
   (D,
    I097_out,
    sync_reset,
    of_pc_ii_24,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I097_out;
  input sync_reset;
  input of_pc_ii_24;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I097_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_24;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_24),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__134 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I097_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_266
   (D,
    I093_out,
    sync_reset,
    of_pc_ii_23,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I093_out;
  input sync_reset;
  input of_pc_ii_23;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I093_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_23;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_23),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__135 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I093_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_268
   (D,
    I089_out,
    sync_reset,
    of_pc_ii_22,
    Clk,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    Q);
  output [0:0]D;
  output I089_out;
  input sync_reset;
  input of_pc_ii_22;
  input Clk;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input [0:0]Q;

  wire Clk;
  wire [0:0]D;
  wire I089_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]if_sel_input;
  wire of_pc_ii_22;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(of_pc_ii_22),
        .Q(D),
        .R(sync_reset));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__136 
       (.I0(if_sel_input),
        .I1(\Using_FPGA.Native_0 ),
        .I2(D),
        .I3(Q),
        .O(I089_out));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_301
   (D,
    MEM_Fwd,
    sync_reset,
    \Using_FPGA.Native_0 ,
    Clk,
    mem_sel_msr,
    \WB_MEM_Result_reg[28] );
  output [0:0]D;
  output [0:0]MEM_Fwd;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input Clk;
  input mem_sel_msr;
  input [0:0]\WB_MEM_Result_reg[28] ;

  wire Clk;
  wire [0:0]D;
  wire [0:0]MEM_Fwd;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\WB_MEM_Result_reg[28] ;
  wire mem_sel_msr;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_0 ),
        .Q(D),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'hB8)) 
    \WB_MEM_Result[28]_i_1 
       (.I0(D),
        .I1(mem_sel_msr),
        .I2(\WB_MEM_Result_reg[28] ),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_302
   (mem_MSR,
    MEM_Fwd,
    sync_reset,
    \Using_FPGA.Native_0 ,
    Clk,
    mem_sel_msr,
    \WB_MEM_Result_reg[0] );
  output [0:0]mem_MSR;
  output [1:0]MEM_Fwd;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input Clk;
  input mem_sel_msr;
  input [1:0]\WB_MEM_Result_reg[0] ;

  wire Clk;
  wire [1:0]MEM_Fwd;
  wire \Using_FPGA.Native_0 ;
  wire [1:0]\WB_MEM_Result_reg[0] ;
  wire [0:0]mem_MSR;
  wire mem_sel_msr;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_0 ),
        .Q(mem_MSR),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \WB_MEM_Result[0]_i_2 
       (.I0(mem_MSR),
        .I1(mem_sel_msr),
        .I2(\WB_MEM_Result_reg[0] [1]),
        .O(MEM_Fwd[1]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \WB_MEM_Result[29]_i_1 
       (.I0(mem_MSR),
        .I1(mem_sel_msr),
        .I2(\WB_MEM_Result_reg[0] [0]),
        .O(MEM_Fwd[0]));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_303
   (D,
    MEM_Fwd,
    sync_reset,
    \Using_FPGA.Native_0 ,
    Clk,
    mem_sel_msr,
    \WB_MEM_Result_reg[30] );
  output [0:0]D;
  output [0:0]MEM_Fwd;
  input sync_reset;
  input \Using_FPGA.Native_0 ;
  input Clk;
  input mem_sel_msr;
  input [0:0]\WB_MEM_Result_reg[30] ;

  wire Clk;
  wire [0:0]D;
  wire [0:0]MEM_Fwd;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\WB_MEM_Result_reg[30] ;
  wire mem_sel_msr;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_0 ),
        .Q(D),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'hB8)) 
    \WB_MEM_Result[30]_i_1 
       (.I0(D),
        .I1(mem_sel_msr),
        .I2(\WB_MEM_Result_reg[30] ),
        .O(MEM_Fwd));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_304
   (ex_MSR,
    \Using_FPGA.Native_0 ,
    sync_reset,
    \Using_FPGA.Native_1 ,
    Clk,
    \Using_FPGA.Native_2 ,
    D);
  output [0:0]ex_MSR;
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input \Using_FPGA.Native_1 ;
  input Clk;
  input \Using_FPGA.Native_2 ;
  input [0:0]D;

  wire Clk;
  wire [0:0]D;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire [0:0]ex_MSR;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_MSR),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_1__93 
       (.I0(ex_MSR),
        .I1(\Using_FPGA.Native_2 ),
        .I2(D),
        .O(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_305
   (ex_MSR,
    \Using_FPGA.Native_0 ,
    sync_reset,
    \Using_FPGA.Native_1 ,
    Clk,
    \Using_FPGA.Native_2 ,
    D);
  output [0:0]ex_MSR;
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input \Using_FPGA.Native_1 ;
  input Clk;
  input \Using_FPGA.Native_2 ;
  input [0:0]D;

  wire Clk;
  wire [0:0]D;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire [0:0]ex_MSR;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_MSR),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_1__92 
       (.I0(ex_MSR),
        .I1(\Using_FPGA.Native_2 ),
        .I2(D),
        .O(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_FDR" *) 
module design_1_microblaze_0_0_MB_FDR_306
   (ex_MSR,
    \Using_FPGA.Native_0 ,
    sync_reset,
    \Using_FPGA.Native_1 ,
    Clk,
    \Using_FPGA.Native_2 ,
    D);
  output [0:0]ex_MSR;
  output \Using_FPGA.Native_0 ;
  input sync_reset;
  input \Using_FPGA.Native_1 ;
  input Clk;
  input \Using_FPGA.Native_2 ;
  input [0:0]D;

  wire Clk;
  wire [0:0]D;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire [0:0]ex_MSR;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDR" *) 
  (* box_type = "PRIMITIVE" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(\Using_FPGA.Native_1 ),
        .Q(ex_MSR),
        .R(sync_reset));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_1__91 
       (.I0(ex_MSR),
        .I1(\Using_FPGA.Native_2 ),
        .I2(D),
        .O(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_FDS" *) 
module design_1_microblaze_0_0_MB_FDS
   (\Using_FPGA.Native_0 ,
    I041_out,
    I045_out,
    I049_out,
    I053_out,
    I057_out,
    I061_out,
    I065_out,
    I069_out,
    I073_out,
    I077_out,
    I081_out,
    I085_out,
    I0129_out,
    I0133_out,
    I0137_out,
    I0141_out,
    I0145_out,
    I0149_out,
    I0153_out,
    I0157_out,
    I0161_out,
    I0165_out,
    I0169_out,
    I0125_out,
    I0121_out,
    I0117_out,
    I0113_out,
    I0109_out,
    I0105_out,
    I0101_out,
    I097_out,
    I093_out,
    I089_out,
    I037_out,
    I033_out,
    I029_out,
    I025_out,
    I021_out,
    I017_out,
    I013_out,
    I09_out,
    I05_out,
    I0_1,
    sync_reset,
    sel_input_i_0,
    Clk,
    \Using_FPGA.Native_1 ,
    of_predecode,
    in,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    \Using_FPGA.Native_5 ,
    \Using_FPGA.Native_6 ,
    \Using_FPGA.Native_7 ,
    \Using_FPGA.Native_8 ,
    \Using_FPGA.Native_9 ,
    \Using_FPGA.Native_10 ,
    \Using_FPGA.Native_11 ,
    \Using_FPGA.Native_12 ,
    \Using_FPGA.Native_13 ,
    \Using_FPGA.Native_14 ,
    \Using_FPGA.Native_15 ,
    \Using_FPGA.Native_16 ,
    \Using_FPGA.Native_17 );
  output \Using_FPGA.Native_0 ;
  output I041_out;
  output I045_out;
  output I049_out;
  output I053_out;
  output I057_out;
  output I061_out;
  output I065_out;
  output I069_out;
  output I073_out;
  output I077_out;
  output I081_out;
  output I085_out;
  output I0129_out;
  output I0133_out;
  output I0137_out;
  output I0141_out;
  output I0145_out;
  output I0149_out;
  output I0153_out;
  output I0157_out;
  output I0161_out;
  output I0165_out;
  output I0169_out;
  output I0125_out;
  output I0121_out;
  output I0117_out;
  output I0113_out;
  output I0109_out;
  output I0105_out;
  output I0101_out;
  output I097_out;
  output I093_out;
  output I089_out;
  output I037_out;
  output I033_out;
  output I029_out;
  output I025_out;
  output I021_out;
  output I017_out;
  output I013_out;
  output I09_out;
  output I05_out;
  output I0_1;
  input sync_reset;
  input sel_input_i_0;
  input Clk;
  input \Using_FPGA.Native_1 ;
  input [0:10]of_predecode;
  input [31:0]in;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;
  input \Using_FPGA.Native_5 ;
  input [16:0]\Using_FPGA.Native_6 ;
  input \Using_FPGA.Native_7 ;
  input \Using_FPGA.Native_8 ;
  input \Using_FPGA.Native_9 ;
  input \Using_FPGA.Native_10 ;
  input \Using_FPGA.Native_11 ;
  input \Using_FPGA.Native_12 ;
  input \Using_FPGA.Native_13 ;
  input \Using_FPGA.Native_14 ;
  input \Using_FPGA.Native_15 ;
  input \Using_FPGA.Native_16 ;
  input \Using_FPGA.Native_17 ;

  wire Clk;
  wire I0101_out;
  wire I0105_out;
  wire I0109_out;
  wire I0113_out;
  wire I0117_out;
  wire I0121_out;
  wire I0125_out;
  wire I0129_out;
  wire I0133_out;
  wire I0137_out;
  wire I013_out;
  wire I0141_out;
  wire I0145_out;
  wire I0149_out;
  wire I0153_out;
  wire I0157_out;
  wire I0161_out;
  wire I0165_out;
  wire I0169_out;
  wire I017_out;
  wire I021_out;
  wire I025_out;
  wire I029_out;
  wire I033_out;
  wire I037_out;
  wire I041_out;
  wire I045_out;
  wire I049_out;
  wire I053_out;
  wire I057_out;
  wire I05_out;
  wire I061_out;
  wire I065_out;
  wire I069_out;
  wire I073_out;
  wire I077_out;
  wire I081_out;
  wire I085_out;
  wire I089_out;
  wire I093_out;
  wire I097_out;
  wire I09_out;
  wire I0_1;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_10 ;
  wire \Using_FPGA.Native_11 ;
  wire \Using_FPGA.Native_12 ;
  wire \Using_FPGA.Native_13 ;
  wire \Using_FPGA.Native_14 ;
  wire \Using_FPGA.Native_15 ;
  wire \Using_FPGA.Native_16 ;
  wire \Using_FPGA.Native_17 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_5 ;
  wire [16:0]\Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_7 ;
  wire \Using_FPGA.Native_8 ;
  wire \Using_FPGA.Native_9 ;
  wire [31:0]in;
  wire [0:10]of_predecode;
  wire sel_input_i_0;
  wire sync_reset;

  (* XILINX_LEGACY_PRIM = "FDS" *) 
  (* box_type = "PRIMITIVE" *) 
  FDSE #(
    .INIT(1'b1)) 
    \Using_FPGA.Native 
       (.C(Clk),
        .CE(1'b1),
        .D(sel_input_i_0),
        .Q(\Using_FPGA.Native_0 ),
        .S(sync_reset));
  LUT6 #(
    .INIT(64'hF870707070707070)) 
    \Using_FPGA.Native_i_1__104 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[0]),
        .I3(in[31]),
        .I4(in[30]),
        .I5(in[28]),
        .O(I041_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__105 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_2 ),
        .I3(in[10]),
        .O(I045_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__106 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_3 ),
        .I3(in[11]),
        .O(I049_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__107 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_4 ),
        .I3(in[12]),
        .O(I053_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__108 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_5 ),
        .I3(in[13]),
        .O(I057_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__109 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [0]),
        .I3(in[14]),
        .O(I061_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__110 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [1]),
        .I3(in[15]),
        .O(I065_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__111 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [2]),
        .I3(in[16]),
        .O(I069_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__112 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [3]),
        .I3(in[17]),
        .O(I073_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__113 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [4]),
        .I3(in[18]),
        .O(I077_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__114 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [5]),
        .I3(in[19]),
        .O(I081_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__115 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [6]),
        .I3(in[20]),
        .O(I085_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__116 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_7 ),
        .I3(in[21]),
        .O(I0129_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__117 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_8 ),
        .I3(in[22]),
        .O(I0133_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__118 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_9 ),
        .I3(in[23]),
        .O(I0137_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__119 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_10 ),
        .I3(in[24]),
        .O(I0141_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__120 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_11 ),
        .I3(in[25]),
        .O(I0145_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__121 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_12 ),
        .I3(in[26]),
        .O(I0149_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__122 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_13 ),
        .I3(in[27]),
        .O(I0153_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__123 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_14 ),
        .I3(in[28]),
        .O(I0157_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__124 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_15 ),
        .I3(in[29]),
        .O(I0161_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__125 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_16 ),
        .I3(in[30]),
        .O(I0165_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__126 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_17 ),
        .I3(in[31]),
        .O(I0169_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__159 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [16]),
        .I3(in[9]),
        .O(I0125_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__160 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [15]),
        .I3(in[8]),
        .O(I0121_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__161 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [14]),
        .I3(in[7]),
        .O(I0117_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__162 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [13]),
        .I3(in[6]),
        .O(I0113_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__163 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [12]),
        .I3(in[5]),
        .O(I0109_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__164 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [11]),
        .I3(in[4]),
        .O(I0105_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__165 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [10]),
        .I3(in[3]),
        .O(I0101_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__166 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [9]),
        .I3(in[2]),
        .O(I097_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__167 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [8]),
        .I3(in[1]),
        .O(I093_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__168 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_6 [7]),
        .I3(in[0]),
        .O(I089_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__169 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[1]),
        .I3(in[9]),
        .O(I037_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__170 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[2]),
        .I3(in[8]),
        .O(I033_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__171 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[3]),
        .I3(in[7]),
        .O(I029_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__172 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[4]),
        .I3(in[6]),
        .O(I025_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__173 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[5]),
        .I3(in[5]),
        .O(I021_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__174 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[6]),
        .I3(in[4]),
        .O(I017_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__175 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[7]),
        .I3(in[3]),
        .O(I013_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__176 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[8]),
        .I3(in[2]),
        .O(I09_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__177 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[9]),
        .I3(in[1]),
        .O(I05_out));
  LUT4 #(
    .INIT(16'hF870)) 
    \Using_FPGA.Native_i_1__178 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(of_predecode[10]),
        .I3(in[0]),
        .O(I0_1));
endmodule

(* ORIG_REF_NAME = "MB_LUT4" *) 
module design_1_microblaze_0_0_MB_LUT4
   (S,
    Q,
    \MEM_DataBus_Addr_reg[0] ,
    I2,
    alu_AddSub_1);
  output S;
  input [0:0]Q;
  input [0:0]\MEM_DataBus_Addr_reg[0] ;
  input I2;
  input alu_AddSub_1;

  wire I2;
  wire [0:0]\MEM_DataBus_Addr_reg[0] ;
  wire [0:0]Q;
  wire S;
  wire alu_AddSub_1;

  (* box_type = "PRIMITIVE" *) 
  LUT4 #(
    .INIT(16'hFA0A)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[0] ),
        .I2(I2),
        .I3(alu_AddSub_1),
        .O(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6
   (sel_input_iii_3,
    if_sel_input,
    addr,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    I5);
  output sel_input_iii_3;
  input [0:0]if_sel_input;
  input [0:0]addr;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input I5;

  wire I5;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]addr;
  wire [0:0]if_sel_input;
  wire sel_input_iii_3;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h00000000CCF0AACC)) 
    \Using_FPGA.Native 
       (.I0(if_sel_input),
        .I1(addr),
        .I2(1'b0),
        .I3(\Using_FPGA.Native_0 ),
        .I4(\Using_FPGA.Native_1 ),
        .I5(I5),
        .O(sel_input_iii_3));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6_114
   (sel_input_iii_2,
    if_sel_input,
    addr,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    I5);
  output sel_input_iii_2;
  input [1:0]if_sel_input;
  input [0:0]addr;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input I5;

  wire I5;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]addr;
  wire [1:0]if_sel_input;
  wire sel_input_iii_2;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h00000000CCF0AACC)) 
    \Using_FPGA.Native 
       (.I0(if_sel_input[0]),
        .I1(if_sel_input[1]),
        .I2(addr),
        .I3(\Using_FPGA.Native_0 ),
        .I4(\Using_FPGA.Native_1 ),
        .I5(I5),
        .O(sel_input_iii_2));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6_116
   (sel_input_iii_1,
    \Using_FPGA.Native_0 ,
    if_sel_input,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    I5);
  output sel_input_iii_1;
  input \Using_FPGA.Native_0 ;
  input [1:0]if_sel_input;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input I5;

  wire I5;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire [1:0]if_sel_input;
  wire sel_input_iii_1;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h00000000CCF0AACC)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(if_sel_input[0]),
        .I2(if_sel_input[1]),
        .I3(\Using_FPGA.Native_1 ),
        .I4(\Using_FPGA.Native_2 ),
        .I5(I5),
        .O(sel_input_iii_1));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6_118
   (sel_input_iii_0,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    if_sel_input,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    I5);
  output sel_input_iii_0;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input I5;

  wire I5;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire [0:0]if_sel_input;
  wire sel_input_iii_0;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h00000000CCF0AACC)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(if_sel_input),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(I5),
        .O(sel_input_iii_0));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[9] ,
    \MEM_DataBus_Addr_reg[9]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[9] ;
  input [0:0]\MEM_DataBus_Addr_reg[9]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[9] ;
  wire [0:0]\MEM_DataBus_Addr_reg[9]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[9] [1]),
        .I2(\MEM_DataBus_Addr_reg[9]_0 ),
        .I3(\MEM_DataBus_Addr_reg[9] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_520
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[8] ,
    \MEM_DataBus_Addr_reg[8]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[8] ;
  input [0:0]\MEM_DataBus_Addr_reg[8]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[8] ;
  wire [0:0]\MEM_DataBus_Addr_reg[8]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[8] [1]),
        .I2(\MEM_DataBus_Addr_reg[8]_0 ),
        .I3(\MEM_DataBus_Addr_reg[8] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_522
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[7] ,
    \MEM_DataBus_Addr_reg[7]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[7] ;
  input [0:0]\MEM_DataBus_Addr_reg[7]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[7] ;
  wire [0:0]\MEM_DataBus_Addr_reg[7]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[7] [1]),
        .I2(\MEM_DataBus_Addr_reg[7]_0 ),
        .I3(\MEM_DataBus_Addr_reg[7] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_524
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[6] ,
    \MEM_DataBus_Addr_reg[6]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[6] ;
  input [0:0]\MEM_DataBus_Addr_reg[6]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[6] ;
  wire [0:0]\MEM_DataBus_Addr_reg[6]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[6] [1]),
        .I2(\MEM_DataBus_Addr_reg[6]_0 ),
        .I3(\MEM_DataBus_Addr_reg[6] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_526
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[5] ,
    \MEM_DataBus_Addr_reg[5]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[5] ;
  input [0:0]\MEM_DataBus_Addr_reg[5]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[5] ;
  wire [0:0]\MEM_DataBus_Addr_reg[5]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[5] [1]),
        .I2(\MEM_DataBus_Addr_reg[5]_0 ),
        .I3(\MEM_DataBus_Addr_reg[5] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_528
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[4] ,
    \MEM_DataBus_Addr_reg[4]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[4] ;
  input [0:0]\MEM_DataBus_Addr_reg[4]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[4] ;
  wire [0:0]\MEM_DataBus_Addr_reg[4]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[4] [1]),
        .I2(\MEM_DataBus_Addr_reg[4]_0 ),
        .I3(\MEM_DataBus_Addr_reg[4] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_530
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[3] ,
    \MEM_DataBus_Addr_reg[3]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[3] ;
  input [0:0]\MEM_DataBus_Addr_reg[3]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[3] ;
  wire [0:0]\MEM_DataBus_Addr_reg[3]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[3] [1]),
        .I2(\MEM_DataBus_Addr_reg[3]_0 ),
        .I3(\MEM_DataBus_Addr_reg[3] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_532
   (DI,
    S,
    Q,
    \Using_FPGA.Native_I2 ,
    \Using_FPGA.Native_I2_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\Using_FPGA.Native_I2 ;
  input [0:0]\Using_FPGA.Native_I2_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [0:0]Q;
  wire S;
  wire [1:0]\Using_FPGA.Native_I2 ;
  wire [0:0]\Using_FPGA.Native_I2_0 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\Using_FPGA.Native_I2 [1]),
        .I2(\Using_FPGA.Native_I2_0 ),
        .I3(\Using_FPGA.Native_I2 [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_534
   (DI,
    S,
    Q,
    \Using_FPGA.Native_I2 ,
    \Using_FPGA.Native_I2_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\Using_FPGA.Native_I2 ;
  input [0:0]\Using_FPGA.Native_I2_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [0:0]Q;
  wire S;
  wire [1:0]\Using_FPGA.Native_I2 ;
  wire [0:0]\Using_FPGA.Native_I2_0 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\Using_FPGA.Native_I2 [1]),
        .I2(\Using_FPGA.Native_I2_0 ),
        .I3(\Using_FPGA.Native_I2 [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_536
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[2] ,
    \MEM_DataBus_Addr_reg[2]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[2] ;
  input [0:0]\MEM_DataBus_Addr_reg[2]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[2] ;
  wire [0:0]\MEM_DataBus_Addr_reg[2]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[2] [1]),
        .I2(\MEM_DataBus_Addr_reg[2]_0 ),
        .I3(\MEM_DataBus_Addr_reg[2] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_538
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[29] ,
    \MEM_DataBus_Addr_reg[29]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[29] ;
  input [0:0]\MEM_DataBus_Addr_reg[29]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[29] ;
  wire [0:0]\MEM_DataBus_Addr_reg[29]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[29] [1]),
        .I2(\MEM_DataBus_Addr_reg[29]_0 ),
        .I3(\MEM_DataBus_Addr_reg[29] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_540
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[28] ,
    \MEM_DataBus_Addr_reg[28]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[28] ;
  input [0:0]\MEM_DataBus_Addr_reg[28]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[28] ;
  wire [0:0]\MEM_DataBus_Addr_reg[28]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[28] [1]),
        .I2(\MEM_DataBus_Addr_reg[28]_0 ),
        .I3(\MEM_DataBus_Addr_reg[28] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_542
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[27] ,
    \MEM_DataBus_Addr_reg[27]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[27] ;
  input [0:0]\MEM_DataBus_Addr_reg[27]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[27] ;
  wire [0:0]\MEM_DataBus_Addr_reg[27]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[27] [1]),
        .I2(\MEM_DataBus_Addr_reg[27]_0 ),
        .I3(\MEM_DataBus_Addr_reg[27] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_544
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[26] ,
    \MEM_DataBus_Addr_reg[26]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[26] ;
  input [0:0]\MEM_DataBus_Addr_reg[26]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[26] ;
  wire [0:0]\MEM_DataBus_Addr_reg[26]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[26] [1]),
        .I2(\MEM_DataBus_Addr_reg[26]_0 ),
        .I3(\MEM_DataBus_Addr_reg[26] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_546
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[25] ,
    \MEM_DataBus_Addr_reg[25]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[25] ;
  input [0:0]\MEM_DataBus_Addr_reg[25]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[25] ;
  wire [0:0]\MEM_DataBus_Addr_reg[25]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[25] [1]),
        .I2(\MEM_DataBus_Addr_reg[25]_0 ),
        .I3(\MEM_DataBus_Addr_reg[25] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_548
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[24] ,
    \MEM_DataBus_Addr_reg[24]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[24] ;
  input [0:0]\MEM_DataBus_Addr_reg[24]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[24] ;
  wire [0:0]\MEM_DataBus_Addr_reg[24]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[24] [1]),
        .I2(\MEM_DataBus_Addr_reg[24]_0 ),
        .I3(\MEM_DataBus_Addr_reg[24] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_550
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[23] ,
    \MEM_DataBus_Addr_reg[23]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[23] ;
  input [0:0]\MEM_DataBus_Addr_reg[23]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[23] ;
  wire [0:0]\MEM_DataBus_Addr_reg[23]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[23] [1]),
        .I2(\MEM_DataBus_Addr_reg[23]_0 ),
        .I3(\MEM_DataBus_Addr_reg[23] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_552
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[22] ,
    \MEM_DataBus_Addr_reg[22]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[22] ;
  input [0:0]\MEM_DataBus_Addr_reg[22]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[22] ;
  wire [0:0]\MEM_DataBus_Addr_reg[22]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[22] [1]),
        .I2(\MEM_DataBus_Addr_reg[22]_0 ),
        .I3(\MEM_DataBus_Addr_reg[22] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_554
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[21] ,
    \MEM_DataBus_Addr_reg[21]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[21] ;
  input [0:0]\MEM_DataBus_Addr_reg[21]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[21] ;
  wire [0:0]\MEM_DataBus_Addr_reg[21]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[21] [1]),
        .I2(\MEM_DataBus_Addr_reg[21]_0 ),
        .I3(\MEM_DataBus_Addr_reg[21] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_556
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[20] ,
    \MEM_DataBus_Addr_reg[20]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[20] ;
  input [0:0]\MEM_DataBus_Addr_reg[20]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[20] ;
  wire [0:0]\MEM_DataBus_Addr_reg[20]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[20] [1]),
        .I2(\MEM_DataBus_Addr_reg[20]_0 ),
        .I3(\MEM_DataBus_Addr_reg[20] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_558
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[1] ,
    \MEM_DataBus_Addr_reg[1]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[1] ;
  input [0:0]\MEM_DataBus_Addr_reg[1]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[1] ;
  wire [0:0]\MEM_DataBus_Addr_reg[1]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[1] [1]),
        .I2(\MEM_DataBus_Addr_reg[1]_0 ),
        .I3(\MEM_DataBus_Addr_reg[1] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_560
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[19] ,
    \MEM_DataBus_Addr_reg[19]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[19] ;
  input [0:0]\MEM_DataBus_Addr_reg[19]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[19] ;
  wire [0:0]\MEM_DataBus_Addr_reg[19]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[19] [1]),
        .I2(\MEM_DataBus_Addr_reg[19]_0 ),
        .I3(\MEM_DataBus_Addr_reg[19] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_562
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[18] ,
    \MEM_DataBus_Addr_reg[18]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[18] ;
  input [0:0]\MEM_DataBus_Addr_reg[18]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[18] ;
  wire [0:0]\MEM_DataBus_Addr_reg[18]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[18] [1]),
        .I2(\MEM_DataBus_Addr_reg[18]_0 ),
        .I3(\MEM_DataBus_Addr_reg[18] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_564
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[17] ,
    \MEM_DataBus_Addr_reg[17]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[17] ;
  input [0:0]\MEM_DataBus_Addr_reg[17]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[17] ;
  wire [0:0]\MEM_DataBus_Addr_reg[17]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[17] [1]),
        .I2(\MEM_DataBus_Addr_reg[17]_0 ),
        .I3(\MEM_DataBus_Addr_reg[17] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_566
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[16] ,
    \MEM_DataBus_Addr_reg[16]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[16] ;
  input [0:0]\MEM_DataBus_Addr_reg[16]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[16] ;
  wire [0:0]\MEM_DataBus_Addr_reg[16]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[16] [1]),
        .I2(\MEM_DataBus_Addr_reg[16]_0 ),
        .I3(\MEM_DataBus_Addr_reg[16] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_568
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[15] ,
    \MEM_DataBus_Addr_reg[15]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[15] ;
  input [0:0]\MEM_DataBus_Addr_reg[15]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[15] ;
  wire [0:0]\MEM_DataBus_Addr_reg[15]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[15] [1]),
        .I2(\MEM_DataBus_Addr_reg[15]_0 ),
        .I3(\MEM_DataBus_Addr_reg[15] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_570
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[14] ,
    \MEM_DataBus_Addr_reg[14]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[14] ;
  input [0:0]\MEM_DataBus_Addr_reg[14]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[14] ;
  wire [0:0]\MEM_DataBus_Addr_reg[14]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[14] [1]),
        .I2(\MEM_DataBus_Addr_reg[14]_0 ),
        .I3(\MEM_DataBus_Addr_reg[14] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_572
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[13] ,
    \MEM_DataBus_Addr_reg[13]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[13] ;
  input [0:0]\MEM_DataBus_Addr_reg[13]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[13] ;
  wire [0:0]\MEM_DataBus_Addr_reg[13]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[13] [1]),
        .I2(\MEM_DataBus_Addr_reg[13]_0 ),
        .I3(\MEM_DataBus_Addr_reg[13] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_574
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[12] ,
    \MEM_DataBus_Addr_reg[12]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[12] ;
  input [0:0]\MEM_DataBus_Addr_reg[12]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[12] ;
  wire [0:0]\MEM_DataBus_Addr_reg[12]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[12] [1]),
        .I2(\MEM_DataBus_Addr_reg[12]_0 ),
        .I3(\MEM_DataBus_Addr_reg[12] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_576
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[11] ,
    \MEM_DataBus_Addr_reg[11]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[11] ;
  input [0:0]\MEM_DataBus_Addr_reg[11]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[11] ;
  wire [0:0]\MEM_DataBus_Addr_reg[11]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[11] [1]),
        .I2(\MEM_DataBus_Addr_reg[11]_0 ),
        .I3(\MEM_DataBus_Addr_reg[11] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2_578
   (DI,
    S,
    Q,
    \MEM_DataBus_Addr_reg[10] ,
    \MEM_DataBus_Addr_reg[10]_0 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output DI;
  output S;
  input [0:0]Q;
  input [1:0]\MEM_DataBus_Addr_reg[10] ;
  input [0:0]\MEM_DataBus_Addr_reg[10]_0 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire DI;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [1:0]\MEM_DataBus_Addr_reg[10] ;
  wire [0:0]\MEM_DataBus_Addr_reg[10]_0 ;
  wire [0:0]Q;
  wire S;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\MEM_DataBus_Addr_reg[10] [1]),
        .I2(\MEM_DataBus_Addr_reg[10]_0 ),
        .I3(\MEM_DataBus_Addr_reg[10] [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O5(DI),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized1
   (muxcy_di,
    muxcy_sel);
  output muxcy_di;
  output muxcy_sel;

  wire muxcy_di;
  wire muxcy_sel;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h00FF00FFFEFEFEFE)) 
    \Using_FPGA.Native 
       (.I0(1'b0),
        .I1(1'b0),
        .I2(1'b0),
        .I3(1'b0),
        .I4(1'b0),
        .I5(1'b1),
        .O5(muxcy_di),
        .O6(muxcy_sel));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3
   (Y,
    I139_out,
    in,
    Instr,
    LOCKSTEP_Master_Out,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 );
  output [1:0]Y;
  output I139_out;
  output [0:0]in;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;
  input [0:0]\Using_FPGA.Native_0 ;
  input [0:0]\Using_FPGA.Native_1 ;
  input [1:0]\Using_FPGA.Native_2 ;

  wire I139_out;
  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [1:0]\Using_FPGA.Native_2 ;
  wire [1:0]Y;
  wire [0:0]in;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
  LUT5 #(
    .INIT(32'hE2222222)) 
    \Using_FPGA.Native_i_2__58 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Y[1]),
        .I3(\Using_FPGA.Native_2 [1]),
        .I4(\Using_FPGA.Native_2 [0]),
        .O(I139_out));
  LUT3 #(
    .INIT(8'h80)) 
    \ibuffer_reg[3][32]_srl4_i_1 
       (.I0(Y[1]),
        .I1(\Using_FPGA.Native_2 [1]),
        .I2(\Using_FPGA.Native_2 [0]),
        .O(in));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_10
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_11
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_12
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_13
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_14
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_15
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_16
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_2
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_3
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_4
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_5
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_6
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_7
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_8
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized3_9
   (Y,
    Instr,
    LOCKSTEP_Master_Out);
  output [1:0]Y;
  input [1:0]Instr;
  input [2:0]LOCKSTEP_Master_Out;

  wire [1:0]Instr;
  wire [2:0]LOCKSTEP_Master_Out;
  wire [1:0]Y;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'hFF00F0F0CCCCAAAA)) 
    \Using_FPGA.Native 
       (.I0(Instr[1]),
        .I1(LOCKSTEP_Master_Out[1]),
        .I2(Instr[0]),
        .I3(LOCKSTEP_Master_Out[0]),
        .I4(LOCKSTEP_Master_Out[2]),
        .I5(1'b1),
        .O5(Y[1]),
        .O6(Y[0]));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5
   (\Using_FPGA.Native_0 ,
    addr_AddSub_31,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output addr_AddSub_31;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;
  wire addr_AddSub_31;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(addr_AddSub_31));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_309
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_312
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_315
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_318
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_321
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_324
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_327
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_330
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_333
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_336
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_339
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_342
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_345
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_348
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_351
   (\Using_FPGA.Native_0 ,
    S,
    DI,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 );
  output \Using_FPGA.Native_0 ;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;

  wire DI;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_354
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_357
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_360
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_363
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_366
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_369
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    I1_1,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input I1_1;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire I1_1;
  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(I1_1),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_372
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_375
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_378
   (O5,
    S,
    DI,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 );
  output O5;
  output S;
  input DI;
  input [0:0]\Using_FPGA.Native_0 ;
  input [0:0]\Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;

  wire DI;
  wire O5;
  wire S;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(DI),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_0 ),
        .I3(\Using_FPGA.Native_1 ),
        .I4(\Using_FPGA.Native_2 ),
        .I5(1'b1),
        .O5(O5),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_381
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_384
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_387
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_390
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_393
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_396
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6_2" *) 
module design_1_microblaze_0_0_MB_LUT6_2__parameterized5_399
   (\Using_FPGA.Native_0 ,
    S,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 );
  output \Using_FPGA.Native_0 ;
  output S;
  input \Using_FPGA.Native_1 ;
  input [0:0]\Using_FPGA.Native_2 ;
  input [0:0]\Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;

  wire S;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire [0:0]\Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;

  (* box_type = "PRIMITIVE" *) 
  LUT6_2 #(
    .INIT(64'h96969696FF00AAAA)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_1 ),
        .I1(1'b0),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(\Using_FPGA.Native_4 ),
        .I5(1'b1),
        .O5(\Using_FPGA.Native_0 ),
        .O6(S));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized10
   (A,
    I0,
    of_predecode,
    D,
    \Using_FPGA.Native_i_1__58_0 ,
    \Using_FPGA.Native_i_1__58_1 ,
    ex_is_multi_or_load_instr,
    O);
  output A;
  input I0;
  input [1:0]of_predecode;
  input [0:0]D;
  input \Using_FPGA.Native_i_1__58_0 ;
  input \Using_FPGA.Native_i_1__58_1 ;
  input ex_is_multi_or_load_instr;
  input O;

  wire A;
  wire [0:0]D;
  wire I0;
  wire O;
  wire \Using_FPGA.Native_i_1__58_0 ;
  wire \Using_FPGA.Native_i_1__58_1 ;
  wire ex_is_multi_or_load_instr;
  wire [1:0]of_predecode;
  wire of_read_ex_write_op1_conflict_part2;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000000000)) 
    \Using_FPGA.Native 
       (.I0(I0),
        .I1(of_predecode[1]),
        .I2(D),
        .I3(of_predecode[0]),
        .I4(\Using_FPGA.Native_i_1__58_0 ),
        .I5(\Using_FPGA.Native_i_1__58_1 ),
        .O(of_read_ex_write_op1_conflict_part2));
  LUT3 #(
    .INIT(8'h7F)) 
    \Using_FPGA.Native_i_1__58 
       (.I0(of_read_ex_write_op1_conflict_part2),
        .I1(ex_is_multi_or_load_instr),
        .I2(O),
        .O(A));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized10_77
   (ex_is_multi_or_load_instr_reg,
    I0,
    of_predecode,
    D,
    \Using_FPGA.Native_i_1__9_0 ,
    \Using_FPGA.Native_i_1__9_1 ,
    of_use_op2_s,
    ex_is_multi_or_load_instr,
    of_read_ex_write_op2_conflict_part1);
  output ex_is_multi_or_load_instr_reg;
  input I0;
  input [1:0]of_predecode;
  input [0:0]D;
  input \Using_FPGA.Native_i_1__9_0 ;
  input \Using_FPGA.Native_i_1__9_1 ;
  input of_use_op2_s;
  input ex_is_multi_or_load_instr;
  input of_read_ex_write_op2_conflict_part1;

  wire [0:0]D;
  wire I0;
  wire \Using_FPGA.Native_i_1__9_0 ;
  wire \Using_FPGA.Native_i_1__9_1 ;
  wire ex_is_multi_or_load_instr;
  wire ex_is_multi_or_load_instr_reg;
  wire [1:0]of_predecode;
  wire of_read_ex_write_op2_conflict_part1;
  wire of_read_ex_write_op2_conflict_part2;
  wire of_use_op2_s;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000000000)) 
    \Using_FPGA.Native 
       (.I0(I0),
        .I1(of_predecode[1]),
        .I2(D),
        .I3(of_predecode[0]),
        .I4(\Using_FPGA.Native_i_1__9_0 ),
        .I5(\Using_FPGA.Native_i_1__9_1 ),
        .O(of_read_ex_write_op2_conflict_part2));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \Using_FPGA.Native_i_1__9 
       (.I0(of_read_ex_write_op2_conflict_part2),
        .I1(of_use_op2_s),
        .I2(ex_is_multi_or_load_instr),
        .I3(of_read_ex_write_op2_conflict_part1),
        .O(ex_is_multi_or_load_instr_reg));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized10_79
   (ex_is_multi_or_load_instr_reg,
    I0,
    \Using_FPGA.Native_i_1__56_0 ,
    D,
    \Using_FPGA.Native_i_1__56_1 ,
    \Using_FPGA.Native_i_1__56_2 ,
    \Using_FPGA.Native_i_1__56_3 ,
    of_read_ex_write_op3_conflict_part1,
    ex_is_multi_or_load_instr,
    of_predecode);
  output ex_is_multi_or_load_instr_reg;
  input I0;
  input \Using_FPGA.Native_i_1__56_0 ;
  input [0:0]D;
  input \Using_FPGA.Native_i_1__56_1 ;
  input \Using_FPGA.Native_i_1__56_2 ;
  input \Using_FPGA.Native_i_1__56_3 ;
  input of_read_ex_write_op3_conflict_part1;
  input ex_is_multi_or_load_instr;
  input [0:0]of_predecode;

  wire [0:0]D;
  wire I0;
  wire \Using_FPGA.Native_i_1__56_0 ;
  wire \Using_FPGA.Native_i_1__56_1 ;
  wire \Using_FPGA.Native_i_1__56_2 ;
  wire \Using_FPGA.Native_i_1__56_3 ;
  wire ex_is_multi_or_load_instr;
  wire ex_is_multi_or_load_instr_reg;
  wire [0:0]of_predecode;
  wire of_read_ex_write_op3_conflict_part1;
  wire of_read_ex_write_op3_conflict_part2;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000000000)) 
    \Using_FPGA.Native 
       (.I0(I0),
        .I1(\Using_FPGA.Native_i_1__56_0 ),
        .I2(D),
        .I3(\Using_FPGA.Native_i_1__56_1 ),
        .I4(\Using_FPGA.Native_i_1__56_2 ),
        .I5(\Using_FPGA.Native_i_1__56_3 ),
        .O(of_read_ex_write_op3_conflict_part2));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \Using_FPGA.Native_i_1__56 
       (.I0(of_read_ex_write_op3_conflict_part2),
        .I1(of_read_ex_write_op3_conflict_part1),
        .I2(ex_is_multi_or_load_instr),
        .I3(of_predecode),
        .O(ex_is_multi_or_load_instr_reg));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized10_81
   (of_read_mem_write_op1_conflict_part2,
    Q,
    of_predecode,
    mem_gpr_write,
    mem_valid_instr);
  output of_read_mem_write_op1_conflict_part2;
  input [1:0]Q;
  input [1:0]of_predecode;
  input mem_gpr_write;
  input mem_valid_instr;

  wire [1:0]Q;
  wire mem_gpr_write;
  wire mem_valid_instr;
  wire [1:0]of_predecode;
  wire of_read_mem_write_op1_conflict_part2;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000000000)) 
    \Using_FPGA.Native 
       (.I0(Q[1]),
        .I1(of_predecode[1]),
        .I2(Q[0]),
        .I3(of_predecode[0]),
        .I4(mem_gpr_write),
        .I5(mem_valid_instr),
        .O(of_read_mem_write_op1_conflict_part2));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized10_83
   (mem_is_multi_or_load_instr_reg,
    Q,
    of_predecode,
    mem_gpr_write,
    mem_valid_instr,
    of_use_op2_s,
    mem_is_multi_or_load_instr,
    of_read_mem_write_op2_conflict_part1);
  output mem_is_multi_or_load_instr_reg;
  input [1:0]Q;
  input [1:0]of_predecode;
  input mem_gpr_write;
  input mem_valid_instr;
  input of_use_op2_s;
  input mem_is_multi_or_load_instr;
  input of_read_mem_write_op2_conflict_part1;

  wire [1:0]Q;
  wire mem_gpr_write;
  wire mem_is_multi_or_load_instr;
  wire mem_is_multi_or_load_instr_reg;
  wire mem_valid_instr;
  wire [1:0]of_predecode;
  wire of_read_mem_write_op2_conflict_part1;
  wire of_read_mem_write_op2_conflict_part2;
  wire of_use_op2_s;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000000000)) 
    \Using_FPGA.Native 
       (.I0(Q[1]),
        .I1(of_predecode[1]),
        .I2(Q[0]),
        .I3(of_predecode[0]),
        .I4(mem_gpr_write),
        .I5(mem_valid_instr),
        .O(of_read_mem_write_op2_conflict_part2));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \Using_FPGA.Native_i_1__10 
       (.I0(of_read_mem_write_op2_conflict_part2),
        .I1(of_use_op2_s),
        .I2(mem_is_multi_or_load_instr),
        .I3(of_read_mem_write_op2_conflict_part1),
        .O(mem_is_multi_or_load_instr_reg));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized10_85
   (mem_is_multi_or_load_instr_reg,
    Q,
    \Using_FPGA.Native_i_1__55_0 ,
    \Using_FPGA.Native_i_1__55_1 ,
    mem_gpr_write,
    mem_valid_instr,
    of_read_mem_write_op3_conflict_part1,
    mem_is_multi_or_load_instr,
    of_predecode);
  output mem_is_multi_or_load_instr_reg;
  input [1:0]Q;
  input \Using_FPGA.Native_i_1__55_0 ;
  input \Using_FPGA.Native_i_1__55_1 ;
  input mem_gpr_write;
  input mem_valid_instr;
  input of_read_mem_write_op3_conflict_part1;
  input mem_is_multi_or_load_instr;
  input [0:0]of_predecode;

  wire [1:0]Q;
  wire \Using_FPGA.Native_i_1__55_0 ;
  wire \Using_FPGA.Native_i_1__55_1 ;
  wire mem_gpr_write;
  wire mem_is_multi_or_load_instr;
  wire mem_is_multi_or_load_instr_reg;
  wire mem_valid_instr;
  wire [0:0]of_predecode;
  wire of_read_mem_write_op3_conflict_part1;
  wire of_read_mem_write_op3_conflict_part2;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000000000)) 
    \Using_FPGA.Native 
       (.I0(Q[1]),
        .I1(\Using_FPGA.Native_i_1__55_0 ),
        .I2(Q[0]),
        .I3(\Using_FPGA.Native_i_1__55_1 ),
        .I4(mem_gpr_write),
        .I5(mem_valid_instr),
        .O(of_read_mem_write_op3_conflict_part2));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \Using_FPGA.Native_i_1__55 
       (.I0(of_read_mem_write_op3_conflict_part2),
        .I1(of_read_mem_write_op3_conflict_part1),
        .I2(mem_is_multi_or_load_instr),
        .I3(of_predecode),
        .O(mem_is_multi_or_load_instr_reg));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized12
   (alu_AddSub_1,
    Q,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    EX_ALU_Sel_Logic,
    EX_Enable_ALU);
  output alu_AddSub_1;
  input [0:0]Q;
  input [1:0]\Using_FPGA.Native_0 ;
  input [0:0]\Using_FPGA.Native_1 ;
  input EX_ALU_Sel_Logic;
  input EX_Enable_ALU;

  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [0:0]Q;
  wire [1:0]\Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire alu_AddSub_1;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h607AA67800008888)) 
    \Using_FPGA.Native 
       (.I0(Q),
        .I1(\Using_FPGA.Native_0 [1]),
        .I2(\Using_FPGA.Native_1 ),
        .I3(\Using_FPGA.Native_0 [0]),
        .I4(EX_ALU_Sel_Logic),
        .I5(EX_Enable_ALU),
        .O(alu_AddSub_1));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized2
   (sel_input_delayslot,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    if_sel_input,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    I5);
  output sel_input_delayslot;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input [0:0]if_sel_input;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input I5;

  wire I5;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire [0:0]if_sel_input;
  wire sel_input_delayslot;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h0000FFFFCCF0AACC)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(if_sel_input),
        .I3(\Using_FPGA.Native_2 ),
        .I4(\Using_FPGA.Native_3 ),
        .I5(I5),
        .O(sel_input_delayslot));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized4
   (sel_input_i_0,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    I4_0,
    I5);
  output sel_input_i_0;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input I4_0;
  input I5;

  wire I4_0;
  wire I5;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire sel_input_i_0;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'hFF00FFFFAE0AAE0A)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(I4_0),
        .I5(I5),
        .O(sel_input_i_0));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized6
   (of_Valid_II,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    I4_0,
    I5);
  output of_Valid_II;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input I4_0;
  input I5;

  wire I4_0;
  wire I5;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire of_Valid_II;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h00FF000051F551F5)) 
    \Using_FPGA.Native 
       (.I0(\Using_FPGA.Native_0 ),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(I4_0),
        .I5(I5),
        .O(of_Valid_II));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized8
   (O,
    D,
    of_predecode);
  output O;
  input [2:0]D;
  input [2:0]of_predecode;

  wire [2:0]D;
  wire O;
  wire [2:0]of_predecode;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native 
       (.I0(D[2]),
        .I1(of_predecode[2]),
        .I2(D[1]),
        .I3(of_predecode[1]),
        .I4(D[0]),
        .I5(of_predecode[0]),
        .O(O));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized8_76
   (of_read_ex_write_op2_conflict_part1,
    D,
    of_predecode);
  output of_read_ex_write_op2_conflict_part1;
  input [2:0]D;
  input [2:0]of_predecode;

  wire [2:0]D;
  wire [2:0]of_predecode;
  wire of_read_ex_write_op2_conflict_part1;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native 
       (.I0(D[2]),
        .I1(of_predecode[2]),
        .I2(D[1]),
        .I3(of_predecode[1]),
        .I4(D[0]),
        .I5(of_predecode[0]),
        .O(of_read_ex_write_op2_conflict_part1));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized8_78
   (of_read_ex_write_op3_conflict_part1,
    D,
    \Using_FPGA.Native_i_1__56 ,
    \Using_FPGA.Native_i_1__56_0 );
  output of_read_ex_write_op3_conflict_part1;
  input [2:0]D;
  input [1:0]\Using_FPGA.Native_i_1__56 ;
  input \Using_FPGA.Native_i_1__56_0 ;

  wire [2:0]D;
  wire [1:0]\Using_FPGA.Native_i_1__56 ;
  wire \Using_FPGA.Native_i_1__56_0 ;
  wire of_read_ex_write_op3_conflict_part1;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native 
       (.I0(D[2]),
        .I1(\Using_FPGA.Native_i_1__56 [1]),
        .I2(D[1]),
        .I3(\Using_FPGA.Native_i_1__56 [0]),
        .I4(D[0]),
        .I5(\Using_FPGA.Native_i_1__56_0 ),
        .O(of_read_ex_write_op3_conflict_part1));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized8_80
   (mem_is_multi_or_load_instr_reg,
    Q,
    of_predecode,
    mem_is_multi_or_load_instr,
    of_read_mem_write_op1_conflict_part2);
  output mem_is_multi_or_load_instr_reg;
  input [2:0]Q;
  input [2:0]of_predecode;
  input mem_is_multi_or_load_instr;
  input of_read_mem_write_op1_conflict_part2;

  wire [2:0]Q;
  wire mem_is_multi_or_load_instr;
  wire mem_is_multi_or_load_instr_reg;
  wire [2:0]of_predecode;
  wire of_read_mem_write_op1_conflict_part1;
  wire of_read_mem_write_op1_conflict_part2;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native 
       (.I0(Q[2]),
        .I1(of_predecode[2]),
        .I2(Q[1]),
        .I3(of_predecode[1]),
        .I4(Q[0]),
        .I5(of_predecode[0]),
        .O(of_read_mem_write_op1_conflict_part1));
  LUT3 #(
    .INIT(8'h7F)) 
    \Using_FPGA.Native_i_1__57 
       (.I0(of_read_mem_write_op1_conflict_part1),
        .I1(mem_is_multi_or_load_instr),
        .I2(of_read_mem_write_op1_conflict_part2),
        .O(mem_is_multi_or_load_instr_reg));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized8_82
   (of_read_mem_write_op2_conflict_part1,
    Q,
    of_predecode);
  output of_read_mem_write_op2_conflict_part1;
  input [2:0]Q;
  input [2:0]of_predecode;

  wire [2:0]Q;
  wire [2:0]of_predecode;
  wire of_read_mem_write_op2_conflict_part1;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native 
       (.I0(Q[2]),
        .I1(of_predecode[2]),
        .I2(Q[1]),
        .I3(of_predecode[1]),
        .I4(Q[0]),
        .I5(of_predecode[0]),
        .O(of_read_mem_write_op2_conflict_part1));
endmodule

(* ORIG_REF_NAME = "MB_LUT6" *) 
module design_1_microblaze_0_0_MB_LUT6__parameterized8_84
   (of_read_mem_write_op3_conflict_part1,
    Q,
    D,
    \Using_FPGA.Native_i_1__55 );
  output of_read_mem_write_op3_conflict_part1;
  input [2:0]Q;
  input [1:0]D;
  input \Using_FPGA.Native_i_1__55 ;

  wire [1:0]D;
  wire [2:0]Q;
  wire \Using_FPGA.Native_i_1__55 ;
  wire of_read_mem_write_op3_conflict_part1;

  (* box_type = "PRIMITIVE" *) 
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    \Using_FPGA.Native 
       (.I0(Q[2]),
        .I1(D[1]),
        .I2(Q[1]),
        .I3(D[0]),
        .I4(Q[0]),
        .I5(\Using_FPGA.Native_i_1__55 ),
        .O(of_read_mem_write_op3_conflict_part1));
endmodule

(* ORIG_REF_NAME = "MB_MULT_AND" *) 
module design_1_microblaze_0_0_MB_MULT_AND
   (DI,
    I0,
    \Using_FPGA.Native_I1 );
  output DI;
  input I0;
  input [0:0]\Using_FPGA.Native_I1 ;

  wire DI;
  wire I0;
  wire [0:0]\Using_FPGA.Native_I1 ;

  (* XILINX_LEGACY_PRIM = "MULT_AND" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \Using_FPGA.Native 
       (.I0(I0),
        .I1(\Using_FPGA.Native_I1 ),
        .O(DI));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY
   (carry_7,
    SRL16_Sel_7,
    Q,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output carry_7;
  input SRL16_Sel_7;
  input [0:0]Q;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  input lopt_20;

  wire [0:0]Q;
  wire SRL16_Sel_7;
  wire carry_7;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire lopt_21;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire [7:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;

  assign \^lopt_14  = lopt_13;
  assign \^lopt_15  = lopt_14;
  assign \^lopt_16  = lopt_15;
  assign \^lopt_17  = lopt_16;
  assign \^lopt_18  = lopt_17;
  assign \^lopt_19  = lopt_18;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_20  = lopt_19;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_21 = lopt_20;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(Q),
        .CI_TOP(1'b0),
        .CO({\^lopt_10 ,\^lopt_11 ,\^lopt_12 ,\^lopt_13 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,carry_7}),
        .DI({\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_17 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b0}),
        .O(\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [7:0]),
        .S({\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,lopt_21,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,SRL16_Sel_7}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_100
   (if_pc_incr_carry1,
    \Using_FPGA.Native_0 ,
    if_pc_incr_carry0,
    lopt,
    lopt_1);
  output if_pc_incr_carry1;
  input \Using_FPGA.Native_0 ;
  input if_pc_incr_carry0;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire \Using_FPGA.Native_0 ;
  wire if_pc_incr_carry0;
  wire if_pc_incr_carry1;

  assign if_pc_incr_carry1 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_101
   (of_PipeRun_carry_2,
    \Using_FPGA.Native_0 ,
    of_PipeRun_carry_3,
    lopt,
    lopt_1);
  output of_PipeRun_carry_2;
  input \Using_FPGA.Native_0 ;
  input of_PipeRun_carry_3;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire \Using_FPGA.Native_0 ;
  wire of_PipeRun_carry_2;
  wire of_PipeRun_carry_3;

  assign lopt_1 = \<const0> ;
  assign of_PipeRun_carry_2 = lopt;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_102
   (of_PipeRun_carry_3,
    \Using_FPGA.Native_0 ,
    of_PipeRun_carry_4,
    lopt,
    lopt_1);
  output of_PipeRun_carry_3;
  input \Using_FPGA.Native_0 ;
  input of_PipeRun_carry_4;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire \Using_FPGA.Native_0 ;
  wire of_PipeRun_carry_3;
  wire of_PipeRun_carry_4;

  assign lopt_1 = \<const0> ;
  assign of_PipeRun_carry_3 = lopt;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_103
   (of_PipeRun_carry_4,
    \Using_FPGA.Native_0 ,
    of_PipeRun_carry_5,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11);
  output of_PipeRun_carry_4;
  input \Using_FPGA.Native_0 ;
  input of_PipeRun_carry_5;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  input lopt_10;
  input lopt_11;

  wire \Using_FPGA.Native_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire lopt_12;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire of_PipeRun_carry_4;
  wire of_PipeRun_carry_5;
  wire [7:5]\NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED ;
  wire [7:5]\NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED ;
  wire [7:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;
  wire [7:5]\NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED ;

  assign \^lopt_11  = lopt_10;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_12 = lopt_11;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(of_PipeRun_carry_5),
        .CI_TOP(1'b0),
        .CO({\NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED [7:5],\^lopt_10 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,of_PipeRun_carry_4}),
        .DI({\NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED [7:5],\^lopt_11 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b0}),
        .O(\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [7:0]),
        .S({\NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED [7:5],lopt_12,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,\Using_FPGA.Native_0 }));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_104
   (of_PipeRun_carry_5,
    \Using_FPGA.Native_0 ,
    of_PipeRun_carry_6,
    lopt,
    lopt_1);
  output of_PipeRun_carry_5;
  input \Using_FPGA.Native_0 ;
  input of_PipeRun_carry_6;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire \Using_FPGA.Native_0 ;
  wire of_PipeRun_carry_5;
  wire of_PipeRun_carry_6;

  assign lopt_1 = \<const0> ;
  assign of_PipeRun_carry_5 = lopt;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_105
   (of_PipeRun_carry_6,
    A,
    of_PipeRun_carry_7,
    lopt,
    lopt_1);
  output of_PipeRun_carry_6;
  input A;
  input of_PipeRun_carry_7;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire A;
  wire of_PipeRun_carry_6;
  wire of_PipeRun_carry_7;

  assign lopt_1 = \<const0> ;
  assign of_PipeRun_carry_6 = lopt;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_106
   (of_PipeRun_carry_7,
    \Using_FPGA.Native_0 ,
    E,
    lopt,
    lopt_1);
  output of_PipeRun_carry_7;
  input \Using_FPGA.Native_0 ;
  input [0:0]E;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire [0:0]E;
  wire \Using_FPGA.Native_0 ;
  wire of_PipeRun_carry_7;

  assign lopt_1 = \<const0> ;
  assign of_PipeRun_carry_7 = lopt;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_107
   (\Using_FPGA.Native_0 ,
    \wb_exception_kind_i_reg[28] ,
    in0,
    ex_Write_ICache_i_reg,
    of_PipeRun_carry_9,
    Q,
    wb_exception,
    \mem_pc_i_reg[0] ,
    ex_Write_DCache_decode_reg,
    ex_write_dcache_instr,
    ex_Write_ICache_i,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14);
  output \Using_FPGA.Native_0 ;
  output [0:0]\wb_exception_kind_i_reg[28] ;
  output in0;
  output ex_Write_ICache_i_reg;
  input of_PipeRun_carry_9;
  input [1:0]Q;
  input wb_exception;
  input \mem_pc_i_reg[0] ;
  input ex_Write_DCache_decode_reg;
  input ex_write_dcache_instr;
  input ex_Write_ICache_i;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  input lopt_9;
  input lopt_10;
  input lopt_11;
  input lopt_12;
  output lopt_13;
  output lopt_14;

  wire \<const0> ;
  wire \<const1> ;
  wire [1:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire ex_Write_DCache_decode_reg;
  wire ex_Write_ICache_i;
  wire ex_Write_ICache_i_reg;
  wire ex_write_dcache_instr;
  wire in0;
  wire \^lopt_1 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire \mem_pc_i_reg[0] ;
  wire of_PipeRun_carry_9;
  wire wb_exception;
  wire [0:0]\wb_exception_kind_i_reg[28] ;

  assign \Using_FPGA.Native_0  = lopt_12;
  assign \^lopt_1  = lopt_11;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_10;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_9;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_13 = \<const0> ;
  assign lopt_14 = \<const1> ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'h10)) 
    ex_Write_DCache_decode_cmb_inferred_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_Write_DCache_decode_reg),
        .I2(ex_write_dcache_instr),
        .O(in0));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'h10)) 
    ex_Write_ICache_i_cmb_inferred_i_1
       (.I0(\Using_FPGA.Native_0 ),
        .I1(ex_Write_DCache_decode_reg),
        .I2(ex_Write_ICache_i),
        .O(ex_Write_ICache_i_reg));
  LUT5 #(
    .INIT(32'h007F0000)) 
    \mem_pc_i[0]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(wb_exception),
        .I3(\mem_pc_i_reg[0] ),
        .I4(\Using_FPGA.Native_0 ),
        .O(\wb_exception_kind_i_reg[28] ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_108
   (of_PipeRun_carry_9,
    EX_MBAR_Stall__1,
    \Using_FPGA.Native_0 ,
    of_PipeRun_carry_10,
    ex_mbar_sleep,
    ex_mbar_decode,
    ex_first_cycle,
    ex_mbar_stall_no_sleep_1,
    ex_jump_hold,
    lopt,
    lopt_1);
  output of_PipeRun_carry_9;
  output EX_MBAR_Stall__1;
  input \Using_FPGA.Native_0 ;
  input of_PipeRun_carry_10;
  input ex_mbar_sleep;
  input ex_mbar_decode;
  input ex_first_cycle;
  input ex_mbar_stall_no_sleep_1;
  input ex_jump_hold;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire EX_MBAR_Stall__1;
  wire \Using_FPGA.Native_0 ;
  wire ex_first_cycle;
  wire ex_jump_hold;
  wire ex_mbar_decode;
  wire ex_mbar_sleep;
  wire ex_mbar_stall_no_sleep_1;
  wire of_PipeRun_carry_10;
  wire of_PipeRun_carry_9;

  assign lopt_1 = \<const0> ;
  assign of_PipeRun_carry_9 = lopt;
  GND GND
       (.G(\<const0> ));
  LUT5 #(
    .INIT(32'hAAAAEEEA)) 
    \Using_FPGA.Native_i_2__81 
       (.I0(ex_mbar_sleep),
        .I1(ex_mbar_decode),
        .I2(ex_first_cycle),
        .I3(ex_mbar_stall_no_sleep_1),
        .I4(ex_jump_hold),
        .O(EX_MBAR_Stall__1));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_109
   (of_PipeRun_carry_10,
    \Using_FPGA.Native_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output of_PipeRun_carry_10;
  input \Using_FPGA.Native_0 ;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire \<const0> ;
  wire \<const1> ;
  wire \Using_FPGA.Native_0 ;
  wire of_PipeRun_carry_10;

  assign lopt_1 = \<const0> ;
  assign lopt_2 = \<const1> ;
  assign of_PipeRun_carry_10 = lopt;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_110
   (of_pause_reg,
    ex_jump_nodelay_reg,
    of_read_imm_reg_ii_reg,
    wb_exception_i_reg,
    wb_exception_i_reg_0,
    of_PipeRun_carry_1,
    ex_jump_nodelay,
    ex_jump,
    ex_jump_nodelay_reg_0,
    IB_Ready,
    if_missed_fetch,
    of_read_imm_reg_ii,
    p_9_in,
    of_read_imm_reg_ii_reg_0,
    wb_exception,
    sync_reset,
    E,
    of_pause,
    lopt,
    lopt_1,
    lopt_2);
  output of_pause_reg;
  output ex_jump_nodelay_reg;
  output of_read_imm_reg_ii_reg;
  output wb_exception_i_reg;
  output wb_exception_i_reg_0;
  input of_PipeRun_carry_1;
  input ex_jump_nodelay;
  input ex_jump;
  input ex_jump_nodelay_reg_0;
  input IB_Ready;
  input if_missed_fetch;
  input of_read_imm_reg_ii;
  input p_9_in;
  input of_read_imm_reg_ii_reg_0;
  input wb_exception;
  input sync_reset;
  input [0:0]E;
  input of_pause;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire \<const0> ;
  wire [0:0]E;
  wire IB_Ready;
  wire \Using_FPGA.Native_i_1__46_n_0 ;
  wire ex_jump;
  wire ex_jump_nodelay;
  wire ex_jump_nodelay_reg;
  wire ex_jump_nodelay_reg_0;
  wire if_missed_fetch;
  wire of_PipeRun_carry_1;
  wire of_pause;
  wire of_pause_reg;
  wire of_read_imm_reg_ii;
  wire of_read_imm_reg_ii_reg;
  wire of_read_imm_reg_ii_reg_0;
  wire p_9_in;
  wire sync_reset;
  wire wb_exception;
  wire wb_exception_i_reg;
  wire wb_exception_i_reg_0;

  assign lopt_1 = \<const0> ;
  assign lopt_2 = \Using_FPGA.Native_i_1__46_n_0 ;
  assign of_pause_reg = lopt;
  GND GND
       (.G(\<const0> ));
  LUT1 #(
    .INIT(2'h1)) 
    \Using_FPGA.Native_i_1__46 
       (.I0(of_pause),
        .O(\Using_FPGA.Native_i_1__46_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'h02)) 
    ex_first_cycle_i_1
       (.I0(of_pause_reg),
        .I1(wb_exception),
        .I2(sync_reset),
        .O(wb_exception_i_reg_0));
  LUT6 #(
    .INIT(64'h0000226E226E226E)) 
    ex_jump_nodelay_i_1
       (.I0(ex_jump_nodelay),
        .I1(of_pause_reg),
        .I2(ex_jump),
        .I3(ex_jump_nodelay_reg_0),
        .I4(IB_Ready),
        .I5(if_missed_fetch),
        .O(ex_jump_nodelay_reg));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'hEFEE)) 
    ex_valid_i_1
       (.I0(wb_exception),
        .I1(sync_reset),
        .I2(of_pause_reg),
        .I3(E),
        .O(wb_exception_i_reg));
  LUT6 #(
    .INIT(64'h000000002EEE2222)) 
    of_read_imm_reg_ii_i_1
       (.I0(of_read_imm_reg_ii),
        .I1(of_pause_reg),
        .I2(ex_jump),
        .I3(ex_jump_nodelay),
        .I4(p_9_in),
        .I5(of_read_imm_reg_ii_reg_0),
        .O(of_read_imm_reg_ii_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_111
   (of_PipeRun_carry_1,
    use_Reg_Neg_S_reg,
    of_PipeRun_carry_2,
    lopt,
    lopt_1);
  output of_PipeRun_carry_1;
  input use_Reg_Neg_S_reg;
  input of_PipeRun_carry_2;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire of_PipeRun_carry_1;
  wire of_PipeRun_carry_2;
  wire use_Reg_Neg_S_reg;

  assign lopt_1 = \<const0> ;
  assign of_PipeRun_carry_1 = lopt;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_299
   (ex_pre_alu_carry,
    muxcy_sel,
    muxcy_di,
    \Using_FPGA.Native_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25);
  output ex_pre_alu_carry;
  input muxcy_sel;
  input muxcy_di;
  input \Using_FPGA.Native_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  input lopt_18;
  input lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;

  wire \Using_FPGA.Native_0 ;
  wire ex_pre_alu_carry;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire lopt_26;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire muxcy_di;
  wire muxcy_sel;
  wire [2:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;

  assign \^lopt_19  = lopt_18;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_20  = lopt_19;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_26 = lopt_25;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(\Using_FPGA.Native_0 ),
        .CI_TOP(1'b0),
        .CO({\^lopt_11 ,\^lopt_12 ,\^lopt_13 ,\^lopt_14 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,ex_pre_alu_carry}),
        .DI({\^lopt_19 ,\^lopt_20 ,\^lopt_21 ,\^lopt_22 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,muxcy_di}),
        .O({\^lopt_15 ,\^lopt_16 ,\^lopt_17 ,\^lopt_18 ,\^lopt_10 ,\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [2:0]}),
        .S({\^lopt_23 ,\^lopt_24 ,\^lopt_25 ,lopt_26,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,muxcy_sel}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_300
   (ex_alu_carryin,
    ex_pre_alu_carry,
    lopt,
    lopt_1,
    lopt_2);
  output ex_alu_carryin;
  input ex_pre_alu_carry;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire \<const0> ;
  wire \<const1> ;
  wire ex_alu_carryin;
  wire ex_pre_alu_carry;

  assign ex_alu_carryin = lopt;
  assign lopt_1 = \<const0> ;
  assign lopt_2 = \<const1> ;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_307
   (CI,
    \Using_FPGA.Native_I2 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output CI;
  input [0:0]\Using_FPGA.Native_I2 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire CI;
  wire [0:0]\Using_FPGA.Native_I2 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire [0:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,CI}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b0}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [0]}),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,\Using_FPGA.Native_I2 }));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_31
   (carry_6,
    SRL16_Sel_6,
    carry_7,
    lopt,
    lopt_1);
  output carry_6;
  input SRL16_Sel_6;
  input carry_7;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire SRL16_Sel_6;
  wire carry_6;
  wire carry_7;

  assign carry_6 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_33
   (carry_5,
    SRL16_Sel_5,
    carry_6,
    lopt,
    lopt_1);
  output carry_5;
  input SRL16_Sel_5;
  input carry_6;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire SRL16_Sel_5;
  wire carry_5;
  wire carry_6;

  assign carry_5 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_35
   (carry_4,
    SRL16_Sel_4,
    carry_5,
    lopt,
    lopt_1);
  output carry_4;
  input SRL16_Sel_4;
  input carry_5;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire SRL16_Sel_4;
  wire carry_4;
  wire carry_5;

  assign carry_4 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_37
   (carry_3,
    SRL16_Sel_3,
    carry_4,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13);
  output carry_3;
  input SRL16_Sel_3;
  input carry_4;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  input lopt_9;
  input lopt_10;
  input lopt_11;
  input lopt_12;
  output lopt_13;

  wire \<const0> ;
  wire SRL16_Sel_3;
  wire carry_3;
  wire carry_4;
  wire \^lopt_1 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_1  = lopt_11;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_10;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_9;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign carry_3 = lopt_12;
  assign lopt = \^lopt_1 ;
  assign lopt_13 = \<const0> ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_39
   (carry_2,
    SRL16_Sel_2,
    carry_3,
    lopt,
    lopt_1);
  output carry_2;
  input SRL16_Sel_2;
  input carry_3;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire SRL16_Sel_2;
  wire carry_2;
  wire carry_3;

  assign carry_2 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_402
   (zero_CI_6,
    ex_op1_cmp_equal,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15);
  output zero_CI_6;
  input ex_op1_cmp_equal;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  output lopt_5;
  input lopt_6;
  output lopt_7;
  output lopt_8;
  output lopt_9;
  output lopt_10;
  input lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;

  wire ex_op1_cmp_equal;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire lopt_16;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire zero_CI_6;
  wire [7:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;

  assign \^lopt_12  = lopt_11;
  assign \^lopt_13  = lopt_12;
  assign \^lopt_14  = lopt_13;
  assign \^lopt_15  = lopt_14;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_7  = lopt_6;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_16 = lopt_15;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_5 = \^lopt_6 ;
  assign lopt_7 = \^lopt_8 ;
  assign lopt_8 = \^lopt_9 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\^lopt_8 ,\^lopt_9 ,\^lopt_10 ,\^lopt_11 ,\^lopt_6 ,\^lopt_4 ,\^lopt_1 ,zero_CI_6}),
        .DI({\^lopt_12 ,\^lopt_2 ,\^lopt_2 ,\^lopt_2 ,\^lopt_2 ,\^lopt_2 ,\^lopt_2 ,1'b0}),
        .O(\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [7:0]),
        .S({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,lopt_16,\^lopt_7 ,\^lopt_5 ,\^lopt_3 ,ex_op1_cmp_equal}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_403
   (ex_op1_zero,
    \Using_FPGA.Native_0 ,
    ex_op1_cmp_equal_n,
    zero_CI_1,
    lopt);
  output ex_op1_zero;
  input \Using_FPGA.Native_0 ;
  input ex_op1_cmp_equal_n;
  input zero_CI_1;
  input lopt;

  wire \Using_FPGA.Native_0 ;
  wire ex_op1_cmp_equal_n;
  wire ex_op1_zero;
  wire zero_CI_1;

  assign ex_op1_zero = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_404
   (zero_CI_1,
    \Using_FPGA.Native_0 ,
    ex_op1_cmp_equal_n,
    zero_CI_2,
    lopt);
  output zero_CI_1;
  input \Using_FPGA.Native_0 ;
  input ex_op1_cmp_equal_n;
  input zero_CI_2;
  input lopt;

  wire \Using_FPGA.Native_0 ;
  wire ex_op1_cmp_equal_n;
  wire zero_CI_1;
  wire zero_CI_2;

  assign zero_CI_1 = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_405
   (zero_CI_2,
    \Using_FPGA.Native_0 ,
    ex_op1_cmp_equal_n,
    zero_CI_3,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10);
  output zero_CI_2;
  input \Using_FPGA.Native_0 ;
  input ex_op1_cmp_equal_n;
  input zero_CI_3;
  output lopt;
  input lopt_1;
  output lopt_2;
  input lopt_3;
  output lopt_4;
  input lopt_5;
  input lopt_6;
  input lopt_7;
  input lopt_8;
  input lopt_9;
  input lopt_10;

  wire \Using_FPGA.Native_0 ;
  wire ex_op1_cmp_equal_n;
  wire \^lopt_1 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire zero_CI_2;
  wire zero_CI_3;

  assign \^lopt_1  = lopt_9;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_8;
  assign \^lopt_4  = lopt_3;
  assign \^lopt_5  = lopt_7;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_6;
  assign lopt = \^lopt_1 ;
  assign lopt_2 = \^lopt_3 ;
  assign lopt_4 = \^lopt_5 ;
  assign zero_CI_2 = lopt_10;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_406
   (zero_CI_3,
    \Using_FPGA.Native_0 ,
    ex_op1_cmp_equal_n,
    zero_CI_4,
    lopt);
  output zero_CI_3;
  input \Using_FPGA.Native_0 ;
  input ex_op1_cmp_equal_n;
  input zero_CI_4;
  input lopt;

  wire \Using_FPGA.Native_0 ;
  wire ex_op1_cmp_equal_n;
  wire zero_CI_3;
  wire zero_CI_4;

  assign zero_CI_3 = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_407
   (zero_CI_4,
    \Using_FPGA.Native_0 ,
    ex_op1_cmp_equal_n,
    zero_CI_5,
    lopt);
  output zero_CI_4;
  input \Using_FPGA.Native_0 ;
  input ex_op1_cmp_equal_n;
  input zero_CI_5;
  input lopt;

  wire \Using_FPGA.Native_0 ;
  wire ex_op1_cmp_equal_n;
  wire zero_CI_4;
  wire zero_CI_5;

  assign zero_CI_4 = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_408
   (zero_CI_5,
    S,
    ex_op1_cmp_equal_n,
    zero_CI_6,
    lopt);
  output zero_CI_5;
  input S;
  input ex_op1_cmp_equal_n;
  input zero_CI_6;
  input lopt;

  wire S;
  wire ex_op1_cmp_equal_n;
  wire zero_CI_5;
  wire zero_CI_6;

  assign zero_CI_5 = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_41
   (carry_1,
    SRL16_Sel_1,
    carry_2,
    lopt,
    lopt_1);
  output carry_1;
  input SRL16_Sel_1;
  input carry_2;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire SRL16_Sel_1;
  wire carry_1;
  wire carry_2;

  assign carry_1 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_43
   (carry_0,
    SRL16_Sel_0,
    carry_1,
    lopt,
    lopt_1);
  output carry_0;
  input SRL16_Sel_0;
  input carry_1;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire SRL16_Sel_0;
  wire carry_0;
  wire carry_1;

  assign carry_0 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_45
   (Hit,
    single_Step_N_reg,
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ,
    carry_0,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ,
    Q,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ,
    force_stop_i,
    single_Step_N,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ,
    ex_Exception_Taken,
    mem_Exception_Taken,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 );
  output Hit;
  output single_Step_N_reg;
  output \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ;
  input carry_0;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ;
  input [0:0]Q;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ;
  input force_stop_i;
  input single_Step_N;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ;
  input ex_Exception_Taken;
  input mem_Exception_Taken;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 ;

  wire Hit;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_5_n_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ;
  wire [0:0]Q;
  wire carry_0;
  wire ex_Exception_Taken;
  wire force_stop_i;
  wire mem_Exception_Taken;
  wire p_45_out;
  wire single_Step_N;
  wire single_Step_N_reg;
  wire [7:1]\NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED ;
  wire [7:1]\NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED ;
  wire [7:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;
  wire [7:1]\NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFFFFDF55FFFF0000)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_1 
       (.I0(\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ),
        .I1(mem_Exception_Taken),
        .I2(ex_Exception_Taken),
        .I3(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ),
        .I4(p_45_out),
        .I5(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 ),
        .O(\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ));
  LUT6 #(
    .INIT(64'hFFFFFFEA00000000)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 
       (.I0(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg ),
        .I1(Q),
        .I2(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ),
        .I3(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ),
        .I4(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_5_n_0 ),
        .I5(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ),
        .O(p_45_out));
  LUT3 #(
    .INIT(8'hF4)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_5 
       (.I0(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 ),
        .I1(Hit),
        .I2(force_stop_i),
        .O(\Performance_Debug_Control.ex_dbg_pc_hit_i_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h55555555CCCC0CCC)) 
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_i_1 
       (.I0(single_Step_N),
        .I1(\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ),
        .I2(\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ),
        .I3(ex_Exception_Taken),
        .I4(mem_Exception_Taken),
        .I5(p_45_out),
        .O(single_Step_N_reg));
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(carry_0),
        .CI_TOP(1'b0),
        .CO({\NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED [7:1],Hit}),
        .DI({\NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED [7:1],1'b1}),
        .O(\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [7:0]),
        .S({\NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED [7:1],1'b1}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_488
   (CI,
    ex_use_carry,
    DI_0,
    ex_alu_carryin,
    lopt);
  output CI;
  input ex_use_carry;
  input DI_0;
  input ex_alu_carryin;
  input lopt;

  wire CI;
  wire DI_0;
  wire ex_alu_carryin;
  wire ex_use_carry;

  assign CI = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_581
   (CI,
    S,
    ex_unsigned_op,
    LO,
    lopt);
  output CI;
  input S;
  input ex_unsigned_op;
  input LO;
  input lopt;

  wire CI;
  wire LO;
  wire S;
  wire ex_unsigned_op;

  assign CI = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_90
   (mem_wait_on_ready_N,
    MEM_DataBus_Ready,
    mem_load_store_access,
    mem_Write_DCache,
    mem_valid_instr,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output mem_wait_on_ready_N;
  input MEM_DataBus_Ready;
  input mem_load_store_access;
  input mem_Write_DCache;
  input mem_valid_instr;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  input lopt_20;

  wire MEM_DataBus_Ready;
  wire \Using_FPGA.Native_i_1__97_n_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire lopt_21;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire mem_Write_DCache;
  wire mem_load_store_access;
  wire mem_valid_instr;
  wire mem_wait_on_ready_N;
  wire [7:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;

  assign \^lopt_14  = lopt_13;
  assign \^lopt_15  = lopt_14;
  assign \^lopt_16  = lopt_15;
  assign \^lopt_17  = lopt_16;
  assign \^lopt_18  = lopt_17;
  assign \^lopt_19  = lopt_18;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_20  = lopt_19;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_21 = lopt_20;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(MEM_DataBus_Ready),
        .CI_TOP(1'b0),
        .CO({\^lopt_10 ,\^lopt_11 ,\^lopt_12 ,\^lopt_13 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,mem_wait_on_ready_N}),
        .DI({\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_17 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b1}),
        .O(\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [7:0]),
        .S({\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,lopt_21,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,\Using_FPGA.Native_i_1__97_n_0 }));
  LUT3 #(
    .INIT(8'hE0)) 
    \Using_FPGA.Native_i_1__97 
       (.I0(mem_load_store_access),
        .I1(mem_Write_DCache),
        .I2(mem_valid_instr),
        .O(\Using_FPGA.Native_i_1__97_n_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_91
   (\Using_FPGA.Native_0 ,
    mem_valid_reg,
    wb_valid_reg,
    wb_gpr_write_dbg0,
    wb_gpr_write_i0,
    mem_wait_on_ready_N,
    mem_valid_instr,
    mem_exception_from_ex,
    mem_valid_reg_0,
    E,
    flush_pipe,
    wb_valid_reg_0,
    wb_valid_reg_1,
    sync_reset,
    wb_exception,
    mem_gpr_write_dbg,
    mem_gpr_write,
    lopt,
    lopt_1,
    lopt_2);
  output \Using_FPGA.Native_0 ;
  output mem_valid_reg;
  output wb_valid_reg;
  output wb_gpr_write_dbg0;
  output wb_gpr_write_i0;
  input mem_wait_on_ready_N;
  input mem_valid_instr;
  input mem_exception_from_ex;
  input mem_valid_reg_0;
  input [0:0]E;
  input flush_pipe;
  input wb_valid_reg_0;
  input [0:0]wb_valid_reg_1;
  input sync_reset;
  input wb_exception;
  input mem_gpr_write_dbg;
  input mem_gpr_write;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire \<const0> ;
  wire \<const1> ;
  wire [0:0]E;
  wire \Using_FPGA.Native_0 ;
  wire flush_pipe;
  wire mem_exception_from_ex;
  wire mem_gpr_write;
  wire mem_gpr_write_dbg;
  wire mem_valid_instr;
  wire mem_valid_reg;
  wire mem_valid_reg_0;
  wire mem_wait_on_ready_N;
  wire sync_reset;
  wire wb_exception;
  wire wb_gpr_write_dbg0;
  wire wb_gpr_write_i0;
  wire wb_valid_reg;
  wire wb_valid_reg_0;
  wire [0:0]wb_valid_reg_1;

  assign \Using_FPGA.Native_0  = lopt;
  assign lopt_1 = \<const0> ;
  assign lopt_2 = \<const1> ;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  LUT6 #(
    .INIT(64'h00000000707000AA)) 
    mem_valid_i_1
       (.I0(mem_valid_instr),
        .I1(mem_exception_from_ex),
        .I2(mem_valid_reg_0),
        .I3(\Using_FPGA.Native_0 ),
        .I4(E),
        .I5(flush_pipe),
        .O(mem_valid_reg));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    wb_gpr_write_dbg_i_1
       (.I0(sync_reset),
        .I1(wb_exception),
        .I2(\Using_FPGA.Native_0 ),
        .I3(mem_gpr_write_dbg),
        .O(wb_gpr_write_dbg0));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    wb_gpr_write_i_i_1
       (.I0(sync_reset),
        .I1(wb_exception),
        .I2(\Using_FPGA.Native_0 ),
        .I3(mem_gpr_write),
        .O(wb_gpr_write_i0));
  LUT5 #(
    .INIT(32'h0000CC0A)) 
    wb_valid_i_1
       (.I0(wb_valid_reg_0),
        .I1(mem_valid_instr),
        .I2(wb_valid_reg_1),
        .I3(\Using_FPGA.Native_0 ),
        .I4(sync_reset),
        .O(wb_valid_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_92
   (jump_carry1,
    S,
    DI,
    ex_op1_zero,
    lopt);
  output jump_carry1;
  input S;
  input DI;
  input ex_op1_zero;
  input lopt;

  wire DI;
  wire S;
  wire ex_op1_zero;
  wire jump_carry1;

  assign jump_carry1 = lopt;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_93
   (jump_carry2,
    jump_carry1,
    out,
    force_Val2_N,
    force2,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11);
  output jump_carry2;
  input jump_carry1;
  input out;
  input force_Val2_N;
  input force2;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  input lopt_10;
  input lopt_11;

  wire force2;
  wire force_DI2;
  wire force_Val2_N;
  wire force_jump2;
  wire jump_carry1;
  wire jump_carry2;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire lopt_12;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire out;
  wire [7:5]\NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED ;
  wire [7:5]\NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED ;
  wire [7:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;
  wire [7:5]\NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED ;

  assign \^lopt_11  = lopt_10;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_12 = lopt_11;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(jump_carry1),
        .CI_TOP(1'b0),
        .CO({\NLW_Using_FPGA.Native_CARRY4_CARRY8_CO_UNCONNECTED [7:5],\^lopt_10 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,jump_carry2}),
        .DI({\NLW_Using_FPGA.Native_CARRY4_CARRY8_DI_UNCONNECTED [7:5],\^lopt_11 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,force_DI2}),
        .O(\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [7:0]),
        .S({\NLW_Using_FPGA.Native_CARRY4_CARRY8_S_UNCONNECTED [7:5],lopt_12,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,force_jump2}));
  LUT2 #(
    .INIT(4'h8)) 
    \Using_FPGA.Native_i_1__1 
       (.I0(out),
        .I1(force2),
        .O(force_jump2));
  LUT2 #(
    .INIT(4'h2)) 
    \Using_FPGA.Native_i_2__20 
       (.I0(out),
        .I1(force_Val2_N),
        .O(force_DI2));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_94
   (ex_jump_wanted,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    jump_carry2,
    of_valid,
    ex_branch_with_delayslot,
    EX_MBAR_Stall__1,
    lopt,
    lopt_1);
  output ex_jump_wanted;
  output \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input jump_carry2;
  input of_valid;
  input ex_branch_with_delayslot;
  input EX_MBAR_Stall__1;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire EX_MBAR_Stall__1;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire ex_branch_with_delayslot;
  wire ex_jump_wanted;
  wire jump_carry2;
  wire of_valid;

  assign ex_jump_wanted = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
  LUT4 #(
    .INIT(16'h55DF)) 
    \Using_FPGA.Native_i_1__100 
       (.I0(ex_jump_wanted),
        .I1(of_valid),
        .I2(ex_branch_with_delayslot),
        .I3(EX_MBAR_Stall__1),
        .O(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_95
   (jump_carry4,
    \Using_FPGA.Native_0 ,
    ex_jump_wanted,
    lopt,
    lopt_1);
  output jump_carry4;
  input \Using_FPGA.Native_0 ;
  input ex_jump_wanted;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire \Using_FPGA.Native_0 ;
  wire ex_jump_wanted;
  wire jump_carry4;

  assign jump_carry4 = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_96
   (jump_carry5,
    jump_carry4,
    lopt,
    lopt_1,
    lopt_2);
  output jump_carry5;
  input jump_carry4;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire \<const0> ;
  wire \<const1> ;
  wire jump_carry4;
  wire jump_carry5;

  assign jump_carry5 = lopt;
  assign lopt_1 = \<const0> ;
  assign lopt_2 = \<const1> ;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_97
   (ex_jump_hold_reg,
    I5,
    of_next_ex_valid,
    ex_jump_hold_reg_0,
    ex_delayslot_Instr0,
    keep_jump_taken_with_ds_reg,
    mem_jump_taken0,
    \if_pc_reg[0] ,
    ex_jump_q_reg,
    jump_carry5,
    wb_exception,
    Q,
    ex_Exception_Taken,
    ex_jump_nodelay,
    of_valid,
    mem_exception_from_ex,
    mem_valid_instr,
    ex_jump_hold,
    E,
    sync_reset,
    keep_jump_taken_with_ds,
    ex_branch_with_delayslot,
    keep_jump_taken_with_ds_reg_0,
    ex_mbar_stall_no_sleep_1,
    ex_first_cycle,
    ex_mbar_decode,
    ex_mbar_sleep,
    ex_databus_addr,
    \if_pc_reg[30] ,
    \if_pc_reg[0]_0 ,
    O,
    \if_pc_reg[28] ,
    \if_pc_reg[27] ,
    \if_pc_reg[26] ,
    \if_pc_reg[25] ,
    \if_pc_reg[24] ,
    \if_pc_reg[23] ,
    \if_pc_reg[22] ,
    \if_pc_reg[21] ,
    \if_pc_reg[20] ,
    \if_pc_reg[19] ,
    \if_pc_reg[18] ,
    \if_pc_reg[17] ,
    \if_pc_reg[16] ,
    \if_pc_reg[15] ,
    \if_pc_reg[14] ,
    \if_pc_reg[13] ,
    \if_pc_reg[12] ,
    \if_pc_reg[11] ,
    \if_pc_reg[10] ,
    \if_pc_reg[9] ,
    \if_pc_reg[8] ,
    \if_pc_reg[7] ,
    \if_pc_reg[6] ,
    \if_pc_reg[5] ,
    \if_pc_reg[4] ,
    \if_pc_reg[3] ,
    \if_pc_reg[2] ,
    \if_pc_reg[1] ,
    O56_out,
    ex_jump_q,
    lopt,
    lopt_1,
    lopt_2);
  output ex_jump_hold_reg;
  output I5;
  output of_next_ex_valid;
  output ex_jump_hold_reg_0;
  output ex_delayslot_Instr0;
  output keep_jump_taken_with_ds_reg;
  output mem_jump_taken0;
  output [31:0]\if_pc_reg[0] ;
  output ex_jump_q_reg;
  input jump_carry5;
  input wb_exception;
  input [1:0]Q;
  input ex_Exception_Taken;
  input ex_jump_nodelay;
  input of_valid;
  input mem_exception_from_ex;
  input mem_valid_instr;
  input ex_jump_hold;
  input [0:0]E;
  input sync_reset;
  input keep_jump_taken_with_ds;
  input ex_branch_with_delayslot;
  input keep_jump_taken_with_ds_reg_0;
  input ex_mbar_stall_no_sleep_1;
  input ex_first_cycle;
  input ex_mbar_decode;
  input ex_mbar_sleep;
  input [1:0]ex_databus_addr;
  input [1:0]\if_pc_reg[30] ;
  input [29:0]\if_pc_reg[0]_0 ;
  input O;
  input \if_pc_reg[28] ;
  input \if_pc_reg[27] ;
  input \if_pc_reg[26] ;
  input \if_pc_reg[25] ;
  input \if_pc_reg[24] ;
  input \if_pc_reg[23] ;
  input \if_pc_reg[22] ;
  input \if_pc_reg[21] ;
  input \if_pc_reg[20] ;
  input \if_pc_reg[19] ;
  input \if_pc_reg[18] ;
  input \if_pc_reg[17] ;
  input \if_pc_reg[16] ;
  input \if_pc_reg[15] ;
  input \if_pc_reg[14] ;
  input \if_pc_reg[13] ;
  input \if_pc_reg[12] ;
  input \if_pc_reg[11] ;
  input \if_pc_reg[10] ;
  input \if_pc_reg[9] ;
  input \if_pc_reg[8] ;
  input \if_pc_reg[7] ;
  input \if_pc_reg[6] ;
  input \if_pc_reg[5] ;
  input \if_pc_reg[4] ;
  input \if_pc_reg[3] ;
  input \if_pc_reg[2] ;
  input \if_pc_reg[1] ;
  input O56_out;
  input ex_jump_q;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire \<const0> ;
  wire [0:0]E;
  wire I5;
  wire O;
  wire O56_out;
  wire [1:0]Q;
  wire \Using_FPGA.Native_i_1__44_n_0 ;
  wire ex_Exception_Taken;
  wire ex_branch_with_delayslot;
  wire [1:0]ex_databus_addr;
  wire ex_delayslot_Instr0;
  wire ex_first_cycle;
  wire ex_jump_hold;
  wire ex_jump_hold_reg;
  wire ex_jump_hold_reg_0;
  wire ex_jump_nodelay;
  wire ex_jump_q;
  wire ex_jump_q_reg;
  wire ex_mbar_decode;
  wire ex_mbar_sleep;
  wire ex_mbar_stall_no_sleep_1;
  wire [31:0]\if_pc_reg[0] ;
  wire [29:0]\if_pc_reg[0]_0 ;
  wire \if_pc_reg[10] ;
  wire \if_pc_reg[11] ;
  wire \if_pc_reg[12] ;
  wire \if_pc_reg[13] ;
  wire \if_pc_reg[14] ;
  wire \if_pc_reg[15] ;
  wire \if_pc_reg[16] ;
  wire \if_pc_reg[17] ;
  wire \if_pc_reg[18] ;
  wire \if_pc_reg[19] ;
  wire \if_pc_reg[1] ;
  wire \if_pc_reg[20] ;
  wire \if_pc_reg[21] ;
  wire \if_pc_reg[22] ;
  wire \if_pc_reg[23] ;
  wire \if_pc_reg[24] ;
  wire \if_pc_reg[25] ;
  wire \if_pc_reg[26] ;
  wire \if_pc_reg[27] ;
  wire \if_pc_reg[28] ;
  wire \if_pc_reg[2] ;
  wire [1:0]\if_pc_reg[30] ;
  wire \if_pc_reg[3] ;
  wire \if_pc_reg[4] ;
  wire \if_pc_reg[5] ;
  wire \if_pc_reg[6] ;
  wire \if_pc_reg[7] ;
  wire \if_pc_reg[8] ;
  wire \if_pc_reg[9] ;
  wire jump_carry5;
  wire keep_jump_taken_with_ds;
  wire keep_jump_taken_with_ds_reg;
  wire keep_jump_taken_with_ds_reg_0;
  wire mem_exception_from_ex;
  wire mem_jump_taken0;
  wire mem_valid_instr;
  wire of_next_ex_valid;
  wire of_valid;
  wire sync_reset;
  wire wb_exception;

  assign ex_jump_hold_reg = lopt;
  assign lopt_1 = \<const0> ;
  assign lopt_2 = \Using_FPGA.Native_i_1__44_n_0 ;
  GND GND
       (.G(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[0]_INST_0 
       (.I0(\if_pc_reg[0]_0 [29]),
        .I1(ex_jump_hold_reg),
        .I2(O56_out),
        .O(\if_pc_reg[0] [31]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[10]_INST_0 
       (.I0(\if_pc_reg[0]_0 [19]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[10] ),
        .O(\if_pc_reg[0] [21]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[11]_INST_0 
       (.I0(\if_pc_reg[0]_0 [18]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[11] ),
        .O(\if_pc_reg[0] [20]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[12]_INST_0 
       (.I0(\if_pc_reg[0]_0 [17]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[12] ),
        .O(\if_pc_reg[0] [19]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[13]_INST_0 
       (.I0(\if_pc_reg[0]_0 [16]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[13] ),
        .O(\if_pc_reg[0] [18]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[14]_INST_0 
       (.I0(\if_pc_reg[0]_0 [15]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[14] ),
        .O(\if_pc_reg[0] [17]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[15]_INST_0 
       (.I0(\if_pc_reg[0]_0 [14]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[15] ),
        .O(\if_pc_reg[0] [16]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[16]_INST_0 
       (.I0(\if_pc_reg[0]_0 [13]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[16] ),
        .O(\if_pc_reg[0] [15]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[17]_INST_0 
       (.I0(\if_pc_reg[0]_0 [12]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[17] ),
        .O(\if_pc_reg[0] [14]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[18]_INST_0 
       (.I0(\if_pc_reg[0]_0 [11]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[18] ),
        .O(\if_pc_reg[0] [13]));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[19]_INST_0 
       (.I0(\if_pc_reg[0]_0 [10]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[19] ),
        .O(\if_pc_reg[0] [12]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[1]_INST_0 
       (.I0(\if_pc_reg[0]_0 [28]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[1] ),
        .O(\if_pc_reg[0] [30]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[20]_INST_0 
       (.I0(\if_pc_reg[0]_0 [9]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[20] ),
        .O(\if_pc_reg[0] [11]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[21]_INST_0 
       (.I0(\if_pc_reg[0]_0 [8]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[21] ),
        .O(\if_pc_reg[0] [10]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[22]_INST_0 
       (.I0(\if_pc_reg[0]_0 [7]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[22] ),
        .O(\if_pc_reg[0] [9]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[23]_INST_0 
       (.I0(\if_pc_reg[0]_0 [6]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[23] ),
        .O(\if_pc_reg[0] [8]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[24]_INST_0 
       (.I0(\if_pc_reg[0]_0 [5]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[24] ),
        .O(\if_pc_reg[0] [7]));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[25]_INST_0 
       (.I0(\if_pc_reg[0]_0 [4]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[25] ),
        .O(\if_pc_reg[0] [6]));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[26]_INST_0 
       (.I0(\if_pc_reg[0]_0 [3]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[26] ),
        .O(\if_pc_reg[0] [5]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[27]_INST_0 
       (.I0(\if_pc_reg[0]_0 [2]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[27] ),
        .O(\if_pc_reg[0] [4]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[28]_INST_0 
       (.I0(\if_pc_reg[0]_0 [1]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[28] ),
        .O(\if_pc_reg[0] [3]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[29]_INST_0 
       (.I0(\if_pc_reg[0]_0 [0]),
        .I1(ex_jump_hold_reg),
        .I2(O),
        .O(\if_pc_reg[0] [2]));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[2]_INST_0 
       (.I0(\if_pc_reg[0]_0 [27]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[2] ),
        .O(\if_pc_reg[0] [29]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[30]_INST_0 
       (.I0(ex_databus_addr[1]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[30] [1]),
        .O(\if_pc_reg[0] [1]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[31]_INST_0 
       (.I0(ex_databus_addr[0]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[30] [0]),
        .O(\if_pc_reg[0] [0]));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[3]_INST_0 
       (.I0(\if_pc_reg[0]_0 [26]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[3] ),
        .O(\if_pc_reg[0] [28]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[4]_INST_0 
       (.I0(\if_pc_reg[0]_0 [25]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[4] ),
        .O(\if_pc_reg[0] [27]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[5]_INST_0 
       (.I0(\if_pc_reg[0]_0 [24]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[5] ),
        .O(\if_pc_reg[0] [26]));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[6]_INST_0 
       (.I0(\if_pc_reg[0]_0 [23]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[6] ),
        .O(\if_pc_reg[0] [25]));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[7]_INST_0 
       (.I0(\if_pc_reg[0]_0 [22]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[7] ),
        .O(\if_pc_reg[0] [24]));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[8]_INST_0 
       (.I0(\if_pc_reg[0]_0 [21]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[8] ),
        .O(\if_pc_reg[0] [23]));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \Instr_Addr[9]_INST_0 
       (.I0(\if_pc_reg[0]_0 [20]),
        .I1(ex_jump_hold_reg),
        .I2(\if_pc_reg[9] ),
        .O(\if_pc_reg[0] [22]));
  LUT5 #(
    .INIT(32'h0000ABFF)) 
    \Using_FPGA.Native_i_1__44 
       (.I0(ex_jump_hold),
        .I1(ex_mbar_stall_no_sleep_1),
        .I2(ex_first_cycle),
        .I3(ex_mbar_decode),
        .I4(ex_mbar_sleep),
        .O(\Using_FPGA.Native_i_1__44_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    \Using_FPGA.Native_i_2 
       (.I0(ex_jump_hold_reg),
        .I1(wb_exception),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(I5));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    ex_delayslot_Instr_i_1
       (.I0(keep_jump_taken_with_ds),
        .I1(ex_branch_with_delayslot),
        .I2(ex_jump_hold_reg),
        .O(ex_delayslot_Instr0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT4 #(
    .INIT(16'h000E)) 
    ex_jump_hold_i_1
       (.I0(ex_jump_hold),
        .I1(ex_jump_hold_reg),
        .I2(E),
        .I3(sync_reset),
        .O(ex_jump_hold_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'h0E)) 
    ex_jump_q_i_1
       (.I0(ex_jump_q),
        .I1(ex_jump_hold_reg),
        .I2(E),
        .O(ex_jump_q_reg));
  LUT6 #(
    .INIT(64'h0000150015001500)) 
    ex_valid_i_2
       (.I0(ex_Exception_Taken),
        .I1(ex_jump_hold_reg),
        .I2(ex_jump_nodelay),
        .I3(of_valid),
        .I4(mem_exception_from_ex),
        .I5(mem_valid_instr),
        .O(of_next_ex_valid));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT5 #(
    .INIT(32'h000000EA)) 
    keep_jump_taken_with_ds_i_1
       (.I0(keep_jump_taken_with_ds),
        .I1(ex_jump_hold_reg),
        .I2(ex_branch_with_delayslot),
        .I3(sync_reset),
        .I4(keep_jump_taken_with_ds_reg_0),
        .O(keep_jump_taken_with_ds_reg));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT2 #(
    .INIT(4'hE)) 
    mem_jump_taken_i_1
       (.I0(ex_jump_hold),
        .I1(ex_jump_hold_reg),
        .O(mem_jump_taken0));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_98
   (CI,
    if_fetch_for_timing_optimization1,
    if_pc_incr_carry1,
    lopt,
    lopt_1);
  output CI;
  input if_fetch_for_timing_optimization1;
  input if_pc_incr_carry1;
  input lopt;
  output lopt_1;

  wire \<const0> ;
  wire CI;
  wire if_fetch_for_timing_optimization1;
  wire if_pc_incr_carry1;

  assign CI = lopt;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_99
   (if_pc_incr_carry0,
    if_missed_fetch,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25);
  output if_pc_incr_carry0;
  input if_missed_fetch;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  input lopt_18;
  input lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;

  wire if_missed_fetch;
  wire if_pc_incr_carry0;
  wire if_valid;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire lopt_26;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire [2:0]\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED ;

  assign \^lopt_19  = lopt_18;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_20  = lopt_19;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_26 = lopt_25;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_CARRY4_CARRY8 
       (.CI(1'b1),
        .CI_TOP(1'b0),
        .CO({\^lopt_11 ,\^lopt_12 ,\^lopt_13 ,\^lopt_14 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,if_pc_incr_carry0}),
        .DI({\^lopt_19 ,\^lopt_20 ,\^lopt_21 ,\^lopt_22 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b0}),
        .O({\^lopt_15 ,\^lopt_16 ,\^lopt_17 ,\^lopt_18 ,\^lopt_10 ,\NLW_Using_FPGA.Native_CARRY4_CARRY8_O_UNCONNECTED [2:0]}),
        .S({\^lopt_23 ,\^lopt_24 ,\^lopt_25 ,lopt_26,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,if_valid}));
  LUT1 #(
    .INIT(2'h1)) 
    \Using_FPGA.Native_i_1__45 
       (.I0(if_missed_fetch),
        .O(if_valid));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY
   (O56_out,
    Q,
    LO);
  output O56_out;
  input [0:0]Q;
  input LO;

  wire LO;
  wire O56_out;
  wire [0:0]Q;
  wire [7:0]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED ;
  wire [7:0]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED ;
  wire [7:1]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED ;
  wire [7:1]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED ;

  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I2_CARRY4_CARRY8 
       (.CI(LO),
        .CI_TOP(1'b0),
        .CO(\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED [7:0]),
        .DI(\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED [7:0]),
        .O({\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED [7:1],O56_out}),
        .S({\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED [7:1],Q}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_270
   (LO,
    \if_pc_reg[10] ,
    Q,
    \if_pc_reg[10]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[10] ;
  input [0:0]Q;
  input \if_pc_reg[10]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[10] ;
  wire \if_pc_reg[10]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[10]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_271
   (LO,
    \if_pc_reg[11] ,
    Q,
    \if_pc_reg[11]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[11] ;
  input [0:0]Q;
  input \if_pc_reg[11]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[11] ;
  wire \if_pc_reg[11]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[11]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_272
   (LO,
    \if_pc_reg[12] ,
    Q,
    \if_pc_reg[12]_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output LO;
  output \if_pc_reg[12] ;
  input [0:0]Q;
  input \if_pc_reg[12]_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[12] ;
  wire \if_pc_reg[12]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign LO = lopt_15;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign \if_pc_reg[12]  = lopt_19;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_20 = \<const0> ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_273
   (LO,
    \if_pc_reg[13] ,
    Q,
    \if_pc_reg[13]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[13] ;
  input [0:0]Q;
  input \if_pc_reg[13]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[13] ;
  wire \if_pc_reg[13]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[13]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_274
   (LO,
    \if_pc_reg[14] ,
    Q,
    \if_pc_reg[14]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[14] ;
  input [0:0]Q;
  input \if_pc_reg[14]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[14] ;
  wire \if_pc_reg[14]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[14]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_275
   (LO,
    \if_pc_reg[15] ,
    Q,
    \if_pc_reg[15]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[15] ;
  input [0:0]Q;
  input \if_pc_reg[15]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[15] ;
  wire \if_pc_reg[15]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[15]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_276
   (LO,
    \if_pc_reg[16] ,
    Q,
    \if_pc_reg[16]_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output LO;
  output \if_pc_reg[16] ;
  input [0:0]Q;
  input \if_pc_reg[16]_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[16] ;
  wire \if_pc_reg[16]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(\if_pc_reg[16]_0 ),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,LO}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b0}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\if_pc_reg[16] }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,Q}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_277
   (LO,
    \if_pc_reg[17] ,
    Q,
    \if_pc_reg[17]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[17] ;
  input [0:0]Q;
  input \if_pc_reg[17]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[17] ;
  wire \if_pc_reg[17]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[17]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_278
   (LO,
    \if_pc_reg[18] ,
    Q,
    \if_pc_reg[18]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[18] ;
  input [0:0]Q;
  input \if_pc_reg[18]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[18] ;
  wire \if_pc_reg[18]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[18]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_279
   (LO,
    \if_pc_reg[19] ,
    Q,
    \if_pc_reg[19]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[19] ;
  input [0:0]Q;
  input \if_pc_reg[19]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[19] ;
  wire \if_pc_reg[19]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[19]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_280
   (LO,
    \if_pc_reg[1] ,
    Q,
    \if_pc_reg[1]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[1] ;
  input [0:0]Q;
  input \if_pc_reg[1]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[1] ;
  wire \if_pc_reg[1]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[1]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_281
   (LO,
    \if_pc_reg[20] ,
    Q,
    \if_pc_reg[20]_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output LO;
  output \if_pc_reg[20] ;
  input [0:0]Q;
  input \if_pc_reg[20]_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[20] ;
  wire \if_pc_reg[20]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign LO = lopt_15;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign \if_pc_reg[20]  = lopt_19;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_20 = \<const0> ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_282
   (LO,
    \if_pc_reg[21] ,
    Q,
    \if_pc_reg[21]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[21] ;
  input [0:0]Q;
  input \if_pc_reg[21]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[21] ;
  wire \if_pc_reg[21]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[21]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_283
   (LO,
    \if_pc_reg[22] ,
    Q,
    \if_pc_reg[22]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[22] ;
  input [0:0]Q;
  input \if_pc_reg[22]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[22] ;
  wire \if_pc_reg[22]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[22]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_284
   (LO,
    \if_pc_reg[23] ,
    Q,
    \if_pc_reg[23]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[23] ;
  input [0:0]Q;
  input \if_pc_reg[23]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[23] ;
  wire \if_pc_reg[23]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[23]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_285
   (LO,
    \if_pc_reg[24] ,
    Q,
    \if_pc_reg[24]_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output LO;
  output \if_pc_reg[24] ;
  input [0:0]Q;
  input \if_pc_reg[24]_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[24] ;
  wire \if_pc_reg[24]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(\if_pc_reg[24]_0 ),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,LO}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b0}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\if_pc_reg[24] }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,Q}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_286
   (LO,
    \if_pc_reg[25] ,
    Q,
    \if_pc_reg[25]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[25] ;
  input [0:0]Q;
  input \if_pc_reg[25]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[25] ;
  wire \if_pc_reg[25]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[25]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_287
   (LO,
    \if_pc_reg[26] ,
    Q,
    \if_pc_reg[26]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[26] ;
  input [0:0]Q;
  input \if_pc_reg[26]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[26] ;
  wire \if_pc_reg[26]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[26]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_288
   (LO,
    \if_pc_reg[27] ,
    Q,
    \if_pc_reg[27]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[27] ;
  input [0:0]Q;
  input \if_pc_reg[27]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[27] ;
  wire \if_pc_reg[27]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[27]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_289
   (LO,
    \if_pc_reg[28] ,
    Q,
    \if_pc_reg[28]_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output LO;
  output \if_pc_reg[28] ;
  input [0:0]Q;
  input \if_pc_reg[28]_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[28] ;
  wire \if_pc_reg[28]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign LO = lopt_15;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign \if_pc_reg[28]  = lopt_19;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_20 = \<const0> ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_290
   (LO,
    O,
    Q,
    CI,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output O;
  input [0:0]Q;
  input CI;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire CI;
  wire LO;
  wire O;
  wire [0:0]Q;

  assign LO = lopt;
  assign O = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_291
   (LO,
    \if_pc_reg[2] ,
    Q,
    \if_pc_reg[2]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[2] ;
  input [0:0]Q;
  input \if_pc_reg[2]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[2] ;
  wire \if_pc_reg[2]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[2]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_292
   (LO,
    \if_pc_reg[3] ,
    Q,
    \if_pc_reg[3]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[3] ;
  input [0:0]Q;
  input \if_pc_reg[3]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[3] ;
  wire \if_pc_reg[3]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[3]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_293
   (LO,
    \if_pc_reg[4] ,
    Q,
    \if_pc_reg[4]_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output LO;
  output \if_pc_reg[4] ;
  input [0:0]Q;
  input \if_pc_reg[4]_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  output lopt_20;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[4] ;
  wire \if_pc_reg[4]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign LO = lopt_15;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign \if_pc_reg[4]  = lopt_19;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_20 = \<const0> ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_294
   (LO,
    \if_pc_reg[5] ,
    Q,
    \if_pc_reg[5]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[5] ;
  input [0:0]Q;
  input \if_pc_reg[5]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[5] ;
  wire \if_pc_reg[5]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[5]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_295
   (LO,
    \if_pc_reg[6] ,
    Q,
    \if_pc_reg[6]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[6] ;
  input [0:0]Q;
  input \if_pc_reg[6]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[6] ;
  wire \if_pc_reg[6]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[6]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_296
   (LO,
    \if_pc_reg[7] ,
    Q,
    \if_pc_reg[7]_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[7] ;
  input [0:0]Q;
  input \if_pc_reg[7]_0 ;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[7] ;
  wire \if_pc_reg[7]_0 ;

  assign LO = lopt;
  assign \if_pc_reg[7]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_297
   (LO,
    \if_pc_reg[8] ,
    Q,
    \if_pc_reg[8]_0 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output LO;
  output \if_pc_reg[8] ;
  input [0:0]Q;
  input \if_pc_reg[8]_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[8] ;
  wire \if_pc_reg[8]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(\if_pc_reg[8]_0 ),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,LO}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,1'b0}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\if_pc_reg[8] }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,Q}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_298
   (LO,
    \if_pc_reg[9] ,
    Q,
    CI,
    lopt,
    lopt_1,
    lopt_2);
  output LO;
  output \if_pc_reg[9] ;
  input [0:0]Q;
  input CI;
  input lopt;
  output lopt_1;
  input lopt_2;

  wire \<const0> ;
  wire CI;
  wire LO;
  wire [0:0]Q;
  wire \if_pc_reg[9] ;

  assign LO = lopt;
  assign \if_pc_reg[9]  = lopt_2;
  assign lopt_1 = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_308
   (\Using_FPGA.Native ,
    addr_AddSub_31,
    LO);
  output [0:0]\Using_FPGA.Native ;
  input addr_AddSub_31;
  input LO;

  wire LO;
  wire [0:0]\Using_FPGA.Native ;
  wire addr_AddSub_31;
  wire [7:0]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED ;
  wire [7:0]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED ;
  wire [7:1]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED ;
  wire [7:1]\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED ;

  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I2_CARRY4_CARRY8 
       (.CI(LO),
        .CI_TOP(1'b0),
        .CO(\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_CO_UNCONNECTED [7:0]),
        .DI(\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_DI_UNCONNECTED [7:0]),
        .O({\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_O_UNCONNECTED [7:1],\Using_FPGA.Native }),
        .S({\NLW_Using_FPGA.Native_I2_CARRY4_CARRY8_S_UNCONNECTED [7:1],addr_AddSub_31}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_310
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3017] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3017] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3017] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_313
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3018] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3018] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3018] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_316
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3019] ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3019] ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire LO;
  wire \LOCKSTEP_Out_reg[3019] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign LO = lopt_15;
  assign \Using_FPGA.Native  = lopt_19;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_319
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3020] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3020] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3020] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_322
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3021] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3021] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3021] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_325
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3022] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3022] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3022] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_328
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[16] ,
    DI,
    \data_rd_reg_reg[16]_0 ,
    \LOCKSTEP_Out_reg[3023] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3023]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3023]_1 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[16] ;
  input DI;
  input \data_rd_reg_reg[16]_0 ;
  input \LOCKSTEP_Out_reg[3023] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3023]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3023]_1 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3023] ;
  wire \LOCKSTEP_Out_reg[3023]_0 ;
  wire \LOCKSTEP_Out_reg[3023]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[16] ;
  wire \data_rd_reg_reg[16]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire wb_byte_access;
  wire [16:16]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[16]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3023] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3023]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(\LOCKSTEP_Out_reg[3023]_1 ),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,LO}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,DI}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,wb_excep_return_addr}),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,S}));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[16]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[16] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[16]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_331
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[17] ,
    DI,
    \data_rd_reg_reg[17]_0 ,
    \LOCKSTEP_Out_reg[3024] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3024]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3024]_1 ,
    lopt,
    lopt_1);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[17] ;
  input DI;
  input \data_rd_reg_reg[17]_0 ;
  input \LOCKSTEP_Out_reg[3024] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3024]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3024]_1 ;
  input lopt;
  input lopt_1;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3024] ;
  wire \LOCKSTEP_Out_reg[3024]_0 ;
  wire \LOCKSTEP_Out_reg[3024]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[17] ;
  wire \data_rd_reg_reg[17]_0 ;
  wire wb_byte_access;
  wire [17:17]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign LO = lopt;
  assign wb_excep_return_addr = lopt_1;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[17]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3024] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3024]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[17]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[17] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[17]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_334
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[18] ,
    DI,
    \data_rd_reg_reg[18]_0 ,
    \LOCKSTEP_Out_reg[3025] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3025]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3025]_1 ,
    lopt,
    lopt_1);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[18] ;
  input DI;
  input \data_rd_reg_reg[18]_0 ;
  input \LOCKSTEP_Out_reg[3025] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3025]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3025]_1 ;
  input lopt;
  input lopt_1;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3025] ;
  wire \LOCKSTEP_Out_reg[3025]_0 ;
  wire \LOCKSTEP_Out_reg[3025]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[18] ;
  wire \data_rd_reg_reg[18]_0 ;
  wire wb_byte_access;
  wire [18:18]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign LO = lopt;
  assign wb_excep_return_addr = lopt_1;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[18]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3025] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3025]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[18]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[18] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[18]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_337
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[19] ,
    DI,
    \data_rd_reg_reg[19]_0 ,
    \LOCKSTEP_Out_reg[3026] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3026]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3026]_1 ,
    lopt,
    lopt_1);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[19] ;
  input DI;
  input \data_rd_reg_reg[19]_0 ;
  input \LOCKSTEP_Out_reg[3026] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3026]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3026]_1 ;
  input lopt;
  input lopt_1;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3026] ;
  wire \LOCKSTEP_Out_reg[3026]_0 ;
  wire \LOCKSTEP_Out_reg[3026]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[19] ;
  wire \data_rd_reg_reg[19]_0 ;
  wire wb_byte_access;
  wire [19:19]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign LO = lopt;
  assign wb_excep_return_addr = lopt_1;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[19]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3026] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3026]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[19]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[19] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[19]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_340
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3008] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3008] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3008] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_343
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[20] ,
    DI,
    \data_rd_reg_reg[20]_0 ,
    \LOCKSTEP_Out_reg[3027] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3027]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3027]_1 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[20] ;
  input DI;
  input \data_rd_reg_reg[20]_0 ;
  input \LOCKSTEP_Out_reg[3027] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3027]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3027]_1 ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3027] ;
  wire \LOCKSTEP_Out_reg[3027]_0 ;
  wire \LOCKSTEP_Out_reg[3027]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[20] ;
  wire \data_rd_reg_reg[20]_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire wb_byte_access;
  wire [20:20]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign LO = lopt_15;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  assign wb_excep_return_addr = lopt_19;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[20]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3027] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3027]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[20]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[20] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[20]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_346
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[21] ,
    DI,
    \data_rd_reg_reg[21]_0 ,
    \LOCKSTEP_Out_reg[3028] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3028]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3028]_1 ,
    lopt,
    lopt_1);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[21] ;
  input DI;
  input \data_rd_reg_reg[21]_0 ;
  input \LOCKSTEP_Out_reg[3028] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3028]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3028]_1 ;
  input lopt;
  input lopt_1;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3028] ;
  wire \LOCKSTEP_Out_reg[3028]_0 ;
  wire \LOCKSTEP_Out_reg[3028]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[21] ;
  wire \data_rd_reg_reg[21]_0 ;
  wire wb_byte_access;
  wire [21:21]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign LO = lopt;
  assign wb_excep_return_addr = lopt_1;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[21]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3028] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3028]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[21]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[21] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[21]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_349
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[22] ,
    DI,
    \data_rd_reg_reg[22]_0 ,
    \LOCKSTEP_Out_reg[3029] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3029]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3029]_1 ,
    lopt,
    lopt_1);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[22] ;
  input DI;
  input \data_rd_reg_reg[22]_0 ;
  input \LOCKSTEP_Out_reg[3029] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3029]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3029]_1 ;
  input lopt;
  input lopt_1;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3029] ;
  wire \LOCKSTEP_Out_reg[3029]_0 ;
  wire \LOCKSTEP_Out_reg[3029]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[22] ;
  wire \data_rd_reg_reg[22]_0 ;
  wire wb_byte_access;
  wire [22:22]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign LO = lopt;
  assign wb_excep_return_addr = lopt_1;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[22]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3029] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3029]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[22]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[22] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[22]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_352
   (wb_gpr_write_dbg_reg,
    WB_Byte_Access_reg,
    LO,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[23] ,
    DI,
    \data_rd_reg_reg[23]_0 ,
    \LOCKSTEP_Out_reg[3030] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3030]_0 ,
    Q,
    S,
    \LOCKSTEP_Out_reg[3030]_1 ,
    lopt,
    lopt_1);
  output [0:0]wb_gpr_write_dbg_reg;
  output [0:0]WB_Byte_Access_reg;
  output LO;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[23] ;
  input DI;
  input \data_rd_reg_reg[23]_0 ;
  input \LOCKSTEP_Out_reg[3030] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3030]_0 ;
  input [0:0]Q;
  input S;
  input \LOCKSTEP_Out_reg[3030]_1 ;
  input lopt;
  input lopt_1;

  wire DI;
  wire LO;
  wire \LOCKSTEP_Out_reg[3030] ;
  wire \LOCKSTEP_Out_reg[3030]_0 ;
  wire \LOCKSTEP_Out_reg[3030]_1 ;
  wire [0:0]Q;
  wire S;
  wire [0:0]WB_Byte_Access_reg;
  wire \data_rd_reg_reg[23] ;
  wire \data_rd_reg_reg[23]_0 ;
  wire wb_byte_access;
  wire [23:23]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:0]wb_gpr_write_dbg_reg;

  assign LO = lopt;
  assign wb_excep_return_addr = lopt_1;
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \Trace_New_Reg_Value[23]_INST_0 
       (.I0(wb_excep_return_addr),
        .I1(\LOCKSTEP_Out_reg[3030] ),
        .I2(wb_byte_access),
        .I3(\LOCKSTEP_Out_reg[3030]_0 ),
        .I4(Q),
        .O(WB_Byte_Access_reg));
  LUT5 #(
    .INIT(32'h8080BF80)) 
    \data_rd_reg[23]_i_1 
       (.I0(WB_Byte_Access_reg),
        .I1(wb_gpr_wr_dbg),
        .I2(\data_rd_reg_reg[23] ),
        .I3(DI),
        .I4(\data_rd_reg_reg[23]_0 ),
        .O(wb_gpr_write_dbg_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_355
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3031] ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3031] ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire LO;
  wire \LOCKSTEP_Out_reg[3031] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(\LOCKSTEP_Out_reg[3031] ),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,LO}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,\Using_FPGA.Native_I2_0 }),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\Using_FPGA.Native }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,S}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_358
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3032] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3032] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3032] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_361
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3033] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3033] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3033] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_364
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3034] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3034] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3034] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_367
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3035] ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3035] ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire LO;
  wire \LOCKSTEP_Out_reg[3035] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign LO = lopt_15;
  assign \Using_FPGA.Native  = lopt_19;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_370
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3036] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3036] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3036] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_373
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3009] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3009] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3009] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_376
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3037] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3037] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3037] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_379
   (LO,
    \Using_FPGA.Native ,
    S,
    DI,
    CI,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input DI;
  input CI;
  input lopt;
  input lopt_1;

  wire CI;
  wire DI;
  wire LO;
  wire S;
  wire [0:0]\Using_FPGA.Native ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_382
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3010] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3010] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3010] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_385
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3011] ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3011] ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire LO;
  wire \LOCKSTEP_Out_reg[3011] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign LO = lopt_15;
  assign \Using_FPGA.Native  = lopt_19;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_388
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3012] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3012] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3012] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_391
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3013] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3013] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3013] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_394
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3014] ,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3014] ;
  input lopt;
  input lopt_1;

  wire LO;
  wire \LOCKSTEP_Out_reg[3014] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_397
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    \LOCKSTEP_Out_reg[3015] ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input \LOCKSTEP_Out_reg[3015] ;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire LO;
  wire \LOCKSTEP_Out_reg[3015] ;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(\LOCKSTEP_Out_reg[3015] ),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,LO}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,\Using_FPGA.Native_I2_0 }),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\Using_FPGA.Native }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,S}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_400
   (LO,
    \Using_FPGA.Native ,
    S,
    \Using_FPGA.Native_I2_0 ,
    CI,
    lopt,
    lopt_1);
  output LO;
  output [0:0]\Using_FPGA.Native ;
  input S;
  input \Using_FPGA.Native_I2_0 ;
  input CI;
  input lopt;
  input lopt_1;

  wire CI;
  wire LO;
  wire S;
  wire [0:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_I2_0 ;

  assign LO = lopt;
  assign \Using_FPGA.Native  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_519
   (EX_CarryOut,
    \EX_Op2_reg[9] ,
    S,
    DI,
    EX_CarryIn,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[9] ;
  input S;
  input DI;
  input EX_CarryIn;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryIn;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[9] ;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[9]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_521
   (EX_CarryOut,
    \EX_Op2_reg[8] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[8] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[8] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[8]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_523
   (EX_CarryOut,
    \EX_Op2_reg[7] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[7] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[7] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[7]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_525
   (EX_CarryOut,
    \EX_Op2_reg[6] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[6] ;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[6] ;
  wire LO;
  wire S;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign EX_CarryOut = lopt_15;
  assign \EX_Op2_reg[6]  = lopt_19;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_527
   (EX_CarryOut,
    \EX_Op2_reg[5] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[5] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[5] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[5]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_529
   (EX_CarryOut,
    \EX_Op2_reg[4] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[4] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[4] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[4]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_531
   (EX_CarryOut,
    \EX_Op2_reg[3] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[3] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[3] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[3]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_533
   (EX_CarryOut,
    ex_databus_addr,
    S,
    DI,
    EX_CarryIn,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]ex_databus_addr;
  input S;
  input DI;
  input EX_CarryIn;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryIn;
  wire EX_CarryOut;
  wire S;
  wire [0:0]ex_databus_addr;

  assign EX_CarryOut = lopt;
  assign ex_databus_addr = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_535
   (EX_CarryOut,
    ex_databus_addr,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output EX_CarryOut;
  output [0:0]ex_databus_addr;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire DI;
  wire EX_CarryOut;
  wire LO;
  wire S;
  wire [0:0]ex_databus_addr;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign EX_CarryOut = lopt_15;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign ex_databus_addr = lopt_19;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_537
   (EX_CarryOut,
    \EX_Op2_reg[2] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[2] ;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[2] ;
  wire LO;
  wire S;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire lopt_11;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;
  wire [7:4]\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_CO_UNCONNECTED ;
  wire [7:4]\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_DI_UNCONNECTED ;
  wire [7:2]\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_O_UNCONNECTED ;
  wire [7:4]\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_S_UNCONNECTED ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = lopt_11;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(LO),
        .CI_TOP(1'b0),
        .CO({\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_CO_UNCONNECTED [7:4],\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,EX_CarryOut}),
        .DI({\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_DI_UNCONNECTED [7:4],\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,DI}),
        .O({\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_O_UNCONNECTED [7:4],lopt_11,\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_O_UNCONNECTED [2],\^lopt_10 ,\EX_Op2_reg[2] }),
        .S({\NLW_Using_FPGA.Native_I1_CARRY4_CARRY8_S_UNCONNECTED [7:4],\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,S}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_539
   (EX_CarryOut,
    \EX_Op2_reg[29] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[29] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[29] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[29]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_541
   (EX_CarryOut,
    \EX_Op2_reg[28] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[28] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[28] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[28]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_543
   (EX_CarryOut,
    \EX_Op2_reg[27] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[27] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[27] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[27]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_545
   (EX_CarryOut,
    \EX_Op2_reg[26] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[26] ;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[26] ;
  wire LO;
  wire S;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(LO),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,EX_CarryOut}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,DI}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\EX_Op2_reg[26] }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,S}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_547
   (EX_CarryOut,
    \EX_Op2_reg[25] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[25] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[25] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[25]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_549
   (EX_CarryOut,
    \EX_Op2_reg[24] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[24] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[24] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[24]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_551
   (EX_CarryOut,
    \EX_Op2_reg[23] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[23] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[23] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[23]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_553
   (EX_CarryOut,
    \EX_Op2_reg[22] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[22] ;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[22] ;
  wire LO;
  wire S;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign EX_CarryOut = lopt_15;
  assign \EX_Op2_reg[22]  = lopt_19;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_555
   (EX_CarryOut,
    \EX_Op2_reg[21] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[21] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[21] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[21]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_557
   (EX_CarryOut,
    \EX_Op2_reg[20] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[20] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[20] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[20]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_559
   (EX_CarryOut,
    \EX_Op2_reg[1] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[1] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[1] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[1]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_561
   (EX_CarryOut,
    \EX_Op2_reg[19] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[19] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[19] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[19]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_563
   (EX_CarryOut,
    \EX_Op2_reg[18] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[18] ;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[18] ;
  wire LO;
  wire S;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(LO),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,EX_CarryOut}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,DI}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\EX_Op2_reg[18] }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,S}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_565
   (EX_CarryOut,
    \EX_Op2_reg[17] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[17] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[17] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[17]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_567
   (EX_CarryOut,
    \EX_Op2_reg[16] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[16] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[16] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[16]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_569
   (EX_CarryOut,
    \EX_Op2_reg[15] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[15] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[15] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[15]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_571
   (EX_CarryOut,
    \EX_Op2_reg[14] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[14] ;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  input lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[14] ;
  wire LO;
  wire S;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_2 ;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign EX_CarryOut = lopt_15;
  assign \EX_Op2_reg[14]  = lopt_19;
  assign \^lopt_1  = lopt_14;
  assign \^lopt_10  = lopt_18;
  assign \^lopt_11  = lopt_17;
  assign \^lopt_12  = lopt_16;
  assign \^lopt_2  = lopt_1;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_4  = lopt_13;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_7  = lopt_12;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_573
   (EX_CarryOut,
    \EX_Op2_reg[13] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[13] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[13] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[13]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_575
   (EX_CarryOut,
    \EX_Op2_reg[12] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[12] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[12] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[12]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_577
   (EX_CarryOut,
    \EX_Op2_reg[11] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[11] ;
  input S;
  input DI;
  input LO;
  input lopt;
  input lopt_1;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[11] ;
  wire LO;
  wire S;

  assign EX_CarryOut = lopt;
  assign \EX_Op2_reg[11]  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_579
   (EX_CarryOut,
    \EX_Op2_reg[10] ,
    S,
    DI,
    LO,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25,
    lopt_26,
    lopt_27);
  output EX_CarryOut;
  output [0:0]\EX_Op2_reg[10] ;
  input S;
  input DI;
  input LO;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;
  input lopt_26;
  input lopt_27;

  wire DI;
  wire EX_CarryOut;
  wire [0:0]\EX_Op2_reg[10] ;
  wire LO;
  wire S;
  wire \^lopt_1 ;
  wire \^lopt_10 ;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire \^lopt_20 ;
  wire \^lopt_21 ;
  wire \^lopt_22 ;
  wire \^lopt_23 ;
  wire \^lopt_24 ;
  wire \^lopt_25 ;
  wire \^lopt_26 ;
  wire \^lopt_27 ;
  wire lopt_28;
  wire \^lopt_3 ;
  wire \^lopt_4 ;
  wire \^lopt_5 ;
  wire \^lopt_6 ;
  wire \^lopt_7 ;
  wire \^lopt_8 ;
  wire \^lopt_9 ;

  assign \^lopt_2  = lopt_1;
  assign \^lopt_21  = lopt_20;
  assign \^lopt_22  = lopt_21;
  assign \^lopt_23  = lopt_22;
  assign \^lopt_24  = lopt_23;
  assign \^lopt_25  = lopt_24;
  assign \^lopt_26  = lopt_25;
  assign \^lopt_27  = lopt_26;
  assign \^lopt_3  = lopt_2;
  assign \^lopt_5  = lopt_4;
  assign \^lopt_6  = lopt_5;
  assign \^lopt_8  = lopt_7;
  assign \^lopt_9  = lopt_8;
  assign lopt = \^lopt_1 ;
  assign lopt_10 = \^lopt_11 ;
  assign lopt_11 = \^lopt_12 ;
  assign lopt_12 = \^lopt_13 ;
  assign lopt_13 = \^lopt_14 ;
  assign lopt_14 = \^lopt_15 ;
  assign lopt_15 = \^lopt_16 ;
  assign lopt_16 = \^lopt_17 ;
  assign lopt_17 = \^lopt_18 ;
  assign lopt_18 = \^lopt_19 ;
  assign lopt_19 = \^lopt_20 ;
  assign lopt_28 = lopt_27;
  assign lopt_3 = \^lopt_4 ;
  assign lopt_6 = \^lopt_7 ;
  assign lopt_9 = \^lopt_10 ;
  (* OPT_MODIFIED = "MLO" *) 
  (* XILINX_LEGACY_PRIM = "(CARRY4)" *) 
  (* XILINX_TRANSFORM_PINMAP = "LO:O" *) 
  (* box_type = "PRIMITIVE" *) 
  CARRY8 \Using_FPGA.Native_I1_CARRY4_CARRY8 
       (.CI(LO),
        .CI_TOP(1'b0),
        .CO({\^lopt_13 ,\^lopt_14 ,\^lopt_15 ,\^lopt_16 ,\^lopt_7 ,\^lopt_4 ,\^lopt_1 ,EX_CarryOut}),
        .DI({\^lopt_21 ,\^lopt_22 ,\^lopt_23 ,\^lopt_24 ,\^lopt_8 ,\^lopt_5 ,\^lopt_2 ,DI}),
        .O({\^lopt_17 ,\^lopt_18 ,\^lopt_19 ,\^lopt_20 ,\^lopt_12 ,\^lopt_11 ,\^lopt_10 ,\EX_Op2_reg[10] }),
        .S({\^lopt_25 ,\^lopt_26 ,\^lopt_27 ,lopt_28,\^lopt_9 ,\^lopt_6 ,\^lopt_3 ,S}));
endmodule

(* ORIG_REF_NAME = "MB_MUXCY_XORCY" *) 
module design_1_microblaze_0_0_MB_MUXCY_XORCY_580
   (\EX_Op2_reg[0] ,
    \EX_Op2_reg[0]_0 ,
    S,
    DI,
    CI,
    lopt,
    lopt_1);
  output \EX_Op2_reg[0] ;
  output [0:0]\EX_Op2_reg[0]_0 ;
  input S;
  input DI;
  input CI;
  input lopt;
  input lopt_1;

  wire CI;
  wire DI;
  wire \EX_Op2_reg[0] ;
  wire [0:0]\EX_Op2_reg[0]_0 ;
  wire S;

  assign \EX_Op2_reg[0]  = lopt;
  assign \EX_Op2_reg[0]_0  = lopt_1;
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7
   (sel_input_i_1,
    I4_0,
    sel_input_iii_0,
    sel_input_delayslot,
    ex_branch_with_delayslot_i,
    wb_exception,
    Q);
  output sel_input_i_1;
  output I4_0;
  input sel_input_iii_0;
  input sel_input_delayslot;
  input ex_branch_with_delayslot_i;
  input wb_exception;
  input [1:0]Q;

  wire I4_0;
  wire [1:0]Q;
  wire ex_branch_with_delayslot_i;
  wire sel_input_delayslot;
  wire sel_input_i_1;
  wire sel_input_iii_0;
  wire wb_exception;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(sel_input_iii_0),
        .I1(sel_input_delayslot),
        .O(sel_input_i_1),
        .S(I4_0));
  LUT4 #(
    .INIT(16'h2AAA)) 
    \Using_FPGA.Native_i_1__0 
       (.I0(ex_branch_with_delayslot_i),
        .I1(wb_exception),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(I4_0));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_120
   (of_instr_ii_42,
    \Using_FPGA.Native_0 ,
    I0169_out,
    I1167_out);
  output of_instr_ii_42;
  input \Using_FPGA.Native_0 ;
  input I0169_out;
  input I1167_out;

  wire I0169_out;
  wire I1167_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_42;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0169_out),
        .I1(I1167_out),
        .O(of_instr_ii_42),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_122
   (of_instr_ii_32,
    \Using_FPGA.Native_0 ,
    I0129_out,
    I1127_out);
  output of_instr_ii_32;
  input \Using_FPGA.Native_0 ;
  input I0129_out;
  input I1127_out;

  wire I0129_out;
  wire I1127_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_32;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0129_out),
        .I1(I1127_out),
        .O(of_instr_ii_32),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_124
   (of_instr_ii_31,
    \Using_FPGA.Native_0 ,
    I0125_out,
    I1123_out);
  output of_instr_ii_31;
  input \Using_FPGA.Native_0 ;
  input I0125_out;
  input I1123_out;

  wire I0125_out;
  wire I1123_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_31;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0125_out),
        .I1(I1123_out),
        .O(of_instr_ii_31),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_126
   (of_instr_ii_30,
    \Using_FPGA.Native_0 ,
    I0121_out,
    I1119_out);
  output of_instr_ii_30;
  input \Using_FPGA.Native_0 ;
  input I0121_out;
  input I1119_out;

  wire I0121_out;
  wire I1119_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_30;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0121_out),
        .I1(I1119_out),
        .O(of_instr_ii_30),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_128
   (of_instr_ii_29,
    \Using_FPGA.Native_0 ,
    I0117_out,
    I1115_out);
  output of_instr_ii_29;
  input \Using_FPGA.Native_0 ;
  input I0117_out;
  input I1115_out;

  wire I0117_out;
  wire I1115_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_29;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0117_out),
        .I1(I1115_out),
        .O(of_instr_ii_29),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_130
   (of_instr_ii_28,
    \Using_FPGA.Native_0 ,
    I0113_out,
    I1111_out);
  output of_instr_ii_28;
  input \Using_FPGA.Native_0 ;
  input I0113_out;
  input I1111_out;

  wire I0113_out;
  wire I1111_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_28;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0113_out),
        .I1(I1111_out),
        .O(of_instr_ii_28),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_132
   (of_instr_ii_27,
    \Using_FPGA.Native_0 ,
    I0109_out,
    I1107_out);
  output of_instr_ii_27;
  input \Using_FPGA.Native_0 ;
  input I0109_out;
  input I1107_out;

  wire I0109_out;
  wire I1107_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_27;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0109_out),
        .I1(I1107_out),
        .O(of_instr_ii_27),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_134
   (of_instr_ii_26,
    \Using_FPGA.Native_0 ,
    I0105_out,
    I1103_out);
  output of_instr_ii_26;
  input \Using_FPGA.Native_0 ;
  input I0105_out;
  input I1103_out;

  wire I0105_out;
  wire I1103_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_26;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0105_out),
        .I1(I1103_out),
        .O(of_instr_ii_26),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_136
   (of_instr_ii_25,
    \Using_FPGA.Native_0 ,
    I0101_out,
    I199_out);
  output of_instr_ii_25;
  input \Using_FPGA.Native_0 ;
  input I0101_out;
  input I199_out;

  wire I0101_out;
  wire I199_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_25;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0101_out),
        .I1(I199_out),
        .O(of_instr_ii_25),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_138
   (of_instr_ii_24,
    \Using_FPGA.Native_0 ,
    I097_out,
    I195_out);
  output of_instr_ii_24;
  input \Using_FPGA.Native_0 ;
  input I097_out;
  input I195_out;

  wire I097_out;
  wire I195_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_24;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I097_out),
        .I1(I195_out),
        .O(of_instr_ii_24),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_140
   (of_instr_ii_23,
    \Using_FPGA.Native_0 ,
    I093_out,
    I191_out);
  output of_instr_ii_23;
  input \Using_FPGA.Native_0 ;
  input I093_out;
  input I191_out;

  wire I093_out;
  wire I191_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_23;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I093_out),
        .I1(I191_out),
        .O(of_instr_ii_23),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_142
   (of_instr_ii_41,
    \Using_FPGA.Native_0 ,
    I0165_out,
    I1163_out);
  output of_instr_ii_41;
  input \Using_FPGA.Native_0 ;
  input I0165_out;
  input I1163_out;

  wire I0165_out;
  wire I1163_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_41;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0165_out),
        .I1(I1163_out),
        .O(of_instr_ii_41),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_144
   (of_instr_ii_22,
    \Using_FPGA.Native_0 ,
    I089_out,
    I187_out);
  output of_instr_ii_22;
  input \Using_FPGA.Native_0 ;
  input I089_out;
  input I187_out;

  wire I089_out;
  wire I187_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_22;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I089_out),
        .I1(I187_out),
        .O(of_instr_ii_22),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_146
   (of_instr_ii_21,
    \Using_FPGA.Native_0 ,
    I085_out,
    I183_out);
  output of_instr_ii_21;
  input \Using_FPGA.Native_0 ;
  input I085_out;
  input I183_out;

  wire I085_out;
  wire I183_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_21;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I085_out),
        .I1(I183_out),
        .O(of_instr_ii_21),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_148
   (of_instr_ii_20,
    \Using_FPGA.Native_0 ,
    I081_out,
    I179_out);
  output of_instr_ii_20;
  input \Using_FPGA.Native_0 ;
  input I081_out;
  input I179_out;

  wire I081_out;
  wire I179_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_20;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I081_out),
        .I1(I179_out),
        .O(of_instr_ii_20),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_150
   (of_instr_ii_19,
    \Using_FPGA.Native_0 ,
    I077_out,
    I175_out);
  output of_instr_ii_19;
  input \Using_FPGA.Native_0 ;
  input I077_out;
  input I175_out;

  wire I077_out;
  wire I175_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_19;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I077_out),
        .I1(I175_out),
        .O(of_instr_ii_19),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_152
   (of_instr_ii_18,
    \Using_FPGA.Native_0 ,
    I073_out,
    I171_out);
  output of_instr_ii_18;
  input \Using_FPGA.Native_0 ;
  input I073_out;
  input I171_out;

  wire I073_out;
  wire I171_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_18;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I073_out),
        .I1(I171_out),
        .O(of_instr_ii_18),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_154
   (of_instr_ii_17,
    \Using_FPGA.Native_0 ,
    I069_out,
    I167_out);
  output of_instr_ii_17;
  input \Using_FPGA.Native_0 ;
  input I069_out;
  input I167_out;

  wire I069_out;
  wire I167_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_17;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I069_out),
        .I1(I167_out),
        .O(of_instr_ii_17),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_156
   (of_instr_ii_16,
    \Using_FPGA.Native_0 ,
    I065_out,
    I163_out);
  output of_instr_ii_16;
  input \Using_FPGA.Native_0 ;
  input I065_out;
  input I163_out;

  wire I065_out;
  wire I163_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_16;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I065_out),
        .I1(I163_out),
        .O(of_instr_ii_16),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_158
   (of_instr_ii_15,
    \Using_FPGA.Native_0 ,
    I061_out,
    I159_out);
  output of_instr_ii_15;
  input \Using_FPGA.Native_0 ;
  input I061_out;
  input I159_out;

  wire I061_out;
  wire I159_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_15;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I061_out),
        .I1(I159_out),
        .O(of_instr_ii_15),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_160
   (of_instr_ii_14,
    \Using_FPGA.Native_0 ,
    I057_out,
    I155_out);
  output of_instr_ii_14;
  input \Using_FPGA.Native_0 ;
  input I057_out;
  input I155_out;

  wire I057_out;
  wire I155_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_14;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I057_out),
        .I1(I155_out),
        .O(of_instr_ii_14),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_162
   (of_instr_ii_13,
    \Using_FPGA.Native_0 ,
    I053_out,
    I151_out);
  output of_instr_ii_13;
  input \Using_FPGA.Native_0 ;
  input I053_out;
  input I151_out;

  wire I053_out;
  wire I151_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_13;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I053_out),
        .I1(I151_out),
        .O(of_instr_ii_13),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_164
   (of_instr_ii_40,
    \Using_FPGA.Native_0 ,
    I0161_out,
    I1159_out);
  output of_instr_ii_40;
  input \Using_FPGA.Native_0 ;
  input I0161_out;
  input I1159_out;

  wire I0161_out;
  wire I1159_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_40;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0161_out),
        .I1(I1159_out),
        .O(of_instr_ii_40),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_166
   (of_instr_ii_12,
    \Using_FPGA.Native_0 ,
    I049_out,
    I147_out);
  output of_instr_ii_12;
  input \Using_FPGA.Native_0 ;
  input I049_out;
  input I147_out;

  wire I049_out;
  wire I147_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_12;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I049_out),
        .I1(I147_out),
        .O(of_instr_ii_12),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_168
   (of_instr_ii_11,
    \Using_FPGA.Native_0 ,
    I045_out,
    I143_out);
  output of_instr_ii_11;
  input \Using_FPGA.Native_0 ;
  input I045_out;
  input I143_out;

  wire I045_out;
  wire I143_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_11;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I045_out),
        .I1(I143_out),
        .O(of_instr_ii_11),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_170
   (of_instr_ii_10,
    \Using_FPGA.Native_0 ,
    I041_out,
    I139_out);
  output of_instr_ii_10;
  input \Using_FPGA.Native_0 ;
  input I041_out;
  input I139_out;

  wire I041_out;
  wire I139_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_10;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I041_out),
        .I1(I139_out),
        .O(of_instr_ii_10),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_172
   (of_instr_ii_9,
    \Using_FPGA.Native_0 ,
    I037_out,
    I135_out);
  output of_instr_ii_9;
  input \Using_FPGA.Native_0 ;
  input I037_out;
  input I135_out;

  wire I037_out;
  wire I135_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_9;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I037_out),
        .I1(I135_out),
        .O(of_instr_ii_9),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_174
   (of_instr_ii_8,
    \Using_FPGA.Native_0 ,
    I033_out,
    I131_out);
  output of_instr_ii_8;
  input \Using_FPGA.Native_0 ;
  input I033_out;
  input I131_out;

  wire I033_out;
  wire I131_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_8;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I033_out),
        .I1(I131_out),
        .O(of_instr_ii_8),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_176
   (of_instr_ii_7,
    \Using_FPGA.Native_0 ,
    I029_out,
    I127_out);
  output of_instr_ii_7;
  input \Using_FPGA.Native_0 ;
  input I029_out;
  input I127_out;

  wire I029_out;
  wire I127_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_7;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I029_out),
        .I1(I127_out),
        .O(of_instr_ii_7),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_178
   (of_instr_ii_6,
    \Using_FPGA.Native_0 ,
    I025_out,
    I123_out);
  output of_instr_ii_6;
  input \Using_FPGA.Native_0 ;
  input I025_out;
  input I123_out;

  wire I025_out;
  wire I123_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_6;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I025_out),
        .I1(I123_out),
        .O(of_instr_ii_6),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_180
   (of_instr_ii_5,
    \Using_FPGA.Native_0 ,
    I021_out,
    I119_out);
  output of_instr_ii_5;
  input \Using_FPGA.Native_0 ;
  input I021_out;
  input I119_out;

  wire I021_out;
  wire I119_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_5;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I021_out),
        .I1(I119_out),
        .O(of_instr_ii_5),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_182
   (of_instr_ii_4,
    \Using_FPGA.Native_0 ,
    I017_out,
    I115_out);
  output of_instr_ii_4;
  input \Using_FPGA.Native_0 ;
  input I017_out;
  input I115_out;

  wire I017_out;
  wire I115_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_4;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I017_out),
        .I1(I115_out),
        .O(of_instr_ii_4),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_184
   (of_instr_ii_3,
    \Using_FPGA.Native_0 ,
    I013_out,
    I111_out);
  output of_instr_ii_3;
  input \Using_FPGA.Native_0 ;
  input I013_out;
  input I111_out;

  wire I013_out;
  wire I111_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_3;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I013_out),
        .I1(I111_out),
        .O(of_instr_ii_3),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_186
   (of_instr_ii_39,
    \Using_FPGA.Native_0 ,
    I0157_out,
    I1155_out);
  output of_instr_ii_39;
  input \Using_FPGA.Native_0 ;
  input I0157_out;
  input I1155_out;

  wire I0157_out;
  wire I1155_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_39;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0157_out),
        .I1(I1155_out),
        .O(of_instr_ii_39),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_188
   (of_instr_ii_2,
    \Using_FPGA.Native_0 ,
    I09_out,
    I17_out);
  output of_instr_ii_2;
  input \Using_FPGA.Native_0 ;
  input I09_out;
  input I17_out;

  wire I09_out;
  wire I17_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_2;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I09_out),
        .I1(I17_out),
        .O(of_instr_ii_2),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_190
   (of_instr_ii_1,
    \Using_FPGA.Native_0 ,
    I05_out,
    I13_out);
  output of_instr_ii_1;
  input \Using_FPGA.Native_0 ;
  input I05_out;
  input I13_out;

  wire I05_out;
  wire I13_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_1;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I05_out),
        .I1(I13_out),
        .O(of_instr_ii_1),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_192
   (of_instr_ii_0,
    IReady_0,
    \Using_FPGA.Native_0 ,
    I0_1,
    I1,
    IReady,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    if_missed_fetch);
  output of_instr_ii_0;
  output IReady_0;
  input \Using_FPGA.Native_0 ;
  input I0_1;
  input I1;
  input IReady;
  input \Using_FPGA.Native_1 ;
  input \Using_FPGA.Native_2 ;
  input \Using_FPGA.Native_3 ;
  input if_missed_fetch;

  wire I0_1;
  wire I1;
  wire IReady;
  wire IReady_0;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire if_missed_fetch;
  wire of_instr_ii_0;

  LUT5 #(
    .INIT(32'h0000FF02)) 
    \PC_Buffer_reg[3][31]_srl4_i_1 
       (.I0(IReady),
        .I1(\Using_FPGA.Native_1 ),
        .I2(\Using_FPGA.Native_2 ),
        .I3(\Using_FPGA.Native_3 ),
        .I4(if_missed_fetch),
        .O(IReady_0));
  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0_1),
        .I1(I1),
        .O(of_instr_ii_0),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_194
   (of_instr_ii_38,
    \Using_FPGA.Native_0 ,
    I0153_out,
    I1151_out);
  output of_instr_ii_38;
  input \Using_FPGA.Native_0 ;
  input I0153_out;
  input I1151_out;

  wire I0153_out;
  wire I1151_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_38;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0153_out),
        .I1(I1151_out),
        .O(of_instr_ii_38),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_196
   (of_instr_ii_37,
    \Using_FPGA.Native_0 ,
    I0149_out,
    I1147_out);
  output of_instr_ii_37;
  input \Using_FPGA.Native_0 ;
  input I0149_out;
  input I1147_out;

  wire I0149_out;
  wire I1147_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_37;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0149_out),
        .I1(I1147_out),
        .O(of_instr_ii_37),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_198
   (of_instr_ii_36,
    \Using_FPGA.Native_0 ,
    I0145_out,
    I1143_out);
  output of_instr_ii_36;
  input \Using_FPGA.Native_0 ;
  input I0145_out;
  input I1143_out;

  wire I0145_out;
  wire I1143_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_36;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0145_out),
        .I1(I1143_out),
        .O(of_instr_ii_36),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_200
   (of_instr_ii_35,
    \Using_FPGA.Native_0 ,
    I0141_out,
    I1139_out);
  output of_instr_ii_35;
  input \Using_FPGA.Native_0 ;
  input I0141_out;
  input I1139_out;

  wire I0141_out;
  wire I1139_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_35;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0141_out),
        .I1(I1139_out),
        .O(of_instr_ii_35),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_202
   (of_instr_ii_34,
    \Using_FPGA.Native_0 ,
    I0137_out,
    I1135_out);
  output of_instr_ii_34;
  input \Using_FPGA.Native_0 ;
  input I0137_out;
  input I1135_out;

  wire I0137_out;
  wire I1135_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_34;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0137_out),
        .I1(I1135_out),
        .O(of_instr_ii_34),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_204
   (of_instr_ii_33,
    \Using_FPGA.Native_0 ,
    I0133_out,
    I1131_out);
  output of_instr_ii_33;
  input \Using_FPGA.Native_0 ;
  input I0133_out;
  input I1131_out;

  wire I0133_out;
  wire I1131_out;
  wire \Using_FPGA.Native_0 ;
  wire of_instr_ii_33;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0133_out),
        .I1(I1131_out),
        .O(of_instr_ii_33),
        .S(\Using_FPGA.Native_0 ));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_207
   (of_pc_ii_31,
    \Using_FPGA.Native_0 ,
    I0125_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_31;
  input \Using_FPGA.Native_0 ;
  input I0125_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0125_out;
  wire I1123_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_31;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0125_out),
        .I1(I1123_out),
        .O(of_pc_ii_31),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__57 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I1123_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_209
   (of_pc_ii_21,
    \Using_FPGA.Native_0 ,
    I085_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_21;
  input \Using_FPGA.Native_0 ;
  input I085_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I085_out;
  wire I183_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_21;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I085_out),
        .I1(I183_out),
        .O(of_pc_ii_21),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__47 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I183_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_211
   (of_pc_ii_20,
    \Using_FPGA.Native_0 ,
    I081_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_20;
  input \Using_FPGA.Native_0 ;
  input I081_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I081_out;
  wire I179_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_20;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I081_out),
        .I1(I179_out),
        .O(of_pc_ii_20),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__46 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I179_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_213
   (of_pc_ii_19,
    \Using_FPGA.Native_0 ,
    I077_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_19;
  input \Using_FPGA.Native_0 ;
  input I077_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I077_out;
  wire I175_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_19;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I077_out),
        .I1(I175_out),
        .O(of_pc_ii_19),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__45 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I175_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_215
   (of_pc_ii_18,
    \Using_FPGA.Native_0 ,
    I073_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_18;
  input \Using_FPGA.Native_0 ;
  input I073_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I073_out;
  wire I171_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_18;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I073_out),
        .I1(I171_out),
        .O(of_pc_ii_18),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__44 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I171_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_217
   (of_pc_ii_17,
    \Using_FPGA.Native_0 ,
    I069_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_17;
  input \Using_FPGA.Native_0 ;
  input I069_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I069_out;
  wire I167_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_17;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I069_out),
        .I1(I167_out),
        .O(of_pc_ii_17),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__43 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I167_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_219
   (of_pc_ii_16,
    \Using_FPGA.Native_0 ,
    I065_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_16;
  input \Using_FPGA.Native_0 ;
  input I065_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I065_out;
  wire I163_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_16;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I065_out),
        .I1(I163_out),
        .O(of_pc_ii_16),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__42 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I163_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_221
   (of_pc_ii_15,
    \Using_FPGA.Native_0 ,
    I061_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_15;
  input \Using_FPGA.Native_0 ;
  input I061_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I061_out;
  wire I159_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_15;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I061_out),
        .I1(I159_out),
        .O(of_pc_ii_15),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__41 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I159_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_223
   (of_pc_ii_14,
    \Using_FPGA.Native_0 ,
    I057_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_14;
  input \Using_FPGA.Native_0 ;
  input I057_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I057_out;
  wire I155_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_14;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I057_out),
        .I1(I155_out),
        .O(of_pc_ii_14),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__40 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I155_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_225
   (of_pc_ii_13,
    \Using_FPGA.Native_0 ,
    I053_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_13;
  input \Using_FPGA.Native_0 ;
  input I053_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I053_out;
  wire I151_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_13;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I053_out),
        .I1(I151_out),
        .O(of_pc_ii_13),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__39 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I151_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_227
   (of_pc_ii_12,
    \Using_FPGA.Native_0 ,
    I049_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_12;
  input \Using_FPGA.Native_0 ;
  input I049_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I049_out;
  wire I147_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_12;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I049_out),
        .I1(I147_out),
        .O(of_pc_ii_12),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__38 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I147_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_229
   (of_pc_ii_30,
    \Using_FPGA.Native_0 ,
    I0121_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_30;
  input \Using_FPGA.Native_0 ;
  input I0121_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0121_out;
  wire I1119_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_30;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0121_out),
        .I1(I1119_out),
        .O(of_pc_ii_30),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__56 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I1119_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_231
   (of_pc_ii_11,
    \Using_FPGA.Native_0 ,
    I045_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_11;
  input \Using_FPGA.Native_0 ;
  input I045_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I045_out;
  wire I143_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_11;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I045_out),
        .I1(I143_out),
        .O(of_pc_ii_11),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__37 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I143_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_233
   (of_pc_ii_10,
    \Using_FPGA.Native_0 ,
    I041_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_10;
  input \Using_FPGA.Native_0 ;
  input I041_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I041_out;
  wire I139_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_10;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I041_out),
        .I1(I139_out),
        .O(of_pc_ii_10),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__36 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I139_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_235
   (of_pc_ii_9,
    \Using_FPGA.Native_0 ,
    I037_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_9;
  input \Using_FPGA.Native_0 ;
  input I037_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I037_out;
  wire I135_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_9;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I037_out),
        .I1(I135_out),
        .O(of_pc_ii_9),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__35 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I135_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_237
   (of_pc_ii_8,
    \Using_FPGA.Native_0 ,
    I033_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_8;
  input \Using_FPGA.Native_0 ;
  input I033_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I033_out;
  wire I131_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_8;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I033_out),
        .I1(I131_out),
        .O(of_pc_ii_8),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__34 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I131_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_239
   (of_pc_ii_7,
    \Using_FPGA.Native_0 ,
    I029_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_7;
  input \Using_FPGA.Native_0 ;
  input I029_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I029_out;
  wire I127_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_7;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I029_out),
        .I1(I127_out),
        .O(of_pc_ii_7),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__33 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I127_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_241
   (of_pc_ii_6,
    \Using_FPGA.Native_0 ,
    I025_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_6;
  input \Using_FPGA.Native_0 ;
  input I025_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I025_out;
  wire I123_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_6;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I025_out),
        .I1(I123_out),
        .O(of_pc_ii_6),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__32 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I123_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_243
   (of_pc_ii_5,
    \Using_FPGA.Native_0 ,
    I021_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_5;
  input \Using_FPGA.Native_0 ;
  input I021_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I021_out;
  wire I119_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_5;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I021_out),
        .I1(I119_out),
        .O(of_pc_ii_5),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__31 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I119_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_245
   (of_pc_ii_4,
    \Using_FPGA.Native_0 ,
    I017_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_4;
  input \Using_FPGA.Native_0 ;
  input I017_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I017_out;
  wire I115_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_4;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I017_out),
        .I1(I115_out),
        .O(of_pc_ii_4),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__30 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I115_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_247
   (of_pc_ii_3,
    \Using_FPGA.Native_0 ,
    I013_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_3;
  input \Using_FPGA.Native_0 ;
  input I013_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I013_out;
  wire I111_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_3;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I013_out),
        .I1(I111_out),
        .O(of_pc_ii_3),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__29 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I111_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_249
   (of_pc_ii_2,
    \Using_FPGA.Native_0 ,
    I09_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_2;
  input \Using_FPGA.Native_0 ;
  input I09_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I09_out;
  wire I17_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_2;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I09_out),
        .I1(I17_out),
        .O(of_pc_ii_2),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__28 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I17_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_251
   (of_pc_ii_29,
    \Using_FPGA.Native_0 ,
    I0117_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_29;
  input \Using_FPGA.Native_0 ;
  input I0117_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0117_out;
  wire I1115_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_29;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0117_out),
        .I1(I1115_out),
        .O(of_pc_ii_29),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__55 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I1115_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_253
   (of_pc_ii_1,
    \Using_FPGA.Native_0 ,
    I05_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_1;
  input \Using_FPGA.Native_0 ;
  input I05_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I05_out;
  wire I13_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_1;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I05_out),
        .I1(I13_out),
        .O(of_pc_ii_1),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__27 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I13_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_255
   (of_pc_ii_0,
    \Using_FPGA.Native_0 ,
    I0,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_0;
  input \Using_FPGA.Native_0 ;
  input I0;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0;
  wire I1;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_0;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0),
        .I1(I1),
        .O(of_pc_ii_0),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__26 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I1));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_257
   (of_pc_ii_28,
    \Using_FPGA.Native_0 ,
    I0113_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_28;
  input \Using_FPGA.Native_0 ;
  input I0113_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0113_out;
  wire I1111_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_28;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0113_out),
        .I1(I1111_out),
        .O(of_pc_ii_28),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__54 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I1111_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_259
   (of_pc_ii_27,
    \Using_FPGA.Native_0 ,
    I0109_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_27;
  input \Using_FPGA.Native_0 ;
  input I0109_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0109_out;
  wire I1107_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_27;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0109_out),
        .I1(I1107_out),
        .O(of_pc_ii_27),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__53 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I1107_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_261
   (of_pc_ii_26,
    \Using_FPGA.Native_0 ,
    I0105_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_26;
  input \Using_FPGA.Native_0 ;
  input I0105_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0105_out;
  wire I1103_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_26;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0105_out),
        .I1(I1103_out),
        .O(of_pc_ii_26),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__52 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I1103_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_263
   (of_pc_ii_25,
    \Using_FPGA.Native_0 ,
    I0101_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_25;
  input \Using_FPGA.Native_0 ;
  input I0101_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I0101_out;
  wire I199_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_25;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I0101_out),
        .I1(I199_out),
        .O(of_pc_ii_25),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__51 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I199_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_265
   (of_pc_ii_24,
    \Using_FPGA.Native_0 ,
    I097_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_24;
  input \Using_FPGA.Native_0 ;
  input I097_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I097_out;
  wire I195_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_24;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I097_out),
        .I1(I195_out),
        .O(of_pc_ii_24),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__50 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I195_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_267
   (of_pc_ii_23,
    \Using_FPGA.Native_0 ,
    I093_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_23;
  input \Using_FPGA.Native_0 ;
  input I093_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I093_out;
  wire I191_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_23;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I093_out),
        .I1(I191_out),
        .O(of_pc_ii_23),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__49 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I191_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_269
   (of_pc_ii_22,
    \Using_FPGA.Native_0 ,
    I089_out,
    out,
    \Using_FPGA.Native_1 ,
    Q);
  output of_pc_ii_22;
  input \Using_FPGA.Native_0 ;
  input I089_out;
  input [0:0]out;
  input \Using_FPGA.Native_1 ;
  input [0:0]Q;

  wire I089_out;
  wire I187_out;
  wire [0:0]Q;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire of_pc_ii_22;
  wire [0:0]out;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(I089_out),
        .I1(I187_out),
        .O(of_pc_ii_22),
        .S(\Using_FPGA.Native_0 ));
  LUT3 #(
    .INIT(8'hE2)) 
    \Using_FPGA.Native_i_2__48 
       (.I0(out),
        .I1(\Using_FPGA.Native_1 ),
        .I2(Q),
        .O(I187_out));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_424
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[0] ,
    I1,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[0] ;
  input I1;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[0] ;
  wire I1;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[0] ),
        .I1(I1),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_4__0 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_425
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[10] ,
    \EX_Op1_reg[10]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[10] ;
  input \EX_Op1_reg[10]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[10] ;
  wire \EX_Op1_reg[10]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[10] ),
        .I1(\EX_Op1_reg[10]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__107 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_426
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[11] ,
    \EX_Op1_reg[11]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[11] ;
  input \EX_Op1_reg[11]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[11] ;
  wire \EX_Op1_reg[11]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[11] ),
        .I1(\EX_Op1_reg[11]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__106 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_427
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[12] ,
    \EX_Op1_reg[12]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[12] ;
  input \EX_Op1_reg[12]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[12] ;
  wire \EX_Op1_reg[12]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[12] ),
        .I1(\EX_Op1_reg[12]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__105 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_428
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[13] ,
    \EX_Op1_reg[13]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[13] ;
  input \EX_Op1_reg[13]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[13] ;
  wire \EX_Op1_reg[13]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[13] ),
        .I1(\EX_Op1_reg[13]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__104 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_429
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[14] ,
    \EX_Op1_reg[14]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[14] ;
  input \EX_Op1_reg[14]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[14] ;
  wire \EX_Op1_reg[14]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[14] ),
        .I1(\EX_Op1_reg[14]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__103 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_430
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[15] ,
    \EX_Op1_reg[15]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[15] ;
  input \EX_Op1_reg[15]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[15] ;
  wire \EX_Op1_reg[15]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[15] ),
        .I1(\EX_Op1_reg[15]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__102 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_431
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[16] ,
    \EX_Op1_reg[16]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[16] ;
  input \EX_Op1_reg[16]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[16] ;
  wire \EX_Op1_reg[16]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[16] ),
        .I1(\EX_Op1_reg[16]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__101 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_432
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[17] ,
    \EX_Op1_reg[17]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[17] ;
  input \EX_Op1_reg[17]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[17] ;
  wire \EX_Op1_reg[17]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[17] ),
        .I1(\EX_Op1_reg[17]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__100 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_433
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[18] ,
    \EX_Op1_reg[18]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[18] ;
  input \EX_Op1_reg[18]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[18] ;
  wire \EX_Op1_reg[18]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[18] ),
        .I1(\EX_Op1_reg[18]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__99 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_434
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[19] ,
    \EX_Op1_reg[19]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[19] ;
  input \EX_Op1_reg[19]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[19] ;
  wire \EX_Op1_reg[19]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[19] ),
        .I1(\EX_Op1_reg[19]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__98 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_435
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[1] ,
    \EX_Op1_reg[1]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[1] ;
  input \EX_Op1_reg[1]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[1] ;
  wire \EX_Op1_reg[1]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[1] ),
        .I1(\EX_Op1_reg[1]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__116 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_436
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[20] ,
    \EX_Op1_reg[20]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[20] ;
  input \EX_Op1_reg[20]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[20] ;
  wire \EX_Op1_reg[20]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[20] ),
        .I1(\EX_Op1_reg[20]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__97 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_437
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[21] ,
    \EX_Op1_reg[21]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[21] ;
  input \EX_Op1_reg[21]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[21] ;
  wire \EX_Op1_reg[21]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[21] ),
        .I1(\EX_Op1_reg[21]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__96 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_438
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[22] ,
    \EX_Op1_reg[22]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[22] ;
  input \EX_Op1_reg[22]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[22] ;
  wire \EX_Op1_reg[22]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[22] ),
        .I1(\EX_Op1_reg[22]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__95 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_439
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[23] ,
    \EX_Op1_reg[23]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[23] ;
  input \EX_Op1_reg[23]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[23] ;
  wire \EX_Op1_reg[23]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[23] ),
        .I1(\EX_Op1_reg[23]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__94 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_440
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[24] ,
    \EX_Op1_reg[24]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[24] ;
  input \EX_Op1_reg[24]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[24] ;
  wire \EX_Op1_reg[24]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[24] ),
        .I1(\EX_Op1_reg[24]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__93 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_441
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[25] ,
    \EX_Op1_reg[25]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[25] ;
  input \EX_Op1_reg[25]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[25] ;
  wire \EX_Op1_reg[25]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[25] ),
        .I1(\EX_Op1_reg[25]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__92 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_442
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[26] ,
    \EX_Op1_reg[26]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[26] ;
  input \EX_Op1_reg[26]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[26] ;
  wire \EX_Op1_reg[26]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[26] ),
        .I1(\EX_Op1_reg[26]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__91 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_443
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[27] ,
    \EX_Op1_reg[27]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[27] ;
  input \EX_Op1_reg[27]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[27] ;
  wire \EX_Op1_reg[27]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[27] ),
        .I1(\EX_Op1_reg[27]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__90 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_444
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[28] ,
    \EX_Op1_reg[28]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[28] ;
  input \EX_Op1_reg[28]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[28] ;
  wire \EX_Op1_reg[28]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[28] ),
        .I1(\EX_Op1_reg[28]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__89 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_445
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[29] ,
    \EX_Op1_reg[29]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[29] ;
  input \EX_Op1_reg[29]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[29] ;
  wire \EX_Op1_reg[29]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[29] ),
        .I1(\EX_Op1_reg[29]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__88 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_446
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[2] ,
    \EX_Op1_reg[2]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[2] ;
  input \EX_Op1_reg[2]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[2] ;
  wire \EX_Op1_reg[2]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[2] ),
        .I1(\EX_Op1_reg[2]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__115 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_447
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[30] ,
    \EX_Op1_reg[30]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[30] ;
  input \EX_Op1_reg[30]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[30] ;
  wire \EX_Op1_reg[30]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[30] ),
        .I1(\EX_Op1_reg[30]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__87 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_448
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[31] ,
    \EX_Op1_reg[31]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[31] ;
  input \EX_Op1_reg[31]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[31] ;
  wire \EX_Op1_reg[31]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[31] ),
        .I1(\EX_Op1_reg[31]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__86 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_449
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[3] ,
    \EX_Op1_reg[3]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[3] ;
  input \EX_Op1_reg[3]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[3] ;
  wire \EX_Op1_reg[3]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[3] ),
        .I1(\EX_Op1_reg[3]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__114 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_450
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[4] ,
    \EX_Op1_reg[4]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[4] ;
  input \EX_Op1_reg[4]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[4] ;
  wire \EX_Op1_reg[4]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[4] ),
        .I1(\EX_Op1_reg[4]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__113 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_451
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[5] ,
    \EX_Op1_reg[5]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[5] ;
  input \EX_Op1_reg[5]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[5] ;
  wire \EX_Op1_reg[5]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[5] ),
        .I1(\EX_Op1_reg[5]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__112 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_452
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[6] ,
    \EX_Op1_reg[6]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[6] ;
  input \EX_Op1_reg[6]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[6] ;
  wire \EX_Op1_reg[6]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[6] ),
        .I1(\EX_Op1_reg[6]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__111 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_453
   (D,
    swap_result_reg,
    of_op1_sel_spr,
    \EX_Op1_reg[7] ,
    \EX_Op1_reg[7]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result_reg;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[7] ;
  input \EX_Op1_reg[7]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[7] ;
  wire \EX_Op1_reg[7]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result_reg;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[7] ),
        .I1(\EX_Op1_reg[7]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__110 
       (.I0(Q[0]),
        .I1(ex_swap_byte_instr),
        .I2(Q[1]),
        .O(swap_result_reg));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_454
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[8] ,
    \EX_Op1_reg[8]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[8] ;
  input \EX_Op1_reg[8]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[8] ;
  wire \EX_Op1_reg[8]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[8] ),
        .I1(\EX_Op1_reg[8]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__109 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_MUXF7" *) 
module design_1_microblaze_0_0_MB_MUXF7_455
   (D,
    swap_result,
    of_op1_sel_spr,
    \EX_Op1_reg[9] ,
    \EX_Op1_reg[9]_0 ,
    Q,
    ex_swap_byte_instr);
  output [0:0]D;
  output [0:0]swap_result;
  input of_op1_sel_spr;
  input [0:0]\EX_Op1_reg[9] ;
  input \EX_Op1_reg[9]_0 ;
  input [1:0]Q;
  input ex_swap_byte_instr;

  wire [0:0]D;
  wire [0:0]\EX_Op1_reg[9] ;
  wire \EX_Op1_reg[9]_0 ;
  wire [1:0]Q;
  wire ex_swap_byte_instr;
  wire of_op1_sel_spr;
  wire [0:0]swap_result;

  (* box_type = "PRIMITIVE" *) 
  MUXF7 \Using_FPGA.Native 
       (.I0(\EX_Op1_reg[9] ),
        .I1(\EX_Op1_reg[9]_0 ),
        .O(D),
        .S(of_op1_sel_spr));
  LUT3 #(
    .INIT(8'hB8)) 
    \Using_FPGA.Native_i_2__108 
       (.I0(Q[1]),
        .I1(ex_swap_byte_instr),
        .I2(Q[0]),
        .O(swap_result));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[0] ,
    DID,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[0]_0 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[0] ;
  input [1:0]DID;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[0]_0 ;

  wire Clk;
  wire [1:0]DID;
  wire \EX_Branch_CMP_Op1_reg[0] ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[0]_0 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[0]_0 ),
        .DIA(DID),
        .DIB(DID),
        .DIC(DID),
        .DID(DID),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[0] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_409
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[20] ,
    \EX_Branch_CMP_Op1_reg[20]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[20]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[20] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[20]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[20]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[20] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[20]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[20]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[20]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[20]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[20]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[20]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[20]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[20] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_410
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[22] ,
    \EX_Branch_CMP_Op1_reg[22]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[22]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[22] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[22]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[22]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[22] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[22]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[22]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[22]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[22]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[22]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[22]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[22]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[22] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_411
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[24] ,
    \EX_Branch_CMP_Op1_reg[24]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[24]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[24] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[24]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[24]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[24] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[24]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[24]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[24]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[24]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[24]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[24]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[24]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[24] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_412
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[26] ,
    \EX_Branch_CMP_Op1_reg[26]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[26]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[26] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[26]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[26]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[26] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[26]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[26]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[26]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[26]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[26]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[26]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[26]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[26] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_413
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[28] ,
    \EX_Branch_CMP_Op1_reg[28]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[28]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[28] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[28]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[28]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[28] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[28]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[28]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[28]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[28]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[28]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[28]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[28]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[28] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_414
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[30] ,
    \EX_Branch_CMP_Op1_reg[30]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[30]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[30] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[30]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[30]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[30] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[30]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[30]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[30]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[30]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[30]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[30]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[30]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[30] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_415
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[2] ,
    \EX_Branch_CMP_Op1_reg[2]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[2]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[2] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[2]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[2]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[2] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[2]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[2]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[2]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[2]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[2]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[2]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[2]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[2] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_416
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[4] ,
    \EX_Branch_CMP_Op1_reg[4]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[4]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[4] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[4]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[4]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[4] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[4]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[4]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[4]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[4]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[4]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[4]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[4]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[4] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_417
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[6] ,
    \EX_Branch_CMP_Op1_reg[6]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[6]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[6] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[6]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[6]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[6] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[6]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[6]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[6]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[6]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[6]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[6]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[6]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[6] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_418
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[8] ,
    \EX_Branch_CMP_Op1_reg[8]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[8]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[8] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[8]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[8]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[8] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[8]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[8]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[8]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[8]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[8]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[8]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[8]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[8] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_419
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[10] ,
    \EX_Branch_CMP_Op1_reg[10]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[10]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[10] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[10]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[10]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[10] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[10]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[10]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[10]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[10]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[10]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[10]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[10]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[10] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_420
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[12] ,
    \EX_Branch_CMP_Op1_reg[12]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[12]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[12] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[12]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[12]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[12] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[12]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[12]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[12]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[12]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[12]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[12]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[12]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[12] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_421
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[14] ,
    \EX_Branch_CMP_Op1_reg[14]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[14]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[14] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[14]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[14]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[14] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[14]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[14]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[14]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[14]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[14]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[14]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[14]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[14] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_422
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[16] ,
    \EX_Branch_CMP_Op1_reg[16]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[16]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[16] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[16]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[16]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[16] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[16]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[16]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[16]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[16]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[16]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[16]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[16]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[16] ));
endmodule

(* ORIG_REF_NAME = "MB_RAM32M" *) 
module design_1_microblaze_0_0_MB_RAM32M_423
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[18] ,
    \EX_Branch_CMP_Op1_reg[18]_0 ,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[18]_1 );
  output [1:0]GPR_Op1;
  output [1:0]GPR_Op2;
  output [1:0]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[18] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[18]_0 ;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[18]_1 ;

  wire Clk;
  wire \EX_Branch_CMP_Op1_reg[18] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[18]_0 ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[18]_1 ;
  wire [1:0]GPR_Op1;
  wire [1:0]GPR_Op2;
  wire [1:0]GPR_Op3;
  wire \Using_FPGA.Native_n_6 ;
  wire \Using_FPGA.Native_n_7 ;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  (* box_type = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \Using_FPGA.Native 
       (.ADDRA({of_gpr_op1_rd_addr[0],of_gpr_op1_rd_addr[1],of_gpr_op1_rd_addr[2],of_gpr_op1_rd_addr[3],of_gpr_op1_rd_addr[4]}),
        .ADDRB(of_imm_data),
        .ADDRC({of_gpr_op3_rd_addr[0],of_gpr_op3_rd_addr[1],of_gpr_op3_rd_addr[2],of_gpr_op3_rd_addr[3],of_gpr_op3_rd_addr[4]}),
        .ADDRD(\EX_Branch_CMP_Op1_reg[18]_1 ),
        .DIA(\EX_Branch_CMP_Op1_reg[18]_0 ),
        .DIB(\EX_Branch_CMP_Op1_reg[18]_0 ),
        .DIC(\EX_Branch_CMP_Op1_reg[18]_0 ),
        .DID(\EX_Branch_CMP_Op1_reg[18]_0 ),
        .DOA(GPR_Op1),
        .DOB(GPR_Op2),
        .DOC(GPR_Op3),
        .DOD({\Using_FPGA.Native_n_6 ,\Using_FPGA.Native_n_7 }),
        .WCLK(Clk),
        .WE(\EX_Branch_CMP_Op1_reg[18] ));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E
   (Q_0,
    Q,
    Dbg_Clk);
  output Q_0;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q_0;

  (* box_type = "PRIMITIVE" *) 
  SRL16E #(
    .INIT(16'h001B),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q_0));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized1
   (Q11_in,
    Q,
    Dbg_Clk);
  output Q11_in;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q11_in;

  (* box_type = "PRIMITIVE" *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.SRL16E_2/Use_unisim.MB_SRL16E_I1 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q11_in));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized1_17
   (\Serial_Dbg_Intf.shift_count_reg[0] ,
    Q,
    Dbg_Clk);
  output \Serial_Dbg_Intf.shift_count_reg[0] ;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire \Serial_Dbg_Intf.shift_count_reg[0] ;

  (* box_type = "PRIMITIVE" *) 
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector[1].SRL16E_Base_Vector/Use_unisim.MB_SRL16E_I1 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(\Serial_Dbg_Intf.shift_count_reg[0] ));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized1_18
   (tdo_config_word1_0,
    Q,
    Dbg_Clk);
  output tdo_config_word1_0;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire tdo_config_word1_0;

  (* box_type = "PRIMITIVE" *) 
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Base_Vector[2].SRL16E_Base_Vector/Use_unisim.MB_SRL16E_I1 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(tdo_config_word1_0));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized1_19
   (Q4_out,
    Q,
    Dbg_Clk);
  output Q4_out;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q4_out;

  (* box_type = "PRIMITIVE" *) 
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[3].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q4_out));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized1_20
   (Q3_out,
    Q,
    Dbg_Clk);
  output Q3_out;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q3_out;

  (* box_type = "PRIMITIVE" *) 
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[4].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q3_out));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized1_23
   (Q0_out,
    Q,
    Dbg_Clk);
  output Q0_out;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q0_out;

  (* box_type = "PRIMITIVE" *) 
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[7].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q0_out));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized1_24
   (Q3_in,
    Q,
    Dbg_Clk);
  output Q3_in;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q3_in;

  (* box_type = "PRIMITIVE" *) 
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Serial_Dbg_Intf.The_Cache_Addresses[8].SRL16E_Cache_I/Use_unisim.MB_SRL16E_I1 " *) 
  SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q3_in));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized3
   (Q6_out,
    Q,
    Dbg_Clk);
  output Q6_out;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q6_out;

  (* box_type = "PRIMITIVE" *) 
  SRL16E #(
    .INIT(16'hFFFF),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q6_out));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized3_21
   (Q2_out,
    Q,
    Dbg_Clk);
  output Q2_out;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q2_out;

  (* box_type = "PRIMITIVE" *) 
  SRL16E #(
    .INIT(16'hFFFF),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q2_out));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized5
   (\Serial_Dbg_Intf.shift_count_reg[6] ,
    Q,
    Dbg_Clk,
    Dbg_TDO_INST_0_i_5,
    Q6_out,
    Q11_in,
    Q_0);
  output \Serial_Dbg_Intf.shift_count_reg[6] ;
  input [6:0]Q;
  input Dbg_Clk;
  input Dbg_TDO_INST_0_i_5;
  input Q6_out;
  input Q11_in;
  input Q_0;

  wire Dbg_Clk;
  wire Dbg_TDO_INST_0_i_24_n_0;
  wire Dbg_TDO_INST_0_i_5;
  wire [6:0]Q;
  wire Q11_in;
  wire Q5_out;
  wire Q6_out;
  wire Q_0;
  wire \Serial_Dbg_Intf.shift_count_reg[6] ;

  MUXF7 Dbg_TDO_INST_0_i_13
       (.I0(Dbg_TDO_INST_0_i_24_n_0),
        .I1(Dbg_TDO_INST_0_i_5),
        .O(\Serial_Dbg_Intf.shift_count_reg[6] ),
        .S(Q[6]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    Dbg_TDO_INST_0_i_24
       (.I0(Q5_out),
        .I1(Q6_out),
        .I2(Q[5]),
        .I3(Q11_in),
        .I4(Q[4]),
        .I5(Q_0),
        .O(Dbg_TDO_INST_0_i_24_n_0));
  (* box_type = "PRIMITIVE" *) 
  SRL16E #(
    .INIT(16'h3FFF),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q5_out));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized5_22
   (\Serial_Dbg_Intf.shift_count_reg[5] ,
    Q,
    Dbg_Clk,
    Q2_out,
    Q3_out,
    Q4_out);
  output \Serial_Dbg_Intf.shift_count_reg[5] ;
  input [5:0]Q;
  input Dbg_Clk;
  input Q2_out;
  input Q3_out;
  input Q4_out;

  wire Dbg_Clk;
  wire [5:0]Q;
  wire Q1_out;
  wire Q2_out;
  wire Q3_out;
  wire Q4_out;
  wire \Serial_Dbg_Intf.shift_count_reg[5] ;

  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    Dbg_TDO_INST_0_i_25
       (.I0(Q1_out),
        .I1(Q2_out),
        .I2(Q[5]),
        .I3(Q3_out),
        .I4(Q[4]),
        .I5(Q4_out),
        .O(\Serial_Dbg_Intf.shift_count_reg[5] ));
  (* box_type = "PRIMITIVE" *) 
  SRL16E #(
    .INIT(16'h3FFF),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q1_out));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized7
   (Q2_in,
    Q,
    Dbg_Clk);
  output Q2_in;
  input [3:0]Q;
  input Dbg_Clk;

  wire Dbg_Clk;
  wire [3:0]Q;
  wire Q2_in;

  (* box_type = "PRIMITIVE" *) 
  SRL16E #(
    .INIT(16'h0064),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q2_in));
endmodule

(* ORIG_REF_NAME = "MB_SRL16E" *) 
module design_1_microblaze_0_0_MB_SRL16E__parameterized9
   (Dbg_TDO,
    Q,
    Dbg_Clk,
    Data_Read_Reg_En,
    TDO_Data_Reg__31,
    Dbg_TDO_INST_0_i_2_0,
    Config_Reg_En,
    TDO_Instr_Reg__0,
    Instr_Insert_Reg_En,
    tdo_config_word1_0,
    Dbg_TDO_INST_0_i_5_0,
    Q2_in,
    Q3_in,
    Q0_out,
    Status_Reg_En,
    TDO_Status_Reg__17);
  output Dbg_TDO;
  input [7:0]Q;
  input Dbg_Clk;
  input Data_Read_Reg_En;
  input TDO_Data_Reg__31;
  input Dbg_TDO_INST_0_i_2_0;
  input Config_Reg_En;
  input TDO_Instr_Reg__0;
  input Instr_Insert_Reg_En;
  input tdo_config_word1_0;
  input Dbg_TDO_INST_0_i_5_0;
  input Q2_in;
  input Q3_in;
  input Q0_out;
  input Status_Reg_En;
  input TDO_Status_Reg__17;

  wire Config_Reg_En;
  wire Data_Read_Reg_En;
  wire Dbg_Clk;
  wire Dbg_TDO;
  wire Dbg_TDO_INST_0_i_12_n_0;
  wire Dbg_TDO_INST_0_i_23_n_0;
  wire Dbg_TDO_INST_0_i_2_0;
  wire Dbg_TDO_INST_0_i_2_n_0;
  wire Dbg_TDO_INST_0_i_5_0;
  wire Dbg_TDO_INST_0_i_5_n_0;
  wire Instr_Insert_Reg_En;
  wire [7:0]Q;
  wire Q0_out;
  wire Q1_in;
  wire Q2_in;
  wire Q3_in;
  wire Status_Reg_En;
  wire TDO_Data_Reg__31;
  wire TDO_Instr_Reg__0;
  wire TDO_Status_Reg__17;
  wire tdo_config_word1_0;

  LUT3 #(
    .INIT(8'hE4)) 
    Dbg_TDO_INST_0
       (.I0(Status_Reg_En),
        .I1(Dbg_TDO_INST_0_i_2_n_0),
        .I2(TDO_Status_Reg__17),
        .O(Dbg_TDO));
  LUT6 #(
    .INIT(64'hCA0ACACACA0A0A0A)) 
    Dbg_TDO_INST_0_i_12
       (.I0(Dbg_TDO_INST_0_i_23_n_0),
        .I1(Q[5]),
        .I2(Q[6]),
        .I3(tdo_config_word1_0),
        .I4(Q[4]),
        .I5(Dbg_TDO_INST_0_i_5_0),
        .O(Dbg_TDO_INST_0_i_12_n_0));
  MUXF7 Dbg_TDO_INST_0_i_2
       (.I0(Dbg_TDO_INST_0_i_5_n_0),
        .I1(TDO_Data_Reg__31),
        .O(Dbg_TDO_INST_0_i_2_n_0),
        .S(Data_Read_Reg_En));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    Dbg_TDO_INST_0_i_23
       (.I0(Q1_in),
        .I1(Q2_in),
        .I2(Q[5]),
        .I3(Q3_in),
        .I4(Q[4]),
        .I5(Q0_out),
        .O(Dbg_TDO_INST_0_i_23_n_0));
  LUT6 #(
    .INIT(64'hB8FFB800B800B800)) 
    Dbg_TDO_INST_0_i_5
       (.I0(Dbg_TDO_INST_0_i_12_n_0),
        .I1(Q[7]),
        .I2(Dbg_TDO_INST_0_i_2_0),
        .I3(Config_Reg_En),
        .I4(TDO_Instr_Reg__0),
        .I5(Instr_Insert_Reg_En),
        .O(Dbg_TDO_INST_0_i_5_n_0));
  (* box_type = "PRIMITIVE" *) 
  SRL16E #(
    .INIT(16'h2500),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16E_I1 
       (.A0(Q[0]),
        .A1(Q[1]),
        .A2(Q[2]),
        .A3(Q[3]),
        .CE(1'b0),
        .CLK(Dbg_Clk),
        .D(1'b0),
        .Q(Q1_in));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E
   (SRL16_Sel_7,
    which_pc__0,
    SRL16_MC15_7,
    Address,
    Dbg_Clk,
    Dbg_Reg_En);
  output SRL16_Sel_7;
  output which_pc__0;
  input SRL16_MC15_7;
  input [3:0]Address;
  input Dbg_Clk;
  input [0:7]Dbg_Reg_En;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire [0:7]Dbg_Reg_En;
  wire SRL16_MC15_7;
  wire SRL16_Sel_7;
  wire \Use_unisim.MB_SRL16CE_I1_i_2_n_0 ;
  wire \Use_unisim.MB_SRL16CE_I1_i_3_n_0 ;
  wire \Use_unisim.MB_SRL16CE_I1_n_1 ;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(SRL16_MC15_7),
        .Q(SRL16_Sel_7),
        .Q15(\Use_unisim.MB_SRL16CE_I1_n_1 ));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    \Use_unisim.MB_SRL16CE_I1_i_1 
       (.I0(Dbg_Reg_En[2]),
        .I1(Dbg_Reg_En[7]),
        .I2(\Use_unisim.MB_SRL16CE_I1_i_2_n_0 ),
        .I3(Dbg_Reg_En[6]),
        .I4(Dbg_Reg_En[3]),
        .I5(\Use_unisim.MB_SRL16CE_I1_i_3_n_0 ),
        .O(which_pc__0));
  LUT2 #(
    .INIT(4'hE)) 
    \Use_unisim.MB_SRL16CE_I1_i_2 
       (.I0(Dbg_Reg_En[1]),
        .I1(Dbg_Reg_En[0]),
        .O(\Use_unisim.MB_SRL16CE_I1_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \Use_unisim.MB_SRL16CE_I1_i_3 
       (.I0(Dbg_Reg_En[4]),
        .I1(Dbg_Reg_En[5]),
        .O(\Use_unisim.MB_SRL16CE_I1_i_3_n_0 ));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E_32
   (SRL16_Sel_6,
    SRL16_MC15_7,
    which_pc__0,
    SRL16_MC15_6,
    Address,
    Dbg_Clk);
  output SRL16_Sel_6;
  output SRL16_MC15_7;
  input which_pc__0;
  input SRL16_MC15_6;
  input [3:0]Address;
  input Dbg_Clk;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire SRL16_MC15_6;
  wire SRL16_MC15_7;
  wire SRL16_Sel_6;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(SRL16_MC15_6),
        .Q(SRL16_Sel_6),
        .Q15(SRL16_MC15_7));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E_34
   (SRL16_Sel_5,
    SRL16_MC15_6,
    which_pc__0,
    SRL16_MC15_5,
    Address,
    Dbg_Clk);
  output SRL16_Sel_5;
  output SRL16_MC15_6;
  input which_pc__0;
  input SRL16_MC15_5;
  input [3:0]Address;
  input Dbg_Clk;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire SRL16_MC15_5;
  wire SRL16_MC15_6;
  wire SRL16_Sel_5;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(SRL16_MC15_5),
        .Q(SRL16_Sel_5),
        .Q15(SRL16_MC15_6));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E_36
   (SRL16_Sel_4,
    SRL16_MC15_5,
    which_pc__0,
    SRL16_MC15_4,
    Address,
    Dbg_Clk);
  output SRL16_Sel_4;
  output SRL16_MC15_5;
  input which_pc__0;
  input SRL16_MC15_4;
  input [3:0]Address;
  input Dbg_Clk;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire SRL16_MC15_4;
  wire SRL16_MC15_5;
  wire SRL16_Sel_4;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(SRL16_MC15_4),
        .Q(SRL16_Sel_4),
        .Q15(SRL16_MC15_5));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E_38
   (SRL16_Sel_3,
    SRL16_MC15_4,
    which_pc__0,
    SRL16_MC15_3,
    Address,
    Dbg_Clk);
  output SRL16_Sel_3;
  output SRL16_MC15_4;
  input which_pc__0;
  input SRL16_MC15_3;
  input [3:0]Address;
  input Dbg_Clk;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire SRL16_MC15_3;
  wire SRL16_MC15_4;
  wire SRL16_Sel_3;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(SRL16_MC15_3),
        .Q(SRL16_Sel_3),
        .Q15(SRL16_MC15_4));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E_40
   (SRL16_Sel_2,
    SRL16_MC15_3,
    which_pc__0,
    SRL16_MC15_2,
    Address,
    Dbg_Clk);
  output SRL16_Sel_2;
  output SRL16_MC15_3;
  input which_pc__0;
  input SRL16_MC15_2;
  input [3:0]Address;
  input Dbg_Clk;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire SRL16_MC15_2;
  wire SRL16_MC15_3;
  wire SRL16_Sel_2;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(SRL16_MC15_2),
        .Q(SRL16_Sel_2),
        .Q15(SRL16_MC15_3));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E_42
   (SRL16_Sel_1,
    SRL16_MC15_2,
    which_pc__0,
    SRL16_MC15_1,
    Address,
    Dbg_Clk);
  output SRL16_Sel_1;
  output SRL16_MC15_2;
  input which_pc__0;
  input SRL16_MC15_1;
  input [3:0]Address;
  input Dbg_Clk;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire SRL16_MC15_1;
  wire SRL16_MC15_2;
  wire SRL16_Sel_1;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(SRL16_MC15_1),
        .Q(SRL16_Sel_1),
        .Q15(SRL16_MC15_2));
endmodule

(* ORIG_REF_NAME = "MB_SRLC16E" *) 
module design_1_microblaze_0_0_MB_SRLC16E_44
   (SRL16_Sel_0,
    SRL16_MC15_1,
    which_pc__0,
    Dbg_TDI,
    Address,
    Dbg_Clk);
  output SRL16_Sel_0;
  output SRL16_MC15_1;
  input which_pc__0;
  input Dbg_TDI;
  input [3:0]Address;
  input Dbg_Clk;

  wire [3:0]Address;
  wire Dbg_Clk;
  wire Dbg_TDI;
  wire SRL16_MC15_1;
  wire SRL16_Sel_0;
  wire which_pc__0;

  (* box_type = "PRIMITIVE" *) 
  SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
    \Use_unisim.MB_SRL16CE_I1 
       (.A0(Address[0]),
        .A1(Address[1]),
        .A2(Address[2]),
        .A3(Address[3]),
        .CE(which_pc__0),
        .CLK(Dbg_Clk),
        .D(Dbg_TDI),
        .Q(SRL16_Sel_0),
        .Q15(SRL16_MC15_1));
endmodule

(* C_ADDR_TAG_BITS = "17" *) (* C_ALLOW_DCACHE_WR = "1" *) (* C_ALLOW_ICACHE_WR = "1" *) 
(* C_AREA_OPTIMIZED = "0" *) (* C_ASYNC_INTERRUPT = "1" *) (* C_ASYNC_WAKEUP = "3" *) 
(* C_AVOID_PRIMITIVES = "0" *) (* C_BASE_VECTORS = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRANCH_TARGET_CACHE_SIZE = "0" *) 
(* C_CACHE_BYTE_SIZE = "8192" *) (* C_DADDR_SIZE = "32" *) (* C_DATA_SIZE = "32" *) 
(* C_DCACHE_ADDR_TAG = "17" *) (* C_DCACHE_ALWAYS_USED = "0" *) (* C_DCACHE_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) 
(* C_DCACHE_BYTE_SIZE = "8192" *) (* C_DCACHE_DATA_WIDTH = "0" *) (* C_DCACHE_FORCE_TAG_LUTRAM = "0" *) 
(* C_DCACHE_HIGHADDR = "64'b0000000000000000000000000000000000111111111111111111111111111111" *) (* C_DCACHE_LINE_LEN = "4" *) (* C_DCACHE_USE_WRITEBACK = "0" *) 
(* C_DCACHE_VICTIMS = "0" *) (* C_DEBUG_COUNTER_WIDTH = "32" *) (* C_DEBUG_ENABLED = "1" *) 
(* C_DEBUG_EVENT_COUNTERS = "5" *) (* C_DEBUG_EXTERNAL_TRACE = "0" *) (* C_DEBUG_INTERFACE = "0" *) 
(* C_DEBUG_LATENCY_COUNTERS = "1" *) (* C_DEBUG_PROFILE_SIZE = "0" *) (* C_DEBUG_TRACE_ASYNC_RESET = "0" *) 
(* C_DEBUG_TRACE_SIZE = "8192" *) (* C_DIV_ZERO_EXCEPTION = "0" *) (* C_DYNAMIC_BUS_SIZING = "0" *) 
(* C_D_AXI = "1" *) (* C_D_LMB = "1" *) (* C_ECC_USE_CE_EXCEPTION = "0" *) 
(* C_EDGE_IS_POSITIVE = "1" *) (* C_ENDIANNESS = "1" *) (* C_FAMILY = "kintexuplus" *) 
(* C_FAULT_TOLERANT = "0" *) (* C_FPU_EXCEPTION = "0" *) (* C_FREQ = "100000000" *) 
(* C_FSL_EXCEPTION = "0" *) (* C_FSL_LINKS = "0" *) (* C_IADDR_SIZE = "32" *) 
(* C_ICACHE_ALWAYS_USED = "0" *) (* C_ICACHE_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_ICACHE_DATA_WIDTH = "0" *) 
(* C_ICACHE_FORCE_TAG_LUTRAM = "0" *) (* C_ICACHE_HIGHADDR = "64'b0000000000000000000000000000000000111111111111111111111111111111" *) (* C_ICACHE_LINE_LEN = "4" *) 
(* C_ICACHE_STREAMS = "0" *) (* C_ICACHE_VICTIMS = "0" *) (* C_ILL_OPCODE_EXCEPTION = "0" *) 
(* C_IMPRECISE_EXCEPTIONS = "0" *) (* C_INSTANCE = "design_1_microblaze_0_0" *) (* C_INSTR_SIZE = "32" *) 
(* C_INTERCONNECT = "2" *) (* C_INTERRUPT_IS_EDGE = "0" *) (* C_I_AXI = "0" *) 
(* C_I_LMB = "1" *) (* C_LMB_DATA_SIZE = "32" *) (* C_LOCKSTEP_MASTER = "0" *) 
(* C_LOCKSTEP_SLAVE = "0" *) (* C_M0_AXIS_DATA_WIDTH = "32" *) (* C_M10_AXIS_DATA_WIDTH = "32" *) 
(* C_M11_AXIS_DATA_WIDTH = "32" *) (* C_M12_AXIS_DATA_WIDTH = "32" *) (* C_M13_AXIS_DATA_WIDTH = "32" *) 
(* C_M14_AXIS_DATA_WIDTH = "32" *) (* C_M15_AXIS_DATA_WIDTH = "32" *) (* C_M1_AXIS_DATA_WIDTH = "32" *) 
(* C_M2_AXIS_DATA_WIDTH = "32" *) (* C_M3_AXIS_DATA_WIDTH = "32" *) (* C_M4_AXIS_DATA_WIDTH = "32" *) 
(* C_M5_AXIS_DATA_WIDTH = "32" *) (* C_M6_AXIS_DATA_WIDTH = "32" *) (* C_M7_AXIS_DATA_WIDTH = "32" *) 
(* C_M8_AXIS_DATA_WIDTH = "32" *) (* C_M9_AXIS_DATA_WIDTH = "32" *) (* C_MMU_DTLB_SIZE = "4" *) 
(* C_MMU_ITLB_SIZE = "2" *) (* C_MMU_PRIVILEGED_INSTR = "0" *) (* C_MMU_TLB_ACCESS = "3" *) 
(* C_MMU_ZONES = "16" *) (* C_M_AXI_DC_ADDR_WIDTH = "32" *) (* C_M_AXI_DC_ARUSER_WIDTH = "5" *) 
(* C_M_AXI_DC_AWUSER_WIDTH = "5" *) (* C_M_AXI_DC_BUSER_WIDTH = "1" *) (* C_M_AXI_DC_DATA_WIDTH = "32" *) 
(* C_M_AXI_DC_EXCLUSIVE_ACCESS = "0" *) (* C_M_AXI_DC_RUSER_WIDTH = "1" *) (* C_M_AXI_DC_THREAD_ID_WIDTH = "1" *) 
(* C_M_AXI_DC_USER_VALUE = "31" *) (* C_M_AXI_DC_WUSER_WIDTH = "1" *) (* C_M_AXI_DP_ADDR_WIDTH = "32" *) 
(* C_M_AXI_DP_DATA_WIDTH = "32" *) (* C_M_AXI_DP_EXCLUSIVE_ACCESS = "0" *) (* C_M_AXI_DP_THREAD_ID_WIDTH = "1" *) 
(* C_M_AXI_D_BUS_EXCEPTION = "0" *) (* C_M_AXI_IC_ADDR_WIDTH = "32" *) (* C_M_AXI_IC_ARUSER_WIDTH = "5" *) 
(* C_M_AXI_IC_AWUSER_WIDTH = "5" *) (* C_M_AXI_IC_BUSER_WIDTH = "1" *) (* C_M_AXI_IC_DATA_WIDTH = "32" *) 
(* C_M_AXI_IC_RUSER_WIDTH = "1" *) (* C_M_AXI_IC_THREAD_ID_WIDTH = "1" *) (* C_M_AXI_IC_USER_VALUE = "31" *) 
(* C_M_AXI_IC_WUSER_WIDTH = "1" *) (* C_M_AXI_IP_ADDR_WIDTH = "32" *) (* C_M_AXI_IP_DATA_WIDTH = "32" *) 
(* C_M_AXI_IP_THREAD_ID_WIDTH = "1" *) (* C_M_AXI_I_BUS_EXCEPTION = "0" *) (* C_NUMBER_OF_PC_BRK = "1" *) 
(* C_NUMBER_OF_RD_ADDR_BRK = "0" *) (* C_NUMBER_OF_WR_ADDR_BRK = "0" *) (* C_NUM_SYNC_FF_CLK = "2" *) 
(* C_NUM_SYNC_FF_CLK_DEBUG = "2" *) (* C_NUM_SYNC_FF_CLK_IRQ = "1" *) (* C_NUM_SYNC_FF_DBG_CLK = "1" *) 
(* C_NUM_SYNC_FF_DBG_TRACE_CLK = "2" *) (* C_OPCODE_0x0_ILLEGAL = "0" *) (* C_OPTIMIZATION = "0" *) 
(* C_PC_WIDTH = "32" *) (* C_PIADDR_SIZE = "32" *) (* C_PVR = "0" *) 
(* C_PVR_USER1 = "8'b00000000" *) (* C_PVR_USER2 = "0" *) (* C_RESET_MSR = "0" *) 
(* C_S0_AXIS_DATA_WIDTH = "32" *) (* C_S10_AXIS_DATA_WIDTH = "32" *) (* C_S11_AXIS_DATA_WIDTH = "32" *) 
(* C_S12_AXIS_DATA_WIDTH = "32" *) (* C_S13_AXIS_DATA_WIDTH = "32" *) (* C_S14_AXIS_DATA_WIDTH = "32" *) 
(* C_S15_AXIS_DATA_WIDTH = "32" *) (* C_S1_AXIS_DATA_WIDTH = "32" *) (* C_S2_AXIS_DATA_WIDTH = "32" *) 
(* C_S3_AXIS_DATA_WIDTH = "32" *) (* C_S4_AXIS_DATA_WIDTH = "32" *) (* C_S5_AXIS_DATA_WIDTH = "32" *) 
(* C_S6_AXIS_DATA_WIDTH = "32" *) (* C_S7_AXIS_DATA_WIDTH = "32" *) (* C_S8_AXIS_DATA_WIDTH = "32" *) 
(* C_S9_AXIS_DATA_WIDTH = "32" *) (* C_SCO = "0" *) (* C_UNALIGNED_EXCEPTIONS = "0" *) 
(* C_USE_BARREL = "0" *) (* C_USE_BRANCH_TARGET_CACHE = "0" *) (* C_USE_CONFIG_RESET = "0" *) 
(* C_USE_DCACHE = "0" *) (* C_USE_DIV = "0" *) (* C_USE_EXTENDED_FSL_INSTR = "0" *) 
(* C_USE_EXT_BRK = "0" *) (* C_USE_EXT_NM_BRK = "0" *) (* C_USE_FPU = "0" *) 
(* C_USE_HW_MUL = "0" *) (* C_USE_ICACHE = "0" *) (* C_USE_INTERRUPT = "0" *) 
(* C_USE_MMU = "0" *) (* C_USE_MSR_INSTR = "0" *) (* C_USE_NON_SECURE = "0" *) 
(* C_USE_PCMP_INSTR = "0" *) (* C_USE_REORDER_INSTR = "1" *) (* C_USE_STACK_PROTECTION = "0" *) 
(* ORIG_REF_NAME = "MicroBlaze" *) (* downgradeipidentifiedwarnings = "yes" *) 
module design_1_microblaze_0_0_MicroBlaze
   (RAM_To,
    RAM_From,
    Clk,
    Reset,
    Mb_Reset,
    Config_Reset,
    Scan_Reset_Sel,
    Scan_Reset,
    Scan_En,
    Reset_Mode,
    Non_Secure,
    Interrupt,
    Interrupt_Address,
    Interrupt_Ack,
    Ext_BRK,
    Ext_NM_BRK,
    Pause,
    Pause_Ack,
    Dbg_Continue,
    Dbg_Stop,
    Dbg_Intr,
    MB_Halted,
    MB_Error,
    Wakeup,
    Sleep,
    Hibernate,
    Suspend,
    Dbg_Wakeup,
    LOCKSTEP_Slave_In,
    LOCKSTEP_Master_Out,
    LOCKSTEP_Out,
    Instr_Addr,
    Instr,
    IFetch,
    I_AS,
    IReady,
    IWAIT,
    ICE,
    IUE,
    M_AXI_IP_AWID,
    M_AXI_IP_AWADDR,
    M_AXI_IP_AWLEN,
    M_AXI_IP_AWSIZE,
    M_AXI_IP_AWBURST,
    M_AXI_IP_AWLOCK,
    M_AXI_IP_AWCACHE,
    M_AXI_IP_AWPROT,
    M_AXI_IP_AWQOS,
    M_AXI_IP_AWVALID,
    M_AXI_IP_AWREADY,
    M_AXI_IP_WDATA,
    M_AXI_IP_WSTRB,
    M_AXI_IP_WLAST,
    M_AXI_IP_WVALID,
    M_AXI_IP_WREADY,
    M_AXI_IP_BID,
    M_AXI_IP_BRESP,
    M_AXI_IP_BVALID,
    M_AXI_IP_BREADY,
    M_AXI_IP_ARID,
    M_AXI_IP_ARADDR,
    M_AXI_IP_ARLEN,
    M_AXI_IP_ARSIZE,
    M_AXI_IP_ARBURST,
    M_AXI_IP_ARLOCK,
    M_AXI_IP_ARCACHE,
    M_AXI_IP_ARPROT,
    M_AXI_IP_ARQOS,
    M_AXI_IP_ARVALID,
    M_AXI_IP_ARREADY,
    M_AXI_IP_RID,
    M_AXI_IP_RDATA,
    M_AXI_IP_RRESP,
    M_AXI_IP_RLAST,
    M_AXI_IP_RVALID,
    M_AXI_IP_RREADY,
    Data_Addr,
    Data_Read,
    Data_Write,
    D_AS,
    Read_Strobe,
    Write_Strobe,
    DReady,
    DWait,
    DCE,
    DUE,
    Byte_Enable,
    M_AXI_DP_AWID,
    M_AXI_DP_AWADDR,
    M_AXI_DP_AWLEN,
    M_AXI_DP_AWSIZE,
    M_AXI_DP_AWBURST,
    M_AXI_DP_AWLOCK,
    M_AXI_DP_AWCACHE,
    M_AXI_DP_AWPROT,
    M_AXI_DP_AWQOS,
    M_AXI_DP_AWVALID,
    M_AXI_DP_AWREADY,
    M_AXI_DP_WDATA,
    M_AXI_DP_WSTRB,
    M_AXI_DP_WLAST,
    M_AXI_DP_WVALID,
    M_AXI_DP_WREADY,
    M_AXI_DP_BID,
    M_AXI_DP_BRESP,
    M_AXI_DP_BVALID,
    M_AXI_DP_BREADY,
    M_AXI_DP_ARID,
    M_AXI_DP_ARADDR,
    M_AXI_DP_ARLEN,
    M_AXI_DP_ARSIZE,
    M_AXI_DP_ARBURST,
    M_AXI_DP_ARLOCK,
    M_AXI_DP_ARCACHE,
    M_AXI_DP_ARPROT,
    M_AXI_DP_ARQOS,
    M_AXI_DP_ARVALID,
    M_AXI_DP_ARREADY,
    M_AXI_DP_RID,
    M_AXI_DP_RDATA,
    M_AXI_DP_RRESP,
    M_AXI_DP_RLAST,
    M_AXI_DP_RVALID,
    M_AXI_DP_RREADY,
    Dbg_Disable,
    Dbg_Clk,
    Dbg_TDI,
    Dbg_TDO,
    Dbg_Reg_En,
    Dbg_Shift,
    Dbg_Capture,
    Dbg_Update,
    Debug_Rst,
    Dbg_Trig_In,
    Dbg_Trig_Ack_In,
    Dbg_Trig_Out,
    Dbg_Trig_Ack_Out,
    Dbg_Trace_Clk,
    Dbg_Trace_Data,
    Dbg_Trace_Ready,
    Dbg_Trace_Valid,
    Dbg_AWADDR,
    Dbg_AWVALID,
    Dbg_AWREADY,
    Dbg_WDATA,
    Dbg_WVALID,
    Dbg_WREADY,
    Dbg_BRESP,
    Dbg_BVALID,
    Dbg_BREADY,
    Dbg_ARADDR,
    Dbg_ARVALID,
    Dbg_ARREADY,
    Dbg_RDATA,
    Dbg_RRESP,
    Dbg_RVALID,
    Dbg_RREADY,
    DEBUG_ACLK,
    DEBUG_ARESETN,
    Trace_Instruction,
    Trace_Valid_Instr,
    Trace_PC,
    Trace_Reg_Write,
    Trace_Reg_Addr,
    Trace_MSR_Reg,
    Trace_PID_Reg,
    Trace_New_Reg_Value,
    Trace_Exception_Taken,
    Trace_Exception_Kind,
    Trace_Jump_Taken,
    Trace_Delay_Slot,
    Trace_Data_Address,
    Trace_Data_Write_Value,
    Trace_Data_Byte_Enable,
    Trace_Data_Access,
    Trace_Data_Read,
    Trace_Data_Write,
    Trace_DCache_Req,
    Trace_DCache_Hit,
    Trace_DCache_Rdy,
    Trace_DCache_Read,
    Trace_ICache_Req,
    Trace_ICache_Hit,
    Trace_ICache_Rdy,
    Trace_OF_PipeRun,
    Trace_EX_PipeRun,
    Trace_MEM_PipeRun,
    Trace_MB_Halted,
    Trace_Jump_Hit,
    M0_AXIS_TLAST,
    M0_AXIS_TDATA,
    M0_AXIS_TVALID,
    M0_AXIS_TREADY,
    M1_AXIS_TLAST,
    M1_AXIS_TDATA,
    M1_AXIS_TVALID,
    M1_AXIS_TREADY,
    M2_AXIS_TLAST,
    M2_AXIS_TDATA,
    M2_AXIS_TVALID,
    M2_AXIS_TREADY,
    M3_AXIS_TLAST,
    M3_AXIS_TDATA,
    M3_AXIS_TVALID,
    M3_AXIS_TREADY,
    M4_AXIS_TLAST,
    M4_AXIS_TDATA,
    M4_AXIS_TVALID,
    M4_AXIS_TREADY,
    M5_AXIS_TLAST,
    M5_AXIS_TDATA,
    M5_AXIS_TVALID,
    M5_AXIS_TREADY,
    M6_AXIS_TLAST,
    M6_AXIS_TDATA,
    M6_AXIS_TVALID,
    M6_AXIS_TREADY,
    M7_AXIS_TLAST,
    M7_AXIS_TDATA,
    M7_AXIS_TVALID,
    M7_AXIS_TREADY,
    M8_AXIS_TLAST,
    M8_AXIS_TDATA,
    M8_AXIS_TVALID,
    M8_AXIS_TREADY,
    M9_AXIS_TLAST,
    M9_AXIS_TDATA,
    M9_AXIS_TVALID,
    M9_AXIS_TREADY,
    M10_AXIS_TLAST,
    M10_AXIS_TDATA,
    M10_AXIS_TVALID,
    M10_AXIS_TREADY,
    M11_AXIS_TLAST,
    M11_AXIS_TDATA,
    M11_AXIS_TVALID,
    M11_AXIS_TREADY,
    M12_AXIS_TLAST,
    M12_AXIS_TDATA,
    M12_AXIS_TVALID,
    M12_AXIS_TREADY,
    M13_AXIS_TLAST,
    M13_AXIS_TDATA,
    M13_AXIS_TVALID,
    M13_AXIS_TREADY,
    M14_AXIS_TLAST,
    M14_AXIS_TDATA,
    M14_AXIS_TVALID,
    M14_AXIS_TREADY,
    M15_AXIS_TLAST,
    M15_AXIS_TDATA,
    M15_AXIS_TVALID,
    M15_AXIS_TREADY,
    S0_AXIS_TLAST,
    S0_AXIS_TDATA,
    S0_AXIS_TVALID,
    S0_AXIS_TREADY,
    S1_AXIS_TLAST,
    S1_AXIS_TDATA,
    S1_AXIS_TVALID,
    S1_AXIS_TREADY,
    S2_AXIS_TLAST,
    S2_AXIS_TDATA,
    S2_AXIS_TVALID,
    S2_AXIS_TREADY,
    S3_AXIS_TLAST,
    S3_AXIS_TDATA,
    S3_AXIS_TVALID,
    S3_AXIS_TREADY,
    S4_AXIS_TLAST,
    S4_AXIS_TDATA,
    S4_AXIS_TVALID,
    S4_AXIS_TREADY,
    S5_AXIS_TLAST,
    S5_AXIS_TDATA,
    S5_AXIS_TVALID,
    S5_AXIS_TREADY,
    S6_AXIS_TLAST,
    S6_AXIS_TDATA,
    S6_AXIS_TVALID,
    S6_AXIS_TREADY,
    S7_AXIS_TLAST,
    S7_AXIS_TDATA,
    S7_AXIS_TVALID,
    S7_AXIS_TREADY,
    S8_AXIS_TLAST,
    S8_AXIS_TDATA,
    S8_AXIS_TVALID,
    S8_AXIS_TREADY,
    S9_AXIS_TLAST,
    S9_AXIS_TDATA,
    S9_AXIS_TVALID,
    S9_AXIS_TREADY,
    S10_AXIS_TLAST,
    S10_AXIS_TDATA,
    S10_AXIS_TVALID,
    S10_AXIS_TREADY,
    S11_AXIS_TLAST,
    S11_AXIS_TDATA,
    S11_AXIS_TVALID,
    S11_AXIS_TREADY,
    S12_AXIS_TLAST,
    S12_AXIS_TDATA,
    S12_AXIS_TVALID,
    S12_AXIS_TREADY,
    S13_AXIS_TLAST,
    S13_AXIS_TDATA,
    S13_AXIS_TVALID,
    S13_AXIS_TREADY,
    S14_AXIS_TLAST,
    S14_AXIS_TDATA,
    S14_AXIS_TVALID,
    S14_AXIS_TREADY,
    S15_AXIS_TLAST,
    S15_AXIS_TDATA,
    S15_AXIS_TVALID,
    S15_AXIS_TREADY,
    M_AXI_IC_AWID,
    M_AXI_IC_AWADDR,
    M_AXI_IC_AWLEN,
    M_AXI_IC_AWSIZE,
    M_AXI_IC_AWBURST,
    M_AXI_IC_AWLOCK,
    M_AXI_IC_AWCACHE,
    M_AXI_IC_AWPROT,
    M_AXI_IC_AWQOS,
    M_AXI_IC_AWVALID,
    M_AXI_IC_AWREADY,
    M_AXI_IC_AWUSER,
    M_AXI_IC_AWDOMAIN,
    M_AXI_IC_AWSNOOP,
    M_AXI_IC_AWBAR,
    M_AXI_IC_WDATA,
    M_AXI_IC_WSTRB,
    M_AXI_IC_WLAST,
    M_AXI_IC_WVALID,
    M_AXI_IC_WREADY,
    M_AXI_IC_WUSER,
    M_AXI_IC_BID,
    M_AXI_IC_BRESP,
    M_AXI_IC_BVALID,
    M_AXI_IC_BREADY,
    M_AXI_IC_BUSER,
    M_AXI_IC_WACK,
    M_AXI_IC_ARID,
    M_AXI_IC_ARADDR,
    M_AXI_IC_ARLEN,
    M_AXI_IC_ARSIZE,
    M_AXI_IC_ARBURST,
    M_AXI_IC_ARLOCK,
    M_AXI_IC_ARCACHE,
    M_AXI_IC_ARPROT,
    M_AXI_IC_ARQOS,
    M_AXI_IC_ARVALID,
    M_AXI_IC_ARREADY,
    M_AXI_IC_ARUSER,
    M_AXI_IC_ARDOMAIN,
    M_AXI_IC_ARSNOOP,
    M_AXI_IC_ARBAR,
    M_AXI_IC_RID,
    M_AXI_IC_RDATA,
    M_AXI_IC_RRESP,
    M_AXI_IC_RLAST,
    M_AXI_IC_RVALID,
    M_AXI_IC_RREADY,
    M_AXI_IC_RUSER,
    M_AXI_IC_RACK,
    M_AXI_IC_ACVALID,
    M_AXI_IC_ACADDR,
    M_AXI_IC_ACSNOOP,
    M_AXI_IC_ACPROT,
    M_AXI_IC_ACREADY,
    M_AXI_IC_CRVALID,
    M_AXI_IC_CRRESP,
    M_AXI_IC_CRREADY,
    M_AXI_IC_CDVALID,
    M_AXI_IC_CDDATA,
    M_AXI_IC_CDLAST,
    M_AXI_IC_CDREADY,
    M_AXI_DC_AWID,
    M_AXI_DC_AWADDR,
    M_AXI_DC_AWLEN,
    M_AXI_DC_AWSIZE,
    M_AXI_DC_AWBURST,
    M_AXI_DC_AWLOCK,
    M_AXI_DC_AWCACHE,
    M_AXI_DC_AWPROT,
    M_AXI_DC_AWQOS,
    M_AXI_DC_AWVALID,
    M_AXI_DC_AWREADY,
    M_AXI_DC_AWUSER,
    M_AXI_DC_AWDOMAIN,
    M_AXI_DC_AWSNOOP,
    M_AXI_DC_AWBAR,
    M_AXI_DC_WDATA,
    M_AXI_DC_WSTRB,
    M_AXI_DC_WLAST,
    M_AXI_DC_WVALID,
    M_AXI_DC_WREADY,
    M_AXI_DC_WUSER,
    M_AXI_DC_BRESP,
    M_AXI_DC_BID,
    M_AXI_DC_BVALID,
    M_AXI_DC_BREADY,
    M_AXI_DC_BUSER,
    M_AXI_DC_WACK,
    M_AXI_DC_ARID,
    M_AXI_DC_ARADDR,
    M_AXI_DC_ARLEN,
    M_AXI_DC_ARSIZE,
    M_AXI_DC_ARBURST,
    M_AXI_DC_ARLOCK,
    M_AXI_DC_ARCACHE,
    M_AXI_DC_ARPROT,
    M_AXI_DC_ARQOS,
    M_AXI_DC_ARVALID,
    M_AXI_DC_ARREADY,
    M_AXI_DC_ARUSER,
    M_AXI_DC_ARDOMAIN,
    M_AXI_DC_ARSNOOP,
    M_AXI_DC_ARBAR,
    M_AXI_DC_RID,
    M_AXI_DC_RDATA,
    M_AXI_DC_RRESP,
    M_AXI_DC_RLAST,
    M_AXI_DC_RVALID,
    M_AXI_DC_RREADY,
    M_AXI_DC_RUSER,
    M_AXI_DC_RACK,
    M_AXI_DC_ACVALID,
    M_AXI_DC_ACADDR,
    M_AXI_DC_ACSNOOP,
    M_AXI_DC_ACPROT,
    M_AXI_DC_ACREADY,
    M_AXI_DC_CRVALID,
    M_AXI_DC_CRRESP,
    M_AXI_DC_CRREADY,
    M_AXI_DC_CDVALID,
    M_AXI_DC_CDDATA,
    M_AXI_DC_CDLAST,
    M_AXI_DC_CDREADY);
  input [255:0]RAM_To;
  output [255:0]RAM_From;
  input Clk;
  input Reset;
  input Mb_Reset;
  input Config_Reset;
  input Scan_Reset_Sel;
  input Scan_Reset;
  input Scan_En;
  input [0:1]Reset_Mode;
  input [0:3]Non_Secure;
  input Interrupt;
  input [0:31]Interrupt_Address;
  output [0:1]Interrupt_Ack;
  input Ext_BRK;
  input Ext_NM_BRK;
  input Pause;
  output Pause_Ack;
  output Dbg_Continue;
  input Dbg_Stop;
  output Dbg_Intr;
  output MB_Halted;
  output MB_Error;
  input [0:1]Wakeup;
  output Sleep;
  output Hibernate;
  output Suspend;
  output Dbg_Wakeup;
  input [0:4095]LOCKSTEP_Slave_In;
  output [0:4095]LOCKSTEP_Master_Out;
  output [0:4095]LOCKSTEP_Out;
  output [0:31]Instr_Addr;
  input [0:31]Instr;
  output IFetch;
  output I_AS;
  input IReady;
  input IWAIT;
  input ICE;
  input IUE;
  output [0:0]M_AXI_IP_AWID;
  output [31:0]M_AXI_IP_AWADDR;
  output [7:0]M_AXI_IP_AWLEN;
  output [2:0]M_AXI_IP_AWSIZE;
  output [1:0]M_AXI_IP_AWBURST;
  output M_AXI_IP_AWLOCK;
  output [3:0]M_AXI_IP_AWCACHE;
  output [2:0]M_AXI_IP_AWPROT;
  output [3:0]M_AXI_IP_AWQOS;
  output M_AXI_IP_AWVALID;
  input M_AXI_IP_AWREADY;
  output [31:0]M_AXI_IP_WDATA;
  output [3:0]M_AXI_IP_WSTRB;
  output M_AXI_IP_WLAST;
  output M_AXI_IP_WVALID;
  input M_AXI_IP_WREADY;
  input [0:0]M_AXI_IP_BID;
  input [1:0]M_AXI_IP_BRESP;
  input M_AXI_IP_BVALID;
  output M_AXI_IP_BREADY;
  output [0:0]M_AXI_IP_ARID;
  output [31:0]M_AXI_IP_ARADDR;
  output [7:0]M_AXI_IP_ARLEN;
  output [2:0]M_AXI_IP_ARSIZE;
  output [1:0]M_AXI_IP_ARBURST;
  output M_AXI_IP_ARLOCK;
  output [3:0]M_AXI_IP_ARCACHE;
  output [2:0]M_AXI_IP_ARPROT;
  output [3:0]M_AXI_IP_ARQOS;
  output M_AXI_IP_ARVALID;
  input M_AXI_IP_ARREADY;
  input [0:0]M_AXI_IP_RID;
  input [31:0]M_AXI_IP_RDATA;
  input [1:0]M_AXI_IP_RRESP;
  input M_AXI_IP_RLAST;
  input M_AXI_IP_RVALID;
  output M_AXI_IP_RREADY;
  output [0:31]Data_Addr;
  input [0:31]Data_Read;
  output [0:31]Data_Write;
  output D_AS;
  output Read_Strobe;
  output Write_Strobe;
  input DReady;
  input DWait;
  input DCE;
  input DUE;
  output [0:3]Byte_Enable;
  output [0:0]M_AXI_DP_AWID;
  output [31:0]M_AXI_DP_AWADDR;
  output [7:0]M_AXI_DP_AWLEN;
  output [2:0]M_AXI_DP_AWSIZE;
  output [1:0]M_AXI_DP_AWBURST;
  output M_AXI_DP_AWLOCK;
  output [3:0]M_AXI_DP_AWCACHE;
  output [2:0]M_AXI_DP_AWPROT;
  output [3:0]M_AXI_DP_AWQOS;
  output M_AXI_DP_AWVALID;
  input M_AXI_DP_AWREADY;
  output [31:0]M_AXI_DP_WDATA;
  output [3:0]M_AXI_DP_WSTRB;
  output M_AXI_DP_WLAST;
  output M_AXI_DP_WVALID;
  input M_AXI_DP_WREADY;
  input [0:0]M_AXI_DP_BID;
  input [1:0]M_AXI_DP_BRESP;
  input M_AXI_DP_BVALID;
  output M_AXI_DP_BREADY;
  output [0:0]M_AXI_DP_ARID;
  output [31:0]M_AXI_DP_ARADDR;
  output [7:0]M_AXI_DP_ARLEN;
  output [2:0]M_AXI_DP_ARSIZE;
  output [1:0]M_AXI_DP_ARBURST;
  output M_AXI_DP_ARLOCK;
  output [3:0]M_AXI_DP_ARCACHE;
  output [2:0]M_AXI_DP_ARPROT;
  output [3:0]M_AXI_DP_ARQOS;
  output M_AXI_DP_ARVALID;
  input M_AXI_DP_ARREADY;
  input [0:0]M_AXI_DP_RID;
  input [31:0]M_AXI_DP_RDATA;
  input [1:0]M_AXI_DP_RRESP;
  input M_AXI_DP_RLAST;
  input M_AXI_DP_RVALID;
  output M_AXI_DP_RREADY;
  input Dbg_Disable;
  input Dbg_Clk;
  input Dbg_TDI;
  output Dbg_TDO;
  input [0:7]Dbg_Reg_En;
  input Dbg_Shift;
  input Dbg_Capture;
  input Dbg_Update;
  input Debug_Rst;
  output [0:7]Dbg_Trig_In;
  input [0:7]Dbg_Trig_Ack_In;
  input [0:7]Dbg_Trig_Out;
  output [0:7]Dbg_Trig_Ack_Out;
  input Dbg_Trace_Clk;
  output [0:35]Dbg_Trace_Data;
  input Dbg_Trace_Ready;
  output Dbg_Trace_Valid;
  input [14:2]Dbg_AWADDR;
  input Dbg_AWVALID;
  output Dbg_AWREADY;
  input [31:0]Dbg_WDATA;
  input Dbg_WVALID;
  output Dbg_WREADY;
  output [1:0]Dbg_BRESP;
  output Dbg_BVALID;
  input Dbg_BREADY;
  input [14:2]Dbg_ARADDR;
  input Dbg_ARVALID;
  output Dbg_ARREADY;
  output [31:0]Dbg_RDATA;
  output [1:0]Dbg_RRESP;
  output Dbg_RVALID;
  input Dbg_RREADY;
  input DEBUG_ACLK;
  input DEBUG_ARESETN;
  (* mark_debug = "false" *) output [0:31]Trace_Instruction;
  (* mark_debug = "false" *) output Trace_Valid_Instr;
  (* mark_debug = "false" *) output [0:31]Trace_PC;
  (* mark_debug = "false" *) output Trace_Reg_Write;
  (* mark_debug = "false" *) output [0:4]Trace_Reg_Addr;
  (* mark_debug = "false" *) output [0:14]Trace_MSR_Reg;
  (* mark_debug = "false" *) output [0:7]Trace_PID_Reg;
  (* mark_debug = "false" *) output [0:31]Trace_New_Reg_Value;
  (* mark_debug = "false" *) output Trace_Exception_Taken;
  (* mark_debug = "false" *) output [0:4]Trace_Exception_Kind;
  (* mark_debug = "false" *) output Trace_Jump_Taken;
  (* mark_debug = "false" *) output Trace_Delay_Slot;
  (* mark_debug = "false" *) output [0:31]Trace_Data_Address;
  (* mark_debug = "false" *) output [0:31]Trace_Data_Write_Value;
  (* mark_debug = "false" *) output [0:3]Trace_Data_Byte_Enable;
  (* mark_debug = "false" *) output Trace_Data_Access;
  (* mark_debug = "false" *) output Trace_Data_Read;
  (* mark_debug = "false" *) output Trace_Data_Write;
  (* mark_debug = "false" *) output Trace_DCache_Req;
  (* mark_debug = "false" *) output Trace_DCache_Hit;
  (* mark_debug = "false" *) output Trace_DCache_Rdy;
  (* mark_debug = "false" *) output Trace_DCache_Read;
  (* mark_debug = "false" *) output Trace_ICache_Req;
  (* mark_debug = "false" *) output Trace_ICache_Hit;
  (* mark_debug = "false" *) output Trace_ICache_Rdy;
  (* mark_debug = "false" *) output Trace_OF_PipeRun;
  (* mark_debug = "false" *) output Trace_EX_PipeRun;
  (* mark_debug = "false" *) output Trace_MEM_PipeRun;
  (* mark_debug = "false" *) output Trace_MB_Halted;
  (* mark_debug = "false" *) output Trace_Jump_Hit;
  output M0_AXIS_TLAST;
  output [31:0]M0_AXIS_TDATA;
  output M0_AXIS_TVALID;
  input M0_AXIS_TREADY;
  output M1_AXIS_TLAST;
  output [31:0]M1_AXIS_TDATA;
  output M1_AXIS_TVALID;
  input M1_AXIS_TREADY;
  output M2_AXIS_TLAST;
  output [31:0]M2_AXIS_TDATA;
  output M2_AXIS_TVALID;
  input M2_AXIS_TREADY;
  output M3_AXIS_TLAST;
  output [31:0]M3_AXIS_TDATA;
  output M3_AXIS_TVALID;
  input M3_AXIS_TREADY;
  output M4_AXIS_TLAST;
  output [31:0]M4_AXIS_TDATA;
  output M4_AXIS_TVALID;
  input M4_AXIS_TREADY;
  output M5_AXIS_TLAST;
  output [31:0]M5_AXIS_TDATA;
  output M5_AXIS_TVALID;
  input M5_AXIS_TREADY;
  output M6_AXIS_TLAST;
  output [31:0]M6_AXIS_TDATA;
  output M6_AXIS_TVALID;
  input M6_AXIS_TREADY;
  output M7_AXIS_TLAST;
  output [31:0]M7_AXIS_TDATA;
  output M7_AXIS_TVALID;
  input M7_AXIS_TREADY;
  output M8_AXIS_TLAST;
  output [31:0]M8_AXIS_TDATA;
  output M8_AXIS_TVALID;
  input M8_AXIS_TREADY;
  output M9_AXIS_TLAST;
  output [31:0]M9_AXIS_TDATA;
  output M9_AXIS_TVALID;
  input M9_AXIS_TREADY;
  output M10_AXIS_TLAST;
  output [31:0]M10_AXIS_TDATA;
  output M10_AXIS_TVALID;
  input M10_AXIS_TREADY;
  output M11_AXIS_TLAST;
  output [31:0]M11_AXIS_TDATA;
  output M11_AXIS_TVALID;
  input M11_AXIS_TREADY;
  output M12_AXIS_TLAST;
  output [31:0]M12_AXIS_TDATA;
  output M12_AXIS_TVALID;
  input M12_AXIS_TREADY;
  output M13_AXIS_TLAST;
  output [31:0]M13_AXIS_TDATA;
  output M13_AXIS_TVALID;
  input M13_AXIS_TREADY;
  output M14_AXIS_TLAST;
  output [31:0]M14_AXIS_TDATA;
  output M14_AXIS_TVALID;
  input M14_AXIS_TREADY;
  output M15_AXIS_TLAST;
  output [31:0]M15_AXIS_TDATA;
  output M15_AXIS_TVALID;
  input M15_AXIS_TREADY;
  input S0_AXIS_TLAST;
  input [31:0]S0_AXIS_TDATA;
  input S0_AXIS_TVALID;
  output S0_AXIS_TREADY;
  input S1_AXIS_TLAST;
  input [31:0]S1_AXIS_TDATA;
  input S1_AXIS_TVALID;
  output S1_AXIS_TREADY;
  input S2_AXIS_TLAST;
  input [31:0]S2_AXIS_TDATA;
  input S2_AXIS_TVALID;
  output S2_AXIS_TREADY;
  input S3_AXIS_TLAST;
  input [31:0]S3_AXIS_TDATA;
  input S3_AXIS_TVALID;
  output S3_AXIS_TREADY;
  input S4_AXIS_TLAST;
  input [31:0]S4_AXIS_TDATA;
  input S4_AXIS_TVALID;
  output S4_AXIS_TREADY;
  input S5_AXIS_TLAST;
  input [31:0]S5_AXIS_TDATA;
  input S5_AXIS_TVALID;
  output S5_AXIS_TREADY;
  input S6_AXIS_TLAST;
  input [31:0]S6_AXIS_TDATA;
  input S6_AXIS_TVALID;
  output S6_AXIS_TREADY;
  input S7_AXIS_TLAST;
  input [31:0]S7_AXIS_TDATA;
  input S7_AXIS_TVALID;
  output S7_AXIS_TREADY;
  input S8_AXIS_TLAST;
  input [31:0]S8_AXIS_TDATA;
  input S8_AXIS_TVALID;
  output S8_AXIS_TREADY;
  input S9_AXIS_TLAST;
  input [31:0]S9_AXIS_TDATA;
  input S9_AXIS_TVALID;
  output S9_AXIS_TREADY;
  input S10_AXIS_TLAST;
  input [31:0]S10_AXIS_TDATA;
  input S10_AXIS_TVALID;
  output S10_AXIS_TREADY;
  input S11_AXIS_TLAST;
  input [31:0]S11_AXIS_TDATA;
  input S11_AXIS_TVALID;
  output S11_AXIS_TREADY;
  input S12_AXIS_TLAST;
  input [31:0]S12_AXIS_TDATA;
  input S12_AXIS_TVALID;
  output S12_AXIS_TREADY;
  input S13_AXIS_TLAST;
  input [31:0]S13_AXIS_TDATA;
  input S13_AXIS_TVALID;
  output S13_AXIS_TREADY;
  input S14_AXIS_TLAST;
  input [31:0]S14_AXIS_TDATA;
  input S14_AXIS_TVALID;
  output S14_AXIS_TREADY;
  input S15_AXIS_TLAST;
  input [31:0]S15_AXIS_TDATA;
  input S15_AXIS_TVALID;
  output S15_AXIS_TREADY;
  output [0:0]M_AXI_IC_AWID;
  output [31:0]M_AXI_IC_AWADDR;
  output [7:0]M_AXI_IC_AWLEN;
  output [2:0]M_AXI_IC_AWSIZE;
  output [1:0]M_AXI_IC_AWBURST;
  output M_AXI_IC_AWLOCK;
  output [3:0]M_AXI_IC_AWCACHE;
  output [2:0]M_AXI_IC_AWPROT;
  output [3:0]M_AXI_IC_AWQOS;
  output M_AXI_IC_AWVALID;
  input M_AXI_IC_AWREADY;
  output [4:0]M_AXI_IC_AWUSER;
  output [1:0]M_AXI_IC_AWDOMAIN;
  output [2:0]M_AXI_IC_AWSNOOP;
  output [1:0]M_AXI_IC_AWBAR;
  output [31:0]M_AXI_IC_WDATA;
  output [3:0]M_AXI_IC_WSTRB;
  output M_AXI_IC_WLAST;
  output M_AXI_IC_WVALID;
  input M_AXI_IC_WREADY;
  output [0:0]M_AXI_IC_WUSER;
  input [0:0]M_AXI_IC_BID;
  input [1:0]M_AXI_IC_BRESP;
  input M_AXI_IC_BVALID;
  output M_AXI_IC_BREADY;
  input [0:0]M_AXI_IC_BUSER;
  output M_AXI_IC_WACK;
  output [0:0]M_AXI_IC_ARID;
  output [31:0]M_AXI_IC_ARADDR;
  output [7:0]M_AXI_IC_ARLEN;
  output [2:0]M_AXI_IC_ARSIZE;
  output [1:0]M_AXI_IC_ARBURST;
  output M_AXI_IC_ARLOCK;
  output [3:0]M_AXI_IC_ARCACHE;
  output [2:0]M_AXI_IC_ARPROT;
  output [3:0]M_AXI_IC_ARQOS;
  output M_AXI_IC_ARVALID;
  input M_AXI_IC_ARREADY;
  output [4:0]M_AXI_IC_ARUSER;
  output [1:0]M_AXI_IC_ARDOMAIN;
  output [3:0]M_AXI_IC_ARSNOOP;
  output [1:0]M_AXI_IC_ARBAR;
  input [0:0]M_AXI_IC_RID;
  input [31:0]M_AXI_IC_RDATA;
  input [1:0]M_AXI_IC_RRESP;
  input M_AXI_IC_RLAST;
  input M_AXI_IC_RVALID;
  output M_AXI_IC_RREADY;
  input [0:0]M_AXI_IC_RUSER;
  output M_AXI_IC_RACK;
  input M_AXI_IC_ACVALID;
  input [31:0]M_AXI_IC_ACADDR;
  input [3:0]M_AXI_IC_ACSNOOP;
  input [2:0]M_AXI_IC_ACPROT;
  output M_AXI_IC_ACREADY;
  output M_AXI_IC_CRVALID;
  output [4:0]M_AXI_IC_CRRESP;
  input M_AXI_IC_CRREADY;
  output M_AXI_IC_CDVALID;
  output [31:0]M_AXI_IC_CDDATA;
  output M_AXI_IC_CDLAST;
  input M_AXI_IC_CDREADY;
  output [0:0]M_AXI_DC_AWID;
  output [31:0]M_AXI_DC_AWADDR;
  output [7:0]M_AXI_DC_AWLEN;
  output [2:0]M_AXI_DC_AWSIZE;
  output [1:0]M_AXI_DC_AWBURST;
  output M_AXI_DC_AWLOCK;
  output [3:0]M_AXI_DC_AWCACHE;
  output [2:0]M_AXI_DC_AWPROT;
  output [3:0]M_AXI_DC_AWQOS;
  output M_AXI_DC_AWVALID;
  input M_AXI_DC_AWREADY;
  output [4:0]M_AXI_DC_AWUSER;
  output [1:0]M_AXI_DC_AWDOMAIN;
  output [2:0]M_AXI_DC_AWSNOOP;
  output [1:0]M_AXI_DC_AWBAR;
  output [31:0]M_AXI_DC_WDATA;
  output [3:0]M_AXI_DC_WSTRB;
  output M_AXI_DC_WLAST;
  output M_AXI_DC_WVALID;
  input M_AXI_DC_WREADY;
  output [0:0]M_AXI_DC_WUSER;
  input [1:0]M_AXI_DC_BRESP;
  input [0:0]M_AXI_DC_BID;
  input M_AXI_DC_BVALID;
  output M_AXI_DC_BREADY;
  input [0:0]M_AXI_DC_BUSER;
  output M_AXI_DC_WACK;
  output [0:0]M_AXI_DC_ARID;
  output [31:0]M_AXI_DC_ARADDR;
  output [7:0]M_AXI_DC_ARLEN;
  output [2:0]M_AXI_DC_ARSIZE;
  output [1:0]M_AXI_DC_ARBURST;
  output M_AXI_DC_ARLOCK;
  output [3:0]M_AXI_DC_ARCACHE;
  output [2:0]M_AXI_DC_ARPROT;
  output [3:0]M_AXI_DC_ARQOS;
  output M_AXI_DC_ARVALID;
  input M_AXI_DC_ARREADY;
  output [4:0]M_AXI_DC_ARUSER;
  output [1:0]M_AXI_DC_ARDOMAIN;
  output [3:0]M_AXI_DC_ARSNOOP;
  output [1:0]M_AXI_DC_ARBAR;
  input [0:0]M_AXI_DC_RID;
  input [31:0]M_AXI_DC_RDATA;
  input [1:0]M_AXI_DC_RRESP;
  input M_AXI_DC_RLAST;
  input M_AXI_DC_RVALID;
  output M_AXI_DC_RREADY;
  input [0:0]M_AXI_DC_RUSER;
  output M_AXI_DC_RACK;
  input M_AXI_DC_ACVALID;
  input [31:0]M_AXI_DC_ACADDR;
  input [3:0]M_AXI_DC_ACSNOOP;
  input [2:0]M_AXI_DC_ACPROT;
  output M_AXI_DC_ACREADY;
  output M_AXI_DC_CRVALID;
  output [4:0]M_AXI_DC_CRRESP;
  input M_AXI_DC_CRREADY;
  output M_AXI_DC_CDVALID;
  output [31:0]M_AXI_DC_CDDATA;
  output M_AXI_DC_CDLAST;
  input M_AXI_DC_CDREADY;

  wire \<const0> ;
  wire \<const1> ;
  wire [0:3]Byte_Enable;
  wire Clk;
  wire Config_Reg_En;
  wire DReady;
  wire DWait;
  wire D_AS;
  wire [0:31]Data_Addr;
  wire [0:31]Data_Read;
  wire Data_Read_Reg_En;
  wire [0:31]Data_Write;
  wire Dbg_Capture;
  wire Dbg_Clk;
  wire Dbg_Continue;
  wire [0:7]Dbg_Reg_En;
  wire Dbg_Shift;
  wire Dbg_Stop;
  wire Dbg_TDI;
  wire Dbg_TDO;
  wire Dbg_TDO_INST_0_i_11_n_0;
  wire Dbg_TDO_INST_0_i_26_n_0;
  wire [0:7]Dbg_Trig_Ack_In;
  wire [0:1]\^Dbg_Trig_Ack_Out ;
  wire [0:1]\^Dbg_Trig_In ;
  wire [0:7]Dbg_Trig_Out;
  wire Dbg_Update;
  wire Debug_Rst;
  wire Hibernate;
  wire IFetch;
  wire IReady;
  wire I_AS;
  wire [0:31]Instr;
  wire [0:31]Instr_Addr;
  wire [1:46]\^LOCKSTEP_Master_Out ;
  wire [2:3228]\^LOCKSTEP_Out ;
  wire [31:0]M_AXI_DP_ARADDR;
  wire M_AXI_DP_ARREADY;
  wire M_AXI_DP_ARVALID;
  wire M_AXI_DP_AWREADY;
  wire M_AXI_DP_AWVALID;
  wire M_AXI_DP_BVALID;
  wire [31:0]M_AXI_DP_RDATA;
  wire M_AXI_DP_RVALID;
  wire [31:0]M_AXI_DP_WDATA;
  wire M_AXI_DP_WREADY;
  wire [3:0]M_AXI_DP_WSTRB;
  wire M_AXI_DP_WVALID;
  wire Mb_Reset;
  wire MicroBlaze_Core_I_n_411;
  wire Pause;
  wire Pause_Ack;
  wire \Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Status_Reg_En ;
  wire Read_Strobe;
  wire Reset;
  wire [0:1]Reset_Mode;
  wire Scan_En;
  wire Scan_Reset;
  wire Scan_Reset_Sel;
  wire Sleep;
  wire Suspend;
  wire Trace_Data_Access;
  wire [0:31]Trace_Data_Address;
  wire [0:3]Trace_Data_Byte_Enable;
  wire Trace_Data_Read;
  wire Trace_Data_Write;
  wire [0:31]Trace_Data_Write_Value;
  wire Trace_Delay_Slot;
  wire Trace_EX_PipeRun;
  wire [1:4]\^Trace_Exception_Kind ;
  wire Trace_Exception_Taken;
  wire [0:31]Trace_Instruction;
  wire Trace_Jump_Taken;
  wire Trace_MEM_PipeRun;
  wire [11:13]\^Trace_MSR_Reg ;
  wire [0:31]Trace_New_Reg_Value;
  wire Trace_OF_PipeRun;
  wire [0:31]Trace_PC;
  wire [0:4]Trace_Reg_Addr;
  wire Trace_Reg_Write;
  wire Trace_Valid_Instr;
  wire [0:1]Wakeup;
  wire Write_Strobe;

  assign Dbg_ARREADY = \<const0> ;
  assign Dbg_AWREADY = \<const0> ;
  assign Dbg_BRESP[1] = \<const0> ;
  assign Dbg_BRESP[0] = \<const0> ;
  assign Dbg_BVALID = \<const0> ;
  assign Dbg_Intr = \<const0> ;
  assign Dbg_RDATA[31] = \<const0> ;
  assign Dbg_RDATA[30] = \<const0> ;
  assign Dbg_RDATA[29] = \<const0> ;
  assign Dbg_RDATA[28] = \<const0> ;
  assign Dbg_RDATA[27] = \<const0> ;
  assign Dbg_RDATA[26] = \<const0> ;
  assign Dbg_RDATA[25] = \<const0> ;
  assign Dbg_RDATA[24] = \<const0> ;
  assign Dbg_RDATA[23] = \<const0> ;
  assign Dbg_RDATA[22] = \<const0> ;
  assign Dbg_RDATA[21] = \<const0> ;
  assign Dbg_RDATA[20] = \<const0> ;
  assign Dbg_RDATA[19] = \<const0> ;
  assign Dbg_RDATA[18] = \<const0> ;
  assign Dbg_RDATA[17] = \<const0> ;
  assign Dbg_RDATA[16] = \<const0> ;
  assign Dbg_RDATA[15] = \<const0> ;
  assign Dbg_RDATA[14] = \<const0> ;
  assign Dbg_RDATA[13] = \<const0> ;
  assign Dbg_RDATA[12] = \<const0> ;
  assign Dbg_RDATA[11] = \<const0> ;
  assign Dbg_RDATA[10] = \<const0> ;
  assign Dbg_RDATA[9] = \<const0> ;
  assign Dbg_RDATA[8] = \<const0> ;
  assign Dbg_RDATA[7] = \<const0> ;
  assign Dbg_RDATA[6] = \<const0> ;
  assign Dbg_RDATA[5] = \<const0> ;
  assign Dbg_RDATA[4] = \<const0> ;
  assign Dbg_RDATA[3] = \<const0> ;
  assign Dbg_RDATA[2] = \<const0> ;
  assign Dbg_RDATA[1] = \<const0> ;
  assign Dbg_RDATA[0] = \<const0> ;
  assign Dbg_RRESP[1] = \<const0> ;
  assign Dbg_RRESP[0] = \<const0> ;
  assign Dbg_RVALID = \<const0> ;
  assign Dbg_Trace_Data[0] = \<const0> ;
  assign Dbg_Trace_Data[1] = \<const0> ;
  assign Dbg_Trace_Data[2] = \<const0> ;
  assign Dbg_Trace_Data[3] = \<const0> ;
  assign Dbg_Trace_Data[4] = \<const0> ;
  assign Dbg_Trace_Data[5] = \<const0> ;
  assign Dbg_Trace_Data[6] = \<const0> ;
  assign Dbg_Trace_Data[7] = \<const0> ;
  assign Dbg_Trace_Data[8] = \<const0> ;
  assign Dbg_Trace_Data[9] = \<const0> ;
  assign Dbg_Trace_Data[10] = \<const0> ;
  assign Dbg_Trace_Data[11] = \<const0> ;
  assign Dbg_Trace_Data[12] = \<const0> ;
  assign Dbg_Trace_Data[13] = \<const0> ;
  assign Dbg_Trace_Data[14] = \<const0> ;
  assign Dbg_Trace_Data[15] = \<const0> ;
  assign Dbg_Trace_Data[16] = \<const0> ;
  assign Dbg_Trace_Data[17] = \<const0> ;
  assign Dbg_Trace_Data[18] = \<const0> ;
  assign Dbg_Trace_Data[19] = \<const0> ;
  assign Dbg_Trace_Data[20] = \<const0> ;
  assign Dbg_Trace_Data[21] = \<const0> ;
  assign Dbg_Trace_Data[22] = \<const0> ;
  assign Dbg_Trace_Data[23] = \<const0> ;
  assign Dbg_Trace_Data[24] = \<const0> ;
  assign Dbg_Trace_Data[25] = \<const0> ;
  assign Dbg_Trace_Data[26] = \<const0> ;
  assign Dbg_Trace_Data[27] = \<const0> ;
  assign Dbg_Trace_Data[28] = \<const0> ;
  assign Dbg_Trace_Data[29] = \<const0> ;
  assign Dbg_Trace_Data[30] = \<const0> ;
  assign Dbg_Trace_Data[31] = \<const0> ;
  assign Dbg_Trace_Data[32] = \<const0> ;
  assign Dbg_Trace_Data[33] = \<const0> ;
  assign Dbg_Trace_Data[34] = \<const0> ;
  assign Dbg_Trace_Data[35] = \<const0> ;
  assign Dbg_Trace_Valid = \<const0> ;
  assign Dbg_Trig_Ack_Out[0:1] = \^Dbg_Trig_Ack_Out [0:1];
  assign Dbg_Trig_Ack_Out[2] = \<const0> ;
  assign Dbg_Trig_Ack_Out[3] = \<const0> ;
  assign Dbg_Trig_Ack_Out[4] = \<const0> ;
  assign Dbg_Trig_Ack_Out[5] = \<const0> ;
  assign Dbg_Trig_Ack_Out[6] = \<const0> ;
  assign Dbg_Trig_Ack_Out[7] = \<const0> ;
  assign Dbg_Trig_In[0:1] = \^Dbg_Trig_In [0:1];
  assign Dbg_Trig_In[2] = \<const0> ;
  assign Dbg_Trig_In[3] = \<const0> ;
  assign Dbg_Trig_In[4] = \<const0> ;
  assign Dbg_Trig_In[5] = \<const0> ;
  assign Dbg_Trig_In[6] = \<const0> ;
  assign Dbg_Trig_In[7] = \<const0> ;
  assign Dbg_WREADY = \<const0> ;
  assign Dbg_Wakeup = \^LOCKSTEP_Master_Out [11];
  assign Interrupt_Ack[0] = \<const0> ;
  assign Interrupt_Ack[1] = \<const0> ;
  assign LOCKSTEP_Master_Out[0] = \<const0> ;
  assign LOCKSTEP_Master_Out[1] = \^LOCKSTEP_Master_Out [1];
  assign LOCKSTEP_Master_Out[2] = \<const0> ;
  assign LOCKSTEP_Master_Out[3:7] = \^LOCKSTEP_Master_Out [3:7];
  assign LOCKSTEP_Master_Out[8] = \^LOCKSTEP_Master_Out [10];
  assign LOCKSTEP_Master_Out[9] = \<const0> ;
  assign LOCKSTEP_Master_Out[10:11] = \^LOCKSTEP_Master_Out [10:11];
  assign LOCKSTEP_Master_Out[12] = Dbg_Continue;
  assign LOCKSTEP_Master_Out[13] = \^LOCKSTEP_Master_Out [13];
  assign LOCKSTEP_Master_Out[14] = Debug_Rst;
  assign LOCKSTEP_Master_Out[15:46] = \^LOCKSTEP_Master_Out [15:46];
  assign LOCKSTEP_Master_Out[47] = \<const0> ;
  assign LOCKSTEP_Master_Out[48] = \<const0> ;
  assign LOCKSTEP_Master_Out[49] = \<const0> ;
  assign LOCKSTEP_Master_Out[50] = \<const0> ;
  assign LOCKSTEP_Master_Out[51] = \<const0> ;
  assign LOCKSTEP_Master_Out[52] = \<const0> ;
  assign LOCKSTEP_Master_Out[53] = \<const0> ;
  assign LOCKSTEP_Master_Out[54] = \<const0> ;
  assign LOCKSTEP_Master_Out[55] = \<const0> ;
  assign LOCKSTEP_Master_Out[56] = \<const0> ;
  assign LOCKSTEP_Master_Out[57] = \<const0> ;
  assign LOCKSTEP_Master_Out[58] = \<const0> ;
  assign LOCKSTEP_Master_Out[59] = \<const0> ;
  assign LOCKSTEP_Master_Out[60] = \<const0> ;
  assign LOCKSTEP_Master_Out[61] = \<const0> ;
  assign LOCKSTEP_Master_Out[62] = \<const0> ;
  assign LOCKSTEP_Master_Out[63] = \<const0> ;
  assign LOCKSTEP_Master_Out[64] = \<const0> ;
  assign LOCKSTEP_Master_Out[65] = \<const0> ;
  assign LOCKSTEP_Master_Out[66] = \<const0> ;
  assign LOCKSTEP_Master_Out[67] = \<const0> ;
  assign LOCKSTEP_Master_Out[68] = \<const0> ;
  assign LOCKSTEP_Master_Out[69] = \<const0> ;
  assign LOCKSTEP_Master_Out[70] = \<const0> ;
  assign LOCKSTEP_Master_Out[71] = \<const0> ;
  assign LOCKSTEP_Master_Out[72] = \<const0> ;
  assign LOCKSTEP_Master_Out[73] = \<const0> ;
  assign LOCKSTEP_Master_Out[74] = \<const0> ;
  assign LOCKSTEP_Master_Out[75] = \<const0> ;
  assign LOCKSTEP_Master_Out[76] = \<const0> ;
  assign LOCKSTEP_Master_Out[77] = \<const0> ;
  assign LOCKSTEP_Master_Out[78] = \<const0> ;
  assign LOCKSTEP_Master_Out[79] = \<const0> ;
  assign LOCKSTEP_Master_Out[80] = \<const0> ;
  assign LOCKSTEP_Master_Out[81] = \<const0> ;
  assign LOCKSTEP_Master_Out[82] = \<const0> ;
  assign LOCKSTEP_Master_Out[83] = \<const0> ;
  assign LOCKSTEP_Master_Out[84] = \<const0> ;
  assign LOCKSTEP_Master_Out[85] = \<const0> ;
  assign LOCKSTEP_Master_Out[86] = \<const0> ;
  assign LOCKSTEP_Master_Out[87] = \<const0> ;
  assign LOCKSTEP_Master_Out[88] = \<const0> ;
  assign LOCKSTEP_Master_Out[89] = \<const0> ;
  assign LOCKSTEP_Master_Out[90] = \<const0> ;
  assign LOCKSTEP_Master_Out[91] = \<const0> ;
  assign LOCKSTEP_Master_Out[92] = \<const0> ;
  assign LOCKSTEP_Master_Out[93] = \<const0> ;
  assign LOCKSTEP_Master_Out[94] = \<const0> ;
  assign LOCKSTEP_Master_Out[95] = \<const0> ;
  assign LOCKSTEP_Master_Out[96] = \<const0> ;
  assign LOCKSTEP_Master_Out[97] = \<const0> ;
  assign LOCKSTEP_Master_Out[98] = \<const0> ;
  assign LOCKSTEP_Master_Out[99] = \<const0> ;
  assign LOCKSTEP_Master_Out[100] = \<const0> ;
  assign LOCKSTEP_Master_Out[101] = \<const0> ;
  assign LOCKSTEP_Master_Out[102] = \<const0> ;
  assign LOCKSTEP_Master_Out[103] = \<const0> ;
  assign LOCKSTEP_Master_Out[104] = \<const0> ;
  assign LOCKSTEP_Master_Out[105] = \<const0> ;
  assign LOCKSTEP_Master_Out[106] = \<const0> ;
  assign LOCKSTEP_Master_Out[107] = \<const0> ;
  assign LOCKSTEP_Master_Out[108] = \<const0> ;
  assign LOCKSTEP_Master_Out[109] = \<const0> ;
  assign LOCKSTEP_Master_Out[110] = \<const0> ;
  assign LOCKSTEP_Master_Out[111] = \<const0> ;
  assign LOCKSTEP_Master_Out[112] = \<const0> ;
  assign LOCKSTEP_Master_Out[113] = \<const0> ;
  assign LOCKSTEP_Master_Out[114] = \<const0> ;
  assign LOCKSTEP_Master_Out[115] = \<const0> ;
  assign LOCKSTEP_Master_Out[116] = \<const0> ;
  assign LOCKSTEP_Master_Out[117] = \<const0> ;
  assign LOCKSTEP_Master_Out[118] = \<const0> ;
  assign LOCKSTEP_Master_Out[119] = \<const0> ;
  assign LOCKSTEP_Master_Out[120] = \<const0> ;
  assign LOCKSTEP_Master_Out[121] = \<const0> ;
  assign LOCKSTEP_Master_Out[122] = \<const0> ;
  assign LOCKSTEP_Master_Out[123] = \<const0> ;
  assign LOCKSTEP_Master_Out[124] = \<const0> ;
  assign LOCKSTEP_Master_Out[125] = \<const0> ;
  assign LOCKSTEP_Master_Out[126] = \<const0> ;
  assign LOCKSTEP_Master_Out[127] = \<const0> ;
  assign LOCKSTEP_Master_Out[128] = \<const0> ;
  assign LOCKSTEP_Master_Out[129] = \<const0> ;
  assign LOCKSTEP_Master_Out[130] = \<const0> ;
  assign LOCKSTEP_Master_Out[131] = \<const0> ;
  assign LOCKSTEP_Master_Out[132] = \<const0> ;
  assign LOCKSTEP_Master_Out[133] = \<const0> ;
  assign LOCKSTEP_Master_Out[134] = \<const0> ;
  assign LOCKSTEP_Master_Out[135] = \<const0> ;
  assign LOCKSTEP_Master_Out[136] = \<const0> ;
  assign LOCKSTEP_Master_Out[137] = \<const0> ;
  assign LOCKSTEP_Master_Out[138] = \<const0> ;
  assign LOCKSTEP_Master_Out[139] = \<const0> ;
  assign LOCKSTEP_Master_Out[140] = \<const0> ;
  assign LOCKSTEP_Master_Out[141] = \<const0> ;
  assign LOCKSTEP_Master_Out[142] = \<const0> ;
  assign LOCKSTEP_Master_Out[143] = \<const0> ;
  assign LOCKSTEP_Master_Out[144] = \<const0> ;
  assign LOCKSTEP_Master_Out[145] = \<const0> ;
  assign LOCKSTEP_Master_Out[146] = \<const0> ;
  assign LOCKSTEP_Master_Out[147] = \<const0> ;
  assign LOCKSTEP_Master_Out[148] = \<const0> ;
  assign LOCKSTEP_Master_Out[149] = \<const0> ;
  assign LOCKSTEP_Master_Out[150] = \<const0> ;
  assign LOCKSTEP_Master_Out[151] = \<const0> ;
  assign LOCKSTEP_Master_Out[152] = \<const0> ;
  assign LOCKSTEP_Master_Out[153] = \<const0> ;
  assign LOCKSTEP_Master_Out[154] = \<const0> ;
  assign LOCKSTEP_Master_Out[155] = \<const0> ;
  assign LOCKSTEP_Master_Out[156] = \<const0> ;
  assign LOCKSTEP_Master_Out[157] = \<const0> ;
  assign LOCKSTEP_Master_Out[158] = \<const0> ;
  assign LOCKSTEP_Master_Out[159] = \<const0> ;
  assign LOCKSTEP_Master_Out[160] = \<const0> ;
  assign LOCKSTEP_Master_Out[161] = \<const0> ;
  assign LOCKSTEP_Master_Out[162] = \<const0> ;
  assign LOCKSTEP_Master_Out[163] = \<const0> ;
  assign LOCKSTEP_Master_Out[164] = \<const0> ;
  assign LOCKSTEP_Master_Out[165] = \<const0> ;
  assign LOCKSTEP_Master_Out[166] = \<const0> ;
  assign LOCKSTEP_Master_Out[167] = \<const0> ;
  assign LOCKSTEP_Master_Out[168] = \<const0> ;
  assign LOCKSTEP_Master_Out[169] = \<const0> ;
  assign LOCKSTEP_Master_Out[170] = \<const0> ;
  assign LOCKSTEP_Master_Out[171] = \<const0> ;
  assign LOCKSTEP_Master_Out[172] = \<const0> ;
  assign LOCKSTEP_Master_Out[173] = \<const0> ;
  assign LOCKSTEP_Master_Out[174] = \<const0> ;
  assign LOCKSTEP_Master_Out[175] = \<const0> ;
  assign LOCKSTEP_Master_Out[176] = \<const0> ;
  assign LOCKSTEP_Master_Out[177] = \<const0> ;
  assign LOCKSTEP_Master_Out[178] = \<const0> ;
  assign LOCKSTEP_Master_Out[179] = \<const0> ;
  assign LOCKSTEP_Master_Out[180] = \<const0> ;
  assign LOCKSTEP_Master_Out[181] = \<const0> ;
  assign LOCKSTEP_Master_Out[182] = \<const0> ;
  assign LOCKSTEP_Master_Out[183] = \<const0> ;
  assign LOCKSTEP_Master_Out[184] = \<const0> ;
  assign LOCKSTEP_Master_Out[185] = \<const0> ;
  assign LOCKSTEP_Master_Out[186] = \<const0> ;
  assign LOCKSTEP_Master_Out[187] = \<const0> ;
  assign LOCKSTEP_Master_Out[188] = \<const0> ;
  assign LOCKSTEP_Master_Out[189] = \<const0> ;
  assign LOCKSTEP_Master_Out[190] = \<const0> ;
  assign LOCKSTEP_Master_Out[191] = \<const0> ;
  assign LOCKSTEP_Master_Out[192] = \<const0> ;
  assign LOCKSTEP_Master_Out[193] = \<const0> ;
  assign LOCKSTEP_Master_Out[194] = \<const0> ;
  assign LOCKSTEP_Master_Out[195] = \<const0> ;
  assign LOCKSTEP_Master_Out[196] = \<const0> ;
  assign LOCKSTEP_Master_Out[197] = \<const0> ;
  assign LOCKSTEP_Master_Out[198] = \<const0> ;
  assign LOCKSTEP_Master_Out[199] = \<const0> ;
  assign LOCKSTEP_Master_Out[200] = \<const0> ;
  assign LOCKSTEP_Master_Out[201] = \<const0> ;
  assign LOCKSTEP_Master_Out[202] = \<const0> ;
  assign LOCKSTEP_Master_Out[203] = \<const0> ;
  assign LOCKSTEP_Master_Out[204] = \<const0> ;
  assign LOCKSTEP_Master_Out[205] = \<const0> ;
  assign LOCKSTEP_Master_Out[206] = \<const0> ;
  assign LOCKSTEP_Master_Out[207] = \<const0> ;
  assign LOCKSTEP_Master_Out[208] = \<const0> ;
  assign LOCKSTEP_Master_Out[209] = \<const0> ;
  assign LOCKSTEP_Master_Out[210] = \<const0> ;
  assign LOCKSTEP_Master_Out[211] = \<const0> ;
  assign LOCKSTEP_Master_Out[212] = \<const0> ;
  assign LOCKSTEP_Master_Out[213] = \<const0> ;
  assign LOCKSTEP_Master_Out[214] = \<const0> ;
  assign LOCKSTEP_Master_Out[215] = \<const0> ;
  assign LOCKSTEP_Master_Out[216] = \<const0> ;
  assign LOCKSTEP_Master_Out[217] = \<const0> ;
  assign LOCKSTEP_Master_Out[218] = \<const0> ;
  assign LOCKSTEP_Master_Out[219] = \<const0> ;
  assign LOCKSTEP_Master_Out[220] = \<const0> ;
  assign LOCKSTEP_Master_Out[221] = \<const0> ;
  assign LOCKSTEP_Master_Out[222] = \<const0> ;
  assign LOCKSTEP_Master_Out[223] = \<const0> ;
  assign LOCKSTEP_Master_Out[224] = \<const0> ;
  assign LOCKSTEP_Master_Out[225] = \<const0> ;
  assign LOCKSTEP_Master_Out[226] = \<const0> ;
  assign LOCKSTEP_Master_Out[227] = \<const0> ;
  assign LOCKSTEP_Master_Out[228] = \<const0> ;
  assign LOCKSTEP_Master_Out[229] = \<const0> ;
  assign LOCKSTEP_Master_Out[230] = \<const0> ;
  assign LOCKSTEP_Master_Out[231] = \<const0> ;
  assign LOCKSTEP_Master_Out[232] = \<const0> ;
  assign LOCKSTEP_Master_Out[233] = \<const0> ;
  assign LOCKSTEP_Master_Out[234] = \<const0> ;
  assign LOCKSTEP_Master_Out[235] = \<const0> ;
  assign LOCKSTEP_Master_Out[236] = \<const0> ;
  assign LOCKSTEP_Master_Out[237] = \<const0> ;
  assign LOCKSTEP_Master_Out[238] = \<const0> ;
  assign LOCKSTEP_Master_Out[239] = \<const0> ;
  assign LOCKSTEP_Master_Out[240] = \<const0> ;
  assign LOCKSTEP_Master_Out[241] = \<const0> ;
  assign LOCKSTEP_Master_Out[242] = \<const0> ;
  assign LOCKSTEP_Master_Out[243] = \<const0> ;
  assign LOCKSTEP_Master_Out[244] = \<const0> ;
  assign LOCKSTEP_Master_Out[245] = \<const0> ;
  assign LOCKSTEP_Master_Out[246] = \<const0> ;
  assign LOCKSTEP_Master_Out[247] = \<const0> ;
  assign LOCKSTEP_Master_Out[248] = \<const0> ;
  assign LOCKSTEP_Master_Out[249] = \<const0> ;
  assign LOCKSTEP_Master_Out[250] = \<const0> ;
  assign LOCKSTEP_Master_Out[251] = \<const0> ;
  assign LOCKSTEP_Master_Out[252] = \<const0> ;
  assign LOCKSTEP_Master_Out[253] = \<const0> ;
  assign LOCKSTEP_Master_Out[254] = \<const0> ;
  assign LOCKSTEP_Master_Out[255] = \<const0> ;
  assign LOCKSTEP_Master_Out[256] = \<const0> ;
  assign LOCKSTEP_Master_Out[257] = \<const0> ;
  assign LOCKSTEP_Master_Out[258] = \<const0> ;
  assign LOCKSTEP_Master_Out[259] = \<const0> ;
  assign LOCKSTEP_Master_Out[260] = \<const0> ;
  assign LOCKSTEP_Master_Out[261] = \<const0> ;
  assign LOCKSTEP_Master_Out[262] = \<const0> ;
  assign LOCKSTEP_Master_Out[263] = \<const0> ;
  assign LOCKSTEP_Master_Out[264] = \<const0> ;
  assign LOCKSTEP_Master_Out[265] = \<const0> ;
  assign LOCKSTEP_Master_Out[266] = \<const0> ;
  assign LOCKSTEP_Master_Out[267] = \<const0> ;
  assign LOCKSTEP_Master_Out[268] = \<const0> ;
  assign LOCKSTEP_Master_Out[269] = \<const0> ;
  assign LOCKSTEP_Master_Out[270] = \<const0> ;
  assign LOCKSTEP_Master_Out[271] = \<const0> ;
  assign LOCKSTEP_Master_Out[272] = \<const0> ;
  assign LOCKSTEP_Master_Out[273] = \<const0> ;
  assign LOCKSTEP_Master_Out[274] = \<const0> ;
  assign LOCKSTEP_Master_Out[275] = \<const0> ;
  assign LOCKSTEP_Master_Out[276] = \<const0> ;
  assign LOCKSTEP_Master_Out[277] = \<const0> ;
  assign LOCKSTEP_Master_Out[278] = \<const0> ;
  assign LOCKSTEP_Master_Out[279] = \<const0> ;
  assign LOCKSTEP_Master_Out[280] = \<const0> ;
  assign LOCKSTEP_Master_Out[281] = \<const0> ;
  assign LOCKSTEP_Master_Out[282] = \<const0> ;
  assign LOCKSTEP_Master_Out[283] = \<const0> ;
  assign LOCKSTEP_Master_Out[284] = \<const0> ;
  assign LOCKSTEP_Master_Out[285] = \<const0> ;
  assign LOCKSTEP_Master_Out[286] = \<const0> ;
  assign LOCKSTEP_Master_Out[287] = \<const0> ;
  assign LOCKSTEP_Master_Out[288] = \<const0> ;
  assign LOCKSTEP_Master_Out[289] = \<const0> ;
  assign LOCKSTEP_Master_Out[290] = \<const0> ;
  assign LOCKSTEP_Master_Out[291] = \<const0> ;
  assign LOCKSTEP_Master_Out[292] = \<const0> ;
  assign LOCKSTEP_Master_Out[293] = \<const0> ;
  assign LOCKSTEP_Master_Out[294] = \<const0> ;
  assign LOCKSTEP_Master_Out[295] = \<const0> ;
  assign LOCKSTEP_Master_Out[296] = \<const0> ;
  assign LOCKSTEP_Master_Out[297] = \<const0> ;
  assign LOCKSTEP_Master_Out[298] = \<const0> ;
  assign LOCKSTEP_Master_Out[299] = \<const0> ;
  assign LOCKSTEP_Master_Out[300] = \<const0> ;
  assign LOCKSTEP_Master_Out[301] = \<const0> ;
  assign LOCKSTEP_Master_Out[302] = \<const0> ;
  assign LOCKSTEP_Master_Out[303] = \<const0> ;
  assign LOCKSTEP_Master_Out[304] = \<const0> ;
  assign LOCKSTEP_Master_Out[305] = \<const0> ;
  assign LOCKSTEP_Master_Out[306] = \<const0> ;
  assign LOCKSTEP_Master_Out[307] = \<const0> ;
  assign LOCKSTEP_Master_Out[308] = \<const0> ;
  assign LOCKSTEP_Master_Out[309] = \<const0> ;
  assign LOCKSTEP_Master_Out[310] = \<const0> ;
  assign LOCKSTEP_Master_Out[311] = \<const0> ;
  assign LOCKSTEP_Master_Out[312] = \<const0> ;
  assign LOCKSTEP_Master_Out[313] = \<const0> ;
  assign LOCKSTEP_Master_Out[314] = \<const0> ;
  assign LOCKSTEP_Master_Out[315] = \<const0> ;
  assign LOCKSTEP_Master_Out[316] = \<const0> ;
  assign LOCKSTEP_Master_Out[317] = \<const0> ;
  assign LOCKSTEP_Master_Out[318] = \<const0> ;
  assign LOCKSTEP_Master_Out[319] = \<const0> ;
  assign LOCKSTEP_Master_Out[320] = \<const0> ;
  assign LOCKSTEP_Master_Out[321] = \<const0> ;
  assign LOCKSTEP_Master_Out[322] = \<const0> ;
  assign LOCKSTEP_Master_Out[323] = \<const0> ;
  assign LOCKSTEP_Master_Out[324] = \<const0> ;
  assign LOCKSTEP_Master_Out[325] = \<const0> ;
  assign LOCKSTEP_Master_Out[326] = \<const0> ;
  assign LOCKSTEP_Master_Out[327] = \<const0> ;
  assign LOCKSTEP_Master_Out[328] = \<const0> ;
  assign LOCKSTEP_Master_Out[329] = \<const0> ;
  assign LOCKSTEP_Master_Out[330] = \<const0> ;
  assign LOCKSTEP_Master_Out[331] = \<const0> ;
  assign LOCKSTEP_Master_Out[332] = \<const0> ;
  assign LOCKSTEP_Master_Out[333] = \<const0> ;
  assign LOCKSTEP_Master_Out[334] = \<const0> ;
  assign LOCKSTEP_Master_Out[335] = \<const0> ;
  assign LOCKSTEP_Master_Out[336] = \<const0> ;
  assign LOCKSTEP_Master_Out[337] = \<const0> ;
  assign LOCKSTEP_Master_Out[338] = \<const0> ;
  assign LOCKSTEP_Master_Out[339] = \<const0> ;
  assign LOCKSTEP_Master_Out[340] = \<const0> ;
  assign LOCKSTEP_Master_Out[341] = \<const0> ;
  assign LOCKSTEP_Master_Out[342] = \<const0> ;
  assign LOCKSTEP_Master_Out[343] = \<const0> ;
  assign LOCKSTEP_Master_Out[344] = \<const0> ;
  assign LOCKSTEP_Master_Out[345] = \<const0> ;
  assign LOCKSTEP_Master_Out[346] = \<const0> ;
  assign LOCKSTEP_Master_Out[347] = \<const0> ;
  assign LOCKSTEP_Master_Out[348] = \<const0> ;
  assign LOCKSTEP_Master_Out[349] = \<const0> ;
  assign LOCKSTEP_Master_Out[350] = \<const0> ;
  assign LOCKSTEP_Master_Out[351] = \<const0> ;
  assign LOCKSTEP_Master_Out[352] = \<const0> ;
  assign LOCKSTEP_Master_Out[353] = \<const0> ;
  assign LOCKSTEP_Master_Out[354] = \<const0> ;
  assign LOCKSTEP_Master_Out[355] = \<const0> ;
  assign LOCKSTEP_Master_Out[356] = \<const0> ;
  assign LOCKSTEP_Master_Out[357] = \<const0> ;
  assign LOCKSTEP_Master_Out[358] = \<const0> ;
  assign LOCKSTEP_Master_Out[359] = \<const0> ;
  assign LOCKSTEP_Master_Out[360] = \<const0> ;
  assign LOCKSTEP_Master_Out[361] = \<const0> ;
  assign LOCKSTEP_Master_Out[362] = \<const0> ;
  assign LOCKSTEP_Master_Out[363] = \<const0> ;
  assign LOCKSTEP_Master_Out[364] = \<const0> ;
  assign LOCKSTEP_Master_Out[365] = \<const0> ;
  assign LOCKSTEP_Master_Out[366] = \<const0> ;
  assign LOCKSTEP_Master_Out[367] = \<const0> ;
  assign LOCKSTEP_Master_Out[368] = \<const0> ;
  assign LOCKSTEP_Master_Out[369] = \<const0> ;
  assign LOCKSTEP_Master_Out[370] = \<const0> ;
  assign LOCKSTEP_Master_Out[371] = \<const0> ;
  assign LOCKSTEP_Master_Out[372] = \<const0> ;
  assign LOCKSTEP_Master_Out[373] = \<const0> ;
  assign LOCKSTEP_Master_Out[374] = \<const0> ;
  assign LOCKSTEP_Master_Out[375] = \<const0> ;
  assign LOCKSTEP_Master_Out[376] = \<const0> ;
  assign LOCKSTEP_Master_Out[377] = \<const0> ;
  assign LOCKSTEP_Master_Out[378] = \<const0> ;
  assign LOCKSTEP_Master_Out[379] = \<const0> ;
  assign LOCKSTEP_Master_Out[380] = \<const0> ;
  assign LOCKSTEP_Master_Out[381] = \<const0> ;
  assign LOCKSTEP_Master_Out[382] = \<const0> ;
  assign LOCKSTEP_Master_Out[383] = \<const0> ;
  assign LOCKSTEP_Master_Out[384] = \<const0> ;
  assign LOCKSTEP_Master_Out[385] = \<const0> ;
  assign LOCKSTEP_Master_Out[386] = \<const0> ;
  assign LOCKSTEP_Master_Out[387] = \<const0> ;
  assign LOCKSTEP_Master_Out[388] = \<const0> ;
  assign LOCKSTEP_Master_Out[389] = \<const0> ;
  assign LOCKSTEP_Master_Out[390] = \<const0> ;
  assign LOCKSTEP_Master_Out[391] = \<const0> ;
  assign LOCKSTEP_Master_Out[392] = \<const0> ;
  assign LOCKSTEP_Master_Out[393] = \<const0> ;
  assign LOCKSTEP_Master_Out[394] = \<const0> ;
  assign LOCKSTEP_Master_Out[395] = \<const0> ;
  assign LOCKSTEP_Master_Out[396] = \<const0> ;
  assign LOCKSTEP_Master_Out[397] = \<const0> ;
  assign LOCKSTEP_Master_Out[398] = \<const0> ;
  assign LOCKSTEP_Master_Out[399] = \<const0> ;
  assign LOCKSTEP_Master_Out[400] = \<const0> ;
  assign LOCKSTEP_Master_Out[401] = \<const0> ;
  assign LOCKSTEP_Master_Out[402] = \<const0> ;
  assign LOCKSTEP_Master_Out[403] = \<const0> ;
  assign LOCKSTEP_Master_Out[404] = \<const0> ;
  assign LOCKSTEP_Master_Out[405] = \<const0> ;
  assign LOCKSTEP_Master_Out[406] = \<const0> ;
  assign LOCKSTEP_Master_Out[407] = \<const0> ;
  assign LOCKSTEP_Master_Out[408] = \<const0> ;
  assign LOCKSTEP_Master_Out[409] = \<const0> ;
  assign LOCKSTEP_Master_Out[410] = \<const0> ;
  assign LOCKSTEP_Master_Out[411] = \<const0> ;
  assign LOCKSTEP_Master_Out[412] = \<const0> ;
  assign LOCKSTEP_Master_Out[413] = \<const0> ;
  assign LOCKSTEP_Master_Out[414] = \<const0> ;
  assign LOCKSTEP_Master_Out[415] = \<const0> ;
  assign LOCKSTEP_Master_Out[416] = \<const0> ;
  assign LOCKSTEP_Master_Out[417] = \<const0> ;
  assign LOCKSTEP_Master_Out[418] = \<const0> ;
  assign LOCKSTEP_Master_Out[419] = \<const0> ;
  assign LOCKSTEP_Master_Out[420] = \<const0> ;
  assign LOCKSTEP_Master_Out[421] = \<const0> ;
  assign LOCKSTEP_Master_Out[422] = \<const0> ;
  assign LOCKSTEP_Master_Out[423] = \<const0> ;
  assign LOCKSTEP_Master_Out[424] = \<const0> ;
  assign LOCKSTEP_Master_Out[425] = \<const0> ;
  assign LOCKSTEP_Master_Out[426] = \<const0> ;
  assign LOCKSTEP_Master_Out[427] = \<const0> ;
  assign LOCKSTEP_Master_Out[428] = \<const0> ;
  assign LOCKSTEP_Master_Out[429] = \<const0> ;
  assign LOCKSTEP_Master_Out[430] = \<const0> ;
  assign LOCKSTEP_Master_Out[431] = \<const0> ;
  assign LOCKSTEP_Master_Out[432] = \<const0> ;
  assign LOCKSTEP_Master_Out[433] = \<const0> ;
  assign LOCKSTEP_Master_Out[434] = \<const0> ;
  assign LOCKSTEP_Master_Out[435] = \<const0> ;
  assign LOCKSTEP_Master_Out[436] = \<const0> ;
  assign LOCKSTEP_Master_Out[437] = \<const0> ;
  assign LOCKSTEP_Master_Out[438] = \<const0> ;
  assign LOCKSTEP_Master_Out[439] = \<const0> ;
  assign LOCKSTEP_Master_Out[440] = \<const0> ;
  assign LOCKSTEP_Master_Out[441] = \<const0> ;
  assign LOCKSTEP_Master_Out[442] = \<const0> ;
  assign LOCKSTEP_Master_Out[443] = \<const0> ;
  assign LOCKSTEP_Master_Out[444] = \<const0> ;
  assign LOCKSTEP_Master_Out[445] = \<const0> ;
  assign LOCKSTEP_Master_Out[446] = \<const0> ;
  assign LOCKSTEP_Master_Out[447] = \<const0> ;
  assign LOCKSTEP_Master_Out[448] = \<const0> ;
  assign LOCKSTEP_Master_Out[449] = \<const0> ;
  assign LOCKSTEP_Master_Out[450] = \<const0> ;
  assign LOCKSTEP_Master_Out[451] = \<const0> ;
  assign LOCKSTEP_Master_Out[452] = \<const0> ;
  assign LOCKSTEP_Master_Out[453] = \<const0> ;
  assign LOCKSTEP_Master_Out[454] = \<const0> ;
  assign LOCKSTEP_Master_Out[455] = \<const0> ;
  assign LOCKSTEP_Master_Out[456] = \<const0> ;
  assign LOCKSTEP_Master_Out[457] = \<const0> ;
  assign LOCKSTEP_Master_Out[458] = \<const0> ;
  assign LOCKSTEP_Master_Out[459] = \<const0> ;
  assign LOCKSTEP_Master_Out[460] = \<const0> ;
  assign LOCKSTEP_Master_Out[461] = \<const0> ;
  assign LOCKSTEP_Master_Out[462] = \<const0> ;
  assign LOCKSTEP_Master_Out[463] = \<const0> ;
  assign LOCKSTEP_Master_Out[464] = \<const0> ;
  assign LOCKSTEP_Master_Out[465] = \<const0> ;
  assign LOCKSTEP_Master_Out[466] = \<const0> ;
  assign LOCKSTEP_Master_Out[467] = \<const0> ;
  assign LOCKSTEP_Master_Out[468] = \<const0> ;
  assign LOCKSTEP_Master_Out[469] = \<const0> ;
  assign LOCKSTEP_Master_Out[470] = \<const0> ;
  assign LOCKSTEP_Master_Out[471] = \<const0> ;
  assign LOCKSTEP_Master_Out[472] = \<const0> ;
  assign LOCKSTEP_Master_Out[473] = \<const0> ;
  assign LOCKSTEP_Master_Out[474] = \<const0> ;
  assign LOCKSTEP_Master_Out[475] = \<const0> ;
  assign LOCKSTEP_Master_Out[476] = \<const0> ;
  assign LOCKSTEP_Master_Out[477] = \<const0> ;
  assign LOCKSTEP_Master_Out[478] = \<const0> ;
  assign LOCKSTEP_Master_Out[479] = \<const0> ;
  assign LOCKSTEP_Master_Out[480] = \<const0> ;
  assign LOCKSTEP_Master_Out[481] = \<const0> ;
  assign LOCKSTEP_Master_Out[482] = \<const0> ;
  assign LOCKSTEP_Master_Out[483] = \<const0> ;
  assign LOCKSTEP_Master_Out[484] = \<const0> ;
  assign LOCKSTEP_Master_Out[485] = \<const0> ;
  assign LOCKSTEP_Master_Out[486] = \<const0> ;
  assign LOCKSTEP_Master_Out[487] = \<const0> ;
  assign LOCKSTEP_Master_Out[488] = \<const0> ;
  assign LOCKSTEP_Master_Out[489] = \<const0> ;
  assign LOCKSTEP_Master_Out[490] = \<const0> ;
  assign LOCKSTEP_Master_Out[491] = \<const0> ;
  assign LOCKSTEP_Master_Out[492] = \<const0> ;
  assign LOCKSTEP_Master_Out[493] = \<const0> ;
  assign LOCKSTEP_Master_Out[494] = \<const0> ;
  assign LOCKSTEP_Master_Out[495] = \<const0> ;
  assign LOCKSTEP_Master_Out[496] = \<const0> ;
  assign LOCKSTEP_Master_Out[497] = \<const0> ;
  assign LOCKSTEP_Master_Out[498] = \<const0> ;
  assign LOCKSTEP_Master_Out[499] = \<const0> ;
  assign LOCKSTEP_Master_Out[500] = \<const0> ;
  assign LOCKSTEP_Master_Out[501] = \<const0> ;
  assign LOCKSTEP_Master_Out[502] = \<const0> ;
  assign LOCKSTEP_Master_Out[503] = \<const0> ;
  assign LOCKSTEP_Master_Out[504] = \<const0> ;
  assign LOCKSTEP_Master_Out[505] = \<const0> ;
  assign LOCKSTEP_Master_Out[506] = \<const0> ;
  assign LOCKSTEP_Master_Out[507] = \<const0> ;
  assign LOCKSTEP_Master_Out[508] = \<const0> ;
  assign LOCKSTEP_Master_Out[509] = \<const0> ;
  assign LOCKSTEP_Master_Out[510] = \<const0> ;
  assign LOCKSTEP_Master_Out[511] = \<const0> ;
  assign LOCKSTEP_Master_Out[512] = \<const0> ;
  assign LOCKSTEP_Master_Out[513] = \<const0> ;
  assign LOCKSTEP_Master_Out[514] = \<const0> ;
  assign LOCKSTEP_Master_Out[515] = \<const0> ;
  assign LOCKSTEP_Master_Out[516] = \<const0> ;
  assign LOCKSTEP_Master_Out[517] = \<const0> ;
  assign LOCKSTEP_Master_Out[518] = \<const0> ;
  assign LOCKSTEP_Master_Out[519] = \<const0> ;
  assign LOCKSTEP_Master_Out[520] = \<const0> ;
  assign LOCKSTEP_Master_Out[521] = \<const0> ;
  assign LOCKSTEP_Master_Out[522] = \<const0> ;
  assign LOCKSTEP_Master_Out[523] = \<const0> ;
  assign LOCKSTEP_Master_Out[524] = \<const0> ;
  assign LOCKSTEP_Master_Out[525] = \<const0> ;
  assign LOCKSTEP_Master_Out[526] = \<const0> ;
  assign LOCKSTEP_Master_Out[527] = \<const0> ;
  assign LOCKSTEP_Master_Out[528] = \<const0> ;
  assign LOCKSTEP_Master_Out[529] = \<const0> ;
  assign LOCKSTEP_Master_Out[530] = \<const0> ;
  assign LOCKSTEP_Master_Out[531] = \<const0> ;
  assign LOCKSTEP_Master_Out[532] = \<const0> ;
  assign LOCKSTEP_Master_Out[533] = \<const0> ;
  assign LOCKSTEP_Master_Out[534] = \<const0> ;
  assign LOCKSTEP_Master_Out[535] = \<const0> ;
  assign LOCKSTEP_Master_Out[536] = \<const0> ;
  assign LOCKSTEP_Master_Out[537] = \<const0> ;
  assign LOCKSTEP_Master_Out[538] = \<const0> ;
  assign LOCKSTEP_Master_Out[539] = \<const0> ;
  assign LOCKSTEP_Master_Out[540] = \<const0> ;
  assign LOCKSTEP_Master_Out[541] = \<const0> ;
  assign LOCKSTEP_Master_Out[542] = \<const0> ;
  assign LOCKSTEP_Master_Out[543] = \<const0> ;
  assign LOCKSTEP_Master_Out[544] = \<const0> ;
  assign LOCKSTEP_Master_Out[545] = \<const0> ;
  assign LOCKSTEP_Master_Out[546] = \<const0> ;
  assign LOCKSTEP_Master_Out[547] = \<const0> ;
  assign LOCKSTEP_Master_Out[548] = \<const0> ;
  assign LOCKSTEP_Master_Out[549] = \<const0> ;
  assign LOCKSTEP_Master_Out[550] = \<const0> ;
  assign LOCKSTEP_Master_Out[551] = \<const0> ;
  assign LOCKSTEP_Master_Out[552] = \<const0> ;
  assign LOCKSTEP_Master_Out[553] = \<const0> ;
  assign LOCKSTEP_Master_Out[554] = \<const0> ;
  assign LOCKSTEP_Master_Out[555] = \<const0> ;
  assign LOCKSTEP_Master_Out[556] = \<const0> ;
  assign LOCKSTEP_Master_Out[557] = \<const0> ;
  assign LOCKSTEP_Master_Out[558] = \<const0> ;
  assign LOCKSTEP_Master_Out[559] = \<const0> ;
  assign LOCKSTEP_Master_Out[560] = \<const0> ;
  assign LOCKSTEP_Master_Out[561] = \<const0> ;
  assign LOCKSTEP_Master_Out[562] = \<const0> ;
  assign LOCKSTEP_Master_Out[563] = \<const0> ;
  assign LOCKSTEP_Master_Out[564] = \<const0> ;
  assign LOCKSTEP_Master_Out[565] = \<const0> ;
  assign LOCKSTEP_Master_Out[566] = \<const0> ;
  assign LOCKSTEP_Master_Out[567] = \<const0> ;
  assign LOCKSTEP_Master_Out[568] = \<const0> ;
  assign LOCKSTEP_Master_Out[569] = \<const0> ;
  assign LOCKSTEP_Master_Out[570] = \<const0> ;
  assign LOCKSTEP_Master_Out[571] = \<const0> ;
  assign LOCKSTEP_Master_Out[572] = \<const0> ;
  assign LOCKSTEP_Master_Out[573] = \<const0> ;
  assign LOCKSTEP_Master_Out[574] = \<const0> ;
  assign LOCKSTEP_Master_Out[575] = \<const0> ;
  assign LOCKSTEP_Master_Out[576] = \<const0> ;
  assign LOCKSTEP_Master_Out[577] = \<const0> ;
  assign LOCKSTEP_Master_Out[578] = \<const0> ;
  assign LOCKSTEP_Master_Out[579] = \<const0> ;
  assign LOCKSTEP_Master_Out[580] = \<const0> ;
  assign LOCKSTEP_Master_Out[581] = \<const0> ;
  assign LOCKSTEP_Master_Out[582] = \<const0> ;
  assign LOCKSTEP_Master_Out[583] = \<const0> ;
  assign LOCKSTEP_Master_Out[584] = \<const0> ;
  assign LOCKSTEP_Master_Out[585] = \<const0> ;
  assign LOCKSTEP_Master_Out[586] = \<const0> ;
  assign LOCKSTEP_Master_Out[587] = \<const0> ;
  assign LOCKSTEP_Master_Out[588] = \<const0> ;
  assign LOCKSTEP_Master_Out[589] = \<const0> ;
  assign LOCKSTEP_Master_Out[590] = \<const0> ;
  assign LOCKSTEP_Master_Out[591] = \<const0> ;
  assign LOCKSTEP_Master_Out[592] = \<const0> ;
  assign LOCKSTEP_Master_Out[593] = \<const0> ;
  assign LOCKSTEP_Master_Out[594] = \<const0> ;
  assign LOCKSTEP_Master_Out[595] = \<const0> ;
  assign LOCKSTEP_Master_Out[596] = \<const0> ;
  assign LOCKSTEP_Master_Out[597] = \<const0> ;
  assign LOCKSTEP_Master_Out[598] = \<const0> ;
  assign LOCKSTEP_Master_Out[599] = \<const0> ;
  assign LOCKSTEP_Master_Out[600] = \<const0> ;
  assign LOCKSTEP_Master_Out[601] = \<const0> ;
  assign LOCKSTEP_Master_Out[602] = \<const0> ;
  assign LOCKSTEP_Master_Out[603] = \<const0> ;
  assign LOCKSTEP_Master_Out[604] = \<const0> ;
  assign LOCKSTEP_Master_Out[605] = \<const0> ;
  assign LOCKSTEP_Master_Out[606] = \<const0> ;
  assign LOCKSTEP_Master_Out[607] = \<const0> ;
  assign LOCKSTEP_Master_Out[608] = \<const0> ;
  assign LOCKSTEP_Master_Out[609] = \<const0> ;
  assign LOCKSTEP_Master_Out[610] = \<const0> ;
  assign LOCKSTEP_Master_Out[611] = \<const0> ;
  assign LOCKSTEP_Master_Out[612] = \<const0> ;
  assign LOCKSTEP_Master_Out[613] = \<const0> ;
  assign LOCKSTEP_Master_Out[614] = \<const0> ;
  assign LOCKSTEP_Master_Out[615] = \<const0> ;
  assign LOCKSTEP_Master_Out[616] = \<const0> ;
  assign LOCKSTEP_Master_Out[617] = \<const0> ;
  assign LOCKSTEP_Master_Out[618] = \<const0> ;
  assign LOCKSTEP_Master_Out[619] = \<const0> ;
  assign LOCKSTEP_Master_Out[620] = \<const0> ;
  assign LOCKSTEP_Master_Out[621] = \<const0> ;
  assign LOCKSTEP_Master_Out[622] = \<const0> ;
  assign LOCKSTEP_Master_Out[623] = \<const0> ;
  assign LOCKSTEP_Master_Out[624] = \<const0> ;
  assign LOCKSTEP_Master_Out[625] = \<const0> ;
  assign LOCKSTEP_Master_Out[626] = \<const0> ;
  assign LOCKSTEP_Master_Out[627] = \<const0> ;
  assign LOCKSTEP_Master_Out[628] = \<const0> ;
  assign LOCKSTEP_Master_Out[629] = \<const0> ;
  assign LOCKSTEP_Master_Out[630] = \<const0> ;
  assign LOCKSTEP_Master_Out[631] = \<const0> ;
  assign LOCKSTEP_Master_Out[632] = \<const0> ;
  assign LOCKSTEP_Master_Out[633] = \<const0> ;
  assign LOCKSTEP_Master_Out[634] = \<const0> ;
  assign LOCKSTEP_Master_Out[635] = \<const0> ;
  assign LOCKSTEP_Master_Out[636] = \<const0> ;
  assign LOCKSTEP_Master_Out[637] = \<const0> ;
  assign LOCKSTEP_Master_Out[638] = \<const0> ;
  assign LOCKSTEP_Master_Out[639] = \<const0> ;
  assign LOCKSTEP_Master_Out[640] = \<const0> ;
  assign LOCKSTEP_Master_Out[641] = \<const0> ;
  assign LOCKSTEP_Master_Out[642] = \<const0> ;
  assign LOCKSTEP_Master_Out[643] = \<const0> ;
  assign LOCKSTEP_Master_Out[644] = \<const0> ;
  assign LOCKSTEP_Master_Out[645] = \<const0> ;
  assign LOCKSTEP_Master_Out[646] = \<const0> ;
  assign LOCKSTEP_Master_Out[647] = \<const0> ;
  assign LOCKSTEP_Master_Out[648] = \<const0> ;
  assign LOCKSTEP_Master_Out[649] = \<const0> ;
  assign LOCKSTEP_Master_Out[650] = \<const0> ;
  assign LOCKSTEP_Master_Out[651] = \<const0> ;
  assign LOCKSTEP_Master_Out[652] = \<const0> ;
  assign LOCKSTEP_Master_Out[653] = \<const0> ;
  assign LOCKSTEP_Master_Out[654] = \<const0> ;
  assign LOCKSTEP_Master_Out[655] = \<const0> ;
  assign LOCKSTEP_Master_Out[656] = \<const0> ;
  assign LOCKSTEP_Master_Out[657] = \<const0> ;
  assign LOCKSTEP_Master_Out[658] = \<const0> ;
  assign LOCKSTEP_Master_Out[659] = \<const0> ;
  assign LOCKSTEP_Master_Out[660] = \<const0> ;
  assign LOCKSTEP_Master_Out[661] = \<const0> ;
  assign LOCKSTEP_Master_Out[662] = \<const0> ;
  assign LOCKSTEP_Master_Out[663] = \<const0> ;
  assign LOCKSTEP_Master_Out[664] = \<const0> ;
  assign LOCKSTEP_Master_Out[665] = \<const0> ;
  assign LOCKSTEP_Master_Out[666] = \<const0> ;
  assign LOCKSTEP_Master_Out[667] = \<const0> ;
  assign LOCKSTEP_Master_Out[668] = \<const0> ;
  assign LOCKSTEP_Master_Out[669] = \<const0> ;
  assign LOCKSTEP_Master_Out[670] = \<const0> ;
  assign LOCKSTEP_Master_Out[671] = \<const0> ;
  assign LOCKSTEP_Master_Out[672] = \<const0> ;
  assign LOCKSTEP_Master_Out[673] = \<const0> ;
  assign LOCKSTEP_Master_Out[674] = \<const0> ;
  assign LOCKSTEP_Master_Out[675] = \<const0> ;
  assign LOCKSTEP_Master_Out[676] = \<const0> ;
  assign LOCKSTEP_Master_Out[677] = \<const0> ;
  assign LOCKSTEP_Master_Out[678] = \<const0> ;
  assign LOCKSTEP_Master_Out[679] = \<const0> ;
  assign LOCKSTEP_Master_Out[680] = \<const0> ;
  assign LOCKSTEP_Master_Out[681] = \<const0> ;
  assign LOCKSTEP_Master_Out[682] = \<const0> ;
  assign LOCKSTEP_Master_Out[683] = \<const0> ;
  assign LOCKSTEP_Master_Out[684] = \<const0> ;
  assign LOCKSTEP_Master_Out[685] = \<const0> ;
  assign LOCKSTEP_Master_Out[686] = \<const0> ;
  assign LOCKSTEP_Master_Out[687] = \<const0> ;
  assign LOCKSTEP_Master_Out[688] = \<const0> ;
  assign LOCKSTEP_Master_Out[689] = \<const0> ;
  assign LOCKSTEP_Master_Out[690] = \<const0> ;
  assign LOCKSTEP_Master_Out[691] = \<const0> ;
  assign LOCKSTEP_Master_Out[692] = \<const0> ;
  assign LOCKSTEP_Master_Out[693] = \<const0> ;
  assign LOCKSTEP_Master_Out[694] = \<const0> ;
  assign LOCKSTEP_Master_Out[695] = \<const0> ;
  assign LOCKSTEP_Master_Out[696] = \<const0> ;
  assign LOCKSTEP_Master_Out[697] = \<const0> ;
  assign LOCKSTEP_Master_Out[698] = \<const0> ;
  assign LOCKSTEP_Master_Out[699] = \<const0> ;
  assign LOCKSTEP_Master_Out[700] = \<const0> ;
  assign LOCKSTEP_Master_Out[701] = \<const0> ;
  assign LOCKSTEP_Master_Out[702] = \<const0> ;
  assign LOCKSTEP_Master_Out[703] = \<const0> ;
  assign LOCKSTEP_Master_Out[704] = \<const0> ;
  assign LOCKSTEP_Master_Out[705] = \<const0> ;
  assign LOCKSTEP_Master_Out[706] = \<const0> ;
  assign LOCKSTEP_Master_Out[707] = \<const0> ;
  assign LOCKSTEP_Master_Out[708] = \<const0> ;
  assign LOCKSTEP_Master_Out[709] = \<const0> ;
  assign LOCKSTEP_Master_Out[710] = \<const0> ;
  assign LOCKSTEP_Master_Out[711] = \<const0> ;
  assign LOCKSTEP_Master_Out[712] = \<const0> ;
  assign LOCKSTEP_Master_Out[713] = \<const0> ;
  assign LOCKSTEP_Master_Out[714] = \<const0> ;
  assign LOCKSTEP_Master_Out[715] = \<const0> ;
  assign LOCKSTEP_Master_Out[716] = \<const0> ;
  assign LOCKSTEP_Master_Out[717] = \<const0> ;
  assign LOCKSTEP_Master_Out[718] = \<const0> ;
  assign LOCKSTEP_Master_Out[719] = \<const0> ;
  assign LOCKSTEP_Master_Out[720] = \<const0> ;
  assign LOCKSTEP_Master_Out[721] = \<const0> ;
  assign LOCKSTEP_Master_Out[722] = \<const0> ;
  assign LOCKSTEP_Master_Out[723] = \<const0> ;
  assign LOCKSTEP_Master_Out[724] = \<const0> ;
  assign LOCKSTEP_Master_Out[725] = \<const0> ;
  assign LOCKSTEP_Master_Out[726] = \<const0> ;
  assign LOCKSTEP_Master_Out[727] = \<const0> ;
  assign LOCKSTEP_Master_Out[728] = \<const0> ;
  assign LOCKSTEP_Master_Out[729] = \<const0> ;
  assign LOCKSTEP_Master_Out[730] = \<const0> ;
  assign LOCKSTEP_Master_Out[731] = \<const0> ;
  assign LOCKSTEP_Master_Out[732] = \<const0> ;
  assign LOCKSTEP_Master_Out[733] = \<const0> ;
  assign LOCKSTEP_Master_Out[734] = \<const0> ;
  assign LOCKSTEP_Master_Out[735] = \<const0> ;
  assign LOCKSTEP_Master_Out[736] = \<const0> ;
  assign LOCKSTEP_Master_Out[737] = \<const0> ;
  assign LOCKSTEP_Master_Out[738] = \<const0> ;
  assign LOCKSTEP_Master_Out[739] = \<const0> ;
  assign LOCKSTEP_Master_Out[740] = \<const0> ;
  assign LOCKSTEP_Master_Out[741] = \<const0> ;
  assign LOCKSTEP_Master_Out[742] = \<const0> ;
  assign LOCKSTEP_Master_Out[743] = \<const0> ;
  assign LOCKSTEP_Master_Out[744] = \<const0> ;
  assign LOCKSTEP_Master_Out[745] = \<const0> ;
  assign LOCKSTEP_Master_Out[746] = \<const0> ;
  assign LOCKSTEP_Master_Out[747] = \<const0> ;
  assign LOCKSTEP_Master_Out[748] = \<const0> ;
  assign LOCKSTEP_Master_Out[749] = \<const0> ;
  assign LOCKSTEP_Master_Out[750] = \<const0> ;
  assign LOCKSTEP_Master_Out[751] = \<const0> ;
  assign LOCKSTEP_Master_Out[752] = \<const0> ;
  assign LOCKSTEP_Master_Out[753] = \<const0> ;
  assign LOCKSTEP_Master_Out[754] = \<const0> ;
  assign LOCKSTEP_Master_Out[755] = \<const0> ;
  assign LOCKSTEP_Master_Out[756] = \<const0> ;
  assign LOCKSTEP_Master_Out[757] = \<const0> ;
  assign LOCKSTEP_Master_Out[758] = \<const0> ;
  assign LOCKSTEP_Master_Out[759] = \<const0> ;
  assign LOCKSTEP_Master_Out[760] = \<const0> ;
  assign LOCKSTEP_Master_Out[761] = \<const0> ;
  assign LOCKSTEP_Master_Out[762] = \<const0> ;
  assign LOCKSTEP_Master_Out[763] = \<const0> ;
  assign LOCKSTEP_Master_Out[764] = \<const0> ;
  assign LOCKSTEP_Master_Out[765] = \<const0> ;
  assign LOCKSTEP_Master_Out[766] = \<const0> ;
  assign LOCKSTEP_Master_Out[767] = \<const0> ;
  assign LOCKSTEP_Master_Out[768] = \<const0> ;
  assign LOCKSTEP_Master_Out[769] = \<const0> ;
  assign LOCKSTEP_Master_Out[770] = \<const0> ;
  assign LOCKSTEP_Master_Out[771] = \<const0> ;
  assign LOCKSTEP_Master_Out[772] = \<const0> ;
  assign LOCKSTEP_Master_Out[773] = \<const0> ;
  assign LOCKSTEP_Master_Out[774] = \<const0> ;
  assign LOCKSTEP_Master_Out[775] = \<const0> ;
  assign LOCKSTEP_Master_Out[776] = \<const0> ;
  assign LOCKSTEP_Master_Out[777] = \<const0> ;
  assign LOCKSTEP_Master_Out[778] = \<const0> ;
  assign LOCKSTEP_Master_Out[779] = \<const0> ;
  assign LOCKSTEP_Master_Out[780] = \<const0> ;
  assign LOCKSTEP_Master_Out[781] = \<const0> ;
  assign LOCKSTEP_Master_Out[782] = \<const0> ;
  assign LOCKSTEP_Master_Out[783] = \<const0> ;
  assign LOCKSTEP_Master_Out[784] = \<const0> ;
  assign LOCKSTEP_Master_Out[785] = \<const0> ;
  assign LOCKSTEP_Master_Out[786] = \<const0> ;
  assign LOCKSTEP_Master_Out[787] = \<const0> ;
  assign LOCKSTEP_Master_Out[788] = \<const0> ;
  assign LOCKSTEP_Master_Out[789] = \<const0> ;
  assign LOCKSTEP_Master_Out[790] = \<const0> ;
  assign LOCKSTEP_Master_Out[791] = \<const0> ;
  assign LOCKSTEP_Master_Out[792] = \<const0> ;
  assign LOCKSTEP_Master_Out[793] = \<const0> ;
  assign LOCKSTEP_Master_Out[794] = \<const0> ;
  assign LOCKSTEP_Master_Out[795] = \<const0> ;
  assign LOCKSTEP_Master_Out[796] = \<const0> ;
  assign LOCKSTEP_Master_Out[797] = \<const0> ;
  assign LOCKSTEP_Master_Out[798] = \<const0> ;
  assign LOCKSTEP_Master_Out[799] = \<const0> ;
  assign LOCKSTEP_Master_Out[800] = \<const0> ;
  assign LOCKSTEP_Master_Out[801] = \<const0> ;
  assign LOCKSTEP_Master_Out[802] = \<const0> ;
  assign LOCKSTEP_Master_Out[803] = \<const0> ;
  assign LOCKSTEP_Master_Out[804] = \<const0> ;
  assign LOCKSTEP_Master_Out[805] = \<const0> ;
  assign LOCKSTEP_Master_Out[806] = \<const0> ;
  assign LOCKSTEP_Master_Out[807] = \<const0> ;
  assign LOCKSTEP_Master_Out[808] = \<const0> ;
  assign LOCKSTEP_Master_Out[809] = \<const0> ;
  assign LOCKSTEP_Master_Out[810] = \<const0> ;
  assign LOCKSTEP_Master_Out[811] = \<const0> ;
  assign LOCKSTEP_Master_Out[812] = \<const0> ;
  assign LOCKSTEP_Master_Out[813] = \<const0> ;
  assign LOCKSTEP_Master_Out[814] = \<const0> ;
  assign LOCKSTEP_Master_Out[815] = \<const0> ;
  assign LOCKSTEP_Master_Out[816] = \<const0> ;
  assign LOCKSTEP_Master_Out[817] = \<const0> ;
  assign LOCKSTEP_Master_Out[818] = \<const0> ;
  assign LOCKSTEP_Master_Out[819] = \<const0> ;
  assign LOCKSTEP_Master_Out[820] = \<const0> ;
  assign LOCKSTEP_Master_Out[821] = \<const0> ;
  assign LOCKSTEP_Master_Out[822] = \<const0> ;
  assign LOCKSTEP_Master_Out[823] = \<const0> ;
  assign LOCKSTEP_Master_Out[824] = \<const0> ;
  assign LOCKSTEP_Master_Out[825] = \<const0> ;
  assign LOCKSTEP_Master_Out[826] = \<const0> ;
  assign LOCKSTEP_Master_Out[827] = \<const0> ;
  assign LOCKSTEP_Master_Out[828] = \<const0> ;
  assign LOCKSTEP_Master_Out[829] = \<const0> ;
  assign LOCKSTEP_Master_Out[830] = \<const0> ;
  assign LOCKSTEP_Master_Out[831] = \<const0> ;
  assign LOCKSTEP_Master_Out[832] = \<const0> ;
  assign LOCKSTEP_Master_Out[833] = \<const0> ;
  assign LOCKSTEP_Master_Out[834] = \<const0> ;
  assign LOCKSTEP_Master_Out[835] = \<const0> ;
  assign LOCKSTEP_Master_Out[836] = \<const0> ;
  assign LOCKSTEP_Master_Out[837] = \<const0> ;
  assign LOCKSTEP_Master_Out[838] = \<const0> ;
  assign LOCKSTEP_Master_Out[839] = \<const0> ;
  assign LOCKSTEP_Master_Out[840] = \<const0> ;
  assign LOCKSTEP_Master_Out[841] = \<const0> ;
  assign LOCKSTEP_Master_Out[842] = \<const0> ;
  assign LOCKSTEP_Master_Out[843] = \<const0> ;
  assign LOCKSTEP_Master_Out[844] = \<const0> ;
  assign LOCKSTEP_Master_Out[845] = \<const0> ;
  assign LOCKSTEP_Master_Out[846] = \<const0> ;
  assign LOCKSTEP_Master_Out[847] = \<const0> ;
  assign LOCKSTEP_Master_Out[848] = \<const0> ;
  assign LOCKSTEP_Master_Out[849] = \<const0> ;
  assign LOCKSTEP_Master_Out[850] = \<const0> ;
  assign LOCKSTEP_Master_Out[851] = \<const0> ;
  assign LOCKSTEP_Master_Out[852] = \<const0> ;
  assign LOCKSTEP_Master_Out[853] = \<const0> ;
  assign LOCKSTEP_Master_Out[854] = \<const0> ;
  assign LOCKSTEP_Master_Out[855] = \<const0> ;
  assign LOCKSTEP_Master_Out[856] = \<const0> ;
  assign LOCKSTEP_Master_Out[857] = \<const0> ;
  assign LOCKSTEP_Master_Out[858] = \<const0> ;
  assign LOCKSTEP_Master_Out[859] = \<const0> ;
  assign LOCKSTEP_Master_Out[860] = \<const0> ;
  assign LOCKSTEP_Master_Out[861] = \<const0> ;
  assign LOCKSTEP_Master_Out[862] = \<const0> ;
  assign LOCKSTEP_Master_Out[863] = \<const0> ;
  assign LOCKSTEP_Master_Out[864] = \<const0> ;
  assign LOCKSTEP_Master_Out[865] = \<const0> ;
  assign LOCKSTEP_Master_Out[866] = \<const0> ;
  assign LOCKSTEP_Master_Out[867] = \<const0> ;
  assign LOCKSTEP_Master_Out[868] = \<const0> ;
  assign LOCKSTEP_Master_Out[869] = \<const0> ;
  assign LOCKSTEP_Master_Out[870] = \<const0> ;
  assign LOCKSTEP_Master_Out[871] = \<const0> ;
  assign LOCKSTEP_Master_Out[872] = \<const0> ;
  assign LOCKSTEP_Master_Out[873] = \<const0> ;
  assign LOCKSTEP_Master_Out[874] = \<const0> ;
  assign LOCKSTEP_Master_Out[875] = \<const0> ;
  assign LOCKSTEP_Master_Out[876] = \<const0> ;
  assign LOCKSTEP_Master_Out[877] = \<const0> ;
  assign LOCKSTEP_Master_Out[878] = \<const0> ;
  assign LOCKSTEP_Master_Out[879] = \<const0> ;
  assign LOCKSTEP_Master_Out[880] = \<const0> ;
  assign LOCKSTEP_Master_Out[881] = \<const0> ;
  assign LOCKSTEP_Master_Out[882] = \<const0> ;
  assign LOCKSTEP_Master_Out[883] = \<const0> ;
  assign LOCKSTEP_Master_Out[884] = \<const0> ;
  assign LOCKSTEP_Master_Out[885] = \<const0> ;
  assign LOCKSTEP_Master_Out[886] = \<const0> ;
  assign LOCKSTEP_Master_Out[887] = \<const0> ;
  assign LOCKSTEP_Master_Out[888] = \<const0> ;
  assign LOCKSTEP_Master_Out[889] = \<const0> ;
  assign LOCKSTEP_Master_Out[890] = \<const0> ;
  assign LOCKSTEP_Master_Out[891] = \<const0> ;
  assign LOCKSTEP_Master_Out[892] = \<const0> ;
  assign LOCKSTEP_Master_Out[893] = \<const0> ;
  assign LOCKSTEP_Master_Out[894] = \<const0> ;
  assign LOCKSTEP_Master_Out[895] = \<const0> ;
  assign LOCKSTEP_Master_Out[896] = \<const0> ;
  assign LOCKSTEP_Master_Out[897] = \<const0> ;
  assign LOCKSTEP_Master_Out[898] = \<const0> ;
  assign LOCKSTEP_Master_Out[899] = \<const0> ;
  assign LOCKSTEP_Master_Out[900] = \<const0> ;
  assign LOCKSTEP_Master_Out[901] = \<const0> ;
  assign LOCKSTEP_Master_Out[902] = \<const0> ;
  assign LOCKSTEP_Master_Out[903] = \<const0> ;
  assign LOCKSTEP_Master_Out[904] = \<const0> ;
  assign LOCKSTEP_Master_Out[905] = \<const0> ;
  assign LOCKSTEP_Master_Out[906] = \<const0> ;
  assign LOCKSTEP_Master_Out[907] = \<const0> ;
  assign LOCKSTEP_Master_Out[908] = \<const0> ;
  assign LOCKSTEP_Master_Out[909] = \<const0> ;
  assign LOCKSTEP_Master_Out[910] = \<const0> ;
  assign LOCKSTEP_Master_Out[911] = \<const0> ;
  assign LOCKSTEP_Master_Out[912] = \<const0> ;
  assign LOCKSTEP_Master_Out[913] = \<const0> ;
  assign LOCKSTEP_Master_Out[914] = \<const0> ;
  assign LOCKSTEP_Master_Out[915] = \<const0> ;
  assign LOCKSTEP_Master_Out[916] = \<const0> ;
  assign LOCKSTEP_Master_Out[917] = \<const0> ;
  assign LOCKSTEP_Master_Out[918] = \<const0> ;
  assign LOCKSTEP_Master_Out[919] = \<const0> ;
  assign LOCKSTEP_Master_Out[920] = \<const0> ;
  assign LOCKSTEP_Master_Out[921] = \<const0> ;
  assign LOCKSTEP_Master_Out[922] = \<const0> ;
  assign LOCKSTEP_Master_Out[923] = \<const0> ;
  assign LOCKSTEP_Master_Out[924] = \<const0> ;
  assign LOCKSTEP_Master_Out[925] = \<const0> ;
  assign LOCKSTEP_Master_Out[926] = \<const0> ;
  assign LOCKSTEP_Master_Out[927] = \<const0> ;
  assign LOCKSTEP_Master_Out[928] = \<const0> ;
  assign LOCKSTEP_Master_Out[929] = \<const0> ;
  assign LOCKSTEP_Master_Out[930] = \<const0> ;
  assign LOCKSTEP_Master_Out[931] = \<const0> ;
  assign LOCKSTEP_Master_Out[932] = \<const0> ;
  assign LOCKSTEP_Master_Out[933] = \<const0> ;
  assign LOCKSTEP_Master_Out[934] = \<const0> ;
  assign LOCKSTEP_Master_Out[935] = \<const0> ;
  assign LOCKSTEP_Master_Out[936] = \<const0> ;
  assign LOCKSTEP_Master_Out[937] = \<const0> ;
  assign LOCKSTEP_Master_Out[938] = \<const0> ;
  assign LOCKSTEP_Master_Out[939] = \<const0> ;
  assign LOCKSTEP_Master_Out[940] = \<const0> ;
  assign LOCKSTEP_Master_Out[941] = \<const0> ;
  assign LOCKSTEP_Master_Out[942] = \<const0> ;
  assign LOCKSTEP_Master_Out[943] = \<const0> ;
  assign LOCKSTEP_Master_Out[944] = \<const0> ;
  assign LOCKSTEP_Master_Out[945] = \<const0> ;
  assign LOCKSTEP_Master_Out[946] = \<const0> ;
  assign LOCKSTEP_Master_Out[947] = \<const0> ;
  assign LOCKSTEP_Master_Out[948] = \<const0> ;
  assign LOCKSTEP_Master_Out[949] = \<const0> ;
  assign LOCKSTEP_Master_Out[950] = \<const0> ;
  assign LOCKSTEP_Master_Out[951] = \<const0> ;
  assign LOCKSTEP_Master_Out[952] = \<const0> ;
  assign LOCKSTEP_Master_Out[953] = \<const0> ;
  assign LOCKSTEP_Master_Out[954] = \<const0> ;
  assign LOCKSTEP_Master_Out[955] = \<const0> ;
  assign LOCKSTEP_Master_Out[956] = \<const0> ;
  assign LOCKSTEP_Master_Out[957] = \<const0> ;
  assign LOCKSTEP_Master_Out[958] = \<const0> ;
  assign LOCKSTEP_Master_Out[959] = \<const0> ;
  assign LOCKSTEP_Master_Out[960] = \<const0> ;
  assign LOCKSTEP_Master_Out[961] = \<const0> ;
  assign LOCKSTEP_Master_Out[962] = \<const0> ;
  assign LOCKSTEP_Master_Out[963] = \<const0> ;
  assign LOCKSTEP_Master_Out[964] = \<const0> ;
  assign LOCKSTEP_Master_Out[965] = \<const0> ;
  assign LOCKSTEP_Master_Out[966] = \<const0> ;
  assign LOCKSTEP_Master_Out[967] = \<const0> ;
  assign LOCKSTEP_Master_Out[968] = \<const0> ;
  assign LOCKSTEP_Master_Out[969] = \<const0> ;
  assign LOCKSTEP_Master_Out[970] = \<const0> ;
  assign LOCKSTEP_Master_Out[971] = \<const0> ;
  assign LOCKSTEP_Master_Out[972] = \<const0> ;
  assign LOCKSTEP_Master_Out[973] = \<const0> ;
  assign LOCKSTEP_Master_Out[974] = \<const0> ;
  assign LOCKSTEP_Master_Out[975] = \<const0> ;
  assign LOCKSTEP_Master_Out[976] = \<const0> ;
  assign LOCKSTEP_Master_Out[977] = \<const0> ;
  assign LOCKSTEP_Master_Out[978] = \<const0> ;
  assign LOCKSTEP_Master_Out[979] = \<const0> ;
  assign LOCKSTEP_Master_Out[980] = \<const0> ;
  assign LOCKSTEP_Master_Out[981] = \<const0> ;
  assign LOCKSTEP_Master_Out[982] = \<const0> ;
  assign LOCKSTEP_Master_Out[983] = \<const0> ;
  assign LOCKSTEP_Master_Out[984] = \<const0> ;
  assign LOCKSTEP_Master_Out[985] = \<const0> ;
  assign LOCKSTEP_Master_Out[986] = \<const0> ;
  assign LOCKSTEP_Master_Out[987] = \<const0> ;
  assign LOCKSTEP_Master_Out[988] = \<const0> ;
  assign LOCKSTEP_Master_Out[989] = \<const0> ;
  assign LOCKSTEP_Master_Out[990] = \<const0> ;
  assign LOCKSTEP_Master_Out[991] = \<const0> ;
  assign LOCKSTEP_Master_Out[992] = \<const0> ;
  assign LOCKSTEP_Master_Out[993] = \<const0> ;
  assign LOCKSTEP_Master_Out[994] = \<const0> ;
  assign LOCKSTEP_Master_Out[995] = \<const0> ;
  assign LOCKSTEP_Master_Out[996] = \<const0> ;
  assign LOCKSTEP_Master_Out[997] = \<const0> ;
  assign LOCKSTEP_Master_Out[998] = \<const0> ;
  assign LOCKSTEP_Master_Out[999] = \<const0> ;
  assign LOCKSTEP_Master_Out[1000] = \<const0> ;
  assign LOCKSTEP_Master_Out[1001] = \<const0> ;
  assign LOCKSTEP_Master_Out[1002] = \<const0> ;
  assign LOCKSTEP_Master_Out[1003] = \<const0> ;
  assign LOCKSTEP_Master_Out[1004] = \<const0> ;
  assign LOCKSTEP_Master_Out[1005] = \<const0> ;
  assign LOCKSTEP_Master_Out[1006] = \<const0> ;
  assign LOCKSTEP_Master_Out[1007] = \<const0> ;
  assign LOCKSTEP_Master_Out[1008] = \<const0> ;
  assign LOCKSTEP_Master_Out[1009] = \<const0> ;
  assign LOCKSTEP_Master_Out[1010] = \<const0> ;
  assign LOCKSTEP_Master_Out[1011] = \<const0> ;
  assign LOCKSTEP_Master_Out[1012] = \<const0> ;
  assign LOCKSTEP_Master_Out[1013] = \<const0> ;
  assign LOCKSTEP_Master_Out[1014] = \<const0> ;
  assign LOCKSTEP_Master_Out[1015] = \<const0> ;
  assign LOCKSTEP_Master_Out[1016] = \<const0> ;
  assign LOCKSTEP_Master_Out[1017] = \<const0> ;
  assign LOCKSTEP_Master_Out[1018] = \<const0> ;
  assign LOCKSTEP_Master_Out[1019] = \<const0> ;
  assign LOCKSTEP_Master_Out[1020] = \<const0> ;
  assign LOCKSTEP_Master_Out[1021] = \<const0> ;
  assign LOCKSTEP_Master_Out[1022] = \<const0> ;
  assign LOCKSTEP_Master_Out[1023] = \<const0> ;
  assign LOCKSTEP_Master_Out[1024] = \<const0> ;
  assign LOCKSTEP_Master_Out[1025] = \<const0> ;
  assign LOCKSTEP_Master_Out[1026] = \<const0> ;
  assign LOCKSTEP_Master_Out[1027] = \<const0> ;
  assign LOCKSTEP_Master_Out[1028] = \<const0> ;
  assign LOCKSTEP_Master_Out[1029] = \<const0> ;
  assign LOCKSTEP_Master_Out[1030] = \<const0> ;
  assign LOCKSTEP_Master_Out[1031] = \<const0> ;
  assign LOCKSTEP_Master_Out[1032] = \<const0> ;
  assign LOCKSTEP_Master_Out[1033] = \<const0> ;
  assign LOCKSTEP_Master_Out[1034] = \<const0> ;
  assign LOCKSTEP_Master_Out[1035] = \<const0> ;
  assign LOCKSTEP_Master_Out[1036] = \<const0> ;
  assign LOCKSTEP_Master_Out[1037] = \<const0> ;
  assign LOCKSTEP_Master_Out[1038] = \<const0> ;
  assign LOCKSTEP_Master_Out[1039] = \<const0> ;
  assign LOCKSTEP_Master_Out[1040] = \<const0> ;
  assign LOCKSTEP_Master_Out[1041] = \<const0> ;
  assign LOCKSTEP_Master_Out[1042] = \<const0> ;
  assign LOCKSTEP_Master_Out[1043] = \<const0> ;
  assign LOCKSTEP_Master_Out[1044] = \<const0> ;
  assign LOCKSTEP_Master_Out[1045] = \<const0> ;
  assign LOCKSTEP_Master_Out[1046] = \<const0> ;
  assign LOCKSTEP_Master_Out[1047] = \<const0> ;
  assign LOCKSTEP_Master_Out[1048] = \<const0> ;
  assign LOCKSTEP_Master_Out[1049] = \<const0> ;
  assign LOCKSTEP_Master_Out[1050] = \<const0> ;
  assign LOCKSTEP_Master_Out[1051] = \<const0> ;
  assign LOCKSTEP_Master_Out[1052] = \<const0> ;
  assign LOCKSTEP_Master_Out[1053] = \<const0> ;
  assign LOCKSTEP_Master_Out[1054] = \<const0> ;
  assign LOCKSTEP_Master_Out[1055] = \<const0> ;
  assign LOCKSTEP_Master_Out[1056] = \<const0> ;
  assign LOCKSTEP_Master_Out[1057] = \<const0> ;
  assign LOCKSTEP_Master_Out[1058] = \<const0> ;
  assign LOCKSTEP_Master_Out[1059] = \<const0> ;
  assign LOCKSTEP_Master_Out[1060] = \<const0> ;
  assign LOCKSTEP_Master_Out[1061] = \<const0> ;
  assign LOCKSTEP_Master_Out[1062] = \<const0> ;
  assign LOCKSTEP_Master_Out[1063] = \<const0> ;
  assign LOCKSTEP_Master_Out[1064] = \<const0> ;
  assign LOCKSTEP_Master_Out[1065] = \<const0> ;
  assign LOCKSTEP_Master_Out[1066] = \<const0> ;
  assign LOCKSTEP_Master_Out[1067] = \<const0> ;
  assign LOCKSTEP_Master_Out[1068] = \<const0> ;
  assign LOCKSTEP_Master_Out[1069] = \<const0> ;
  assign LOCKSTEP_Master_Out[1070] = \<const0> ;
  assign LOCKSTEP_Master_Out[1071] = \<const0> ;
  assign LOCKSTEP_Master_Out[1072] = \<const0> ;
  assign LOCKSTEP_Master_Out[1073] = \<const0> ;
  assign LOCKSTEP_Master_Out[1074] = \<const0> ;
  assign LOCKSTEP_Master_Out[1075] = \<const0> ;
  assign LOCKSTEP_Master_Out[1076] = \<const0> ;
  assign LOCKSTEP_Master_Out[1077] = \<const0> ;
  assign LOCKSTEP_Master_Out[1078] = \<const0> ;
  assign LOCKSTEP_Master_Out[1079] = \<const0> ;
  assign LOCKSTEP_Master_Out[1080] = \<const0> ;
  assign LOCKSTEP_Master_Out[1081] = \<const0> ;
  assign LOCKSTEP_Master_Out[1082] = \<const0> ;
  assign LOCKSTEP_Master_Out[1083] = \<const0> ;
  assign LOCKSTEP_Master_Out[1084] = \<const0> ;
  assign LOCKSTEP_Master_Out[1085] = \<const0> ;
  assign LOCKSTEP_Master_Out[1086] = \<const0> ;
  assign LOCKSTEP_Master_Out[1087] = \<const0> ;
  assign LOCKSTEP_Master_Out[1088] = \<const0> ;
  assign LOCKSTEP_Master_Out[1089] = \<const0> ;
  assign LOCKSTEP_Master_Out[1090] = \<const0> ;
  assign LOCKSTEP_Master_Out[1091] = \<const0> ;
  assign LOCKSTEP_Master_Out[1092] = \<const0> ;
  assign LOCKSTEP_Master_Out[1093] = \<const0> ;
  assign LOCKSTEP_Master_Out[1094] = \<const0> ;
  assign LOCKSTEP_Master_Out[1095] = \<const0> ;
  assign LOCKSTEP_Master_Out[1096] = \<const0> ;
  assign LOCKSTEP_Master_Out[1097] = \<const0> ;
  assign LOCKSTEP_Master_Out[1098] = \<const0> ;
  assign LOCKSTEP_Master_Out[1099] = \<const0> ;
  assign LOCKSTEP_Master_Out[1100] = \<const0> ;
  assign LOCKSTEP_Master_Out[1101] = \<const0> ;
  assign LOCKSTEP_Master_Out[1102] = \<const0> ;
  assign LOCKSTEP_Master_Out[1103] = \<const0> ;
  assign LOCKSTEP_Master_Out[1104] = \<const0> ;
  assign LOCKSTEP_Master_Out[1105] = \<const0> ;
  assign LOCKSTEP_Master_Out[1106] = \<const0> ;
  assign LOCKSTEP_Master_Out[1107] = \<const0> ;
  assign LOCKSTEP_Master_Out[1108] = \<const0> ;
  assign LOCKSTEP_Master_Out[1109] = \<const0> ;
  assign LOCKSTEP_Master_Out[1110] = \<const0> ;
  assign LOCKSTEP_Master_Out[1111] = \<const0> ;
  assign LOCKSTEP_Master_Out[1112] = \<const0> ;
  assign LOCKSTEP_Master_Out[1113] = \<const0> ;
  assign LOCKSTEP_Master_Out[1114] = \<const0> ;
  assign LOCKSTEP_Master_Out[1115] = \<const0> ;
  assign LOCKSTEP_Master_Out[1116] = \<const0> ;
  assign LOCKSTEP_Master_Out[1117] = \<const0> ;
  assign LOCKSTEP_Master_Out[1118] = \<const0> ;
  assign LOCKSTEP_Master_Out[1119] = \<const0> ;
  assign LOCKSTEP_Master_Out[1120] = \<const0> ;
  assign LOCKSTEP_Master_Out[1121] = \<const0> ;
  assign LOCKSTEP_Master_Out[1122] = \<const0> ;
  assign LOCKSTEP_Master_Out[1123] = \<const0> ;
  assign LOCKSTEP_Master_Out[1124] = \<const0> ;
  assign LOCKSTEP_Master_Out[1125] = \<const0> ;
  assign LOCKSTEP_Master_Out[1126] = \<const0> ;
  assign LOCKSTEP_Master_Out[1127] = \<const0> ;
  assign LOCKSTEP_Master_Out[1128] = \<const0> ;
  assign LOCKSTEP_Master_Out[1129] = \<const0> ;
  assign LOCKSTEP_Master_Out[1130] = \<const0> ;
  assign LOCKSTEP_Master_Out[1131] = \<const0> ;
  assign LOCKSTEP_Master_Out[1132] = \<const0> ;
  assign LOCKSTEP_Master_Out[1133] = \<const0> ;
  assign LOCKSTEP_Master_Out[1134] = \<const0> ;
  assign LOCKSTEP_Master_Out[1135] = \<const0> ;
  assign LOCKSTEP_Master_Out[1136] = \<const0> ;
  assign LOCKSTEP_Master_Out[1137] = \<const0> ;
  assign LOCKSTEP_Master_Out[1138] = \<const0> ;
  assign LOCKSTEP_Master_Out[1139] = \<const0> ;
  assign LOCKSTEP_Master_Out[1140] = \<const0> ;
  assign LOCKSTEP_Master_Out[1141] = \<const0> ;
  assign LOCKSTEP_Master_Out[1142] = \<const0> ;
  assign LOCKSTEP_Master_Out[1143] = \<const0> ;
  assign LOCKSTEP_Master_Out[1144] = \<const0> ;
  assign LOCKSTEP_Master_Out[1145] = \<const0> ;
  assign LOCKSTEP_Master_Out[1146] = \<const0> ;
  assign LOCKSTEP_Master_Out[1147] = \<const0> ;
  assign LOCKSTEP_Master_Out[1148] = \<const0> ;
  assign LOCKSTEP_Master_Out[1149] = \<const0> ;
  assign LOCKSTEP_Master_Out[1150] = \<const0> ;
  assign LOCKSTEP_Master_Out[1151] = \<const0> ;
  assign LOCKSTEP_Master_Out[1152] = \<const0> ;
  assign LOCKSTEP_Master_Out[1153] = \<const0> ;
  assign LOCKSTEP_Master_Out[1154] = \<const0> ;
  assign LOCKSTEP_Master_Out[1155] = \<const0> ;
  assign LOCKSTEP_Master_Out[1156] = \<const0> ;
  assign LOCKSTEP_Master_Out[1157] = \<const0> ;
  assign LOCKSTEP_Master_Out[1158] = \<const0> ;
  assign LOCKSTEP_Master_Out[1159] = \<const0> ;
  assign LOCKSTEP_Master_Out[1160] = \<const0> ;
  assign LOCKSTEP_Master_Out[1161] = \<const0> ;
  assign LOCKSTEP_Master_Out[1162] = \<const0> ;
  assign LOCKSTEP_Master_Out[1163] = \<const0> ;
  assign LOCKSTEP_Master_Out[1164] = \<const0> ;
  assign LOCKSTEP_Master_Out[1165] = \<const0> ;
  assign LOCKSTEP_Master_Out[1166] = \<const0> ;
  assign LOCKSTEP_Master_Out[1167] = \<const0> ;
  assign LOCKSTEP_Master_Out[1168] = \<const0> ;
  assign LOCKSTEP_Master_Out[1169] = \<const0> ;
  assign LOCKSTEP_Master_Out[1170] = \<const0> ;
  assign LOCKSTEP_Master_Out[1171] = \<const0> ;
  assign LOCKSTEP_Master_Out[1172] = \<const0> ;
  assign LOCKSTEP_Master_Out[1173] = \<const0> ;
  assign LOCKSTEP_Master_Out[1174] = \<const0> ;
  assign LOCKSTEP_Master_Out[1175] = \<const0> ;
  assign LOCKSTEP_Master_Out[1176] = \<const0> ;
  assign LOCKSTEP_Master_Out[1177] = \<const0> ;
  assign LOCKSTEP_Master_Out[1178] = \<const0> ;
  assign LOCKSTEP_Master_Out[1179] = \<const0> ;
  assign LOCKSTEP_Master_Out[1180] = \<const0> ;
  assign LOCKSTEP_Master_Out[1181] = \<const0> ;
  assign LOCKSTEP_Master_Out[1182] = \<const0> ;
  assign LOCKSTEP_Master_Out[1183] = \<const0> ;
  assign LOCKSTEP_Master_Out[1184] = \<const0> ;
  assign LOCKSTEP_Master_Out[1185] = \<const0> ;
  assign LOCKSTEP_Master_Out[1186] = \<const0> ;
  assign LOCKSTEP_Master_Out[1187] = \<const0> ;
  assign LOCKSTEP_Master_Out[1188] = \<const0> ;
  assign LOCKSTEP_Master_Out[1189] = \<const0> ;
  assign LOCKSTEP_Master_Out[1190] = \<const0> ;
  assign LOCKSTEP_Master_Out[1191] = \<const0> ;
  assign LOCKSTEP_Master_Out[1192] = \<const0> ;
  assign LOCKSTEP_Master_Out[1193] = \<const0> ;
  assign LOCKSTEP_Master_Out[1194] = \<const0> ;
  assign LOCKSTEP_Master_Out[1195] = \<const0> ;
  assign LOCKSTEP_Master_Out[1196] = \<const0> ;
  assign LOCKSTEP_Master_Out[1197] = \<const0> ;
  assign LOCKSTEP_Master_Out[1198] = \<const0> ;
  assign LOCKSTEP_Master_Out[1199] = \<const0> ;
  assign LOCKSTEP_Master_Out[1200] = \<const0> ;
  assign LOCKSTEP_Master_Out[1201] = \<const0> ;
  assign LOCKSTEP_Master_Out[1202] = \<const0> ;
  assign LOCKSTEP_Master_Out[1203] = \<const0> ;
  assign LOCKSTEP_Master_Out[1204] = \<const0> ;
  assign LOCKSTEP_Master_Out[1205] = \<const0> ;
  assign LOCKSTEP_Master_Out[1206] = \<const0> ;
  assign LOCKSTEP_Master_Out[1207] = \<const0> ;
  assign LOCKSTEP_Master_Out[1208] = \<const0> ;
  assign LOCKSTEP_Master_Out[1209] = \<const0> ;
  assign LOCKSTEP_Master_Out[1210] = \<const0> ;
  assign LOCKSTEP_Master_Out[1211] = \<const0> ;
  assign LOCKSTEP_Master_Out[1212] = \<const0> ;
  assign LOCKSTEP_Master_Out[1213] = \<const0> ;
  assign LOCKSTEP_Master_Out[1214] = \<const0> ;
  assign LOCKSTEP_Master_Out[1215] = \<const0> ;
  assign LOCKSTEP_Master_Out[1216] = \<const0> ;
  assign LOCKSTEP_Master_Out[1217] = \<const0> ;
  assign LOCKSTEP_Master_Out[1218] = \<const0> ;
  assign LOCKSTEP_Master_Out[1219] = \<const0> ;
  assign LOCKSTEP_Master_Out[1220] = \<const0> ;
  assign LOCKSTEP_Master_Out[1221] = \<const0> ;
  assign LOCKSTEP_Master_Out[1222] = \<const0> ;
  assign LOCKSTEP_Master_Out[1223] = \<const0> ;
  assign LOCKSTEP_Master_Out[1224] = \<const0> ;
  assign LOCKSTEP_Master_Out[1225] = \<const0> ;
  assign LOCKSTEP_Master_Out[1226] = \<const0> ;
  assign LOCKSTEP_Master_Out[1227] = \<const0> ;
  assign LOCKSTEP_Master_Out[1228] = \<const0> ;
  assign LOCKSTEP_Master_Out[1229] = \<const0> ;
  assign LOCKSTEP_Master_Out[1230] = \<const0> ;
  assign LOCKSTEP_Master_Out[1231] = \<const0> ;
  assign LOCKSTEP_Master_Out[1232] = \<const0> ;
  assign LOCKSTEP_Master_Out[1233] = \<const0> ;
  assign LOCKSTEP_Master_Out[1234] = \<const0> ;
  assign LOCKSTEP_Master_Out[1235] = \<const0> ;
  assign LOCKSTEP_Master_Out[1236] = \<const0> ;
  assign LOCKSTEP_Master_Out[1237] = \<const0> ;
  assign LOCKSTEP_Master_Out[1238] = \<const0> ;
  assign LOCKSTEP_Master_Out[1239] = \<const0> ;
  assign LOCKSTEP_Master_Out[1240] = \<const0> ;
  assign LOCKSTEP_Master_Out[1241] = \<const0> ;
  assign LOCKSTEP_Master_Out[1242] = \<const0> ;
  assign LOCKSTEP_Master_Out[1243] = \<const0> ;
  assign LOCKSTEP_Master_Out[1244] = \<const0> ;
  assign LOCKSTEP_Master_Out[1245] = \<const0> ;
  assign LOCKSTEP_Master_Out[1246] = \<const0> ;
  assign LOCKSTEP_Master_Out[1247] = \<const0> ;
  assign LOCKSTEP_Master_Out[1248] = \<const0> ;
  assign LOCKSTEP_Master_Out[1249] = \<const0> ;
  assign LOCKSTEP_Master_Out[1250] = \<const0> ;
  assign LOCKSTEP_Master_Out[1251] = \<const0> ;
  assign LOCKSTEP_Master_Out[1252] = \<const0> ;
  assign LOCKSTEP_Master_Out[1253] = \<const0> ;
  assign LOCKSTEP_Master_Out[1254] = \<const0> ;
  assign LOCKSTEP_Master_Out[1255] = \<const0> ;
  assign LOCKSTEP_Master_Out[1256] = \<const0> ;
  assign LOCKSTEP_Master_Out[1257] = \<const0> ;
  assign LOCKSTEP_Master_Out[1258] = \<const0> ;
  assign LOCKSTEP_Master_Out[1259] = \<const0> ;
  assign LOCKSTEP_Master_Out[1260] = \<const0> ;
  assign LOCKSTEP_Master_Out[1261] = \<const0> ;
  assign LOCKSTEP_Master_Out[1262] = \<const0> ;
  assign LOCKSTEP_Master_Out[1263] = \<const0> ;
  assign LOCKSTEP_Master_Out[1264] = \<const0> ;
  assign LOCKSTEP_Master_Out[1265] = \<const0> ;
  assign LOCKSTEP_Master_Out[1266] = \<const0> ;
  assign LOCKSTEP_Master_Out[1267] = \<const0> ;
  assign LOCKSTEP_Master_Out[1268] = \<const0> ;
  assign LOCKSTEP_Master_Out[1269] = \<const0> ;
  assign LOCKSTEP_Master_Out[1270] = \<const0> ;
  assign LOCKSTEP_Master_Out[1271] = \<const0> ;
  assign LOCKSTEP_Master_Out[1272] = \<const0> ;
  assign LOCKSTEP_Master_Out[1273] = \<const0> ;
  assign LOCKSTEP_Master_Out[1274] = \<const0> ;
  assign LOCKSTEP_Master_Out[1275] = \<const0> ;
  assign LOCKSTEP_Master_Out[1276] = \<const0> ;
  assign LOCKSTEP_Master_Out[1277] = \<const0> ;
  assign LOCKSTEP_Master_Out[1278] = \<const0> ;
  assign LOCKSTEP_Master_Out[1279] = \<const0> ;
  assign LOCKSTEP_Master_Out[1280] = \<const0> ;
  assign LOCKSTEP_Master_Out[1281] = \<const0> ;
  assign LOCKSTEP_Master_Out[1282] = \<const0> ;
  assign LOCKSTEP_Master_Out[1283] = \<const0> ;
  assign LOCKSTEP_Master_Out[1284] = \<const0> ;
  assign LOCKSTEP_Master_Out[1285] = \<const0> ;
  assign LOCKSTEP_Master_Out[1286] = \<const0> ;
  assign LOCKSTEP_Master_Out[1287] = \<const0> ;
  assign LOCKSTEP_Master_Out[1288] = \<const0> ;
  assign LOCKSTEP_Master_Out[1289] = \<const0> ;
  assign LOCKSTEP_Master_Out[1290] = \<const0> ;
  assign LOCKSTEP_Master_Out[1291] = \<const0> ;
  assign LOCKSTEP_Master_Out[1292] = \<const0> ;
  assign LOCKSTEP_Master_Out[1293] = \<const0> ;
  assign LOCKSTEP_Master_Out[1294] = \<const0> ;
  assign LOCKSTEP_Master_Out[1295] = \<const0> ;
  assign LOCKSTEP_Master_Out[1296] = \<const0> ;
  assign LOCKSTEP_Master_Out[1297] = \<const0> ;
  assign LOCKSTEP_Master_Out[1298] = \<const0> ;
  assign LOCKSTEP_Master_Out[1299] = \<const0> ;
  assign LOCKSTEP_Master_Out[1300] = \<const0> ;
  assign LOCKSTEP_Master_Out[1301] = \<const0> ;
  assign LOCKSTEP_Master_Out[1302] = \<const0> ;
  assign LOCKSTEP_Master_Out[1303] = \<const0> ;
  assign LOCKSTEP_Master_Out[1304] = \<const0> ;
  assign LOCKSTEP_Master_Out[1305] = \<const0> ;
  assign LOCKSTEP_Master_Out[1306] = \<const0> ;
  assign LOCKSTEP_Master_Out[1307] = \<const0> ;
  assign LOCKSTEP_Master_Out[1308] = \<const0> ;
  assign LOCKSTEP_Master_Out[1309] = \<const0> ;
  assign LOCKSTEP_Master_Out[1310] = \<const0> ;
  assign LOCKSTEP_Master_Out[1311] = \<const0> ;
  assign LOCKSTEP_Master_Out[1312] = \<const0> ;
  assign LOCKSTEP_Master_Out[1313] = \<const0> ;
  assign LOCKSTEP_Master_Out[1314] = \<const0> ;
  assign LOCKSTEP_Master_Out[1315] = \<const0> ;
  assign LOCKSTEP_Master_Out[1316] = \<const0> ;
  assign LOCKSTEP_Master_Out[1317] = \<const0> ;
  assign LOCKSTEP_Master_Out[1318] = \<const0> ;
  assign LOCKSTEP_Master_Out[1319] = \<const0> ;
  assign LOCKSTEP_Master_Out[1320] = \<const0> ;
  assign LOCKSTEP_Master_Out[1321] = \<const0> ;
  assign LOCKSTEP_Master_Out[1322] = \<const0> ;
  assign LOCKSTEP_Master_Out[1323] = \<const0> ;
  assign LOCKSTEP_Master_Out[1324] = \<const0> ;
  assign LOCKSTEP_Master_Out[1325] = \<const0> ;
  assign LOCKSTEP_Master_Out[1326] = \<const0> ;
  assign LOCKSTEP_Master_Out[1327] = \<const0> ;
  assign LOCKSTEP_Master_Out[1328] = \<const0> ;
  assign LOCKSTEP_Master_Out[1329] = \<const0> ;
  assign LOCKSTEP_Master_Out[1330] = \<const0> ;
  assign LOCKSTEP_Master_Out[1331] = \<const0> ;
  assign LOCKSTEP_Master_Out[1332] = \<const0> ;
  assign LOCKSTEP_Master_Out[1333] = \<const0> ;
  assign LOCKSTEP_Master_Out[1334] = \<const0> ;
  assign LOCKSTEP_Master_Out[1335] = \<const0> ;
  assign LOCKSTEP_Master_Out[1336] = \<const0> ;
  assign LOCKSTEP_Master_Out[1337] = \<const0> ;
  assign LOCKSTEP_Master_Out[1338] = \<const0> ;
  assign LOCKSTEP_Master_Out[1339] = \<const0> ;
  assign LOCKSTEP_Master_Out[1340] = \<const0> ;
  assign LOCKSTEP_Master_Out[1341] = \<const0> ;
  assign LOCKSTEP_Master_Out[1342] = \<const0> ;
  assign LOCKSTEP_Master_Out[1343] = \<const0> ;
  assign LOCKSTEP_Master_Out[1344] = \<const0> ;
  assign LOCKSTEP_Master_Out[1345] = \<const0> ;
  assign LOCKSTEP_Master_Out[1346] = \<const0> ;
  assign LOCKSTEP_Master_Out[1347] = \<const0> ;
  assign LOCKSTEP_Master_Out[1348] = \<const0> ;
  assign LOCKSTEP_Master_Out[1349] = \<const0> ;
  assign LOCKSTEP_Master_Out[1350] = \<const0> ;
  assign LOCKSTEP_Master_Out[1351] = \<const0> ;
  assign LOCKSTEP_Master_Out[1352] = \<const0> ;
  assign LOCKSTEP_Master_Out[1353] = \<const0> ;
  assign LOCKSTEP_Master_Out[1354] = \<const0> ;
  assign LOCKSTEP_Master_Out[1355] = \<const0> ;
  assign LOCKSTEP_Master_Out[1356] = \<const0> ;
  assign LOCKSTEP_Master_Out[1357] = \<const0> ;
  assign LOCKSTEP_Master_Out[1358] = \<const0> ;
  assign LOCKSTEP_Master_Out[1359] = \<const0> ;
  assign LOCKSTEP_Master_Out[1360] = \<const0> ;
  assign LOCKSTEP_Master_Out[1361] = \<const0> ;
  assign LOCKSTEP_Master_Out[1362] = \<const0> ;
  assign LOCKSTEP_Master_Out[1363] = \<const0> ;
  assign LOCKSTEP_Master_Out[1364] = \<const0> ;
  assign LOCKSTEP_Master_Out[1365] = \<const0> ;
  assign LOCKSTEP_Master_Out[1366] = \<const0> ;
  assign LOCKSTEP_Master_Out[1367] = \<const0> ;
  assign LOCKSTEP_Master_Out[1368] = \<const0> ;
  assign LOCKSTEP_Master_Out[1369] = \<const0> ;
  assign LOCKSTEP_Master_Out[1370] = \<const0> ;
  assign LOCKSTEP_Master_Out[1371] = \<const0> ;
  assign LOCKSTEP_Master_Out[1372] = \<const0> ;
  assign LOCKSTEP_Master_Out[1373] = \<const0> ;
  assign LOCKSTEP_Master_Out[1374] = \<const0> ;
  assign LOCKSTEP_Master_Out[1375] = \<const0> ;
  assign LOCKSTEP_Master_Out[1376] = \<const0> ;
  assign LOCKSTEP_Master_Out[1377] = \<const0> ;
  assign LOCKSTEP_Master_Out[1378] = \<const0> ;
  assign LOCKSTEP_Master_Out[1379] = \<const0> ;
  assign LOCKSTEP_Master_Out[1380] = \<const0> ;
  assign LOCKSTEP_Master_Out[1381] = \<const0> ;
  assign LOCKSTEP_Master_Out[1382] = \<const0> ;
  assign LOCKSTEP_Master_Out[1383] = \<const0> ;
  assign LOCKSTEP_Master_Out[1384] = \<const0> ;
  assign LOCKSTEP_Master_Out[1385] = \<const0> ;
  assign LOCKSTEP_Master_Out[1386] = \<const0> ;
  assign LOCKSTEP_Master_Out[1387] = \<const0> ;
  assign LOCKSTEP_Master_Out[1388] = \<const0> ;
  assign LOCKSTEP_Master_Out[1389] = \<const0> ;
  assign LOCKSTEP_Master_Out[1390] = \<const0> ;
  assign LOCKSTEP_Master_Out[1391] = \<const0> ;
  assign LOCKSTEP_Master_Out[1392] = \<const0> ;
  assign LOCKSTEP_Master_Out[1393] = \<const0> ;
  assign LOCKSTEP_Master_Out[1394] = \<const0> ;
  assign LOCKSTEP_Master_Out[1395] = \<const0> ;
  assign LOCKSTEP_Master_Out[1396] = \<const0> ;
  assign LOCKSTEP_Master_Out[1397] = \<const0> ;
  assign LOCKSTEP_Master_Out[1398] = \<const0> ;
  assign LOCKSTEP_Master_Out[1399] = \<const0> ;
  assign LOCKSTEP_Master_Out[1400] = \<const0> ;
  assign LOCKSTEP_Master_Out[1401] = \<const0> ;
  assign LOCKSTEP_Master_Out[1402] = \<const0> ;
  assign LOCKSTEP_Master_Out[1403] = \<const0> ;
  assign LOCKSTEP_Master_Out[1404] = \<const0> ;
  assign LOCKSTEP_Master_Out[1405] = \<const0> ;
  assign LOCKSTEP_Master_Out[1406] = \<const0> ;
  assign LOCKSTEP_Master_Out[1407] = \<const0> ;
  assign LOCKSTEP_Master_Out[1408] = \<const0> ;
  assign LOCKSTEP_Master_Out[1409] = \<const0> ;
  assign LOCKSTEP_Master_Out[1410] = \<const0> ;
  assign LOCKSTEP_Master_Out[1411] = \<const0> ;
  assign LOCKSTEP_Master_Out[1412] = \<const0> ;
  assign LOCKSTEP_Master_Out[1413] = \<const0> ;
  assign LOCKSTEP_Master_Out[1414] = \<const0> ;
  assign LOCKSTEP_Master_Out[1415] = \<const0> ;
  assign LOCKSTEP_Master_Out[1416] = \<const0> ;
  assign LOCKSTEP_Master_Out[1417] = \<const0> ;
  assign LOCKSTEP_Master_Out[1418] = \<const0> ;
  assign LOCKSTEP_Master_Out[1419] = \<const0> ;
  assign LOCKSTEP_Master_Out[1420] = \<const0> ;
  assign LOCKSTEP_Master_Out[1421] = \<const0> ;
  assign LOCKSTEP_Master_Out[1422] = \<const0> ;
  assign LOCKSTEP_Master_Out[1423] = \<const0> ;
  assign LOCKSTEP_Master_Out[1424] = \<const0> ;
  assign LOCKSTEP_Master_Out[1425] = \<const0> ;
  assign LOCKSTEP_Master_Out[1426] = \<const0> ;
  assign LOCKSTEP_Master_Out[1427] = \<const0> ;
  assign LOCKSTEP_Master_Out[1428] = \<const0> ;
  assign LOCKSTEP_Master_Out[1429] = \<const0> ;
  assign LOCKSTEP_Master_Out[1430] = \<const0> ;
  assign LOCKSTEP_Master_Out[1431] = \<const0> ;
  assign LOCKSTEP_Master_Out[1432] = \<const0> ;
  assign LOCKSTEP_Master_Out[1433] = \<const0> ;
  assign LOCKSTEP_Master_Out[1434] = \<const0> ;
  assign LOCKSTEP_Master_Out[1435] = \<const0> ;
  assign LOCKSTEP_Master_Out[1436] = \<const0> ;
  assign LOCKSTEP_Master_Out[1437] = \<const0> ;
  assign LOCKSTEP_Master_Out[1438] = \<const0> ;
  assign LOCKSTEP_Master_Out[1439] = \<const0> ;
  assign LOCKSTEP_Master_Out[1440] = \<const0> ;
  assign LOCKSTEP_Master_Out[1441] = \<const0> ;
  assign LOCKSTEP_Master_Out[1442] = \<const0> ;
  assign LOCKSTEP_Master_Out[1443] = \<const0> ;
  assign LOCKSTEP_Master_Out[1444] = \<const0> ;
  assign LOCKSTEP_Master_Out[1445] = \<const0> ;
  assign LOCKSTEP_Master_Out[1446] = \<const0> ;
  assign LOCKSTEP_Master_Out[1447] = \<const0> ;
  assign LOCKSTEP_Master_Out[1448] = \<const0> ;
  assign LOCKSTEP_Master_Out[1449] = \<const0> ;
  assign LOCKSTEP_Master_Out[1450] = \<const0> ;
  assign LOCKSTEP_Master_Out[1451] = \<const0> ;
  assign LOCKSTEP_Master_Out[1452] = \<const0> ;
  assign LOCKSTEP_Master_Out[1453] = \<const0> ;
  assign LOCKSTEP_Master_Out[1454] = \<const0> ;
  assign LOCKSTEP_Master_Out[1455] = \<const0> ;
  assign LOCKSTEP_Master_Out[1456] = \<const0> ;
  assign LOCKSTEP_Master_Out[1457] = \<const0> ;
  assign LOCKSTEP_Master_Out[1458] = \<const0> ;
  assign LOCKSTEP_Master_Out[1459] = \<const0> ;
  assign LOCKSTEP_Master_Out[1460] = \<const0> ;
  assign LOCKSTEP_Master_Out[1461] = \<const0> ;
  assign LOCKSTEP_Master_Out[1462] = \<const0> ;
  assign LOCKSTEP_Master_Out[1463] = \<const0> ;
  assign LOCKSTEP_Master_Out[1464] = \<const0> ;
  assign LOCKSTEP_Master_Out[1465] = \<const0> ;
  assign LOCKSTEP_Master_Out[1466] = \<const0> ;
  assign LOCKSTEP_Master_Out[1467] = \<const0> ;
  assign LOCKSTEP_Master_Out[1468] = \<const0> ;
  assign LOCKSTEP_Master_Out[1469] = \<const0> ;
  assign LOCKSTEP_Master_Out[1470] = \<const0> ;
  assign LOCKSTEP_Master_Out[1471] = \<const0> ;
  assign LOCKSTEP_Master_Out[1472] = \<const0> ;
  assign LOCKSTEP_Master_Out[1473] = \<const0> ;
  assign LOCKSTEP_Master_Out[1474] = \<const0> ;
  assign LOCKSTEP_Master_Out[1475] = \<const0> ;
  assign LOCKSTEP_Master_Out[1476] = \<const0> ;
  assign LOCKSTEP_Master_Out[1477] = \<const0> ;
  assign LOCKSTEP_Master_Out[1478] = \<const0> ;
  assign LOCKSTEP_Master_Out[1479] = \<const0> ;
  assign LOCKSTEP_Master_Out[1480] = \<const0> ;
  assign LOCKSTEP_Master_Out[1481] = \<const0> ;
  assign LOCKSTEP_Master_Out[1482] = \<const0> ;
  assign LOCKSTEP_Master_Out[1483] = \<const0> ;
  assign LOCKSTEP_Master_Out[1484] = \<const0> ;
  assign LOCKSTEP_Master_Out[1485] = \<const0> ;
  assign LOCKSTEP_Master_Out[1486] = \<const0> ;
  assign LOCKSTEP_Master_Out[1487] = \<const0> ;
  assign LOCKSTEP_Master_Out[1488] = \<const0> ;
  assign LOCKSTEP_Master_Out[1489] = \<const0> ;
  assign LOCKSTEP_Master_Out[1490] = \<const0> ;
  assign LOCKSTEP_Master_Out[1491] = \<const0> ;
  assign LOCKSTEP_Master_Out[1492] = \<const0> ;
  assign LOCKSTEP_Master_Out[1493] = \<const0> ;
  assign LOCKSTEP_Master_Out[1494] = \<const0> ;
  assign LOCKSTEP_Master_Out[1495] = \<const0> ;
  assign LOCKSTEP_Master_Out[1496] = \<const0> ;
  assign LOCKSTEP_Master_Out[1497] = \<const0> ;
  assign LOCKSTEP_Master_Out[1498] = \<const0> ;
  assign LOCKSTEP_Master_Out[1499] = \<const0> ;
  assign LOCKSTEP_Master_Out[1500] = \<const0> ;
  assign LOCKSTEP_Master_Out[1501] = \<const0> ;
  assign LOCKSTEP_Master_Out[1502] = \<const0> ;
  assign LOCKSTEP_Master_Out[1503] = \<const0> ;
  assign LOCKSTEP_Master_Out[1504] = \<const0> ;
  assign LOCKSTEP_Master_Out[1505] = \<const0> ;
  assign LOCKSTEP_Master_Out[1506] = \<const0> ;
  assign LOCKSTEP_Master_Out[1507] = \<const0> ;
  assign LOCKSTEP_Master_Out[1508] = \<const0> ;
  assign LOCKSTEP_Master_Out[1509] = \<const0> ;
  assign LOCKSTEP_Master_Out[1510] = \<const0> ;
  assign LOCKSTEP_Master_Out[1511] = \<const0> ;
  assign LOCKSTEP_Master_Out[1512] = \<const0> ;
  assign LOCKSTEP_Master_Out[1513] = \<const0> ;
  assign LOCKSTEP_Master_Out[1514] = \<const0> ;
  assign LOCKSTEP_Master_Out[1515] = \<const0> ;
  assign LOCKSTEP_Master_Out[1516] = \<const0> ;
  assign LOCKSTEP_Master_Out[1517] = \<const0> ;
  assign LOCKSTEP_Master_Out[1518] = \<const0> ;
  assign LOCKSTEP_Master_Out[1519] = \<const0> ;
  assign LOCKSTEP_Master_Out[1520] = \<const0> ;
  assign LOCKSTEP_Master_Out[1521] = \<const0> ;
  assign LOCKSTEP_Master_Out[1522] = \<const0> ;
  assign LOCKSTEP_Master_Out[1523] = \<const0> ;
  assign LOCKSTEP_Master_Out[1524] = \<const0> ;
  assign LOCKSTEP_Master_Out[1525] = \<const0> ;
  assign LOCKSTEP_Master_Out[1526] = \<const0> ;
  assign LOCKSTEP_Master_Out[1527] = \<const0> ;
  assign LOCKSTEP_Master_Out[1528] = \<const0> ;
  assign LOCKSTEP_Master_Out[1529] = \<const0> ;
  assign LOCKSTEP_Master_Out[1530] = \<const0> ;
  assign LOCKSTEP_Master_Out[1531] = \<const0> ;
  assign LOCKSTEP_Master_Out[1532] = \<const0> ;
  assign LOCKSTEP_Master_Out[1533] = \<const0> ;
  assign LOCKSTEP_Master_Out[1534] = \<const0> ;
  assign LOCKSTEP_Master_Out[1535] = \<const0> ;
  assign LOCKSTEP_Master_Out[1536] = \<const0> ;
  assign LOCKSTEP_Master_Out[1537] = \<const0> ;
  assign LOCKSTEP_Master_Out[1538] = \<const0> ;
  assign LOCKSTEP_Master_Out[1539] = \<const0> ;
  assign LOCKSTEP_Master_Out[1540] = \<const0> ;
  assign LOCKSTEP_Master_Out[1541] = \<const0> ;
  assign LOCKSTEP_Master_Out[1542] = \<const0> ;
  assign LOCKSTEP_Master_Out[1543] = \<const0> ;
  assign LOCKSTEP_Master_Out[1544] = \<const0> ;
  assign LOCKSTEP_Master_Out[1545] = \<const0> ;
  assign LOCKSTEP_Master_Out[1546] = \<const0> ;
  assign LOCKSTEP_Master_Out[1547] = \<const0> ;
  assign LOCKSTEP_Master_Out[1548] = \<const0> ;
  assign LOCKSTEP_Master_Out[1549] = \<const0> ;
  assign LOCKSTEP_Master_Out[1550] = \<const0> ;
  assign LOCKSTEP_Master_Out[1551] = \<const0> ;
  assign LOCKSTEP_Master_Out[1552] = \<const0> ;
  assign LOCKSTEP_Master_Out[1553] = \<const0> ;
  assign LOCKSTEP_Master_Out[1554] = \<const0> ;
  assign LOCKSTEP_Master_Out[1555] = \<const0> ;
  assign LOCKSTEP_Master_Out[1556] = \<const0> ;
  assign LOCKSTEP_Master_Out[1557] = \<const0> ;
  assign LOCKSTEP_Master_Out[1558] = \<const0> ;
  assign LOCKSTEP_Master_Out[1559] = \<const0> ;
  assign LOCKSTEP_Master_Out[1560] = \<const0> ;
  assign LOCKSTEP_Master_Out[1561] = \<const0> ;
  assign LOCKSTEP_Master_Out[1562] = \<const0> ;
  assign LOCKSTEP_Master_Out[1563] = \<const0> ;
  assign LOCKSTEP_Master_Out[1564] = \<const0> ;
  assign LOCKSTEP_Master_Out[1565] = \<const0> ;
  assign LOCKSTEP_Master_Out[1566] = \<const0> ;
  assign LOCKSTEP_Master_Out[1567] = \<const0> ;
  assign LOCKSTEP_Master_Out[1568] = \<const0> ;
  assign LOCKSTEP_Master_Out[1569] = \<const0> ;
  assign LOCKSTEP_Master_Out[1570] = \<const0> ;
  assign LOCKSTEP_Master_Out[1571] = \<const0> ;
  assign LOCKSTEP_Master_Out[1572] = \<const0> ;
  assign LOCKSTEP_Master_Out[1573] = \<const0> ;
  assign LOCKSTEP_Master_Out[1574] = \<const0> ;
  assign LOCKSTEP_Master_Out[1575] = \<const0> ;
  assign LOCKSTEP_Master_Out[1576] = \<const0> ;
  assign LOCKSTEP_Master_Out[1577] = \<const0> ;
  assign LOCKSTEP_Master_Out[1578] = \<const0> ;
  assign LOCKSTEP_Master_Out[1579] = \<const0> ;
  assign LOCKSTEP_Master_Out[1580] = \<const0> ;
  assign LOCKSTEP_Master_Out[1581] = \<const0> ;
  assign LOCKSTEP_Master_Out[1582] = \<const0> ;
  assign LOCKSTEP_Master_Out[1583] = \<const0> ;
  assign LOCKSTEP_Master_Out[1584] = \<const0> ;
  assign LOCKSTEP_Master_Out[1585] = \<const0> ;
  assign LOCKSTEP_Master_Out[1586] = \<const0> ;
  assign LOCKSTEP_Master_Out[1587] = \<const0> ;
  assign LOCKSTEP_Master_Out[1588] = \<const0> ;
  assign LOCKSTEP_Master_Out[1589] = \<const0> ;
  assign LOCKSTEP_Master_Out[1590] = \<const0> ;
  assign LOCKSTEP_Master_Out[1591] = \<const0> ;
  assign LOCKSTEP_Master_Out[1592] = \<const0> ;
  assign LOCKSTEP_Master_Out[1593] = \<const0> ;
  assign LOCKSTEP_Master_Out[1594] = \<const0> ;
  assign LOCKSTEP_Master_Out[1595] = \<const0> ;
  assign LOCKSTEP_Master_Out[1596] = \<const0> ;
  assign LOCKSTEP_Master_Out[1597] = \<const0> ;
  assign LOCKSTEP_Master_Out[1598] = \<const0> ;
  assign LOCKSTEP_Master_Out[1599] = \<const0> ;
  assign LOCKSTEP_Master_Out[1600] = \<const0> ;
  assign LOCKSTEP_Master_Out[1601] = \<const0> ;
  assign LOCKSTEP_Master_Out[1602] = \<const0> ;
  assign LOCKSTEP_Master_Out[1603] = \<const0> ;
  assign LOCKSTEP_Master_Out[1604] = \<const0> ;
  assign LOCKSTEP_Master_Out[1605] = \<const0> ;
  assign LOCKSTEP_Master_Out[1606] = \<const0> ;
  assign LOCKSTEP_Master_Out[1607] = \<const0> ;
  assign LOCKSTEP_Master_Out[1608] = \<const0> ;
  assign LOCKSTEP_Master_Out[1609] = \<const0> ;
  assign LOCKSTEP_Master_Out[1610] = \<const0> ;
  assign LOCKSTEP_Master_Out[1611] = \<const0> ;
  assign LOCKSTEP_Master_Out[1612] = \<const0> ;
  assign LOCKSTEP_Master_Out[1613] = \<const0> ;
  assign LOCKSTEP_Master_Out[1614] = \<const0> ;
  assign LOCKSTEP_Master_Out[1615] = \<const0> ;
  assign LOCKSTEP_Master_Out[1616] = \<const0> ;
  assign LOCKSTEP_Master_Out[1617] = \<const0> ;
  assign LOCKSTEP_Master_Out[1618] = \<const0> ;
  assign LOCKSTEP_Master_Out[1619] = \<const0> ;
  assign LOCKSTEP_Master_Out[1620] = \<const0> ;
  assign LOCKSTEP_Master_Out[1621] = \<const0> ;
  assign LOCKSTEP_Master_Out[1622] = \<const0> ;
  assign LOCKSTEP_Master_Out[1623] = \<const0> ;
  assign LOCKSTEP_Master_Out[1624] = \<const0> ;
  assign LOCKSTEP_Master_Out[1625] = \<const0> ;
  assign LOCKSTEP_Master_Out[1626] = \<const0> ;
  assign LOCKSTEP_Master_Out[1627] = \<const0> ;
  assign LOCKSTEP_Master_Out[1628] = \<const0> ;
  assign LOCKSTEP_Master_Out[1629] = \<const0> ;
  assign LOCKSTEP_Master_Out[1630] = \<const0> ;
  assign LOCKSTEP_Master_Out[1631] = \<const0> ;
  assign LOCKSTEP_Master_Out[1632] = \<const0> ;
  assign LOCKSTEP_Master_Out[1633] = \<const0> ;
  assign LOCKSTEP_Master_Out[1634] = \<const0> ;
  assign LOCKSTEP_Master_Out[1635] = \<const0> ;
  assign LOCKSTEP_Master_Out[1636] = \<const0> ;
  assign LOCKSTEP_Master_Out[1637] = \<const0> ;
  assign LOCKSTEP_Master_Out[1638] = \<const0> ;
  assign LOCKSTEP_Master_Out[1639] = \<const0> ;
  assign LOCKSTEP_Master_Out[1640] = \<const0> ;
  assign LOCKSTEP_Master_Out[1641] = \<const0> ;
  assign LOCKSTEP_Master_Out[1642] = \<const0> ;
  assign LOCKSTEP_Master_Out[1643] = \<const0> ;
  assign LOCKSTEP_Master_Out[1644] = \<const0> ;
  assign LOCKSTEP_Master_Out[1645] = \<const0> ;
  assign LOCKSTEP_Master_Out[1646] = \<const0> ;
  assign LOCKSTEP_Master_Out[1647] = \<const0> ;
  assign LOCKSTEP_Master_Out[1648] = \<const0> ;
  assign LOCKSTEP_Master_Out[1649] = \<const0> ;
  assign LOCKSTEP_Master_Out[1650] = \<const0> ;
  assign LOCKSTEP_Master_Out[1651] = \<const0> ;
  assign LOCKSTEP_Master_Out[1652] = \<const0> ;
  assign LOCKSTEP_Master_Out[1653] = \<const0> ;
  assign LOCKSTEP_Master_Out[1654] = \<const0> ;
  assign LOCKSTEP_Master_Out[1655] = \<const0> ;
  assign LOCKSTEP_Master_Out[1656] = \<const0> ;
  assign LOCKSTEP_Master_Out[1657] = \<const0> ;
  assign LOCKSTEP_Master_Out[1658] = \<const0> ;
  assign LOCKSTEP_Master_Out[1659] = \<const0> ;
  assign LOCKSTEP_Master_Out[1660] = \<const0> ;
  assign LOCKSTEP_Master_Out[1661] = \<const0> ;
  assign LOCKSTEP_Master_Out[1662] = \<const0> ;
  assign LOCKSTEP_Master_Out[1663] = \<const0> ;
  assign LOCKSTEP_Master_Out[1664] = \<const0> ;
  assign LOCKSTEP_Master_Out[1665] = \<const0> ;
  assign LOCKSTEP_Master_Out[1666] = \<const0> ;
  assign LOCKSTEP_Master_Out[1667] = \<const0> ;
  assign LOCKSTEP_Master_Out[1668] = \<const0> ;
  assign LOCKSTEP_Master_Out[1669] = \<const0> ;
  assign LOCKSTEP_Master_Out[1670] = \<const0> ;
  assign LOCKSTEP_Master_Out[1671] = \<const0> ;
  assign LOCKSTEP_Master_Out[1672] = \<const0> ;
  assign LOCKSTEP_Master_Out[1673] = \<const0> ;
  assign LOCKSTEP_Master_Out[1674] = \<const0> ;
  assign LOCKSTEP_Master_Out[1675] = \<const0> ;
  assign LOCKSTEP_Master_Out[1676] = \<const0> ;
  assign LOCKSTEP_Master_Out[1677] = \<const0> ;
  assign LOCKSTEP_Master_Out[1678] = \<const0> ;
  assign LOCKSTEP_Master_Out[1679] = \<const0> ;
  assign LOCKSTEP_Master_Out[1680] = \<const0> ;
  assign LOCKSTEP_Master_Out[1681] = \<const0> ;
  assign LOCKSTEP_Master_Out[1682] = \<const0> ;
  assign LOCKSTEP_Master_Out[1683] = \<const0> ;
  assign LOCKSTEP_Master_Out[1684] = \<const0> ;
  assign LOCKSTEP_Master_Out[1685] = \<const0> ;
  assign LOCKSTEP_Master_Out[1686] = \<const0> ;
  assign LOCKSTEP_Master_Out[1687] = \<const0> ;
  assign LOCKSTEP_Master_Out[1688] = \<const0> ;
  assign LOCKSTEP_Master_Out[1689] = \<const0> ;
  assign LOCKSTEP_Master_Out[1690] = \<const0> ;
  assign LOCKSTEP_Master_Out[1691] = \<const0> ;
  assign LOCKSTEP_Master_Out[1692] = \<const0> ;
  assign LOCKSTEP_Master_Out[1693] = \<const0> ;
  assign LOCKSTEP_Master_Out[1694] = \<const0> ;
  assign LOCKSTEP_Master_Out[1695] = \<const0> ;
  assign LOCKSTEP_Master_Out[1696] = \<const0> ;
  assign LOCKSTEP_Master_Out[1697] = \<const0> ;
  assign LOCKSTEP_Master_Out[1698] = \<const0> ;
  assign LOCKSTEP_Master_Out[1699] = \<const0> ;
  assign LOCKSTEP_Master_Out[1700] = \<const0> ;
  assign LOCKSTEP_Master_Out[1701] = \<const0> ;
  assign LOCKSTEP_Master_Out[1702] = \<const0> ;
  assign LOCKSTEP_Master_Out[1703] = \<const0> ;
  assign LOCKSTEP_Master_Out[1704] = \<const0> ;
  assign LOCKSTEP_Master_Out[1705] = \<const0> ;
  assign LOCKSTEP_Master_Out[1706] = \<const0> ;
  assign LOCKSTEP_Master_Out[1707] = \<const0> ;
  assign LOCKSTEP_Master_Out[1708] = \<const0> ;
  assign LOCKSTEP_Master_Out[1709] = \<const0> ;
  assign LOCKSTEP_Master_Out[1710] = \<const0> ;
  assign LOCKSTEP_Master_Out[1711] = \<const0> ;
  assign LOCKSTEP_Master_Out[1712] = \<const0> ;
  assign LOCKSTEP_Master_Out[1713] = \<const0> ;
  assign LOCKSTEP_Master_Out[1714] = \<const0> ;
  assign LOCKSTEP_Master_Out[1715] = \<const0> ;
  assign LOCKSTEP_Master_Out[1716] = \<const0> ;
  assign LOCKSTEP_Master_Out[1717] = \<const0> ;
  assign LOCKSTEP_Master_Out[1718] = \<const0> ;
  assign LOCKSTEP_Master_Out[1719] = \<const0> ;
  assign LOCKSTEP_Master_Out[1720] = \<const0> ;
  assign LOCKSTEP_Master_Out[1721] = \<const0> ;
  assign LOCKSTEP_Master_Out[1722] = \<const0> ;
  assign LOCKSTEP_Master_Out[1723] = \<const0> ;
  assign LOCKSTEP_Master_Out[1724] = \<const0> ;
  assign LOCKSTEP_Master_Out[1725] = \<const0> ;
  assign LOCKSTEP_Master_Out[1726] = \<const0> ;
  assign LOCKSTEP_Master_Out[1727] = \<const0> ;
  assign LOCKSTEP_Master_Out[1728] = \<const0> ;
  assign LOCKSTEP_Master_Out[1729] = \<const0> ;
  assign LOCKSTEP_Master_Out[1730] = \<const0> ;
  assign LOCKSTEP_Master_Out[1731] = \<const0> ;
  assign LOCKSTEP_Master_Out[1732] = \<const0> ;
  assign LOCKSTEP_Master_Out[1733] = \<const0> ;
  assign LOCKSTEP_Master_Out[1734] = \<const0> ;
  assign LOCKSTEP_Master_Out[1735] = \<const0> ;
  assign LOCKSTEP_Master_Out[1736] = \<const0> ;
  assign LOCKSTEP_Master_Out[1737] = \<const0> ;
  assign LOCKSTEP_Master_Out[1738] = \<const0> ;
  assign LOCKSTEP_Master_Out[1739] = \<const0> ;
  assign LOCKSTEP_Master_Out[1740] = \<const0> ;
  assign LOCKSTEP_Master_Out[1741] = \<const0> ;
  assign LOCKSTEP_Master_Out[1742] = \<const0> ;
  assign LOCKSTEP_Master_Out[1743] = \<const0> ;
  assign LOCKSTEP_Master_Out[1744] = \<const0> ;
  assign LOCKSTEP_Master_Out[1745] = \<const0> ;
  assign LOCKSTEP_Master_Out[1746] = \<const0> ;
  assign LOCKSTEP_Master_Out[1747] = \<const0> ;
  assign LOCKSTEP_Master_Out[1748] = \<const0> ;
  assign LOCKSTEP_Master_Out[1749] = \<const0> ;
  assign LOCKSTEP_Master_Out[1750] = \<const0> ;
  assign LOCKSTEP_Master_Out[1751] = \<const0> ;
  assign LOCKSTEP_Master_Out[1752] = \<const0> ;
  assign LOCKSTEP_Master_Out[1753] = \<const0> ;
  assign LOCKSTEP_Master_Out[1754] = \<const0> ;
  assign LOCKSTEP_Master_Out[1755] = \<const0> ;
  assign LOCKSTEP_Master_Out[1756] = \<const0> ;
  assign LOCKSTEP_Master_Out[1757] = \<const0> ;
  assign LOCKSTEP_Master_Out[1758] = \<const0> ;
  assign LOCKSTEP_Master_Out[1759] = \<const0> ;
  assign LOCKSTEP_Master_Out[1760] = \<const0> ;
  assign LOCKSTEP_Master_Out[1761] = \<const0> ;
  assign LOCKSTEP_Master_Out[1762] = \<const0> ;
  assign LOCKSTEP_Master_Out[1763] = \<const0> ;
  assign LOCKSTEP_Master_Out[1764] = \<const0> ;
  assign LOCKSTEP_Master_Out[1765] = \<const0> ;
  assign LOCKSTEP_Master_Out[1766] = \<const0> ;
  assign LOCKSTEP_Master_Out[1767] = \<const0> ;
  assign LOCKSTEP_Master_Out[1768] = \<const0> ;
  assign LOCKSTEP_Master_Out[1769] = \<const0> ;
  assign LOCKSTEP_Master_Out[1770] = \<const0> ;
  assign LOCKSTEP_Master_Out[1771] = \<const0> ;
  assign LOCKSTEP_Master_Out[1772] = \<const0> ;
  assign LOCKSTEP_Master_Out[1773] = \<const0> ;
  assign LOCKSTEP_Master_Out[1774] = \<const0> ;
  assign LOCKSTEP_Master_Out[1775] = \<const0> ;
  assign LOCKSTEP_Master_Out[1776] = \<const0> ;
  assign LOCKSTEP_Master_Out[1777] = \<const0> ;
  assign LOCKSTEP_Master_Out[1778] = \<const0> ;
  assign LOCKSTEP_Master_Out[1779] = \<const0> ;
  assign LOCKSTEP_Master_Out[1780] = \<const0> ;
  assign LOCKSTEP_Master_Out[1781] = \<const0> ;
  assign LOCKSTEP_Master_Out[1782] = \<const0> ;
  assign LOCKSTEP_Master_Out[1783] = \<const0> ;
  assign LOCKSTEP_Master_Out[1784] = \<const0> ;
  assign LOCKSTEP_Master_Out[1785] = \<const0> ;
  assign LOCKSTEP_Master_Out[1786] = \<const0> ;
  assign LOCKSTEP_Master_Out[1787] = \<const0> ;
  assign LOCKSTEP_Master_Out[1788] = \<const0> ;
  assign LOCKSTEP_Master_Out[1789] = \<const0> ;
  assign LOCKSTEP_Master_Out[1790] = \<const0> ;
  assign LOCKSTEP_Master_Out[1791] = \<const0> ;
  assign LOCKSTEP_Master_Out[1792] = \<const0> ;
  assign LOCKSTEP_Master_Out[1793] = \<const0> ;
  assign LOCKSTEP_Master_Out[1794] = \<const0> ;
  assign LOCKSTEP_Master_Out[1795] = \<const0> ;
  assign LOCKSTEP_Master_Out[1796] = \<const0> ;
  assign LOCKSTEP_Master_Out[1797] = \<const0> ;
  assign LOCKSTEP_Master_Out[1798] = \<const0> ;
  assign LOCKSTEP_Master_Out[1799] = \<const0> ;
  assign LOCKSTEP_Master_Out[1800] = \<const0> ;
  assign LOCKSTEP_Master_Out[1801] = \<const0> ;
  assign LOCKSTEP_Master_Out[1802] = \<const0> ;
  assign LOCKSTEP_Master_Out[1803] = \<const0> ;
  assign LOCKSTEP_Master_Out[1804] = \<const0> ;
  assign LOCKSTEP_Master_Out[1805] = \<const0> ;
  assign LOCKSTEP_Master_Out[1806] = \<const0> ;
  assign LOCKSTEP_Master_Out[1807] = \<const0> ;
  assign LOCKSTEP_Master_Out[1808] = \<const0> ;
  assign LOCKSTEP_Master_Out[1809] = \<const0> ;
  assign LOCKSTEP_Master_Out[1810] = \<const0> ;
  assign LOCKSTEP_Master_Out[1811] = \<const0> ;
  assign LOCKSTEP_Master_Out[1812] = \<const0> ;
  assign LOCKSTEP_Master_Out[1813] = \<const0> ;
  assign LOCKSTEP_Master_Out[1814] = \<const0> ;
  assign LOCKSTEP_Master_Out[1815] = \<const0> ;
  assign LOCKSTEP_Master_Out[1816] = \<const0> ;
  assign LOCKSTEP_Master_Out[1817] = \<const0> ;
  assign LOCKSTEP_Master_Out[1818] = \<const0> ;
  assign LOCKSTEP_Master_Out[1819] = \<const0> ;
  assign LOCKSTEP_Master_Out[1820] = \<const0> ;
  assign LOCKSTEP_Master_Out[1821] = \<const0> ;
  assign LOCKSTEP_Master_Out[1822] = \<const0> ;
  assign LOCKSTEP_Master_Out[1823] = \<const0> ;
  assign LOCKSTEP_Master_Out[1824] = \<const0> ;
  assign LOCKSTEP_Master_Out[1825] = \<const0> ;
  assign LOCKSTEP_Master_Out[1826] = \<const0> ;
  assign LOCKSTEP_Master_Out[1827] = \<const0> ;
  assign LOCKSTEP_Master_Out[1828] = \<const0> ;
  assign LOCKSTEP_Master_Out[1829] = \<const0> ;
  assign LOCKSTEP_Master_Out[1830] = \<const0> ;
  assign LOCKSTEP_Master_Out[1831] = \<const0> ;
  assign LOCKSTEP_Master_Out[1832] = \<const0> ;
  assign LOCKSTEP_Master_Out[1833] = \<const0> ;
  assign LOCKSTEP_Master_Out[1834] = \<const0> ;
  assign LOCKSTEP_Master_Out[1835] = \<const0> ;
  assign LOCKSTEP_Master_Out[1836] = \<const0> ;
  assign LOCKSTEP_Master_Out[1837] = \<const0> ;
  assign LOCKSTEP_Master_Out[1838] = \<const0> ;
  assign LOCKSTEP_Master_Out[1839] = \<const0> ;
  assign LOCKSTEP_Master_Out[1840] = \<const0> ;
  assign LOCKSTEP_Master_Out[1841] = \<const0> ;
  assign LOCKSTEP_Master_Out[1842] = \<const0> ;
  assign LOCKSTEP_Master_Out[1843] = \<const0> ;
  assign LOCKSTEP_Master_Out[1844] = \<const0> ;
  assign LOCKSTEP_Master_Out[1845] = \<const0> ;
  assign LOCKSTEP_Master_Out[1846] = \<const0> ;
  assign LOCKSTEP_Master_Out[1847] = \<const0> ;
  assign LOCKSTEP_Master_Out[1848] = \<const0> ;
  assign LOCKSTEP_Master_Out[1849] = \<const0> ;
  assign LOCKSTEP_Master_Out[1850] = \<const0> ;
  assign LOCKSTEP_Master_Out[1851] = \<const0> ;
  assign LOCKSTEP_Master_Out[1852] = \<const0> ;
  assign LOCKSTEP_Master_Out[1853] = \<const0> ;
  assign LOCKSTEP_Master_Out[1854] = \<const0> ;
  assign LOCKSTEP_Master_Out[1855] = \<const0> ;
  assign LOCKSTEP_Master_Out[1856] = \<const0> ;
  assign LOCKSTEP_Master_Out[1857] = \<const0> ;
  assign LOCKSTEP_Master_Out[1858] = \<const0> ;
  assign LOCKSTEP_Master_Out[1859] = \<const0> ;
  assign LOCKSTEP_Master_Out[1860] = \<const0> ;
  assign LOCKSTEP_Master_Out[1861] = \<const0> ;
  assign LOCKSTEP_Master_Out[1862] = \<const0> ;
  assign LOCKSTEP_Master_Out[1863] = \<const0> ;
  assign LOCKSTEP_Master_Out[1864] = \<const0> ;
  assign LOCKSTEP_Master_Out[1865] = \<const0> ;
  assign LOCKSTEP_Master_Out[1866] = \<const0> ;
  assign LOCKSTEP_Master_Out[1867] = \<const0> ;
  assign LOCKSTEP_Master_Out[1868] = \<const0> ;
  assign LOCKSTEP_Master_Out[1869] = \<const0> ;
  assign LOCKSTEP_Master_Out[1870] = \<const0> ;
  assign LOCKSTEP_Master_Out[1871] = \<const0> ;
  assign LOCKSTEP_Master_Out[1872] = \<const0> ;
  assign LOCKSTEP_Master_Out[1873] = \<const0> ;
  assign LOCKSTEP_Master_Out[1874] = \<const0> ;
  assign LOCKSTEP_Master_Out[1875] = \<const0> ;
  assign LOCKSTEP_Master_Out[1876] = \<const0> ;
  assign LOCKSTEP_Master_Out[1877] = \<const0> ;
  assign LOCKSTEP_Master_Out[1878] = \<const0> ;
  assign LOCKSTEP_Master_Out[1879] = \<const0> ;
  assign LOCKSTEP_Master_Out[1880] = \<const0> ;
  assign LOCKSTEP_Master_Out[1881] = \<const0> ;
  assign LOCKSTEP_Master_Out[1882] = \<const0> ;
  assign LOCKSTEP_Master_Out[1883] = \<const0> ;
  assign LOCKSTEP_Master_Out[1884] = \<const0> ;
  assign LOCKSTEP_Master_Out[1885] = \<const0> ;
  assign LOCKSTEP_Master_Out[1886] = \<const0> ;
  assign LOCKSTEP_Master_Out[1887] = \<const0> ;
  assign LOCKSTEP_Master_Out[1888] = \<const0> ;
  assign LOCKSTEP_Master_Out[1889] = \<const0> ;
  assign LOCKSTEP_Master_Out[1890] = \<const0> ;
  assign LOCKSTEP_Master_Out[1891] = \<const0> ;
  assign LOCKSTEP_Master_Out[1892] = \<const0> ;
  assign LOCKSTEP_Master_Out[1893] = \<const0> ;
  assign LOCKSTEP_Master_Out[1894] = \<const0> ;
  assign LOCKSTEP_Master_Out[1895] = \<const0> ;
  assign LOCKSTEP_Master_Out[1896] = \<const0> ;
  assign LOCKSTEP_Master_Out[1897] = \<const0> ;
  assign LOCKSTEP_Master_Out[1898] = \<const0> ;
  assign LOCKSTEP_Master_Out[1899] = \<const0> ;
  assign LOCKSTEP_Master_Out[1900] = \<const0> ;
  assign LOCKSTEP_Master_Out[1901] = \<const0> ;
  assign LOCKSTEP_Master_Out[1902] = \<const0> ;
  assign LOCKSTEP_Master_Out[1903] = \<const0> ;
  assign LOCKSTEP_Master_Out[1904] = \<const0> ;
  assign LOCKSTEP_Master_Out[1905] = \<const0> ;
  assign LOCKSTEP_Master_Out[1906] = \<const0> ;
  assign LOCKSTEP_Master_Out[1907] = \<const0> ;
  assign LOCKSTEP_Master_Out[1908] = \<const0> ;
  assign LOCKSTEP_Master_Out[1909] = \<const0> ;
  assign LOCKSTEP_Master_Out[1910] = \<const0> ;
  assign LOCKSTEP_Master_Out[1911] = \<const0> ;
  assign LOCKSTEP_Master_Out[1912] = \<const0> ;
  assign LOCKSTEP_Master_Out[1913] = \<const0> ;
  assign LOCKSTEP_Master_Out[1914] = \<const0> ;
  assign LOCKSTEP_Master_Out[1915] = \<const0> ;
  assign LOCKSTEP_Master_Out[1916] = \<const0> ;
  assign LOCKSTEP_Master_Out[1917] = \<const0> ;
  assign LOCKSTEP_Master_Out[1918] = \<const0> ;
  assign LOCKSTEP_Master_Out[1919] = \<const0> ;
  assign LOCKSTEP_Master_Out[1920] = \<const0> ;
  assign LOCKSTEP_Master_Out[1921] = \<const0> ;
  assign LOCKSTEP_Master_Out[1922] = \<const0> ;
  assign LOCKSTEP_Master_Out[1923] = \<const0> ;
  assign LOCKSTEP_Master_Out[1924] = \<const0> ;
  assign LOCKSTEP_Master_Out[1925] = \<const0> ;
  assign LOCKSTEP_Master_Out[1926] = \<const0> ;
  assign LOCKSTEP_Master_Out[1927] = \<const0> ;
  assign LOCKSTEP_Master_Out[1928] = \<const0> ;
  assign LOCKSTEP_Master_Out[1929] = \<const0> ;
  assign LOCKSTEP_Master_Out[1930] = \<const0> ;
  assign LOCKSTEP_Master_Out[1931] = \<const0> ;
  assign LOCKSTEP_Master_Out[1932] = \<const0> ;
  assign LOCKSTEP_Master_Out[1933] = \<const0> ;
  assign LOCKSTEP_Master_Out[1934] = \<const0> ;
  assign LOCKSTEP_Master_Out[1935] = \<const0> ;
  assign LOCKSTEP_Master_Out[1936] = \<const0> ;
  assign LOCKSTEP_Master_Out[1937] = \<const0> ;
  assign LOCKSTEP_Master_Out[1938] = \<const0> ;
  assign LOCKSTEP_Master_Out[1939] = \<const0> ;
  assign LOCKSTEP_Master_Out[1940] = \<const0> ;
  assign LOCKSTEP_Master_Out[1941] = \<const0> ;
  assign LOCKSTEP_Master_Out[1942] = \<const0> ;
  assign LOCKSTEP_Master_Out[1943] = \<const0> ;
  assign LOCKSTEP_Master_Out[1944] = \<const0> ;
  assign LOCKSTEP_Master_Out[1945] = \<const0> ;
  assign LOCKSTEP_Master_Out[1946] = \<const0> ;
  assign LOCKSTEP_Master_Out[1947] = \<const0> ;
  assign LOCKSTEP_Master_Out[1948] = \<const0> ;
  assign LOCKSTEP_Master_Out[1949] = \<const0> ;
  assign LOCKSTEP_Master_Out[1950] = \<const0> ;
  assign LOCKSTEP_Master_Out[1951] = \<const0> ;
  assign LOCKSTEP_Master_Out[1952] = \<const0> ;
  assign LOCKSTEP_Master_Out[1953] = \<const0> ;
  assign LOCKSTEP_Master_Out[1954] = \<const0> ;
  assign LOCKSTEP_Master_Out[1955] = \<const0> ;
  assign LOCKSTEP_Master_Out[1956] = \<const0> ;
  assign LOCKSTEP_Master_Out[1957] = \<const0> ;
  assign LOCKSTEP_Master_Out[1958] = \<const0> ;
  assign LOCKSTEP_Master_Out[1959] = \<const0> ;
  assign LOCKSTEP_Master_Out[1960] = \<const0> ;
  assign LOCKSTEP_Master_Out[1961] = \<const0> ;
  assign LOCKSTEP_Master_Out[1962] = \<const0> ;
  assign LOCKSTEP_Master_Out[1963] = \<const0> ;
  assign LOCKSTEP_Master_Out[1964] = \<const0> ;
  assign LOCKSTEP_Master_Out[1965] = \<const0> ;
  assign LOCKSTEP_Master_Out[1966] = \<const0> ;
  assign LOCKSTEP_Master_Out[1967] = \<const0> ;
  assign LOCKSTEP_Master_Out[1968] = \<const0> ;
  assign LOCKSTEP_Master_Out[1969] = \<const0> ;
  assign LOCKSTEP_Master_Out[1970] = \<const0> ;
  assign LOCKSTEP_Master_Out[1971] = \<const0> ;
  assign LOCKSTEP_Master_Out[1972] = \<const0> ;
  assign LOCKSTEP_Master_Out[1973] = \<const0> ;
  assign LOCKSTEP_Master_Out[1974] = \<const0> ;
  assign LOCKSTEP_Master_Out[1975] = \<const0> ;
  assign LOCKSTEP_Master_Out[1976] = \<const0> ;
  assign LOCKSTEP_Master_Out[1977] = \<const0> ;
  assign LOCKSTEP_Master_Out[1978] = \<const0> ;
  assign LOCKSTEP_Master_Out[1979] = \<const0> ;
  assign LOCKSTEP_Master_Out[1980] = \<const0> ;
  assign LOCKSTEP_Master_Out[1981] = \<const0> ;
  assign LOCKSTEP_Master_Out[1982] = \<const0> ;
  assign LOCKSTEP_Master_Out[1983] = \<const0> ;
  assign LOCKSTEP_Master_Out[1984] = \<const0> ;
  assign LOCKSTEP_Master_Out[1985] = \<const0> ;
  assign LOCKSTEP_Master_Out[1986] = \<const0> ;
  assign LOCKSTEP_Master_Out[1987] = \<const0> ;
  assign LOCKSTEP_Master_Out[1988] = \<const0> ;
  assign LOCKSTEP_Master_Out[1989] = \<const0> ;
  assign LOCKSTEP_Master_Out[1990] = \<const0> ;
  assign LOCKSTEP_Master_Out[1991] = \<const0> ;
  assign LOCKSTEP_Master_Out[1992] = \<const0> ;
  assign LOCKSTEP_Master_Out[1993] = \<const0> ;
  assign LOCKSTEP_Master_Out[1994] = \<const0> ;
  assign LOCKSTEP_Master_Out[1995] = \<const0> ;
  assign LOCKSTEP_Master_Out[1996] = \<const0> ;
  assign LOCKSTEP_Master_Out[1997] = \<const0> ;
  assign LOCKSTEP_Master_Out[1998] = \<const0> ;
  assign LOCKSTEP_Master_Out[1999] = \<const0> ;
  assign LOCKSTEP_Master_Out[2000] = \<const0> ;
  assign LOCKSTEP_Master_Out[2001] = \<const0> ;
  assign LOCKSTEP_Master_Out[2002] = \<const0> ;
  assign LOCKSTEP_Master_Out[2003] = \<const0> ;
  assign LOCKSTEP_Master_Out[2004] = \<const0> ;
  assign LOCKSTEP_Master_Out[2005] = \<const0> ;
  assign LOCKSTEP_Master_Out[2006] = \<const0> ;
  assign LOCKSTEP_Master_Out[2007] = \<const0> ;
  assign LOCKSTEP_Master_Out[2008] = \<const0> ;
  assign LOCKSTEP_Master_Out[2009] = \<const0> ;
  assign LOCKSTEP_Master_Out[2010] = \<const0> ;
  assign LOCKSTEP_Master_Out[2011] = \<const0> ;
  assign LOCKSTEP_Master_Out[2012] = \<const0> ;
  assign LOCKSTEP_Master_Out[2013] = \<const0> ;
  assign LOCKSTEP_Master_Out[2014] = \<const0> ;
  assign LOCKSTEP_Master_Out[2015] = \<const0> ;
  assign LOCKSTEP_Master_Out[2016] = \<const0> ;
  assign LOCKSTEP_Master_Out[2017] = \<const0> ;
  assign LOCKSTEP_Master_Out[2018] = \<const0> ;
  assign LOCKSTEP_Master_Out[2019] = \<const0> ;
  assign LOCKSTEP_Master_Out[2020] = \<const0> ;
  assign LOCKSTEP_Master_Out[2021] = \<const0> ;
  assign LOCKSTEP_Master_Out[2022] = \<const0> ;
  assign LOCKSTEP_Master_Out[2023] = \<const0> ;
  assign LOCKSTEP_Master_Out[2024] = \<const0> ;
  assign LOCKSTEP_Master_Out[2025] = \<const0> ;
  assign LOCKSTEP_Master_Out[2026] = \<const0> ;
  assign LOCKSTEP_Master_Out[2027] = \<const0> ;
  assign LOCKSTEP_Master_Out[2028] = \<const0> ;
  assign LOCKSTEP_Master_Out[2029] = \<const0> ;
  assign LOCKSTEP_Master_Out[2030] = \<const0> ;
  assign LOCKSTEP_Master_Out[2031] = \<const0> ;
  assign LOCKSTEP_Master_Out[2032] = \<const0> ;
  assign LOCKSTEP_Master_Out[2033] = \<const0> ;
  assign LOCKSTEP_Master_Out[2034] = \<const0> ;
  assign LOCKSTEP_Master_Out[2035] = \<const0> ;
  assign LOCKSTEP_Master_Out[2036] = \<const0> ;
  assign LOCKSTEP_Master_Out[2037] = \<const0> ;
  assign LOCKSTEP_Master_Out[2038] = \<const0> ;
  assign LOCKSTEP_Master_Out[2039] = \<const0> ;
  assign LOCKSTEP_Master_Out[2040] = \<const0> ;
  assign LOCKSTEP_Master_Out[2041] = \<const0> ;
  assign LOCKSTEP_Master_Out[2042] = \<const0> ;
  assign LOCKSTEP_Master_Out[2043] = \<const0> ;
  assign LOCKSTEP_Master_Out[2044] = \<const0> ;
  assign LOCKSTEP_Master_Out[2045] = \<const0> ;
  assign LOCKSTEP_Master_Out[2046] = \<const0> ;
  assign LOCKSTEP_Master_Out[2047] = \<const0> ;
  assign LOCKSTEP_Master_Out[2048] = \<const0> ;
  assign LOCKSTEP_Master_Out[2049] = \<const0> ;
  assign LOCKSTEP_Master_Out[2050] = \<const0> ;
  assign LOCKSTEP_Master_Out[2051] = \<const0> ;
  assign LOCKSTEP_Master_Out[2052] = \<const0> ;
  assign LOCKSTEP_Master_Out[2053] = \<const0> ;
  assign LOCKSTEP_Master_Out[2054] = \<const0> ;
  assign LOCKSTEP_Master_Out[2055] = \<const0> ;
  assign LOCKSTEP_Master_Out[2056] = \<const0> ;
  assign LOCKSTEP_Master_Out[2057] = \<const0> ;
  assign LOCKSTEP_Master_Out[2058] = \<const0> ;
  assign LOCKSTEP_Master_Out[2059] = \<const0> ;
  assign LOCKSTEP_Master_Out[2060] = \<const0> ;
  assign LOCKSTEP_Master_Out[2061] = \<const0> ;
  assign LOCKSTEP_Master_Out[2062] = \<const0> ;
  assign LOCKSTEP_Master_Out[2063] = \<const0> ;
  assign LOCKSTEP_Master_Out[2064] = \<const0> ;
  assign LOCKSTEP_Master_Out[2065] = \<const0> ;
  assign LOCKSTEP_Master_Out[2066] = \<const0> ;
  assign LOCKSTEP_Master_Out[2067] = \<const0> ;
  assign LOCKSTEP_Master_Out[2068] = \<const0> ;
  assign LOCKSTEP_Master_Out[2069] = \<const0> ;
  assign LOCKSTEP_Master_Out[2070] = \<const0> ;
  assign LOCKSTEP_Master_Out[2071] = \<const0> ;
  assign LOCKSTEP_Master_Out[2072] = \<const0> ;
  assign LOCKSTEP_Master_Out[2073] = \<const0> ;
  assign LOCKSTEP_Master_Out[2074] = \<const0> ;
  assign LOCKSTEP_Master_Out[2075] = \<const0> ;
  assign LOCKSTEP_Master_Out[2076] = \<const0> ;
  assign LOCKSTEP_Master_Out[2077] = \<const0> ;
  assign LOCKSTEP_Master_Out[2078] = \<const0> ;
  assign LOCKSTEP_Master_Out[2079] = \<const0> ;
  assign LOCKSTEP_Master_Out[2080] = \<const0> ;
  assign LOCKSTEP_Master_Out[2081] = \<const0> ;
  assign LOCKSTEP_Master_Out[2082] = \<const0> ;
  assign LOCKSTEP_Master_Out[2083] = \<const0> ;
  assign LOCKSTEP_Master_Out[2084] = \<const0> ;
  assign LOCKSTEP_Master_Out[2085] = \<const0> ;
  assign LOCKSTEP_Master_Out[2086] = \<const0> ;
  assign LOCKSTEP_Master_Out[2087] = \<const0> ;
  assign LOCKSTEP_Master_Out[2088] = \<const0> ;
  assign LOCKSTEP_Master_Out[2089] = \<const0> ;
  assign LOCKSTEP_Master_Out[2090] = \<const0> ;
  assign LOCKSTEP_Master_Out[2091] = \<const0> ;
  assign LOCKSTEP_Master_Out[2092] = \<const0> ;
  assign LOCKSTEP_Master_Out[2093] = \<const0> ;
  assign LOCKSTEP_Master_Out[2094] = \<const0> ;
  assign LOCKSTEP_Master_Out[2095] = \<const0> ;
  assign LOCKSTEP_Master_Out[2096] = \<const0> ;
  assign LOCKSTEP_Master_Out[2097] = \<const0> ;
  assign LOCKSTEP_Master_Out[2098] = \<const0> ;
  assign LOCKSTEP_Master_Out[2099] = \<const0> ;
  assign LOCKSTEP_Master_Out[2100] = \<const0> ;
  assign LOCKSTEP_Master_Out[2101] = \<const0> ;
  assign LOCKSTEP_Master_Out[2102] = \<const0> ;
  assign LOCKSTEP_Master_Out[2103] = \<const0> ;
  assign LOCKSTEP_Master_Out[2104] = \<const0> ;
  assign LOCKSTEP_Master_Out[2105] = \<const0> ;
  assign LOCKSTEP_Master_Out[2106] = \<const0> ;
  assign LOCKSTEP_Master_Out[2107] = \<const0> ;
  assign LOCKSTEP_Master_Out[2108] = \<const0> ;
  assign LOCKSTEP_Master_Out[2109] = \<const0> ;
  assign LOCKSTEP_Master_Out[2110] = \<const0> ;
  assign LOCKSTEP_Master_Out[2111] = \<const0> ;
  assign LOCKSTEP_Master_Out[2112] = \<const0> ;
  assign LOCKSTEP_Master_Out[2113] = \<const0> ;
  assign LOCKSTEP_Master_Out[2114] = \<const0> ;
  assign LOCKSTEP_Master_Out[2115] = \<const0> ;
  assign LOCKSTEP_Master_Out[2116] = \<const0> ;
  assign LOCKSTEP_Master_Out[2117] = \<const0> ;
  assign LOCKSTEP_Master_Out[2118] = \<const0> ;
  assign LOCKSTEP_Master_Out[2119] = \<const0> ;
  assign LOCKSTEP_Master_Out[2120] = \<const0> ;
  assign LOCKSTEP_Master_Out[2121] = \<const0> ;
  assign LOCKSTEP_Master_Out[2122] = \<const0> ;
  assign LOCKSTEP_Master_Out[2123] = \<const0> ;
  assign LOCKSTEP_Master_Out[2124] = \<const0> ;
  assign LOCKSTEP_Master_Out[2125] = \<const0> ;
  assign LOCKSTEP_Master_Out[2126] = \<const0> ;
  assign LOCKSTEP_Master_Out[2127] = \<const0> ;
  assign LOCKSTEP_Master_Out[2128] = \<const0> ;
  assign LOCKSTEP_Master_Out[2129] = \<const0> ;
  assign LOCKSTEP_Master_Out[2130] = \<const0> ;
  assign LOCKSTEP_Master_Out[2131] = \<const0> ;
  assign LOCKSTEP_Master_Out[2132] = \<const0> ;
  assign LOCKSTEP_Master_Out[2133] = \<const0> ;
  assign LOCKSTEP_Master_Out[2134] = \<const0> ;
  assign LOCKSTEP_Master_Out[2135] = \<const0> ;
  assign LOCKSTEP_Master_Out[2136] = \<const0> ;
  assign LOCKSTEP_Master_Out[2137] = \<const0> ;
  assign LOCKSTEP_Master_Out[2138] = \<const0> ;
  assign LOCKSTEP_Master_Out[2139] = \<const0> ;
  assign LOCKSTEP_Master_Out[2140] = \<const0> ;
  assign LOCKSTEP_Master_Out[2141] = \<const0> ;
  assign LOCKSTEP_Master_Out[2142] = \<const0> ;
  assign LOCKSTEP_Master_Out[2143] = \<const0> ;
  assign LOCKSTEP_Master_Out[2144] = \<const0> ;
  assign LOCKSTEP_Master_Out[2145] = \<const0> ;
  assign LOCKSTEP_Master_Out[2146] = \<const0> ;
  assign LOCKSTEP_Master_Out[2147] = \<const0> ;
  assign LOCKSTEP_Master_Out[2148] = \<const0> ;
  assign LOCKSTEP_Master_Out[2149] = \<const0> ;
  assign LOCKSTEP_Master_Out[2150] = \<const0> ;
  assign LOCKSTEP_Master_Out[2151] = \<const0> ;
  assign LOCKSTEP_Master_Out[2152] = \<const0> ;
  assign LOCKSTEP_Master_Out[2153] = \<const0> ;
  assign LOCKSTEP_Master_Out[2154] = \<const0> ;
  assign LOCKSTEP_Master_Out[2155] = \<const0> ;
  assign LOCKSTEP_Master_Out[2156] = \<const0> ;
  assign LOCKSTEP_Master_Out[2157] = \<const0> ;
  assign LOCKSTEP_Master_Out[2158] = \<const0> ;
  assign LOCKSTEP_Master_Out[2159] = \<const0> ;
  assign LOCKSTEP_Master_Out[2160] = \<const0> ;
  assign LOCKSTEP_Master_Out[2161] = \<const0> ;
  assign LOCKSTEP_Master_Out[2162] = \<const0> ;
  assign LOCKSTEP_Master_Out[2163] = \<const0> ;
  assign LOCKSTEP_Master_Out[2164] = \<const0> ;
  assign LOCKSTEP_Master_Out[2165] = \<const0> ;
  assign LOCKSTEP_Master_Out[2166] = \<const0> ;
  assign LOCKSTEP_Master_Out[2167] = \<const0> ;
  assign LOCKSTEP_Master_Out[2168] = \<const0> ;
  assign LOCKSTEP_Master_Out[2169] = \<const0> ;
  assign LOCKSTEP_Master_Out[2170] = \<const0> ;
  assign LOCKSTEP_Master_Out[2171] = \<const0> ;
  assign LOCKSTEP_Master_Out[2172] = \<const0> ;
  assign LOCKSTEP_Master_Out[2173] = \<const0> ;
  assign LOCKSTEP_Master_Out[2174] = \<const0> ;
  assign LOCKSTEP_Master_Out[2175] = \<const0> ;
  assign LOCKSTEP_Master_Out[2176] = \<const0> ;
  assign LOCKSTEP_Master_Out[2177] = \<const0> ;
  assign LOCKSTEP_Master_Out[2178] = \<const0> ;
  assign LOCKSTEP_Master_Out[2179] = \<const0> ;
  assign LOCKSTEP_Master_Out[2180] = \<const0> ;
  assign LOCKSTEP_Master_Out[2181] = \<const0> ;
  assign LOCKSTEP_Master_Out[2182] = \<const0> ;
  assign LOCKSTEP_Master_Out[2183] = \<const0> ;
  assign LOCKSTEP_Master_Out[2184] = \<const0> ;
  assign LOCKSTEP_Master_Out[2185] = \<const0> ;
  assign LOCKSTEP_Master_Out[2186] = \<const0> ;
  assign LOCKSTEP_Master_Out[2187] = \<const0> ;
  assign LOCKSTEP_Master_Out[2188] = \<const0> ;
  assign LOCKSTEP_Master_Out[2189] = \<const0> ;
  assign LOCKSTEP_Master_Out[2190] = \<const0> ;
  assign LOCKSTEP_Master_Out[2191] = \<const0> ;
  assign LOCKSTEP_Master_Out[2192] = \<const0> ;
  assign LOCKSTEP_Master_Out[2193] = \<const0> ;
  assign LOCKSTEP_Master_Out[2194] = \<const0> ;
  assign LOCKSTEP_Master_Out[2195] = \<const0> ;
  assign LOCKSTEP_Master_Out[2196] = \<const0> ;
  assign LOCKSTEP_Master_Out[2197] = \<const0> ;
  assign LOCKSTEP_Master_Out[2198] = \<const0> ;
  assign LOCKSTEP_Master_Out[2199] = \<const0> ;
  assign LOCKSTEP_Master_Out[2200] = \<const0> ;
  assign LOCKSTEP_Master_Out[2201] = \<const0> ;
  assign LOCKSTEP_Master_Out[2202] = \<const0> ;
  assign LOCKSTEP_Master_Out[2203] = \<const0> ;
  assign LOCKSTEP_Master_Out[2204] = \<const0> ;
  assign LOCKSTEP_Master_Out[2205] = \<const0> ;
  assign LOCKSTEP_Master_Out[2206] = \<const0> ;
  assign LOCKSTEP_Master_Out[2207] = \<const0> ;
  assign LOCKSTEP_Master_Out[2208] = \<const0> ;
  assign LOCKSTEP_Master_Out[2209] = \<const0> ;
  assign LOCKSTEP_Master_Out[2210] = \<const0> ;
  assign LOCKSTEP_Master_Out[2211] = \<const0> ;
  assign LOCKSTEP_Master_Out[2212] = \<const0> ;
  assign LOCKSTEP_Master_Out[2213] = \<const0> ;
  assign LOCKSTEP_Master_Out[2214] = \<const0> ;
  assign LOCKSTEP_Master_Out[2215] = \<const0> ;
  assign LOCKSTEP_Master_Out[2216] = \<const0> ;
  assign LOCKSTEP_Master_Out[2217] = \<const0> ;
  assign LOCKSTEP_Master_Out[2218] = \<const0> ;
  assign LOCKSTEP_Master_Out[2219] = \<const0> ;
  assign LOCKSTEP_Master_Out[2220] = \<const0> ;
  assign LOCKSTEP_Master_Out[2221] = \<const0> ;
  assign LOCKSTEP_Master_Out[2222] = \<const0> ;
  assign LOCKSTEP_Master_Out[2223] = \<const0> ;
  assign LOCKSTEP_Master_Out[2224] = \<const0> ;
  assign LOCKSTEP_Master_Out[2225] = \<const0> ;
  assign LOCKSTEP_Master_Out[2226] = \<const0> ;
  assign LOCKSTEP_Master_Out[2227] = \<const0> ;
  assign LOCKSTEP_Master_Out[2228] = \<const0> ;
  assign LOCKSTEP_Master_Out[2229] = \<const0> ;
  assign LOCKSTEP_Master_Out[2230] = \<const0> ;
  assign LOCKSTEP_Master_Out[2231] = \<const0> ;
  assign LOCKSTEP_Master_Out[2232] = \<const0> ;
  assign LOCKSTEP_Master_Out[2233] = \<const0> ;
  assign LOCKSTEP_Master_Out[2234] = \<const0> ;
  assign LOCKSTEP_Master_Out[2235] = \<const0> ;
  assign LOCKSTEP_Master_Out[2236] = \<const0> ;
  assign LOCKSTEP_Master_Out[2237] = \<const0> ;
  assign LOCKSTEP_Master_Out[2238] = \<const0> ;
  assign LOCKSTEP_Master_Out[2239] = \<const0> ;
  assign LOCKSTEP_Master_Out[2240] = \<const0> ;
  assign LOCKSTEP_Master_Out[2241] = \<const0> ;
  assign LOCKSTEP_Master_Out[2242] = \<const0> ;
  assign LOCKSTEP_Master_Out[2243] = \<const0> ;
  assign LOCKSTEP_Master_Out[2244] = \<const0> ;
  assign LOCKSTEP_Master_Out[2245] = \<const0> ;
  assign LOCKSTEP_Master_Out[2246] = \<const0> ;
  assign LOCKSTEP_Master_Out[2247] = \<const0> ;
  assign LOCKSTEP_Master_Out[2248] = \<const0> ;
  assign LOCKSTEP_Master_Out[2249] = \<const0> ;
  assign LOCKSTEP_Master_Out[2250] = \<const0> ;
  assign LOCKSTEP_Master_Out[2251] = \<const0> ;
  assign LOCKSTEP_Master_Out[2252] = \<const0> ;
  assign LOCKSTEP_Master_Out[2253] = \<const0> ;
  assign LOCKSTEP_Master_Out[2254] = \<const0> ;
  assign LOCKSTEP_Master_Out[2255] = \<const0> ;
  assign LOCKSTEP_Master_Out[2256] = \<const0> ;
  assign LOCKSTEP_Master_Out[2257] = \<const0> ;
  assign LOCKSTEP_Master_Out[2258] = \<const0> ;
  assign LOCKSTEP_Master_Out[2259] = \<const0> ;
  assign LOCKSTEP_Master_Out[2260] = \<const0> ;
  assign LOCKSTEP_Master_Out[2261] = \<const0> ;
  assign LOCKSTEP_Master_Out[2262] = \<const0> ;
  assign LOCKSTEP_Master_Out[2263] = \<const0> ;
  assign LOCKSTEP_Master_Out[2264] = \<const0> ;
  assign LOCKSTEP_Master_Out[2265] = \<const0> ;
  assign LOCKSTEP_Master_Out[2266] = \<const0> ;
  assign LOCKSTEP_Master_Out[2267] = \<const0> ;
  assign LOCKSTEP_Master_Out[2268] = \<const0> ;
  assign LOCKSTEP_Master_Out[2269] = \<const0> ;
  assign LOCKSTEP_Master_Out[2270] = \<const0> ;
  assign LOCKSTEP_Master_Out[2271] = \<const0> ;
  assign LOCKSTEP_Master_Out[2272] = \<const0> ;
  assign LOCKSTEP_Master_Out[2273] = \<const0> ;
  assign LOCKSTEP_Master_Out[2274] = \<const0> ;
  assign LOCKSTEP_Master_Out[2275] = \<const0> ;
  assign LOCKSTEP_Master_Out[2276] = \<const0> ;
  assign LOCKSTEP_Master_Out[2277] = \<const0> ;
  assign LOCKSTEP_Master_Out[2278] = \<const0> ;
  assign LOCKSTEP_Master_Out[2279] = \<const0> ;
  assign LOCKSTEP_Master_Out[2280] = \<const0> ;
  assign LOCKSTEP_Master_Out[2281] = \<const0> ;
  assign LOCKSTEP_Master_Out[2282] = \<const0> ;
  assign LOCKSTEP_Master_Out[2283] = \<const0> ;
  assign LOCKSTEP_Master_Out[2284] = \<const0> ;
  assign LOCKSTEP_Master_Out[2285] = \<const0> ;
  assign LOCKSTEP_Master_Out[2286] = \<const0> ;
  assign LOCKSTEP_Master_Out[2287] = \<const0> ;
  assign LOCKSTEP_Master_Out[2288] = \<const0> ;
  assign LOCKSTEP_Master_Out[2289] = \<const0> ;
  assign LOCKSTEP_Master_Out[2290] = \<const0> ;
  assign LOCKSTEP_Master_Out[2291] = \<const0> ;
  assign LOCKSTEP_Master_Out[2292] = \<const0> ;
  assign LOCKSTEP_Master_Out[2293] = \<const0> ;
  assign LOCKSTEP_Master_Out[2294] = \<const0> ;
  assign LOCKSTEP_Master_Out[2295] = \<const0> ;
  assign LOCKSTEP_Master_Out[2296] = \<const0> ;
  assign LOCKSTEP_Master_Out[2297] = \<const0> ;
  assign LOCKSTEP_Master_Out[2298] = \<const0> ;
  assign LOCKSTEP_Master_Out[2299] = \<const0> ;
  assign LOCKSTEP_Master_Out[2300] = \<const0> ;
  assign LOCKSTEP_Master_Out[2301] = \<const0> ;
  assign LOCKSTEP_Master_Out[2302] = \<const0> ;
  assign LOCKSTEP_Master_Out[2303] = \<const0> ;
  assign LOCKSTEP_Master_Out[2304] = \<const0> ;
  assign LOCKSTEP_Master_Out[2305] = \<const0> ;
  assign LOCKSTEP_Master_Out[2306] = \<const0> ;
  assign LOCKSTEP_Master_Out[2307] = \<const0> ;
  assign LOCKSTEP_Master_Out[2308] = \<const0> ;
  assign LOCKSTEP_Master_Out[2309] = \<const0> ;
  assign LOCKSTEP_Master_Out[2310] = \<const0> ;
  assign LOCKSTEP_Master_Out[2311] = \<const0> ;
  assign LOCKSTEP_Master_Out[2312] = \<const0> ;
  assign LOCKSTEP_Master_Out[2313] = \<const0> ;
  assign LOCKSTEP_Master_Out[2314] = \<const0> ;
  assign LOCKSTEP_Master_Out[2315] = \<const0> ;
  assign LOCKSTEP_Master_Out[2316] = \<const0> ;
  assign LOCKSTEP_Master_Out[2317] = \<const0> ;
  assign LOCKSTEP_Master_Out[2318] = \<const0> ;
  assign LOCKSTEP_Master_Out[2319] = \<const0> ;
  assign LOCKSTEP_Master_Out[2320] = \<const0> ;
  assign LOCKSTEP_Master_Out[2321] = \<const0> ;
  assign LOCKSTEP_Master_Out[2322] = \<const0> ;
  assign LOCKSTEP_Master_Out[2323] = \<const0> ;
  assign LOCKSTEP_Master_Out[2324] = \<const0> ;
  assign LOCKSTEP_Master_Out[2325] = \<const0> ;
  assign LOCKSTEP_Master_Out[2326] = \<const0> ;
  assign LOCKSTEP_Master_Out[2327] = \<const0> ;
  assign LOCKSTEP_Master_Out[2328] = \<const0> ;
  assign LOCKSTEP_Master_Out[2329] = \<const0> ;
  assign LOCKSTEP_Master_Out[2330] = \<const0> ;
  assign LOCKSTEP_Master_Out[2331] = \<const0> ;
  assign LOCKSTEP_Master_Out[2332] = \<const0> ;
  assign LOCKSTEP_Master_Out[2333] = \<const0> ;
  assign LOCKSTEP_Master_Out[2334] = \<const0> ;
  assign LOCKSTEP_Master_Out[2335] = \<const0> ;
  assign LOCKSTEP_Master_Out[2336] = \<const0> ;
  assign LOCKSTEP_Master_Out[2337] = \<const0> ;
  assign LOCKSTEP_Master_Out[2338] = \<const0> ;
  assign LOCKSTEP_Master_Out[2339] = \<const0> ;
  assign LOCKSTEP_Master_Out[2340] = \<const0> ;
  assign LOCKSTEP_Master_Out[2341] = \<const0> ;
  assign LOCKSTEP_Master_Out[2342] = \<const0> ;
  assign LOCKSTEP_Master_Out[2343] = \<const0> ;
  assign LOCKSTEP_Master_Out[2344] = \<const0> ;
  assign LOCKSTEP_Master_Out[2345] = \<const0> ;
  assign LOCKSTEP_Master_Out[2346] = \<const0> ;
  assign LOCKSTEP_Master_Out[2347] = \<const0> ;
  assign LOCKSTEP_Master_Out[2348] = \<const0> ;
  assign LOCKSTEP_Master_Out[2349] = \<const0> ;
  assign LOCKSTEP_Master_Out[2350] = \<const0> ;
  assign LOCKSTEP_Master_Out[2351] = \<const0> ;
  assign LOCKSTEP_Master_Out[2352] = \<const0> ;
  assign LOCKSTEP_Master_Out[2353] = \<const0> ;
  assign LOCKSTEP_Master_Out[2354] = \<const0> ;
  assign LOCKSTEP_Master_Out[2355] = \<const0> ;
  assign LOCKSTEP_Master_Out[2356] = \<const0> ;
  assign LOCKSTEP_Master_Out[2357] = \<const0> ;
  assign LOCKSTEP_Master_Out[2358] = \<const0> ;
  assign LOCKSTEP_Master_Out[2359] = \<const0> ;
  assign LOCKSTEP_Master_Out[2360] = \<const0> ;
  assign LOCKSTEP_Master_Out[2361] = \<const0> ;
  assign LOCKSTEP_Master_Out[2362] = \<const0> ;
  assign LOCKSTEP_Master_Out[2363] = \<const0> ;
  assign LOCKSTEP_Master_Out[2364] = \<const0> ;
  assign LOCKSTEP_Master_Out[2365] = \<const0> ;
  assign LOCKSTEP_Master_Out[2366] = \<const0> ;
  assign LOCKSTEP_Master_Out[2367] = \<const0> ;
  assign LOCKSTEP_Master_Out[2368] = \<const0> ;
  assign LOCKSTEP_Master_Out[2369] = \<const0> ;
  assign LOCKSTEP_Master_Out[2370] = \<const0> ;
  assign LOCKSTEP_Master_Out[2371] = \<const0> ;
  assign LOCKSTEP_Master_Out[2372] = \<const0> ;
  assign LOCKSTEP_Master_Out[2373] = \<const0> ;
  assign LOCKSTEP_Master_Out[2374] = \<const0> ;
  assign LOCKSTEP_Master_Out[2375] = \<const0> ;
  assign LOCKSTEP_Master_Out[2376] = \<const0> ;
  assign LOCKSTEP_Master_Out[2377] = \<const0> ;
  assign LOCKSTEP_Master_Out[2378] = \<const0> ;
  assign LOCKSTEP_Master_Out[2379] = \<const0> ;
  assign LOCKSTEP_Master_Out[2380] = \<const0> ;
  assign LOCKSTEP_Master_Out[2381] = \<const0> ;
  assign LOCKSTEP_Master_Out[2382] = \<const0> ;
  assign LOCKSTEP_Master_Out[2383] = \<const0> ;
  assign LOCKSTEP_Master_Out[2384] = \<const0> ;
  assign LOCKSTEP_Master_Out[2385] = \<const0> ;
  assign LOCKSTEP_Master_Out[2386] = \<const0> ;
  assign LOCKSTEP_Master_Out[2387] = \<const0> ;
  assign LOCKSTEP_Master_Out[2388] = \<const0> ;
  assign LOCKSTEP_Master_Out[2389] = \<const0> ;
  assign LOCKSTEP_Master_Out[2390] = \<const0> ;
  assign LOCKSTEP_Master_Out[2391] = \<const0> ;
  assign LOCKSTEP_Master_Out[2392] = \<const0> ;
  assign LOCKSTEP_Master_Out[2393] = \<const0> ;
  assign LOCKSTEP_Master_Out[2394] = \<const0> ;
  assign LOCKSTEP_Master_Out[2395] = \<const0> ;
  assign LOCKSTEP_Master_Out[2396] = \<const0> ;
  assign LOCKSTEP_Master_Out[2397] = \<const0> ;
  assign LOCKSTEP_Master_Out[2398] = \<const0> ;
  assign LOCKSTEP_Master_Out[2399] = \<const0> ;
  assign LOCKSTEP_Master_Out[2400] = \<const0> ;
  assign LOCKSTEP_Master_Out[2401] = \<const0> ;
  assign LOCKSTEP_Master_Out[2402] = \<const0> ;
  assign LOCKSTEP_Master_Out[2403] = \<const0> ;
  assign LOCKSTEP_Master_Out[2404] = \<const0> ;
  assign LOCKSTEP_Master_Out[2405] = \<const0> ;
  assign LOCKSTEP_Master_Out[2406] = \<const0> ;
  assign LOCKSTEP_Master_Out[2407] = \<const0> ;
  assign LOCKSTEP_Master_Out[2408] = \<const0> ;
  assign LOCKSTEP_Master_Out[2409] = \<const0> ;
  assign LOCKSTEP_Master_Out[2410] = \<const0> ;
  assign LOCKSTEP_Master_Out[2411] = \<const0> ;
  assign LOCKSTEP_Master_Out[2412] = \<const0> ;
  assign LOCKSTEP_Master_Out[2413] = \<const0> ;
  assign LOCKSTEP_Master_Out[2414] = \<const0> ;
  assign LOCKSTEP_Master_Out[2415] = \<const0> ;
  assign LOCKSTEP_Master_Out[2416] = \<const0> ;
  assign LOCKSTEP_Master_Out[2417] = \<const0> ;
  assign LOCKSTEP_Master_Out[2418] = \<const0> ;
  assign LOCKSTEP_Master_Out[2419] = \<const0> ;
  assign LOCKSTEP_Master_Out[2420] = \<const0> ;
  assign LOCKSTEP_Master_Out[2421] = \<const0> ;
  assign LOCKSTEP_Master_Out[2422] = \<const0> ;
  assign LOCKSTEP_Master_Out[2423] = \<const0> ;
  assign LOCKSTEP_Master_Out[2424] = \<const0> ;
  assign LOCKSTEP_Master_Out[2425] = \<const0> ;
  assign LOCKSTEP_Master_Out[2426] = \<const0> ;
  assign LOCKSTEP_Master_Out[2427] = \<const0> ;
  assign LOCKSTEP_Master_Out[2428] = \<const0> ;
  assign LOCKSTEP_Master_Out[2429] = \<const0> ;
  assign LOCKSTEP_Master_Out[2430] = \<const0> ;
  assign LOCKSTEP_Master_Out[2431] = \<const0> ;
  assign LOCKSTEP_Master_Out[2432] = \<const0> ;
  assign LOCKSTEP_Master_Out[2433] = \<const0> ;
  assign LOCKSTEP_Master_Out[2434] = \<const0> ;
  assign LOCKSTEP_Master_Out[2435] = \<const0> ;
  assign LOCKSTEP_Master_Out[2436] = \<const0> ;
  assign LOCKSTEP_Master_Out[2437] = \<const0> ;
  assign LOCKSTEP_Master_Out[2438] = \<const0> ;
  assign LOCKSTEP_Master_Out[2439] = \<const0> ;
  assign LOCKSTEP_Master_Out[2440] = \<const0> ;
  assign LOCKSTEP_Master_Out[2441] = \<const0> ;
  assign LOCKSTEP_Master_Out[2442] = \<const0> ;
  assign LOCKSTEP_Master_Out[2443] = \<const0> ;
  assign LOCKSTEP_Master_Out[2444] = \<const0> ;
  assign LOCKSTEP_Master_Out[2445] = \<const0> ;
  assign LOCKSTEP_Master_Out[2446] = \<const0> ;
  assign LOCKSTEP_Master_Out[2447] = \<const0> ;
  assign LOCKSTEP_Master_Out[2448] = \<const0> ;
  assign LOCKSTEP_Master_Out[2449] = \<const0> ;
  assign LOCKSTEP_Master_Out[2450] = \<const0> ;
  assign LOCKSTEP_Master_Out[2451] = \<const0> ;
  assign LOCKSTEP_Master_Out[2452] = \<const0> ;
  assign LOCKSTEP_Master_Out[2453] = \<const0> ;
  assign LOCKSTEP_Master_Out[2454] = \<const0> ;
  assign LOCKSTEP_Master_Out[2455] = \<const0> ;
  assign LOCKSTEP_Master_Out[2456] = \<const0> ;
  assign LOCKSTEP_Master_Out[2457] = \<const0> ;
  assign LOCKSTEP_Master_Out[2458] = \<const0> ;
  assign LOCKSTEP_Master_Out[2459] = \<const0> ;
  assign LOCKSTEP_Master_Out[2460] = \<const0> ;
  assign LOCKSTEP_Master_Out[2461] = \<const0> ;
  assign LOCKSTEP_Master_Out[2462] = \<const0> ;
  assign LOCKSTEP_Master_Out[2463] = \<const0> ;
  assign LOCKSTEP_Master_Out[2464] = \<const0> ;
  assign LOCKSTEP_Master_Out[2465] = \<const0> ;
  assign LOCKSTEP_Master_Out[2466] = \<const0> ;
  assign LOCKSTEP_Master_Out[2467] = \<const0> ;
  assign LOCKSTEP_Master_Out[2468] = \<const0> ;
  assign LOCKSTEP_Master_Out[2469] = \<const0> ;
  assign LOCKSTEP_Master_Out[2470] = \<const0> ;
  assign LOCKSTEP_Master_Out[2471] = \<const0> ;
  assign LOCKSTEP_Master_Out[2472] = \<const0> ;
  assign LOCKSTEP_Master_Out[2473] = \<const0> ;
  assign LOCKSTEP_Master_Out[2474] = \<const0> ;
  assign LOCKSTEP_Master_Out[2475] = \<const0> ;
  assign LOCKSTEP_Master_Out[2476] = \<const0> ;
  assign LOCKSTEP_Master_Out[2477] = \<const0> ;
  assign LOCKSTEP_Master_Out[2478] = \<const0> ;
  assign LOCKSTEP_Master_Out[2479] = \<const0> ;
  assign LOCKSTEP_Master_Out[2480] = \<const0> ;
  assign LOCKSTEP_Master_Out[2481] = \<const0> ;
  assign LOCKSTEP_Master_Out[2482] = \<const0> ;
  assign LOCKSTEP_Master_Out[2483] = \<const0> ;
  assign LOCKSTEP_Master_Out[2484] = \<const0> ;
  assign LOCKSTEP_Master_Out[2485] = \<const0> ;
  assign LOCKSTEP_Master_Out[2486] = \<const0> ;
  assign LOCKSTEP_Master_Out[2487] = \<const0> ;
  assign LOCKSTEP_Master_Out[2488] = \<const0> ;
  assign LOCKSTEP_Master_Out[2489] = \<const0> ;
  assign LOCKSTEP_Master_Out[2490] = \<const0> ;
  assign LOCKSTEP_Master_Out[2491] = \<const0> ;
  assign LOCKSTEP_Master_Out[2492] = \<const0> ;
  assign LOCKSTEP_Master_Out[2493] = \<const0> ;
  assign LOCKSTEP_Master_Out[2494] = \<const0> ;
  assign LOCKSTEP_Master_Out[2495] = \<const0> ;
  assign LOCKSTEP_Master_Out[2496] = \<const0> ;
  assign LOCKSTEP_Master_Out[2497] = \<const0> ;
  assign LOCKSTEP_Master_Out[2498] = \<const0> ;
  assign LOCKSTEP_Master_Out[2499] = \<const0> ;
  assign LOCKSTEP_Master_Out[2500] = \<const0> ;
  assign LOCKSTEP_Master_Out[2501] = \<const0> ;
  assign LOCKSTEP_Master_Out[2502] = \<const0> ;
  assign LOCKSTEP_Master_Out[2503] = \<const0> ;
  assign LOCKSTEP_Master_Out[2504] = \<const0> ;
  assign LOCKSTEP_Master_Out[2505] = \<const0> ;
  assign LOCKSTEP_Master_Out[2506] = \<const0> ;
  assign LOCKSTEP_Master_Out[2507] = \<const0> ;
  assign LOCKSTEP_Master_Out[2508] = \<const0> ;
  assign LOCKSTEP_Master_Out[2509] = \<const0> ;
  assign LOCKSTEP_Master_Out[2510] = \<const0> ;
  assign LOCKSTEP_Master_Out[2511] = \<const0> ;
  assign LOCKSTEP_Master_Out[2512] = \<const0> ;
  assign LOCKSTEP_Master_Out[2513] = \<const0> ;
  assign LOCKSTEP_Master_Out[2514] = \<const0> ;
  assign LOCKSTEP_Master_Out[2515] = \<const0> ;
  assign LOCKSTEP_Master_Out[2516] = \<const0> ;
  assign LOCKSTEP_Master_Out[2517] = \<const0> ;
  assign LOCKSTEP_Master_Out[2518] = \<const0> ;
  assign LOCKSTEP_Master_Out[2519] = \<const0> ;
  assign LOCKSTEP_Master_Out[2520] = \<const0> ;
  assign LOCKSTEP_Master_Out[2521] = \<const0> ;
  assign LOCKSTEP_Master_Out[2522] = \<const0> ;
  assign LOCKSTEP_Master_Out[2523] = \<const0> ;
  assign LOCKSTEP_Master_Out[2524] = \<const0> ;
  assign LOCKSTEP_Master_Out[2525] = \<const0> ;
  assign LOCKSTEP_Master_Out[2526] = \<const0> ;
  assign LOCKSTEP_Master_Out[2527] = \<const0> ;
  assign LOCKSTEP_Master_Out[2528] = \<const0> ;
  assign LOCKSTEP_Master_Out[2529] = \<const0> ;
  assign LOCKSTEP_Master_Out[2530] = \<const0> ;
  assign LOCKSTEP_Master_Out[2531] = \<const0> ;
  assign LOCKSTEP_Master_Out[2532] = \<const0> ;
  assign LOCKSTEP_Master_Out[2533] = \<const0> ;
  assign LOCKSTEP_Master_Out[2534] = \<const0> ;
  assign LOCKSTEP_Master_Out[2535] = \<const0> ;
  assign LOCKSTEP_Master_Out[2536] = \<const0> ;
  assign LOCKSTEP_Master_Out[2537] = \<const0> ;
  assign LOCKSTEP_Master_Out[2538] = \<const0> ;
  assign LOCKSTEP_Master_Out[2539] = \<const0> ;
  assign LOCKSTEP_Master_Out[2540] = \<const0> ;
  assign LOCKSTEP_Master_Out[2541] = \<const0> ;
  assign LOCKSTEP_Master_Out[2542] = \<const0> ;
  assign LOCKSTEP_Master_Out[2543] = \<const0> ;
  assign LOCKSTEP_Master_Out[2544] = \<const0> ;
  assign LOCKSTEP_Master_Out[2545] = \<const0> ;
  assign LOCKSTEP_Master_Out[2546] = \<const0> ;
  assign LOCKSTEP_Master_Out[2547] = \<const0> ;
  assign LOCKSTEP_Master_Out[2548] = \<const0> ;
  assign LOCKSTEP_Master_Out[2549] = \<const0> ;
  assign LOCKSTEP_Master_Out[2550] = \<const0> ;
  assign LOCKSTEP_Master_Out[2551] = \<const0> ;
  assign LOCKSTEP_Master_Out[2552] = \<const0> ;
  assign LOCKSTEP_Master_Out[2553] = \<const0> ;
  assign LOCKSTEP_Master_Out[2554] = \<const0> ;
  assign LOCKSTEP_Master_Out[2555] = \<const0> ;
  assign LOCKSTEP_Master_Out[2556] = \<const0> ;
  assign LOCKSTEP_Master_Out[2557] = \<const0> ;
  assign LOCKSTEP_Master_Out[2558] = \<const0> ;
  assign LOCKSTEP_Master_Out[2559] = \<const0> ;
  assign LOCKSTEP_Master_Out[2560] = \<const0> ;
  assign LOCKSTEP_Master_Out[2561] = \<const0> ;
  assign LOCKSTEP_Master_Out[2562] = \<const0> ;
  assign LOCKSTEP_Master_Out[2563] = \<const0> ;
  assign LOCKSTEP_Master_Out[2564] = \<const0> ;
  assign LOCKSTEP_Master_Out[2565] = \<const0> ;
  assign LOCKSTEP_Master_Out[2566] = \<const0> ;
  assign LOCKSTEP_Master_Out[2567] = \<const0> ;
  assign LOCKSTEP_Master_Out[2568] = \<const0> ;
  assign LOCKSTEP_Master_Out[2569] = \<const0> ;
  assign LOCKSTEP_Master_Out[2570] = \<const0> ;
  assign LOCKSTEP_Master_Out[2571] = \<const0> ;
  assign LOCKSTEP_Master_Out[2572] = \<const0> ;
  assign LOCKSTEP_Master_Out[2573] = \<const0> ;
  assign LOCKSTEP_Master_Out[2574] = \<const0> ;
  assign LOCKSTEP_Master_Out[2575] = \<const0> ;
  assign LOCKSTEP_Master_Out[2576] = \<const0> ;
  assign LOCKSTEP_Master_Out[2577] = \<const0> ;
  assign LOCKSTEP_Master_Out[2578] = \<const0> ;
  assign LOCKSTEP_Master_Out[2579] = \<const0> ;
  assign LOCKSTEP_Master_Out[2580] = \<const0> ;
  assign LOCKSTEP_Master_Out[2581] = \<const0> ;
  assign LOCKSTEP_Master_Out[2582] = \<const0> ;
  assign LOCKSTEP_Master_Out[2583] = \<const0> ;
  assign LOCKSTEP_Master_Out[2584] = \<const0> ;
  assign LOCKSTEP_Master_Out[2585] = \<const0> ;
  assign LOCKSTEP_Master_Out[2586] = \<const0> ;
  assign LOCKSTEP_Master_Out[2587] = \<const0> ;
  assign LOCKSTEP_Master_Out[2588] = \<const0> ;
  assign LOCKSTEP_Master_Out[2589] = \<const0> ;
  assign LOCKSTEP_Master_Out[2590] = \<const0> ;
  assign LOCKSTEP_Master_Out[2591] = \<const0> ;
  assign LOCKSTEP_Master_Out[2592] = \<const0> ;
  assign LOCKSTEP_Master_Out[2593] = \<const0> ;
  assign LOCKSTEP_Master_Out[2594] = \<const0> ;
  assign LOCKSTEP_Master_Out[2595] = \<const0> ;
  assign LOCKSTEP_Master_Out[2596] = \<const0> ;
  assign LOCKSTEP_Master_Out[2597] = \<const0> ;
  assign LOCKSTEP_Master_Out[2598] = \<const0> ;
  assign LOCKSTEP_Master_Out[2599] = \<const0> ;
  assign LOCKSTEP_Master_Out[2600] = \<const0> ;
  assign LOCKSTEP_Master_Out[2601] = \<const0> ;
  assign LOCKSTEP_Master_Out[2602] = \<const0> ;
  assign LOCKSTEP_Master_Out[2603] = \<const0> ;
  assign LOCKSTEP_Master_Out[2604] = \<const0> ;
  assign LOCKSTEP_Master_Out[2605] = \<const0> ;
  assign LOCKSTEP_Master_Out[2606] = \<const0> ;
  assign LOCKSTEP_Master_Out[2607] = \<const0> ;
  assign LOCKSTEP_Master_Out[2608] = \<const0> ;
  assign LOCKSTEP_Master_Out[2609] = \<const0> ;
  assign LOCKSTEP_Master_Out[2610] = \<const0> ;
  assign LOCKSTEP_Master_Out[2611] = \<const0> ;
  assign LOCKSTEP_Master_Out[2612] = \<const0> ;
  assign LOCKSTEP_Master_Out[2613] = \<const0> ;
  assign LOCKSTEP_Master_Out[2614] = \<const0> ;
  assign LOCKSTEP_Master_Out[2615] = \<const0> ;
  assign LOCKSTEP_Master_Out[2616] = \<const0> ;
  assign LOCKSTEP_Master_Out[2617] = \<const0> ;
  assign LOCKSTEP_Master_Out[2618] = \<const0> ;
  assign LOCKSTEP_Master_Out[2619] = \<const0> ;
  assign LOCKSTEP_Master_Out[2620] = \<const0> ;
  assign LOCKSTEP_Master_Out[2621] = \<const0> ;
  assign LOCKSTEP_Master_Out[2622] = \<const0> ;
  assign LOCKSTEP_Master_Out[2623] = \<const0> ;
  assign LOCKSTEP_Master_Out[2624] = \<const0> ;
  assign LOCKSTEP_Master_Out[2625] = \<const0> ;
  assign LOCKSTEP_Master_Out[2626] = \<const0> ;
  assign LOCKSTEP_Master_Out[2627] = \<const0> ;
  assign LOCKSTEP_Master_Out[2628] = \<const0> ;
  assign LOCKSTEP_Master_Out[2629] = \<const0> ;
  assign LOCKSTEP_Master_Out[2630] = \<const0> ;
  assign LOCKSTEP_Master_Out[2631] = \<const0> ;
  assign LOCKSTEP_Master_Out[2632] = \<const0> ;
  assign LOCKSTEP_Master_Out[2633] = \<const0> ;
  assign LOCKSTEP_Master_Out[2634] = \<const0> ;
  assign LOCKSTEP_Master_Out[2635] = \<const0> ;
  assign LOCKSTEP_Master_Out[2636] = \<const0> ;
  assign LOCKSTEP_Master_Out[2637] = \<const0> ;
  assign LOCKSTEP_Master_Out[2638] = \<const0> ;
  assign LOCKSTEP_Master_Out[2639] = \<const0> ;
  assign LOCKSTEP_Master_Out[2640] = \<const0> ;
  assign LOCKSTEP_Master_Out[2641] = \<const0> ;
  assign LOCKSTEP_Master_Out[2642] = \<const0> ;
  assign LOCKSTEP_Master_Out[2643] = \<const0> ;
  assign LOCKSTEP_Master_Out[2644] = \<const0> ;
  assign LOCKSTEP_Master_Out[2645] = \<const0> ;
  assign LOCKSTEP_Master_Out[2646] = \<const0> ;
  assign LOCKSTEP_Master_Out[2647] = \<const0> ;
  assign LOCKSTEP_Master_Out[2648] = \<const0> ;
  assign LOCKSTEP_Master_Out[2649] = \<const0> ;
  assign LOCKSTEP_Master_Out[2650] = \<const0> ;
  assign LOCKSTEP_Master_Out[2651] = \<const0> ;
  assign LOCKSTEP_Master_Out[2652] = \<const0> ;
  assign LOCKSTEP_Master_Out[2653] = \<const0> ;
  assign LOCKSTEP_Master_Out[2654] = \<const0> ;
  assign LOCKSTEP_Master_Out[2655] = \<const0> ;
  assign LOCKSTEP_Master_Out[2656] = \<const0> ;
  assign LOCKSTEP_Master_Out[2657] = \<const0> ;
  assign LOCKSTEP_Master_Out[2658] = \<const0> ;
  assign LOCKSTEP_Master_Out[2659] = \<const0> ;
  assign LOCKSTEP_Master_Out[2660] = \<const0> ;
  assign LOCKSTEP_Master_Out[2661] = \<const0> ;
  assign LOCKSTEP_Master_Out[2662] = \<const0> ;
  assign LOCKSTEP_Master_Out[2663] = \<const0> ;
  assign LOCKSTEP_Master_Out[2664] = \<const0> ;
  assign LOCKSTEP_Master_Out[2665] = \<const0> ;
  assign LOCKSTEP_Master_Out[2666] = \<const0> ;
  assign LOCKSTEP_Master_Out[2667] = \<const0> ;
  assign LOCKSTEP_Master_Out[2668] = \<const0> ;
  assign LOCKSTEP_Master_Out[2669] = \<const0> ;
  assign LOCKSTEP_Master_Out[2670] = \<const0> ;
  assign LOCKSTEP_Master_Out[2671] = \<const0> ;
  assign LOCKSTEP_Master_Out[2672] = \<const0> ;
  assign LOCKSTEP_Master_Out[2673] = \<const0> ;
  assign LOCKSTEP_Master_Out[2674] = \<const0> ;
  assign LOCKSTEP_Master_Out[2675] = \<const0> ;
  assign LOCKSTEP_Master_Out[2676] = \<const0> ;
  assign LOCKSTEP_Master_Out[2677] = \<const0> ;
  assign LOCKSTEP_Master_Out[2678] = \<const0> ;
  assign LOCKSTEP_Master_Out[2679] = \<const0> ;
  assign LOCKSTEP_Master_Out[2680] = \<const0> ;
  assign LOCKSTEP_Master_Out[2681] = \<const0> ;
  assign LOCKSTEP_Master_Out[2682] = \<const0> ;
  assign LOCKSTEP_Master_Out[2683] = \<const0> ;
  assign LOCKSTEP_Master_Out[2684] = \<const0> ;
  assign LOCKSTEP_Master_Out[2685] = \<const0> ;
  assign LOCKSTEP_Master_Out[2686] = \<const0> ;
  assign LOCKSTEP_Master_Out[2687] = \<const0> ;
  assign LOCKSTEP_Master_Out[2688] = \<const0> ;
  assign LOCKSTEP_Master_Out[2689] = \<const0> ;
  assign LOCKSTEP_Master_Out[2690] = \<const0> ;
  assign LOCKSTEP_Master_Out[2691] = \<const0> ;
  assign LOCKSTEP_Master_Out[2692] = \<const0> ;
  assign LOCKSTEP_Master_Out[2693] = \<const0> ;
  assign LOCKSTEP_Master_Out[2694] = \<const0> ;
  assign LOCKSTEP_Master_Out[2695] = \<const0> ;
  assign LOCKSTEP_Master_Out[2696] = \<const0> ;
  assign LOCKSTEP_Master_Out[2697] = \<const0> ;
  assign LOCKSTEP_Master_Out[2698] = \<const0> ;
  assign LOCKSTEP_Master_Out[2699] = \<const0> ;
  assign LOCKSTEP_Master_Out[2700] = \<const0> ;
  assign LOCKSTEP_Master_Out[2701] = \<const0> ;
  assign LOCKSTEP_Master_Out[2702] = \<const0> ;
  assign LOCKSTEP_Master_Out[2703] = \<const0> ;
  assign LOCKSTEP_Master_Out[2704] = \<const0> ;
  assign LOCKSTEP_Master_Out[2705] = \<const0> ;
  assign LOCKSTEP_Master_Out[2706] = \<const0> ;
  assign LOCKSTEP_Master_Out[2707] = \<const0> ;
  assign LOCKSTEP_Master_Out[2708] = \<const0> ;
  assign LOCKSTEP_Master_Out[2709] = \<const0> ;
  assign LOCKSTEP_Master_Out[2710] = \<const0> ;
  assign LOCKSTEP_Master_Out[2711] = \<const0> ;
  assign LOCKSTEP_Master_Out[2712] = \<const0> ;
  assign LOCKSTEP_Master_Out[2713] = \<const0> ;
  assign LOCKSTEP_Master_Out[2714] = \<const0> ;
  assign LOCKSTEP_Master_Out[2715] = \<const0> ;
  assign LOCKSTEP_Master_Out[2716] = \<const0> ;
  assign LOCKSTEP_Master_Out[2717] = \<const0> ;
  assign LOCKSTEP_Master_Out[2718] = \<const0> ;
  assign LOCKSTEP_Master_Out[2719] = \<const0> ;
  assign LOCKSTEP_Master_Out[2720] = \<const0> ;
  assign LOCKSTEP_Master_Out[2721] = \<const0> ;
  assign LOCKSTEP_Master_Out[2722] = \<const0> ;
  assign LOCKSTEP_Master_Out[2723] = \<const0> ;
  assign LOCKSTEP_Master_Out[2724] = \<const0> ;
  assign LOCKSTEP_Master_Out[2725] = \<const0> ;
  assign LOCKSTEP_Master_Out[2726] = \<const0> ;
  assign LOCKSTEP_Master_Out[2727] = \<const0> ;
  assign LOCKSTEP_Master_Out[2728] = \<const0> ;
  assign LOCKSTEP_Master_Out[2729] = \<const0> ;
  assign LOCKSTEP_Master_Out[2730] = \<const0> ;
  assign LOCKSTEP_Master_Out[2731] = \<const0> ;
  assign LOCKSTEP_Master_Out[2732] = \<const0> ;
  assign LOCKSTEP_Master_Out[2733] = \<const0> ;
  assign LOCKSTEP_Master_Out[2734] = \<const0> ;
  assign LOCKSTEP_Master_Out[2735] = \<const0> ;
  assign LOCKSTEP_Master_Out[2736] = \<const0> ;
  assign LOCKSTEP_Master_Out[2737] = \<const0> ;
  assign LOCKSTEP_Master_Out[2738] = \<const0> ;
  assign LOCKSTEP_Master_Out[2739] = \<const0> ;
  assign LOCKSTEP_Master_Out[2740] = \<const0> ;
  assign LOCKSTEP_Master_Out[2741] = \<const0> ;
  assign LOCKSTEP_Master_Out[2742] = \<const0> ;
  assign LOCKSTEP_Master_Out[2743] = \<const0> ;
  assign LOCKSTEP_Master_Out[2744] = \<const0> ;
  assign LOCKSTEP_Master_Out[2745] = \<const0> ;
  assign LOCKSTEP_Master_Out[2746] = \<const0> ;
  assign LOCKSTEP_Master_Out[2747] = \<const0> ;
  assign LOCKSTEP_Master_Out[2748] = \<const0> ;
  assign LOCKSTEP_Master_Out[2749] = \<const0> ;
  assign LOCKSTEP_Master_Out[2750] = \<const0> ;
  assign LOCKSTEP_Master_Out[2751] = \<const0> ;
  assign LOCKSTEP_Master_Out[2752] = \<const0> ;
  assign LOCKSTEP_Master_Out[2753] = \<const0> ;
  assign LOCKSTEP_Master_Out[2754] = \<const0> ;
  assign LOCKSTEP_Master_Out[2755] = \<const0> ;
  assign LOCKSTEP_Master_Out[2756] = \<const0> ;
  assign LOCKSTEP_Master_Out[2757] = \<const0> ;
  assign LOCKSTEP_Master_Out[2758] = \<const0> ;
  assign LOCKSTEP_Master_Out[2759] = \<const0> ;
  assign LOCKSTEP_Master_Out[2760] = \<const0> ;
  assign LOCKSTEP_Master_Out[2761] = \<const0> ;
  assign LOCKSTEP_Master_Out[2762] = \<const0> ;
  assign LOCKSTEP_Master_Out[2763] = \<const0> ;
  assign LOCKSTEP_Master_Out[2764] = \<const0> ;
  assign LOCKSTEP_Master_Out[2765] = \<const0> ;
  assign LOCKSTEP_Master_Out[2766] = \<const0> ;
  assign LOCKSTEP_Master_Out[2767] = \<const0> ;
  assign LOCKSTEP_Master_Out[2768] = \<const0> ;
  assign LOCKSTEP_Master_Out[2769] = \<const0> ;
  assign LOCKSTEP_Master_Out[2770] = \<const0> ;
  assign LOCKSTEP_Master_Out[2771] = \<const0> ;
  assign LOCKSTEP_Master_Out[2772] = \<const0> ;
  assign LOCKSTEP_Master_Out[2773] = \<const0> ;
  assign LOCKSTEP_Master_Out[2774] = \<const0> ;
  assign LOCKSTEP_Master_Out[2775] = \<const0> ;
  assign LOCKSTEP_Master_Out[2776] = \<const0> ;
  assign LOCKSTEP_Master_Out[2777] = \<const0> ;
  assign LOCKSTEP_Master_Out[2778] = \<const0> ;
  assign LOCKSTEP_Master_Out[2779] = \<const0> ;
  assign LOCKSTEP_Master_Out[2780] = \<const0> ;
  assign LOCKSTEP_Master_Out[2781] = \<const0> ;
  assign LOCKSTEP_Master_Out[2782] = \<const0> ;
  assign LOCKSTEP_Master_Out[2783] = \<const0> ;
  assign LOCKSTEP_Master_Out[2784] = \<const0> ;
  assign LOCKSTEP_Master_Out[2785] = \<const0> ;
  assign LOCKSTEP_Master_Out[2786] = \<const0> ;
  assign LOCKSTEP_Master_Out[2787] = \<const0> ;
  assign LOCKSTEP_Master_Out[2788] = \<const0> ;
  assign LOCKSTEP_Master_Out[2789] = \<const0> ;
  assign LOCKSTEP_Master_Out[2790] = \<const0> ;
  assign LOCKSTEP_Master_Out[2791] = \<const0> ;
  assign LOCKSTEP_Master_Out[2792] = \<const0> ;
  assign LOCKSTEP_Master_Out[2793] = \<const0> ;
  assign LOCKSTEP_Master_Out[2794] = \<const0> ;
  assign LOCKSTEP_Master_Out[2795] = \<const0> ;
  assign LOCKSTEP_Master_Out[2796] = \<const0> ;
  assign LOCKSTEP_Master_Out[2797] = \<const0> ;
  assign LOCKSTEP_Master_Out[2798] = \<const0> ;
  assign LOCKSTEP_Master_Out[2799] = \<const0> ;
  assign LOCKSTEP_Master_Out[2800] = \<const0> ;
  assign LOCKSTEP_Master_Out[2801] = \<const0> ;
  assign LOCKSTEP_Master_Out[2802] = \<const0> ;
  assign LOCKSTEP_Master_Out[2803] = \<const0> ;
  assign LOCKSTEP_Master_Out[2804] = \<const0> ;
  assign LOCKSTEP_Master_Out[2805] = \<const0> ;
  assign LOCKSTEP_Master_Out[2806] = \<const0> ;
  assign LOCKSTEP_Master_Out[2807] = \<const0> ;
  assign LOCKSTEP_Master_Out[2808] = \<const0> ;
  assign LOCKSTEP_Master_Out[2809] = \<const0> ;
  assign LOCKSTEP_Master_Out[2810] = \<const0> ;
  assign LOCKSTEP_Master_Out[2811] = \<const0> ;
  assign LOCKSTEP_Master_Out[2812] = \<const0> ;
  assign LOCKSTEP_Master_Out[2813] = \<const0> ;
  assign LOCKSTEP_Master_Out[2814] = \<const0> ;
  assign LOCKSTEP_Master_Out[2815] = \<const0> ;
  assign LOCKSTEP_Master_Out[2816] = \<const0> ;
  assign LOCKSTEP_Master_Out[2817] = \<const0> ;
  assign LOCKSTEP_Master_Out[2818] = \<const0> ;
  assign LOCKSTEP_Master_Out[2819] = \<const0> ;
  assign LOCKSTEP_Master_Out[2820] = \<const0> ;
  assign LOCKSTEP_Master_Out[2821] = \<const0> ;
  assign LOCKSTEP_Master_Out[2822] = \<const0> ;
  assign LOCKSTEP_Master_Out[2823] = \<const0> ;
  assign LOCKSTEP_Master_Out[2824] = \<const0> ;
  assign LOCKSTEP_Master_Out[2825] = \<const0> ;
  assign LOCKSTEP_Master_Out[2826] = \<const0> ;
  assign LOCKSTEP_Master_Out[2827] = \<const0> ;
  assign LOCKSTEP_Master_Out[2828] = \<const0> ;
  assign LOCKSTEP_Master_Out[2829] = \<const0> ;
  assign LOCKSTEP_Master_Out[2830] = \<const0> ;
  assign LOCKSTEP_Master_Out[2831] = \<const0> ;
  assign LOCKSTEP_Master_Out[2832] = \<const0> ;
  assign LOCKSTEP_Master_Out[2833] = \<const0> ;
  assign LOCKSTEP_Master_Out[2834] = \<const0> ;
  assign LOCKSTEP_Master_Out[2835] = \<const0> ;
  assign LOCKSTEP_Master_Out[2836] = \<const0> ;
  assign LOCKSTEP_Master_Out[2837] = \<const0> ;
  assign LOCKSTEP_Master_Out[2838] = \<const0> ;
  assign LOCKSTEP_Master_Out[2839] = \<const0> ;
  assign LOCKSTEP_Master_Out[2840] = \<const0> ;
  assign LOCKSTEP_Master_Out[2841] = \<const0> ;
  assign LOCKSTEP_Master_Out[2842] = \<const0> ;
  assign LOCKSTEP_Master_Out[2843] = \<const0> ;
  assign LOCKSTEP_Master_Out[2844] = \<const0> ;
  assign LOCKSTEP_Master_Out[2845] = \<const0> ;
  assign LOCKSTEP_Master_Out[2846] = \<const0> ;
  assign LOCKSTEP_Master_Out[2847] = \<const0> ;
  assign LOCKSTEP_Master_Out[2848] = \<const0> ;
  assign LOCKSTEP_Master_Out[2849] = \<const0> ;
  assign LOCKSTEP_Master_Out[2850] = \<const0> ;
  assign LOCKSTEP_Master_Out[2851] = \<const0> ;
  assign LOCKSTEP_Master_Out[2852] = \<const0> ;
  assign LOCKSTEP_Master_Out[2853] = \<const0> ;
  assign LOCKSTEP_Master_Out[2854] = \<const0> ;
  assign LOCKSTEP_Master_Out[2855] = \<const0> ;
  assign LOCKSTEP_Master_Out[2856] = \<const0> ;
  assign LOCKSTEP_Master_Out[2857] = \<const0> ;
  assign LOCKSTEP_Master_Out[2858] = \<const0> ;
  assign LOCKSTEP_Master_Out[2859] = \<const0> ;
  assign LOCKSTEP_Master_Out[2860] = \<const0> ;
  assign LOCKSTEP_Master_Out[2861] = \<const0> ;
  assign LOCKSTEP_Master_Out[2862] = \<const0> ;
  assign LOCKSTEP_Master_Out[2863] = \<const0> ;
  assign LOCKSTEP_Master_Out[2864] = \<const0> ;
  assign LOCKSTEP_Master_Out[2865] = \<const0> ;
  assign LOCKSTEP_Master_Out[2866] = \<const0> ;
  assign LOCKSTEP_Master_Out[2867] = \<const0> ;
  assign LOCKSTEP_Master_Out[2868] = \<const0> ;
  assign LOCKSTEP_Master_Out[2869] = \<const0> ;
  assign LOCKSTEP_Master_Out[2870] = \<const0> ;
  assign LOCKSTEP_Master_Out[2871] = \<const0> ;
  assign LOCKSTEP_Master_Out[2872] = \<const0> ;
  assign LOCKSTEP_Master_Out[2873] = \<const0> ;
  assign LOCKSTEP_Master_Out[2874] = \<const0> ;
  assign LOCKSTEP_Master_Out[2875] = \<const0> ;
  assign LOCKSTEP_Master_Out[2876] = \<const0> ;
  assign LOCKSTEP_Master_Out[2877] = \<const0> ;
  assign LOCKSTEP_Master_Out[2878] = \<const0> ;
  assign LOCKSTEP_Master_Out[2879] = \<const0> ;
  assign LOCKSTEP_Master_Out[2880] = \<const0> ;
  assign LOCKSTEP_Master_Out[2881] = \<const0> ;
  assign LOCKSTEP_Master_Out[2882] = \<const0> ;
  assign LOCKSTEP_Master_Out[2883] = \<const0> ;
  assign LOCKSTEP_Master_Out[2884] = \<const0> ;
  assign LOCKSTEP_Master_Out[2885] = \<const0> ;
  assign LOCKSTEP_Master_Out[2886] = \<const0> ;
  assign LOCKSTEP_Master_Out[2887] = \<const0> ;
  assign LOCKSTEP_Master_Out[2888] = \<const0> ;
  assign LOCKSTEP_Master_Out[2889] = \<const0> ;
  assign LOCKSTEP_Master_Out[2890] = \<const0> ;
  assign LOCKSTEP_Master_Out[2891] = \<const0> ;
  assign LOCKSTEP_Master_Out[2892] = \<const0> ;
  assign LOCKSTEP_Master_Out[2893] = \<const0> ;
  assign LOCKSTEP_Master_Out[2894] = \<const0> ;
  assign LOCKSTEP_Master_Out[2895] = \<const0> ;
  assign LOCKSTEP_Master_Out[2896] = \<const0> ;
  assign LOCKSTEP_Master_Out[2897] = \<const0> ;
  assign LOCKSTEP_Master_Out[2898] = \<const0> ;
  assign LOCKSTEP_Master_Out[2899] = \<const0> ;
  assign LOCKSTEP_Master_Out[2900] = \<const0> ;
  assign LOCKSTEP_Master_Out[2901] = \<const0> ;
  assign LOCKSTEP_Master_Out[2902] = \<const0> ;
  assign LOCKSTEP_Master_Out[2903] = \<const0> ;
  assign LOCKSTEP_Master_Out[2904] = \<const0> ;
  assign LOCKSTEP_Master_Out[2905] = \<const0> ;
  assign LOCKSTEP_Master_Out[2906] = \<const0> ;
  assign LOCKSTEP_Master_Out[2907] = \<const0> ;
  assign LOCKSTEP_Master_Out[2908] = \<const0> ;
  assign LOCKSTEP_Master_Out[2909] = \<const0> ;
  assign LOCKSTEP_Master_Out[2910] = \<const0> ;
  assign LOCKSTEP_Master_Out[2911] = \<const0> ;
  assign LOCKSTEP_Master_Out[2912] = \<const0> ;
  assign LOCKSTEP_Master_Out[2913] = \<const0> ;
  assign LOCKSTEP_Master_Out[2914] = \<const0> ;
  assign LOCKSTEP_Master_Out[2915] = \<const0> ;
  assign LOCKSTEP_Master_Out[2916] = \<const0> ;
  assign LOCKSTEP_Master_Out[2917] = \<const0> ;
  assign LOCKSTEP_Master_Out[2918] = \<const0> ;
  assign LOCKSTEP_Master_Out[2919] = \<const0> ;
  assign LOCKSTEP_Master_Out[2920] = \<const0> ;
  assign LOCKSTEP_Master_Out[2921] = \<const0> ;
  assign LOCKSTEP_Master_Out[2922] = \<const0> ;
  assign LOCKSTEP_Master_Out[2923] = \<const0> ;
  assign LOCKSTEP_Master_Out[2924] = \<const0> ;
  assign LOCKSTEP_Master_Out[2925] = \<const0> ;
  assign LOCKSTEP_Master_Out[2926] = \<const0> ;
  assign LOCKSTEP_Master_Out[2927] = \<const0> ;
  assign LOCKSTEP_Master_Out[2928] = \<const0> ;
  assign LOCKSTEP_Master_Out[2929] = \<const0> ;
  assign LOCKSTEP_Master_Out[2930] = \<const0> ;
  assign LOCKSTEP_Master_Out[2931] = \<const0> ;
  assign LOCKSTEP_Master_Out[2932] = \<const0> ;
  assign LOCKSTEP_Master_Out[2933] = \<const0> ;
  assign LOCKSTEP_Master_Out[2934] = \<const0> ;
  assign LOCKSTEP_Master_Out[2935] = \<const0> ;
  assign LOCKSTEP_Master_Out[2936] = \<const0> ;
  assign LOCKSTEP_Master_Out[2937] = \<const0> ;
  assign LOCKSTEP_Master_Out[2938] = \<const0> ;
  assign LOCKSTEP_Master_Out[2939] = \<const0> ;
  assign LOCKSTEP_Master_Out[2940] = \<const0> ;
  assign LOCKSTEP_Master_Out[2941] = \<const0> ;
  assign LOCKSTEP_Master_Out[2942] = \<const0> ;
  assign LOCKSTEP_Master_Out[2943] = \<const0> ;
  assign LOCKSTEP_Master_Out[2944] = \<const0> ;
  assign LOCKSTEP_Master_Out[2945] = \<const0> ;
  assign LOCKSTEP_Master_Out[2946] = \<const0> ;
  assign LOCKSTEP_Master_Out[2947] = \<const0> ;
  assign LOCKSTEP_Master_Out[2948] = \<const0> ;
  assign LOCKSTEP_Master_Out[2949] = \<const0> ;
  assign LOCKSTEP_Master_Out[2950] = \<const0> ;
  assign LOCKSTEP_Master_Out[2951] = \<const0> ;
  assign LOCKSTEP_Master_Out[2952] = \<const0> ;
  assign LOCKSTEP_Master_Out[2953] = \<const0> ;
  assign LOCKSTEP_Master_Out[2954] = \<const0> ;
  assign LOCKSTEP_Master_Out[2955] = \<const0> ;
  assign LOCKSTEP_Master_Out[2956] = \<const0> ;
  assign LOCKSTEP_Master_Out[2957] = \<const0> ;
  assign LOCKSTEP_Master_Out[2958] = \<const0> ;
  assign LOCKSTEP_Master_Out[2959] = \<const0> ;
  assign LOCKSTEP_Master_Out[2960] = \<const0> ;
  assign LOCKSTEP_Master_Out[2961] = \<const0> ;
  assign LOCKSTEP_Master_Out[2962] = \<const0> ;
  assign LOCKSTEP_Master_Out[2963] = \<const0> ;
  assign LOCKSTEP_Master_Out[2964] = \<const0> ;
  assign LOCKSTEP_Master_Out[2965] = \<const0> ;
  assign LOCKSTEP_Master_Out[2966] = \<const0> ;
  assign LOCKSTEP_Master_Out[2967] = \<const0> ;
  assign LOCKSTEP_Master_Out[2968] = \<const0> ;
  assign LOCKSTEP_Master_Out[2969] = \<const0> ;
  assign LOCKSTEP_Master_Out[2970] = \<const0> ;
  assign LOCKSTEP_Master_Out[2971] = \<const0> ;
  assign LOCKSTEP_Master_Out[2972] = \<const0> ;
  assign LOCKSTEP_Master_Out[2973] = \<const0> ;
  assign LOCKSTEP_Master_Out[2974] = \<const0> ;
  assign LOCKSTEP_Master_Out[2975] = \<const0> ;
  assign LOCKSTEP_Master_Out[2976] = \<const0> ;
  assign LOCKSTEP_Master_Out[2977] = \<const0> ;
  assign LOCKSTEP_Master_Out[2978] = \<const0> ;
  assign LOCKSTEP_Master_Out[2979] = \<const0> ;
  assign LOCKSTEP_Master_Out[2980] = \<const0> ;
  assign LOCKSTEP_Master_Out[2981] = \<const0> ;
  assign LOCKSTEP_Master_Out[2982] = \<const0> ;
  assign LOCKSTEP_Master_Out[2983] = \<const0> ;
  assign LOCKSTEP_Master_Out[2984] = \<const0> ;
  assign LOCKSTEP_Master_Out[2985] = \<const0> ;
  assign LOCKSTEP_Master_Out[2986] = \<const0> ;
  assign LOCKSTEP_Master_Out[2987] = \<const0> ;
  assign LOCKSTEP_Master_Out[2988] = \<const0> ;
  assign LOCKSTEP_Master_Out[2989] = \<const0> ;
  assign LOCKSTEP_Master_Out[2990] = \<const0> ;
  assign LOCKSTEP_Master_Out[2991] = \<const0> ;
  assign LOCKSTEP_Master_Out[2992] = \<const0> ;
  assign LOCKSTEP_Master_Out[2993] = \<const0> ;
  assign LOCKSTEP_Master_Out[2994] = \<const0> ;
  assign LOCKSTEP_Master_Out[2995] = \<const0> ;
  assign LOCKSTEP_Master_Out[2996] = \<const0> ;
  assign LOCKSTEP_Master_Out[2997] = \<const0> ;
  assign LOCKSTEP_Master_Out[2998] = \<const0> ;
  assign LOCKSTEP_Master_Out[2999] = \<const0> ;
  assign LOCKSTEP_Master_Out[3000] = \<const0> ;
  assign LOCKSTEP_Master_Out[3001] = \<const0> ;
  assign LOCKSTEP_Master_Out[3002] = \<const0> ;
  assign LOCKSTEP_Master_Out[3003] = \<const0> ;
  assign LOCKSTEP_Master_Out[3004] = \<const0> ;
  assign LOCKSTEP_Master_Out[3005] = \<const0> ;
  assign LOCKSTEP_Master_Out[3006] = \<const0> ;
  assign LOCKSTEP_Master_Out[3007] = \<const0> ;
  assign LOCKSTEP_Master_Out[3008] = \<const0> ;
  assign LOCKSTEP_Master_Out[3009] = \<const0> ;
  assign LOCKSTEP_Master_Out[3010] = \<const0> ;
  assign LOCKSTEP_Master_Out[3011] = \<const0> ;
  assign LOCKSTEP_Master_Out[3012] = \<const0> ;
  assign LOCKSTEP_Master_Out[3013] = \<const0> ;
  assign LOCKSTEP_Master_Out[3014] = \<const0> ;
  assign LOCKSTEP_Master_Out[3015] = \<const0> ;
  assign LOCKSTEP_Master_Out[3016] = \<const0> ;
  assign LOCKSTEP_Master_Out[3017] = \<const0> ;
  assign LOCKSTEP_Master_Out[3018] = \<const0> ;
  assign LOCKSTEP_Master_Out[3019] = \<const0> ;
  assign LOCKSTEP_Master_Out[3020] = \<const0> ;
  assign LOCKSTEP_Master_Out[3021] = \<const0> ;
  assign LOCKSTEP_Master_Out[3022] = \<const0> ;
  assign LOCKSTEP_Master_Out[3023] = \<const0> ;
  assign LOCKSTEP_Master_Out[3024] = \<const0> ;
  assign LOCKSTEP_Master_Out[3025] = \<const0> ;
  assign LOCKSTEP_Master_Out[3026] = \<const0> ;
  assign LOCKSTEP_Master_Out[3027] = \<const0> ;
  assign LOCKSTEP_Master_Out[3028] = \<const0> ;
  assign LOCKSTEP_Master_Out[3029] = \<const0> ;
  assign LOCKSTEP_Master_Out[3030] = \<const0> ;
  assign LOCKSTEP_Master_Out[3031] = \<const0> ;
  assign LOCKSTEP_Master_Out[3032] = \<const0> ;
  assign LOCKSTEP_Master_Out[3033] = \<const0> ;
  assign LOCKSTEP_Master_Out[3034] = \<const0> ;
  assign LOCKSTEP_Master_Out[3035] = \<const0> ;
  assign LOCKSTEP_Master_Out[3036] = \<const0> ;
  assign LOCKSTEP_Master_Out[3037] = \<const0> ;
  assign LOCKSTEP_Master_Out[3038] = \<const0> ;
  assign LOCKSTEP_Master_Out[3039] = \<const0> ;
  assign LOCKSTEP_Master_Out[3040] = \<const0> ;
  assign LOCKSTEP_Master_Out[3041] = \<const0> ;
  assign LOCKSTEP_Master_Out[3042] = \<const0> ;
  assign LOCKSTEP_Master_Out[3043] = \<const0> ;
  assign LOCKSTEP_Master_Out[3044] = \<const0> ;
  assign LOCKSTEP_Master_Out[3045] = \<const0> ;
  assign LOCKSTEP_Master_Out[3046] = \<const0> ;
  assign LOCKSTEP_Master_Out[3047] = \<const0> ;
  assign LOCKSTEP_Master_Out[3048] = \<const0> ;
  assign LOCKSTEP_Master_Out[3049] = \<const0> ;
  assign LOCKSTEP_Master_Out[3050] = \<const0> ;
  assign LOCKSTEP_Master_Out[3051] = \<const0> ;
  assign LOCKSTEP_Master_Out[3052] = \<const0> ;
  assign LOCKSTEP_Master_Out[3053] = \<const0> ;
  assign LOCKSTEP_Master_Out[3054] = \<const0> ;
  assign LOCKSTEP_Master_Out[3055] = \<const0> ;
  assign LOCKSTEP_Master_Out[3056] = \<const0> ;
  assign LOCKSTEP_Master_Out[3057] = \<const0> ;
  assign LOCKSTEP_Master_Out[3058] = \<const0> ;
  assign LOCKSTEP_Master_Out[3059] = \<const0> ;
  assign LOCKSTEP_Master_Out[3060] = \<const0> ;
  assign LOCKSTEP_Master_Out[3061] = \<const0> ;
  assign LOCKSTEP_Master_Out[3062] = \<const0> ;
  assign LOCKSTEP_Master_Out[3063] = \<const0> ;
  assign LOCKSTEP_Master_Out[3064] = \<const0> ;
  assign LOCKSTEP_Master_Out[3065] = \<const0> ;
  assign LOCKSTEP_Master_Out[3066] = \<const0> ;
  assign LOCKSTEP_Master_Out[3067] = \<const0> ;
  assign LOCKSTEP_Master_Out[3068] = \<const0> ;
  assign LOCKSTEP_Master_Out[3069] = \<const0> ;
  assign LOCKSTEP_Master_Out[3070] = \<const0> ;
  assign LOCKSTEP_Master_Out[3071] = \<const0> ;
  assign LOCKSTEP_Master_Out[3072] = \<const0> ;
  assign LOCKSTEP_Master_Out[3073] = \<const0> ;
  assign LOCKSTEP_Master_Out[3074] = \<const0> ;
  assign LOCKSTEP_Master_Out[3075] = \<const0> ;
  assign LOCKSTEP_Master_Out[3076] = \<const0> ;
  assign LOCKSTEP_Master_Out[3077] = \<const0> ;
  assign LOCKSTEP_Master_Out[3078] = \<const0> ;
  assign LOCKSTEP_Master_Out[3079] = \<const0> ;
  assign LOCKSTEP_Master_Out[3080] = \<const0> ;
  assign LOCKSTEP_Master_Out[3081] = \<const0> ;
  assign LOCKSTEP_Master_Out[3082] = \<const0> ;
  assign LOCKSTEP_Master_Out[3083] = \<const0> ;
  assign LOCKSTEP_Master_Out[3084] = \<const0> ;
  assign LOCKSTEP_Master_Out[3085] = \<const0> ;
  assign LOCKSTEP_Master_Out[3086] = \<const0> ;
  assign LOCKSTEP_Master_Out[3087] = \<const0> ;
  assign LOCKSTEP_Master_Out[3088] = \<const0> ;
  assign LOCKSTEP_Master_Out[3089] = \<const0> ;
  assign LOCKSTEP_Master_Out[3090] = \<const0> ;
  assign LOCKSTEP_Master_Out[3091] = \<const0> ;
  assign LOCKSTEP_Master_Out[3092] = \<const0> ;
  assign LOCKSTEP_Master_Out[3093] = \<const0> ;
  assign LOCKSTEP_Master_Out[3094] = \<const0> ;
  assign LOCKSTEP_Master_Out[3095] = \<const0> ;
  assign LOCKSTEP_Master_Out[3096] = \<const0> ;
  assign LOCKSTEP_Master_Out[3097] = \<const0> ;
  assign LOCKSTEP_Master_Out[3098] = \<const0> ;
  assign LOCKSTEP_Master_Out[3099] = \<const0> ;
  assign LOCKSTEP_Master_Out[3100] = \<const0> ;
  assign LOCKSTEP_Master_Out[3101] = \<const0> ;
  assign LOCKSTEP_Master_Out[3102] = \<const0> ;
  assign LOCKSTEP_Master_Out[3103] = \<const0> ;
  assign LOCKSTEP_Master_Out[3104] = \<const0> ;
  assign LOCKSTEP_Master_Out[3105] = \<const0> ;
  assign LOCKSTEP_Master_Out[3106] = \<const0> ;
  assign LOCKSTEP_Master_Out[3107] = \<const0> ;
  assign LOCKSTEP_Master_Out[3108] = \<const0> ;
  assign LOCKSTEP_Master_Out[3109] = \<const0> ;
  assign LOCKSTEP_Master_Out[3110] = \<const0> ;
  assign LOCKSTEP_Master_Out[3111] = \<const0> ;
  assign LOCKSTEP_Master_Out[3112] = \<const0> ;
  assign LOCKSTEP_Master_Out[3113] = \<const0> ;
  assign LOCKSTEP_Master_Out[3114] = \<const0> ;
  assign LOCKSTEP_Master_Out[3115] = \<const0> ;
  assign LOCKSTEP_Master_Out[3116] = \<const0> ;
  assign LOCKSTEP_Master_Out[3117] = \<const0> ;
  assign LOCKSTEP_Master_Out[3118] = \<const0> ;
  assign LOCKSTEP_Master_Out[3119] = \<const0> ;
  assign LOCKSTEP_Master_Out[3120] = \<const0> ;
  assign LOCKSTEP_Master_Out[3121] = \<const0> ;
  assign LOCKSTEP_Master_Out[3122] = \<const0> ;
  assign LOCKSTEP_Master_Out[3123] = \<const0> ;
  assign LOCKSTEP_Master_Out[3124] = \<const0> ;
  assign LOCKSTEP_Master_Out[3125] = \<const0> ;
  assign LOCKSTEP_Master_Out[3126] = \<const0> ;
  assign LOCKSTEP_Master_Out[3127] = \<const0> ;
  assign LOCKSTEP_Master_Out[3128] = \<const0> ;
  assign LOCKSTEP_Master_Out[3129] = \<const0> ;
  assign LOCKSTEP_Master_Out[3130] = \<const0> ;
  assign LOCKSTEP_Master_Out[3131] = \<const0> ;
  assign LOCKSTEP_Master_Out[3132] = \<const0> ;
  assign LOCKSTEP_Master_Out[3133] = \<const0> ;
  assign LOCKSTEP_Master_Out[3134] = \<const0> ;
  assign LOCKSTEP_Master_Out[3135] = \<const0> ;
  assign LOCKSTEP_Master_Out[3136] = \<const0> ;
  assign LOCKSTEP_Master_Out[3137] = \<const0> ;
  assign LOCKSTEP_Master_Out[3138] = \<const0> ;
  assign LOCKSTEP_Master_Out[3139] = \<const0> ;
  assign LOCKSTEP_Master_Out[3140] = \<const0> ;
  assign LOCKSTEP_Master_Out[3141] = \<const0> ;
  assign LOCKSTEP_Master_Out[3142] = \<const0> ;
  assign LOCKSTEP_Master_Out[3143] = \<const0> ;
  assign LOCKSTEP_Master_Out[3144] = \<const0> ;
  assign LOCKSTEP_Master_Out[3145] = \<const0> ;
  assign LOCKSTEP_Master_Out[3146] = \<const0> ;
  assign LOCKSTEP_Master_Out[3147] = \<const0> ;
  assign LOCKSTEP_Master_Out[3148] = \<const0> ;
  assign LOCKSTEP_Master_Out[3149] = \<const0> ;
  assign LOCKSTEP_Master_Out[3150] = \<const0> ;
  assign LOCKSTEP_Master_Out[3151] = \<const0> ;
  assign LOCKSTEP_Master_Out[3152] = \<const0> ;
  assign LOCKSTEP_Master_Out[3153] = \<const0> ;
  assign LOCKSTEP_Master_Out[3154] = \<const0> ;
  assign LOCKSTEP_Master_Out[3155] = \<const0> ;
  assign LOCKSTEP_Master_Out[3156] = \<const0> ;
  assign LOCKSTEP_Master_Out[3157] = \<const0> ;
  assign LOCKSTEP_Master_Out[3158] = \<const0> ;
  assign LOCKSTEP_Master_Out[3159] = \<const0> ;
  assign LOCKSTEP_Master_Out[3160] = \<const0> ;
  assign LOCKSTEP_Master_Out[3161] = \<const0> ;
  assign LOCKSTEP_Master_Out[3162] = \<const0> ;
  assign LOCKSTEP_Master_Out[3163] = \<const0> ;
  assign LOCKSTEP_Master_Out[3164] = \<const0> ;
  assign LOCKSTEP_Master_Out[3165] = \<const0> ;
  assign LOCKSTEP_Master_Out[3166] = \<const0> ;
  assign LOCKSTEP_Master_Out[3167] = \<const0> ;
  assign LOCKSTEP_Master_Out[3168] = \<const0> ;
  assign LOCKSTEP_Master_Out[3169] = \<const0> ;
  assign LOCKSTEP_Master_Out[3170] = \<const0> ;
  assign LOCKSTEP_Master_Out[3171] = \<const0> ;
  assign LOCKSTEP_Master_Out[3172] = \<const0> ;
  assign LOCKSTEP_Master_Out[3173] = \<const0> ;
  assign LOCKSTEP_Master_Out[3174] = \<const0> ;
  assign LOCKSTEP_Master_Out[3175] = \<const0> ;
  assign LOCKSTEP_Master_Out[3176] = \<const0> ;
  assign LOCKSTEP_Master_Out[3177] = \<const0> ;
  assign LOCKSTEP_Master_Out[3178] = \<const0> ;
  assign LOCKSTEP_Master_Out[3179] = \<const0> ;
  assign LOCKSTEP_Master_Out[3180] = \<const0> ;
  assign LOCKSTEP_Master_Out[3181] = \<const0> ;
  assign LOCKSTEP_Master_Out[3182] = \<const0> ;
  assign LOCKSTEP_Master_Out[3183] = \<const0> ;
  assign LOCKSTEP_Master_Out[3184] = \<const0> ;
  assign LOCKSTEP_Master_Out[3185] = \<const0> ;
  assign LOCKSTEP_Master_Out[3186] = \<const0> ;
  assign LOCKSTEP_Master_Out[3187] = \<const0> ;
  assign LOCKSTEP_Master_Out[3188] = \<const0> ;
  assign LOCKSTEP_Master_Out[3189] = \<const0> ;
  assign LOCKSTEP_Master_Out[3190] = \<const0> ;
  assign LOCKSTEP_Master_Out[3191] = \<const0> ;
  assign LOCKSTEP_Master_Out[3192] = \<const0> ;
  assign LOCKSTEP_Master_Out[3193] = \<const0> ;
  assign LOCKSTEP_Master_Out[3194] = \<const0> ;
  assign LOCKSTEP_Master_Out[3195] = \<const0> ;
  assign LOCKSTEP_Master_Out[3196] = \<const0> ;
  assign LOCKSTEP_Master_Out[3197] = \<const0> ;
  assign LOCKSTEP_Master_Out[3198] = \<const0> ;
  assign LOCKSTEP_Master_Out[3199] = \<const0> ;
  assign LOCKSTEP_Master_Out[3200] = \<const0> ;
  assign LOCKSTEP_Master_Out[3201] = \<const0> ;
  assign LOCKSTEP_Master_Out[3202] = \<const0> ;
  assign LOCKSTEP_Master_Out[3203] = \<const0> ;
  assign LOCKSTEP_Master_Out[3204] = \<const0> ;
  assign LOCKSTEP_Master_Out[3205] = \<const0> ;
  assign LOCKSTEP_Master_Out[3206] = \<const0> ;
  assign LOCKSTEP_Master_Out[3207] = \<const0> ;
  assign LOCKSTEP_Master_Out[3208] = \<const0> ;
  assign LOCKSTEP_Master_Out[3209] = \<const0> ;
  assign LOCKSTEP_Master_Out[3210] = \<const0> ;
  assign LOCKSTEP_Master_Out[3211] = \<const0> ;
  assign LOCKSTEP_Master_Out[3212] = \<const0> ;
  assign LOCKSTEP_Master_Out[3213] = \<const0> ;
  assign LOCKSTEP_Master_Out[3214] = \<const0> ;
  assign LOCKSTEP_Master_Out[3215] = \<const0> ;
  assign LOCKSTEP_Master_Out[3216] = \<const0> ;
  assign LOCKSTEP_Master_Out[3217] = \<const0> ;
  assign LOCKSTEP_Master_Out[3218] = \<const0> ;
  assign LOCKSTEP_Master_Out[3219] = \<const0> ;
  assign LOCKSTEP_Master_Out[3220] = \<const0> ;
  assign LOCKSTEP_Master_Out[3221] = \<const0> ;
  assign LOCKSTEP_Master_Out[3222] = \<const0> ;
  assign LOCKSTEP_Master_Out[3223] = \<const0> ;
  assign LOCKSTEP_Master_Out[3224] = \<const0> ;
  assign LOCKSTEP_Master_Out[3225] = \<const0> ;
  assign LOCKSTEP_Master_Out[3226] = \<const0> ;
  assign LOCKSTEP_Master_Out[3227] = \<const0> ;
  assign LOCKSTEP_Master_Out[3228] = \<const0> ;
  assign LOCKSTEP_Master_Out[3229] = \<const0> ;
  assign LOCKSTEP_Master_Out[3230] = \<const0> ;
  assign LOCKSTEP_Master_Out[3231] = \<const0> ;
  assign LOCKSTEP_Master_Out[3232] = \<const0> ;
  assign LOCKSTEP_Master_Out[3233] = \<const0> ;
  assign LOCKSTEP_Master_Out[3234] = \<const0> ;
  assign LOCKSTEP_Master_Out[3235] = \<const0> ;
  assign LOCKSTEP_Master_Out[3236] = \<const0> ;
  assign LOCKSTEP_Master_Out[3237] = \<const0> ;
  assign LOCKSTEP_Master_Out[3238] = \<const0> ;
  assign LOCKSTEP_Master_Out[3239] = \<const0> ;
  assign LOCKSTEP_Master_Out[3240] = \<const0> ;
  assign LOCKSTEP_Master_Out[3241] = \<const0> ;
  assign LOCKSTEP_Master_Out[3242] = \<const0> ;
  assign LOCKSTEP_Master_Out[3243] = \<const0> ;
  assign LOCKSTEP_Master_Out[3244] = \<const0> ;
  assign LOCKSTEP_Master_Out[3245] = \<const0> ;
  assign LOCKSTEP_Master_Out[3246] = \<const0> ;
  assign LOCKSTEP_Master_Out[3247] = \<const0> ;
  assign LOCKSTEP_Master_Out[3248] = \<const0> ;
  assign LOCKSTEP_Master_Out[3249] = \<const0> ;
  assign LOCKSTEP_Master_Out[3250] = \<const0> ;
  assign LOCKSTEP_Master_Out[3251] = \<const0> ;
  assign LOCKSTEP_Master_Out[3252] = \<const0> ;
  assign LOCKSTEP_Master_Out[3253] = \<const0> ;
  assign LOCKSTEP_Master_Out[3254] = \<const0> ;
  assign LOCKSTEP_Master_Out[3255] = \<const0> ;
  assign LOCKSTEP_Master_Out[3256] = \<const0> ;
  assign LOCKSTEP_Master_Out[3257] = \<const0> ;
  assign LOCKSTEP_Master_Out[3258] = \<const0> ;
  assign LOCKSTEP_Master_Out[3259] = \<const0> ;
  assign LOCKSTEP_Master_Out[3260] = \<const0> ;
  assign LOCKSTEP_Master_Out[3261] = \<const0> ;
  assign LOCKSTEP_Master_Out[3262] = \<const0> ;
  assign LOCKSTEP_Master_Out[3263] = \<const0> ;
  assign LOCKSTEP_Master_Out[3264] = \<const0> ;
  assign LOCKSTEP_Master_Out[3265] = \<const0> ;
  assign LOCKSTEP_Master_Out[3266] = \<const0> ;
  assign LOCKSTEP_Master_Out[3267] = \<const0> ;
  assign LOCKSTEP_Master_Out[3268] = \<const0> ;
  assign LOCKSTEP_Master_Out[3269] = \<const0> ;
  assign LOCKSTEP_Master_Out[3270] = \<const0> ;
  assign LOCKSTEP_Master_Out[3271] = \<const0> ;
  assign LOCKSTEP_Master_Out[3272] = \<const0> ;
  assign LOCKSTEP_Master_Out[3273] = \<const0> ;
  assign LOCKSTEP_Master_Out[3274] = \<const0> ;
  assign LOCKSTEP_Master_Out[3275] = \<const0> ;
  assign LOCKSTEP_Master_Out[3276] = \<const0> ;
  assign LOCKSTEP_Master_Out[3277] = \<const0> ;
  assign LOCKSTEP_Master_Out[3278] = \<const0> ;
  assign LOCKSTEP_Master_Out[3279] = \<const0> ;
  assign LOCKSTEP_Master_Out[3280] = \<const0> ;
  assign LOCKSTEP_Master_Out[3281] = \<const0> ;
  assign LOCKSTEP_Master_Out[3282] = \<const0> ;
  assign LOCKSTEP_Master_Out[3283] = \<const0> ;
  assign LOCKSTEP_Master_Out[3284] = \<const0> ;
  assign LOCKSTEP_Master_Out[3285] = \<const0> ;
  assign LOCKSTEP_Master_Out[3286] = \<const0> ;
  assign LOCKSTEP_Master_Out[3287] = \<const0> ;
  assign LOCKSTEP_Master_Out[3288] = \<const0> ;
  assign LOCKSTEP_Master_Out[3289] = \<const0> ;
  assign LOCKSTEP_Master_Out[3290] = \<const0> ;
  assign LOCKSTEP_Master_Out[3291] = \<const0> ;
  assign LOCKSTEP_Master_Out[3292] = \<const0> ;
  assign LOCKSTEP_Master_Out[3293] = \<const0> ;
  assign LOCKSTEP_Master_Out[3294] = \<const0> ;
  assign LOCKSTEP_Master_Out[3295] = \<const0> ;
  assign LOCKSTEP_Master_Out[3296] = \<const0> ;
  assign LOCKSTEP_Master_Out[3297] = \<const0> ;
  assign LOCKSTEP_Master_Out[3298] = \<const0> ;
  assign LOCKSTEP_Master_Out[3299] = \<const0> ;
  assign LOCKSTEP_Master_Out[3300] = \<const0> ;
  assign LOCKSTEP_Master_Out[3301] = \<const0> ;
  assign LOCKSTEP_Master_Out[3302] = \<const0> ;
  assign LOCKSTEP_Master_Out[3303] = \<const0> ;
  assign LOCKSTEP_Master_Out[3304] = \<const0> ;
  assign LOCKSTEP_Master_Out[3305] = \<const0> ;
  assign LOCKSTEP_Master_Out[3306] = \<const0> ;
  assign LOCKSTEP_Master_Out[3307] = \<const0> ;
  assign LOCKSTEP_Master_Out[3308] = \<const0> ;
  assign LOCKSTEP_Master_Out[3309] = \<const0> ;
  assign LOCKSTEP_Master_Out[3310] = \<const0> ;
  assign LOCKSTEP_Master_Out[3311] = \<const0> ;
  assign LOCKSTEP_Master_Out[3312] = \<const0> ;
  assign LOCKSTEP_Master_Out[3313] = \<const0> ;
  assign LOCKSTEP_Master_Out[3314] = \<const0> ;
  assign LOCKSTEP_Master_Out[3315] = \<const0> ;
  assign LOCKSTEP_Master_Out[3316] = \<const0> ;
  assign LOCKSTEP_Master_Out[3317] = \<const0> ;
  assign LOCKSTEP_Master_Out[3318] = \<const0> ;
  assign LOCKSTEP_Master_Out[3319] = \<const0> ;
  assign LOCKSTEP_Master_Out[3320] = \<const0> ;
  assign LOCKSTEP_Master_Out[3321] = \<const0> ;
  assign LOCKSTEP_Master_Out[3322] = \<const0> ;
  assign LOCKSTEP_Master_Out[3323] = \<const0> ;
  assign LOCKSTEP_Master_Out[3324] = \<const0> ;
  assign LOCKSTEP_Master_Out[3325] = \<const0> ;
  assign LOCKSTEP_Master_Out[3326] = \<const0> ;
  assign LOCKSTEP_Master_Out[3327] = \<const0> ;
  assign LOCKSTEP_Master_Out[3328] = \<const0> ;
  assign LOCKSTEP_Master_Out[3329] = \<const0> ;
  assign LOCKSTEP_Master_Out[3330] = \<const0> ;
  assign LOCKSTEP_Master_Out[3331] = \<const0> ;
  assign LOCKSTEP_Master_Out[3332] = \<const0> ;
  assign LOCKSTEP_Master_Out[3333] = \<const0> ;
  assign LOCKSTEP_Master_Out[3334] = \<const0> ;
  assign LOCKSTEP_Master_Out[3335] = \<const0> ;
  assign LOCKSTEP_Master_Out[3336] = \<const0> ;
  assign LOCKSTEP_Master_Out[3337] = \<const0> ;
  assign LOCKSTEP_Master_Out[3338] = \<const0> ;
  assign LOCKSTEP_Master_Out[3339] = \<const0> ;
  assign LOCKSTEP_Master_Out[3340] = \<const0> ;
  assign LOCKSTEP_Master_Out[3341] = \<const0> ;
  assign LOCKSTEP_Master_Out[3342] = \<const0> ;
  assign LOCKSTEP_Master_Out[3343] = \<const0> ;
  assign LOCKSTEP_Master_Out[3344] = \<const0> ;
  assign LOCKSTEP_Master_Out[3345] = \<const0> ;
  assign LOCKSTEP_Master_Out[3346] = \<const0> ;
  assign LOCKSTEP_Master_Out[3347] = \<const0> ;
  assign LOCKSTEP_Master_Out[3348] = \<const0> ;
  assign LOCKSTEP_Master_Out[3349] = \<const0> ;
  assign LOCKSTEP_Master_Out[3350] = \<const0> ;
  assign LOCKSTEP_Master_Out[3351] = \<const0> ;
  assign LOCKSTEP_Master_Out[3352] = \<const0> ;
  assign LOCKSTEP_Master_Out[3353] = \<const0> ;
  assign LOCKSTEP_Master_Out[3354] = \<const0> ;
  assign LOCKSTEP_Master_Out[3355] = \<const0> ;
  assign LOCKSTEP_Master_Out[3356] = \<const0> ;
  assign LOCKSTEP_Master_Out[3357] = \<const0> ;
  assign LOCKSTEP_Master_Out[3358] = \<const0> ;
  assign LOCKSTEP_Master_Out[3359] = \<const0> ;
  assign LOCKSTEP_Master_Out[3360] = \<const0> ;
  assign LOCKSTEP_Master_Out[3361] = \<const0> ;
  assign LOCKSTEP_Master_Out[3362] = \<const0> ;
  assign LOCKSTEP_Master_Out[3363] = \<const0> ;
  assign LOCKSTEP_Master_Out[3364] = \<const0> ;
  assign LOCKSTEP_Master_Out[3365] = \<const0> ;
  assign LOCKSTEP_Master_Out[3366] = \<const0> ;
  assign LOCKSTEP_Master_Out[3367] = \<const0> ;
  assign LOCKSTEP_Master_Out[3368] = \<const0> ;
  assign LOCKSTEP_Master_Out[3369] = \<const0> ;
  assign LOCKSTEP_Master_Out[3370] = \<const0> ;
  assign LOCKSTEP_Master_Out[3371] = \<const0> ;
  assign LOCKSTEP_Master_Out[3372] = \<const0> ;
  assign LOCKSTEP_Master_Out[3373] = \<const0> ;
  assign LOCKSTEP_Master_Out[3374] = \<const0> ;
  assign LOCKSTEP_Master_Out[3375] = \<const0> ;
  assign LOCKSTEP_Master_Out[3376] = \<const0> ;
  assign LOCKSTEP_Master_Out[3377] = \<const0> ;
  assign LOCKSTEP_Master_Out[3378] = \<const0> ;
  assign LOCKSTEP_Master_Out[3379] = \<const0> ;
  assign LOCKSTEP_Master_Out[3380] = \<const0> ;
  assign LOCKSTEP_Master_Out[3381] = \<const0> ;
  assign LOCKSTEP_Master_Out[3382] = \<const0> ;
  assign LOCKSTEP_Master_Out[3383] = \<const0> ;
  assign LOCKSTEP_Master_Out[3384] = \<const0> ;
  assign LOCKSTEP_Master_Out[3385] = \<const0> ;
  assign LOCKSTEP_Master_Out[3386] = \<const0> ;
  assign LOCKSTEP_Master_Out[3387] = \<const0> ;
  assign LOCKSTEP_Master_Out[3388] = \<const0> ;
  assign LOCKSTEP_Master_Out[3389] = \<const0> ;
  assign LOCKSTEP_Master_Out[3390] = \<const0> ;
  assign LOCKSTEP_Master_Out[3391] = \<const0> ;
  assign LOCKSTEP_Master_Out[3392] = \<const0> ;
  assign LOCKSTEP_Master_Out[3393] = \<const0> ;
  assign LOCKSTEP_Master_Out[3394] = \<const0> ;
  assign LOCKSTEP_Master_Out[3395] = \<const0> ;
  assign LOCKSTEP_Master_Out[3396] = \<const0> ;
  assign LOCKSTEP_Master_Out[3397] = \<const0> ;
  assign LOCKSTEP_Master_Out[3398] = \<const0> ;
  assign LOCKSTEP_Master_Out[3399] = \<const0> ;
  assign LOCKSTEP_Master_Out[3400] = \<const0> ;
  assign LOCKSTEP_Master_Out[3401] = \<const0> ;
  assign LOCKSTEP_Master_Out[3402] = \<const0> ;
  assign LOCKSTEP_Master_Out[3403] = \<const0> ;
  assign LOCKSTEP_Master_Out[3404] = \<const0> ;
  assign LOCKSTEP_Master_Out[3405] = \<const0> ;
  assign LOCKSTEP_Master_Out[3406] = \<const0> ;
  assign LOCKSTEP_Master_Out[3407] = \<const0> ;
  assign LOCKSTEP_Master_Out[3408] = \<const0> ;
  assign LOCKSTEP_Master_Out[3409] = \<const0> ;
  assign LOCKSTEP_Master_Out[3410] = \<const0> ;
  assign LOCKSTEP_Master_Out[3411] = \<const0> ;
  assign LOCKSTEP_Master_Out[3412] = \<const0> ;
  assign LOCKSTEP_Master_Out[3413] = \<const0> ;
  assign LOCKSTEP_Master_Out[3414] = \<const0> ;
  assign LOCKSTEP_Master_Out[3415] = \<const0> ;
  assign LOCKSTEP_Master_Out[3416] = \<const0> ;
  assign LOCKSTEP_Master_Out[3417] = \<const0> ;
  assign LOCKSTEP_Master_Out[3418] = \<const0> ;
  assign LOCKSTEP_Master_Out[3419] = \<const0> ;
  assign LOCKSTEP_Master_Out[3420] = \<const0> ;
  assign LOCKSTEP_Master_Out[3421] = \<const0> ;
  assign LOCKSTEP_Master_Out[3422] = \<const0> ;
  assign LOCKSTEP_Master_Out[3423] = \<const0> ;
  assign LOCKSTEP_Master_Out[3424] = \<const0> ;
  assign LOCKSTEP_Master_Out[3425] = \<const0> ;
  assign LOCKSTEP_Master_Out[3426] = \<const0> ;
  assign LOCKSTEP_Master_Out[3427] = \<const0> ;
  assign LOCKSTEP_Master_Out[3428] = \<const0> ;
  assign LOCKSTEP_Master_Out[3429] = \<const0> ;
  assign LOCKSTEP_Master_Out[3430] = \<const0> ;
  assign LOCKSTEP_Master_Out[3431] = \<const0> ;
  assign LOCKSTEP_Master_Out[3432] = \<const0> ;
  assign LOCKSTEP_Master_Out[3433] = \<const0> ;
  assign LOCKSTEP_Master_Out[3434] = \<const0> ;
  assign LOCKSTEP_Master_Out[3435] = \<const0> ;
  assign LOCKSTEP_Master_Out[3436] = \<const0> ;
  assign LOCKSTEP_Master_Out[3437] = \<const0> ;
  assign LOCKSTEP_Master_Out[3438] = \<const0> ;
  assign LOCKSTEP_Master_Out[3439] = \<const0> ;
  assign LOCKSTEP_Master_Out[3440] = \<const0> ;
  assign LOCKSTEP_Master_Out[3441] = \<const0> ;
  assign LOCKSTEP_Master_Out[3442] = \<const0> ;
  assign LOCKSTEP_Master_Out[3443] = \<const0> ;
  assign LOCKSTEP_Master_Out[3444] = \<const0> ;
  assign LOCKSTEP_Master_Out[3445] = \<const0> ;
  assign LOCKSTEP_Master_Out[3446] = \<const0> ;
  assign LOCKSTEP_Master_Out[3447] = \<const0> ;
  assign LOCKSTEP_Master_Out[3448] = \<const0> ;
  assign LOCKSTEP_Master_Out[3449] = \<const0> ;
  assign LOCKSTEP_Master_Out[3450] = \<const0> ;
  assign LOCKSTEP_Master_Out[3451] = \<const0> ;
  assign LOCKSTEP_Master_Out[3452] = \<const0> ;
  assign LOCKSTEP_Master_Out[3453] = \<const0> ;
  assign LOCKSTEP_Master_Out[3454] = \<const0> ;
  assign LOCKSTEP_Master_Out[3455] = \<const0> ;
  assign LOCKSTEP_Master_Out[3456] = \<const0> ;
  assign LOCKSTEP_Master_Out[3457] = \<const0> ;
  assign LOCKSTEP_Master_Out[3458] = \<const0> ;
  assign LOCKSTEP_Master_Out[3459] = \<const0> ;
  assign LOCKSTEP_Master_Out[3460] = \<const0> ;
  assign LOCKSTEP_Master_Out[3461] = \<const0> ;
  assign LOCKSTEP_Master_Out[3462] = \<const0> ;
  assign LOCKSTEP_Master_Out[3463] = \<const0> ;
  assign LOCKSTEP_Master_Out[3464] = \<const0> ;
  assign LOCKSTEP_Master_Out[3465] = \<const0> ;
  assign LOCKSTEP_Master_Out[3466] = \<const0> ;
  assign LOCKSTEP_Master_Out[3467] = \<const0> ;
  assign LOCKSTEP_Master_Out[3468] = \<const0> ;
  assign LOCKSTEP_Master_Out[3469] = \<const0> ;
  assign LOCKSTEP_Master_Out[3470] = \<const0> ;
  assign LOCKSTEP_Master_Out[3471] = \<const0> ;
  assign LOCKSTEP_Master_Out[3472] = \<const0> ;
  assign LOCKSTEP_Master_Out[3473] = \<const0> ;
  assign LOCKSTEP_Master_Out[3474] = \<const0> ;
  assign LOCKSTEP_Master_Out[3475] = \<const0> ;
  assign LOCKSTEP_Master_Out[3476] = \<const0> ;
  assign LOCKSTEP_Master_Out[3477] = \<const0> ;
  assign LOCKSTEP_Master_Out[3478] = \<const0> ;
  assign LOCKSTEP_Master_Out[3479] = \<const0> ;
  assign LOCKSTEP_Master_Out[3480] = \<const0> ;
  assign LOCKSTEP_Master_Out[3481] = \<const0> ;
  assign LOCKSTEP_Master_Out[3482] = \<const0> ;
  assign LOCKSTEP_Master_Out[3483] = \<const0> ;
  assign LOCKSTEP_Master_Out[3484] = \<const0> ;
  assign LOCKSTEP_Master_Out[3485] = \<const0> ;
  assign LOCKSTEP_Master_Out[3486] = \<const0> ;
  assign LOCKSTEP_Master_Out[3487] = \<const0> ;
  assign LOCKSTEP_Master_Out[3488] = \<const0> ;
  assign LOCKSTEP_Master_Out[3489] = \<const0> ;
  assign LOCKSTEP_Master_Out[3490] = \<const0> ;
  assign LOCKSTEP_Master_Out[3491] = \<const0> ;
  assign LOCKSTEP_Master_Out[3492] = \<const0> ;
  assign LOCKSTEP_Master_Out[3493] = \<const0> ;
  assign LOCKSTEP_Master_Out[3494] = \<const0> ;
  assign LOCKSTEP_Master_Out[3495] = \<const0> ;
  assign LOCKSTEP_Master_Out[3496] = \<const0> ;
  assign LOCKSTEP_Master_Out[3497] = \<const0> ;
  assign LOCKSTEP_Master_Out[3498] = \<const0> ;
  assign LOCKSTEP_Master_Out[3499] = \<const0> ;
  assign LOCKSTEP_Master_Out[3500] = \<const0> ;
  assign LOCKSTEP_Master_Out[3501] = \<const0> ;
  assign LOCKSTEP_Master_Out[3502] = \<const0> ;
  assign LOCKSTEP_Master_Out[3503] = \<const0> ;
  assign LOCKSTEP_Master_Out[3504] = \<const0> ;
  assign LOCKSTEP_Master_Out[3505] = \<const0> ;
  assign LOCKSTEP_Master_Out[3506] = \<const0> ;
  assign LOCKSTEP_Master_Out[3507] = \<const0> ;
  assign LOCKSTEP_Master_Out[3508] = \<const0> ;
  assign LOCKSTEP_Master_Out[3509] = \<const0> ;
  assign LOCKSTEP_Master_Out[3510] = \<const0> ;
  assign LOCKSTEP_Master_Out[3511] = \<const0> ;
  assign LOCKSTEP_Master_Out[3512] = \<const0> ;
  assign LOCKSTEP_Master_Out[3513] = \<const0> ;
  assign LOCKSTEP_Master_Out[3514] = \<const0> ;
  assign LOCKSTEP_Master_Out[3515] = \<const0> ;
  assign LOCKSTEP_Master_Out[3516] = \<const0> ;
  assign LOCKSTEP_Master_Out[3517] = \<const0> ;
  assign LOCKSTEP_Master_Out[3518] = \<const0> ;
  assign LOCKSTEP_Master_Out[3519] = \<const0> ;
  assign LOCKSTEP_Master_Out[3520] = \<const0> ;
  assign LOCKSTEP_Master_Out[3521] = \<const0> ;
  assign LOCKSTEP_Master_Out[3522] = \<const0> ;
  assign LOCKSTEP_Master_Out[3523] = \<const0> ;
  assign LOCKSTEP_Master_Out[3524] = \<const0> ;
  assign LOCKSTEP_Master_Out[3525] = \<const0> ;
  assign LOCKSTEP_Master_Out[3526] = \<const0> ;
  assign LOCKSTEP_Master_Out[3527] = \<const0> ;
  assign LOCKSTEP_Master_Out[3528] = \<const0> ;
  assign LOCKSTEP_Master_Out[3529] = \<const0> ;
  assign LOCKSTEP_Master_Out[3530] = \<const0> ;
  assign LOCKSTEP_Master_Out[3531] = \<const0> ;
  assign LOCKSTEP_Master_Out[3532] = \<const0> ;
  assign LOCKSTEP_Master_Out[3533] = \<const0> ;
  assign LOCKSTEP_Master_Out[3534] = \<const0> ;
  assign LOCKSTEP_Master_Out[3535] = \<const0> ;
  assign LOCKSTEP_Master_Out[3536] = \<const0> ;
  assign LOCKSTEP_Master_Out[3537] = \<const0> ;
  assign LOCKSTEP_Master_Out[3538] = \<const0> ;
  assign LOCKSTEP_Master_Out[3539] = \<const0> ;
  assign LOCKSTEP_Master_Out[3540] = \<const0> ;
  assign LOCKSTEP_Master_Out[3541] = \<const0> ;
  assign LOCKSTEP_Master_Out[3542] = \<const0> ;
  assign LOCKSTEP_Master_Out[3543] = \<const0> ;
  assign LOCKSTEP_Master_Out[3544] = \<const0> ;
  assign LOCKSTEP_Master_Out[3545] = \<const0> ;
  assign LOCKSTEP_Master_Out[3546] = \<const0> ;
  assign LOCKSTEP_Master_Out[3547] = \<const0> ;
  assign LOCKSTEP_Master_Out[3548] = \<const0> ;
  assign LOCKSTEP_Master_Out[3549] = \<const0> ;
  assign LOCKSTEP_Master_Out[3550] = \<const0> ;
  assign LOCKSTEP_Master_Out[3551] = \<const0> ;
  assign LOCKSTEP_Master_Out[3552] = \<const0> ;
  assign LOCKSTEP_Master_Out[3553] = \<const0> ;
  assign LOCKSTEP_Master_Out[3554] = \<const0> ;
  assign LOCKSTEP_Master_Out[3555] = \<const0> ;
  assign LOCKSTEP_Master_Out[3556] = \<const0> ;
  assign LOCKSTEP_Master_Out[3557] = \<const0> ;
  assign LOCKSTEP_Master_Out[3558] = \<const0> ;
  assign LOCKSTEP_Master_Out[3559] = \<const0> ;
  assign LOCKSTEP_Master_Out[3560] = \<const0> ;
  assign LOCKSTEP_Master_Out[3561] = \<const0> ;
  assign LOCKSTEP_Master_Out[3562] = \<const0> ;
  assign LOCKSTEP_Master_Out[3563] = \<const0> ;
  assign LOCKSTEP_Master_Out[3564] = \<const0> ;
  assign LOCKSTEP_Master_Out[3565] = \<const0> ;
  assign LOCKSTEP_Master_Out[3566] = \<const0> ;
  assign LOCKSTEP_Master_Out[3567] = \<const0> ;
  assign LOCKSTEP_Master_Out[3568] = \<const0> ;
  assign LOCKSTEP_Master_Out[3569] = \<const0> ;
  assign LOCKSTEP_Master_Out[3570] = \<const0> ;
  assign LOCKSTEP_Master_Out[3571] = \<const0> ;
  assign LOCKSTEP_Master_Out[3572] = \<const0> ;
  assign LOCKSTEP_Master_Out[3573] = \<const0> ;
  assign LOCKSTEP_Master_Out[3574] = \<const0> ;
  assign LOCKSTEP_Master_Out[3575] = \<const0> ;
  assign LOCKSTEP_Master_Out[3576] = \<const0> ;
  assign LOCKSTEP_Master_Out[3577] = \<const0> ;
  assign LOCKSTEP_Master_Out[3578] = \<const0> ;
  assign LOCKSTEP_Master_Out[3579] = \<const0> ;
  assign LOCKSTEP_Master_Out[3580] = \<const0> ;
  assign LOCKSTEP_Master_Out[3581] = \<const0> ;
  assign LOCKSTEP_Master_Out[3582] = \<const0> ;
  assign LOCKSTEP_Master_Out[3583] = \<const0> ;
  assign LOCKSTEP_Master_Out[3584] = \<const0> ;
  assign LOCKSTEP_Master_Out[3585] = \<const0> ;
  assign LOCKSTEP_Master_Out[3586] = \<const0> ;
  assign LOCKSTEP_Master_Out[3587] = \<const0> ;
  assign LOCKSTEP_Master_Out[3588] = \<const0> ;
  assign LOCKSTEP_Master_Out[3589] = \<const0> ;
  assign LOCKSTEP_Master_Out[3590] = \<const0> ;
  assign LOCKSTEP_Master_Out[3591] = \<const0> ;
  assign LOCKSTEP_Master_Out[3592] = \<const0> ;
  assign LOCKSTEP_Master_Out[3593] = \<const0> ;
  assign LOCKSTEP_Master_Out[3594] = \<const0> ;
  assign LOCKSTEP_Master_Out[3595] = \<const0> ;
  assign LOCKSTEP_Master_Out[3596] = \<const0> ;
  assign LOCKSTEP_Master_Out[3597] = \<const0> ;
  assign LOCKSTEP_Master_Out[3598] = \<const0> ;
  assign LOCKSTEP_Master_Out[3599] = \<const0> ;
  assign LOCKSTEP_Master_Out[3600] = \<const0> ;
  assign LOCKSTEP_Master_Out[3601] = \<const0> ;
  assign LOCKSTEP_Master_Out[3602] = \<const0> ;
  assign LOCKSTEP_Master_Out[3603] = \<const0> ;
  assign LOCKSTEP_Master_Out[3604] = \<const0> ;
  assign LOCKSTEP_Master_Out[3605] = \<const0> ;
  assign LOCKSTEP_Master_Out[3606] = \<const0> ;
  assign LOCKSTEP_Master_Out[3607] = \<const0> ;
  assign LOCKSTEP_Master_Out[3608] = \<const0> ;
  assign LOCKSTEP_Master_Out[3609] = \<const0> ;
  assign LOCKSTEP_Master_Out[3610] = \<const0> ;
  assign LOCKSTEP_Master_Out[3611] = \<const0> ;
  assign LOCKSTEP_Master_Out[3612] = \<const0> ;
  assign LOCKSTEP_Master_Out[3613] = \<const0> ;
  assign LOCKSTEP_Master_Out[3614] = \<const0> ;
  assign LOCKSTEP_Master_Out[3615] = \<const0> ;
  assign LOCKSTEP_Master_Out[3616] = \<const0> ;
  assign LOCKSTEP_Master_Out[3617] = \<const0> ;
  assign LOCKSTEP_Master_Out[3618] = \<const0> ;
  assign LOCKSTEP_Master_Out[3619] = \<const0> ;
  assign LOCKSTEP_Master_Out[3620] = \<const0> ;
  assign LOCKSTEP_Master_Out[3621] = \<const0> ;
  assign LOCKSTEP_Master_Out[3622] = \<const0> ;
  assign LOCKSTEP_Master_Out[3623] = \<const0> ;
  assign LOCKSTEP_Master_Out[3624] = \<const0> ;
  assign LOCKSTEP_Master_Out[3625] = \<const0> ;
  assign LOCKSTEP_Master_Out[3626] = \<const0> ;
  assign LOCKSTEP_Master_Out[3627] = \<const0> ;
  assign LOCKSTEP_Master_Out[3628] = \<const0> ;
  assign LOCKSTEP_Master_Out[3629] = \<const0> ;
  assign LOCKSTEP_Master_Out[3630] = \<const0> ;
  assign LOCKSTEP_Master_Out[3631] = \<const0> ;
  assign LOCKSTEP_Master_Out[3632] = \<const0> ;
  assign LOCKSTEP_Master_Out[3633] = \<const0> ;
  assign LOCKSTEP_Master_Out[3634] = \<const0> ;
  assign LOCKSTEP_Master_Out[3635] = \<const0> ;
  assign LOCKSTEP_Master_Out[3636] = \<const0> ;
  assign LOCKSTEP_Master_Out[3637] = \<const0> ;
  assign LOCKSTEP_Master_Out[3638] = \<const0> ;
  assign LOCKSTEP_Master_Out[3639] = \<const0> ;
  assign LOCKSTEP_Master_Out[3640] = \<const0> ;
  assign LOCKSTEP_Master_Out[3641] = \<const0> ;
  assign LOCKSTEP_Master_Out[3642] = \<const0> ;
  assign LOCKSTEP_Master_Out[3643] = \<const0> ;
  assign LOCKSTEP_Master_Out[3644] = \<const0> ;
  assign LOCKSTEP_Master_Out[3645] = \<const0> ;
  assign LOCKSTEP_Master_Out[3646] = \<const0> ;
  assign LOCKSTEP_Master_Out[3647] = \<const0> ;
  assign LOCKSTEP_Master_Out[3648] = \<const0> ;
  assign LOCKSTEP_Master_Out[3649] = \<const0> ;
  assign LOCKSTEP_Master_Out[3650] = \<const0> ;
  assign LOCKSTEP_Master_Out[3651] = \<const0> ;
  assign LOCKSTEP_Master_Out[3652] = \<const0> ;
  assign LOCKSTEP_Master_Out[3653] = \<const0> ;
  assign LOCKSTEP_Master_Out[3654] = \<const0> ;
  assign LOCKSTEP_Master_Out[3655] = \<const0> ;
  assign LOCKSTEP_Master_Out[3656] = \<const0> ;
  assign LOCKSTEP_Master_Out[3657] = \<const0> ;
  assign LOCKSTEP_Master_Out[3658] = \<const0> ;
  assign LOCKSTEP_Master_Out[3659] = \<const0> ;
  assign LOCKSTEP_Master_Out[3660] = \<const0> ;
  assign LOCKSTEP_Master_Out[3661] = \<const0> ;
  assign LOCKSTEP_Master_Out[3662] = \<const0> ;
  assign LOCKSTEP_Master_Out[3663] = \<const0> ;
  assign LOCKSTEP_Master_Out[3664] = \<const0> ;
  assign LOCKSTEP_Master_Out[3665] = \<const0> ;
  assign LOCKSTEP_Master_Out[3666] = \<const0> ;
  assign LOCKSTEP_Master_Out[3667] = \<const0> ;
  assign LOCKSTEP_Master_Out[3668] = \<const0> ;
  assign LOCKSTEP_Master_Out[3669] = \<const0> ;
  assign LOCKSTEP_Master_Out[3670] = \<const0> ;
  assign LOCKSTEP_Master_Out[3671] = \<const0> ;
  assign LOCKSTEP_Master_Out[3672] = \<const0> ;
  assign LOCKSTEP_Master_Out[3673] = \<const0> ;
  assign LOCKSTEP_Master_Out[3674] = \<const0> ;
  assign LOCKSTEP_Master_Out[3675] = \<const0> ;
  assign LOCKSTEP_Master_Out[3676] = \<const0> ;
  assign LOCKSTEP_Master_Out[3677] = \<const0> ;
  assign LOCKSTEP_Master_Out[3678] = \<const0> ;
  assign LOCKSTEP_Master_Out[3679] = \<const0> ;
  assign LOCKSTEP_Master_Out[3680] = \<const0> ;
  assign LOCKSTEP_Master_Out[3681] = \<const0> ;
  assign LOCKSTEP_Master_Out[3682] = \<const0> ;
  assign LOCKSTEP_Master_Out[3683] = \<const0> ;
  assign LOCKSTEP_Master_Out[3684] = \<const0> ;
  assign LOCKSTEP_Master_Out[3685] = \<const0> ;
  assign LOCKSTEP_Master_Out[3686] = \<const0> ;
  assign LOCKSTEP_Master_Out[3687] = \<const0> ;
  assign LOCKSTEP_Master_Out[3688] = \<const0> ;
  assign LOCKSTEP_Master_Out[3689] = \<const0> ;
  assign LOCKSTEP_Master_Out[3690] = \<const0> ;
  assign LOCKSTEP_Master_Out[3691] = \<const0> ;
  assign LOCKSTEP_Master_Out[3692] = \<const0> ;
  assign LOCKSTEP_Master_Out[3693] = \<const0> ;
  assign LOCKSTEP_Master_Out[3694] = \<const0> ;
  assign LOCKSTEP_Master_Out[3695] = \<const0> ;
  assign LOCKSTEP_Master_Out[3696] = \<const0> ;
  assign LOCKSTEP_Master_Out[3697] = \<const0> ;
  assign LOCKSTEP_Master_Out[3698] = \<const0> ;
  assign LOCKSTEP_Master_Out[3699] = \<const0> ;
  assign LOCKSTEP_Master_Out[3700] = \<const0> ;
  assign LOCKSTEP_Master_Out[3701] = \<const0> ;
  assign LOCKSTEP_Master_Out[3702] = \<const0> ;
  assign LOCKSTEP_Master_Out[3703] = \<const0> ;
  assign LOCKSTEP_Master_Out[3704] = \<const0> ;
  assign LOCKSTEP_Master_Out[3705] = \<const0> ;
  assign LOCKSTEP_Master_Out[3706] = \<const0> ;
  assign LOCKSTEP_Master_Out[3707] = \<const0> ;
  assign LOCKSTEP_Master_Out[3708] = \<const0> ;
  assign LOCKSTEP_Master_Out[3709] = \<const0> ;
  assign LOCKSTEP_Master_Out[3710] = \<const0> ;
  assign LOCKSTEP_Master_Out[3711] = \<const0> ;
  assign LOCKSTEP_Master_Out[3712] = \<const0> ;
  assign LOCKSTEP_Master_Out[3713] = \<const0> ;
  assign LOCKSTEP_Master_Out[3714] = \<const0> ;
  assign LOCKSTEP_Master_Out[3715] = \<const0> ;
  assign LOCKSTEP_Master_Out[3716] = \<const0> ;
  assign LOCKSTEP_Master_Out[3717] = \<const0> ;
  assign LOCKSTEP_Master_Out[3718] = \<const0> ;
  assign LOCKSTEP_Master_Out[3719] = \<const0> ;
  assign LOCKSTEP_Master_Out[3720] = \<const0> ;
  assign LOCKSTEP_Master_Out[3721] = \<const0> ;
  assign LOCKSTEP_Master_Out[3722] = \<const0> ;
  assign LOCKSTEP_Master_Out[3723] = \<const0> ;
  assign LOCKSTEP_Master_Out[3724] = \<const0> ;
  assign LOCKSTEP_Master_Out[3725] = \<const0> ;
  assign LOCKSTEP_Master_Out[3726] = \<const0> ;
  assign LOCKSTEP_Master_Out[3727] = \<const0> ;
  assign LOCKSTEP_Master_Out[3728] = \<const0> ;
  assign LOCKSTEP_Master_Out[3729] = \<const0> ;
  assign LOCKSTEP_Master_Out[3730] = \<const0> ;
  assign LOCKSTEP_Master_Out[3731] = \<const0> ;
  assign LOCKSTEP_Master_Out[3732] = \<const0> ;
  assign LOCKSTEP_Master_Out[3733] = \<const0> ;
  assign LOCKSTEP_Master_Out[3734] = \<const0> ;
  assign LOCKSTEP_Master_Out[3735] = \<const0> ;
  assign LOCKSTEP_Master_Out[3736] = \<const0> ;
  assign LOCKSTEP_Master_Out[3737] = \<const0> ;
  assign LOCKSTEP_Master_Out[3738] = \<const0> ;
  assign LOCKSTEP_Master_Out[3739] = \<const0> ;
  assign LOCKSTEP_Master_Out[3740] = \<const0> ;
  assign LOCKSTEP_Master_Out[3741] = \<const0> ;
  assign LOCKSTEP_Master_Out[3742] = \<const0> ;
  assign LOCKSTEP_Master_Out[3743] = \<const0> ;
  assign LOCKSTEP_Master_Out[3744] = \<const0> ;
  assign LOCKSTEP_Master_Out[3745] = \<const0> ;
  assign LOCKSTEP_Master_Out[3746] = \<const0> ;
  assign LOCKSTEP_Master_Out[3747] = \<const0> ;
  assign LOCKSTEP_Master_Out[3748] = \<const0> ;
  assign LOCKSTEP_Master_Out[3749] = \<const0> ;
  assign LOCKSTEP_Master_Out[3750] = \<const0> ;
  assign LOCKSTEP_Master_Out[3751] = \<const0> ;
  assign LOCKSTEP_Master_Out[3752] = \<const0> ;
  assign LOCKSTEP_Master_Out[3753] = \<const0> ;
  assign LOCKSTEP_Master_Out[3754] = \<const0> ;
  assign LOCKSTEP_Master_Out[3755] = \<const0> ;
  assign LOCKSTEP_Master_Out[3756] = \<const0> ;
  assign LOCKSTEP_Master_Out[3757] = \<const0> ;
  assign LOCKSTEP_Master_Out[3758] = \<const0> ;
  assign LOCKSTEP_Master_Out[3759] = \<const0> ;
  assign LOCKSTEP_Master_Out[3760] = \<const0> ;
  assign LOCKSTEP_Master_Out[3761] = \<const0> ;
  assign LOCKSTEP_Master_Out[3762] = \<const0> ;
  assign LOCKSTEP_Master_Out[3763] = \<const0> ;
  assign LOCKSTEP_Master_Out[3764] = \<const0> ;
  assign LOCKSTEP_Master_Out[3765] = \<const0> ;
  assign LOCKSTEP_Master_Out[3766] = \<const0> ;
  assign LOCKSTEP_Master_Out[3767] = \<const0> ;
  assign LOCKSTEP_Master_Out[3768] = \<const0> ;
  assign LOCKSTEP_Master_Out[3769] = \<const0> ;
  assign LOCKSTEP_Master_Out[3770] = \<const0> ;
  assign LOCKSTEP_Master_Out[3771] = \<const0> ;
  assign LOCKSTEP_Master_Out[3772] = \<const0> ;
  assign LOCKSTEP_Master_Out[3773] = \<const0> ;
  assign LOCKSTEP_Master_Out[3774] = \<const0> ;
  assign LOCKSTEP_Master_Out[3775] = \<const0> ;
  assign LOCKSTEP_Master_Out[3776] = \<const0> ;
  assign LOCKSTEP_Master_Out[3777] = \<const0> ;
  assign LOCKSTEP_Master_Out[3778] = \<const0> ;
  assign LOCKSTEP_Master_Out[3779] = \<const0> ;
  assign LOCKSTEP_Master_Out[3780] = \<const0> ;
  assign LOCKSTEP_Master_Out[3781] = \<const0> ;
  assign LOCKSTEP_Master_Out[3782] = \<const0> ;
  assign LOCKSTEP_Master_Out[3783] = \<const0> ;
  assign LOCKSTEP_Master_Out[3784] = \<const0> ;
  assign LOCKSTEP_Master_Out[3785] = \<const0> ;
  assign LOCKSTEP_Master_Out[3786] = \<const0> ;
  assign LOCKSTEP_Master_Out[3787] = \<const0> ;
  assign LOCKSTEP_Master_Out[3788] = \<const0> ;
  assign LOCKSTEP_Master_Out[3789] = \<const0> ;
  assign LOCKSTEP_Master_Out[3790] = \<const0> ;
  assign LOCKSTEP_Master_Out[3791] = \<const0> ;
  assign LOCKSTEP_Master_Out[3792] = \<const0> ;
  assign LOCKSTEP_Master_Out[3793] = \<const0> ;
  assign LOCKSTEP_Master_Out[3794] = \<const0> ;
  assign LOCKSTEP_Master_Out[3795] = \<const0> ;
  assign LOCKSTEP_Master_Out[3796] = \<const0> ;
  assign LOCKSTEP_Master_Out[3797] = \<const0> ;
  assign LOCKSTEP_Master_Out[3798] = \<const0> ;
  assign LOCKSTEP_Master_Out[3799] = \<const0> ;
  assign LOCKSTEP_Master_Out[3800] = \<const0> ;
  assign LOCKSTEP_Master_Out[3801] = \<const0> ;
  assign LOCKSTEP_Master_Out[3802] = \<const0> ;
  assign LOCKSTEP_Master_Out[3803] = \<const0> ;
  assign LOCKSTEP_Master_Out[3804] = \<const0> ;
  assign LOCKSTEP_Master_Out[3805] = \<const0> ;
  assign LOCKSTEP_Master_Out[3806] = \<const0> ;
  assign LOCKSTEP_Master_Out[3807] = \<const0> ;
  assign LOCKSTEP_Master_Out[3808] = \<const0> ;
  assign LOCKSTEP_Master_Out[3809] = \<const0> ;
  assign LOCKSTEP_Master_Out[3810] = \<const0> ;
  assign LOCKSTEP_Master_Out[3811] = \<const0> ;
  assign LOCKSTEP_Master_Out[3812] = \<const0> ;
  assign LOCKSTEP_Master_Out[3813] = \<const0> ;
  assign LOCKSTEP_Master_Out[3814] = \<const0> ;
  assign LOCKSTEP_Master_Out[3815] = \<const0> ;
  assign LOCKSTEP_Master_Out[3816] = \<const0> ;
  assign LOCKSTEP_Master_Out[3817] = \<const0> ;
  assign LOCKSTEP_Master_Out[3818] = \<const0> ;
  assign LOCKSTEP_Master_Out[3819] = \<const0> ;
  assign LOCKSTEP_Master_Out[3820] = \<const0> ;
  assign LOCKSTEP_Master_Out[3821] = \<const0> ;
  assign LOCKSTEP_Master_Out[3822] = \<const0> ;
  assign LOCKSTEP_Master_Out[3823] = \<const0> ;
  assign LOCKSTEP_Master_Out[3824] = \<const0> ;
  assign LOCKSTEP_Master_Out[3825] = \<const0> ;
  assign LOCKSTEP_Master_Out[3826] = \<const0> ;
  assign LOCKSTEP_Master_Out[3827] = \<const0> ;
  assign LOCKSTEP_Master_Out[3828] = \<const0> ;
  assign LOCKSTEP_Master_Out[3829] = \<const0> ;
  assign LOCKSTEP_Master_Out[3830] = \<const0> ;
  assign LOCKSTEP_Master_Out[3831] = \<const0> ;
  assign LOCKSTEP_Master_Out[3832] = \<const0> ;
  assign LOCKSTEP_Master_Out[3833] = \<const0> ;
  assign LOCKSTEP_Master_Out[3834] = \<const0> ;
  assign LOCKSTEP_Master_Out[3835] = \<const0> ;
  assign LOCKSTEP_Master_Out[3836] = \<const0> ;
  assign LOCKSTEP_Master_Out[3837] = \<const0> ;
  assign LOCKSTEP_Master_Out[3838] = \<const0> ;
  assign LOCKSTEP_Master_Out[3839] = \<const0> ;
  assign LOCKSTEP_Master_Out[3840] = \<const0> ;
  assign LOCKSTEP_Master_Out[3841] = \<const0> ;
  assign LOCKSTEP_Master_Out[3842] = \<const0> ;
  assign LOCKSTEP_Master_Out[3843] = \<const0> ;
  assign LOCKSTEP_Master_Out[3844] = \<const0> ;
  assign LOCKSTEP_Master_Out[3845] = \<const0> ;
  assign LOCKSTEP_Master_Out[3846] = \<const0> ;
  assign LOCKSTEP_Master_Out[3847] = \<const0> ;
  assign LOCKSTEP_Master_Out[3848] = \<const0> ;
  assign LOCKSTEP_Master_Out[3849] = \<const0> ;
  assign LOCKSTEP_Master_Out[3850] = \<const0> ;
  assign LOCKSTEP_Master_Out[3851] = \<const0> ;
  assign LOCKSTEP_Master_Out[3852] = \<const0> ;
  assign LOCKSTEP_Master_Out[3853] = \<const0> ;
  assign LOCKSTEP_Master_Out[3854] = \<const0> ;
  assign LOCKSTEP_Master_Out[3855] = \<const0> ;
  assign LOCKSTEP_Master_Out[3856] = \<const0> ;
  assign LOCKSTEP_Master_Out[3857] = \<const0> ;
  assign LOCKSTEP_Master_Out[3858] = \<const0> ;
  assign LOCKSTEP_Master_Out[3859] = \<const0> ;
  assign LOCKSTEP_Master_Out[3860] = \<const0> ;
  assign LOCKSTEP_Master_Out[3861] = \<const0> ;
  assign LOCKSTEP_Master_Out[3862] = \<const0> ;
  assign LOCKSTEP_Master_Out[3863] = \<const0> ;
  assign LOCKSTEP_Master_Out[3864] = \<const0> ;
  assign LOCKSTEP_Master_Out[3865] = \<const0> ;
  assign LOCKSTEP_Master_Out[3866] = \<const0> ;
  assign LOCKSTEP_Master_Out[3867] = \<const0> ;
  assign LOCKSTEP_Master_Out[3868] = \<const0> ;
  assign LOCKSTEP_Master_Out[3869] = \<const0> ;
  assign LOCKSTEP_Master_Out[3870] = \<const0> ;
  assign LOCKSTEP_Master_Out[3871] = \<const0> ;
  assign LOCKSTEP_Master_Out[3872] = \<const0> ;
  assign LOCKSTEP_Master_Out[3873] = \<const0> ;
  assign LOCKSTEP_Master_Out[3874] = \<const0> ;
  assign LOCKSTEP_Master_Out[3875] = \<const0> ;
  assign LOCKSTEP_Master_Out[3876] = \<const0> ;
  assign LOCKSTEP_Master_Out[3877] = \<const0> ;
  assign LOCKSTEP_Master_Out[3878] = \<const0> ;
  assign LOCKSTEP_Master_Out[3879] = \<const0> ;
  assign LOCKSTEP_Master_Out[3880] = \<const0> ;
  assign LOCKSTEP_Master_Out[3881] = \<const0> ;
  assign LOCKSTEP_Master_Out[3882] = \<const0> ;
  assign LOCKSTEP_Master_Out[3883] = \<const0> ;
  assign LOCKSTEP_Master_Out[3884] = \<const0> ;
  assign LOCKSTEP_Master_Out[3885] = \<const0> ;
  assign LOCKSTEP_Master_Out[3886] = \<const0> ;
  assign LOCKSTEP_Master_Out[3887] = \<const0> ;
  assign LOCKSTEP_Master_Out[3888] = \<const0> ;
  assign LOCKSTEP_Master_Out[3889] = \<const0> ;
  assign LOCKSTEP_Master_Out[3890] = \<const0> ;
  assign LOCKSTEP_Master_Out[3891] = \<const0> ;
  assign LOCKSTEP_Master_Out[3892] = \<const0> ;
  assign LOCKSTEP_Master_Out[3893] = \<const0> ;
  assign LOCKSTEP_Master_Out[3894] = \<const0> ;
  assign LOCKSTEP_Master_Out[3895] = \<const0> ;
  assign LOCKSTEP_Master_Out[3896] = \<const0> ;
  assign LOCKSTEP_Master_Out[3897] = \<const0> ;
  assign LOCKSTEP_Master_Out[3898] = \<const0> ;
  assign LOCKSTEP_Master_Out[3899] = \<const0> ;
  assign LOCKSTEP_Master_Out[3900] = \<const0> ;
  assign LOCKSTEP_Master_Out[3901] = \<const0> ;
  assign LOCKSTEP_Master_Out[3902] = \<const0> ;
  assign LOCKSTEP_Master_Out[3903] = \<const0> ;
  assign LOCKSTEP_Master_Out[3904] = \<const0> ;
  assign LOCKSTEP_Master_Out[3905] = \<const0> ;
  assign LOCKSTEP_Master_Out[3906] = \<const0> ;
  assign LOCKSTEP_Master_Out[3907] = \<const0> ;
  assign LOCKSTEP_Master_Out[3908] = \<const0> ;
  assign LOCKSTEP_Master_Out[3909] = \<const0> ;
  assign LOCKSTEP_Master_Out[3910] = \<const0> ;
  assign LOCKSTEP_Master_Out[3911] = \<const0> ;
  assign LOCKSTEP_Master_Out[3912] = \<const0> ;
  assign LOCKSTEP_Master_Out[3913] = \<const0> ;
  assign LOCKSTEP_Master_Out[3914] = \<const0> ;
  assign LOCKSTEP_Master_Out[3915] = \<const0> ;
  assign LOCKSTEP_Master_Out[3916] = \<const0> ;
  assign LOCKSTEP_Master_Out[3917] = \<const0> ;
  assign LOCKSTEP_Master_Out[3918] = \<const0> ;
  assign LOCKSTEP_Master_Out[3919] = \<const0> ;
  assign LOCKSTEP_Master_Out[3920] = \<const0> ;
  assign LOCKSTEP_Master_Out[3921] = \<const0> ;
  assign LOCKSTEP_Master_Out[3922] = \<const0> ;
  assign LOCKSTEP_Master_Out[3923] = \<const0> ;
  assign LOCKSTEP_Master_Out[3924] = \<const0> ;
  assign LOCKSTEP_Master_Out[3925] = \<const0> ;
  assign LOCKSTEP_Master_Out[3926] = \<const0> ;
  assign LOCKSTEP_Master_Out[3927] = \<const0> ;
  assign LOCKSTEP_Master_Out[3928] = \<const0> ;
  assign LOCKSTEP_Master_Out[3929] = \<const0> ;
  assign LOCKSTEP_Master_Out[3930] = \<const0> ;
  assign LOCKSTEP_Master_Out[3931] = \<const0> ;
  assign LOCKSTEP_Master_Out[3932] = \<const0> ;
  assign LOCKSTEP_Master_Out[3933] = \<const0> ;
  assign LOCKSTEP_Master_Out[3934] = \<const0> ;
  assign LOCKSTEP_Master_Out[3935] = \<const0> ;
  assign LOCKSTEP_Master_Out[3936] = \<const0> ;
  assign LOCKSTEP_Master_Out[3937] = \<const0> ;
  assign LOCKSTEP_Master_Out[3938] = \<const0> ;
  assign LOCKSTEP_Master_Out[3939] = \<const0> ;
  assign LOCKSTEP_Master_Out[3940] = \<const0> ;
  assign LOCKSTEP_Master_Out[3941] = \<const0> ;
  assign LOCKSTEP_Master_Out[3942] = \<const0> ;
  assign LOCKSTEP_Master_Out[3943] = \<const0> ;
  assign LOCKSTEP_Master_Out[3944] = \<const0> ;
  assign LOCKSTEP_Master_Out[3945] = \<const0> ;
  assign LOCKSTEP_Master_Out[3946] = \<const0> ;
  assign LOCKSTEP_Master_Out[3947] = \<const0> ;
  assign LOCKSTEP_Master_Out[3948] = \<const0> ;
  assign LOCKSTEP_Master_Out[3949] = \<const0> ;
  assign LOCKSTEP_Master_Out[3950] = \<const0> ;
  assign LOCKSTEP_Master_Out[3951] = \<const0> ;
  assign LOCKSTEP_Master_Out[3952] = \<const0> ;
  assign LOCKSTEP_Master_Out[3953] = \<const0> ;
  assign LOCKSTEP_Master_Out[3954] = \<const0> ;
  assign LOCKSTEP_Master_Out[3955] = \<const0> ;
  assign LOCKSTEP_Master_Out[3956] = \<const0> ;
  assign LOCKSTEP_Master_Out[3957] = \<const0> ;
  assign LOCKSTEP_Master_Out[3958] = \<const0> ;
  assign LOCKSTEP_Master_Out[3959] = \<const0> ;
  assign LOCKSTEP_Master_Out[3960] = \<const0> ;
  assign LOCKSTEP_Master_Out[3961] = \<const0> ;
  assign LOCKSTEP_Master_Out[3962] = \<const0> ;
  assign LOCKSTEP_Master_Out[3963] = \<const0> ;
  assign LOCKSTEP_Master_Out[3964] = \<const0> ;
  assign LOCKSTEP_Master_Out[3965] = \<const0> ;
  assign LOCKSTEP_Master_Out[3966] = \<const0> ;
  assign LOCKSTEP_Master_Out[3967] = \<const0> ;
  assign LOCKSTEP_Master_Out[3968] = \<const0> ;
  assign LOCKSTEP_Master_Out[3969] = \<const0> ;
  assign LOCKSTEP_Master_Out[3970] = \<const0> ;
  assign LOCKSTEP_Master_Out[3971] = \<const0> ;
  assign LOCKSTEP_Master_Out[3972] = \<const0> ;
  assign LOCKSTEP_Master_Out[3973] = \<const0> ;
  assign LOCKSTEP_Master_Out[3974] = \<const0> ;
  assign LOCKSTEP_Master_Out[3975] = \<const0> ;
  assign LOCKSTEP_Master_Out[3976] = \<const0> ;
  assign LOCKSTEP_Master_Out[3977] = \<const0> ;
  assign LOCKSTEP_Master_Out[3978] = \<const0> ;
  assign LOCKSTEP_Master_Out[3979] = \<const0> ;
  assign LOCKSTEP_Master_Out[3980] = \<const0> ;
  assign LOCKSTEP_Master_Out[3981] = \<const0> ;
  assign LOCKSTEP_Master_Out[3982] = \<const0> ;
  assign LOCKSTEP_Master_Out[3983] = \<const0> ;
  assign LOCKSTEP_Master_Out[3984] = \<const0> ;
  assign LOCKSTEP_Master_Out[3985] = \<const0> ;
  assign LOCKSTEP_Master_Out[3986] = \<const0> ;
  assign LOCKSTEP_Master_Out[3987] = \<const0> ;
  assign LOCKSTEP_Master_Out[3988] = \<const0> ;
  assign LOCKSTEP_Master_Out[3989] = \<const0> ;
  assign LOCKSTEP_Master_Out[3990] = \<const0> ;
  assign LOCKSTEP_Master_Out[3991] = \<const0> ;
  assign LOCKSTEP_Master_Out[3992] = \<const0> ;
  assign LOCKSTEP_Master_Out[3993] = \<const0> ;
  assign LOCKSTEP_Master_Out[3994] = \<const0> ;
  assign LOCKSTEP_Master_Out[3995] = \<const0> ;
  assign LOCKSTEP_Master_Out[3996] = \<const0> ;
  assign LOCKSTEP_Master_Out[3997] = \<const0> ;
  assign LOCKSTEP_Master_Out[3998] = \<const0> ;
  assign LOCKSTEP_Master_Out[3999] = \<const0> ;
  assign LOCKSTEP_Master_Out[4000] = \<const0> ;
  assign LOCKSTEP_Master_Out[4001] = \<const0> ;
  assign LOCKSTEP_Master_Out[4002] = \<const0> ;
  assign LOCKSTEP_Master_Out[4003] = \<const0> ;
  assign LOCKSTEP_Master_Out[4004] = \<const0> ;
  assign LOCKSTEP_Master_Out[4005] = \<const0> ;
  assign LOCKSTEP_Master_Out[4006] = \<const0> ;
  assign LOCKSTEP_Master_Out[4007] = \<const0> ;
  assign LOCKSTEP_Master_Out[4008] = \<const0> ;
  assign LOCKSTEP_Master_Out[4009] = \<const0> ;
  assign LOCKSTEP_Master_Out[4010] = \<const0> ;
  assign LOCKSTEP_Master_Out[4011] = \<const0> ;
  assign LOCKSTEP_Master_Out[4012] = \<const0> ;
  assign LOCKSTEP_Master_Out[4013] = \<const0> ;
  assign LOCKSTEP_Master_Out[4014] = \<const0> ;
  assign LOCKSTEP_Master_Out[4015] = \<const0> ;
  assign LOCKSTEP_Master_Out[4016] = \<const0> ;
  assign LOCKSTEP_Master_Out[4017] = \<const0> ;
  assign LOCKSTEP_Master_Out[4018] = \<const0> ;
  assign LOCKSTEP_Master_Out[4019] = \<const0> ;
  assign LOCKSTEP_Master_Out[4020] = \<const0> ;
  assign LOCKSTEP_Master_Out[4021] = \<const0> ;
  assign LOCKSTEP_Master_Out[4022] = \<const0> ;
  assign LOCKSTEP_Master_Out[4023] = \<const0> ;
  assign LOCKSTEP_Master_Out[4024] = \<const0> ;
  assign LOCKSTEP_Master_Out[4025] = \<const0> ;
  assign LOCKSTEP_Master_Out[4026] = \<const0> ;
  assign LOCKSTEP_Master_Out[4027] = \<const0> ;
  assign LOCKSTEP_Master_Out[4028] = \<const0> ;
  assign LOCKSTEP_Master_Out[4029] = \<const0> ;
  assign LOCKSTEP_Master_Out[4030] = \<const0> ;
  assign LOCKSTEP_Master_Out[4031] = \<const0> ;
  assign LOCKSTEP_Master_Out[4032] = \<const0> ;
  assign LOCKSTEP_Master_Out[4033] = \<const0> ;
  assign LOCKSTEP_Master_Out[4034] = \<const0> ;
  assign LOCKSTEP_Master_Out[4035] = \<const0> ;
  assign LOCKSTEP_Master_Out[4036] = \<const0> ;
  assign LOCKSTEP_Master_Out[4037] = \<const0> ;
  assign LOCKSTEP_Master_Out[4038] = \<const0> ;
  assign LOCKSTEP_Master_Out[4039] = \<const0> ;
  assign LOCKSTEP_Master_Out[4040] = \<const0> ;
  assign LOCKSTEP_Master_Out[4041] = \<const0> ;
  assign LOCKSTEP_Master_Out[4042] = \<const0> ;
  assign LOCKSTEP_Master_Out[4043] = \<const0> ;
  assign LOCKSTEP_Master_Out[4044] = \<const0> ;
  assign LOCKSTEP_Master_Out[4045] = \<const0> ;
  assign LOCKSTEP_Master_Out[4046] = \<const0> ;
  assign LOCKSTEP_Master_Out[4047] = \<const0> ;
  assign LOCKSTEP_Master_Out[4048] = \<const0> ;
  assign LOCKSTEP_Master_Out[4049] = \<const0> ;
  assign LOCKSTEP_Master_Out[4050] = \<const0> ;
  assign LOCKSTEP_Master_Out[4051] = \<const0> ;
  assign LOCKSTEP_Master_Out[4052] = \<const0> ;
  assign LOCKSTEP_Master_Out[4053] = \<const0> ;
  assign LOCKSTEP_Master_Out[4054] = \<const0> ;
  assign LOCKSTEP_Master_Out[4055] = \<const0> ;
  assign LOCKSTEP_Master_Out[4056] = \<const0> ;
  assign LOCKSTEP_Master_Out[4057] = \<const0> ;
  assign LOCKSTEP_Master_Out[4058] = \<const0> ;
  assign LOCKSTEP_Master_Out[4059] = \<const0> ;
  assign LOCKSTEP_Master_Out[4060] = \<const0> ;
  assign LOCKSTEP_Master_Out[4061] = \<const0> ;
  assign LOCKSTEP_Master_Out[4062] = \<const0> ;
  assign LOCKSTEP_Master_Out[4063] = \<const0> ;
  assign LOCKSTEP_Master_Out[4064] = \<const0> ;
  assign LOCKSTEP_Master_Out[4065] = \<const0> ;
  assign LOCKSTEP_Master_Out[4066] = \<const0> ;
  assign LOCKSTEP_Master_Out[4067] = \<const0> ;
  assign LOCKSTEP_Master_Out[4068] = \<const0> ;
  assign LOCKSTEP_Master_Out[4069] = \<const0> ;
  assign LOCKSTEP_Master_Out[4070] = \<const0> ;
  assign LOCKSTEP_Master_Out[4071] = \<const0> ;
  assign LOCKSTEP_Master_Out[4072] = \<const0> ;
  assign LOCKSTEP_Master_Out[4073] = \<const0> ;
  assign LOCKSTEP_Master_Out[4074] = \<const0> ;
  assign LOCKSTEP_Master_Out[4075] = \<const0> ;
  assign LOCKSTEP_Master_Out[4076] = \<const0> ;
  assign LOCKSTEP_Master_Out[4077] = \<const0> ;
  assign LOCKSTEP_Master_Out[4078] = \<const0> ;
  assign LOCKSTEP_Master_Out[4079] = \<const0> ;
  assign LOCKSTEP_Master_Out[4080] = \<const0> ;
  assign LOCKSTEP_Master_Out[4081] = \<const0> ;
  assign LOCKSTEP_Master_Out[4082] = \<const0> ;
  assign LOCKSTEP_Master_Out[4083] = \<const0> ;
  assign LOCKSTEP_Master_Out[4084] = \<const0> ;
  assign LOCKSTEP_Master_Out[4085] = \<const0> ;
  assign LOCKSTEP_Master_Out[4086] = \<const0> ;
  assign LOCKSTEP_Master_Out[4087] = \<const0> ;
  assign LOCKSTEP_Master_Out[4088] = \<const0> ;
  assign LOCKSTEP_Master_Out[4089] = \<const0> ;
  assign LOCKSTEP_Master_Out[4090] = \<const0> ;
  assign LOCKSTEP_Master_Out[4091] = \<const0> ;
  assign LOCKSTEP_Master_Out[4092] = \<const0> ;
  assign LOCKSTEP_Master_Out[4093] = \<const0> ;
  assign LOCKSTEP_Master_Out[4094] = \<const0> ;
  assign LOCKSTEP_Master_Out[4095] = \<const0> ;
  assign LOCKSTEP_Out[0] = \^LOCKSTEP_Out [3228];
  assign LOCKSTEP_Out[1] = \<const0> ;
  assign LOCKSTEP_Out[2:35] = \^LOCKSTEP_Out [2:35];
  assign LOCKSTEP_Out[36] = \<const0> ;
  assign LOCKSTEP_Out[37] = \<const0> ;
  assign LOCKSTEP_Out[38] = \<const0> ;
  assign LOCKSTEP_Out[39] = \<const0> ;
  assign LOCKSTEP_Out[40] = \<const0> ;
  assign LOCKSTEP_Out[41] = \<const0> ;
  assign LOCKSTEP_Out[42] = \<const0> ;
  assign LOCKSTEP_Out[43] = \<const0> ;
  assign LOCKSTEP_Out[44] = \<const0> ;
  assign LOCKSTEP_Out[45] = \<const0> ;
  assign LOCKSTEP_Out[46] = \<const0> ;
  assign LOCKSTEP_Out[47] = \<const0> ;
  assign LOCKSTEP_Out[48] = \<const0> ;
  assign LOCKSTEP_Out[49] = \<const0> ;
  assign LOCKSTEP_Out[50] = \<const0> ;
  assign LOCKSTEP_Out[51] = \<const0> ;
  assign LOCKSTEP_Out[52] = \<const0> ;
  assign LOCKSTEP_Out[53] = \<const0> ;
  assign LOCKSTEP_Out[54] = \<const0> ;
  assign LOCKSTEP_Out[55] = \<const0> ;
  assign LOCKSTEP_Out[56] = \<const0> ;
  assign LOCKSTEP_Out[57] = \<const0> ;
  assign LOCKSTEP_Out[58] = \<const0> ;
  assign LOCKSTEP_Out[59] = \<const0> ;
  assign LOCKSTEP_Out[60] = \<const0> ;
  assign LOCKSTEP_Out[61] = \<const0> ;
  assign LOCKSTEP_Out[62] = \<const0> ;
  assign LOCKSTEP_Out[63] = \<const0> ;
  assign LOCKSTEP_Out[64] = \<const0> ;
  assign LOCKSTEP_Out[65] = \<const0> ;
  assign LOCKSTEP_Out[66] = \<const0> ;
  assign LOCKSTEP_Out[67] = \<const0> ;
  assign LOCKSTEP_Out[68:99] = \^LOCKSTEP_Out [68:99];
  assign LOCKSTEP_Out[100] = \<const0> ;
  assign LOCKSTEP_Out[101] = \<const0> ;
  assign LOCKSTEP_Out[102] = \<const0> ;
  assign LOCKSTEP_Out[103] = \<const0> ;
  assign LOCKSTEP_Out[104] = \<const0> ;
  assign LOCKSTEP_Out[105] = \<const0> ;
  assign LOCKSTEP_Out[106] = \<const0> ;
  assign LOCKSTEP_Out[107] = \<const0> ;
  assign LOCKSTEP_Out[108] = \<const0> ;
  assign LOCKSTEP_Out[109] = \<const0> ;
  assign LOCKSTEP_Out[110] = \<const0> ;
  assign LOCKSTEP_Out[111] = \<const0> ;
  assign LOCKSTEP_Out[112] = \<const0> ;
  assign LOCKSTEP_Out[113] = \<const0> ;
  assign LOCKSTEP_Out[114] = \<const0> ;
  assign LOCKSTEP_Out[115] = \<const0> ;
  assign LOCKSTEP_Out[116] = \<const0> ;
  assign LOCKSTEP_Out[117] = \<const0> ;
  assign LOCKSTEP_Out[118] = \<const0> ;
  assign LOCKSTEP_Out[119] = \<const0> ;
  assign LOCKSTEP_Out[120] = \<const0> ;
  assign LOCKSTEP_Out[121] = \<const0> ;
  assign LOCKSTEP_Out[122] = \<const0> ;
  assign LOCKSTEP_Out[123] = \<const0> ;
  assign LOCKSTEP_Out[124] = \<const0> ;
  assign LOCKSTEP_Out[125] = \<const0> ;
  assign LOCKSTEP_Out[126] = \<const0> ;
  assign LOCKSTEP_Out[127] = \<const0> ;
  assign LOCKSTEP_Out[128] = \<const0> ;
  assign LOCKSTEP_Out[129] = \<const0> ;
  assign LOCKSTEP_Out[130] = \<const0> ;
  assign LOCKSTEP_Out[131] = \<const0> ;
  assign LOCKSTEP_Out[132:163] = \^LOCKSTEP_Out [132:163];
  assign LOCKSTEP_Out[164] = \<const0> ;
  assign LOCKSTEP_Out[165] = \<const0> ;
  assign LOCKSTEP_Out[166] = \<const0> ;
  assign LOCKSTEP_Out[167] = \<const0> ;
  assign LOCKSTEP_Out[168] = \<const0> ;
  assign LOCKSTEP_Out[169] = \<const0> ;
  assign LOCKSTEP_Out[170] = \<const0> ;
  assign LOCKSTEP_Out[171] = \<const0> ;
  assign LOCKSTEP_Out[172] = \<const0> ;
  assign LOCKSTEP_Out[173] = \<const0> ;
  assign LOCKSTEP_Out[174] = \<const0> ;
  assign LOCKSTEP_Out[175] = \<const0> ;
  assign LOCKSTEP_Out[176] = \<const0> ;
  assign LOCKSTEP_Out[177] = \<const0> ;
  assign LOCKSTEP_Out[178] = \<const0> ;
  assign LOCKSTEP_Out[179] = \<const0> ;
  assign LOCKSTEP_Out[180] = \<const0> ;
  assign LOCKSTEP_Out[181] = \<const0> ;
  assign LOCKSTEP_Out[182] = \<const0> ;
  assign LOCKSTEP_Out[183] = \<const0> ;
  assign LOCKSTEP_Out[184] = \<const0> ;
  assign LOCKSTEP_Out[185] = \<const0> ;
  assign LOCKSTEP_Out[186] = \<const0> ;
  assign LOCKSTEP_Out[187] = \<const0> ;
  assign LOCKSTEP_Out[188] = \<const0> ;
  assign LOCKSTEP_Out[189] = \<const0> ;
  assign LOCKSTEP_Out[190] = \<const0> ;
  assign LOCKSTEP_Out[191] = \<const0> ;
  assign LOCKSTEP_Out[192] = \<const0> ;
  assign LOCKSTEP_Out[193] = \<const0> ;
  assign LOCKSTEP_Out[194] = \<const0> ;
  assign LOCKSTEP_Out[195] = \<const0> ;
  assign LOCKSTEP_Out[196:202] = \^LOCKSTEP_Out [196:202];
  assign LOCKSTEP_Out[203] = \<const0> ;
  assign LOCKSTEP_Out[204] = \<const0> ;
  assign LOCKSTEP_Out[205] = \<const0> ;
  assign LOCKSTEP_Out[206] = \<const0> ;
  assign LOCKSTEP_Out[207] = \<const0> ;
  assign LOCKSTEP_Out[208] = \<const0> ;
  assign LOCKSTEP_Out[209] = \<const0> ;
  assign LOCKSTEP_Out[210] = \<const0> ;
  assign LOCKSTEP_Out[211] = \<const0> ;
  assign LOCKSTEP_Out[212] = \<const0> ;
  assign LOCKSTEP_Out[213] = \<const0> ;
  assign LOCKSTEP_Out[214] = \<const0> ;
  assign LOCKSTEP_Out[215] = \<const0> ;
  assign LOCKSTEP_Out[216] = \<const0> ;
  assign LOCKSTEP_Out[217] = \<const0> ;
  assign LOCKSTEP_Out[218] = \<const0> ;
  assign LOCKSTEP_Out[219] = \<const0> ;
  assign LOCKSTEP_Out[220] = \<const0> ;
  assign LOCKSTEP_Out[221] = \<const0> ;
  assign LOCKSTEP_Out[222] = \<const0> ;
  assign LOCKSTEP_Out[223] = \<const0> ;
  assign LOCKSTEP_Out[224] = \<const0> ;
  assign LOCKSTEP_Out[225] = \<const0> ;
  assign LOCKSTEP_Out[226] = \<const0> ;
  assign LOCKSTEP_Out[227] = \<const0> ;
  assign LOCKSTEP_Out[228] = \<const0> ;
  assign LOCKSTEP_Out[229] = \<const0> ;
  assign LOCKSTEP_Out[230] = \<const0> ;
  assign LOCKSTEP_Out[231] = \<const0> ;
  assign LOCKSTEP_Out[232] = \<const0> ;
  assign LOCKSTEP_Out[233] = \<const0> ;
  assign LOCKSTEP_Out[234] = \<const0> ;
  assign LOCKSTEP_Out[235] = \<const0> ;
  assign LOCKSTEP_Out[236] = \<const0> ;
  assign LOCKSTEP_Out[237] = \<const0> ;
  assign LOCKSTEP_Out[238] = \<const0> ;
  assign LOCKSTEP_Out[239] = \<const0> ;
  assign LOCKSTEP_Out[240] = \<const0> ;
  assign LOCKSTEP_Out[241] = \<const0> ;
  assign LOCKSTEP_Out[242] = \<const0> ;
  assign LOCKSTEP_Out[243] = \<const0> ;
  assign LOCKSTEP_Out[244] = \<const0> ;
  assign LOCKSTEP_Out[245] = \<const0> ;
  assign LOCKSTEP_Out[246] = \<const0> ;
  assign LOCKSTEP_Out[247] = \<const0> ;
  assign LOCKSTEP_Out[248] = \<const0> ;
  assign LOCKSTEP_Out[249] = \<const0> ;
  assign LOCKSTEP_Out[250] = \<const0> ;
  assign LOCKSTEP_Out[251] = \<const0> ;
  assign LOCKSTEP_Out[252] = \<const0> ;
  assign LOCKSTEP_Out[253] = \<const0> ;
  assign LOCKSTEP_Out[254] = \<const0> ;
  assign LOCKSTEP_Out[255] = \<const0> ;
  assign LOCKSTEP_Out[256] = \<const0> ;
  assign LOCKSTEP_Out[257] = \<const0> ;
  assign LOCKSTEP_Out[258] = \<const0> ;
  assign LOCKSTEP_Out[259] = \<const0> ;
  assign LOCKSTEP_Out[260] = \<const0> ;
  assign LOCKSTEP_Out[261] = \<const0> ;
  assign LOCKSTEP_Out[262] = \<const0> ;
  assign LOCKSTEP_Out[263] = \<const0> ;
  assign LOCKSTEP_Out[264] = \<const0> ;
  assign LOCKSTEP_Out[265] = \<const0> ;
  assign LOCKSTEP_Out[266] = \<const0> ;
  assign LOCKSTEP_Out[267] = \<const0> ;
  assign LOCKSTEP_Out[268] = \<const0> ;
  assign LOCKSTEP_Out[269] = \<const0> ;
  assign LOCKSTEP_Out[270] = \<const0> ;
  assign LOCKSTEP_Out[271] = \<const0> ;
  assign LOCKSTEP_Out[272] = \<const0> ;
  assign LOCKSTEP_Out[273] = \<const0> ;
  assign LOCKSTEP_Out[274] = \<const0> ;
  assign LOCKSTEP_Out[275] = \<const0> ;
  assign LOCKSTEP_Out[276] = \<const0> ;
  assign LOCKSTEP_Out[277] = \<const0> ;
  assign LOCKSTEP_Out[278] = \<const0> ;
  assign LOCKSTEP_Out[279] = \<const0> ;
  assign LOCKSTEP_Out[280] = \<const0> ;
  assign LOCKSTEP_Out[281] = \<const0> ;
  assign LOCKSTEP_Out[282] = \<const0> ;
  assign LOCKSTEP_Out[283] = \<const0> ;
  assign LOCKSTEP_Out[284] = \<const0> ;
  assign LOCKSTEP_Out[285] = \<const0> ;
  assign LOCKSTEP_Out[286] = \<const0> ;
  assign LOCKSTEP_Out[287] = \<const0> ;
  assign LOCKSTEP_Out[288] = \<const0> ;
  assign LOCKSTEP_Out[289] = \<const0> ;
  assign LOCKSTEP_Out[290] = \<const0> ;
  assign LOCKSTEP_Out[291] = \<const0> ;
  assign LOCKSTEP_Out[292] = \<const0> ;
  assign LOCKSTEP_Out[293] = \<const0> ;
  assign LOCKSTEP_Out[294] = \<const0> ;
  assign LOCKSTEP_Out[295] = \<const0> ;
  assign LOCKSTEP_Out[296] = \<const0> ;
  assign LOCKSTEP_Out[297] = \<const0> ;
  assign LOCKSTEP_Out[298] = \<const0> ;
  assign LOCKSTEP_Out[299] = \<const0> ;
  assign LOCKSTEP_Out[300] = \<const0> ;
  assign LOCKSTEP_Out[301] = \<const0> ;
  assign LOCKSTEP_Out[302] = \<const0> ;
  assign LOCKSTEP_Out[303] = \<const0> ;
  assign LOCKSTEP_Out[304] = \<const0> ;
  assign LOCKSTEP_Out[305] = \<const0> ;
  assign LOCKSTEP_Out[306] = \<const0> ;
  assign LOCKSTEP_Out[307] = \<const0> ;
  assign LOCKSTEP_Out[308] = \<const0> ;
  assign LOCKSTEP_Out[309] = \<const0> ;
  assign LOCKSTEP_Out[310] = \<const0> ;
  assign LOCKSTEP_Out[311] = \<const0> ;
  assign LOCKSTEP_Out[312] = \<const0> ;
  assign LOCKSTEP_Out[313] = \<const0> ;
  assign LOCKSTEP_Out[314] = \<const0> ;
  assign LOCKSTEP_Out[315] = \<const0> ;
  assign LOCKSTEP_Out[316] = \<const0> ;
  assign LOCKSTEP_Out[317] = \<const0> ;
  assign LOCKSTEP_Out[318] = \<const0> ;
  assign LOCKSTEP_Out[319] = \<const0> ;
  assign LOCKSTEP_Out[320] = \<const0> ;
  assign LOCKSTEP_Out[321] = \<const0> ;
  assign LOCKSTEP_Out[322] = \<const0> ;
  assign LOCKSTEP_Out[323] = \<const0> ;
  assign LOCKSTEP_Out[324] = \<const0> ;
  assign LOCKSTEP_Out[325] = \<const0> ;
  assign LOCKSTEP_Out[326] = \<const0> ;
  assign LOCKSTEP_Out[327] = \<const0> ;
  assign LOCKSTEP_Out[328] = \<const0> ;
  assign LOCKSTEP_Out[329] = \<const0> ;
  assign LOCKSTEP_Out[330] = \<const0> ;
  assign LOCKSTEP_Out[331] = \<const0> ;
  assign LOCKSTEP_Out[332] = \<const0> ;
  assign LOCKSTEP_Out[333] = \<const0> ;
  assign LOCKSTEP_Out[334] = \<const0> ;
  assign LOCKSTEP_Out[335] = \<const0> ;
  assign LOCKSTEP_Out[336] = \<const0> ;
  assign LOCKSTEP_Out[337] = \<const0> ;
  assign LOCKSTEP_Out[338] = \<const0> ;
  assign LOCKSTEP_Out[339] = \<const0> ;
  assign LOCKSTEP_Out[340] = \<const0> ;
  assign LOCKSTEP_Out[341] = \<const0> ;
  assign LOCKSTEP_Out[342] = \<const0> ;
  assign LOCKSTEP_Out[343] = \<const0> ;
  assign LOCKSTEP_Out[344] = \<const0> ;
  assign LOCKSTEP_Out[345] = \<const0> ;
  assign LOCKSTEP_Out[346] = \<const0> ;
  assign LOCKSTEP_Out[347] = \<const0> ;
  assign LOCKSTEP_Out[348] = \<const0> ;
  assign LOCKSTEP_Out[349] = \<const0> ;
  assign LOCKSTEP_Out[350] = \<const0> ;
  assign LOCKSTEP_Out[351] = \<const0> ;
  assign LOCKSTEP_Out[352] = \<const0> ;
  assign LOCKSTEP_Out[353] = \<const0> ;
  assign LOCKSTEP_Out[354] = \<const0> ;
  assign LOCKSTEP_Out[355] = \<const0> ;
  assign LOCKSTEP_Out[356] = \<const0> ;
  assign LOCKSTEP_Out[357] = \<const0> ;
  assign LOCKSTEP_Out[358] = \<const0> ;
  assign LOCKSTEP_Out[359] = \<const0> ;
  assign LOCKSTEP_Out[360] = \<const0> ;
  assign LOCKSTEP_Out[361] = \<const0> ;
  assign LOCKSTEP_Out[362] = \<const0> ;
  assign LOCKSTEP_Out[363] = \<const0> ;
  assign LOCKSTEP_Out[364] = \<const0> ;
  assign LOCKSTEP_Out[365] = \<const0> ;
  assign LOCKSTEP_Out[366] = \<const0> ;
  assign LOCKSTEP_Out[367] = \<const0> ;
  assign LOCKSTEP_Out[368] = \<const0> ;
  assign LOCKSTEP_Out[369] = \<const0> ;
  assign LOCKSTEP_Out[370] = \<const0> ;
  assign LOCKSTEP_Out[371] = \<const0> ;
  assign LOCKSTEP_Out[372] = \<const0> ;
  assign LOCKSTEP_Out[373] = \<const0> ;
  assign LOCKSTEP_Out[374] = \<const0> ;
  assign LOCKSTEP_Out[375] = \<const0> ;
  assign LOCKSTEP_Out[376] = \<const0> ;
  assign LOCKSTEP_Out[377] = \<const0> ;
  assign LOCKSTEP_Out[378] = \<const0> ;
  assign LOCKSTEP_Out[379] = \<const0> ;
  assign LOCKSTEP_Out[380] = \<const0> ;
  assign LOCKSTEP_Out[381] = \<const0> ;
  assign LOCKSTEP_Out[382] = \<const0> ;
  assign LOCKSTEP_Out[383] = \<const0> ;
  assign LOCKSTEP_Out[384] = \<const0> ;
  assign LOCKSTEP_Out[385] = \<const0> ;
  assign LOCKSTEP_Out[386] = \<const0> ;
  assign LOCKSTEP_Out[387] = \<const0> ;
  assign LOCKSTEP_Out[388] = \<const0> ;
  assign LOCKSTEP_Out[389] = \<const0> ;
  assign LOCKSTEP_Out[390] = \<const0> ;
  assign LOCKSTEP_Out[391] = \<const0> ;
  assign LOCKSTEP_Out[392] = \<const0> ;
  assign LOCKSTEP_Out[393] = \<const0> ;
  assign LOCKSTEP_Out[394] = \<const0> ;
  assign LOCKSTEP_Out[395] = \<const0> ;
  assign LOCKSTEP_Out[396] = \<const0> ;
  assign LOCKSTEP_Out[397] = \<const0> ;
  assign LOCKSTEP_Out[398] = \<const0> ;
  assign LOCKSTEP_Out[399] = \<const0> ;
  assign LOCKSTEP_Out[400] = \<const0> ;
  assign LOCKSTEP_Out[401] = \<const0> ;
  assign LOCKSTEP_Out[402] = \<const0> ;
  assign LOCKSTEP_Out[403] = \<const0> ;
  assign LOCKSTEP_Out[404] = \<const0> ;
  assign LOCKSTEP_Out[405] = \<const0> ;
  assign LOCKSTEP_Out[406] = \<const0> ;
  assign LOCKSTEP_Out[407] = \<const0> ;
  assign LOCKSTEP_Out[408] = \<const0> ;
  assign LOCKSTEP_Out[409] = \<const0> ;
  assign LOCKSTEP_Out[410] = \<const0> ;
  assign LOCKSTEP_Out[411] = \<const0> ;
  assign LOCKSTEP_Out[412] = \<const0> ;
  assign LOCKSTEP_Out[413] = \<const0> ;
  assign LOCKSTEP_Out[414] = \<const0> ;
  assign LOCKSTEP_Out[415] = \<const0> ;
  assign LOCKSTEP_Out[416] = \<const0> ;
  assign LOCKSTEP_Out[417] = \<const0> ;
  assign LOCKSTEP_Out[418] = \<const0> ;
  assign LOCKSTEP_Out[419] = \<const0> ;
  assign LOCKSTEP_Out[420] = \<const0> ;
  assign LOCKSTEP_Out[421] = \<const0> ;
  assign LOCKSTEP_Out[422] = \<const0> ;
  assign LOCKSTEP_Out[423] = \<const0> ;
  assign LOCKSTEP_Out[424] = \<const0> ;
  assign LOCKSTEP_Out[425] = \<const0> ;
  assign LOCKSTEP_Out[426] = \<const0> ;
  assign LOCKSTEP_Out[427] = \<const0> ;
  assign LOCKSTEP_Out[428] = \<const0> ;
  assign LOCKSTEP_Out[429] = \<const0> ;
  assign LOCKSTEP_Out[430] = \<const0> ;
  assign LOCKSTEP_Out[431] = \<const0> ;
  assign LOCKSTEP_Out[432] = \<const0> ;
  assign LOCKSTEP_Out[433] = \<const0> ;
  assign LOCKSTEP_Out[434] = \<const0> ;
  assign LOCKSTEP_Out[435] = \<const0> ;
  assign LOCKSTEP_Out[436] = \<const0> ;
  assign LOCKSTEP_Out[437] = \<const0> ;
  assign LOCKSTEP_Out[438] = \<const0> ;
  assign LOCKSTEP_Out[439] = \<const0> ;
  assign LOCKSTEP_Out[440] = \<const0> ;
  assign LOCKSTEP_Out[441] = \<const0> ;
  assign LOCKSTEP_Out[442] = \<const0> ;
  assign LOCKSTEP_Out[443] = \<const0> ;
  assign LOCKSTEP_Out[444] = \<const0> ;
  assign LOCKSTEP_Out[445] = \<const0> ;
  assign LOCKSTEP_Out[446] = \<const0> ;
  assign LOCKSTEP_Out[447] = \<const0> ;
  assign LOCKSTEP_Out[448] = \<const0> ;
  assign LOCKSTEP_Out[449] = \<const0> ;
  assign LOCKSTEP_Out[450] = \<const0> ;
  assign LOCKSTEP_Out[451] = \<const0> ;
  assign LOCKSTEP_Out[452] = \<const0> ;
  assign LOCKSTEP_Out[453] = \<const0> ;
  assign LOCKSTEP_Out[454] = \<const0> ;
  assign LOCKSTEP_Out[455] = \<const0> ;
  assign LOCKSTEP_Out[456] = \<const0> ;
  assign LOCKSTEP_Out[457] = \<const0> ;
  assign LOCKSTEP_Out[458] = \<const0> ;
  assign LOCKSTEP_Out[459] = \<const0> ;
  assign LOCKSTEP_Out[460] = \<const0> ;
  assign LOCKSTEP_Out[461] = \<const0> ;
  assign LOCKSTEP_Out[462] = \<const0> ;
  assign LOCKSTEP_Out[463] = \<const0> ;
  assign LOCKSTEP_Out[464] = \<const0> ;
  assign LOCKSTEP_Out[465] = \<const0> ;
  assign LOCKSTEP_Out[466:497] = \^LOCKSTEP_Out [632:663];
  assign LOCKSTEP_Out[498] = \<const0> ;
  assign LOCKSTEP_Out[499] = \<const0> ;
  assign LOCKSTEP_Out[500] = \<const0> ;
  assign LOCKSTEP_Out[501] = \<const0> ;
  assign LOCKSTEP_Out[502] = \<const0> ;
  assign LOCKSTEP_Out[503] = \<const0> ;
  assign LOCKSTEP_Out[504] = \<const0> ;
  assign LOCKSTEP_Out[505] = \<const0> ;
  assign LOCKSTEP_Out[506] = \<const0> ;
  assign LOCKSTEP_Out[507] = \<const0> ;
  assign LOCKSTEP_Out[508] = \<const0> ;
  assign LOCKSTEP_Out[509] = \<const0> ;
  assign LOCKSTEP_Out[510] = \<const0> ;
  assign LOCKSTEP_Out[511] = \<const0> ;
  assign LOCKSTEP_Out[512] = \<const0> ;
  assign LOCKSTEP_Out[513] = \<const0> ;
  assign LOCKSTEP_Out[514] = \<const0> ;
  assign LOCKSTEP_Out[515] = \<const0> ;
  assign LOCKSTEP_Out[516] = \<const0> ;
  assign LOCKSTEP_Out[517] = \<const0> ;
  assign LOCKSTEP_Out[518] = \<const0> ;
  assign LOCKSTEP_Out[519] = \<const0> ;
  assign LOCKSTEP_Out[520] = \<const0> ;
  assign LOCKSTEP_Out[521] = \<const0> ;
  assign LOCKSTEP_Out[522] = \<const0> ;
  assign LOCKSTEP_Out[523] = \<const0> ;
  assign LOCKSTEP_Out[524] = \<const0> ;
  assign LOCKSTEP_Out[525] = \<const0> ;
  assign LOCKSTEP_Out[526] = \<const0> ;
  assign LOCKSTEP_Out[527] = \<const0> ;
  assign LOCKSTEP_Out[528] = \<const0> ;
  assign LOCKSTEP_Out[529] = \<const0> ;
  assign LOCKSTEP_Out[530] = \<const0> ;
  assign LOCKSTEP_Out[531] = \<const0> ;
  assign LOCKSTEP_Out[532] = \<const0> ;
  assign LOCKSTEP_Out[533] = \<const0> ;
  assign LOCKSTEP_Out[534] = \<const0> ;
  assign LOCKSTEP_Out[535] = \<const0> ;
  assign LOCKSTEP_Out[536] = \<const0> ;
  assign LOCKSTEP_Out[537] = \<const0> ;
  assign LOCKSTEP_Out[538] = \<const0> ;
  assign LOCKSTEP_Out[539] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[540] = \<const0> ;
  assign LOCKSTEP_Out[541] = \<const0> ;
  assign LOCKSTEP_Out[542] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[543] = \<const0> ;
  assign LOCKSTEP_Out[544] = \<const0> ;
  assign LOCKSTEP_Out[545] = \<const0> ;
  assign LOCKSTEP_Out[546] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[547] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[548] = \<const0> ;
  assign LOCKSTEP_Out[549] = \<const0> ;
  assign LOCKSTEP_Out[550] = \<const0> ;
  assign LOCKSTEP_Out[551] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[552] = \<const0> ;
  assign LOCKSTEP_Out[553] = \<const0> ;
  assign LOCKSTEP_Out[554] = \<const0> ;
  assign LOCKSTEP_Out[555:587] = \^LOCKSTEP_Out [555:587];
  assign LOCKSTEP_Out[588] = \<const0> ;
  assign LOCKSTEP_Out[589] = \<const0> ;
  assign LOCKSTEP_Out[590] = \<const0> ;
  assign LOCKSTEP_Out[591] = \<const0> ;
  assign LOCKSTEP_Out[592] = \<const0> ;
  assign LOCKSTEP_Out[593] = \<const0> ;
  assign LOCKSTEP_Out[594] = \<const0> ;
  assign LOCKSTEP_Out[595] = \<const0> ;
  assign LOCKSTEP_Out[596] = \<const0> ;
  assign LOCKSTEP_Out[597] = \<const0> ;
  assign LOCKSTEP_Out[598] = \<const0> ;
  assign LOCKSTEP_Out[599] = \<const0> ;
  assign LOCKSTEP_Out[600] = \<const0> ;
  assign LOCKSTEP_Out[601] = \<const0> ;
  assign LOCKSTEP_Out[602] = \<const0> ;
  assign LOCKSTEP_Out[603] = \<const0> ;
  assign LOCKSTEP_Out[604] = \<const0> ;
  assign LOCKSTEP_Out[605] = \<const0> ;
  assign LOCKSTEP_Out[606] = \<const0> ;
  assign LOCKSTEP_Out[607] = \<const0> ;
  assign LOCKSTEP_Out[608] = \<const0> ;
  assign LOCKSTEP_Out[609] = \<const0> ;
  assign LOCKSTEP_Out[610] = \<const0> ;
  assign LOCKSTEP_Out[611] = \<const0> ;
  assign LOCKSTEP_Out[612] = \<const0> ;
  assign LOCKSTEP_Out[613] = \<const0> ;
  assign LOCKSTEP_Out[614] = \<const0> ;
  assign LOCKSTEP_Out[615] = \<const0> ;
  assign LOCKSTEP_Out[616] = \<const0> ;
  assign LOCKSTEP_Out[617] = \<const0> ;
  assign LOCKSTEP_Out[618] = \<const0> ;
  assign LOCKSTEP_Out[619] = \<const0> ;
  assign LOCKSTEP_Out[620:623] = \^LOCKSTEP_Out [620:623];
  assign LOCKSTEP_Out[624] = \<const0> ;
  assign LOCKSTEP_Out[625] = \<const0> ;
  assign LOCKSTEP_Out[626] = \<const0> ;
  assign LOCKSTEP_Out[627] = \<const0> ;
  assign LOCKSTEP_Out[628] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[629] = \^LOCKSTEP_Out [629];
  assign LOCKSTEP_Out[630] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[631] = \<const0> ;
  assign LOCKSTEP_Out[632:663] = \^LOCKSTEP_Out [632:663];
  assign LOCKSTEP_Out[664] = \<const0> ;
  assign LOCKSTEP_Out[665] = \<const0> ;
  assign LOCKSTEP_Out[666] = \<const0> ;
  assign LOCKSTEP_Out[667] = \<const0> ;
  assign LOCKSTEP_Out[668] = \<const0> ;
  assign LOCKSTEP_Out[669] = \<const0> ;
  assign LOCKSTEP_Out[670] = \<const0> ;
  assign LOCKSTEP_Out[671] = \<const0> ;
  assign LOCKSTEP_Out[672] = \<const0> ;
  assign LOCKSTEP_Out[673] = \<const0> ;
  assign LOCKSTEP_Out[674] = \<const0> ;
  assign LOCKSTEP_Out[675] = \<const0> ;
  assign LOCKSTEP_Out[676] = \<const0> ;
  assign LOCKSTEP_Out[677] = \<const0> ;
  assign LOCKSTEP_Out[678] = \<const0> ;
  assign LOCKSTEP_Out[679] = \<const0> ;
  assign LOCKSTEP_Out[680] = \<const0> ;
  assign LOCKSTEP_Out[681] = \<const0> ;
  assign LOCKSTEP_Out[682] = \<const0> ;
  assign LOCKSTEP_Out[683] = \<const0> ;
  assign LOCKSTEP_Out[684] = \<const0> ;
  assign LOCKSTEP_Out[685] = \<const0> ;
  assign LOCKSTEP_Out[686] = \<const0> ;
  assign LOCKSTEP_Out[687] = \<const0> ;
  assign LOCKSTEP_Out[688] = \<const0> ;
  assign LOCKSTEP_Out[689] = \<const0> ;
  assign LOCKSTEP_Out[690] = \<const0> ;
  assign LOCKSTEP_Out[691] = \<const0> ;
  assign LOCKSTEP_Out[692] = \<const0> ;
  assign LOCKSTEP_Out[693] = \<const0> ;
  assign LOCKSTEP_Out[694] = \<const0> ;
  assign LOCKSTEP_Out[695] = \<const0> ;
  assign LOCKSTEP_Out[696] = \<const0> ;
  assign LOCKSTEP_Out[697] = \<const0> ;
  assign LOCKSTEP_Out[698] = \<const0> ;
  assign LOCKSTEP_Out[699] = \<const0> ;
  assign LOCKSTEP_Out[700] = \<const0> ;
  assign LOCKSTEP_Out[701] = \<const0> ;
  assign LOCKSTEP_Out[702] = \<const0> ;
  assign LOCKSTEP_Out[703] = \<const0> ;
  assign LOCKSTEP_Out[704] = \<const0> ;
  assign LOCKSTEP_Out[705] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[706] = \<const0> ;
  assign LOCKSTEP_Out[707] = \<const0> ;
  assign LOCKSTEP_Out[708] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[709] = \<const0> ;
  assign LOCKSTEP_Out[710] = \<const0> ;
  assign LOCKSTEP_Out[711] = \<const0> ;
  assign LOCKSTEP_Out[712] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[713] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[714] = \<const0> ;
  assign LOCKSTEP_Out[715] = \<const0> ;
  assign LOCKSTEP_Out[716] = \<const0> ;
  assign LOCKSTEP_Out[717] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[718] = \<const0> ;
  assign LOCKSTEP_Out[719] = \<const0> ;
  assign LOCKSTEP_Out[720] = \<const0> ;
  assign LOCKSTEP_Out[721] = \^LOCKSTEP_Out [721];
  assign LOCKSTEP_Out[722] = \^LOCKSTEP_Out [542];
  assign LOCKSTEP_Out[723] = \<const0> ;
  assign LOCKSTEP_Out[724] = \<const0> ;
  assign LOCKSTEP_Out[725] = \<const0> ;
  assign LOCKSTEP_Out[726] = \<const0> ;
  assign LOCKSTEP_Out[727] = \<const0> ;
  assign LOCKSTEP_Out[728] = \<const0> ;
  assign LOCKSTEP_Out[729] = \<const0> ;
  assign LOCKSTEP_Out[730] = \<const0> ;
  assign LOCKSTEP_Out[731] = \<const0> ;
  assign LOCKSTEP_Out[732] = \<const0> ;
  assign LOCKSTEP_Out[733] = \<const0> ;
  assign LOCKSTEP_Out[734] = \<const0> ;
  assign LOCKSTEP_Out[735] = \<const0> ;
  assign LOCKSTEP_Out[736] = \<const0> ;
  assign LOCKSTEP_Out[737] = \<const0> ;
  assign LOCKSTEP_Out[738] = \<const0> ;
  assign LOCKSTEP_Out[739] = \<const0> ;
  assign LOCKSTEP_Out[740] = \<const0> ;
  assign LOCKSTEP_Out[741] = \<const0> ;
  assign LOCKSTEP_Out[742] = \<const0> ;
  assign LOCKSTEP_Out[743] = \<const0> ;
  assign LOCKSTEP_Out[744] = \<const0> ;
  assign LOCKSTEP_Out[745] = \<const0> ;
  assign LOCKSTEP_Out[746] = \<const0> ;
  assign LOCKSTEP_Out[747] = \<const0> ;
  assign LOCKSTEP_Out[748] = \<const0> ;
  assign LOCKSTEP_Out[749] = \<const0> ;
  assign LOCKSTEP_Out[750] = \<const0> ;
  assign LOCKSTEP_Out[751] = \<const0> ;
  assign LOCKSTEP_Out[752] = \<const0> ;
  assign LOCKSTEP_Out[753] = \<const0> ;
  assign LOCKSTEP_Out[754] = \<const0> ;
  assign LOCKSTEP_Out[755] = \<const0> ;
  assign LOCKSTEP_Out[756] = \<const0> ;
  assign LOCKSTEP_Out[757] = \<const0> ;
  assign LOCKSTEP_Out[758] = \<const0> ;
  assign LOCKSTEP_Out[759] = \<const0> ;
  assign LOCKSTEP_Out[760] = \<const0> ;
  assign LOCKSTEP_Out[761] = \<const0> ;
  assign LOCKSTEP_Out[762] = \<const0> ;
  assign LOCKSTEP_Out[763] = \<const0> ;
  assign LOCKSTEP_Out[764] = \<const0> ;
  assign LOCKSTEP_Out[765] = \<const0> ;
  assign LOCKSTEP_Out[766] = \<const0> ;
  assign LOCKSTEP_Out[767] = \<const0> ;
  assign LOCKSTEP_Out[768] = \<const0> ;
  assign LOCKSTEP_Out[769] = \<const0> ;
  assign LOCKSTEP_Out[770] = \<const0> ;
  assign LOCKSTEP_Out[771] = \<const0> ;
  assign LOCKSTEP_Out[772] = \<const0> ;
  assign LOCKSTEP_Out[773] = \<const0> ;
  assign LOCKSTEP_Out[774] = \<const0> ;
  assign LOCKSTEP_Out[775] = \<const0> ;
  assign LOCKSTEP_Out[776] = \<const0> ;
  assign LOCKSTEP_Out[777] = \<const0> ;
  assign LOCKSTEP_Out[778] = \<const0> ;
  assign LOCKSTEP_Out[779] = \<const0> ;
  assign LOCKSTEP_Out[780] = \<const0> ;
  assign LOCKSTEP_Out[781] = \<const0> ;
  assign LOCKSTEP_Out[782] = \<const0> ;
  assign LOCKSTEP_Out[783] = \<const0> ;
  assign LOCKSTEP_Out[784] = \<const0> ;
  assign LOCKSTEP_Out[785] = \<const0> ;
  assign LOCKSTEP_Out[786] = \<const0> ;
  assign LOCKSTEP_Out[787] = \<const0> ;
  assign LOCKSTEP_Out[788] = \<const0> ;
  assign LOCKSTEP_Out[789] = \<const0> ;
  assign LOCKSTEP_Out[790] = \<const0> ;
  assign LOCKSTEP_Out[791] = \<const0> ;
  assign LOCKSTEP_Out[792] = \<const0> ;
  assign LOCKSTEP_Out[793] = \<const0> ;
  assign LOCKSTEP_Out[794] = \<const0> ;
  assign LOCKSTEP_Out[795] = \<const0> ;
  assign LOCKSTEP_Out[796] = \<const0> ;
  assign LOCKSTEP_Out[797] = \<const0> ;
  assign LOCKSTEP_Out[798] = \<const0> ;
  assign LOCKSTEP_Out[799] = \<const0> ;
  assign LOCKSTEP_Out[800] = \<const0> ;
  assign LOCKSTEP_Out[801] = \<const0> ;
  assign LOCKSTEP_Out[802] = \<const0> ;
  assign LOCKSTEP_Out[803] = \<const0> ;
  assign LOCKSTEP_Out[804] = \<const0> ;
  assign LOCKSTEP_Out[805] = \<const0> ;
  assign LOCKSTEP_Out[806] = \<const0> ;
  assign LOCKSTEP_Out[807] = \<const0> ;
  assign LOCKSTEP_Out[808] = \<const0> ;
  assign LOCKSTEP_Out[809] = \<const0> ;
  assign LOCKSTEP_Out[810] = \<const0> ;
  assign LOCKSTEP_Out[811] = \<const0> ;
  assign LOCKSTEP_Out[812] = \<const0> ;
  assign LOCKSTEP_Out[813] = \<const0> ;
  assign LOCKSTEP_Out[814] = \<const0> ;
  assign LOCKSTEP_Out[815] = \<const0> ;
  assign LOCKSTEP_Out[816] = \<const0> ;
  assign LOCKSTEP_Out[817] = \<const0> ;
  assign LOCKSTEP_Out[818] = \<const0> ;
  assign LOCKSTEP_Out[819] = \<const0> ;
  assign LOCKSTEP_Out[820] = \<const0> ;
  assign LOCKSTEP_Out[821] = \<const0> ;
  assign LOCKSTEP_Out[822] = \<const0> ;
  assign LOCKSTEP_Out[823] = \<const0> ;
  assign LOCKSTEP_Out[824] = \<const0> ;
  assign LOCKSTEP_Out[825] = \<const0> ;
  assign LOCKSTEP_Out[826] = \<const0> ;
  assign LOCKSTEP_Out[827] = \<const0> ;
  assign LOCKSTEP_Out[828] = \<const0> ;
  assign LOCKSTEP_Out[829] = \<const0> ;
  assign LOCKSTEP_Out[830] = \<const0> ;
  assign LOCKSTEP_Out[831] = \<const0> ;
  assign LOCKSTEP_Out[832] = \<const0> ;
  assign LOCKSTEP_Out[833] = \<const0> ;
  assign LOCKSTEP_Out[834] = \<const0> ;
  assign LOCKSTEP_Out[835] = \<const0> ;
  assign LOCKSTEP_Out[836] = \<const0> ;
  assign LOCKSTEP_Out[837] = \<const0> ;
  assign LOCKSTEP_Out[838] = \<const0> ;
  assign LOCKSTEP_Out[839] = \<const0> ;
  assign LOCKSTEP_Out[840] = \<const0> ;
  assign LOCKSTEP_Out[841] = \<const0> ;
  assign LOCKSTEP_Out[842] = \<const0> ;
  assign LOCKSTEP_Out[843] = \<const0> ;
  assign LOCKSTEP_Out[844] = \<const0> ;
  assign LOCKSTEP_Out[845] = \<const0> ;
  assign LOCKSTEP_Out[846] = \<const0> ;
  assign LOCKSTEP_Out[847] = \<const0> ;
  assign LOCKSTEP_Out[848] = \<const0> ;
  assign LOCKSTEP_Out[849] = \<const0> ;
  assign LOCKSTEP_Out[850] = \<const0> ;
  assign LOCKSTEP_Out[851] = \<const0> ;
  assign LOCKSTEP_Out[852] = \<const0> ;
  assign LOCKSTEP_Out[853] = \<const0> ;
  assign LOCKSTEP_Out[854] = \<const0> ;
  assign LOCKSTEP_Out[855] = \<const0> ;
  assign LOCKSTEP_Out[856] = \<const0> ;
  assign LOCKSTEP_Out[857] = \<const0> ;
  assign LOCKSTEP_Out[858] = \<const0> ;
  assign LOCKSTEP_Out[859] = \<const0> ;
  assign LOCKSTEP_Out[860] = \<const0> ;
  assign LOCKSTEP_Out[861] = \<const0> ;
  assign LOCKSTEP_Out[862] = \<const0> ;
  assign LOCKSTEP_Out[863] = \<const0> ;
  assign LOCKSTEP_Out[864] = \<const0> ;
  assign LOCKSTEP_Out[865] = \<const0> ;
  assign LOCKSTEP_Out[866] = \<const0> ;
  assign LOCKSTEP_Out[867] = \<const0> ;
  assign LOCKSTEP_Out[868] = \<const0> ;
  assign LOCKSTEP_Out[869] = \<const0> ;
  assign LOCKSTEP_Out[870] = \<const0> ;
  assign LOCKSTEP_Out[871] = \<const0> ;
  assign LOCKSTEP_Out[872] = \<const0> ;
  assign LOCKSTEP_Out[873] = \<const0> ;
  assign LOCKSTEP_Out[874] = \<const0> ;
  assign LOCKSTEP_Out[875] = \<const0> ;
  assign LOCKSTEP_Out[876] = \<const0> ;
  assign LOCKSTEP_Out[877] = \<const0> ;
  assign LOCKSTEP_Out[878] = \<const0> ;
  assign LOCKSTEP_Out[879] = \<const0> ;
  assign LOCKSTEP_Out[880] = \<const0> ;
  assign LOCKSTEP_Out[881] = \<const0> ;
  assign LOCKSTEP_Out[882] = \<const0> ;
  assign LOCKSTEP_Out[883] = \<const0> ;
  assign LOCKSTEP_Out[884] = \<const0> ;
  assign LOCKSTEP_Out[885] = \<const0> ;
  assign LOCKSTEP_Out[886] = \<const0> ;
  assign LOCKSTEP_Out[887] = \<const0> ;
  assign LOCKSTEP_Out[888] = \<const0> ;
  assign LOCKSTEP_Out[889] = \<const0> ;
  assign LOCKSTEP_Out[890] = \<const0> ;
  assign LOCKSTEP_Out[891] = \<const0> ;
  assign LOCKSTEP_Out[892] = \<const0> ;
  assign LOCKSTEP_Out[893] = \<const0> ;
  assign LOCKSTEP_Out[894] = \<const0> ;
  assign LOCKSTEP_Out[895] = \<const0> ;
  assign LOCKSTEP_Out[896] = \<const0> ;
  assign LOCKSTEP_Out[897] = \<const0> ;
  assign LOCKSTEP_Out[898] = \<const0> ;
  assign LOCKSTEP_Out[899] = \<const0> ;
  assign LOCKSTEP_Out[900] = \<const0> ;
  assign LOCKSTEP_Out[901] = \<const0> ;
  assign LOCKSTEP_Out[902] = \<const0> ;
  assign LOCKSTEP_Out[903] = \<const0> ;
  assign LOCKSTEP_Out[904] = \<const0> ;
  assign LOCKSTEP_Out[905] = \<const0> ;
  assign LOCKSTEP_Out[906] = \<const0> ;
  assign LOCKSTEP_Out[907] = \<const0> ;
  assign LOCKSTEP_Out[908] = \<const0> ;
  assign LOCKSTEP_Out[909] = \<const0> ;
  assign LOCKSTEP_Out[910] = \<const0> ;
  assign LOCKSTEP_Out[911] = \<const0> ;
  assign LOCKSTEP_Out[912] = \<const0> ;
  assign LOCKSTEP_Out[913] = \<const0> ;
  assign LOCKSTEP_Out[914] = \<const0> ;
  assign LOCKSTEP_Out[915] = \<const0> ;
  assign LOCKSTEP_Out[916] = \<const0> ;
  assign LOCKSTEP_Out[917] = \<const0> ;
  assign LOCKSTEP_Out[918] = \<const0> ;
  assign LOCKSTEP_Out[919] = \<const0> ;
  assign LOCKSTEP_Out[920] = \<const0> ;
  assign LOCKSTEP_Out[921] = \<const0> ;
  assign LOCKSTEP_Out[922] = \<const0> ;
  assign LOCKSTEP_Out[923] = \<const0> ;
  assign LOCKSTEP_Out[924] = \<const0> ;
  assign LOCKSTEP_Out[925] = \<const0> ;
  assign LOCKSTEP_Out[926] = \<const0> ;
  assign LOCKSTEP_Out[927] = \<const0> ;
  assign LOCKSTEP_Out[928] = \<const0> ;
  assign LOCKSTEP_Out[929] = \<const0> ;
  assign LOCKSTEP_Out[930] = \<const0> ;
  assign LOCKSTEP_Out[931] = \<const0> ;
  assign LOCKSTEP_Out[932] = \<const0> ;
  assign LOCKSTEP_Out[933] = \<const0> ;
  assign LOCKSTEP_Out[934] = \<const0> ;
  assign LOCKSTEP_Out[935] = \<const0> ;
  assign LOCKSTEP_Out[936] = \<const0> ;
  assign LOCKSTEP_Out[937] = \<const0> ;
  assign LOCKSTEP_Out[938] = \<const0> ;
  assign LOCKSTEP_Out[939] = \<const0> ;
  assign LOCKSTEP_Out[940] = \<const0> ;
  assign LOCKSTEP_Out[941] = \<const0> ;
  assign LOCKSTEP_Out[942] = \<const0> ;
  assign LOCKSTEP_Out[943] = \<const0> ;
  assign LOCKSTEP_Out[944] = \<const0> ;
  assign LOCKSTEP_Out[945] = \<const0> ;
  assign LOCKSTEP_Out[946] = \<const0> ;
  assign LOCKSTEP_Out[947] = \<const0> ;
  assign LOCKSTEP_Out[948] = \<const0> ;
  assign LOCKSTEP_Out[949] = \<const0> ;
  assign LOCKSTEP_Out[950] = \<const0> ;
  assign LOCKSTEP_Out[951] = \<const0> ;
  assign LOCKSTEP_Out[952] = \<const0> ;
  assign LOCKSTEP_Out[953] = \<const0> ;
  assign LOCKSTEP_Out[954] = \<const0> ;
  assign LOCKSTEP_Out[955] = \<const0> ;
  assign LOCKSTEP_Out[956] = \<const0> ;
  assign LOCKSTEP_Out[957] = \<const0> ;
  assign LOCKSTEP_Out[958] = \<const0> ;
  assign LOCKSTEP_Out[959] = \<const0> ;
  assign LOCKSTEP_Out[960] = \<const0> ;
  assign LOCKSTEP_Out[961] = \<const0> ;
  assign LOCKSTEP_Out[962] = \<const0> ;
  assign LOCKSTEP_Out[963] = \<const0> ;
  assign LOCKSTEP_Out[964] = \<const0> ;
  assign LOCKSTEP_Out[965] = \<const0> ;
  assign LOCKSTEP_Out[966] = \<const0> ;
  assign LOCKSTEP_Out[967] = \<const0> ;
  assign LOCKSTEP_Out[968] = \<const0> ;
  assign LOCKSTEP_Out[969] = \<const0> ;
  assign LOCKSTEP_Out[970] = \<const0> ;
  assign LOCKSTEP_Out[971] = \<const0> ;
  assign LOCKSTEP_Out[972] = \<const0> ;
  assign LOCKSTEP_Out[973] = \<const0> ;
  assign LOCKSTEP_Out[974] = \<const0> ;
  assign LOCKSTEP_Out[975] = \<const0> ;
  assign LOCKSTEP_Out[976] = \<const0> ;
  assign LOCKSTEP_Out[977] = \<const0> ;
  assign LOCKSTEP_Out[978] = \<const0> ;
  assign LOCKSTEP_Out[979] = \<const0> ;
  assign LOCKSTEP_Out[980] = \<const0> ;
  assign LOCKSTEP_Out[981] = \<const0> ;
  assign LOCKSTEP_Out[982] = \<const0> ;
  assign LOCKSTEP_Out[983] = \<const0> ;
  assign LOCKSTEP_Out[984] = \<const0> ;
  assign LOCKSTEP_Out[985] = \<const0> ;
  assign LOCKSTEP_Out[986] = \<const0> ;
  assign LOCKSTEP_Out[987] = \<const0> ;
  assign LOCKSTEP_Out[988] = \<const0> ;
  assign LOCKSTEP_Out[989] = \<const0> ;
  assign LOCKSTEP_Out[990] = \<const0> ;
  assign LOCKSTEP_Out[991] = \<const0> ;
  assign LOCKSTEP_Out[992] = \<const0> ;
  assign LOCKSTEP_Out[993] = \<const0> ;
  assign LOCKSTEP_Out[994] = \<const0> ;
  assign LOCKSTEP_Out[995] = \<const0> ;
  assign LOCKSTEP_Out[996] = \<const0> ;
  assign LOCKSTEP_Out[997] = \<const0> ;
  assign LOCKSTEP_Out[998] = \<const0> ;
  assign LOCKSTEP_Out[999] = \<const0> ;
  assign LOCKSTEP_Out[1000] = \<const0> ;
  assign LOCKSTEP_Out[1001] = \<const0> ;
  assign LOCKSTEP_Out[1002] = \<const0> ;
  assign LOCKSTEP_Out[1003] = \<const0> ;
  assign LOCKSTEP_Out[1004] = \<const0> ;
  assign LOCKSTEP_Out[1005] = \<const0> ;
  assign LOCKSTEP_Out[1006] = \<const0> ;
  assign LOCKSTEP_Out[1007] = \<const0> ;
  assign LOCKSTEP_Out[1008] = \<const0> ;
  assign LOCKSTEP_Out[1009] = \<const0> ;
  assign LOCKSTEP_Out[1010] = \<const0> ;
  assign LOCKSTEP_Out[1011] = \<const0> ;
  assign LOCKSTEP_Out[1012] = \<const0> ;
  assign LOCKSTEP_Out[1013] = \<const0> ;
  assign LOCKSTEP_Out[1014] = \<const0> ;
  assign LOCKSTEP_Out[1015] = \<const0> ;
  assign LOCKSTEP_Out[1016] = \<const0> ;
  assign LOCKSTEP_Out[1017] = \<const0> ;
  assign LOCKSTEP_Out[1018] = \<const0> ;
  assign LOCKSTEP_Out[1019] = \<const0> ;
  assign LOCKSTEP_Out[1020] = \<const0> ;
  assign LOCKSTEP_Out[1021] = \<const0> ;
  assign LOCKSTEP_Out[1022] = \<const0> ;
  assign LOCKSTEP_Out[1023] = \<const0> ;
  assign LOCKSTEP_Out[1024] = \<const0> ;
  assign LOCKSTEP_Out[1025] = \<const0> ;
  assign LOCKSTEP_Out[1026] = \<const0> ;
  assign LOCKSTEP_Out[1027] = \<const0> ;
  assign LOCKSTEP_Out[1028] = \<const0> ;
  assign LOCKSTEP_Out[1029] = \<const0> ;
  assign LOCKSTEP_Out[1030] = \<const0> ;
  assign LOCKSTEP_Out[1031] = \<const0> ;
  assign LOCKSTEP_Out[1032] = \<const0> ;
  assign LOCKSTEP_Out[1033] = \<const0> ;
  assign LOCKSTEP_Out[1034] = \<const0> ;
  assign LOCKSTEP_Out[1035] = \<const0> ;
  assign LOCKSTEP_Out[1036] = \<const0> ;
  assign LOCKSTEP_Out[1037] = \<const0> ;
  assign LOCKSTEP_Out[1038] = \<const0> ;
  assign LOCKSTEP_Out[1039] = \<const0> ;
  assign LOCKSTEP_Out[1040] = \<const0> ;
  assign LOCKSTEP_Out[1041] = \<const0> ;
  assign LOCKSTEP_Out[1042] = \<const0> ;
  assign LOCKSTEP_Out[1043] = \<const0> ;
  assign LOCKSTEP_Out[1044] = \<const0> ;
  assign LOCKSTEP_Out[1045] = \<const0> ;
  assign LOCKSTEP_Out[1046] = \<const0> ;
  assign LOCKSTEP_Out[1047] = \<const0> ;
  assign LOCKSTEP_Out[1048] = \<const0> ;
  assign LOCKSTEP_Out[1049] = \<const0> ;
  assign LOCKSTEP_Out[1050] = \<const0> ;
  assign LOCKSTEP_Out[1051] = \<const0> ;
  assign LOCKSTEP_Out[1052] = \<const0> ;
  assign LOCKSTEP_Out[1053] = \<const0> ;
  assign LOCKSTEP_Out[1054] = \<const0> ;
  assign LOCKSTEP_Out[1055] = \<const0> ;
  assign LOCKSTEP_Out[1056] = \<const0> ;
  assign LOCKSTEP_Out[1057] = \<const0> ;
  assign LOCKSTEP_Out[1058] = \<const0> ;
  assign LOCKSTEP_Out[1059] = \<const0> ;
  assign LOCKSTEP_Out[1060] = \<const0> ;
  assign LOCKSTEP_Out[1061] = \<const0> ;
  assign LOCKSTEP_Out[1062] = \<const0> ;
  assign LOCKSTEP_Out[1063] = \<const0> ;
  assign LOCKSTEP_Out[1064] = \<const0> ;
  assign LOCKSTEP_Out[1065] = \<const0> ;
  assign LOCKSTEP_Out[1066] = \<const0> ;
  assign LOCKSTEP_Out[1067] = \<const0> ;
  assign LOCKSTEP_Out[1068] = \<const0> ;
  assign LOCKSTEP_Out[1069] = \<const0> ;
  assign LOCKSTEP_Out[1070] = \<const0> ;
  assign LOCKSTEP_Out[1071] = \<const0> ;
  assign LOCKSTEP_Out[1072] = \<const0> ;
  assign LOCKSTEP_Out[1073] = \<const0> ;
  assign LOCKSTEP_Out[1074] = \<const0> ;
  assign LOCKSTEP_Out[1075] = \<const0> ;
  assign LOCKSTEP_Out[1076] = \<const0> ;
  assign LOCKSTEP_Out[1077] = \<const0> ;
  assign LOCKSTEP_Out[1078] = \<const0> ;
  assign LOCKSTEP_Out[1079] = \<const0> ;
  assign LOCKSTEP_Out[1080] = \<const0> ;
  assign LOCKSTEP_Out[1081] = \<const0> ;
  assign LOCKSTEP_Out[1082] = \<const0> ;
  assign LOCKSTEP_Out[1083] = \<const0> ;
  assign LOCKSTEP_Out[1084] = \<const0> ;
  assign LOCKSTEP_Out[1085] = \<const0> ;
  assign LOCKSTEP_Out[1086] = \<const0> ;
  assign LOCKSTEP_Out[1087] = \<const0> ;
  assign LOCKSTEP_Out[1088] = \<const0> ;
  assign LOCKSTEP_Out[1089] = \<const0> ;
  assign LOCKSTEP_Out[1090] = \<const0> ;
  assign LOCKSTEP_Out[1091] = \<const0> ;
  assign LOCKSTEP_Out[1092] = \<const0> ;
  assign LOCKSTEP_Out[1093] = \<const0> ;
  assign LOCKSTEP_Out[1094] = \<const0> ;
  assign LOCKSTEP_Out[1095] = \<const0> ;
  assign LOCKSTEP_Out[1096] = \<const0> ;
  assign LOCKSTEP_Out[1097] = \<const0> ;
  assign LOCKSTEP_Out[1098] = \<const0> ;
  assign LOCKSTEP_Out[1099] = \<const0> ;
  assign LOCKSTEP_Out[1100] = \<const0> ;
  assign LOCKSTEP_Out[1101] = \<const0> ;
  assign LOCKSTEP_Out[1102] = \<const0> ;
  assign LOCKSTEP_Out[1103] = \<const0> ;
  assign LOCKSTEP_Out[1104] = \<const0> ;
  assign LOCKSTEP_Out[1105] = \<const0> ;
  assign LOCKSTEP_Out[1106] = \<const0> ;
  assign LOCKSTEP_Out[1107] = \<const0> ;
  assign LOCKSTEP_Out[1108] = \<const0> ;
  assign LOCKSTEP_Out[1109] = \<const0> ;
  assign LOCKSTEP_Out[1110] = \<const0> ;
  assign LOCKSTEP_Out[1111] = \<const0> ;
  assign LOCKSTEP_Out[1112] = \<const0> ;
  assign LOCKSTEP_Out[1113] = \<const0> ;
  assign LOCKSTEP_Out[1114] = \<const0> ;
  assign LOCKSTEP_Out[1115] = \<const0> ;
  assign LOCKSTEP_Out[1116] = \<const0> ;
  assign LOCKSTEP_Out[1117] = \<const0> ;
  assign LOCKSTEP_Out[1118] = \<const0> ;
  assign LOCKSTEP_Out[1119] = \<const0> ;
  assign LOCKSTEP_Out[1120] = \<const0> ;
  assign LOCKSTEP_Out[1121] = \<const0> ;
  assign LOCKSTEP_Out[1122] = \<const0> ;
  assign LOCKSTEP_Out[1123] = \<const0> ;
  assign LOCKSTEP_Out[1124] = \<const0> ;
  assign LOCKSTEP_Out[1125] = \<const0> ;
  assign LOCKSTEP_Out[1126] = \<const0> ;
  assign LOCKSTEP_Out[1127] = \<const0> ;
  assign LOCKSTEP_Out[1128] = \<const0> ;
  assign LOCKSTEP_Out[1129] = \<const0> ;
  assign LOCKSTEP_Out[1130] = \<const0> ;
  assign LOCKSTEP_Out[1131] = \<const0> ;
  assign LOCKSTEP_Out[1132] = \<const0> ;
  assign LOCKSTEP_Out[1133] = \<const0> ;
  assign LOCKSTEP_Out[1134] = \<const0> ;
  assign LOCKSTEP_Out[1135] = \<const0> ;
  assign LOCKSTEP_Out[1136] = \<const0> ;
  assign LOCKSTEP_Out[1137] = \<const0> ;
  assign LOCKSTEP_Out[1138] = \<const0> ;
  assign LOCKSTEP_Out[1139] = \<const0> ;
  assign LOCKSTEP_Out[1140] = \<const0> ;
  assign LOCKSTEP_Out[1141] = \<const0> ;
  assign LOCKSTEP_Out[1142] = \<const0> ;
  assign LOCKSTEP_Out[1143] = \<const0> ;
  assign LOCKSTEP_Out[1144] = \<const0> ;
  assign LOCKSTEP_Out[1145] = \<const0> ;
  assign LOCKSTEP_Out[1146] = \<const0> ;
  assign LOCKSTEP_Out[1147] = \<const0> ;
  assign LOCKSTEP_Out[1148] = \<const0> ;
  assign LOCKSTEP_Out[1149] = \<const0> ;
  assign LOCKSTEP_Out[1150] = \<const0> ;
  assign LOCKSTEP_Out[1151] = \<const0> ;
  assign LOCKSTEP_Out[1152] = \<const0> ;
  assign LOCKSTEP_Out[1153] = \<const0> ;
  assign LOCKSTEP_Out[1154] = \<const0> ;
  assign LOCKSTEP_Out[1155] = \<const0> ;
  assign LOCKSTEP_Out[1156] = \<const0> ;
  assign LOCKSTEP_Out[1157] = \<const0> ;
  assign LOCKSTEP_Out[1158] = \<const0> ;
  assign LOCKSTEP_Out[1159] = \<const0> ;
  assign LOCKSTEP_Out[1160] = \<const0> ;
  assign LOCKSTEP_Out[1161] = \<const0> ;
  assign LOCKSTEP_Out[1162] = \<const0> ;
  assign LOCKSTEP_Out[1163] = \<const0> ;
  assign LOCKSTEP_Out[1164] = \<const0> ;
  assign LOCKSTEP_Out[1165] = \<const0> ;
  assign LOCKSTEP_Out[1166] = \<const0> ;
  assign LOCKSTEP_Out[1167] = \<const0> ;
  assign LOCKSTEP_Out[1168] = \<const0> ;
  assign LOCKSTEP_Out[1169] = \<const0> ;
  assign LOCKSTEP_Out[1170] = \<const0> ;
  assign LOCKSTEP_Out[1171] = \<const0> ;
  assign LOCKSTEP_Out[1172] = \<const0> ;
  assign LOCKSTEP_Out[1173] = \<const0> ;
  assign LOCKSTEP_Out[1174] = \<const0> ;
  assign LOCKSTEP_Out[1175] = \<const0> ;
  assign LOCKSTEP_Out[1176] = \<const0> ;
  assign LOCKSTEP_Out[1177] = \<const0> ;
  assign LOCKSTEP_Out[1178] = \<const0> ;
  assign LOCKSTEP_Out[1179] = \<const0> ;
  assign LOCKSTEP_Out[1180] = \<const0> ;
  assign LOCKSTEP_Out[1181] = \<const0> ;
  assign LOCKSTEP_Out[1182] = \<const0> ;
  assign LOCKSTEP_Out[1183] = \<const0> ;
  assign LOCKSTEP_Out[1184] = \<const0> ;
  assign LOCKSTEP_Out[1185] = \<const0> ;
  assign LOCKSTEP_Out[1186] = \<const0> ;
  assign LOCKSTEP_Out[1187] = \<const0> ;
  assign LOCKSTEP_Out[1188] = \<const0> ;
  assign LOCKSTEP_Out[1189] = \<const0> ;
  assign LOCKSTEP_Out[1190] = \<const0> ;
  assign LOCKSTEP_Out[1191] = \<const0> ;
  assign LOCKSTEP_Out[1192] = \<const0> ;
  assign LOCKSTEP_Out[1193] = \<const0> ;
  assign LOCKSTEP_Out[1194] = \<const0> ;
  assign LOCKSTEP_Out[1195] = \<const0> ;
  assign LOCKSTEP_Out[1196] = \<const0> ;
  assign LOCKSTEP_Out[1197] = \<const0> ;
  assign LOCKSTEP_Out[1198] = \<const0> ;
  assign LOCKSTEP_Out[1199] = \<const0> ;
  assign LOCKSTEP_Out[1200] = \<const0> ;
  assign LOCKSTEP_Out[1201] = \<const0> ;
  assign LOCKSTEP_Out[1202] = \<const0> ;
  assign LOCKSTEP_Out[1203] = \<const0> ;
  assign LOCKSTEP_Out[1204] = \<const0> ;
  assign LOCKSTEP_Out[1205] = \<const0> ;
  assign LOCKSTEP_Out[1206] = \<const0> ;
  assign LOCKSTEP_Out[1207] = \<const0> ;
  assign LOCKSTEP_Out[1208] = \<const0> ;
  assign LOCKSTEP_Out[1209] = \<const0> ;
  assign LOCKSTEP_Out[1210] = \<const0> ;
  assign LOCKSTEP_Out[1211] = \<const0> ;
  assign LOCKSTEP_Out[1212] = \<const0> ;
  assign LOCKSTEP_Out[1213] = \<const0> ;
  assign LOCKSTEP_Out[1214] = \<const0> ;
  assign LOCKSTEP_Out[1215] = \<const0> ;
  assign LOCKSTEP_Out[1216] = \<const0> ;
  assign LOCKSTEP_Out[1217] = \<const0> ;
  assign LOCKSTEP_Out[1218] = \<const0> ;
  assign LOCKSTEP_Out[1219] = \<const0> ;
  assign LOCKSTEP_Out[1220] = \<const0> ;
  assign LOCKSTEP_Out[1221] = \<const0> ;
  assign LOCKSTEP_Out[1222] = \<const0> ;
  assign LOCKSTEP_Out[1223] = \<const0> ;
  assign LOCKSTEP_Out[1224] = \<const0> ;
  assign LOCKSTEP_Out[1225] = \<const0> ;
  assign LOCKSTEP_Out[1226] = \<const0> ;
  assign LOCKSTEP_Out[1227] = \<const0> ;
  assign LOCKSTEP_Out[1228] = \<const0> ;
  assign LOCKSTEP_Out[1229] = \<const0> ;
  assign LOCKSTEP_Out[1230] = \<const0> ;
  assign LOCKSTEP_Out[1231] = \<const0> ;
  assign LOCKSTEP_Out[1232] = \<const0> ;
  assign LOCKSTEP_Out[1233] = \<const0> ;
  assign LOCKSTEP_Out[1234] = \<const0> ;
  assign LOCKSTEP_Out[1235] = \<const0> ;
  assign LOCKSTEP_Out[1236] = \<const0> ;
  assign LOCKSTEP_Out[1237] = \<const0> ;
  assign LOCKSTEP_Out[1238] = \<const0> ;
  assign LOCKSTEP_Out[1239] = \<const0> ;
  assign LOCKSTEP_Out[1240] = \<const0> ;
  assign LOCKSTEP_Out[1241] = \<const0> ;
  assign LOCKSTEP_Out[1242] = \<const0> ;
  assign LOCKSTEP_Out[1243] = \<const0> ;
  assign LOCKSTEP_Out[1244] = \<const0> ;
  assign LOCKSTEP_Out[1245] = \<const0> ;
  assign LOCKSTEP_Out[1246] = \<const0> ;
  assign LOCKSTEP_Out[1247] = \<const0> ;
  assign LOCKSTEP_Out[1248] = \<const0> ;
  assign LOCKSTEP_Out[1249] = \<const0> ;
  assign LOCKSTEP_Out[1250] = \<const0> ;
  assign LOCKSTEP_Out[1251] = \<const0> ;
  assign LOCKSTEP_Out[1252] = \<const0> ;
  assign LOCKSTEP_Out[1253] = \<const0> ;
  assign LOCKSTEP_Out[1254] = \<const0> ;
  assign LOCKSTEP_Out[1255] = \<const0> ;
  assign LOCKSTEP_Out[1256] = \<const0> ;
  assign LOCKSTEP_Out[1257] = \<const0> ;
  assign LOCKSTEP_Out[1258] = \<const0> ;
  assign LOCKSTEP_Out[1259] = \<const0> ;
  assign LOCKSTEP_Out[1260] = \<const0> ;
  assign LOCKSTEP_Out[1261] = \<const0> ;
  assign LOCKSTEP_Out[1262] = \<const0> ;
  assign LOCKSTEP_Out[1263] = \<const0> ;
  assign LOCKSTEP_Out[1264] = \<const0> ;
  assign LOCKSTEP_Out[1265] = \<const0> ;
  assign LOCKSTEP_Out[1266] = \<const0> ;
  assign LOCKSTEP_Out[1267] = \<const0> ;
  assign LOCKSTEP_Out[1268] = \<const0> ;
  assign LOCKSTEP_Out[1269] = \<const0> ;
  assign LOCKSTEP_Out[1270] = \<const0> ;
  assign LOCKSTEP_Out[1271] = \<const0> ;
  assign LOCKSTEP_Out[1272] = \<const0> ;
  assign LOCKSTEP_Out[1273] = \<const0> ;
  assign LOCKSTEP_Out[1274] = \<const0> ;
  assign LOCKSTEP_Out[1275] = \<const0> ;
  assign LOCKSTEP_Out[1276] = \<const0> ;
  assign LOCKSTEP_Out[1277] = \<const0> ;
  assign LOCKSTEP_Out[1278] = \<const0> ;
  assign LOCKSTEP_Out[1279] = \<const0> ;
  assign LOCKSTEP_Out[1280] = \<const0> ;
  assign LOCKSTEP_Out[1281] = \<const0> ;
  assign LOCKSTEP_Out[1282] = \<const0> ;
  assign LOCKSTEP_Out[1283] = \<const0> ;
  assign LOCKSTEP_Out[1284] = \<const0> ;
  assign LOCKSTEP_Out[1285] = \<const0> ;
  assign LOCKSTEP_Out[1286] = \<const0> ;
  assign LOCKSTEP_Out[1287] = \<const0> ;
  assign LOCKSTEP_Out[1288] = \<const0> ;
  assign LOCKSTEP_Out[1289] = \<const0> ;
  assign LOCKSTEP_Out[1290] = \<const0> ;
  assign LOCKSTEP_Out[1291] = \<const0> ;
  assign LOCKSTEP_Out[1292] = \<const0> ;
  assign LOCKSTEP_Out[1293] = \<const0> ;
  assign LOCKSTEP_Out[1294] = \<const0> ;
  assign LOCKSTEP_Out[1295] = \<const0> ;
  assign LOCKSTEP_Out[1296] = \<const0> ;
  assign LOCKSTEP_Out[1297] = \<const0> ;
  assign LOCKSTEP_Out[1298] = \<const0> ;
  assign LOCKSTEP_Out[1299] = \<const0> ;
  assign LOCKSTEP_Out[1300] = \<const0> ;
  assign LOCKSTEP_Out[1301] = \<const0> ;
  assign LOCKSTEP_Out[1302] = \<const0> ;
  assign LOCKSTEP_Out[1303] = \<const0> ;
  assign LOCKSTEP_Out[1304] = \<const0> ;
  assign LOCKSTEP_Out[1305] = \<const0> ;
  assign LOCKSTEP_Out[1306] = \<const0> ;
  assign LOCKSTEP_Out[1307] = \<const0> ;
  assign LOCKSTEP_Out[1308] = \<const0> ;
  assign LOCKSTEP_Out[1309] = \<const0> ;
  assign LOCKSTEP_Out[1310] = \<const0> ;
  assign LOCKSTEP_Out[1311] = \<const0> ;
  assign LOCKSTEP_Out[1312] = \<const0> ;
  assign LOCKSTEP_Out[1313] = \<const0> ;
  assign LOCKSTEP_Out[1314] = \<const0> ;
  assign LOCKSTEP_Out[1315] = \<const0> ;
  assign LOCKSTEP_Out[1316] = \<const0> ;
  assign LOCKSTEP_Out[1317] = \<const0> ;
  assign LOCKSTEP_Out[1318] = \<const0> ;
  assign LOCKSTEP_Out[1319] = \<const0> ;
  assign LOCKSTEP_Out[1320] = \<const0> ;
  assign LOCKSTEP_Out[1321] = \<const0> ;
  assign LOCKSTEP_Out[1322] = \<const0> ;
  assign LOCKSTEP_Out[1323] = \<const0> ;
  assign LOCKSTEP_Out[1324] = \<const0> ;
  assign LOCKSTEP_Out[1325] = \<const0> ;
  assign LOCKSTEP_Out[1326] = \<const0> ;
  assign LOCKSTEP_Out[1327] = \<const0> ;
  assign LOCKSTEP_Out[1328] = \<const0> ;
  assign LOCKSTEP_Out[1329] = \<const0> ;
  assign LOCKSTEP_Out[1330] = \<const0> ;
  assign LOCKSTEP_Out[1331] = \<const0> ;
  assign LOCKSTEP_Out[1332] = \<const0> ;
  assign LOCKSTEP_Out[1333] = \<const0> ;
  assign LOCKSTEP_Out[1334] = \<const0> ;
  assign LOCKSTEP_Out[1335] = \<const0> ;
  assign LOCKSTEP_Out[1336] = \<const0> ;
  assign LOCKSTEP_Out[1337] = \<const0> ;
  assign LOCKSTEP_Out[1338] = \<const0> ;
  assign LOCKSTEP_Out[1339] = \<const0> ;
  assign LOCKSTEP_Out[1340] = \<const0> ;
  assign LOCKSTEP_Out[1341] = \<const0> ;
  assign LOCKSTEP_Out[1342] = \<const0> ;
  assign LOCKSTEP_Out[1343] = \<const0> ;
  assign LOCKSTEP_Out[1344] = \<const0> ;
  assign LOCKSTEP_Out[1345] = \<const0> ;
  assign LOCKSTEP_Out[1346] = \<const0> ;
  assign LOCKSTEP_Out[1347] = \<const0> ;
  assign LOCKSTEP_Out[1348] = \<const0> ;
  assign LOCKSTEP_Out[1349] = \<const0> ;
  assign LOCKSTEP_Out[1350] = \<const0> ;
  assign LOCKSTEP_Out[1351] = \<const0> ;
  assign LOCKSTEP_Out[1352] = \<const0> ;
  assign LOCKSTEP_Out[1353] = \<const0> ;
  assign LOCKSTEP_Out[1354] = \<const0> ;
  assign LOCKSTEP_Out[1355] = \<const0> ;
  assign LOCKSTEP_Out[1356] = \<const0> ;
  assign LOCKSTEP_Out[1357] = \<const0> ;
  assign LOCKSTEP_Out[1358] = \<const0> ;
  assign LOCKSTEP_Out[1359] = \<const0> ;
  assign LOCKSTEP_Out[1360] = \<const0> ;
  assign LOCKSTEP_Out[1361] = \<const0> ;
  assign LOCKSTEP_Out[1362] = \<const0> ;
  assign LOCKSTEP_Out[1363] = \<const0> ;
  assign LOCKSTEP_Out[1364] = \<const0> ;
  assign LOCKSTEP_Out[1365] = \<const0> ;
  assign LOCKSTEP_Out[1366] = \<const0> ;
  assign LOCKSTEP_Out[1367] = \<const0> ;
  assign LOCKSTEP_Out[1368] = \<const0> ;
  assign LOCKSTEP_Out[1369] = \<const0> ;
  assign LOCKSTEP_Out[1370] = \<const0> ;
  assign LOCKSTEP_Out[1371] = \<const0> ;
  assign LOCKSTEP_Out[1372] = \<const0> ;
  assign LOCKSTEP_Out[1373] = \<const0> ;
  assign LOCKSTEP_Out[1374] = \<const0> ;
  assign LOCKSTEP_Out[1375] = \<const0> ;
  assign LOCKSTEP_Out[1376] = \<const0> ;
  assign LOCKSTEP_Out[1377] = \<const0> ;
  assign LOCKSTEP_Out[1378] = \<const0> ;
  assign LOCKSTEP_Out[1379] = \<const0> ;
  assign LOCKSTEP_Out[1380] = \<const0> ;
  assign LOCKSTEP_Out[1381] = \<const0> ;
  assign LOCKSTEP_Out[1382] = \<const0> ;
  assign LOCKSTEP_Out[1383] = \<const0> ;
  assign LOCKSTEP_Out[1384] = \<const0> ;
  assign LOCKSTEP_Out[1385] = \<const0> ;
  assign LOCKSTEP_Out[1386] = \<const0> ;
  assign LOCKSTEP_Out[1387] = \<const0> ;
  assign LOCKSTEP_Out[1388] = \<const0> ;
  assign LOCKSTEP_Out[1389] = \<const0> ;
  assign LOCKSTEP_Out[1390] = \<const0> ;
  assign LOCKSTEP_Out[1391] = \<const0> ;
  assign LOCKSTEP_Out[1392] = \<const0> ;
  assign LOCKSTEP_Out[1393] = \<const0> ;
  assign LOCKSTEP_Out[1394] = \<const0> ;
  assign LOCKSTEP_Out[1395] = \<const0> ;
  assign LOCKSTEP_Out[1396] = \<const0> ;
  assign LOCKSTEP_Out[1397] = \<const0> ;
  assign LOCKSTEP_Out[1398] = \<const0> ;
  assign LOCKSTEP_Out[1399] = \<const0> ;
  assign LOCKSTEP_Out[1400] = \<const0> ;
  assign LOCKSTEP_Out[1401] = \<const0> ;
  assign LOCKSTEP_Out[1402] = \<const0> ;
  assign LOCKSTEP_Out[1403] = \<const0> ;
  assign LOCKSTEP_Out[1404] = \<const0> ;
  assign LOCKSTEP_Out[1405] = \<const0> ;
  assign LOCKSTEP_Out[1406] = \<const0> ;
  assign LOCKSTEP_Out[1407] = \<const0> ;
  assign LOCKSTEP_Out[1408] = \<const0> ;
  assign LOCKSTEP_Out[1409] = \<const0> ;
  assign LOCKSTEP_Out[1410] = \<const0> ;
  assign LOCKSTEP_Out[1411] = \<const0> ;
  assign LOCKSTEP_Out[1412] = \<const0> ;
  assign LOCKSTEP_Out[1413] = \<const0> ;
  assign LOCKSTEP_Out[1414] = \<const0> ;
  assign LOCKSTEP_Out[1415] = \<const0> ;
  assign LOCKSTEP_Out[1416] = \<const0> ;
  assign LOCKSTEP_Out[1417] = \<const0> ;
  assign LOCKSTEP_Out[1418] = \<const0> ;
  assign LOCKSTEP_Out[1419] = \<const0> ;
  assign LOCKSTEP_Out[1420] = \<const0> ;
  assign LOCKSTEP_Out[1421] = \<const0> ;
  assign LOCKSTEP_Out[1422] = \<const0> ;
  assign LOCKSTEP_Out[1423] = \<const0> ;
  assign LOCKSTEP_Out[1424] = \<const0> ;
  assign LOCKSTEP_Out[1425] = \<const0> ;
  assign LOCKSTEP_Out[1426] = \<const0> ;
  assign LOCKSTEP_Out[1427] = \<const0> ;
  assign LOCKSTEP_Out[1428] = \<const0> ;
  assign LOCKSTEP_Out[1429] = \<const0> ;
  assign LOCKSTEP_Out[1430] = \<const0> ;
  assign LOCKSTEP_Out[1431] = \<const0> ;
  assign LOCKSTEP_Out[1432] = \<const0> ;
  assign LOCKSTEP_Out[1433] = \<const0> ;
  assign LOCKSTEP_Out[1434] = \<const0> ;
  assign LOCKSTEP_Out[1435] = \<const0> ;
  assign LOCKSTEP_Out[1436] = \<const0> ;
  assign LOCKSTEP_Out[1437] = \<const0> ;
  assign LOCKSTEP_Out[1438] = \<const0> ;
  assign LOCKSTEP_Out[1439] = \<const0> ;
  assign LOCKSTEP_Out[1440] = \<const0> ;
  assign LOCKSTEP_Out[1441] = \<const0> ;
  assign LOCKSTEP_Out[1442] = \<const0> ;
  assign LOCKSTEP_Out[1443] = \<const0> ;
  assign LOCKSTEP_Out[1444] = \<const0> ;
  assign LOCKSTEP_Out[1445] = \<const0> ;
  assign LOCKSTEP_Out[1446] = \<const0> ;
  assign LOCKSTEP_Out[1447] = \<const0> ;
  assign LOCKSTEP_Out[1448] = \<const0> ;
  assign LOCKSTEP_Out[1449] = \<const0> ;
  assign LOCKSTEP_Out[1450] = \<const0> ;
  assign LOCKSTEP_Out[1451] = \<const0> ;
  assign LOCKSTEP_Out[1452] = \<const0> ;
  assign LOCKSTEP_Out[1453] = \<const0> ;
  assign LOCKSTEP_Out[1454] = \<const0> ;
  assign LOCKSTEP_Out[1455] = \<const0> ;
  assign LOCKSTEP_Out[1456] = \<const0> ;
  assign LOCKSTEP_Out[1457] = \<const0> ;
  assign LOCKSTEP_Out[1458] = \<const0> ;
  assign LOCKSTEP_Out[1459] = \<const0> ;
  assign LOCKSTEP_Out[1460] = \<const0> ;
  assign LOCKSTEP_Out[1461] = \<const0> ;
  assign LOCKSTEP_Out[1462] = \<const0> ;
  assign LOCKSTEP_Out[1463] = \<const0> ;
  assign LOCKSTEP_Out[1464] = \<const0> ;
  assign LOCKSTEP_Out[1465] = \<const0> ;
  assign LOCKSTEP_Out[1466] = \<const0> ;
  assign LOCKSTEP_Out[1467] = \<const0> ;
  assign LOCKSTEP_Out[1468] = \<const0> ;
  assign LOCKSTEP_Out[1469] = \<const0> ;
  assign LOCKSTEP_Out[1470] = \<const0> ;
  assign LOCKSTEP_Out[1471] = \<const0> ;
  assign LOCKSTEP_Out[1472] = \<const0> ;
  assign LOCKSTEP_Out[1473] = \<const0> ;
  assign LOCKSTEP_Out[1474] = \<const0> ;
  assign LOCKSTEP_Out[1475] = \<const0> ;
  assign LOCKSTEP_Out[1476] = \<const0> ;
  assign LOCKSTEP_Out[1477] = \<const0> ;
  assign LOCKSTEP_Out[1478] = \<const0> ;
  assign LOCKSTEP_Out[1479] = \<const0> ;
  assign LOCKSTEP_Out[1480] = \<const0> ;
  assign LOCKSTEP_Out[1481] = \<const0> ;
  assign LOCKSTEP_Out[1482] = \<const0> ;
  assign LOCKSTEP_Out[1483] = \<const0> ;
  assign LOCKSTEP_Out[1484] = \<const0> ;
  assign LOCKSTEP_Out[1485] = \<const0> ;
  assign LOCKSTEP_Out[1486] = \<const0> ;
  assign LOCKSTEP_Out[1487] = \<const0> ;
  assign LOCKSTEP_Out[1488] = \<const0> ;
  assign LOCKSTEP_Out[1489] = \<const0> ;
  assign LOCKSTEP_Out[1490] = \<const0> ;
  assign LOCKSTEP_Out[1491] = \<const0> ;
  assign LOCKSTEP_Out[1492] = \<const0> ;
  assign LOCKSTEP_Out[1493] = \<const0> ;
  assign LOCKSTEP_Out[1494] = \<const0> ;
  assign LOCKSTEP_Out[1495] = \<const0> ;
  assign LOCKSTEP_Out[1496] = \<const0> ;
  assign LOCKSTEP_Out[1497] = \<const0> ;
  assign LOCKSTEP_Out[1498] = \<const0> ;
  assign LOCKSTEP_Out[1499] = \<const0> ;
  assign LOCKSTEP_Out[1500] = \<const0> ;
  assign LOCKSTEP_Out[1501] = \<const0> ;
  assign LOCKSTEP_Out[1502] = \<const0> ;
  assign LOCKSTEP_Out[1503] = \<const0> ;
  assign LOCKSTEP_Out[1504] = \<const0> ;
  assign LOCKSTEP_Out[1505] = \<const0> ;
  assign LOCKSTEP_Out[1506] = \<const0> ;
  assign LOCKSTEP_Out[1507] = \<const0> ;
  assign LOCKSTEP_Out[1508] = \<const0> ;
  assign LOCKSTEP_Out[1509] = \<const0> ;
  assign LOCKSTEP_Out[1510] = \<const0> ;
  assign LOCKSTEP_Out[1511] = \<const0> ;
  assign LOCKSTEP_Out[1512] = \<const0> ;
  assign LOCKSTEP_Out[1513] = \<const0> ;
  assign LOCKSTEP_Out[1514] = \<const0> ;
  assign LOCKSTEP_Out[1515] = \<const0> ;
  assign LOCKSTEP_Out[1516] = \<const0> ;
  assign LOCKSTEP_Out[1517] = \<const0> ;
  assign LOCKSTEP_Out[1518] = \<const0> ;
  assign LOCKSTEP_Out[1519] = \<const0> ;
  assign LOCKSTEP_Out[1520] = \<const0> ;
  assign LOCKSTEP_Out[1521] = \<const0> ;
  assign LOCKSTEP_Out[1522] = \<const0> ;
  assign LOCKSTEP_Out[1523] = \<const0> ;
  assign LOCKSTEP_Out[1524] = \<const0> ;
  assign LOCKSTEP_Out[1525] = \<const0> ;
  assign LOCKSTEP_Out[1526] = \<const0> ;
  assign LOCKSTEP_Out[1527] = \<const0> ;
  assign LOCKSTEP_Out[1528] = \<const0> ;
  assign LOCKSTEP_Out[1529] = \<const0> ;
  assign LOCKSTEP_Out[1530] = \<const0> ;
  assign LOCKSTEP_Out[1531] = \<const0> ;
  assign LOCKSTEP_Out[1532] = \<const0> ;
  assign LOCKSTEP_Out[1533] = \<const0> ;
  assign LOCKSTEP_Out[1534] = \<const0> ;
  assign LOCKSTEP_Out[1535] = \<const0> ;
  assign LOCKSTEP_Out[1536] = \<const0> ;
  assign LOCKSTEP_Out[1537] = \<const0> ;
  assign LOCKSTEP_Out[1538] = \<const0> ;
  assign LOCKSTEP_Out[1539] = \<const0> ;
  assign LOCKSTEP_Out[1540] = \<const0> ;
  assign LOCKSTEP_Out[1541] = \<const0> ;
  assign LOCKSTEP_Out[1542] = \<const0> ;
  assign LOCKSTEP_Out[1543] = \<const0> ;
  assign LOCKSTEP_Out[1544] = \<const0> ;
  assign LOCKSTEP_Out[1545] = \<const0> ;
  assign LOCKSTEP_Out[1546] = \<const0> ;
  assign LOCKSTEP_Out[1547] = \<const0> ;
  assign LOCKSTEP_Out[1548] = \<const0> ;
  assign LOCKSTEP_Out[1549] = \<const0> ;
  assign LOCKSTEP_Out[1550] = \<const0> ;
  assign LOCKSTEP_Out[1551] = \<const0> ;
  assign LOCKSTEP_Out[1552] = \<const0> ;
  assign LOCKSTEP_Out[1553] = \<const0> ;
  assign LOCKSTEP_Out[1554] = \<const0> ;
  assign LOCKSTEP_Out[1555] = \<const0> ;
  assign LOCKSTEP_Out[1556] = \<const0> ;
  assign LOCKSTEP_Out[1557] = \<const0> ;
  assign LOCKSTEP_Out[1558] = \<const0> ;
  assign LOCKSTEP_Out[1559] = \<const0> ;
  assign LOCKSTEP_Out[1560] = \<const0> ;
  assign LOCKSTEP_Out[1561] = \<const0> ;
  assign LOCKSTEP_Out[1562] = \<const0> ;
  assign LOCKSTEP_Out[1563] = \<const0> ;
  assign LOCKSTEP_Out[1564] = \<const0> ;
  assign LOCKSTEP_Out[1565] = \<const0> ;
  assign LOCKSTEP_Out[1566] = \<const0> ;
  assign LOCKSTEP_Out[1567] = \<const0> ;
  assign LOCKSTEP_Out[1568] = \<const0> ;
  assign LOCKSTEP_Out[1569] = \<const0> ;
  assign LOCKSTEP_Out[1570] = \<const0> ;
  assign LOCKSTEP_Out[1571] = \<const0> ;
  assign LOCKSTEP_Out[1572] = \<const0> ;
  assign LOCKSTEP_Out[1573] = \<const0> ;
  assign LOCKSTEP_Out[1574] = \<const0> ;
  assign LOCKSTEP_Out[1575] = \<const0> ;
  assign LOCKSTEP_Out[1576] = \<const0> ;
  assign LOCKSTEP_Out[1577] = \<const0> ;
  assign LOCKSTEP_Out[1578] = \<const0> ;
  assign LOCKSTEP_Out[1579] = \<const0> ;
  assign LOCKSTEP_Out[1580] = \<const0> ;
  assign LOCKSTEP_Out[1581] = \<const0> ;
  assign LOCKSTEP_Out[1582] = \<const0> ;
  assign LOCKSTEP_Out[1583] = \<const0> ;
  assign LOCKSTEP_Out[1584] = \<const0> ;
  assign LOCKSTEP_Out[1585] = \<const0> ;
  assign LOCKSTEP_Out[1586] = \<const0> ;
  assign LOCKSTEP_Out[1587] = \<const0> ;
  assign LOCKSTEP_Out[1588] = \<const0> ;
  assign LOCKSTEP_Out[1589] = \<const0> ;
  assign LOCKSTEP_Out[1590] = \<const0> ;
  assign LOCKSTEP_Out[1591] = \<const0> ;
  assign LOCKSTEP_Out[1592] = \<const0> ;
  assign LOCKSTEP_Out[1593] = \<const0> ;
  assign LOCKSTEP_Out[1594] = \<const0> ;
  assign LOCKSTEP_Out[1595] = \<const0> ;
  assign LOCKSTEP_Out[1596] = \<const0> ;
  assign LOCKSTEP_Out[1597] = \<const0> ;
  assign LOCKSTEP_Out[1598] = \<const0> ;
  assign LOCKSTEP_Out[1599] = \<const0> ;
  assign LOCKSTEP_Out[1600] = \<const0> ;
  assign LOCKSTEP_Out[1601] = \<const0> ;
  assign LOCKSTEP_Out[1602] = \<const0> ;
  assign LOCKSTEP_Out[1603] = \<const0> ;
  assign LOCKSTEP_Out[1604] = \<const0> ;
  assign LOCKSTEP_Out[1605] = \<const0> ;
  assign LOCKSTEP_Out[1606] = \<const0> ;
  assign LOCKSTEP_Out[1607] = \<const0> ;
  assign LOCKSTEP_Out[1608] = \<const0> ;
  assign LOCKSTEP_Out[1609] = \<const0> ;
  assign LOCKSTEP_Out[1610] = \<const0> ;
  assign LOCKSTEP_Out[1611] = \<const0> ;
  assign LOCKSTEP_Out[1612] = \<const0> ;
  assign LOCKSTEP_Out[1613] = \<const0> ;
  assign LOCKSTEP_Out[1614] = \<const0> ;
  assign LOCKSTEP_Out[1615] = \<const0> ;
  assign LOCKSTEP_Out[1616] = \<const0> ;
  assign LOCKSTEP_Out[1617] = \<const0> ;
  assign LOCKSTEP_Out[1618] = \<const0> ;
  assign LOCKSTEP_Out[1619] = \<const0> ;
  assign LOCKSTEP_Out[1620] = \<const0> ;
  assign LOCKSTEP_Out[1621] = \<const0> ;
  assign LOCKSTEP_Out[1622] = \<const0> ;
  assign LOCKSTEP_Out[1623] = \<const0> ;
  assign LOCKSTEP_Out[1624] = \<const0> ;
  assign LOCKSTEP_Out[1625] = \<const0> ;
  assign LOCKSTEP_Out[1626] = \<const0> ;
  assign LOCKSTEP_Out[1627] = \<const0> ;
  assign LOCKSTEP_Out[1628] = \<const0> ;
  assign LOCKSTEP_Out[1629] = \<const0> ;
  assign LOCKSTEP_Out[1630] = \<const0> ;
  assign LOCKSTEP_Out[1631] = \<const0> ;
  assign LOCKSTEP_Out[1632] = \<const0> ;
  assign LOCKSTEP_Out[1633] = \<const0> ;
  assign LOCKSTEP_Out[1634] = \<const0> ;
  assign LOCKSTEP_Out[1635] = \<const0> ;
  assign LOCKSTEP_Out[1636] = \<const0> ;
  assign LOCKSTEP_Out[1637] = \<const0> ;
  assign LOCKSTEP_Out[1638] = \<const0> ;
  assign LOCKSTEP_Out[1639] = \<const0> ;
  assign LOCKSTEP_Out[1640] = \<const0> ;
  assign LOCKSTEP_Out[1641] = \<const0> ;
  assign LOCKSTEP_Out[1642] = \<const0> ;
  assign LOCKSTEP_Out[1643] = \<const0> ;
  assign LOCKSTEP_Out[1644] = \<const0> ;
  assign LOCKSTEP_Out[1645] = \<const0> ;
  assign LOCKSTEP_Out[1646] = \<const0> ;
  assign LOCKSTEP_Out[1647] = \<const0> ;
  assign LOCKSTEP_Out[1648] = \<const0> ;
  assign LOCKSTEP_Out[1649] = \<const0> ;
  assign LOCKSTEP_Out[1650] = \<const0> ;
  assign LOCKSTEP_Out[1651] = \<const0> ;
  assign LOCKSTEP_Out[1652] = \<const0> ;
  assign LOCKSTEP_Out[1653] = \<const0> ;
  assign LOCKSTEP_Out[1654] = \<const0> ;
  assign LOCKSTEP_Out[1655] = \<const0> ;
  assign LOCKSTEP_Out[1656] = \<const0> ;
  assign LOCKSTEP_Out[1657] = \<const0> ;
  assign LOCKSTEP_Out[1658] = \<const0> ;
  assign LOCKSTEP_Out[1659] = \<const0> ;
  assign LOCKSTEP_Out[1660] = \<const0> ;
  assign LOCKSTEP_Out[1661] = \<const0> ;
  assign LOCKSTEP_Out[1662] = \<const0> ;
  assign LOCKSTEP_Out[1663] = \<const0> ;
  assign LOCKSTEP_Out[1664] = \<const0> ;
  assign LOCKSTEP_Out[1665] = \<const0> ;
  assign LOCKSTEP_Out[1666] = \<const0> ;
  assign LOCKSTEP_Out[1667] = \<const0> ;
  assign LOCKSTEP_Out[1668] = \<const0> ;
  assign LOCKSTEP_Out[1669] = \<const0> ;
  assign LOCKSTEP_Out[1670] = \<const0> ;
  assign LOCKSTEP_Out[1671] = \<const0> ;
  assign LOCKSTEP_Out[1672] = \<const0> ;
  assign LOCKSTEP_Out[1673] = \<const0> ;
  assign LOCKSTEP_Out[1674] = \<const0> ;
  assign LOCKSTEP_Out[1675] = \<const0> ;
  assign LOCKSTEP_Out[1676] = \<const0> ;
  assign LOCKSTEP_Out[1677] = \<const0> ;
  assign LOCKSTEP_Out[1678] = \<const0> ;
  assign LOCKSTEP_Out[1679] = \<const0> ;
  assign LOCKSTEP_Out[1680] = \<const0> ;
  assign LOCKSTEP_Out[1681] = \<const0> ;
  assign LOCKSTEP_Out[1682] = \<const0> ;
  assign LOCKSTEP_Out[1683] = \<const0> ;
  assign LOCKSTEP_Out[1684] = \<const0> ;
  assign LOCKSTEP_Out[1685] = \<const0> ;
  assign LOCKSTEP_Out[1686] = \<const0> ;
  assign LOCKSTEP_Out[1687] = \<const0> ;
  assign LOCKSTEP_Out[1688] = \<const0> ;
  assign LOCKSTEP_Out[1689] = \<const0> ;
  assign LOCKSTEP_Out[1690] = \<const0> ;
  assign LOCKSTEP_Out[1691] = \<const0> ;
  assign LOCKSTEP_Out[1692] = \<const0> ;
  assign LOCKSTEP_Out[1693] = \<const0> ;
  assign LOCKSTEP_Out[1694] = \<const0> ;
  assign LOCKSTEP_Out[1695] = \<const0> ;
  assign LOCKSTEP_Out[1696] = \<const0> ;
  assign LOCKSTEP_Out[1697] = \<const0> ;
  assign LOCKSTEP_Out[1698] = \<const0> ;
  assign LOCKSTEP_Out[1699] = \<const0> ;
  assign LOCKSTEP_Out[1700] = \<const0> ;
  assign LOCKSTEP_Out[1701] = \<const0> ;
  assign LOCKSTEP_Out[1702] = \<const0> ;
  assign LOCKSTEP_Out[1703] = \<const0> ;
  assign LOCKSTEP_Out[1704] = \<const0> ;
  assign LOCKSTEP_Out[1705] = \<const0> ;
  assign LOCKSTEP_Out[1706] = \<const0> ;
  assign LOCKSTEP_Out[1707] = \<const0> ;
  assign LOCKSTEP_Out[1708] = \<const0> ;
  assign LOCKSTEP_Out[1709] = \<const0> ;
  assign LOCKSTEP_Out[1710] = \<const0> ;
  assign LOCKSTEP_Out[1711] = \<const0> ;
  assign LOCKSTEP_Out[1712] = \<const0> ;
  assign LOCKSTEP_Out[1713] = \<const0> ;
  assign LOCKSTEP_Out[1714] = \<const0> ;
  assign LOCKSTEP_Out[1715] = \<const0> ;
  assign LOCKSTEP_Out[1716] = \<const0> ;
  assign LOCKSTEP_Out[1717] = \<const0> ;
  assign LOCKSTEP_Out[1718] = \<const0> ;
  assign LOCKSTEP_Out[1719] = \<const0> ;
  assign LOCKSTEP_Out[1720] = \<const0> ;
  assign LOCKSTEP_Out[1721] = \<const0> ;
  assign LOCKSTEP_Out[1722] = \<const0> ;
  assign LOCKSTEP_Out[1723] = \<const0> ;
  assign LOCKSTEP_Out[1724] = \<const0> ;
  assign LOCKSTEP_Out[1725] = \<const0> ;
  assign LOCKSTEP_Out[1726] = \<const0> ;
  assign LOCKSTEP_Out[1727] = \<const0> ;
  assign LOCKSTEP_Out[1728] = \<const0> ;
  assign LOCKSTEP_Out[1729] = \<const0> ;
  assign LOCKSTEP_Out[1730] = \<const0> ;
  assign LOCKSTEP_Out[1731] = \<const0> ;
  assign LOCKSTEP_Out[1732] = \<const0> ;
  assign LOCKSTEP_Out[1733] = \<const0> ;
  assign LOCKSTEP_Out[1734] = \<const0> ;
  assign LOCKSTEP_Out[1735] = \<const0> ;
  assign LOCKSTEP_Out[1736] = \<const0> ;
  assign LOCKSTEP_Out[1737] = \<const0> ;
  assign LOCKSTEP_Out[1738] = \<const0> ;
  assign LOCKSTEP_Out[1739] = \<const0> ;
  assign LOCKSTEP_Out[1740] = \<const0> ;
  assign LOCKSTEP_Out[1741] = \<const0> ;
  assign LOCKSTEP_Out[1742] = \<const0> ;
  assign LOCKSTEP_Out[1743] = \<const0> ;
  assign LOCKSTEP_Out[1744] = \<const0> ;
  assign LOCKSTEP_Out[1745] = \<const0> ;
  assign LOCKSTEP_Out[1746] = \<const0> ;
  assign LOCKSTEP_Out[1747] = \<const0> ;
  assign LOCKSTEP_Out[1748] = \<const0> ;
  assign LOCKSTEP_Out[1749] = \<const0> ;
  assign LOCKSTEP_Out[1750] = \<const0> ;
  assign LOCKSTEP_Out[1751] = \<const0> ;
  assign LOCKSTEP_Out[1752] = \<const0> ;
  assign LOCKSTEP_Out[1753] = \<const0> ;
  assign LOCKSTEP_Out[1754] = \<const0> ;
  assign LOCKSTEP_Out[1755] = \<const0> ;
  assign LOCKSTEP_Out[1756] = \<const0> ;
  assign LOCKSTEP_Out[1757] = \<const0> ;
  assign LOCKSTEP_Out[1758] = \<const0> ;
  assign LOCKSTEP_Out[1759] = \<const0> ;
  assign LOCKSTEP_Out[1760] = \<const0> ;
  assign LOCKSTEP_Out[1761] = \<const0> ;
  assign LOCKSTEP_Out[1762] = \<const0> ;
  assign LOCKSTEP_Out[1763] = \<const0> ;
  assign LOCKSTEP_Out[1764] = \<const0> ;
  assign LOCKSTEP_Out[1765] = \<const0> ;
  assign LOCKSTEP_Out[1766] = \<const0> ;
  assign LOCKSTEP_Out[1767] = \<const0> ;
  assign LOCKSTEP_Out[1768] = \<const0> ;
  assign LOCKSTEP_Out[1769] = \<const0> ;
  assign LOCKSTEP_Out[1770] = \<const0> ;
  assign LOCKSTEP_Out[1771] = \<const0> ;
  assign LOCKSTEP_Out[1772] = \<const0> ;
  assign LOCKSTEP_Out[1773] = \<const0> ;
  assign LOCKSTEP_Out[1774] = \<const0> ;
  assign LOCKSTEP_Out[1775] = \<const0> ;
  assign LOCKSTEP_Out[1776] = \<const0> ;
  assign LOCKSTEP_Out[1777] = \<const0> ;
  assign LOCKSTEP_Out[1778] = \<const0> ;
  assign LOCKSTEP_Out[1779] = \<const0> ;
  assign LOCKSTEP_Out[1780] = \<const0> ;
  assign LOCKSTEP_Out[1781] = \<const0> ;
  assign LOCKSTEP_Out[1782] = \<const0> ;
  assign LOCKSTEP_Out[1783] = \<const0> ;
  assign LOCKSTEP_Out[1784] = \<const0> ;
  assign LOCKSTEP_Out[1785] = \<const0> ;
  assign LOCKSTEP_Out[1786] = \<const0> ;
  assign LOCKSTEP_Out[1787] = \<const0> ;
  assign LOCKSTEP_Out[1788] = \<const0> ;
  assign LOCKSTEP_Out[1789] = \<const0> ;
  assign LOCKSTEP_Out[1790] = \<const0> ;
  assign LOCKSTEP_Out[1791] = \<const0> ;
  assign LOCKSTEP_Out[1792] = \<const0> ;
  assign LOCKSTEP_Out[1793] = \<const0> ;
  assign LOCKSTEP_Out[1794] = \<const0> ;
  assign LOCKSTEP_Out[1795] = \<const0> ;
  assign LOCKSTEP_Out[1796] = \<const0> ;
  assign LOCKSTEP_Out[1797] = \<const0> ;
  assign LOCKSTEP_Out[1798] = \<const0> ;
  assign LOCKSTEP_Out[1799] = \<const0> ;
  assign LOCKSTEP_Out[1800] = \<const0> ;
  assign LOCKSTEP_Out[1801] = \<const0> ;
  assign LOCKSTEP_Out[1802] = \<const0> ;
  assign LOCKSTEP_Out[1803] = \<const0> ;
  assign LOCKSTEP_Out[1804] = \<const0> ;
  assign LOCKSTEP_Out[1805] = \<const0> ;
  assign LOCKSTEP_Out[1806] = \<const0> ;
  assign LOCKSTEP_Out[1807] = \<const0> ;
  assign LOCKSTEP_Out[1808] = \<const0> ;
  assign LOCKSTEP_Out[1809] = \<const0> ;
  assign LOCKSTEP_Out[1810] = \<const0> ;
  assign LOCKSTEP_Out[1811] = \<const0> ;
  assign LOCKSTEP_Out[1812] = \<const0> ;
  assign LOCKSTEP_Out[1813] = \<const0> ;
  assign LOCKSTEP_Out[1814] = \<const0> ;
  assign LOCKSTEP_Out[1815] = \<const0> ;
  assign LOCKSTEP_Out[1816] = \<const0> ;
  assign LOCKSTEP_Out[1817] = \<const0> ;
  assign LOCKSTEP_Out[1818] = \<const0> ;
  assign LOCKSTEP_Out[1819] = \<const0> ;
  assign LOCKSTEP_Out[1820] = \<const0> ;
  assign LOCKSTEP_Out[1821] = \<const0> ;
  assign LOCKSTEP_Out[1822] = \<const0> ;
  assign LOCKSTEP_Out[1823] = \<const0> ;
  assign LOCKSTEP_Out[1824] = \<const0> ;
  assign LOCKSTEP_Out[1825] = \<const0> ;
  assign LOCKSTEP_Out[1826] = \<const0> ;
  assign LOCKSTEP_Out[1827] = \<const0> ;
  assign LOCKSTEP_Out[1828] = \<const0> ;
  assign LOCKSTEP_Out[1829] = \<const0> ;
  assign LOCKSTEP_Out[1830] = \<const0> ;
  assign LOCKSTEP_Out[1831] = \<const0> ;
  assign LOCKSTEP_Out[1832] = \<const0> ;
  assign LOCKSTEP_Out[1833] = \<const0> ;
  assign LOCKSTEP_Out[1834] = \<const0> ;
  assign LOCKSTEP_Out[1835] = \<const0> ;
  assign LOCKSTEP_Out[1836] = \<const0> ;
  assign LOCKSTEP_Out[1837] = \<const0> ;
  assign LOCKSTEP_Out[1838] = \<const0> ;
  assign LOCKSTEP_Out[1839] = \<const0> ;
  assign LOCKSTEP_Out[1840] = \<const0> ;
  assign LOCKSTEP_Out[1841] = \<const0> ;
  assign LOCKSTEP_Out[1842] = \<const0> ;
  assign LOCKSTEP_Out[1843] = \<const0> ;
  assign LOCKSTEP_Out[1844] = \<const0> ;
  assign LOCKSTEP_Out[1845] = \<const0> ;
  assign LOCKSTEP_Out[1846] = \<const0> ;
  assign LOCKSTEP_Out[1847] = \<const0> ;
  assign LOCKSTEP_Out[1848] = \<const0> ;
  assign LOCKSTEP_Out[1849] = \<const0> ;
  assign LOCKSTEP_Out[1850] = \<const0> ;
  assign LOCKSTEP_Out[1851] = \<const0> ;
  assign LOCKSTEP_Out[1852] = \<const0> ;
  assign LOCKSTEP_Out[1853] = \<const0> ;
  assign LOCKSTEP_Out[1854] = \<const0> ;
  assign LOCKSTEP_Out[1855] = \<const0> ;
  assign LOCKSTEP_Out[1856] = \<const0> ;
  assign LOCKSTEP_Out[1857] = \<const0> ;
  assign LOCKSTEP_Out[1858] = \<const0> ;
  assign LOCKSTEP_Out[1859] = \<const0> ;
  assign LOCKSTEP_Out[1860] = \<const0> ;
  assign LOCKSTEP_Out[1861] = \<const0> ;
  assign LOCKSTEP_Out[1862] = \<const0> ;
  assign LOCKSTEP_Out[1863] = \<const0> ;
  assign LOCKSTEP_Out[1864] = \<const0> ;
  assign LOCKSTEP_Out[1865] = \<const0> ;
  assign LOCKSTEP_Out[1866] = \<const0> ;
  assign LOCKSTEP_Out[1867] = \<const0> ;
  assign LOCKSTEP_Out[1868] = \<const0> ;
  assign LOCKSTEP_Out[1869] = \<const0> ;
  assign LOCKSTEP_Out[1870] = \<const0> ;
  assign LOCKSTEP_Out[1871] = \<const0> ;
  assign LOCKSTEP_Out[1872] = \<const0> ;
  assign LOCKSTEP_Out[1873] = \<const0> ;
  assign LOCKSTEP_Out[1874] = \<const0> ;
  assign LOCKSTEP_Out[1875] = \<const0> ;
  assign LOCKSTEP_Out[1876] = \<const0> ;
  assign LOCKSTEP_Out[1877] = \<const0> ;
  assign LOCKSTEP_Out[1878] = \<const0> ;
  assign LOCKSTEP_Out[1879] = \<const0> ;
  assign LOCKSTEP_Out[1880] = \<const0> ;
  assign LOCKSTEP_Out[1881] = \<const0> ;
  assign LOCKSTEP_Out[1882] = \<const0> ;
  assign LOCKSTEP_Out[1883] = \<const0> ;
  assign LOCKSTEP_Out[1884] = \<const0> ;
  assign LOCKSTEP_Out[1885] = \<const0> ;
  assign LOCKSTEP_Out[1886] = \<const0> ;
  assign LOCKSTEP_Out[1887] = \<const0> ;
  assign LOCKSTEP_Out[1888] = \<const0> ;
  assign LOCKSTEP_Out[1889] = \<const0> ;
  assign LOCKSTEP_Out[1890] = \<const0> ;
  assign LOCKSTEP_Out[1891] = \<const0> ;
  assign LOCKSTEP_Out[1892] = \<const0> ;
  assign LOCKSTEP_Out[1893] = \<const0> ;
  assign LOCKSTEP_Out[1894] = \<const0> ;
  assign LOCKSTEP_Out[1895] = \<const0> ;
  assign LOCKSTEP_Out[1896] = \<const0> ;
  assign LOCKSTEP_Out[1897] = \<const0> ;
  assign LOCKSTEP_Out[1898] = \<const0> ;
  assign LOCKSTEP_Out[1899] = \<const0> ;
  assign LOCKSTEP_Out[1900] = \<const0> ;
  assign LOCKSTEP_Out[1901] = \<const0> ;
  assign LOCKSTEP_Out[1902] = \<const0> ;
  assign LOCKSTEP_Out[1903] = \<const0> ;
  assign LOCKSTEP_Out[1904] = \<const0> ;
  assign LOCKSTEP_Out[1905] = \<const0> ;
  assign LOCKSTEP_Out[1906] = \<const0> ;
  assign LOCKSTEP_Out[1907] = \<const0> ;
  assign LOCKSTEP_Out[1908] = \<const0> ;
  assign LOCKSTEP_Out[1909] = \<const0> ;
  assign LOCKSTEP_Out[1910] = \<const0> ;
  assign LOCKSTEP_Out[1911] = \<const0> ;
  assign LOCKSTEP_Out[1912] = \<const0> ;
  assign LOCKSTEP_Out[1913] = \<const0> ;
  assign LOCKSTEP_Out[1914] = \<const0> ;
  assign LOCKSTEP_Out[1915] = \<const0> ;
  assign LOCKSTEP_Out[1916] = \<const0> ;
  assign LOCKSTEP_Out[1917] = \<const0> ;
  assign LOCKSTEP_Out[1918] = \<const0> ;
  assign LOCKSTEP_Out[1919] = \<const0> ;
  assign LOCKSTEP_Out[1920] = \<const0> ;
  assign LOCKSTEP_Out[1921] = \<const0> ;
  assign LOCKSTEP_Out[1922] = \<const0> ;
  assign LOCKSTEP_Out[1923] = \<const0> ;
  assign LOCKSTEP_Out[1924] = \<const0> ;
  assign LOCKSTEP_Out[1925] = \<const0> ;
  assign LOCKSTEP_Out[1926] = \<const0> ;
  assign LOCKSTEP_Out[1927] = \<const0> ;
  assign LOCKSTEP_Out[1928] = \<const0> ;
  assign LOCKSTEP_Out[1929] = \<const0> ;
  assign LOCKSTEP_Out[1930] = \<const0> ;
  assign LOCKSTEP_Out[1931] = \<const0> ;
  assign LOCKSTEP_Out[1932] = \<const0> ;
  assign LOCKSTEP_Out[1933] = \<const0> ;
  assign LOCKSTEP_Out[1934] = \<const0> ;
  assign LOCKSTEP_Out[1935] = \<const0> ;
  assign LOCKSTEP_Out[1936] = \<const0> ;
  assign LOCKSTEP_Out[1937] = \<const0> ;
  assign LOCKSTEP_Out[1938] = \<const0> ;
  assign LOCKSTEP_Out[1939] = \<const0> ;
  assign LOCKSTEP_Out[1940] = \<const0> ;
  assign LOCKSTEP_Out[1941] = \<const0> ;
  assign LOCKSTEP_Out[1942] = \<const0> ;
  assign LOCKSTEP_Out[1943] = \<const0> ;
  assign LOCKSTEP_Out[1944] = \<const0> ;
  assign LOCKSTEP_Out[1945] = \<const0> ;
  assign LOCKSTEP_Out[1946] = \<const0> ;
  assign LOCKSTEP_Out[1947] = \<const0> ;
  assign LOCKSTEP_Out[1948] = \<const0> ;
  assign LOCKSTEP_Out[1949] = \<const0> ;
  assign LOCKSTEP_Out[1950] = \<const0> ;
  assign LOCKSTEP_Out[1951] = \<const0> ;
  assign LOCKSTEP_Out[1952] = \<const0> ;
  assign LOCKSTEP_Out[1953] = \<const0> ;
  assign LOCKSTEP_Out[1954] = \<const0> ;
  assign LOCKSTEP_Out[1955] = \<const0> ;
  assign LOCKSTEP_Out[1956] = \<const0> ;
  assign LOCKSTEP_Out[1957] = \<const0> ;
  assign LOCKSTEP_Out[1958] = \<const0> ;
  assign LOCKSTEP_Out[1959] = \<const0> ;
  assign LOCKSTEP_Out[1960] = \<const0> ;
  assign LOCKSTEP_Out[1961] = \<const0> ;
  assign LOCKSTEP_Out[1962] = \<const0> ;
  assign LOCKSTEP_Out[1963] = \<const0> ;
  assign LOCKSTEP_Out[1964] = \<const0> ;
  assign LOCKSTEP_Out[1965] = \<const0> ;
  assign LOCKSTEP_Out[1966] = \<const0> ;
  assign LOCKSTEP_Out[1967] = \<const0> ;
  assign LOCKSTEP_Out[1968] = \<const0> ;
  assign LOCKSTEP_Out[1969] = \<const0> ;
  assign LOCKSTEP_Out[1970] = \<const0> ;
  assign LOCKSTEP_Out[1971] = \<const0> ;
  assign LOCKSTEP_Out[1972] = \<const0> ;
  assign LOCKSTEP_Out[1973] = \<const0> ;
  assign LOCKSTEP_Out[1974] = \<const0> ;
  assign LOCKSTEP_Out[1975] = \<const0> ;
  assign LOCKSTEP_Out[1976] = \<const0> ;
  assign LOCKSTEP_Out[1977] = \<const0> ;
  assign LOCKSTEP_Out[1978] = \<const0> ;
  assign LOCKSTEP_Out[1979] = \<const0> ;
  assign LOCKSTEP_Out[1980] = \<const0> ;
  assign LOCKSTEP_Out[1981] = \<const0> ;
  assign LOCKSTEP_Out[1982] = \<const0> ;
  assign LOCKSTEP_Out[1983] = \<const0> ;
  assign LOCKSTEP_Out[1984] = \<const0> ;
  assign LOCKSTEP_Out[1985] = \<const0> ;
  assign LOCKSTEP_Out[1986] = \<const0> ;
  assign LOCKSTEP_Out[1987] = \<const0> ;
  assign LOCKSTEP_Out[1988] = \<const0> ;
  assign LOCKSTEP_Out[1989] = \<const0> ;
  assign LOCKSTEP_Out[1990] = \<const0> ;
  assign LOCKSTEP_Out[1991] = \<const0> ;
  assign LOCKSTEP_Out[1992] = \<const0> ;
  assign LOCKSTEP_Out[1993] = \<const0> ;
  assign LOCKSTEP_Out[1994] = \<const0> ;
  assign LOCKSTEP_Out[1995] = \<const0> ;
  assign LOCKSTEP_Out[1996] = \<const0> ;
  assign LOCKSTEP_Out[1997] = \<const0> ;
  assign LOCKSTEP_Out[1998] = \<const0> ;
  assign LOCKSTEP_Out[1999] = \<const0> ;
  assign LOCKSTEP_Out[2000] = \<const0> ;
  assign LOCKSTEP_Out[2001] = \<const0> ;
  assign LOCKSTEP_Out[2002] = \<const0> ;
  assign LOCKSTEP_Out[2003] = \<const0> ;
  assign LOCKSTEP_Out[2004] = \<const0> ;
  assign LOCKSTEP_Out[2005] = \<const0> ;
  assign LOCKSTEP_Out[2006] = \<const0> ;
  assign LOCKSTEP_Out[2007] = \<const0> ;
  assign LOCKSTEP_Out[2008] = \<const0> ;
  assign LOCKSTEP_Out[2009] = \<const0> ;
  assign LOCKSTEP_Out[2010] = \<const0> ;
  assign LOCKSTEP_Out[2011] = \<const0> ;
  assign LOCKSTEP_Out[2012] = \<const0> ;
  assign LOCKSTEP_Out[2013] = \<const0> ;
  assign LOCKSTEP_Out[2014] = \<const0> ;
  assign LOCKSTEP_Out[2015] = \<const0> ;
  assign LOCKSTEP_Out[2016] = \<const0> ;
  assign LOCKSTEP_Out[2017] = \<const0> ;
  assign LOCKSTEP_Out[2018] = \<const0> ;
  assign LOCKSTEP_Out[2019] = \<const0> ;
  assign LOCKSTEP_Out[2020] = \<const0> ;
  assign LOCKSTEP_Out[2021] = \<const0> ;
  assign LOCKSTEP_Out[2022] = \<const0> ;
  assign LOCKSTEP_Out[2023] = \<const0> ;
  assign LOCKSTEP_Out[2024] = \<const0> ;
  assign LOCKSTEP_Out[2025] = \<const0> ;
  assign LOCKSTEP_Out[2026] = \<const0> ;
  assign LOCKSTEP_Out[2027] = \<const0> ;
  assign LOCKSTEP_Out[2028] = \<const0> ;
  assign LOCKSTEP_Out[2029] = \<const0> ;
  assign LOCKSTEP_Out[2030] = \<const0> ;
  assign LOCKSTEP_Out[2031] = \<const0> ;
  assign LOCKSTEP_Out[2032] = \<const0> ;
  assign LOCKSTEP_Out[2033] = \<const0> ;
  assign LOCKSTEP_Out[2034] = \<const0> ;
  assign LOCKSTEP_Out[2035] = \<const0> ;
  assign LOCKSTEP_Out[2036] = \<const0> ;
  assign LOCKSTEP_Out[2037] = \<const0> ;
  assign LOCKSTEP_Out[2038] = \<const0> ;
  assign LOCKSTEP_Out[2039] = \<const0> ;
  assign LOCKSTEP_Out[2040] = \<const0> ;
  assign LOCKSTEP_Out[2041] = \<const0> ;
  assign LOCKSTEP_Out[2042] = \<const0> ;
  assign LOCKSTEP_Out[2043] = \<const0> ;
  assign LOCKSTEP_Out[2044] = \<const0> ;
  assign LOCKSTEP_Out[2045] = \<const0> ;
  assign LOCKSTEP_Out[2046] = \<const0> ;
  assign LOCKSTEP_Out[2047] = \<const0> ;
  assign LOCKSTEP_Out[2048] = \<const0> ;
  assign LOCKSTEP_Out[2049] = \<const0> ;
  assign LOCKSTEP_Out[2050] = \<const0> ;
  assign LOCKSTEP_Out[2051] = \<const0> ;
  assign LOCKSTEP_Out[2052] = \<const0> ;
  assign LOCKSTEP_Out[2053] = \<const0> ;
  assign LOCKSTEP_Out[2054] = \<const0> ;
  assign LOCKSTEP_Out[2055] = \<const0> ;
  assign LOCKSTEP_Out[2056] = \<const0> ;
  assign LOCKSTEP_Out[2057] = \<const0> ;
  assign LOCKSTEP_Out[2058] = \<const0> ;
  assign LOCKSTEP_Out[2059] = \<const0> ;
  assign LOCKSTEP_Out[2060] = \<const0> ;
  assign LOCKSTEP_Out[2061] = \<const0> ;
  assign LOCKSTEP_Out[2062] = \<const0> ;
  assign LOCKSTEP_Out[2063] = \<const0> ;
  assign LOCKSTEP_Out[2064] = \<const0> ;
  assign LOCKSTEP_Out[2065] = \<const0> ;
  assign LOCKSTEP_Out[2066] = \<const0> ;
  assign LOCKSTEP_Out[2067] = \<const0> ;
  assign LOCKSTEP_Out[2068] = \<const0> ;
  assign LOCKSTEP_Out[2069] = \<const0> ;
  assign LOCKSTEP_Out[2070] = \<const0> ;
  assign LOCKSTEP_Out[2071] = \<const0> ;
  assign LOCKSTEP_Out[2072] = \<const0> ;
  assign LOCKSTEP_Out[2073] = \<const0> ;
  assign LOCKSTEP_Out[2074] = \<const0> ;
  assign LOCKSTEP_Out[2075] = \<const0> ;
  assign LOCKSTEP_Out[2076] = \<const0> ;
  assign LOCKSTEP_Out[2077] = \<const0> ;
  assign LOCKSTEP_Out[2078] = \<const0> ;
  assign LOCKSTEP_Out[2079] = \<const0> ;
  assign LOCKSTEP_Out[2080] = \<const0> ;
  assign LOCKSTEP_Out[2081] = \<const0> ;
  assign LOCKSTEP_Out[2082] = \<const0> ;
  assign LOCKSTEP_Out[2083] = \<const0> ;
  assign LOCKSTEP_Out[2084] = \<const0> ;
  assign LOCKSTEP_Out[2085] = \<const0> ;
  assign LOCKSTEP_Out[2086] = \<const0> ;
  assign LOCKSTEP_Out[2087] = \<const0> ;
  assign LOCKSTEP_Out[2088] = \<const0> ;
  assign LOCKSTEP_Out[2089] = \<const0> ;
  assign LOCKSTEP_Out[2090] = \<const0> ;
  assign LOCKSTEP_Out[2091] = \<const0> ;
  assign LOCKSTEP_Out[2092] = \<const0> ;
  assign LOCKSTEP_Out[2093] = \<const0> ;
  assign LOCKSTEP_Out[2094] = \<const0> ;
  assign LOCKSTEP_Out[2095] = \<const0> ;
  assign LOCKSTEP_Out[2096] = \<const0> ;
  assign LOCKSTEP_Out[2097] = \<const0> ;
  assign LOCKSTEP_Out[2098] = \<const0> ;
  assign LOCKSTEP_Out[2099] = \<const0> ;
  assign LOCKSTEP_Out[2100] = \<const0> ;
  assign LOCKSTEP_Out[2101] = \<const0> ;
  assign LOCKSTEP_Out[2102] = \<const0> ;
  assign LOCKSTEP_Out[2103] = \<const0> ;
  assign LOCKSTEP_Out[2104] = \<const0> ;
  assign LOCKSTEP_Out[2105] = \<const0> ;
  assign LOCKSTEP_Out[2106] = \<const0> ;
  assign LOCKSTEP_Out[2107] = \<const0> ;
  assign LOCKSTEP_Out[2108] = \<const0> ;
  assign LOCKSTEP_Out[2109] = \<const0> ;
  assign LOCKSTEP_Out[2110] = \<const0> ;
  assign LOCKSTEP_Out[2111] = \<const0> ;
  assign LOCKSTEP_Out[2112] = \<const0> ;
  assign LOCKSTEP_Out[2113] = \<const0> ;
  assign LOCKSTEP_Out[2114] = \<const0> ;
  assign LOCKSTEP_Out[2115] = \<const0> ;
  assign LOCKSTEP_Out[2116] = \<const0> ;
  assign LOCKSTEP_Out[2117] = \<const0> ;
  assign LOCKSTEP_Out[2118] = \<const0> ;
  assign LOCKSTEP_Out[2119] = \<const0> ;
  assign LOCKSTEP_Out[2120] = \<const0> ;
  assign LOCKSTEP_Out[2121] = \<const0> ;
  assign LOCKSTEP_Out[2122] = \<const0> ;
  assign LOCKSTEP_Out[2123] = \<const0> ;
  assign LOCKSTEP_Out[2124] = \<const0> ;
  assign LOCKSTEP_Out[2125] = \<const0> ;
  assign LOCKSTEP_Out[2126] = \<const0> ;
  assign LOCKSTEP_Out[2127] = \<const0> ;
  assign LOCKSTEP_Out[2128] = \<const0> ;
  assign LOCKSTEP_Out[2129] = \<const0> ;
  assign LOCKSTEP_Out[2130] = \<const0> ;
  assign LOCKSTEP_Out[2131] = \<const0> ;
  assign LOCKSTEP_Out[2132] = \<const0> ;
  assign LOCKSTEP_Out[2133] = \<const0> ;
  assign LOCKSTEP_Out[2134] = \<const0> ;
  assign LOCKSTEP_Out[2135] = \<const0> ;
  assign LOCKSTEP_Out[2136] = \<const0> ;
  assign LOCKSTEP_Out[2137] = \<const0> ;
  assign LOCKSTEP_Out[2138] = \<const0> ;
  assign LOCKSTEP_Out[2139] = \<const0> ;
  assign LOCKSTEP_Out[2140] = \<const0> ;
  assign LOCKSTEP_Out[2141] = \<const0> ;
  assign LOCKSTEP_Out[2142] = \<const0> ;
  assign LOCKSTEP_Out[2143] = \<const0> ;
  assign LOCKSTEP_Out[2144] = \<const0> ;
  assign LOCKSTEP_Out[2145] = \<const0> ;
  assign LOCKSTEP_Out[2146] = \<const0> ;
  assign LOCKSTEP_Out[2147] = \<const0> ;
  assign LOCKSTEP_Out[2148] = \<const0> ;
  assign LOCKSTEP_Out[2149] = \<const0> ;
  assign LOCKSTEP_Out[2150] = \<const0> ;
  assign LOCKSTEP_Out[2151] = \<const0> ;
  assign LOCKSTEP_Out[2152] = \<const0> ;
  assign LOCKSTEP_Out[2153] = \<const0> ;
  assign LOCKSTEP_Out[2154] = \<const0> ;
  assign LOCKSTEP_Out[2155] = \<const0> ;
  assign LOCKSTEP_Out[2156] = \<const0> ;
  assign LOCKSTEP_Out[2157] = \<const0> ;
  assign LOCKSTEP_Out[2158] = \<const0> ;
  assign LOCKSTEP_Out[2159] = \<const0> ;
  assign LOCKSTEP_Out[2160] = \<const0> ;
  assign LOCKSTEP_Out[2161] = \<const0> ;
  assign LOCKSTEP_Out[2162] = \<const0> ;
  assign LOCKSTEP_Out[2163] = \<const0> ;
  assign LOCKSTEP_Out[2164] = \<const0> ;
  assign LOCKSTEP_Out[2165] = \<const0> ;
  assign LOCKSTEP_Out[2166] = \<const0> ;
  assign LOCKSTEP_Out[2167] = \<const0> ;
  assign LOCKSTEP_Out[2168] = \<const0> ;
  assign LOCKSTEP_Out[2169] = \<const0> ;
  assign LOCKSTEP_Out[2170] = \<const0> ;
  assign LOCKSTEP_Out[2171] = \<const0> ;
  assign LOCKSTEP_Out[2172] = \<const0> ;
  assign LOCKSTEP_Out[2173] = \<const0> ;
  assign LOCKSTEP_Out[2174] = \<const0> ;
  assign LOCKSTEP_Out[2175] = \<const0> ;
  assign LOCKSTEP_Out[2176] = \<const0> ;
  assign LOCKSTEP_Out[2177] = \<const0> ;
  assign LOCKSTEP_Out[2178] = \<const0> ;
  assign LOCKSTEP_Out[2179] = \<const0> ;
  assign LOCKSTEP_Out[2180] = \<const0> ;
  assign LOCKSTEP_Out[2181] = \<const0> ;
  assign LOCKSTEP_Out[2182] = \<const0> ;
  assign LOCKSTEP_Out[2183] = \<const0> ;
  assign LOCKSTEP_Out[2184] = \<const0> ;
  assign LOCKSTEP_Out[2185] = \<const0> ;
  assign LOCKSTEP_Out[2186] = \<const0> ;
  assign LOCKSTEP_Out[2187] = \<const0> ;
  assign LOCKSTEP_Out[2188] = \<const0> ;
  assign LOCKSTEP_Out[2189] = \<const0> ;
  assign LOCKSTEP_Out[2190] = \<const0> ;
  assign LOCKSTEP_Out[2191] = \<const0> ;
  assign LOCKSTEP_Out[2192] = \<const0> ;
  assign LOCKSTEP_Out[2193] = \<const0> ;
  assign LOCKSTEP_Out[2194] = \<const0> ;
  assign LOCKSTEP_Out[2195] = \<const0> ;
  assign LOCKSTEP_Out[2196] = \<const0> ;
  assign LOCKSTEP_Out[2197] = \<const0> ;
  assign LOCKSTEP_Out[2198] = \<const0> ;
  assign LOCKSTEP_Out[2199] = \<const0> ;
  assign LOCKSTEP_Out[2200] = \<const0> ;
  assign LOCKSTEP_Out[2201] = \<const0> ;
  assign LOCKSTEP_Out[2202] = \<const0> ;
  assign LOCKSTEP_Out[2203] = \<const0> ;
  assign LOCKSTEP_Out[2204] = \<const0> ;
  assign LOCKSTEP_Out[2205] = \<const0> ;
  assign LOCKSTEP_Out[2206] = \<const0> ;
  assign LOCKSTEP_Out[2207] = \<const0> ;
  assign LOCKSTEP_Out[2208] = \<const0> ;
  assign LOCKSTEP_Out[2209] = \<const0> ;
  assign LOCKSTEP_Out[2210] = \<const0> ;
  assign LOCKSTEP_Out[2211] = \<const0> ;
  assign LOCKSTEP_Out[2212] = \<const0> ;
  assign LOCKSTEP_Out[2213] = \<const0> ;
  assign LOCKSTEP_Out[2214] = \<const0> ;
  assign LOCKSTEP_Out[2215] = \<const0> ;
  assign LOCKSTEP_Out[2216] = \<const0> ;
  assign LOCKSTEP_Out[2217] = \<const0> ;
  assign LOCKSTEP_Out[2218] = \<const0> ;
  assign LOCKSTEP_Out[2219] = \<const0> ;
  assign LOCKSTEP_Out[2220] = \<const0> ;
  assign LOCKSTEP_Out[2221] = \<const0> ;
  assign LOCKSTEP_Out[2222] = \<const0> ;
  assign LOCKSTEP_Out[2223] = \<const0> ;
  assign LOCKSTEP_Out[2224] = \<const0> ;
  assign LOCKSTEP_Out[2225] = \<const0> ;
  assign LOCKSTEP_Out[2226] = \<const0> ;
  assign LOCKSTEP_Out[2227] = \<const0> ;
  assign LOCKSTEP_Out[2228] = \<const0> ;
  assign LOCKSTEP_Out[2229] = \<const0> ;
  assign LOCKSTEP_Out[2230] = \<const0> ;
  assign LOCKSTEP_Out[2231] = \<const0> ;
  assign LOCKSTEP_Out[2232] = \<const0> ;
  assign LOCKSTEP_Out[2233] = \<const0> ;
  assign LOCKSTEP_Out[2234] = \<const0> ;
  assign LOCKSTEP_Out[2235] = \<const0> ;
  assign LOCKSTEP_Out[2236] = \<const0> ;
  assign LOCKSTEP_Out[2237] = \<const0> ;
  assign LOCKSTEP_Out[2238] = \<const0> ;
  assign LOCKSTEP_Out[2239] = \<const0> ;
  assign LOCKSTEP_Out[2240] = \<const0> ;
  assign LOCKSTEP_Out[2241] = \<const0> ;
  assign LOCKSTEP_Out[2242] = \<const0> ;
  assign LOCKSTEP_Out[2243] = \<const0> ;
  assign LOCKSTEP_Out[2244] = \<const0> ;
  assign LOCKSTEP_Out[2245] = \<const0> ;
  assign LOCKSTEP_Out[2246] = \<const0> ;
  assign LOCKSTEP_Out[2247] = \<const0> ;
  assign LOCKSTEP_Out[2248] = \<const0> ;
  assign LOCKSTEP_Out[2249] = \<const0> ;
  assign LOCKSTEP_Out[2250] = \<const0> ;
  assign LOCKSTEP_Out[2251] = \<const0> ;
  assign LOCKSTEP_Out[2252] = \<const0> ;
  assign LOCKSTEP_Out[2253] = \<const0> ;
  assign LOCKSTEP_Out[2254] = \<const0> ;
  assign LOCKSTEP_Out[2255] = \<const0> ;
  assign LOCKSTEP_Out[2256] = \<const0> ;
  assign LOCKSTEP_Out[2257] = \<const0> ;
  assign LOCKSTEP_Out[2258] = \<const0> ;
  assign LOCKSTEP_Out[2259] = \<const0> ;
  assign LOCKSTEP_Out[2260] = \<const0> ;
  assign LOCKSTEP_Out[2261] = \<const0> ;
  assign LOCKSTEP_Out[2262] = \<const0> ;
  assign LOCKSTEP_Out[2263] = \<const0> ;
  assign LOCKSTEP_Out[2264] = \<const0> ;
  assign LOCKSTEP_Out[2265] = \<const0> ;
  assign LOCKSTEP_Out[2266] = \<const0> ;
  assign LOCKSTEP_Out[2267] = \<const0> ;
  assign LOCKSTEP_Out[2268] = \<const0> ;
  assign LOCKSTEP_Out[2269] = \<const0> ;
  assign LOCKSTEP_Out[2270] = \<const0> ;
  assign LOCKSTEP_Out[2271] = \<const0> ;
  assign LOCKSTEP_Out[2272] = \<const0> ;
  assign LOCKSTEP_Out[2273] = \<const0> ;
  assign LOCKSTEP_Out[2274] = \<const0> ;
  assign LOCKSTEP_Out[2275] = \<const0> ;
  assign LOCKSTEP_Out[2276] = \<const0> ;
  assign LOCKSTEP_Out[2277] = \<const0> ;
  assign LOCKSTEP_Out[2278] = \<const0> ;
  assign LOCKSTEP_Out[2279] = \<const0> ;
  assign LOCKSTEP_Out[2280] = \<const0> ;
  assign LOCKSTEP_Out[2281] = \<const0> ;
  assign LOCKSTEP_Out[2282] = \<const0> ;
  assign LOCKSTEP_Out[2283] = \<const0> ;
  assign LOCKSTEP_Out[2284] = \<const0> ;
  assign LOCKSTEP_Out[2285] = \<const0> ;
  assign LOCKSTEP_Out[2286] = \<const0> ;
  assign LOCKSTEP_Out[2287] = \<const0> ;
  assign LOCKSTEP_Out[2288] = \<const0> ;
  assign LOCKSTEP_Out[2289] = \<const0> ;
  assign LOCKSTEP_Out[2290] = \<const0> ;
  assign LOCKSTEP_Out[2291] = \<const0> ;
  assign LOCKSTEP_Out[2292] = \<const0> ;
  assign LOCKSTEP_Out[2293] = \<const0> ;
  assign LOCKSTEP_Out[2294] = \<const0> ;
  assign LOCKSTEP_Out[2295] = \<const0> ;
  assign LOCKSTEP_Out[2296] = \<const0> ;
  assign LOCKSTEP_Out[2297] = \<const0> ;
  assign LOCKSTEP_Out[2298] = \<const0> ;
  assign LOCKSTEP_Out[2299] = \<const0> ;
  assign LOCKSTEP_Out[2300] = \<const0> ;
  assign LOCKSTEP_Out[2301] = \<const0> ;
  assign LOCKSTEP_Out[2302] = \<const0> ;
  assign LOCKSTEP_Out[2303] = \<const0> ;
  assign LOCKSTEP_Out[2304] = \<const0> ;
  assign LOCKSTEP_Out[2305] = \<const0> ;
  assign LOCKSTEP_Out[2306] = \<const0> ;
  assign LOCKSTEP_Out[2307] = \<const0> ;
  assign LOCKSTEP_Out[2308] = \<const0> ;
  assign LOCKSTEP_Out[2309] = \<const0> ;
  assign LOCKSTEP_Out[2310] = \<const0> ;
  assign LOCKSTEP_Out[2311] = \<const0> ;
  assign LOCKSTEP_Out[2312] = \<const0> ;
  assign LOCKSTEP_Out[2313] = \<const0> ;
  assign LOCKSTEP_Out[2314] = \<const0> ;
  assign LOCKSTEP_Out[2315] = \<const0> ;
  assign LOCKSTEP_Out[2316] = \<const0> ;
  assign LOCKSTEP_Out[2317] = \<const0> ;
  assign LOCKSTEP_Out[2318] = \<const0> ;
  assign LOCKSTEP_Out[2319] = \<const0> ;
  assign LOCKSTEP_Out[2320] = \<const0> ;
  assign LOCKSTEP_Out[2321] = \<const0> ;
  assign LOCKSTEP_Out[2322] = \<const0> ;
  assign LOCKSTEP_Out[2323] = \<const0> ;
  assign LOCKSTEP_Out[2324] = \<const0> ;
  assign LOCKSTEP_Out[2325] = \<const0> ;
  assign LOCKSTEP_Out[2326] = \<const0> ;
  assign LOCKSTEP_Out[2327] = \<const0> ;
  assign LOCKSTEP_Out[2328] = \<const0> ;
  assign LOCKSTEP_Out[2329] = \<const0> ;
  assign LOCKSTEP_Out[2330] = \<const0> ;
  assign LOCKSTEP_Out[2331] = \<const0> ;
  assign LOCKSTEP_Out[2332] = \<const0> ;
  assign LOCKSTEP_Out[2333] = \<const0> ;
  assign LOCKSTEP_Out[2334] = \<const0> ;
  assign LOCKSTEP_Out[2335] = \<const0> ;
  assign LOCKSTEP_Out[2336] = \<const0> ;
  assign LOCKSTEP_Out[2337] = \<const0> ;
  assign LOCKSTEP_Out[2338] = \<const0> ;
  assign LOCKSTEP_Out[2339] = \<const0> ;
  assign LOCKSTEP_Out[2340] = \<const0> ;
  assign LOCKSTEP_Out[2341] = \<const0> ;
  assign LOCKSTEP_Out[2342] = \<const0> ;
  assign LOCKSTEP_Out[2343] = \<const0> ;
  assign LOCKSTEP_Out[2344] = \<const0> ;
  assign LOCKSTEP_Out[2345] = \<const0> ;
  assign LOCKSTEP_Out[2346] = \<const0> ;
  assign LOCKSTEP_Out[2347] = \<const0> ;
  assign LOCKSTEP_Out[2348] = \<const0> ;
  assign LOCKSTEP_Out[2349] = \<const0> ;
  assign LOCKSTEP_Out[2350] = \<const0> ;
  assign LOCKSTEP_Out[2351] = \<const0> ;
  assign LOCKSTEP_Out[2352] = \<const0> ;
  assign LOCKSTEP_Out[2353] = \<const0> ;
  assign LOCKSTEP_Out[2354] = \<const0> ;
  assign LOCKSTEP_Out[2355] = \<const0> ;
  assign LOCKSTEP_Out[2356] = \<const0> ;
  assign LOCKSTEP_Out[2357] = \<const0> ;
  assign LOCKSTEP_Out[2358] = \<const0> ;
  assign LOCKSTEP_Out[2359] = \<const0> ;
  assign LOCKSTEP_Out[2360] = \<const0> ;
  assign LOCKSTEP_Out[2361] = \<const0> ;
  assign LOCKSTEP_Out[2362] = \<const0> ;
  assign LOCKSTEP_Out[2363] = \<const0> ;
  assign LOCKSTEP_Out[2364] = \<const0> ;
  assign LOCKSTEP_Out[2365] = \<const0> ;
  assign LOCKSTEP_Out[2366] = \<const0> ;
  assign LOCKSTEP_Out[2367] = \<const0> ;
  assign LOCKSTEP_Out[2368] = \<const0> ;
  assign LOCKSTEP_Out[2369] = \<const0> ;
  assign LOCKSTEP_Out[2370] = \<const0> ;
  assign LOCKSTEP_Out[2371] = \<const0> ;
  assign LOCKSTEP_Out[2372] = \<const0> ;
  assign LOCKSTEP_Out[2373] = \<const0> ;
  assign LOCKSTEP_Out[2374] = \<const0> ;
  assign LOCKSTEP_Out[2375] = \<const0> ;
  assign LOCKSTEP_Out[2376] = \<const0> ;
  assign LOCKSTEP_Out[2377] = \<const0> ;
  assign LOCKSTEP_Out[2378] = \<const0> ;
  assign LOCKSTEP_Out[2379] = \<const0> ;
  assign LOCKSTEP_Out[2380] = \<const0> ;
  assign LOCKSTEP_Out[2381] = \<const0> ;
  assign LOCKSTEP_Out[2382] = \<const0> ;
  assign LOCKSTEP_Out[2383] = \<const0> ;
  assign LOCKSTEP_Out[2384] = \<const0> ;
  assign LOCKSTEP_Out[2385] = \<const0> ;
  assign LOCKSTEP_Out[2386] = \<const0> ;
  assign LOCKSTEP_Out[2387] = \<const0> ;
  assign LOCKSTEP_Out[2388] = \<const0> ;
  assign LOCKSTEP_Out[2389] = \<const0> ;
  assign LOCKSTEP_Out[2390] = \<const0> ;
  assign LOCKSTEP_Out[2391] = \<const0> ;
  assign LOCKSTEP_Out[2392] = \<const0> ;
  assign LOCKSTEP_Out[2393] = \<const0> ;
  assign LOCKSTEP_Out[2394] = \<const0> ;
  assign LOCKSTEP_Out[2395] = \<const0> ;
  assign LOCKSTEP_Out[2396] = \<const0> ;
  assign LOCKSTEP_Out[2397] = \<const0> ;
  assign LOCKSTEP_Out[2398] = \<const0> ;
  assign LOCKSTEP_Out[2399] = \<const0> ;
  assign LOCKSTEP_Out[2400] = \<const0> ;
  assign LOCKSTEP_Out[2401] = \<const0> ;
  assign LOCKSTEP_Out[2402] = \<const0> ;
  assign LOCKSTEP_Out[2403] = \<const0> ;
  assign LOCKSTEP_Out[2404] = \<const0> ;
  assign LOCKSTEP_Out[2405] = \<const0> ;
  assign LOCKSTEP_Out[2406] = \<const0> ;
  assign LOCKSTEP_Out[2407] = \<const0> ;
  assign LOCKSTEP_Out[2408] = \<const0> ;
  assign LOCKSTEP_Out[2409] = \<const0> ;
  assign LOCKSTEP_Out[2410] = \<const0> ;
  assign LOCKSTEP_Out[2411] = \<const0> ;
  assign LOCKSTEP_Out[2412] = \<const0> ;
  assign LOCKSTEP_Out[2413] = \<const0> ;
  assign LOCKSTEP_Out[2414] = \<const0> ;
  assign LOCKSTEP_Out[2415] = \<const0> ;
  assign LOCKSTEP_Out[2416] = \<const0> ;
  assign LOCKSTEP_Out[2417] = \<const0> ;
  assign LOCKSTEP_Out[2418] = \<const0> ;
  assign LOCKSTEP_Out[2419] = \<const0> ;
  assign LOCKSTEP_Out[2420] = \<const0> ;
  assign LOCKSTEP_Out[2421] = \<const0> ;
  assign LOCKSTEP_Out[2422] = \<const0> ;
  assign LOCKSTEP_Out[2423] = \<const0> ;
  assign LOCKSTEP_Out[2424] = \<const0> ;
  assign LOCKSTEP_Out[2425] = \<const0> ;
  assign LOCKSTEP_Out[2426] = \<const0> ;
  assign LOCKSTEP_Out[2427] = \<const0> ;
  assign LOCKSTEP_Out[2428] = \<const0> ;
  assign LOCKSTEP_Out[2429] = \<const0> ;
  assign LOCKSTEP_Out[2430] = \<const0> ;
  assign LOCKSTEP_Out[2431] = \<const0> ;
  assign LOCKSTEP_Out[2432] = \<const0> ;
  assign LOCKSTEP_Out[2433] = \<const0> ;
  assign LOCKSTEP_Out[2434] = \<const0> ;
  assign LOCKSTEP_Out[2435] = \<const0> ;
  assign LOCKSTEP_Out[2436] = \<const0> ;
  assign LOCKSTEP_Out[2437] = \<const0> ;
  assign LOCKSTEP_Out[2438] = \<const0> ;
  assign LOCKSTEP_Out[2439] = \<const0> ;
  assign LOCKSTEP_Out[2440] = \<const0> ;
  assign LOCKSTEP_Out[2441] = \<const0> ;
  assign LOCKSTEP_Out[2442] = \<const0> ;
  assign LOCKSTEP_Out[2443] = \<const0> ;
  assign LOCKSTEP_Out[2444] = \<const0> ;
  assign LOCKSTEP_Out[2445] = \<const0> ;
  assign LOCKSTEP_Out[2446] = \<const0> ;
  assign LOCKSTEP_Out[2447] = \<const0> ;
  assign LOCKSTEP_Out[2448] = \<const0> ;
  assign LOCKSTEP_Out[2449] = \<const0> ;
  assign LOCKSTEP_Out[2450] = \<const0> ;
  assign LOCKSTEP_Out[2451] = \<const0> ;
  assign LOCKSTEP_Out[2452] = \<const0> ;
  assign LOCKSTEP_Out[2453] = \<const0> ;
  assign LOCKSTEP_Out[2454] = \<const0> ;
  assign LOCKSTEP_Out[2455] = \<const0> ;
  assign LOCKSTEP_Out[2456] = \<const0> ;
  assign LOCKSTEP_Out[2457] = \<const0> ;
  assign LOCKSTEP_Out[2458] = \<const0> ;
  assign LOCKSTEP_Out[2459] = \<const0> ;
  assign LOCKSTEP_Out[2460] = \<const0> ;
  assign LOCKSTEP_Out[2461] = \<const0> ;
  assign LOCKSTEP_Out[2462] = \<const0> ;
  assign LOCKSTEP_Out[2463] = \<const0> ;
  assign LOCKSTEP_Out[2464] = \<const0> ;
  assign LOCKSTEP_Out[2465] = \<const0> ;
  assign LOCKSTEP_Out[2466] = \<const0> ;
  assign LOCKSTEP_Out[2467] = \<const0> ;
  assign LOCKSTEP_Out[2468] = \<const0> ;
  assign LOCKSTEP_Out[2469] = \<const0> ;
  assign LOCKSTEP_Out[2470] = \<const0> ;
  assign LOCKSTEP_Out[2471] = \<const0> ;
  assign LOCKSTEP_Out[2472] = \<const0> ;
  assign LOCKSTEP_Out[2473] = \<const0> ;
  assign LOCKSTEP_Out[2474] = \<const0> ;
  assign LOCKSTEP_Out[2475] = \<const0> ;
  assign LOCKSTEP_Out[2476] = \<const0> ;
  assign LOCKSTEP_Out[2477] = \<const0> ;
  assign LOCKSTEP_Out[2478] = \<const0> ;
  assign LOCKSTEP_Out[2479] = \<const0> ;
  assign LOCKSTEP_Out[2480] = \<const0> ;
  assign LOCKSTEP_Out[2481] = \<const0> ;
  assign LOCKSTEP_Out[2482] = \<const0> ;
  assign LOCKSTEP_Out[2483] = \<const0> ;
  assign LOCKSTEP_Out[2484] = \<const0> ;
  assign LOCKSTEP_Out[2485] = \<const0> ;
  assign LOCKSTEP_Out[2486] = \<const0> ;
  assign LOCKSTEP_Out[2487] = \<const0> ;
  assign LOCKSTEP_Out[2488] = \<const0> ;
  assign LOCKSTEP_Out[2489] = \<const0> ;
  assign LOCKSTEP_Out[2490] = \<const0> ;
  assign LOCKSTEP_Out[2491] = \<const0> ;
  assign LOCKSTEP_Out[2492] = \<const0> ;
  assign LOCKSTEP_Out[2493] = \<const0> ;
  assign LOCKSTEP_Out[2494] = \<const0> ;
  assign LOCKSTEP_Out[2495] = \<const0> ;
  assign LOCKSTEP_Out[2496] = \<const0> ;
  assign LOCKSTEP_Out[2497] = \<const0> ;
  assign LOCKSTEP_Out[2498] = \<const0> ;
  assign LOCKSTEP_Out[2499] = \<const0> ;
  assign LOCKSTEP_Out[2500] = \<const0> ;
  assign LOCKSTEP_Out[2501] = \<const0> ;
  assign LOCKSTEP_Out[2502] = \<const0> ;
  assign LOCKSTEP_Out[2503] = \<const0> ;
  assign LOCKSTEP_Out[2504] = \<const0> ;
  assign LOCKSTEP_Out[2505] = \<const0> ;
  assign LOCKSTEP_Out[2506] = \<const0> ;
  assign LOCKSTEP_Out[2507] = \<const0> ;
  assign LOCKSTEP_Out[2508] = \<const0> ;
  assign LOCKSTEP_Out[2509] = \<const0> ;
  assign LOCKSTEP_Out[2510] = \<const0> ;
  assign LOCKSTEP_Out[2511] = \<const0> ;
  assign LOCKSTEP_Out[2512] = \<const0> ;
  assign LOCKSTEP_Out[2513] = \<const0> ;
  assign LOCKSTEP_Out[2514] = \<const0> ;
  assign LOCKSTEP_Out[2515] = \<const0> ;
  assign LOCKSTEP_Out[2516] = \<const0> ;
  assign LOCKSTEP_Out[2517] = \<const0> ;
  assign LOCKSTEP_Out[2518] = \<const0> ;
  assign LOCKSTEP_Out[2519] = \<const0> ;
  assign LOCKSTEP_Out[2520] = \<const0> ;
  assign LOCKSTEP_Out[2521] = \<const0> ;
  assign LOCKSTEP_Out[2522] = \<const0> ;
  assign LOCKSTEP_Out[2523] = \<const0> ;
  assign LOCKSTEP_Out[2524] = \<const0> ;
  assign LOCKSTEP_Out[2525] = \<const0> ;
  assign LOCKSTEP_Out[2526] = \<const0> ;
  assign LOCKSTEP_Out[2527] = \<const0> ;
  assign LOCKSTEP_Out[2528] = \<const0> ;
  assign LOCKSTEP_Out[2529] = \<const0> ;
  assign LOCKSTEP_Out[2530] = \<const0> ;
  assign LOCKSTEP_Out[2531] = \<const0> ;
  assign LOCKSTEP_Out[2532] = \<const0> ;
  assign LOCKSTEP_Out[2533] = \<const0> ;
  assign LOCKSTEP_Out[2534] = \<const0> ;
  assign LOCKSTEP_Out[2535] = \<const0> ;
  assign LOCKSTEP_Out[2536] = \<const0> ;
  assign LOCKSTEP_Out[2537] = \<const0> ;
  assign LOCKSTEP_Out[2538] = \<const0> ;
  assign LOCKSTEP_Out[2539] = \<const0> ;
  assign LOCKSTEP_Out[2540] = \<const0> ;
  assign LOCKSTEP_Out[2541] = \<const0> ;
  assign LOCKSTEP_Out[2542] = \<const0> ;
  assign LOCKSTEP_Out[2543] = \<const0> ;
  assign LOCKSTEP_Out[2544] = \<const0> ;
  assign LOCKSTEP_Out[2545] = \<const0> ;
  assign LOCKSTEP_Out[2546] = \<const0> ;
  assign LOCKSTEP_Out[2547] = \<const0> ;
  assign LOCKSTEP_Out[2548] = \<const0> ;
  assign LOCKSTEP_Out[2549] = \<const0> ;
  assign LOCKSTEP_Out[2550] = \<const0> ;
  assign LOCKSTEP_Out[2551] = \<const0> ;
  assign LOCKSTEP_Out[2552] = \<const0> ;
  assign LOCKSTEP_Out[2553] = \<const0> ;
  assign LOCKSTEP_Out[2554] = \<const0> ;
  assign LOCKSTEP_Out[2555] = \<const0> ;
  assign LOCKSTEP_Out[2556] = \<const0> ;
  assign LOCKSTEP_Out[2557] = \<const0> ;
  assign LOCKSTEP_Out[2558] = \<const0> ;
  assign LOCKSTEP_Out[2559] = \<const0> ;
  assign LOCKSTEP_Out[2560] = \<const0> ;
  assign LOCKSTEP_Out[2561] = \<const0> ;
  assign LOCKSTEP_Out[2562] = \<const0> ;
  assign LOCKSTEP_Out[2563] = \<const0> ;
  assign LOCKSTEP_Out[2564] = \<const0> ;
  assign LOCKSTEP_Out[2565] = \<const0> ;
  assign LOCKSTEP_Out[2566] = \<const0> ;
  assign LOCKSTEP_Out[2567] = \<const0> ;
  assign LOCKSTEP_Out[2568] = \<const0> ;
  assign LOCKSTEP_Out[2569] = \<const0> ;
  assign LOCKSTEP_Out[2570] = \<const0> ;
  assign LOCKSTEP_Out[2571] = \<const0> ;
  assign LOCKSTEP_Out[2572] = \<const0> ;
  assign LOCKSTEP_Out[2573] = \<const0> ;
  assign LOCKSTEP_Out[2574] = \<const0> ;
  assign LOCKSTEP_Out[2575] = \<const0> ;
  assign LOCKSTEP_Out[2576] = \<const0> ;
  assign LOCKSTEP_Out[2577] = \<const0> ;
  assign LOCKSTEP_Out[2578] = \<const0> ;
  assign LOCKSTEP_Out[2579] = \<const0> ;
  assign LOCKSTEP_Out[2580] = \<const0> ;
  assign LOCKSTEP_Out[2581] = \<const0> ;
  assign LOCKSTEP_Out[2582] = \<const0> ;
  assign LOCKSTEP_Out[2583] = \<const0> ;
  assign LOCKSTEP_Out[2584] = \<const0> ;
  assign LOCKSTEP_Out[2585] = \<const0> ;
  assign LOCKSTEP_Out[2586] = \<const0> ;
  assign LOCKSTEP_Out[2587] = \<const0> ;
  assign LOCKSTEP_Out[2588] = \<const0> ;
  assign LOCKSTEP_Out[2589] = \<const0> ;
  assign LOCKSTEP_Out[2590] = \<const0> ;
  assign LOCKSTEP_Out[2591] = \<const0> ;
  assign LOCKSTEP_Out[2592] = \<const0> ;
  assign LOCKSTEP_Out[2593] = \<const0> ;
  assign LOCKSTEP_Out[2594] = \<const0> ;
  assign LOCKSTEP_Out[2595] = \<const0> ;
  assign LOCKSTEP_Out[2596] = \<const0> ;
  assign LOCKSTEP_Out[2597] = \<const0> ;
  assign LOCKSTEP_Out[2598] = \<const0> ;
  assign LOCKSTEP_Out[2599] = \<const0> ;
  assign LOCKSTEP_Out[2600] = \<const0> ;
  assign LOCKSTEP_Out[2601] = \<const0> ;
  assign LOCKSTEP_Out[2602] = \<const0> ;
  assign LOCKSTEP_Out[2603] = \<const0> ;
  assign LOCKSTEP_Out[2604] = \<const0> ;
  assign LOCKSTEP_Out[2605] = \<const0> ;
  assign LOCKSTEP_Out[2606] = \<const0> ;
  assign LOCKSTEP_Out[2607] = \<const0> ;
  assign LOCKSTEP_Out[2608] = \<const0> ;
  assign LOCKSTEP_Out[2609] = \<const0> ;
  assign LOCKSTEP_Out[2610] = \<const0> ;
  assign LOCKSTEP_Out[2611] = \<const0> ;
  assign LOCKSTEP_Out[2612] = \<const0> ;
  assign LOCKSTEP_Out[2613] = \<const0> ;
  assign LOCKSTEP_Out[2614] = \<const0> ;
  assign LOCKSTEP_Out[2615] = \<const0> ;
  assign LOCKSTEP_Out[2616] = \<const0> ;
  assign LOCKSTEP_Out[2617] = \<const0> ;
  assign LOCKSTEP_Out[2618] = \<const0> ;
  assign LOCKSTEP_Out[2619] = \<const0> ;
  assign LOCKSTEP_Out[2620] = \<const0> ;
  assign LOCKSTEP_Out[2621] = \<const0> ;
  assign LOCKSTEP_Out[2622] = \<const0> ;
  assign LOCKSTEP_Out[2623] = \<const0> ;
  assign LOCKSTEP_Out[2624] = \<const0> ;
  assign LOCKSTEP_Out[2625] = \<const0> ;
  assign LOCKSTEP_Out[2626] = \<const0> ;
  assign LOCKSTEP_Out[2627] = \<const0> ;
  assign LOCKSTEP_Out[2628] = \<const0> ;
  assign LOCKSTEP_Out[2629] = \<const0> ;
  assign LOCKSTEP_Out[2630] = \<const0> ;
  assign LOCKSTEP_Out[2631] = \<const0> ;
  assign LOCKSTEP_Out[2632] = \<const0> ;
  assign LOCKSTEP_Out[2633] = \<const0> ;
  assign LOCKSTEP_Out[2634] = \<const0> ;
  assign LOCKSTEP_Out[2635] = \<const0> ;
  assign LOCKSTEP_Out[2636] = \<const0> ;
  assign LOCKSTEP_Out[2637] = \<const0> ;
  assign LOCKSTEP_Out[2638] = \<const0> ;
  assign LOCKSTEP_Out[2639] = \<const0> ;
  assign LOCKSTEP_Out[2640] = \<const0> ;
  assign LOCKSTEP_Out[2641] = \<const0> ;
  assign LOCKSTEP_Out[2642] = \<const0> ;
  assign LOCKSTEP_Out[2643] = \<const0> ;
  assign LOCKSTEP_Out[2644] = \<const0> ;
  assign LOCKSTEP_Out[2645] = \<const0> ;
  assign LOCKSTEP_Out[2646] = \<const0> ;
  assign LOCKSTEP_Out[2647] = \<const0> ;
  assign LOCKSTEP_Out[2648] = \<const0> ;
  assign LOCKSTEP_Out[2649] = \<const0> ;
  assign LOCKSTEP_Out[2650] = \<const0> ;
  assign LOCKSTEP_Out[2651] = \<const0> ;
  assign LOCKSTEP_Out[2652] = \<const0> ;
  assign LOCKSTEP_Out[2653] = \<const0> ;
  assign LOCKSTEP_Out[2654] = \<const0> ;
  assign LOCKSTEP_Out[2655] = \<const0> ;
  assign LOCKSTEP_Out[2656] = \<const0> ;
  assign LOCKSTEP_Out[2657] = \<const0> ;
  assign LOCKSTEP_Out[2658] = \<const0> ;
  assign LOCKSTEP_Out[2659] = \<const0> ;
  assign LOCKSTEP_Out[2660] = \<const0> ;
  assign LOCKSTEP_Out[2661] = \<const0> ;
  assign LOCKSTEP_Out[2662] = \<const0> ;
  assign LOCKSTEP_Out[2663] = \<const0> ;
  assign LOCKSTEP_Out[2664] = \<const0> ;
  assign LOCKSTEP_Out[2665] = \<const0> ;
  assign LOCKSTEP_Out[2666] = \<const0> ;
  assign LOCKSTEP_Out[2667] = \<const0> ;
  assign LOCKSTEP_Out[2668] = \<const0> ;
  assign LOCKSTEP_Out[2669] = \<const0> ;
  assign LOCKSTEP_Out[2670] = \<const0> ;
  assign LOCKSTEP_Out[2671] = \<const0> ;
  assign LOCKSTEP_Out[2672] = \<const0> ;
  assign LOCKSTEP_Out[2673] = \<const0> ;
  assign LOCKSTEP_Out[2674] = \<const0> ;
  assign LOCKSTEP_Out[2675] = \<const0> ;
  assign LOCKSTEP_Out[2676] = \<const0> ;
  assign LOCKSTEP_Out[2677] = \<const0> ;
  assign LOCKSTEP_Out[2678] = \<const0> ;
  assign LOCKSTEP_Out[2679] = \<const0> ;
  assign LOCKSTEP_Out[2680] = \<const0> ;
  assign LOCKSTEP_Out[2681] = \<const0> ;
  assign LOCKSTEP_Out[2682] = \<const0> ;
  assign LOCKSTEP_Out[2683] = \<const0> ;
  assign LOCKSTEP_Out[2684] = \<const0> ;
  assign LOCKSTEP_Out[2685] = \<const0> ;
  assign LOCKSTEP_Out[2686] = \<const0> ;
  assign LOCKSTEP_Out[2687] = \<const0> ;
  assign LOCKSTEP_Out[2688] = \<const0> ;
  assign LOCKSTEP_Out[2689] = \<const0> ;
  assign LOCKSTEP_Out[2690] = \<const0> ;
  assign LOCKSTEP_Out[2691] = \<const0> ;
  assign LOCKSTEP_Out[2692] = \<const0> ;
  assign LOCKSTEP_Out[2693] = \<const0> ;
  assign LOCKSTEP_Out[2694] = \<const0> ;
  assign LOCKSTEP_Out[2695] = \<const0> ;
  assign LOCKSTEP_Out[2696] = \<const0> ;
  assign LOCKSTEP_Out[2697] = \<const0> ;
  assign LOCKSTEP_Out[2698] = \<const0> ;
  assign LOCKSTEP_Out[2699] = \<const0> ;
  assign LOCKSTEP_Out[2700] = \<const0> ;
  assign LOCKSTEP_Out[2701] = \<const0> ;
  assign LOCKSTEP_Out[2702] = \<const0> ;
  assign LOCKSTEP_Out[2703] = \<const0> ;
  assign LOCKSTEP_Out[2704] = \<const0> ;
  assign LOCKSTEP_Out[2705] = \<const0> ;
  assign LOCKSTEP_Out[2706] = \<const0> ;
  assign LOCKSTEP_Out[2707] = \<const0> ;
  assign LOCKSTEP_Out[2708] = \<const0> ;
  assign LOCKSTEP_Out[2709] = \<const0> ;
  assign LOCKSTEP_Out[2710] = \<const0> ;
  assign LOCKSTEP_Out[2711] = \<const0> ;
  assign LOCKSTEP_Out[2712] = \<const0> ;
  assign LOCKSTEP_Out[2713] = \<const0> ;
  assign LOCKSTEP_Out[2714] = \<const0> ;
  assign LOCKSTEP_Out[2715] = \<const0> ;
  assign LOCKSTEP_Out[2716] = \<const0> ;
  assign LOCKSTEP_Out[2717] = \<const0> ;
  assign LOCKSTEP_Out[2718] = \<const0> ;
  assign LOCKSTEP_Out[2719] = \<const0> ;
  assign LOCKSTEP_Out[2720] = \<const0> ;
  assign LOCKSTEP_Out[2721] = \<const0> ;
  assign LOCKSTEP_Out[2722] = \<const0> ;
  assign LOCKSTEP_Out[2723] = \<const0> ;
  assign LOCKSTEP_Out[2724] = \<const0> ;
  assign LOCKSTEP_Out[2725] = \<const0> ;
  assign LOCKSTEP_Out[2726] = \<const0> ;
  assign LOCKSTEP_Out[2727] = \<const0> ;
  assign LOCKSTEP_Out[2728] = \<const0> ;
  assign LOCKSTEP_Out[2729] = \<const0> ;
  assign LOCKSTEP_Out[2730] = \<const0> ;
  assign LOCKSTEP_Out[2731] = \<const0> ;
  assign LOCKSTEP_Out[2732] = \<const0> ;
  assign LOCKSTEP_Out[2733] = \<const0> ;
  assign LOCKSTEP_Out[2734] = \<const0> ;
  assign LOCKSTEP_Out[2735] = \<const0> ;
  assign LOCKSTEP_Out[2736] = \<const0> ;
  assign LOCKSTEP_Out[2737] = \<const0> ;
  assign LOCKSTEP_Out[2738] = \<const0> ;
  assign LOCKSTEP_Out[2739] = \<const0> ;
  assign LOCKSTEP_Out[2740] = \<const0> ;
  assign LOCKSTEP_Out[2741] = \<const0> ;
  assign LOCKSTEP_Out[2742] = \<const0> ;
  assign LOCKSTEP_Out[2743] = \<const0> ;
  assign LOCKSTEP_Out[2744] = \<const0> ;
  assign LOCKSTEP_Out[2745] = \<const0> ;
  assign LOCKSTEP_Out[2746] = \<const0> ;
  assign LOCKSTEP_Out[2747] = \<const0> ;
  assign LOCKSTEP_Out[2748] = \<const0> ;
  assign LOCKSTEP_Out[2749] = \<const0> ;
  assign LOCKSTEP_Out[2750] = \<const0> ;
  assign LOCKSTEP_Out[2751] = \<const0> ;
  assign LOCKSTEP_Out[2752] = \<const0> ;
  assign LOCKSTEP_Out[2753] = \<const0> ;
  assign LOCKSTEP_Out[2754] = \<const0> ;
  assign LOCKSTEP_Out[2755] = \<const0> ;
  assign LOCKSTEP_Out[2756] = \<const0> ;
  assign LOCKSTEP_Out[2757] = \<const0> ;
  assign LOCKSTEP_Out[2758] = \<const0> ;
  assign LOCKSTEP_Out[2759] = \<const0> ;
  assign LOCKSTEP_Out[2760] = \<const0> ;
  assign LOCKSTEP_Out[2761] = \<const0> ;
  assign LOCKSTEP_Out[2762] = \<const0> ;
  assign LOCKSTEP_Out[2763] = \<const0> ;
  assign LOCKSTEP_Out[2764] = \<const0> ;
  assign LOCKSTEP_Out[2765] = \<const0> ;
  assign LOCKSTEP_Out[2766] = \<const0> ;
  assign LOCKSTEP_Out[2767] = \<const0> ;
  assign LOCKSTEP_Out[2768] = \<const0> ;
  assign LOCKSTEP_Out[2769] = \<const0> ;
  assign LOCKSTEP_Out[2770] = \<const0> ;
  assign LOCKSTEP_Out[2771] = \<const0> ;
  assign LOCKSTEP_Out[2772] = \<const0> ;
  assign LOCKSTEP_Out[2773] = \<const0> ;
  assign LOCKSTEP_Out[2774] = \<const0> ;
  assign LOCKSTEP_Out[2775] = \<const0> ;
  assign LOCKSTEP_Out[2776] = \<const0> ;
  assign LOCKSTEP_Out[2777] = \<const0> ;
  assign LOCKSTEP_Out[2778] = \<const0> ;
  assign LOCKSTEP_Out[2779] = \<const0> ;
  assign LOCKSTEP_Out[2780] = \<const0> ;
  assign LOCKSTEP_Out[2781] = \<const0> ;
  assign LOCKSTEP_Out[2782] = \<const0> ;
  assign LOCKSTEP_Out[2783] = \<const0> ;
  assign LOCKSTEP_Out[2784] = \<const0> ;
  assign LOCKSTEP_Out[2785] = \<const0> ;
  assign LOCKSTEP_Out[2786] = \<const0> ;
  assign LOCKSTEP_Out[2787] = \<const0> ;
  assign LOCKSTEP_Out[2788] = \<const0> ;
  assign LOCKSTEP_Out[2789] = \<const0> ;
  assign LOCKSTEP_Out[2790] = \<const0> ;
  assign LOCKSTEP_Out[2791] = \<const0> ;
  assign LOCKSTEP_Out[2792] = \<const0> ;
  assign LOCKSTEP_Out[2793] = \<const0> ;
  assign LOCKSTEP_Out[2794] = \<const0> ;
  assign LOCKSTEP_Out[2795] = \<const0> ;
  assign LOCKSTEP_Out[2796] = \<const0> ;
  assign LOCKSTEP_Out[2797] = \<const0> ;
  assign LOCKSTEP_Out[2798] = \<const0> ;
  assign LOCKSTEP_Out[2799] = \<const0> ;
  assign LOCKSTEP_Out[2800] = \<const0> ;
  assign LOCKSTEP_Out[2801] = \<const0> ;
  assign LOCKSTEP_Out[2802] = \<const0> ;
  assign LOCKSTEP_Out[2803] = \<const0> ;
  assign LOCKSTEP_Out[2804] = \<const0> ;
  assign LOCKSTEP_Out[2805] = \<const0> ;
  assign LOCKSTEP_Out[2806] = \<const0> ;
  assign LOCKSTEP_Out[2807] = \<const0> ;
  assign LOCKSTEP_Out[2808] = \<const0> ;
  assign LOCKSTEP_Out[2809] = \<const0> ;
  assign LOCKSTEP_Out[2810] = \<const0> ;
  assign LOCKSTEP_Out[2811] = \<const0> ;
  assign LOCKSTEP_Out[2812] = \<const0> ;
  assign LOCKSTEP_Out[2813] = \<const0> ;
  assign LOCKSTEP_Out[2814] = \<const0> ;
  assign LOCKSTEP_Out[2815] = \<const0> ;
  assign LOCKSTEP_Out[2816] = \<const0> ;
  assign LOCKSTEP_Out[2817] = \<const0> ;
  assign LOCKSTEP_Out[2818] = \<const0> ;
  assign LOCKSTEP_Out[2819] = \<const0> ;
  assign LOCKSTEP_Out[2820] = \<const0> ;
  assign LOCKSTEP_Out[2821] = \<const0> ;
  assign LOCKSTEP_Out[2822] = \<const0> ;
  assign LOCKSTEP_Out[2823] = \<const0> ;
  assign LOCKSTEP_Out[2824] = \<const0> ;
  assign LOCKSTEP_Out[2825] = \<const0> ;
  assign LOCKSTEP_Out[2826] = \<const0> ;
  assign LOCKSTEP_Out[2827] = \<const0> ;
  assign LOCKSTEP_Out[2828] = \<const0> ;
  assign LOCKSTEP_Out[2829] = \<const0> ;
  assign LOCKSTEP_Out[2830] = \<const0> ;
  assign LOCKSTEP_Out[2831] = \<const0> ;
  assign LOCKSTEP_Out[2832] = \<const0> ;
  assign LOCKSTEP_Out[2833] = \<const0> ;
  assign LOCKSTEP_Out[2834] = \<const0> ;
  assign LOCKSTEP_Out[2835] = \<const0> ;
  assign LOCKSTEP_Out[2836] = \<const0> ;
  assign LOCKSTEP_Out[2837] = \<const0> ;
  assign LOCKSTEP_Out[2838] = \<const0> ;
  assign LOCKSTEP_Out[2839] = \<const0> ;
  assign LOCKSTEP_Out[2840] = \<const0> ;
  assign LOCKSTEP_Out[2841] = \<const0> ;
  assign LOCKSTEP_Out[2842] = \<const0> ;
  assign LOCKSTEP_Out[2843] = \<const0> ;
  assign LOCKSTEP_Out[2844] = \<const0> ;
  assign LOCKSTEP_Out[2845] = \<const0> ;
  assign LOCKSTEP_Out[2846] = \<const0> ;
  assign LOCKSTEP_Out[2847] = \<const0> ;
  assign LOCKSTEP_Out[2848] = \<const0> ;
  assign LOCKSTEP_Out[2849] = \<const0> ;
  assign LOCKSTEP_Out[2850] = \<const0> ;
  assign LOCKSTEP_Out[2851] = \<const0> ;
  assign LOCKSTEP_Out[2852] = \<const0> ;
  assign LOCKSTEP_Out[2853] = \<const0> ;
  assign LOCKSTEP_Out[2854] = \<const0> ;
  assign LOCKSTEP_Out[2855] = \<const0> ;
  assign LOCKSTEP_Out[2856] = \<const0> ;
  assign LOCKSTEP_Out[2857] = \<const0> ;
  assign LOCKSTEP_Out[2858] = \<const0> ;
  assign LOCKSTEP_Out[2859] = \<const0> ;
  assign LOCKSTEP_Out[2860] = \<const0> ;
  assign LOCKSTEP_Out[2861] = \<const0> ;
  assign LOCKSTEP_Out[2862] = \<const0> ;
  assign LOCKSTEP_Out[2863] = \<const0> ;
  assign LOCKSTEP_Out[2864] = \<const0> ;
  assign LOCKSTEP_Out[2865] = \<const0> ;
  assign LOCKSTEP_Out[2866] = \<const0> ;
  assign LOCKSTEP_Out[2867] = \<const0> ;
  assign LOCKSTEP_Out[2868] = \<const0> ;
  assign LOCKSTEP_Out[2869] = \<const0> ;
  assign LOCKSTEP_Out[2870] = \<const0> ;
  assign LOCKSTEP_Out[2871] = \<const0> ;
  assign LOCKSTEP_Out[2872] = \<const0> ;
  assign LOCKSTEP_Out[2873] = \<const0> ;
  assign LOCKSTEP_Out[2874] = \<const0> ;
  assign LOCKSTEP_Out[2875] = \<const0> ;
  assign LOCKSTEP_Out[2876] = \<const0> ;
  assign LOCKSTEP_Out[2877] = \<const0> ;
  assign LOCKSTEP_Out[2878] = \<const0> ;
  assign LOCKSTEP_Out[2879] = \<const0> ;
  assign LOCKSTEP_Out[2880] = \<const0> ;
  assign LOCKSTEP_Out[2881:2945] = \^LOCKSTEP_Out [2881:2945];
  assign LOCKSTEP_Out[2946] = \<const0> ;
  assign LOCKSTEP_Out[2947] = \<const0> ;
  assign LOCKSTEP_Out[2948] = \<const0> ;
  assign LOCKSTEP_Out[2949] = \<const0> ;
  assign LOCKSTEP_Out[2950] = \<const0> ;
  assign LOCKSTEP_Out[2951] = \<const0> ;
  assign LOCKSTEP_Out[2952] = \<const0> ;
  assign LOCKSTEP_Out[2953] = \<const0> ;
  assign LOCKSTEP_Out[2954] = \<const0> ;
  assign LOCKSTEP_Out[2955] = \<const0> ;
  assign LOCKSTEP_Out[2956] = \<const0> ;
  assign LOCKSTEP_Out[2957] = \<const0> ;
  assign LOCKSTEP_Out[2958] = \<const0> ;
  assign LOCKSTEP_Out[2959] = \<const0> ;
  assign LOCKSTEP_Out[2960] = \<const0> ;
  assign LOCKSTEP_Out[2961] = \<const0> ;
  assign LOCKSTEP_Out[2962] = \<const0> ;
  assign LOCKSTEP_Out[2963] = \<const0> ;
  assign LOCKSTEP_Out[2964] = \<const0> ;
  assign LOCKSTEP_Out[2965] = \<const0> ;
  assign LOCKSTEP_Out[2966] = \<const0> ;
  assign LOCKSTEP_Out[2967] = \<const0> ;
  assign LOCKSTEP_Out[2968] = \<const0> ;
  assign LOCKSTEP_Out[2969] = \<const0> ;
  assign LOCKSTEP_Out[2970] = \<const0> ;
  assign LOCKSTEP_Out[2971] = \<const0> ;
  assign LOCKSTEP_Out[2972] = \<const0> ;
  assign LOCKSTEP_Out[2973] = \<const0> ;
  assign LOCKSTEP_Out[2974] = \<const0> ;
  assign LOCKSTEP_Out[2975] = \<const0> ;
  assign LOCKSTEP_Out[2976] = \<const0> ;
  assign LOCKSTEP_Out[2977] = \<const0> ;
  assign LOCKSTEP_Out[2978:2983] = \^LOCKSTEP_Out [2978:2983];
  assign LOCKSTEP_Out[2984] = \<const0> ;
  assign LOCKSTEP_Out[2985] = \<const0> ;
  assign LOCKSTEP_Out[2986] = \<const0> ;
  assign LOCKSTEP_Out[2987] = \<const0> ;
  assign LOCKSTEP_Out[2988] = \<const0> ;
  assign LOCKSTEP_Out[2989] = \<const0> ;
  assign LOCKSTEP_Out[2990] = \<const0> ;
  assign LOCKSTEP_Out[2991] = \<const0> ;
  assign LOCKSTEP_Out[2992] = \<const0> ;
  assign LOCKSTEP_Out[2993] = \<const0> ;
  assign LOCKSTEP_Out[2994] = \<const0> ;
  assign LOCKSTEP_Out[2995:2997] = \^LOCKSTEP_Out [2995:2997];
  assign LOCKSTEP_Out[2998] = \<const0> ;
  assign LOCKSTEP_Out[2999] = \<const0> ;
  assign LOCKSTEP_Out[3000] = \<const0> ;
  assign LOCKSTEP_Out[3001] = \<const0> ;
  assign LOCKSTEP_Out[3002] = \<const0> ;
  assign LOCKSTEP_Out[3003] = \<const0> ;
  assign LOCKSTEP_Out[3004] = \<const0> ;
  assign LOCKSTEP_Out[3005] = \<const0> ;
  assign LOCKSTEP_Out[3006] = \<const0> ;
  assign LOCKSTEP_Out[3007:3038] = \^LOCKSTEP_Out [3007:3038];
  assign LOCKSTEP_Out[3039] = \<const0> ;
  assign LOCKSTEP_Out[3040] = \<const0> ;
  assign LOCKSTEP_Out[3041] = \<const0> ;
  assign LOCKSTEP_Out[3042] = \<const0> ;
  assign LOCKSTEP_Out[3043] = \<const0> ;
  assign LOCKSTEP_Out[3044] = \<const0> ;
  assign LOCKSTEP_Out[3045] = \<const0> ;
  assign LOCKSTEP_Out[3046] = \<const0> ;
  assign LOCKSTEP_Out[3047] = \<const0> ;
  assign LOCKSTEP_Out[3048] = \<const0> ;
  assign LOCKSTEP_Out[3049] = \<const0> ;
  assign LOCKSTEP_Out[3050] = \<const0> ;
  assign LOCKSTEP_Out[3051] = \<const0> ;
  assign LOCKSTEP_Out[3052] = \<const0> ;
  assign LOCKSTEP_Out[3053] = \<const0> ;
  assign LOCKSTEP_Out[3054] = \<const0> ;
  assign LOCKSTEP_Out[3055] = \<const0> ;
  assign LOCKSTEP_Out[3056] = \<const0> ;
  assign LOCKSTEP_Out[3057] = \<const0> ;
  assign LOCKSTEP_Out[3058] = \<const0> ;
  assign LOCKSTEP_Out[3059] = \<const0> ;
  assign LOCKSTEP_Out[3060] = \<const0> ;
  assign LOCKSTEP_Out[3061] = \<const0> ;
  assign LOCKSTEP_Out[3062] = \<const0> ;
  assign LOCKSTEP_Out[3063] = \<const0> ;
  assign LOCKSTEP_Out[3064] = \<const0> ;
  assign LOCKSTEP_Out[3065] = \<const0> ;
  assign LOCKSTEP_Out[3066] = \<const0> ;
  assign LOCKSTEP_Out[3067] = \<const0> ;
  assign LOCKSTEP_Out[3068] = \<const0> ;
  assign LOCKSTEP_Out[3069] = \<const0> ;
  assign LOCKSTEP_Out[3070] = \<const0> ;
  assign LOCKSTEP_Out[3071] = \^LOCKSTEP_Out [3071];
  assign LOCKSTEP_Out[3072] = \<const0> ;
  assign LOCKSTEP_Out[3073] = \^LOCKSTEP_Out [3073];
  assign LOCKSTEP_Out[3074] = \<const0> ;
  assign LOCKSTEP_Out[3075] = \<const0> ;
  assign LOCKSTEP_Out[3076:3110] = \^LOCKSTEP_Out [3076:3110];
  assign LOCKSTEP_Out[3111] = \<const0> ;
  assign LOCKSTEP_Out[3112] = \<const0> ;
  assign LOCKSTEP_Out[3113] = \<const0> ;
  assign LOCKSTEP_Out[3114] = \<const0> ;
  assign LOCKSTEP_Out[3115] = \<const0> ;
  assign LOCKSTEP_Out[3116] = \<const0> ;
  assign LOCKSTEP_Out[3117] = \<const0> ;
  assign LOCKSTEP_Out[3118] = \<const0> ;
  assign LOCKSTEP_Out[3119] = \<const0> ;
  assign LOCKSTEP_Out[3120] = \<const0> ;
  assign LOCKSTEP_Out[3121] = \<const0> ;
  assign LOCKSTEP_Out[3122] = \<const0> ;
  assign LOCKSTEP_Out[3123] = \<const0> ;
  assign LOCKSTEP_Out[3124] = \<const0> ;
  assign LOCKSTEP_Out[3125] = \<const0> ;
  assign LOCKSTEP_Out[3126] = \<const0> ;
  assign LOCKSTEP_Out[3127] = \<const0> ;
  assign LOCKSTEP_Out[3128] = \<const0> ;
  assign LOCKSTEP_Out[3129] = \<const0> ;
  assign LOCKSTEP_Out[3130] = \<const0> ;
  assign LOCKSTEP_Out[3131] = \<const0> ;
  assign LOCKSTEP_Out[3132] = \<const0> ;
  assign LOCKSTEP_Out[3133] = \<const0> ;
  assign LOCKSTEP_Out[3134] = \<const0> ;
  assign LOCKSTEP_Out[3135] = \<const0> ;
  assign LOCKSTEP_Out[3136] = \<const0> ;
  assign LOCKSTEP_Out[3137] = \<const0> ;
  assign LOCKSTEP_Out[3138] = \<const0> ;
  assign LOCKSTEP_Out[3139] = \<const0> ;
  assign LOCKSTEP_Out[3140] = \<const0> ;
  assign LOCKSTEP_Out[3141] = \<const0> ;
  assign LOCKSTEP_Out[3142] = \<const0> ;
  assign LOCKSTEP_Out[3143:3174] = \^LOCKSTEP_Out [3143:3174];
  assign LOCKSTEP_Out[3175] = \<const0> ;
  assign LOCKSTEP_Out[3176] = \<const0> ;
  assign LOCKSTEP_Out[3177] = \<const0> ;
  assign LOCKSTEP_Out[3178] = \<const0> ;
  assign LOCKSTEP_Out[3179] = \<const0> ;
  assign LOCKSTEP_Out[3180] = \<const0> ;
  assign LOCKSTEP_Out[3181] = \<const0> ;
  assign LOCKSTEP_Out[3182] = \<const0> ;
  assign LOCKSTEP_Out[3183] = \<const0> ;
  assign LOCKSTEP_Out[3184] = \<const0> ;
  assign LOCKSTEP_Out[3185] = \<const0> ;
  assign LOCKSTEP_Out[3186] = \<const0> ;
  assign LOCKSTEP_Out[3187] = \<const0> ;
  assign LOCKSTEP_Out[3188] = \<const0> ;
  assign LOCKSTEP_Out[3189] = \<const0> ;
  assign LOCKSTEP_Out[3190] = \<const0> ;
  assign LOCKSTEP_Out[3191] = \<const0> ;
  assign LOCKSTEP_Out[3192] = \<const0> ;
  assign LOCKSTEP_Out[3193] = \<const0> ;
  assign LOCKSTEP_Out[3194] = \<const0> ;
  assign LOCKSTEP_Out[3195] = \<const0> ;
  assign LOCKSTEP_Out[3196] = \<const0> ;
  assign LOCKSTEP_Out[3197] = \<const0> ;
  assign LOCKSTEP_Out[3198] = \<const0> ;
  assign LOCKSTEP_Out[3199] = \<const0> ;
  assign LOCKSTEP_Out[3200] = \<const0> ;
  assign LOCKSTEP_Out[3201] = \<const0> ;
  assign LOCKSTEP_Out[3202] = \<const0> ;
  assign LOCKSTEP_Out[3203] = \<const0> ;
  assign LOCKSTEP_Out[3204] = \<const0> ;
  assign LOCKSTEP_Out[3205] = \<const0> ;
  assign LOCKSTEP_Out[3206] = \<const0> ;
  assign LOCKSTEP_Out[3207:3210] = \^LOCKSTEP_Out [3207:3210];
  assign LOCKSTEP_Out[3211] = \<const0> ;
  assign LOCKSTEP_Out[3212] = \<const0> ;
  assign LOCKSTEP_Out[3213] = \<const0> ;
  assign LOCKSTEP_Out[3214] = \<const0> ;
  assign LOCKSTEP_Out[3215:3217] = \^LOCKSTEP_Out [3215:3217];
  assign LOCKSTEP_Out[3218] = \<const0> ;
  assign LOCKSTEP_Out[3219] = \<const0> ;
  assign LOCKSTEP_Out[3220] = \<const0> ;
  assign LOCKSTEP_Out[3221] = \<const0> ;
  assign LOCKSTEP_Out[3222] = \<const0> ;
  assign LOCKSTEP_Out[3223] = \<const0> ;
  assign LOCKSTEP_Out[3224] = \<const0> ;
  assign LOCKSTEP_Out[3225:3228] = \^LOCKSTEP_Out [3225:3228];
  assign LOCKSTEP_Out[3229] = \<const0> ;
  assign LOCKSTEP_Out[3230] = \<const0> ;
  assign LOCKSTEP_Out[3231] = \<const0> ;
  assign LOCKSTEP_Out[3232] = \<const0> ;
  assign LOCKSTEP_Out[3233] = \<const0> ;
  assign LOCKSTEP_Out[3234] = \<const0> ;
  assign LOCKSTEP_Out[3235] = \<const0> ;
  assign LOCKSTEP_Out[3236] = \<const0> ;
  assign LOCKSTEP_Out[3237] = \<const0> ;
  assign LOCKSTEP_Out[3238] = \<const0> ;
  assign LOCKSTEP_Out[3239] = \<const0> ;
  assign LOCKSTEP_Out[3240] = \<const0> ;
  assign LOCKSTEP_Out[3241] = \<const0> ;
  assign LOCKSTEP_Out[3242] = \<const0> ;
  assign LOCKSTEP_Out[3243] = \<const0> ;
  assign LOCKSTEP_Out[3244] = \<const0> ;
  assign LOCKSTEP_Out[3245] = \<const0> ;
  assign LOCKSTEP_Out[3246] = \<const0> ;
  assign LOCKSTEP_Out[3247] = \<const0> ;
  assign LOCKSTEP_Out[3248] = \<const0> ;
  assign LOCKSTEP_Out[3249] = \<const0> ;
  assign LOCKSTEP_Out[3250] = \<const0> ;
  assign LOCKSTEP_Out[3251] = \<const0> ;
  assign LOCKSTEP_Out[3252] = \<const0> ;
  assign LOCKSTEP_Out[3253] = \<const0> ;
  assign LOCKSTEP_Out[3254] = \<const0> ;
  assign LOCKSTEP_Out[3255] = \<const0> ;
  assign LOCKSTEP_Out[3256] = \<const0> ;
  assign LOCKSTEP_Out[3257] = \<const0> ;
  assign LOCKSTEP_Out[3258] = \<const0> ;
  assign LOCKSTEP_Out[3259] = \<const0> ;
  assign LOCKSTEP_Out[3260] = \<const0> ;
  assign LOCKSTEP_Out[3261] = \<const0> ;
  assign LOCKSTEP_Out[3262] = \<const0> ;
  assign LOCKSTEP_Out[3263] = \<const0> ;
  assign LOCKSTEP_Out[3264] = \<const0> ;
  assign LOCKSTEP_Out[3265] = \<const0> ;
  assign LOCKSTEP_Out[3266] = \<const0> ;
  assign LOCKSTEP_Out[3267] = \<const0> ;
  assign LOCKSTEP_Out[3268] = \<const0> ;
  assign LOCKSTEP_Out[3269] = \<const0> ;
  assign LOCKSTEP_Out[3270] = \<const0> ;
  assign LOCKSTEP_Out[3271] = \<const0> ;
  assign LOCKSTEP_Out[3272] = \<const0> ;
  assign LOCKSTEP_Out[3273] = \<const0> ;
  assign LOCKSTEP_Out[3274] = \<const0> ;
  assign LOCKSTEP_Out[3275] = \<const0> ;
  assign LOCKSTEP_Out[3276] = \<const0> ;
  assign LOCKSTEP_Out[3277] = \<const0> ;
  assign LOCKSTEP_Out[3278] = \<const0> ;
  assign LOCKSTEP_Out[3279] = \<const0> ;
  assign LOCKSTEP_Out[3280] = \<const0> ;
  assign LOCKSTEP_Out[3281] = \<const0> ;
  assign LOCKSTEP_Out[3282] = \<const0> ;
  assign LOCKSTEP_Out[3283] = \<const0> ;
  assign LOCKSTEP_Out[3284] = \<const0> ;
  assign LOCKSTEP_Out[3285] = \<const0> ;
  assign LOCKSTEP_Out[3286] = \<const0> ;
  assign LOCKSTEP_Out[3287] = \<const0> ;
  assign LOCKSTEP_Out[3288] = \<const0> ;
  assign LOCKSTEP_Out[3289] = \<const0> ;
  assign LOCKSTEP_Out[3290] = \<const0> ;
  assign LOCKSTEP_Out[3291] = \<const0> ;
  assign LOCKSTEP_Out[3292] = \<const0> ;
  assign LOCKSTEP_Out[3293] = \<const0> ;
  assign LOCKSTEP_Out[3294] = \<const0> ;
  assign LOCKSTEP_Out[3295] = \<const0> ;
  assign LOCKSTEP_Out[3296] = \<const0> ;
  assign LOCKSTEP_Out[3297] = \<const0> ;
  assign LOCKSTEP_Out[3298] = \<const0> ;
  assign LOCKSTEP_Out[3299] = \<const0> ;
  assign LOCKSTEP_Out[3300] = \<const0> ;
  assign LOCKSTEP_Out[3301] = \<const0> ;
  assign LOCKSTEP_Out[3302] = \<const0> ;
  assign LOCKSTEP_Out[3303] = \<const0> ;
  assign LOCKSTEP_Out[3304] = \<const0> ;
  assign LOCKSTEP_Out[3305] = \<const0> ;
  assign LOCKSTEP_Out[3306] = \<const0> ;
  assign LOCKSTEP_Out[3307] = \<const0> ;
  assign LOCKSTEP_Out[3308] = \<const0> ;
  assign LOCKSTEP_Out[3309] = \<const0> ;
  assign LOCKSTEP_Out[3310] = \<const0> ;
  assign LOCKSTEP_Out[3311] = \<const0> ;
  assign LOCKSTEP_Out[3312] = \<const0> ;
  assign LOCKSTEP_Out[3313] = \<const0> ;
  assign LOCKSTEP_Out[3314] = \<const0> ;
  assign LOCKSTEP_Out[3315] = \<const0> ;
  assign LOCKSTEP_Out[3316] = \<const0> ;
  assign LOCKSTEP_Out[3317] = \<const0> ;
  assign LOCKSTEP_Out[3318] = \<const0> ;
  assign LOCKSTEP_Out[3319] = \<const0> ;
  assign LOCKSTEP_Out[3320] = \<const0> ;
  assign LOCKSTEP_Out[3321] = \<const0> ;
  assign LOCKSTEP_Out[3322] = \<const0> ;
  assign LOCKSTEP_Out[3323] = \<const0> ;
  assign LOCKSTEP_Out[3324] = \<const0> ;
  assign LOCKSTEP_Out[3325] = \<const0> ;
  assign LOCKSTEP_Out[3326] = \<const0> ;
  assign LOCKSTEP_Out[3327] = \<const0> ;
  assign LOCKSTEP_Out[3328] = \<const0> ;
  assign LOCKSTEP_Out[3329] = \<const0> ;
  assign LOCKSTEP_Out[3330] = \<const0> ;
  assign LOCKSTEP_Out[3331] = \<const0> ;
  assign LOCKSTEP_Out[3332] = \<const0> ;
  assign LOCKSTEP_Out[3333] = \<const0> ;
  assign LOCKSTEP_Out[3334] = \<const0> ;
  assign LOCKSTEP_Out[3335] = \<const0> ;
  assign LOCKSTEP_Out[3336] = \<const0> ;
  assign LOCKSTEP_Out[3337] = \<const0> ;
  assign LOCKSTEP_Out[3338] = \<const0> ;
  assign LOCKSTEP_Out[3339] = \<const0> ;
  assign LOCKSTEP_Out[3340] = \<const0> ;
  assign LOCKSTEP_Out[3341] = \<const0> ;
  assign LOCKSTEP_Out[3342] = \<const0> ;
  assign LOCKSTEP_Out[3343] = \<const0> ;
  assign LOCKSTEP_Out[3344] = \<const0> ;
  assign LOCKSTEP_Out[3345] = \<const0> ;
  assign LOCKSTEP_Out[3346] = \<const0> ;
  assign LOCKSTEP_Out[3347] = \<const0> ;
  assign LOCKSTEP_Out[3348] = \<const0> ;
  assign LOCKSTEP_Out[3349] = \<const0> ;
  assign LOCKSTEP_Out[3350] = \<const0> ;
  assign LOCKSTEP_Out[3351] = \<const0> ;
  assign LOCKSTEP_Out[3352] = \<const0> ;
  assign LOCKSTEP_Out[3353] = \<const0> ;
  assign LOCKSTEP_Out[3354] = \<const0> ;
  assign LOCKSTEP_Out[3355] = \<const0> ;
  assign LOCKSTEP_Out[3356] = \<const0> ;
  assign LOCKSTEP_Out[3357] = \<const0> ;
  assign LOCKSTEP_Out[3358] = \<const0> ;
  assign LOCKSTEP_Out[3359] = \<const0> ;
  assign LOCKSTEP_Out[3360] = \<const0> ;
  assign LOCKSTEP_Out[3361] = \<const0> ;
  assign LOCKSTEP_Out[3362] = \<const0> ;
  assign LOCKSTEP_Out[3363] = \<const0> ;
  assign LOCKSTEP_Out[3364] = \<const0> ;
  assign LOCKSTEP_Out[3365] = \<const0> ;
  assign LOCKSTEP_Out[3366] = \<const0> ;
  assign LOCKSTEP_Out[3367] = \<const0> ;
  assign LOCKSTEP_Out[3368] = \<const0> ;
  assign LOCKSTEP_Out[3369] = \<const0> ;
  assign LOCKSTEP_Out[3370] = \<const0> ;
  assign LOCKSTEP_Out[3371] = \<const0> ;
  assign LOCKSTEP_Out[3372] = \<const0> ;
  assign LOCKSTEP_Out[3373] = \<const0> ;
  assign LOCKSTEP_Out[3374] = \<const0> ;
  assign LOCKSTEP_Out[3375] = \<const0> ;
  assign LOCKSTEP_Out[3376] = \<const0> ;
  assign LOCKSTEP_Out[3377] = \<const0> ;
  assign LOCKSTEP_Out[3378] = \<const0> ;
  assign LOCKSTEP_Out[3379] = \<const0> ;
  assign LOCKSTEP_Out[3380] = \<const0> ;
  assign LOCKSTEP_Out[3381] = \<const0> ;
  assign LOCKSTEP_Out[3382] = \<const0> ;
  assign LOCKSTEP_Out[3383] = \<const0> ;
  assign LOCKSTEP_Out[3384] = \<const0> ;
  assign LOCKSTEP_Out[3385] = \<const0> ;
  assign LOCKSTEP_Out[3386] = \<const0> ;
  assign LOCKSTEP_Out[3387] = \<const0> ;
  assign LOCKSTEP_Out[3388] = \<const0> ;
  assign LOCKSTEP_Out[3389] = \<const0> ;
  assign LOCKSTEP_Out[3390] = \<const0> ;
  assign LOCKSTEP_Out[3391] = \<const0> ;
  assign LOCKSTEP_Out[3392] = \<const0> ;
  assign LOCKSTEP_Out[3393] = \<const0> ;
  assign LOCKSTEP_Out[3394] = \<const0> ;
  assign LOCKSTEP_Out[3395] = \<const0> ;
  assign LOCKSTEP_Out[3396] = \<const0> ;
  assign LOCKSTEP_Out[3397] = \<const0> ;
  assign LOCKSTEP_Out[3398] = \<const0> ;
  assign LOCKSTEP_Out[3399] = \<const0> ;
  assign LOCKSTEP_Out[3400] = \<const0> ;
  assign LOCKSTEP_Out[3401] = \<const0> ;
  assign LOCKSTEP_Out[3402] = \<const0> ;
  assign LOCKSTEP_Out[3403] = \<const0> ;
  assign LOCKSTEP_Out[3404] = \<const0> ;
  assign LOCKSTEP_Out[3405] = \<const0> ;
  assign LOCKSTEP_Out[3406] = \<const0> ;
  assign LOCKSTEP_Out[3407] = \<const0> ;
  assign LOCKSTEP_Out[3408] = \<const0> ;
  assign LOCKSTEP_Out[3409] = \<const0> ;
  assign LOCKSTEP_Out[3410] = \<const0> ;
  assign LOCKSTEP_Out[3411] = \<const0> ;
  assign LOCKSTEP_Out[3412] = \<const0> ;
  assign LOCKSTEP_Out[3413] = \<const0> ;
  assign LOCKSTEP_Out[3414] = \<const0> ;
  assign LOCKSTEP_Out[3415] = \<const0> ;
  assign LOCKSTEP_Out[3416] = \<const0> ;
  assign LOCKSTEP_Out[3417] = \<const0> ;
  assign LOCKSTEP_Out[3418] = \<const0> ;
  assign LOCKSTEP_Out[3419] = \<const0> ;
  assign LOCKSTEP_Out[3420] = \<const0> ;
  assign LOCKSTEP_Out[3421] = \<const0> ;
  assign LOCKSTEP_Out[3422] = \<const0> ;
  assign LOCKSTEP_Out[3423] = \<const0> ;
  assign LOCKSTEP_Out[3424] = \<const0> ;
  assign LOCKSTEP_Out[3425] = \<const0> ;
  assign LOCKSTEP_Out[3426] = \<const0> ;
  assign LOCKSTEP_Out[3427] = \<const0> ;
  assign LOCKSTEP_Out[3428] = \<const0> ;
  assign LOCKSTEP_Out[3429] = \<const0> ;
  assign LOCKSTEP_Out[3430] = \<const0> ;
  assign LOCKSTEP_Out[3431] = \<const0> ;
  assign LOCKSTEP_Out[3432] = \<const0> ;
  assign LOCKSTEP_Out[3433] = \<const0> ;
  assign LOCKSTEP_Out[3434] = \<const0> ;
  assign LOCKSTEP_Out[3435] = \<const0> ;
  assign LOCKSTEP_Out[3436] = \<const0> ;
  assign LOCKSTEP_Out[3437] = \<const0> ;
  assign LOCKSTEP_Out[3438] = \<const0> ;
  assign LOCKSTEP_Out[3439] = \<const0> ;
  assign LOCKSTEP_Out[3440] = \<const0> ;
  assign LOCKSTEP_Out[3441] = \<const0> ;
  assign LOCKSTEP_Out[3442] = \<const0> ;
  assign LOCKSTEP_Out[3443] = \<const0> ;
  assign LOCKSTEP_Out[3444] = \<const0> ;
  assign LOCKSTEP_Out[3445] = \<const0> ;
  assign LOCKSTEP_Out[3446] = \<const0> ;
  assign LOCKSTEP_Out[3447] = \<const0> ;
  assign LOCKSTEP_Out[3448] = \<const0> ;
  assign LOCKSTEP_Out[3449] = \<const0> ;
  assign LOCKSTEP_Out[3450] = \<const0> ;
  assign LOCKSTEP_Out[3451] = \<const0> ;
  assign LOCKSTEP_Out[3452] = \<const0> ;
  assign LOCKSTEP_Out[3453] = \<const0> ;
  assign LOCKSTEP_Out[3454] = \<const0> ;
  assign LOCKSTEP_Out[3455] = \<const0> ;
  assign LOCKSTEP_Out[3456] = \<const0> ;
  assign LOCKSTEP_Out[3457] = \<const0> ;
  assign LOCKSTEP_Out[3458] = \<const0> ;
  assign LOCKSTEP_Out[3459] = \<const0> ;
  assign LOCKSTEP_Out[3460] = \<const0> ;
  assign LOCKSTEP_Out[3461] = \<const0> ;
  assign LOCKSTEP_Out[3462] = \<const0> ;
  assign LOCKSTEP_Out[3463] = \<const0> ;
  assign LOCKSTEP_Out[3464] = \<const0> ;
  assign LOCKSTEP_Out[3465] = \<const0> ;
  assign LOCKSTEP_Out[3466] = \<const0> ;
  assign LOCKSTEP_Out[3467] = \<const0> ;
  assign LOCKSTEP_Out[3468] = \<const0> ;
  assign LOCKSTEP_Out[3469] = \<const0> ;
  assign LOCKSTEP_Out[3470] = \<const0> ;
  assign LOCKSTEP_Out[3471] = \<const0> ;
  assign LOCKSTEP_Out[3472] = \<const0> ;
  assign LOCKSTEP_Out[3473] = \<const0> ;
  assign LOCKSTEP_Out[3474] = \<const0> ;
  assign LOCKSTEP_Out[3475] = \<const0> ;
  assign LOCKSTEP_Out[3476] = \<const0> ;
  assign LOCKSTEP_Out[3477] = \<const0> ;
  assign LOCKSTEP_Out[3478] = \<const0> ;
  assign LOCKSTEP_Out[3479] = \<const0> ;
  assign LOCKSTEP_Out[3480] = \<const0> ;
  assign LOCKSTEP_Out[3481] = \<const0> ;
  assign LOCKSTEP_Out[3482] = \<const0> ;
  assign LOCKSTEP_Out[3483] = \<const0> ;
  assign LOCKSTEP_Out[3484] = \<const0> ;
  assign LOCKSTEP_Out[3485] = \<const0> ;
  assign LOCKSTEP_Out[3486] = \<const0> ;
  assign LOCKSTEP_Out[3487] = \<const0> ;
  assign LOCKSTEP_Out[3488] = \<const0> ;
  assign LOCKSTEP_Out[3489] = \<const0> ;
  assign LOCKSTEP_Out[3490] = \<const0> ;
  assign LOCKSTEP_Out[3491] = \<const0> ;
  assign LOCKSTEP_Out[3492] = \<const0> ;
  assign LOCKSTEP_Out[3493] = \<const0> ;
  assign LOCKSTEP_Out[3494] = \<const0> ;
  assign LOCKSTEP_Out[3495] = \<const0> ;
  assign LOCKSTEP_Out[3496] = \<const0> ;
  assign LOCKSTEP_Out[3497] = \<const0> ;
  assign LOCKSTEP_Out[3498] = \<const0> ;
  assign LOCKSTEP_Out[3499] = \<const0> ;
  assign LOCKSTEP_Out[3500] = \<const0> ;
  assign LOCKSTEP_Out[3501] = \<const0> ;
  assign LOCKSTEP_Out[3502] = \<const0> ;
  assign LOCKSTEP_Out[3503] = \<const0> ;
  assign LOCKSTEP_Out[3504] = \<const0> ;
  assign LOCKSTEP_Out[3505] = \<const0> ;
  assign LOCKSTEP_Out[3506] = \<const0> ;
  assign LOCKSTEP_Out[3507] = \<const0> ;
  assign LOCKSTEP_Out[3508] = \<const0> ;
  assign LOCKSTEP_Out[3509] = \<const0> ;
  assign LOCKSTEP_Out[3510] = \<const0> ;
  assign LOCKSTEP_Out[3511] = \<const0> ;
  assign LOCKSTEP_Out[3512] = \<const0> ;
  assign LOCKSTEP_Out[3513] = \<const0> ;
  assign LOCKSTEP_Out[3514] = \<const0> ;
  assign LOCKSTEP_Out[3515] = \<const0> ;
  assign LOCKSTEP_Out[3516] = \<const0> ;
  assign LOCKSTEP_Out[3517] = \<const0> ;
  assign LOCKSTEP_Out[3518] = \<const0> ;
  assign LOCKSTEP_Out[3519] = \<const0> ;
  assign LOCKSTEP_Out[3520] = \<const0> ;
  assign LOCKSTEP_Out[3521] = \<const0> ;
  assign LOCKSTEP_Out[3522] = \<const0> ;
  assign LOCKSTEP_Out[3523] = \<const0> ;
  assign LOCKSTEP_Out[3524] = \<const0> ;
  assign LOCKSTEP_Out[3525] = \<const0> ;
  assign LOCKSTEP_Out[3526] = \<const0> ;
  assign LOCKSTEP_Out[3527] = \<const0> ;
  assign LOCKSTEP_Out[3528] = \<const0> ;
  assign LOCKSTEP_Out[3529] = \<const0> ;
  assign LOCKSTEP_Out[3530] = \<const0> ;
  assign LOCKSTEP_Out[3531] = \<const0> ;
  assign LOCKSTEP_Out[3532] = \<const0> ;
  assign LOCKSTEP_Out[3533] = \<const0> ;
  assign LOCKSTEP_Out[3534] = \<const0> ;
  assign LOCKSTEP_Out[3535] = \<const0> ;
  assign LOCKSTEP_Out[3536] = \<const0> ;
  assign LOCKSTEP_Out[3537] = \<const0> ;
  assign LOCKSTEP_Out[3538] = \<const0> ;
  assign LOCKSTEP_Out[3539] = \<const0> ;
  assign LOCKSTEP_Out[3540] = \<const0> ;
  assign LOCKSTEP_Out[3541] = \<const0> ;
  assign LOCKSTEP_Out[3542] = \<const0> ;
  assign LOCKSTEP_Out[3543] = \<const0> ;
  assign LOCKSTEP_Out[3544] = \<const0> ;
  assign LOCKSTEP_Out[3545] = \<const0> ;
  assign LOCKSTEP_Out[3546] = \<const0> ;
  assign LOCKSTEP_Out[3547] = \<const0> ;
  assign LOCKSTEP_Out[3548] = \<const0> ;
  assign LOCKSTEP_Out[3549] = \<const0> ;
  assign LOCKSTEP_Out[3550] = \<const0> ;
  assign LOCKSTEP_Out[3551] = \<const0> ;
  assign LOCKSTEP_Out[3552] = \<const0> ;
  assign LOCKSTEP_Out[3553] = \<const0> ;
  assign LOCKSTEP_Out[3554] = \<const0> ;
  assign LOCKSTEP_Out[3555] = \<const0> ;
  assign LOCKSTEP_Out[3556] = \<const0> ;
  assign LOCKSTEP_Out[3557] = \<const0> ;
  assign LOCKSTEP_Out[3558] = \<const0> ;
  assign LOCKSTEP_Out[3559] = \<const0> ;
  assign LOCKSTEP_Out[3560] = \<const0> ;
  assign LOCKSTEP_Out[3561] = \<const0> ;
  assign LOCKSTEP_Out[3562] = \<const0> ;
  assign LOCKSTEP_Out[3563] = \<const0> ;
  assign LOCKSTEP_Out[3564] = \<const0> ;
  assign LOCKSTEP_Out[3565] = \<const0> ;
  assign LOCKSTEP_Out[3566] = \<const0> ;
  assign LOCKSTEP_Out[3567] = \<const0> ;
  assign LOCKSTEP_Out[3568] = \<const0> ;
  assign LOCKSTEP_Out[3569] = \<const0> ;
  assign LOCKSTEP_Out[3570] = \<const0> ;
  assign LOCKSTEP_Out[3571] = \<const0> ;
  assign LOCKSTEP_Out[3572] = \<const0> ;
  assign LOCKSTEP_Out[3573] = \<const0> ;
  assign LOCKSTEP_Out[3574] = \<const0> ;
  assign LOCKSTEP_Out[3575] = \<const0> ;
  assign LOCKSTEP_Out[3576] = \<const0> ;
  assign LOCKSTEP_Out[3577] = \<const0> ;
  assign LOCKSTEP_Out[3578] = \<const0> ;
  assign LOCKSTEP_Out[3579] = \<const0> ;
  assign LOCKSTEP_Out[3580] = \<const0> ;
  assign LOCKSTEP_Out[3581] = \<const0> ;
  assign LOCKSTEP_Out[3582] = \<const0> ;
  assign LOCKSTEP_Out[3583] = \<const0> ;
  assign LOCKSTEP_Out[3584] = \<const0> ;
  assign LOCKSTEP_Out[3585] = \<const0> ;
  assign LOCKSTEP_Out[3586] = \<const0> ;
  assign LOCKSTEP_Out[3587] = \<const0> ;
  assign LOCKSTEP_Out[3588] = \<const0> ;
  assign LOCKSTEP_Out[3589] = \<const0> ;
  assign LOCKSTEP_Out[3590] = \<const0> ;
  assign LOCKSTEP_Out[3591] = \<const0> ;
  assign LOCKSTEP_Out[3592] = \<const0> ;
  assign LOCKSTEP_Out[3593] = \<const0> ;
  assign LOCKSTEP_Out[3594] = \<const0> ;
  assign LOCKSTEP_Out[3595] = \<const0> ;
  assign LOCKSTEP_Out[3596] = \<const0> ;
  assign LOCKSTEP_Out[3597] = \<const0> ;
  assign LOCKSTEP_Out[3598] = \<const0> ;
  assign LOCKSTEP_Out[3599] = \<const0> ;
  assign LOCKSTEP_Out[3600] = \<const0> ;
  assign LOCKSTEP_Out[3601] = \<const0> ;
  assign LOCKSTEP_Out[3602] = \<const0> ;
  assign LOCKSTEP_Out[3603] = \<const0> ;
  assign LOCKSTEP_Out[3604] = \<const0> ;
  assign LOCKSTEP_Out[3605] = \<const0> ;
  assign LOCKSTEP_Out[3606] = \<const0> ;
  assign LOCKSTEP_Out[3607] = \<const0> ;
  assign LOCKSTEP_Out[3608] = \<const0> ;
  assign LOCKSTEP_Out[3609] = \<const0> ;
  assign LOCKSTEP_Out[3610] = \<const0> ;
  assign LOCKSTEP_Out[3611] = \<const0> ;
  assign LOCKSTEP_Out[3612] = \<const0> ;
  assign LOCKSTEP_Out[3613] = \<const0> ;
  assign LOCKSTEP_Out[3614] = \<const0> ;
  assign LOCKSTEP_Out[3615] = \<const0> ;
  assign LOCKSTEP_Out[3616] = \<const0> ;
  assign LOCKSTEP_Out[3617] = \<const0> ;
  assign LOCKSTEP_Out[3618] = \<const0> ;
  assign LOCKSTEP_Out[3619] = \<const0> ;
  assign LOCKSTEP_Out[3620] = \<const0> ;
  assign LOCKSTEP_Out[3621] = \<const0> ;
  assign LOCKSTEP_Out[3622] = \<const0> ;
  assign LOCKSTEP_Out[3623] = \<const0> ;
  assign LOCKSTEP_Out[3624] = \<const0> ;
  assign LOCKSTEP_Out[3625] = \<const0> ;
  assign LOCKSTEP_Out[3626] = \<const0> ;
  assign LOCKSTEP_Out[3627] = \<const0> ;
  assign LOCKSTEP_Out[3628] = \<const0> ;
  assign LOCKSTEP_Out[3629] = \<const0> ;
  assign LOCKSTEP_Out[3630] = \<const0> ;
  assign LOCKSTEP_Out[3631] = \<const0> ;
  assign LOCKSTEP_Out[3632] = \<const0> ;
  assign LOCKSTEP_Out[3633] = \<const0> ;
  assign LOCKSTEP_Out[3634] = \<const0> ;
  assign LOCKSTEP_Out[3635] = \<const0> ;
  assign LOCKSTEP_Out[3636] = \<const0> ;
  assign LOCKSTEP_Out[3637] = \<const0> ;
  assign LOCKSTEP_Out[3638] = \<const0> ;
  assign LOCKSTEP_Out[3639] = \<const0> ;
  assign LOCKSTEP_Out[3640] = \<const0> ;
  assign LOCKSTEP_Out[3641] = \<const0> ;
  assign LOCKSTEP_Out[3642] = \<const0> ;
  assign LOCKSTEP_Out[3643] = \<const0> ;
  assign LOCKSTEP_Out[3644] = \<const0> ;
  assign LOCKSTEP_Out[3645] = \<const0> ;
  assign LOCKSTEP_Out[3646] = \<const0> ;
  assign LOCKSTEP_Out[3647] = \<const0> ;
  assign LOCKSTEP_Out[3648] = \<const0> ;
  assign LOCKSTEP_Out[3649] = \<const0> ;
  assign LOCKSTEP_Out[3650] = \<const0> ;
  assign LOCKSTEP_Out[3651] = \<const0> ;
  assign LOCKSTEP_Out[3652] = \<const0> ;
  assign LOCKSTEP_Out[3653] = \<const0> ;
  assign LOCKSTEP_Out[3654] = \<const0> ;
  assign LOCKSTEP_Out[3655] = \<const0> ;
  assign LOCKSTEP_Out[3656] = \<const0> ;
  assign LOCKSTEP_Out[3657] = \<const0> ;
  assign LOCKSTEP_Out[3658] = \<const0> ;
  assign LOCKSTEP_Out[3659] = \<const0> ;
  assign LOCKSTEP_Out[3660] = \<const0> ;
  assign LOCKSTEP_Out[3661] = \<const0> ;
  assign LOCKSTEP_Out[3662] = \<const0> ;
  assign LOCKSTEP_Out[3663] = \<const0> ;
  assign LOCKSTEP_Out[3664] = \<const0> ;
  assign LOCKSTEP_Out[3665] = \<const0> ;
  assign LOCKSTEP_Out[3666] = \<const0> ;
  assign LOCKSTEP_Out[3667] = \<const0> ;
  assign LOCKSTEP_Out[3668] = \<const0> ;
  assign LOCKSTEP_Out[3669] = \<const0> ;
  assign LOCKSTEP_Out[3670] = \<const0> ;
  assign LOCKSTEP_Out[3671] = \<const0> ;
  assign LOCKSTEP_Out[3672] = \<const0> ;
  assign LOCKSTEP_Out[3673] = \<const0> ;
  assign LOCKSTEP_Out[3674] = \<const0> ;
  assign LOCKSTEP_Out[3675] = \<const0> ;
  assign LOCKSTEP_Out[3676] = \<const0> ;
  assign LOCKSTEP_Out[3677] = \<const0> ;
  assign LOCKSTEP_Out[3678] = \<const0> ;
  assign LOCKSTEP_Out[3679] = \<const0> ;
  assign LOCKSTEP_Out[3680] = \<const0> ;
  assign LOCKSTEP_Out[3681] = \<const0> ;
  assign LOCKSTEP_Out[3682] = \<const0> ;
  assign LOCKSTEP_Out[3683] = \<const0> ;
  assign LOCKSTEP_Out[3684] = \<const0> ;
  assign LOCKSTEP_Out[3685] = \<const0> ;
  assign LOCKSTEP_Out[3686] = \<const0> ;
  assign LOCKSTEP_Out[3687] = \<const0> ;
  assign LOCKSTEP_Out[3688] = \<const0> ;
  assign LOCKSTEP_Out[3689] = \<const0> ;
  assign LOCKSTEP_Out[3690] = \<const0> ;
  assign LOCKSTEP_Out[3691] = \<const0> ;
  assign LOCKSTEP_Out[3692] = \<const0> ;
  assign LOCKSTEP_Out[3693] = \<const0> ;
  assign LOCKSTEP_Out[3694] = \<const0> ;
  assign LOCKSTEP_Out[3695] = \<const0> ;
  assign LOCKSTEP_Out[3696] = \<const0> ;
  assign LOCKSTEP_Out[3697] = \<const0> ;
  assign LOCKSTEP_Out[3698] = \<const0> ;
  assign LOCKSTEP_Out[3699] = \<const0> ;
  assign LOCKSTEP_Out[3700] = \<const0> ;
  assign LOCKSTEP_Out[3701] = \<const0> ;
  assign LOCKSTEP_Out[3702] = \<const0> ;
  assign LOCKSTEP_Out[3703] = \<const0> ;
  assign LOCKSTEP_Out[3704] = \<const0> ;
  assign LOCKSTEP_Out[3705] = \<const0> ;
  assign LOCKSTEP_Out[3706] = \<const0> ;
  assign LOCKSTEP_Out[3707] = \<const0> ;
  assign LOCKSTEP_Out[3708] = \<const0> ;
  assign LOCKSTEP_Out[3709] = \<const0> ;
  assign LOCKSTEP_Out[3710] = \<const0> ;
  assign LOCKSTEP_Out[3711] = \<const0> ;
  assign LOCKSTEP_Out[3712] = \<const0> ;
  assign LOCKSTEP_Out[3713] = \<const0> ;
  assign LOCKSTEP_Out[3714] = \<const0> ;
  assign LOCKSTEP_Out[3715] = \<const0> ;
  assign LOCKSTEP_Out[3716] = \<const0> ;
  assign LOCKSTEP_Out[3717] = \<const0> ;
  assign LOCKSTEP_Out[3718] = \<const0> ;
  assign LOCKSTEP_Out[3719] = \<const0> ;
  assign LOCKSTEP_Out[3720] = \<const0> ;
  assign LOCKSTEP_Out[3721] = \<const0> ;
  assign LOCKSTEP_Out[3722] = \<const0> ;
  assign LOCKSTEP_Out[3723] = \<const0> ;
  assign LOCKSTEP_Out[3724] = \<const0> ;
  assign LOCKSTEP_Out[3725] = \<const0> ;
  assign LOCKSTEP_Out[3726] = \<const0> ;
  assign LOCKSTEP_Out[3727] = \<const0> ;
  assign LOCKSTEP_Out[3728] = \<const0> ;
  assign LOCKSTEP_Out[3729] = \<const0> ;
  assign LOCKSTEP_Out[3730] = \<const0> ;
  assign LOCKSTEP_Out[3731] = \<const0> ;
  assign LOCKSTEP_Out[3732] = \<const0> ;
  assign LOCKSTEP_Out[3733] = \<const0> ;
  assign LOCKSTEP_Out[3734] = \<const0> ;
  assign LOCKSTEP_Out[3735] = \<const0> ;
  assign LOCKSTEP_Out[3736] = \<const0> ;
  assign LOCKSTEP_Out[3737] = \<const0> ;
  assign LOCKSTEP_Out[3738] = \<const0> ;
  assign LOCKSTEP_Out[3739] = \<const0> ;
  assign LOCKSTEP_Out[3740] = \<const0> ;
  assign LOCKSTEP_Out[3741] = \<const0> ;
  assign LOCKSTEP_Out[3742] = \<const0> ;
  assign LOCKSTEP_Out[3743] = \<const0> ;
  assign LOCKSTEP_Out[3744] = \<const0> ;
  assign LOCKSTEP_Out[3745] = \<const0> ;
  assign LOCKSTEP_Out[3746] = \<const0> ;
  assign LOCKSTEP_Out[3747] = \<const0> ;
  assign LOCKSTEP_Out[3748] = \<const0> ;
  assign LOCKSTEP_Out[3749] = \<const0> ;
  assign LOCKSTEP_Out[3750] = \<const0> ;
  assign LOCKSTEP_Out[3751] = \<const0> ;
  assign LOCKSTEP_Out[3752] = \<const0> ;
  assign LOCKSTEP_Out[3753] = \<const0> ;
  assign LOCKSTEP_Out[3754] = \<const0> ;
  assign LOCKSTEP_Out[3755] = \<const0> ;
  assign LOCKSTEP_Out[3756] = \<const0> ;
  assign LOCKSTEP_Out[3757] = \<const0> ;
  assign LOCKSTEP_Out[3758] = \<const0> ;
  assign LOCKSTEP_Out[3759] = \<const0> ;
  assign LOCKSTEP_Out[3760] = \<const0> ;
  assign LOCKSTEP_Out[3761] = \<const0> ;
  assign LOCKSTEP_Out[3762] = \<const0> ;
  assign LOCKSTEP_Out[3763] = \<const0> ;
  assign LOCKSTEP_Out[3764] = \<const0> ;
  assign LOCKSTEP_Out[3765] = \<const0> ;
  assign LOCKSTEP_Out[3766] = \<const0> ;
  assign LOCKSTEP_Out[3767] = \<const0> ;
  assign LOCKSTEP_Out[3768] = \<const0> ;
  assign LOCKSTEP_Out[3769] = \<const0> ;
  assign LOCKSTEP_Out[3770] = \<const0> ;
  assign LOCKSTEP_Out[3771] = \<const0> ;
  assign LOCKSTEP_Out[3772] = \<const0> ;
  assign LOCKSTEP_Out[3773] = \<const0> ;
  assign LOCKSTEP_Out[3774] = \<const0> ;
  assign LOCKSTEP_Out[3775] = \<const0> ;
  assign LOCKSTEP_Out[3776] = \<const0> ;
  assign LOCKSTEP_Out[3777] = \<const0> ;
  assign LOCKSTEP_Out[3778] = \<const0> ;
  assign LOCKSTEP_Out[3779] = \<const0> ;
  assign LOCKSTEP_Out[3780] = \<const0> ;
  assign LOCKSTEP_Out[3781] = \<const0> ;
  assign LOCKSTEP_Out[3782] = \<const0> ;
  assign LOCKSTEP_Out[3783] = \<const0> ;
  assign LOCKSTEP_Out[3784] = \<const0> ;
  assign LOCKSTEP_Out[3785] = \<const0> ;
  assign LOCKSTEP_Out[3786] = \<const0> ;
  assign LOCKSTEP_Out[3787] = \<const0> ;
  assign LOCKSTEP_Out[3788] = \<const0> ;
  assign LOCKSTEP_Out[3789] = \<const0> ;
  assign LOCKSTEP_Out[3790] = \<const0> ;
  assign LOCKSTEP_Out[3791] = \<const0> ;
  assign LOCKSTEP_Out[3792] = \<const0> ;
  assign LOCKSTEP_Out[3793] = \<const0> ;
  assign LOCKSTEP_Out[3794] = \<const0> ;
  assign LOCKSTEP_Out[3795] = \<const0> ;
  assign LOCKSTEP_Out[3796] = \<const0> ;
  assign LOCKSTEP_Out[3797] = \<const0> ;
  assign LOCKSTEP_Out[3798] = \<const0> ;
  assign LOCKSTEP_Out[3799] = \<const0> ;
  assign LOCKSTEP_Out[3800] = \<const0> ;
  assign LOCKSTEP_Out[3801] = \<const0> ;
  assign LOCKSTEP_Out[3802] = \<const0> ;
  assign LOCKSTEP_Out[3803] = \<const0> ;
  assign LOCKSTEP_Out[3804] = \<const0> ;
  assign LOCKSTEP_Out[3805] = \<const0> ;
  assign LOCKSTEP_Out[3806] = \<const0> ;
  assign LOCKSTEP_Out[3807] = \<const0> ;
  assign LOCKSTEP_Out[3808] = \<const0> ;
  assign LOCKSTEP_Out[3809] = \<const0> ;
  assign LOCKSTEP_Out[3810] = \<const0> ;
  assign LOCKSTEP_Out[3811] = \<const0> ;
  assign LOCKSTEP_Out[3812] = \<const0> ;
  assign LOCKSTEP_Out[3813] = \<const0> ;
  assign LOCKSTEP_Out[3814] = \<const0> ;
  assign LOCKSTEP_Out[3815] = \<const0> ;
  assign LOCKSTEP_Out[3816] = \<const0> ;
  assign LOCKSTEP_Out[3817] = \<const0> ;
  assign LOCKSTEP_Out[3818] = \<const0> ;
  assign LOCKSTEP_Out[3819] = \<const0> ;
  assign LOCKSTEP_Out[3820] = \<const0> ;
  assign LOCKSTEP_Out[3821] = \<const0> ;
  assign LOCKSTEP_Out[3822] = \<const0> ;
  assign LOCKSTEP_Out[3823] = \<const0> ;
  assign LOCKSTEP_Out[3824] = \<const0> ;
  assign LOCKSTEP_Out[3825] = \<const0> ;
  assign LOCKSTEP_Out[3826] = \<const0> ;
  assign LOCKSTEP_Out[3827] = \<const0> ;
  assign LOCKSTEP_Out[3828] = \<const0> ;
  assign LOCKSTEP_Out[3829] = \<const0> ;
  assign LOCKSTEP_Out[3830] = \<const0> ;
  assign LOCKSTEP_Out[3831] = \<const0> ;
  assign LOCKSTEP_Out[3832] = \<const0> ;
  assign LOCKSTEP_Out[3833] = \<const0> ;
  assign LOCKSTEP_Out[3834] = \<const0> ;
  assign LOCKSTEP_Out[3835] = \<const0> ;
  assign LOCKSTEP_Out[3836] = \<const0> ;
  assign LOCKSTEP_Out[3837] = \<const0> ;
  assign LOCKSTEP_Out[3838] = \<const0> ;
  assign LOCKSTEP_Out[3839] = \<const0> ;
  assign LOCKSTEP_Out[3840] = \<const0> ;
  assign LOCKSTEP_Out[3841] = \<const0> ;
  assign LOCKSTEP_Out[3842] = \<const0> ;
  assign LOCKSTEP_Out[3843] = \<const0> ;
  assign LOCKSTEP_Out[3844] = \<const0> ;
  assign LOCKSTEP_Out[3845] = \<const0> ;
  assign LOCKSTEP_Out[3846] = \<const0> ;
  assign LOCKSTEP_Out[3847] = \<const0> ;
  assign LOCKSTEP_Out[3848] = \<const0> ;
  assign LOCKSTEP_Out[3849] = \<const0> ;
  assign LOCKSTEP_Out[3850] = \<const0> ;
  assign LOCKSTEP_Out[3851] = \<const0> ;
  assign LOCKSTEP_Out[3852] = \<const0> ;
  assign LOCKSTEP_Out[3853] = \<const0> ;
  assign LOCKSTEP_Out[3854] = \<const0> ;
  assign LOCKSTEP_Out[3855] = \<const0> ;
  assign LOCKSTEP_Out[3856] = \<const0> ;
  assign LOCKSTEP_Out[3857] = \<const0> ;
  assign LOCKSTEP_Out[3858] = \<const0> ;
  assign LOCKSTEP_Out[3859] = \<const0> ;
  assign LOCKSTEP_Out[3860] = \<const0> ;
  assign LOCKSTEP_Out[3861] = \<const0> ;
  assign LOCKSTEP_Out[3862] = \<const0> ;
  assign LOCKSTEP_Out[3863] = \<const0> ;
  assign LOCKSTEP_Out[3864] = \<const0> ;
  assign LOCKSTEP_Out[3865] = \<const0> ;
  assign LOCKSTEP_Out[3866] = \<const0> ;
  assign LOCKSTEP_Out[3867] = \<const0> ;
  assign LOCKSTEP_Out[3868] = \<const0> ;
  assign LOCKSTEP_Out[3869] = \<const0> ;
  assign LOCKSTEP_Out[3870] = \<const0> ;
  assign LOCKSTEP_Out[3871] = \<const0> ;
  assign LOCKSTEP_Out[3872] = \<const0> ;
  assign LOCKSTEP_Out[3873] = \<const0> ;
  assign LOCKSTEP_Out[3874] = \<const0> ;
  assign LOCKSTEP_Out[3875] = \<const0> ;
  assign LOCKSTEP_Out[3876] = \<const0> ;
  assign LOCKSTEP_Out[3877] = \<const0> ;
  assign LOCKSTEP_Out[3878] = \<const0> ;
  assign LOCKSTEP_Out[3879] = \<const0> ;
  assign LOCKSTEP_Out[3880] = \<const0> ;
  assign LOCKSTEP_Out[3881] = \<const0> ;
  assign LOCKSTEP_Out[3882] = \<const0> ;
  assign LOCKSTEP_Out[3883] = \<const0> ;
  assign LOCKSTEP_Out[3884] = \<const0> ;
  assign LOCKSTEP_Out[3885] = \<const0> ;
  assign LOCKSTEP_Out[3886] = \<const0> ;
  assign LOCKSTEP_Out[3887] = \<const0> ;
  assign LOCKSTEP_Out[3888] = \<const0> ;
  assign LOCKSTEP_Out[3889] = \<const0> ;
  assign LOCKSTEP_Out[3890] = \<const0> ;
  assign LOCKSTEP_Out[3891] = \<const0> ;
  assign LOCKSTEP_Out[3892] = \<const0> ;
  assign LOCKSTEP_Out[3893] = \<const0> ;
  assign LOCKSTEP_Out[3894] = \<const0> ;
  assign LOCKSTEP_Out[3895] = \<const0> ;
  assign LOCKSTEP_Out[3896] = \<const0> ;
  assign LOCKSTEP_Out[3897] = \<const0> ;
  assign LOCKSTEP_Out[3898] = \<const0> ;
  assign LOCKSTEP_Out[3899] = \<const0> ;
  assign LOCKSTEP_Out[3900] = \<const0> ;
  assign LOCKSTEP_Out[3901] = \<const0> ;
  assign LOCKSTEP_Out[3902] = \<const0> ;
  assign LOCKSTEP_Out[3903] = \<const0> ;
  assign LOCKSTEP_Out[3904] = \<const0> ;
  assign LOCKSTEP_Out[3905] = \<const0> ;
  assign LOCKSTEP_Out[3906] = \<const0> ;
  assign LOCKSTEP_Out[3907] = \<const0> ;
  assign LOCKSTEP_Out[3908] = \<const0> ;
  assign LOCKSTEP_Out[3909] = \<const0> ;
  assign LOCKSTEP_Out[3910] = \<const0> ;
  assign LOCKSTEP_Out[3911] = \<const0> ;
  assign LOCKSTEP_Out[3912] = \<const0> ;
  assign LOCKSTEP_Out[3913] = \<const0> ;
  assign LOCKSTEP_Out[3914] = \<const0> ;
  assign LOCKSTEP_Out[3915] = \<const0> ;
  assign LOCKSTEP_Out[3916] = \<const0> ;
  assign LOCKSTEP_Out[3917] = \<const0> ;
  assign LOCKSTEP_Out[3918] = \<const0> ;
  assign LOCKSTEP_Out[3919] = \<const0> ;
  assign LOCKSTEP_Out[3920] = \<const0> ;
  assign LOCKSTEP_Out[3921] = \<const0> ;
  assign LOCKSTEP_Out[3922] = \<const0> ;
  assign LOCKSTEP_Out[3923] = \<const0> ;
  assign LOCKSTEP_Out[3924] = \<const0> ;
  assign LOCKSTEP_Out[3925] = \<const0> ;
  assign LOCKSTEP_Out[3926] = \<const0> ;
  assign LOCKSTEP_Out[3927] = \<const0> ;
  assign LOCKSTEP_Out[3928] = \<const0> ;
  assign LOCKSTEP_Out[3929] = \<const0> ;
  assign LOCKSTEP_Out[3930] = \<const0> ;
  assign LOCKSTEP_Out[3931] = \<const0> ;
  assign LOCKSTEP_Out[3932] = \<const0> ;
  assign LOCKSTEP_Out[3933] = \<const0> ;
  assign LOCKSTEP_Out[3934] = \<const0> ;
  assign LOCKSTEP_Out[3935] = \<const0> ;
  assign LOCKSTEP_Out[3936] = \<const0> ;
  assign LOCKSTEP_Out[3937] = \<const0> ;
  assign LOCKSTEP_Out[3938] = \<const0> ;
  assign LOCKSTEP_Out[3939] = \<const0> ;
  assign LOCKSTEP_Out[3940] = \<const0> ;
  assign LOCKSTEP_Out[3941] = \<const0> ;
  assign LOCKSTEP_Out[3942] = \<const0> ;
  assign LOCKSTEP_Out[3943] = \<const0> ;
  assign LOCKSTEP_Out[3944] = \<const0> ;
  assign LOCKSTEP_Out[3945] = \<const0> ;
  assign LOCKSTEP_Out[3946] = \<const0> ;
  assign LOCKSTEP_Out[3947] = \<const0> ;
  assign LOCKSTEP_Out[3948] = \<const0> ;
  assign LOCKSTEP_Out[3949] = \<const0> ;
  assign LOCKSTEP_Out[3950] = \<const0> ;
  assign LOCKSTEP_Out[3951] = \<const0> ;
  assign LOCKSTEP_Out[3952] = \<const0> ;
  assign LOCKSTEP_Out[3953] = \<const0> ;
  assign LOCKSTEP_Out[3954] = \<const0> ;
  assign LOCKSTEP_Out[3955] = \<const0> ;
  assign LOCKSTEP_Out[3956] = \<const0> ;
  assign LOCKSTEP_Out[3957] = \<const0> ;
  assign LOCKSTEP_Out[3958] = \<const0> ;
  assign LOCKSTEP_Out[3959] = \<const0> ;
  assign LOCKSTEP_Out[3960] = \<const0> ;
  assign LOCKSTEP_Out[3961] = \<const0> ;
  assign LOCKSTEP_Out[3962] = \<const0> ;
  assign LOCKSTEP_Out[3963] = \<const0> ;
  assign LOCKSTEP_Out[3964] = \<const0> ;
  assign LOCKSTEP_Out[3965] = \<const0> ;
  assign LOCKSTEP_Out[3966] = \<const0> ;
  assign LOCKSTEP_Out[3967] = \<const0> ;
  assign LOCKSTEP_Out[3968] = \<const0> ;
  assign LOCKSTEP_Out[3969] = \<const0> ;
  assign LOCKSTEP_Out[3970] = \<const0> ;
  assign LOCKSTEP_Out[3971] = \<const0> ;
  assign LOCKSTEP_Out[3972] = \<const0> ;
  assign LOCKSTEP_Out[3973] = \<const0> ;
  assign LOCKSTEP_Out[3974] = \<const0> ;
  assign LOCKSTEP_Out[3975] = \<const0> ;
  assign LOCKSTEP_Out[3976] = \<const0> ;
  assign LOCKSTEP_Out[3977] = \<const0> ;
  assign LOCKSTEP_Out[3978] = \<const0> ;
  assign LOCKSTEP_Out[3979] = \<const0> ;
  assign LOCKSTEP_Out[3980] = \<const0> ;
  assign LOCKSTEP_Out[3981] = \<const0> ;
  assign LOCKSTEP_Out[3982] = \<const0> ;
  assign LOCKSTEP_Out[3983] = \<const0> ;
  assign LOCKSTEP_Out[3984] = \<const0> ;
  assign LOCKSTEP_Out[3985] = \<const0> ;
  assign LOCKSTEP_Out[3986] = \<const0> ;
  assign LOCKSTEP_Out[3987] = \<const0> ;
  assign LOCKSTEP_Out[3988] = \<const0> ;
  assign LOCKSTEP_Out[3989] = \<const0> ;
  assign LOCKSTEP_Out[3990] = \<const0> ;
  assign LOCKSTEP_Out[3991] = \<const0> ;
  assign LOCKSTEP_Out[3992] = \<const0> ;
  assign LOCKSTEP_Out[3993] = \<const0> ;
  assign LOCKSTEP_Out[3994] = \<const0> ;
  assign LOCKSTEP_Out[3995] = \<const0> ;
  assign LOCKSTEP_Out[3996] = \<const0> ;
  assign LOCKSTEP_Out[3997] = \<const0> ;
  assign LOCKSTEP_Out[3998] = \<const0> ;
  assign LOCKSTEP_Out[3999] = \<const0> ;
  assign LOCKSTEP_Out[4000] = \<const0> ;
  assign LOCKSTEP_Out[4001] = \<const0> ;
  assign LOCKSTEP_Out[4002] = \<const0> ;
  assign LOCKSTEP_Out[4003] = \<const0> ;
  assign LOCKSTEP_Out[4004] = \<const0> ;
  assign LOCKSTEP_Out[4005] = \<const0> ;
  assign LOCKSTEP_Out[4006] = \<const0> ;
  assign LOCKSTEP_Out[4007] = \<const0> ;
  assign LOCKSTEP_Out[4008] = \<const0> ;
  assign LOCKSTEP_Out[4009] = \<const0> ;
  assign LOCKSTEP_Out[4010] = \<const0> ;
  assign LOCKSTEP_Out[4011] = \<const0> ;
  assign LOCKSTEP_Out[4012] = \<const0> ;
  assign LOCKSTEP_Out[4013] = \<const0> ;
  assign LOCKSTEP_Out[4014] = \<const0> ;
  assign LOCKSTEP_Out[4015] = \<const0> ;
  assign LOCKSTEP_Out[4016] = \<const0> ;
  assign LOCKSTEP_Out[4017] = \<const0> ;
  assign LOCKSTEP_Out[4018] = \<const0> ;
  assign LOCKSTEP_Out[4019] = \<const0> ;
  assign LOCKSTEP_Out[4020] = \<const0> ;
  assign LOCKSTEP_Out[4021] = \<const0> ;
  assign LOCKSTEP_Out[4022] = \<const0> ;
  assign LOCKSTEP_Out[4023] = \<const0> ;
  assign LOCKSTEP_Out[4024] = \<const0> ;
  assign LOCKSTEP_Out[4025] = \<const0> ;
  assign LOCKSTEP_Out[4026] = \<const0> ;
  assign LOCKSTEP_Out[4027] = \<const0> ;
  assign LOCKSTEP_Out[4028] = \<const0> ;
  assign LOCKSTEP_Out[4029] = \<const0> ;
  assign LOCKSTEP_Out[4030] = \<const0> ;
  assign LOCKSTEP_Out[4031] = \<const0> ;
  assign LOCKSTEP_Out[4032] = \<const0> ;
  assign LOCKSTEP_Out[4033] = \<const0> ;
  assign LOCKSTEP_Out[4034] = \<const0> ;
  assign LOCKSTEP_Out[4035] = \<const0> ;
  assign LOCKSTEP_Out[4036] = \<const0> ;
  assign LOCKSTEP_Out[4037] = \<const0> ;
  assign LOCKSTEP_Out[4038] = \<const0> ;
  assign LOCKSTEP_Out[4039] = \<const0> ;
  assign LOCKSTEP_Out[4040] = \<const0> ;
  assign LOCKSTEP_Out[4041] = \<const0> ;
  assign LOCKSTEP_Out[4042] = \<const0> ;
  assign LOCKSTEP_Out[4043] = \<const0> ;
  assign LOCKSTEP_Out[4044] = \<const0> ;
  assign LOCKSTEP_Out[4045] = \<const0> ;
  assign LOCKSTEP_Out[4046] = \<const0> ;
  assign LOCKSTEP_Out[4047] = \<const0> ;
  assign LOCKSTEP_Out[4048] = \<const0> ;
  assign LOCKSTEP_Out[4049] = \<const0> ;
  assign LOCKSTEP_Out[4050] = \<const0> ;
  assign LOCKSTEP_Out[4051] = \<const0> ;
  assign LOCKSTEP_Out[4052] = \<const0> ;
  assign LOCKSTEP_Out[4053] = \<const0> ;
  assign LOCKSTEP_Out[4054] = \<const0> ;
  assign LOCKSTEP_Out[4055] = \<const0> ;
  assign LOCKSTEP_Out[4056] = \<const0> ;
  assign LOCKSTEP_Out[4057] = \<const0> ;
  assign LOCKSTEP_Out[4058] = \<const0> ;
  assign LOCKSTEP_Out[4059] = \<const0> ;
  assign LOCKSTEP_Out[4060] = \<const0> ;
  assign LOCKSTEP_Out[4061] = \<const0> ;
  assign LOCKSTEP_Out[4062] = \<const0> ;
  assign LOCKSTEP_Out[4063] = \<const0> ;
  assign LOCKSTEP_Out[4064] = \<const0> ;
  assign LOCKSTEP_Out[4065] = \<const0> ;
  assign LOCKSTEP_Out[4066] = \<const0> ;
  assign LOCKSTEP_Out[4067] = \<const0> ;
  assign LOCKSTEP_Out[4068] = \<const0> ;
  assign LOCKSTEP_Out[4069] = \<const0> ;
  assign LOCKSTEP_Out[4070] = \<const0> ;
  assign LOCKSTEP_Out[4071] = \<const0> ;
  assign LOCKSTEP_Out[4072] = \<const0> ;
  assign LOCKSTEP_Out[4073] = \<const0> ;
  assign LOCKSTEP_Out[4074] = \<const0> ;
  assign LOCKSTEP_Out[4075] = \<const0> ;
  assign LOCKSTEP_Out[4076] = \<const0> ;
  assign LOCKSTEP_Out[4077] = \<const0> ;
  assign LOCKSTEP_Out[4078] = \<const0> ;
  assign LOCKSTEP_Out[4079] = \<const0> ;
  assign LOCKSTEP_Out[4080] = \<const0> ;
  assign LOCKSTEP_Out[4081] = \<const0> ;
  assign LOCKSTEP_Out[4082] = \<const0> ;
  assign LOCKSTEP_Out[4083] = \<const0> ;
  assign LOCKSTEP_Out[4084] = \<const0> ;
  assign LOCKSTEP_Out[4085] = \<const0> ;
  assign LOCKSTEP_Out[4086] = \<const0> ;
  assign LOCKSTEP_Out[4087] = \<const0> ;
  assign LOCKSTEP_Out[4088] = \<const0> ;
  assign LOCKSTEP_Out[4089] = \<const0> ;
  assign LOCKSTEP_Out[4090] = \<const0> ;
  assign LOCKSTEP_Out[4091] = \<const0> ;
  assign LOCKSTEP_Out[4092] = \<const0> ;
  assign LOCKSTEP_Out[4093] = \<const0> ;
  assign LOCKSTEP_Out[4094] = \<const0> ;
  assign LOCKSTEP_Out[4095] = \<const0> ;
  assign M0_AXIS_TDATA[31] = \<const0> ;
  assign M0_AXIS_TDATA[30] = \<const0> ;
  assign M0_AXIS_TDATA[29] = \<const0> ;
  assign M0_AXIS_TDATA[28] = \<const0> ;
  assign M0_AXIS_TDATA[27] = \<const0> ;
  assign M0_AXIS_TDATA[26] = \<const0> ;
  assign M0_AXIS_TDATA[25] = \<const0> ;
  assign M0_AXIS_TDATA[24] = \<const0> ;
  assign M0_AXIS_TDATA[23] = \<const0> ;
  assign M0_AXIS_TDATA[22] = \<const0> ;
  assign M0_AXIS_TDATA[21] = \<const0> ;
  assign M0_AXIS_TDATA[20] = \<const0> ;
  assign M0_AXIS_TDATA[19] = \<const0> ;
  assign M0_AXIS_TDATA[18] = \<const0> ;
  assign M0_AXIS_TDATA[17] = \<const0> ;
  assign M0_AXIS_TDATA[16] = \<const0> ;
  assign M0_AXIS_TDATA[15] = \<const0> ;
  assign M0_AXIS_TDATA[14] = \<const0> ;
  assign M0_AXIS_TDATA[13] = \<const0> ;
  assign M0_AXIS_TDATA[12] = \<const0> ;
  assign M0_AXIS_TDATA[11] = \<const0> ;
  assign M0_AXIS_TDATA[10] = \<const0> ;
  assign M0_AXIS_TDATA[9] = \<const0> ;
  assign M0_AXIS_TDATA[8] = \<const0> ;
  assign M0_AXIS_TDATA[7] = \<const0> ;
  assign M0_AXIS_TDATA[6] = \<const0> ;
  assign M0_AXIS_TDATA[5] = \<const0> ;
  assign M0_AXIS_TDATA[4] = \<const0> ;
  assign M0_AXIS_TDATA[3] = \<const0> ;
  assign M0_AXIS_TDATA[2] = \<const0> ;
  assign M0_AXIS_TDATA[1] = \<const0> ;
  assign M0_AXIS_TDATA[0] = \<const0> ;
  assign M0_AXIS_TLAST = \<const0> ;
  assign M0_AXIS_TVALID = \<const0> ;
  assign M10_AXIS_TDATA[31] = \<const0> ;
  assign M10_AXIS_TDATA[30] = \<const0> ;
  assign M10_AXIS_TDATA[29] = \<const0> ;
  assign M10_AXIS_TDATA[28] = \<const0> ;
  assign M10_AXIS_TDATA[27] = \<const0> ;
  assign M10_AXIS_TDATA[26] = \<const0> ;
  assign M10_AXIS_TDATA[25] = \<const0> ;
  assign M10_AXIS_TDATA[24] = \<const0> ;
  assign M10_AXIS_TDATA[23] = \<const0> ;
  assign M10_AXIS_TDATA[22] = \<const0> ;
  assign M10_AXIS_TDATA[21] = \<const0> ;
  assign M10_AXIS_TDATA[20] = \<const0> ;
  assign M10_AXIS_TDATA[19] = \<const0> ;
  assign M10_AXIS_TDATA[18] = \<const0> ;
  assign M10_AXIS_TDATA[17] = \<const0> ;
  assign M10_AXIS_TDATA[16] = \<const0> ;
  assign M10_AXIS_TDATA[15] = \<const0> ;
  assign M10_AXIS_TDATA[14] = \<const0> ;
  assign M10_AXIS_TDATA[13] = \<const0> ;
  assign M10_AXIS_TDATA[12] = \<const0> ;
  assign M10_AXIS_TDATA[11] = \<const0> ;
  assign M10_AXIS_TDATA[10] = \<const0> ;
  assign M10_AXIS_TDATA[9] = \<const0> ;
  assign M10_AXIS_TDATA[8] = \<const0> ;
  assign M10_AXIS_TDATA[7] = \<const0> ;
  assign M10_AXIS_TDATA[6] = \<const0> ;
  assign M10_AXIS_TDATA[5] = \<const0> ;
  assign M10_AXIS_TDATA[4] = \<const0> ;
  assign M10_AXIS_TDATA[3] = \<const0> ;
  assign M10_AXIS_TDATA[2] = \<const0> ;
  assign M10_AXIS_TDATA[1] = \<const0> ;
  assign M10_AXIS_TDATA[0] = \<const0> ;
  assign M10_AXIS_TLAST = \<const0> ;
  assign M10_AXIS_TVALID = \<const0> ;
  assign M11_AXIS_TDATA[31] = \<const0> ;
  assign M11_AXIS_TDATA[30] = \<const0> ;
  assign M11_AXIS_TDATA[29] = \<const0> ;
  assign M11_AXIS_TDATA[28] = \<const0> ;
  assign M11_AXIS_TDATA[27] = \<const0> ;
  assign M11_AXIS_TDATA[26] = \<const0> ;
  assign M11_AXIS_TDATA[25] = \<const0> ;
  assign M11_AXIS_TDATA[24] = \<const0> ;
  assign M11_AXIS_TDATA[23] = \<const0> ;
  assign M11_AXIS_TDATA[22] = \<const0> ;
  assign M11_AXIS_TDATA[21] = \<const0> ;
  assign M11_AXIS_TDATA[20] = \<const0> ;
  assign M11_AXIS_TDATA[19] = \<const0> ;
  assign M11_AXIS_TDATA[18] = \<const0> ;
  assign M11_AXIS_TDATA[17] = \<const0> ;
  assign M11_AXIS_TDATA[16] = \<const0> ;
  assign M11_AXIS_TDATA[15] = \<const0> ;
  assign M11_AXIS_TDATA[14] = \<const0> ;
  assign M11_AXIS_TDATA[13] = \<const0> ;
  assign M11_AXIS_TDATA[12] = \<const0> ;
  assign M11_AXIS_TDATA[11] = \<const0> ;
  assign M11_AXIS_TDATA[10] = \<const0> ;
  assign M11_AXIS_TDATA[9] = \<const0> ;
  assign M11_AXIS_TDATA[8] = \<const0> ;
  assign M11_AXIS_TDATA[7] = \<const0> ;
  assign M11_AXIS_TDATA[6] = \<const0> ;
  assign M11_AXIS_TDATA[5] = \<const0> ;
  assign M11_AXIS_TDATA[4] = \<const0> ;
  assign M11_AXIS_TDATA[3] = \<const0> ;
  assign M11_AXIS_TDATA[2] = \<const0> ;
  assign M11_AXIS_TDATA[1] = \<const0> ;
  assign M11_AXIS_TDATA[0] = \<const0> ;
  assign M11_AXIS_TLAST = \<const0> ;
  assign M11_AXIS_TVALID = \<const0> ;
  assign M12_AXIS_TDATA[31] = \<const0> ;
  assign M12_AXIS_TDATA[30] = \<const0> ;
  assign M12_AXIS_TDATA[29] = \<const0> ;
  assign M12_AXIS_TDATA[28] = \<const0> ;
  assign M12_AXIS_TDATA[27] = \<const0> ;
  assign M12_AXIS_TDATA[26] = \<const0> ;
  assign M12_AXIS_TDATA[25] = \<const0> ;
  assign M12_AXIS_TDATA[24] = \<const0> ;
  assign M12_AXIS_TDATA[23] = \<const0> ;
  assign M12_AXIS_TDATA[22] = \<const0> ;
  assign M12_AXIS_TDATA[21] = \<const0> ;
  assign M12_AXIS_TDATA[20] = \<const0> ;
  assign M12_AXIS_TDATA[19] = \<const0> ;
  assign M12_AXIS_TDATA[18] = \<const0> ;
  assign M12_AXIS_TDATA[17] = \<const0> ;
  assign M12_AXIS_TDATA[16] = \<const0> ;
  assign M12_AXIS_TDATA[15] = \<const0> ;
  assign M12_AXIS_TDATA[14] = \<const0> ;
  assign M12_AXIS_TDATA[13] = \<const0> ;
  assign M12_AXIS_TDATA[12] = \<const0> ;
  assign M12_AXIS_TDATA[11] = \<const0> ;
  assign M12_AXIS_TDATA[10] = \<const0> ;
  assign M12_AXIS_TDATA[9] = \<const0> ;
  assign M12_AXIS_TDATA[8] = \<const0> ;
  assign M12_AXIS_TDATA[7] = \<const0> ;
  assign M12_AXIS_TDATA[6] = \<const0> ;
  assign M12_AXIS_TDATA[5] = \<const0> ;
  assign M12_AXIS_TDATA[4] = \<const0> ;
  assign M12_AXIS_TDATA[3] = \<const0> ;
  assign M12_AXIS_TDATA[2] = \<const0> ;
  assign M12_AXIS_TDATA[1] = \<const0> ;
  assign M12_AXIS_TDATA[0] = \<const0> ;
  assign M12_AXIS_TLAST = \<const0> ;
  assign M12_AXIS_TVALID = \<const0> ;
  assign M13_AXIS_TDATA[31] = \<const0> ;
  assign M13_AXIS_TDATA[30] = \<const0> ;
  assign M13_AXIS_TDATA[29] = \<const0> ;
  assign M13_AXIS_TDATA[28] = \<const0> ;
  assign M13_AXIS_TDATA[27] = \<const0> ;
  assign M13_AXIS_TDATA[26] = \<const0> ;
  assign M13_AXIS_TDATA[25] = \<const0> ;
  assign M13_AXIS_TDATA[24] = \<const0> ;
  assign M13_AXIS_TDATA[23] = \<const0> ;
  assign M13_AXIS_TDATA[22] = \<const0> ;
  assign M13_AXIS_TDATA[21] = \<const0> ;
  assign M13_AXIS_TDATA[20] = \<const0> ;
  assign M13_AXIS_TDATA[19] = \<const0> ;
  assign M13_AXIS_TDATA[18] = \<const0> ;
  assign M13_AXIS_TDATA[17] = \<const0> ;
  assign M13_AXIS_TDATA[16] = \<const0> ;
  assign M13_AXIS_TDATA[15] = \<const0> ;
  assign M13_AXIS_TDATA[14] = \<const0> ;
  assign M13_AXIS_TDATA[13] = \<const0> ;
  assign M13_AXIS_TDATA[12] = \<const0> ;
  assign M13_AXIS_TDATA[11] = \<const0> ;
  assign M13_AXIS_TDATA[10] = \<const0> ;
  assign M13_AXIS_TDATA[9] = \<const0> ;
  assign M13_AXIS_TDATA[8] = \<const0> ;
  assign M13_AXIS_TDATA[7] = \<const0> ;
  assign M13_AXIS_TDATA[6] = \<const0> ;
  assign M13_AXIS_TDATA[5] = \<const0> ;
  assign M13_AXIS_TDATA[4] = \<const0> ;
  assign M13_AXIS_TDATA[3] = \<const0> ;
  assign M13_AXIS_TDATA[2] = \<const0> ;
  assign M13_AXIS_TDATA[1] = \<const0> ;
  assign M13_AXIS_TDATA[0] = \<const0> ;
  assign M13_AXIS_TLAST = \<const0> ;
  assign M13_AXIS_TVALID = \<const0> ;
  assign M14_AXIS_TDATA[31] = \<const0> ;
  assign M14_AXIS_TDATA[30] = \<const0> ;
  assign M14_AXIS_TDATA[29] = \<const0> ;
  assign M14_AXIS_TDATA[28] = \<const0> ;
  assign M14_AXIS_TDATA[27] = \<const0> ;
  assign M14_AXIS_TDATA[26] = \<const0> ;
  assign M14_AXIS_TDATA[25] = \<const0> ;
  assign M14_AXIS_TDATA[24] = \<const0> ;
  assign M14_AXIS_TDATA[23] = \<const0> ;
  assign M14_AXIS_TDATA[22] = \<const0> ;
  assign M14_AXIS_TDATA[21] = \<const0> ;
  assign M14_AXIS_TDATA[20] = \<const0> ;
  assign M14_AXIS_TDATA[19] = \<const0> ;
  assign M14_AXIS_TDATA[18] = \<const0> ;
  assign M14_AXIS_TDATA[17] = \<const0> ;
  assign M14_AXIS_TDATA[16] = \<const0> ;
  assign M14_AXIS_TDATA[15] = \<const0> ;
  assign M14_AXIS_TDATA[14] = \<const0> ;
  assign M14_AXIS_TDATA[13] = \<const0> ;
  assign M14_AXIS_TDATA[12] = \<const0> ;
  assign M14_AXIS_TDATA[11] = \<const0> ;
  assign M14_AXIS_TDATA[10] = \<const0> ;
  assign M14_AXIS_TDATA[9] = \<const0> ;
  assign M14_AXIS_TDATA[8] = \<const0> ;
  assign M14_AXIS_TDATA[7] = \<const0> ;
  assign M14_AXIS_TDATA[6] = \<const0> ;
  assign M14_AXIS_TDATA[5] = \<const0> ;
  assign M14_AXIS_TDATA[4] = \<const0> ;
  assign M14_AXIS_TDATA[3] = \<const0> ;
  assign M14_AXIS_TDATA[2] = \<const0> ;
  assign M14_AXIS_TDATA[1] = \<const0> ;
  assign M14_AXIS_TDATA[0] = \<const0> ;
  assign M14_AXIS_TLAST = \<const0> ;
  assign M14_AXIS_TVALID = \<const0> ;
  assign M15_AXIS_TDATA[31] = \<const0> ;
  assign M15_AXIS_TDATA[30] = \<const0> ;
  assign M15_AXIS_TDATA[29] = \<const0> ;
  assign M15_AXIS_TDATA[28] = \<const0> ;
  assign M15_AXIS_TDATA[27] = \<const0> ;
  assign M15_AXIS_TDATA[26] = \<const0> ;
  assign M15_AXIS_TDATA[25] = \<const0> ;
  assign M15_AXIS_TDATA[24] = \<const0> ;
  assign M15_AXIS_TDATA[23] = \<const0> ;
  assign M15_AXIS_TDATA[22] = \<const0> ;
  assign M15_AXIS_TDATA[21] = \<const0> ;
  assign M15_AXIS_TDATA[20] = \<const0> ;
  assign M15_AXIS_TDATA[19] = \<const0> ;
  assign M15_AXIS_TDATA[18] = \<const0> ;
  assign M15_AXIS_TDATA[17] = \<const0> ;
  assign M15_AXIS_TDATA[16] = \<const0> ;
  assign M15_AXIS_TDATA[15] = \<const0> ;
  assign M15_AXIS_TDATA[14] = \<const0> ;
  assign M15_AXIS_TDATA[13] = \<const0> ;
  assign M15_AXIS_TDATA[12] = \<const0> ;
  assign M15_AXIS_TDATA[11] = \<const0> ;
  assign M15_AXIS_TDATA[10] = \<const0> ;
  assign M15_AXIS_TDATA[9] = \<const0> ;
  assign M15_AXIS_TDATA[8] = \<const0> ;
  assign M15_AXIS_TDATA[7] = \<const0> ;
  assign M15_AXIS_TDATA[6] = \<const0> ;
  assign M15_AXIS_TDATA[5] = \<const0> ;
  assign M15_AXIS_TDATA[4] = \<const0> ;
  assign M15_AXIS_TDATA[3] = \<const0> ;
  assign M15_AXIS_TDATA[2] = \<const0> ;
  assign M15_AXIS_TDATA[1] = \<const0> ;
  assign M15_AXIS_TDATA[0] = \<const0> ;
  assign M15_AXIS_TLAST = \<const0> ;
  assign M15_AXIS_TVALID = \<const0> ;
  assign M1_AXIS_TDATA[31] = \<const0> ;
  assign M1_AXIS_TDATA[30] = \<const0> ;
  assign M1_AXIS_TDATA[29] = \<const0> ;
  assign M1_AXIS_TDATA[28] = \<const0> ;
  assign M1_AXIS_TDATA[27] = \<const0> ;
  assign M1_AXIS_TDATA[26] = \<const0> ;
  assign M1_AXIS_TDATA[25] = \<const0> ;
  assign M1_AXIS_TDATA[24] = \<const0> ;
  assign M1_AXIS_TDATA[23] = \<const0> ;
  assign M1_AXIS_TDATA[22] = \<const0> ;
  assign M1_AXIS_TDATA[21] = \<const0> ;
  assign M1_AXIS_TDATA[20] = \<const0> ;
  assign M1_AXIS_TDATA[19] = \<const0> ;
  assign M1_AXIS_TDATA[18] = \<const0> ;
  assign M1_AXIS_TDATA[17] = \<const0> ;
  assign M1_AXIS_TDATA[16] = \<const0> ;
  assign M1_AXIS_TDATA[15] = \<const0> ;
  assign M1_AXIS_TDATA[14] = \<const0> ;
  assign M1_AXIS_TDATA[13] = \<const0> ;
  assign M1_AXIS_TDATA[12] = \<const0> ;
  assign M1_AXIS_TDATA[11] = \<const0> ;
  assign M1_AXIS_TDATA[10] = \<const0> ;
  assign M1_AXIS_TDATA[9] = \<const0> ;
  assign M1_AXIS_TDATA[8] = \<const0> ;
  assign M1_AXIS_TDATA[7] = \<const0> ;
  assign M1_AXIS_TDATA[6] = \<const0> ;
  assign M1_AXIS_TDATA[5] = \<const0> ;
  assign M1_AXIS_TDATA[4] = \<const0> ;
  assign M1_AXIS_TDATA[3] = \<const0> ;
  assign M1_AXIS_TDATA[2] = \<const0> ;
  assign M1_AXIS_TDATA[1] = \<const0> ;
  assign M1_AXIS_TDATA[0] = \<const0> ;
  assign M1_AXIS_TLAST = \<const0> ;
  assign M1_AXIS_TVALID = \<const0> ;
  assign M2_AXIS_TDATA[31] = \<const0> ;
  assign M2_AXIS_TDATA[30] = \<const0> ;
  assign M2_AXIS_TDATA[29] = \<const0> ;
  assign M2_AXIS_TDATA[28] = \<const0> ;
  assign M2_AXIS_TDATA[27] = \<const0> ;
  assign M2_AXIS_TDATA[26] = \<const0> ;
  assign M2_AXIS_TDATA[25] = \<const0> ;
  assign M2_AXIS_TDATA[24] = \<const0> ;
  assign M2_AXIS_TDATA[23] = \<const0> ;
  assign M2_AXIS_TDATA[22] = \<const0> ;
  assign M2_AXIS_TDATA[21] = \<const0> ;
  assign M2_AXIS_TDATA[20] = \<const0> ;
  assign M2_AXIS_TDATA[19] = \<const0> ;
  assign M2_AXIS_TDATA[18] = \<const0> ;
  assign M2_AXIS_TDATA[17] = \<const0> ;
  assign M2_AXIS_TDATA[16] = \<const0> ;
  assign M2_AXIS_TDATA[15] = \<const0> ;
  assign M2_AXIS_TDATA[14] = \<const0> ;
  assign M2_AXIS_TDATA[13] = \<const0> ;
  assign M2_AXIS_TDATA[12] = \<const0> ;
  assign M2_AXIS_TDATA[11] = \<const0> ;
  assign M2_AXIS_TDATA[10] = \<const0> ;
  assign M2_AXIS_TDATA[9] = \<const0> ;
  assign M2_AXIS_TDATA[8] = \<const0> ;
  assign M2_AXIS_TDATA[7] = \<const0> ;
  assign M2_AXIS_TDATA[6] = \<const0> ;
  assign M2_AXIS_TDATA[5] = \<const0> ;
  assign M2_AXIS_TDATA[4] = \<const0> ;
  assign M2_AXIS_TDATA[3] = \<const0> ;
  assign M2_AXIS_TDATA[2] = \<const0> ;
  assign M2_AXIS_TDATA[1] = \<const0> ;
  assign M2_AXIS_TDATA[0] = \<const0> ;
  assign M2_AXIS_TLAST = \<const0> ;
  assign M2_AXIS_TVALID = \<const0> ;
  assign M3_AXIS_TDATA[31] = \<const0> ;
  assign M3_AXIS_TDATA[30] = \<const0> ;
  assign M3_AXIS_TDATA[29] = \<const0> ;
  assign M3_AXIS_TDATA[28] = \<const0> ;
  assign M3_AXIS_TDATA[27] = \<const0> ;
  assign M3_AXIS_TDATA[26] = \<const0> ;
  assign M3_AXIS_TDATA[25] = \<const0> ;
  assign M3_AXIS_TDATA[24] = \<const0> ;
  assign M3_AXIS_TDATA[23] = \<const0> ;
  assign M3_AXIS_TDATA[22] = \<const0> ;
  assign M3_AXIS_TDATA[21] = \<const0> ;
  assign M3_AXIS_TDATA[20] = \<const0> ;
  assign M3_AXIS_TDATA[19] = \<const0> ;
  assign M3_AXIS_TDATA[18] = \<const0> ;
  assign M3_AXIS_TDATA[17] = \<const0> ;
  assign M3_AXIS_TDATA[16] = \<const0> ;
  assign M3_AXIS_TDATA[15] = \<const0> ;
  assign M3_AXIS_TDATA[14] = \<const0> ;
  assign M3_AXIS_TDATA[13] = \<const0> ;
  assign M3_AXIS_TDATA[12] = \<const0> ;
  assign M3_AXIS_TDATA[11] = \<const0> ;
  assign M3_AXIS_TDATA[10] = \<const0> ;
  assign M3_AXIS_TDATA[9] = \<const0> ;
  assign M3_AXIS_TDATA[8] = \<const0> ;
  assign M3_AXIS_TDATA[7] = \<const0> ;
  assign M3_AXIS_TDATA[6] = \<const0> ;
  assign M3_AXIS_TDATA[5] = \<const0> ;
  assign M3_AXIS_TDATA[4] = \<const0> ;
  assign M3_AXIS_TDATA[3] = \<const0> ;
  assign M3_AXIS_TDATA[2] = \<const0> ;
  assign M3_AXIS_TDATA[1] = \<const0> ;
  assign M3_AXIS_TDATA[0] = \<const0> ;
  assign M3_AXIS_TLAST = \<const0> ;
  assign M3_AXIS_TVALID = \<const0> ;
  assign M4_AXIS_TDATA[31] = \<const0> ;
  assign M4_AXIS_TDATA[30] = \<const0> ;
  assign M4_AXIS_TDATA[29] = \<const0> ;
  assign M4_AXIS_TDATA[28] = \<const0> ;
  assign M4_AXIS_TDATA[27] = \<const0> ;
  assign M4_AXIS_TDATA[26] = \<const0> ;
  assign M4_AXIS_TDATA[25] = \<const0> ;
  assign M4_AXIS_TDATA[24] = \<const0> ;
  assign M4_AXIS_TDATA[23] = \<const0> ;
  assign M4_AXIS_TDATA[22] = \<const0> ;
  assign M4_AXIS_TDATA[21] = \<const0> ;
  assign M4_AXIS_TDATA[20] = \<const0> ;
  assign M4_AXIS_TDATA[19] = \<const0> ;
  assign M4_AXIS_TDATA[18] = \<const0> ;
  assign M4_AXIS_TDATA[17] = \<const0> ;
  assign M4_AXIS_TDATA[16] = \<const0> ;
  assign M4_AXIS_TDATA[15] = \<const0> ;
  assign M4_AXIS_TDATA[14] = \<const0> ;
  assign M4_AXIS_TDATA[13] = \<const0> ;
  assign M4_AXIS_TDATA[12] = \<const0> ;
  assign M4_AXIS_TDATA[11] = \<const0> ;
  assign M4_AXIS_TDATA[10] = \<const0> ;
  assign M4_AXIS_TDATA[9] = \<const0> ;
  assign M4_AXIS_TDATA[8] = \<const0> ;
  assign M4_AXIS_TDATA[7] = \<const0> ;
  assign M4_AXIS_TDATA[6] = \<const0> ;
  assign M4_AXIS_TDATA[5] = \<const0> ;
  assign M4_AXIS_TDATA[4] = \<const0> ;
  assign M4_AXIS_TDATA[3] = \<const0> ;
  assign M4_AXIS_TDATA[2] = \<const0> ;
  assign M4_AXIS_TDATA[1] = \<const0> ;
  assign M4_AXIS_TDATA[0] = \<const0> ;
  assign M4_AXIS_TLAST = \<const0> ;
  assign M4_AXIS_TVALID = \<const0> ;
  assign M5_AXIS_TDATA[31] = \<const0> ;
  assign M5_AXIS_TDATA[30] = \<const0> ;
  assign M5_AXIS_TDATA[29] = \<const0> ;
  assign M5_AXIS_TDATA[28] = \<const0> ;
  assign M5_AXIS_TDATA[27] = \<const0> ;
  assign M5_AXIS_TDATA[26] = \<const0> ;
  assign M5_AXIS_TDATA[25] = \<const0> ;
  assign M5_AXIS_TDATA[24] = \<const0> ;
  assign M5_AXIS_TDATA[23] = \<const0> ;
  assign M5_AXIS_TDATA[22] = \<const0> ;
  assign M5_AXIS_TDATA[21] = \<const0> ;
  assign M5_AXIS_TDATA[20] = \<const0> ;
  assign M5_AXIS_TDATA[19] = \<const0> ;
  assign M5_AXIS_TDATA[18] = \<const0> ;
  assign M5_AXIS_TDATA[17] = \<const0> ;
  assign M5_AXIS_TDATA[16] = \<const0> ;
  assign M5_AXIS_TDATA[15] = \<const0> ;
  assign M5_AXIS_TDATA[14] = \<const0> ;
  assign M5_AXIS_TDATA[13] = \<const0> ;
  assign M5_AXIS_TDATA[12] = \<const0> ;
  assign M5_AXIS_TDATA[11] = \<const0> ;
  assign M5_AXIS_TDATA[10] = \<const0> ;
  assign M5_AXIS_TDATA[9] = \<const0> ;
  assign M5_AXIS_TDATA[8] = \<const0> ;
  assign M5_AXIS_TDATA[7] = \<const0> ;
  assign M5_AXIS_TDATA[6] = \<const0> ;
  assign M5_AXIS_TDATA[5] = \<const0> ;
  assign M5_AXIS_TDATA[4] = \<const0> ;
  assign M5_AXIS_TDATA[3] = \<const0> ;
  assign M5_AXIS_TDATA[2] = \<const0> ;
  assign M5_AXIS_TDATA[1] = \<const0> ;
  assign M5_AXIS_TDATA[0] = \<const0> ;
  assign M5_AXIS_TLAST = \<const0> ;
  assign M5_AXIS_TVALID = \<const0> ;
  assign M6_AXIS_TDATA[31] = \<const0> ;
  assign M6_AXIS_TDATA[30] = \<const0> ;
  assign M6_AXIS_TDATA[29] = \<const0> ;
  assign M6_AXIS_TDATA[28] = \<const0> ;
  assign M6_AXIS_TDATA[27] = \<const0> ;
  assign M6_AXIS_TDATA[26] = \<const0> ;
  assign M6_AXIS_TDATA[25] = \<const0> ;
  assign M6_AXIS_TDATA[24] = \<const0> ;
  assign M6_AXIS_TDATA[23] = \<const0> ;
  assign M6_AXIS_TDATA[22] = \<const0> ;
  assign M6_AXIS_TDATA[21] = \<const0> ;
  assign M6_AXIS_TDATA[20] = \<const0> ;
  assign M6_AXIS_TDATA[19] = \<const0> ;
  assign M6_AXIS_TDATA[18] = \<const0> ;
  assign M6_AXIS_TDATA[17] = \<const0> ;
  assign M6_AXIS_TDATA[16] = \<const0> ;
  assign M6_AXIS_TDATA[15] = \<const0> ;
  assign M6_AXIS_TDATA[14] = \<const0> ;
  assign M6_AXIS_TDATA[13] = \<const0> ;
  assign M6_AXIS_TDATA[12] = \<const0> ;
  assign M6_AXIS_TDATA[11] = \<const0> ;
  assign M6_AXIS_TDATA[10] = \<const0> ;
  assign M6_AXIS_TDATA[9] = \<const0> ;
  assign M6_AXIS_TDATA[8] = \<const0> ;
  assign M6_AXIS_TDATA[7] = \<const0> ;
  assign M6_AXIS_TDATA[6] = \<const0> ;
  assign M6_AXIS_TDATA[5] = \<const0> ;
  assign M6_AXIS_TDATA[4] = \<const0> ;
  assign M6_AXIS_TDATA[3] = \<const0> ;
  assign M6_AXIS_TDATA[2] = \<const0> ;
  assign M6_AXIS_TDATA[1] = \<const0> ;
  assign M6_AXIS_TDATA[0] = \<const0> ;
  assign M6_AXIS_TLAST = \<const0> ;
  assign M6_AXIS_TVALID = \<const0> ;
  assign M7_AXIS_TDATA[31] = \<const0> ;
  assign M7_AXIS_TDATA[30] = \<const0> ;
  assign M7_AXIS_TDATA[29] = \<const0> ;
  assign M7_AXIS_TDATA[28] = \<const0> ;
  assign M7_AXIS_TDATA[27] = \<const0> ;
  assign M7_AXIS_TDATA[26] = \<const0> ;
  assign M7_AXIS_TDATA[25] = \<const0> ;
  assign M7_AXIS_TDATA[24] = \<const0> ;
  assign M7_AXIS_TDATA[23] = \<const0> ;
  assign M7_AXIS_TDATA[22] = \<const0> ;
  assign M7_AXIS_TDATA[21] = \<const0> ;
  assign M7_AXIS_TDATA[20] = \<const0> ;
  assign M7_AXIS_TDATA[19] = \<const0> ;
  assign M7_AXIS_TDATA[18] = \<const0> ;
  assign M7_AXIS_TDATA[17] = \<const0> ;
  assign M7_AXIS_TDATA[16] = \<const0> ;
  assign M7_AXIS_TDATA[15] = \<const0> ;
  assign M7_AXIS_TDATA[14] = \<const0> ;
  assign M7_AXIS_TDATA[13] = \<const0> ;
  assign M7_AXIS_TDATA[12] = \<const0> ;
  assign M7_AXIS_TDATA[11] = \<const0> ;
  assign M7_AXIS_TDATA[10] = \<const0> ;
  assign M7_AXIS_TDATA[9] = \<const0> ;
  assign M7_AXIS_TDATA[8] = \<const0> ;
  assign M7_AXIS_TDATA[7] = \<const0> ;
  assign M7_AXIS_TDATA[6] = \<const0> ;
  assign M7_AXIS_TDATA[5] = \<const0> ;
  assign M7_AXIS_TDATA[4] = \<const0> ;
  assign M7_AXIS_TDATA[3] = \<const0> ;
  assign M7_AXIS_TDATA[2] = \<const0> ;
  assign M7_AXIS_TDATA[1] = \<const0> ;
  assign M7_AXIS_TDATA[0] = \<const0> ;
  assign M7_AXIS_TLAST = \<const0> ;
  assign M7_AXIS_TVALID = \<const0> ;
  assign M8_AXIS_TDATA[31] = \<const0> ;
  assign M8_AXIS_TDATA[30] = \<const0> ;
  assign M8_AXIS_TDATA[29] = \<const0> ;
  assign M8_AXIS_TDATA[28] = \<const0> ;
  assign M8_AXIS_TDATA[27] = \<const0> ;
  assign M8_AXIS_TDATA[26] = \<const0> ;
  assign M8_AXIS_TDATA[25] = \<const0> ;
  assign M8_AXIS_TDATA[24] = \<const0> ;
  assign M8_AXIS_TDATA[23] = \<const0> ;
  assign M8_AXIS_TDATA[22] = \<const0> ;
  assign M8_AXIS_TDATA[21] = \<const0> ;
  assign M8_AXIS_TDATA[20] = \<const0> ;
  assign M8_AXIS_TDATA[19] = \<const0> ;
  assign M8_AXIS_TDATA[18] = \<const0> ;
  assign M8_AXIS_TDATA[17] = \<const0> ;
  assign M8_AXIS_TDATA[16] = \<const0> ;
  assign M8_AXIS_TDATA[15] = \<const0> ;
  assign M8_AXIS_TDATA[14] = \<const0> ;
  assign M8_AXIS_TDATA[13] = \<const0> ;
  assign M8_AXIS_TDATA[12] = \<const0> ;
  assign M8_AXIS_TDATA[11] = \<const0> ;
  assign M8_AXIS_TDATA[10] = \<const0> ;
  assign M8_AXIS_TDATA[9] = \<const0> ;
  assign M8_AXIS_TDATA[8] = \<const0> ;
  assign M8_AXIS_TDATA[7] = \<const0> ;
  assign M8_AXIS_TDATA[6] = \<const0> ;
  assign M8_AXIS_TDATA[5] = \<const0> ;
  assign M8_AXIS_TDATA[4] = \<const0> ;
  assign M8_AXIS_TDATA[3] = \<const0> ;
  assign M8_AXIS_TDATA[2] = \<const0> ;
  assign M8_AXIS_TDATA[1] = \<const0> ;
  assign M8_AXIS_TDATA[0] = \<const0> ;
  assign M8_AXIS_TLAST = \<const0> ;
  assign M8_AXIS_TVALID = \<const0> ;
  assign M9_AXIS_TDATA[31] = \<const0> ;
  assign M9_AXIS_TDATA[30] = \<const0> ;
  assign M9_AXIS_TDATA[29] = \<const0> ;
  assign M9_AXIS_TDATA[28] = \<const0> ;
  assign M9_AXIS_TDATA[27] = \<const0> ;
  assign M9_AXIS_TDATA[26] = \<const0> ;
  assign M9_AXIS_TDATA[25] = \<const0> ;
  assign M9_AXIS_TDATA[24] = \<const0> ;
  assign M9_AXIS_TDATA[23] = \<const0> ;
  assign M9_AXIS_TDATA[22] = \<const0> ;
  assign M9_AXIS_TDATA[21] = \<const0> ;
  assign M9_AXIS_TDATA[20] = \<const0> ;
  assign M9_AXIS_TDATA[19] = \<const0> ;
  assign M9_AXIS_TDATA[18] = \<const0> ;
  assign M9_AXIS_TDATA[17] = \<const0> ;
  assign M9_AXIS_TDATA[16] = \<const0> ;
  assign M9_AXIS_TDATA[15] = \<const0> ;
  assign M9_AXIS_TDATA[14] = \<const0> ;
  assign M9_AXIS_TDATA[13] = \<const0> ;
  assign M9_AXIS_TDATA[12] = \<const0> ;
  assign M9_AXIS_TDATA[11] = \<const0> ;
  assign M9_AXIS_TDATA[10] = \<const0> ;
  assign M9_AXIS_TDATA[9] = \<const0> ;
  assign M9_AXIS_TDATA[8] = \<const0> ;
  assign M9_AXIS_TDATA[7] = \<const0> ;
  assign M9_AXIS_TDATA[6] = \<const0> ;
  assign M9_AXIS_TDATA[5] = \<const0> ;
  assign M9_AXIS_TDATA[4] = \<const0> ;
  assign M9_AXIS_TDATA[3] = \<const0> ;
  assign M9_AXIS_TDATA[2] = \<const0> ;
  assign M9_AXIS_TDATA[1] = \<const0> ;
  assign M9_AXIS_TDATA[0] = \<const0> ;
  assign M9_AXIS_TLAST = \<const0> ;
  assign M9_AXIS_TVALID = \<const0> ;
  assign MB_Error = \<const0> ;
  assign MB_Halted = \^LOCKSTEP_Master_Out [10];
  assign M_AXI_DC_ACREADY = \<const0> ;
  assign M_AXI_DC_ARADDR[31] = \<const0> ;
  assign M_AXI_DC_ARADDR[30] = \<const0> ;
  assign M_AXI_DC_ARADDR[29] = \<const0> ;
  assign M_AXI_DC_ARADDR[28] = \<const0> ;
  assign M_AXI_DC_ARADDR[27] = \<const0> ;
  assign M_AXI_DC_ARADDR[26] = \<const0> ;
  assign M_AXI_DC_ARADDR[25] = \<const0> ;
  assign M_AXI_DC_ARADDR[24] = \<const0> ;
  assign M_AXI_DC_ARADDR[23] = \<const0> ;
  assign M_AXI_DC_ARADDR[22] = \<const0> ;
  assign M_AXI_DC_ARADDR[21] = \<const0> ;
  assign M_AXI_DC_ARADDR[20] = \<const0> ;
  assign M_AXI_DC_ARADDR[19] = \<const0> ;
  assign M_AXI_DC_ARADDR[18] = \<const0> ;
  assign M_AXI_DC_ARADDR[17] = \<const0> ;
  assign M_AXI_DC_ARADDR[16] = \<const0> ;
  assign M_AXI_DC_ARADDR[15] = \<const0> ;
  assign M_AXI_DC_ARADDR[14] = \<const0> ;
  assign M_AXI_DC_ARADDR[13] = \<const0> ;
  assign M_AXI_DC_ARADDR[12] = \<const0> ;
  assign M_AXI_DC_ARADDR[11] = \<const0> ;
  assign M_AXI_DC_ARADDR[10] = \<const0> ;
  assign M_AXI_DC_ARADDR[9] = \<const0> ;
  assign M_AXI_DC_ARADDR[8] = \<const0> ;
  assign M_AXI_DC_ARADDR[7] = \<const0> ;
  assign M_AXI_DC_ARADDR[6] = \<const0> ;
  assign M_AXI_DC_ARADDR[5] = \<const0> ;
  assign M_AXI_DC_ARADDR[4] = \<const0> ;
  assign M_AXI_DC_ARADDR[3] = \<const0> ;
  assign M_AXI_DC_ARADDR[2] = \<const0> ;
  assign M_AXI_DC_ARADDR[1] = \<const0> ;
  assign M_AXI_DC_ARADDR[0] = \<const0> ;
  assign M_AXI_DC_ARBAR[1] = \<const0> ;
  assign M_AXI_DC_ARBAR[0] = \<const0> ;
  assign M_AXI_DC_ARBURST[1] = \<const0> ;
  assign M_AXI_DC_ARBURST[0] = \<const0> ;
  assign M_AXI_DC_ARCACHE[3] = \<const0> ;
  assign M_AXI_DC_ARCACHE[2] = \<const0> ;
  assign M_AXI_DC_ARCACHE[1] = \<const0> ;
  assign M_AXI_DC_ARCACHE[0] = \<const0> ;
  assign M_AXI_DC_ARDOMAIN[1] = \<const0> ;
  assign M_AXI_DC_ARDOMAIN[0] = \<const0> ;
  assign M_AXI_DC_ARID[0] = \<const0> ;
  assign M_AXI_DC_ARLEN[7] = \<const0> ;
  assign M_AXI_DC_ARLEN[6] = \<const0> ;
  assign M_AXI_DC_ARLEN[5] = \<const0> ;
  assign M_AXI_DC_ARLEN[4] = \<const0> ;
  assign M_AXI_DC_ARLEN[3] = \<const0> ;
  assign M_AXI_DC_ARLEN[2] = \<const0> ;
  assign M_AXI_DC_ARLEN[1] = \<const0> ;
  assign M_AXI_DC_ARLEN[0] = \<const0> ;
  assign M_AXI_DC_ARLOCK = \<const0> ;
  assign M_AXI_DC_ARPROT[2] = \<const0> ;
  assign M_AXI_DC_ARPROT[1] = \<const0> ;
  assign M_AXI_DC_ARPROT[0] = \<const0> ;
  assign M_AXI_DC_ARQOS[3] = \<const0> ;
  assign M_AXI_DC_ARQOS[2] = \<const0> ;
  assign M_AXI_DC_ARQOS[1] = \<const0> ;
  assign M_AXI_DC_ARQOS[0] = \<const0> ;
  assign M_AXI_DC_ARSIZE[2] = \<const0> ;
  assign M_AXI_DC_ARSIZE[1] = \<const0> ;
  assign M_AXI_DC_ARSIZE[0] = \<const0> ;
  assign M_AXI_DC_ARSNOOP[3] = \<const0> ;
  assign M_AXI_DC_ARSNOOP[2] = \<const0> ;
  assign M_AXI_DC_ARSNOOP[1] = \<const0> ;
  assign M_AXI_DC_ARSNOOP[0] = \<const0> ;
  assign M_AXI_DC_ARUSER[4] = \<const0> ;
  assign M_AXI_DC_ARUSER[3] = \<const0> ;
  assign M_AXI_DC_ARUSER[2] = \<const0> ;
  assign M_AXI_DC_ARUSER[1] = \<const0> ;
  assign M_AXI_DC_ARUSER[0] = \<const0> ;
  assign M_AXI_DC_ARVALID = \<const0> ;
  assign M_AXI_DC_AWADDR[31] = \<const0> ;
  assign M_AXI_DC_AWADDR[30] = \<const0> ;
  assign M_AXI_DC_AWADDR[29] = \<const0> ;
  assign M_AXI_DC_AWADDR[28] = \<const0> ;
  assign M_AXI_DC_AWADDR[27] = \<const0> ;
  assign M_AXI_DC_AWADDR[26] = \<const0> ;
  assign M_AXI_DC_AWADDR[25] = \<const0> ;
  assign M_AXI_DC_AWADDR[24] = \<const0> ;
  assign M_AXI_DC_AWADDR[23] = \<const0> ;
  assign M_AXI_DC_AWADDR[22] = \<const0> ;
  assign M_AXI_DC_AWADDR[21] = \<const0> ;
  assign M_AXI_DC_AWADDR[20] = \<const0> ;
  assign M_AXI_DC_AWADDR[19] = \<const0> ;
  assign M_AXI_DC_AWADDR[18] = \<const0> ;
  assign M_AXI_DC_AWADDR[17] = \<const0> ;
  assign M_AXI_DC_AWADDR[16] = \<const0> ;
  assign M_AXI_DC_AWADDR[15] = \<const0> ;
  assign M_AXI_DC_AWADDR[14] = \<const0> ;
  assign M_AXI_DC_AWADDR[13] = \<const0> ;
  assign M_AXI_DC_AWADDR[12] = \<const0> ;
  assign M_AXI_DC_AWADDR[11] = \<const0> ;
  assign M_AXI_DC_AWADDR[10] = \<const0> ;
  assign M_AXI_DC_AWADDR[9] = \<const0> ;
  assign M_AXI_DC_AWADDR[8] = \<const0> ;
  assign M_AXI_DC_AWADDR[7] = \<const0> ;
  assign M_AXI_DC_AWADDR[6] = \<const0> ;
  assign M_AXI_DC_AWADDR[5] = \<const0> ;
  assign M_AXI_DC_AWADDR[4] = \<const0> ;
  assign M_AXI_DC_AWADDR[3] = \<const0> ;
  assign M_AXI_DC_AWADDR[2] = \<const0> ;
  assign M_AXI_DC_AWADDR[1] = \<const0> ;
  assign M_AXI_DC_AWADDR[0] = \<const0> ;
  assign M_AXI_DC_AWBAR[1] = \<const0> ;
  assign M_AXI_DC_AWBAR[0] = \<const0> ;
  assign M_AXI_DC_AWBURST[1] = \<const0> ;
  assign M_AXI_DC_AWBURST[0] = \<const0> ;
  assign M_AXI_DC_AWCACHE[3] = \<const0> ;
  assign M_AXI_DC_AWCACHE[2] = \<const0> ;
  assign M_AXI_DC_AWCACHE[1] = \<const0> ;
  assign M_AXI_DC_AWCACHE[0] = \<const0> ;
  assign M_AXI_DC_AWDOMAIN[1] = \<const0> ;
  assign M_AXI_DC_AWDOMAIN[0] = \<const0> ;
  assign M_AXI_DC_AWID[0] = \<const0> ;
  assign M_AXI_DC_AWLEN[7] = \<const0> ;
  assign M_AXI_DC_AWLEN[6] = \<const0> ;
  assign M_AXI_DC_AWLEN[5] = \<const0> ;
  assign M_AXI_DC_AWLEN[4] = \<const0> ;
  assign M_AXI_DC_AWLEN[3] = \<const0> ;
  assign M_AXI_DC_AWLEN[2] = \<const0> ;
  assign M_AXI_DC_AWLEN[1] = \<const0> ;
  assign M_AXI_DC_AWLEN[0] = \<const0> ;
  assign M_AXI_DC_AWLOCK = \<const0> ;
  assign M_AXI_DC_AWPROT[2] = \<const0> ;
  assign M_AXI_DC_AWPROT[1] = \<const0> ;
  assign M_AXI_DC_AWPROT[0] = \<const0> ;
  assign M_AXI_DC_AWQOS[3] = \<const0> ;
  assign M_AXI_DC_AWQOS[2] = \<const0> ;
  assign M_AXI_DC_AWQOS[1] = \<const0> ;
  assign M_AXI_DC_AWQOS[0] = \<const0> ;
  assign M_AXI_DC_AWSIZE[2] = \<const0> ;
  assign M_AXI_DC_AWSIZE[1] = \<const0> ;
  assign M_AXI_DC_AWSIZE[0] = \<const0> ;
  assign M_AXI_DC_AWSNOOP[2] = \<const0> ;
  assign M_AXI_DC_AWSNOOP[1] = \<const0> ;
  assign M_AXI_DC_AWSNOOP[0] = \<const0> ;
  assign M_AXI_DC_AWUSER[4] = \<const0> ;
  assign M_AXI_DC_AWUSER[3] = \<const0> ;
  assign M_AXI_DC_AWUSER[2] = \<const0> ;
  assign M_AXI_DC_AWUSER[1] = \<const0> ;
  assign M_AXI_DC_AWUSER[0] = \<const0> ;
  assign M_AXI_DC_AWVALID = \<const0> ;
  assign M_AXI_DC_BREADY = \<const0> ;
  assign M_AXI_DC_CDDATA[31] = \<const0> ;
  assign M_AXI_DC_CDDATA[30] = \<const0> ;
  assign M_AXI_DC_CDDATA[29] = \<const0> ;
  assign M_AXI_DC_CDDATA[28] = \<const0> ;
  assign M_AXI_DC_CDDATA[27] = \<const0> ;
  assign M_AXI_DC_CDDATA[26] = \<const0> ;
  assign M_AXI_DC_CDDATA[25] = \<const0> ;
  assign M_AXI_DC_CDDATA[24] = \<const0> ;
  assign M_AXI_DC_CDDATA[23] = \<const0> ;
  assign M_AXI_DC_CDDATA[22] = \<const0> ;
  assign M_AXI_DC_CDDATA[21] = \<const0> ;
  assign M_AXI_DC_CDDATA[20] = \<const0> ;
  assign M_AXI_DC_CDDATA[19] = \<const0> ;
  assign M_AXI_DC_CDDATA[18] = \<const0> ;
  assign M_AXI_DC_CDDATA[17] = \<const0> ;
  assign M_AXI_DC_CDDATA[16] = \<const0> ;
  assign M_AXI_DC_CDDATA[15] = \<const0> ;
  assign M_AXI_DC_CDDATA[14] = \<const0> ;
  assign M_AXI_DC_CDDATA[13] = \<const0> ;
  assign M_AXI_DC_CDDATA[12] = \<const0> ;
  assign M_AXI_DC_CDDATA[11] = \<const0> ;
  assign M_AXI_DC_CDDATA[10] = \<const0> ;
  assign M_AXI_DC_CDDATA[9] = \<const0> ;
  assign M_AXI_DC_CDDATA[8] = \<const0> ;
  assign M_AXI_DC_CDDATA[7] = \<const0> ;
  assign M_AXI_DC_CDDATA[6] = \<const0> ;
  assign M_AXI_DC_CDDATA[5] = \<const0> ;
  assign M_AXI_DC_CDDATA[4] = \<const0> ;
  assign M_AXI_DC_CDDATA[3] = \<const0> ;
  assign M_AXI_DC_CDDATA[2] = \<const0> ;
  assign M_AXI_DC_CDDATA[1] = \<const0> ;
  assign M_AXI_DC_CDDATA[0] = \<const0> ;
  assign M_AXI_DC_CDLAST = \<const0> ;
  assign M_AXI_DC_CDVALID = \<const0> ;
  assign M_AXI_DC_CRRESP[4] = \<const0> ;
  assign M_AXI_DC_CRRESP[3] = \<const0> ;
  assign M_AXI_DC_CRRESP[2] = \<const0> ;
  assign M_AXI_DC_CRRESP[1] = \<const0> ;
  assign M_AXI_DC_CRRESP[0] = \<const0> ;
  assign M_AXI_DC_CRVALID = \<const0> ;
  assign M_AXI_DC_RACK = \<const0> ;
  assign M_AXI_DC_RREADY = \<const0> ;
  assign M_AXI_DC_WACK = \<const0> ;
  assign M_AXI_DC_WDATA[31] = \<const0> ;
  assign M_AXI_DC_WDATA[30] = \<const0> ;
  assign M_AXI_DC_WDATA[29] = \<const0> ;
  assign M_AXI_DC_WDATA[28] = \<const0> ;
  assign M_AXI_DC_WDATA[27] = \<const0> ;
  assign M_AXI_DC_WDATA[26] = \<const0> ;
  assign M_AXI_DC_WDATA[25] = \<const0> ;
  assign M_AXI_DC_WDATA[24] = \<const0> ;
  assign M_AXI_DC_WDATA[23] = \<const0> ;
  assign M_AXI_DC_WDATA[22] = \<const0> ;
  assign M_AXI_DC_WDATA[21] = \<const0> ;
  assign M_AXI_DC_WDATA[20] = \<const0> ;
  assign M_AXI_DC_WDATA[19] = \<const0> ;
  assign M_AXI_DC_WDATA[18] = \<const0> ;
  assign M_AXI_DC_WDATA[17] = \<const0> ;
  assign M_AXI_DC_WDATA[16] = \<const0> ;
  assign M_AXI_DC_WDATA[15] = \<const0> ;
  assign M_AXI_DC_WDATA[14] = \<const0> ;
  assign M_AXI_DC_WDATA[13] = \<const0> ;
  assign M_AXI_DC_WDATA[12] = \<const0> ;
  assign M_AXI_DC_WDATA[11] = \<const0> ;
  assign M_AXI_DC_WDATA[10] = \<const0> ;
  assign M_AXI_DC_WDATA[9] = \<const0> ;
  assign M_AXI_DC_WDATA[8] = \<const0> ;
  assign M_AXI_DC_WDATA[7] = \<const0> ;
  assign M_AXI_DC_WDATA[6] = \<const0> ;
  assign M_AXI_DC_WDATA[5] = \<const0> ;
  assign M_AXI_DC_WDATA[4] = \<const0> ;
  assign M_AXI_DC_WDATA[3] = \<const0> ;
  assign M_AXI_DC_WDATA[2] = \<const0> ;
  assign M_AXI_DC_WDATA[1] = \<const0> ;
  assign M_AXI_DC_WDATA[0] = \<const0> ;
  assign M_AXI_DC_WLAST = \<const0> ;
  assign M_AXI_DC_WSTRB[3] = \<const0> ;
  assign M_AXI_DC_WSTRB[2] = \<const0> ;
  assign M_AXI_DC_WSTRB[1] = \<const0> ;
  assign M_AXI_DC_WSTRB[0] = \<const0> ;
  assign M_AXI_DC_WUSER[0] = \<const0> ;
  assign M_AXI_DC_WVALID = \<const0> ;
  assign M_AXI_DP_ARBURST[1] = \<const0> ;
  assign M_AXI_DP_ARBURST[0] = \<const1> ;
  assign M_AXI_DP_ARCACHE[3] = \<const0> ;
  assign M_AXI_DP_ARCACHE[2] = \<const0> ;
  assign M_AXI_DP_ARCACHE[1] = \<const1> ;
  assign M_AXI_DP_ARCACHE[0] = \<const1> ;
  assign M_AXI_DP_ARID[0] = \<const0> ;
  assign M_AXI_DP_ARLEN[7] = \<const0> ;
  assign M_AXI_DP_ARLEN[6] = \<const0> ;
  assign M_AXI_DP_ARLEN[5] = \<const0> ;
  assign M_AXI_DP_ARLEN[4] = \<const0> ;
  assign M_AXI_DP_ARLEN[3] = \<const0> ;
  assign M_AXI_DP_ARLEN[2] = \<const0> ;
  assign M_AXI_DP_ARLEN[1] = \<const0> ;
  assign M_AXI_DP_ARLEN[0] = \<const0> ;
  assign M_AXI_DP_ARLOCK = \<const0> ;
  assign M_AXI_DP_ARPROT[2] = \<const0> ;
  assign M_AXI_DP_ARPROT[1] = \<const0> ;
  assign M_AXI_DP_ARPROT[0] = \<const0> ;
  assign M_AXI_DP_ARQOS[3] = \<const1> ;
  assign M_AXI_DP_ARQOS[2] = \<const0> ;
  assign M_AXI_DP_ARQOS[1] = \<const0> ;
  assign M_AXI_DP_ARQOS[0] = \<const0> ;
  assign M_AXI_DP_ARSIZE[2] = \<const0> ;
  assign M_AXI_DP_ARSIZE[1] = \<const1> ;
  assign M_AXI_DP_ARSIZE[0] = \<const0> ;
  assign M_AXI_DP_AWADDR[31:0] = M_AXI_DP_ARADDR;
  assign M_AXI_DP_AWBURST[1] = \<const0> ;
  assign M_AXI_DP_AWBURST[0] = \<const1> ;
  assign M_AXI_DP_AWCACHE[3] = \<const0> ;
  assign M_AXI_DP_AWCACHE[2] = \<const0> ;
  assign M_AXI_DP_AWCACHE[1] = \<const1> ;
  assign M_AXI_DP_AWCACHE[0] = \<const1> ;
  assign M_AXI_DP_AWID[0] = \<const0> ;
  assign M_AXI_DP_AWLEN[7] = \<const0> ;
  assign M_AXI_DP_AWLEN[6] = \<const0> ;
  assign M_AXI_DP_AWLEN[5] = \<const0> ;
  assign M_AXI_DP_AWLEN[4] = \<const0> ;
  assign M_AXI_DP_AWLEN[3] = \<const0> ;
  assign M_AXI_DP_AWLEN[2] = \<const0> ;
  assign M_AXI_DP_AWLEN[1] = \<const0> ;
  assign M_AXI_DP_AWLEN[0] = \<const0> ;
  assign M_AXI_DP_AWLOCK = \<const0> ;
  assign M_AXI_DP_AWPROT[2] = \<const0> ;
  assign M_AXI_DP_AWPROT[1] = \<const0> ;
  assign M_AXI_DP_AWPROT[0] = \<const0> ;
  assign M_AXI_DP_AWQOS[3] = \<const1> ;
  assign M_AXI_DP_AWQOS[2] = \<const0> ;
  assign M_AXI_DP_AWQOS[1] = \<const0> ;
  assign M_AXI_DP_AWQOS[0] = \<const0> ;
  assign M_AXI_DP_AWSIZE[2] = \<const0> ;
  assign M_AXI_DP_AWSIZE[1] = \<const1> ;
  assign M_AXI_DP_AWSIZE[0] = \<const0> ;
  assign M_AXI_DP_BREADY = \<const1> ;
  assign M_AXI_DP_RREADY = \<const1> ;
  assign M_AXI_DP_WLAST = \<const1> ;
  assign M_AXI_IC_ACREADY = \<const0> ;
  assign M_AXI_IC_ARADDR[31] = \<const0> ;
  assign M_AXI_IC_ARADDR[30] = \<const0> ;
  assign M_AXI_IC_ARADDR[29] = \<const0> ;
  assign M_AXI_IC_ARADDR[28] = \<const0> ;
  assign M_AXI_IC_ARADDR[27] = \<const0> ;
  assign M_AXI_IC_ARADDR[26] = \<const0> ;
  assign M_AXI_IC_ARADDR[25] = \<const0> ;
  assign M_AXI_IC_ARADDR[24] = \<const0> ;
  assign M_AXI_IC_ARADDR[23] = \<const0> ;
  assign M_AXI_IC_ARADDR[22] = \<const0> ;
  assign M_AXI_IC_ARADDR[21] = \<const0> ;
  assign M_AXI_IC_ARADDR[20] = \<const0> ;
  assign M_AXI_IC_ARADDR[19] = \<const0> ;
  assign M_AXI_IC_ARADDR[18] = \<const0> ;
  assign M_AXI_IC_ARADDR[17] = \<const0> ;
  assign M_AXI_IC_ARADDR[16] = \<const0> ;
  assign M_AXI_IC_ARADDR[15] = \<const0> ;
  assign M_AXI_IC_ARADDR[14] = \<const0> ;
  assign M_AXI_IC_ARADDR[13] = \<const0> ;
  assign M_AXI_IC_ARADDR[12] = \<const0> ;
  assign M_AXI_IC_ARADDR[11] = \<const0> ;
  assign M_AXI_IC_ARADDR[10] = \<const0> ;
  assign M_AXI_IC_ARADDR[9] = \<const0> ;
  assign M_AXI_IC_ARADDR[8] = \<const0> ;
  assign M_AXI_IC_ARADDR[7] = \<const0> ;
  assign M_AXI_IC_ARADDR[6] = \<const0> ;
  assign M_AXI_IC_ARADDR[5] = \<const0> ;
  assign M_AXI_IC_ARADDR[4] = \<const0> ;
  assign M_AXI_IC_ARADDR[3] = \<const0> ;
  assign M_AXI_IC_ARADDR[2] = \<const0> ;
  assign M_AXI_IC_ARADDR[1] = \<const0> ;
  assign M_AXI_IC_ARADDR[0] = \<const0> ;
  assign M_AXI_IC_ARBAR[1] = \<const0> ;
  assign M_AXI_IC_ARBAR[0] = \<const0> ;
  assign M_AXI_IC_ARBURST[1] = \<const0> ;
  assign M_AXI_IC_ARBURST[0] = \<const0> ;
  assign M_AXI_IC_ARCACHE[3] = \<const0> ;
  assign M_AXI_IC_ARCACHE[2] = \<const0> ;
  assign M_AXI_IC_ARCACHE[1] = \<const0> ;
  assign M_AXI_IC_ARCACHE[0] = \<const0> ;
  assign M_AXI_IC_ARDOMAIN[1] = \<const0> ;
  assign M_AXI_IC_ARDOMAIN[0] = \<const0> ;
  assign M_AXI_IC_ARID[0] = \<const0> ;
  assign M_AXI_IC_ARLEN[7] = \<const0> ;
  assign M_AXI_IC_ARLEN[6] = \<const0> ;
  assign M_AXI_IC_ARLEN[5] = \<const0> ;
  assign M_AXI_IC_ARLEN[4] = \<const0> ;
  assign M_AXI_IC_ARLEN[3] = \<const0> ;
  assign M_AXI_IC_ARLEN[2] = \<const0> ;
  assign M_AXI_IC_ARLEN[1] = \<const0> ;
  assign M_AXI_IC_ARLEN[0] = \<const0> ;
  assign M_AXI_IC_ARLOCK = \<const0> ;
  assign M_AXI_IC_ARPROT[2] = \<const0> ;
  assign M_AXI_IC_ARPROT[1] = \<const0> ;
  assign M_AXI_IC_ARPROT[0] = \<const0> ;
  assign M_AXI_IC_ARQOS[3] = \<const0> ;
  assign M_AXI_IC_ARQOS[2] = \<const0> ;
  assign M_AXI_IC_ARQOS[1] = \<const0> ;
  assign M_AXI_IC_ARQOS[0] = \<const0> ;
  assign M_AXI_IC_ARSIZE[2] = \<const0> ;
  assign M_AXI_IC_ARSIZE[1] = \<const0> ;
  assign M_AXI_IC_ARSIZE[0] = \<const0> ;
  assign M_AXI_IC_ARSNOOP[3] = \<const0> ;
  assign M_AXI_IC_ARSNOOP[2] = \<const0> ;
  assign M_AXI_IC_ARSNOOP[1] = \<const0> ;
  assign M_AXI_IC_ARSNOOP[0] = \<const0> ;
  assign M_AXI_IC_ARUSER[4] = \<const0> ;
  assign M_AXI_IC_ARUSER[3] = \<const0> ;
  assign M_AXI_IC_ARUSER[2] = \<const0> ;
  assign M_AXI_IC_ARUSER[1] = \<const0> ;
  assign M_AXI_IC_ARUSER[0] = \<const0> ;
  assign M_AXI_IC_ARVALID = \<const0> ;
  assign M_AXI_IC_AWADDR[31] = \<const0> ;
  assign M_AXI_IC_AWADDR[30] = \<const0> ;
  assign M_AXI_IC_AWADDR[29] = \<const0> ;
  assign M_AXI_IC_AWADDR[28] = \<const0> ;
  assign M_AXI_IC_AWADDR[27] = \<const0> ;
  assign M_AXI_IC_AWADDR[26] = \<const0> ;
  assign M_AXI_IC_AWADDR[25] = \<const0> ;
  assign M_AXI_IC_AWADDR[24] = \<const0> ;
  assign M_AXI_IC_AWADDR[23] = \<const0> ;
  assign M_AXI_IC_AWADDR[22] = \<const0> ;
  assign M_AXI_IC_AWADDR[21] = \<const0> ;
  assign M_AXI_IC_AWADDR[20] = \<const0> ;
  assign M_AXI_IC_AWADDR[19] = \<const0> ;
  assign M_AXI_IC_AWADDR[18] = \<const0> ;
  assign M_AXI_IC_AWADDR[17] = \<const0> ;
  assign M_AXI_IC_AWADDR[16] = \<const0> ;
  assign M_AXI_IC_AWADDR[15] = \<const0> ;
  assign M_AXI_IC_AWADDR[14] = \<const0> ;
  assign M_AXI_IC_AWADDR[13] = \<const0> ;
  assign M_AXI_IC_AWADDR[12] = \<const0> ;
  assign M_AXI_IC_AWADDR[11] = \<const0> ;
  assign M_AXI_IC_AWADDR[10] = \<const0> ;
  assign M_AXI_IC_AWADDR[9] = \<const0> ;
  assign M_AXI_IC_AWADDR[8] = \<const0> ;
  assign M_AXI_IC_AWADDR[7] = \<const0> ;
  assign M_AXI_IC_AWADDR[6] = \<const0> ;
  assign M_AXI_IC_AWADDR[5] = \<const0> ;
  assign M_AXI_IC_AWADDR[4] = \<const0> ;
  assign M_AXI_IC_AWADDR[3] = \<const0> ;
  assign M_AXI_IC_AWADDR[2] = \<const0> ;
  assign M_AXI_IC_AWADDR[1] = \<const0> ;
  assign M_AXI_IC_AWADDR[0] = \<const0> ;
  assign M_AXI_IC_AWBAR[1] = \<const0> ;
  assign M_AXI_IC_AWBAR[0] = \<const0> ;
  assign M_AXI_IC_AWBURST[1] = \<const0> ;
  assign M_AXI_IC_AWBURST[0] = \<const0> ;
  assign M_AXI_IC_AWCACHE[3] = \<const0> ;
  assign M_AXI_IC_AWCACHE[2] = \<const0> ;
  assign M_AXI_IC_AWCACHE[1] = \<const0> ;
  assign M_AXI_IC_AWCACHE[0] = \<const0> ;
  assign M_AXI_IC_AWDOMAIN[1] = \<const0> ;
  assign M_AXI_IC_AWDOMAIN[0] = \<const0> ;
  assign M_AXI_IC_AWID[0] = \<const0> ;
  assign M_AXI_IC_AWLEN[7] = \<const0> ;
  assign M_AXI_IC_AWLEN[6] = \<const0> ;
  assign M_AXI_IC_AWLEN[5] = \<const0> ;
  assign M_AXI_IC_AWLEN[4] = \<const0> ;
  assign M_AXI_IC_AWLEN[3] = \<const0> ;
  assign M_AXI_IC_AWLEN[2] = \<const0> ;
  assign M_AXI_IC_AWLEN[1] = \<const0> ;
  assign M_AXI_IC_AWLEN[0] = \<const0> ;
  assign M_AXI_IC_AWLOCK = \<const0> ;
  assign M_AXI_IC_AWPROT[2] = \<const0> ;
  assign M_AXI_IC_AWPROT[1] = \<const0> ;
  assign M_AXI_IC_AWPROT[0] = \<const0> ;
  assign M_AXI_IC_AWQOS[3] = \<const0> ;
  assign M_AXI_IC_AWQOS[2] = \<const0> ;
  assign M_AXI_IC_AWQOS[1] = \<const0> ;
  assign M_AXI_IC_AWQOS[0] = \<const0> ;
  assign M_AXI_IC_AWSIZE[2] = \<const0> ;
  assign M_AXI_IC_AWSIZE[1] = \<const0> ;
  assign M_AXI_IC_AWSIZE[0] = \<const0> ;
  assign M_AXI_IC_AWSNOOP[2] = \<const0> ;
  assign M_AXI_IC_AWSNOOP[1] = \<const0> ;
  assign M_AXI_IC_AWSNOOP[0] = \<const0> ;
  assign M_AXI_IC_AWUSER[4] = \<const0> ;
  assign M_AXI_IC_AWUSER[3] = \<const0> ;
  assign M_AXI_IC_AWUSER[2] = \<const0> ;
  assign M_AXI_IC_AWUSER[1] = \<const0> ;
  assign M_AXI_IC_AWUSER[0] = \<const0> ;
  assign M_AXI_IC_AWVALID = \<const0> ;
  assign M_AXI_IC_BREADY = \<const0> ;
  assign M_AXI_IC_CDDATA[31] = \<const0> ;
  assign M_AXI_IC_CDDATA[30] = \<const0> ;
  assign M_AXI_IC_CDDATA[29] = \<const0> ;
  assign M_AXI_IC_CDDATA[28] = \<const0> ;
  assign M_AXI_IC_CDDATA[27] = \<const0> ;
  assign M_AXI_IC_CDDATA[26] = \<const0> ;
  assign M_AXI_IC_CDDATA[25] = \<const0> ;
  assign M_AXI_IC_CDDATA[24] = \<const0> ;
  assign M_AXI_IC_CDDATA[23] = \<const0> ;
  assign M_AXI_IC_CDDATA[22] = \<const0> ;
  assign M_AXI_IC_CDDATA[21] = \<const0> ;
  assign M_AXI_IC_CDDATA[20] = \<const0> ;
  assign M_AXI_IC_CDDATA[19] = \<const0> ;
  assign M_AXI_IC_CDDATA[18] = \<const0> ;
  assign M_AXI_IC_CDDATA[17] = \<const0> ;
  assign M_AXI_IC_CDDATA[16] = \<const0> ;
  assign M_AXI_IC_CDDATA[15] = \<const0> ;
  assign M_AXI_IC_CDDATA[14] = \<const0> ;
  assign M_AXI_IC_CDDATA[13] = \<const0> ;
  assign M_AXI_IC_CDDATA[12] = \<const0> ;
  assign M_AXI_IC_CDDATA[11] = \<const0> ;
  assign M_AXI_IC_CDDATA[10] = \<const0> ;
  assign M_AXI_IC_CDDATA[9] = \<const0> ;
  assign M_AXI_IC_CDDATA[8] = \<const0> ;
  assign M_AXI_IC_CDDATA[7] = \<const0> ;
  assign M_AXI_IC_CDDATA[6] = \<const0> ;
  assign M_AXI_IC_CDDATA[5] = \<const0> ;
  assign M_AXI_IC_CDDATA[4] = \<const0> ;
  assign M_AXI_IC_CDDATA[3] = \<const0> ;
  assign M_AXI_IC_CDDATA[2] = \<const0> ;
  assign M_AXI_IC_CDDATA[1] = \<const0> ;
  assign M_AXI_IC_CDDATA[0] = \<const0> ;
  assign M_AXI_IC_CDLAST = \<const0> ;
  assign M_AXI_IC_CDVALID = \<const0> ;
  assign M_AXI_IC_CRRESP[4] = \<const0> ;
  assign M_AXI_IC_CRRESP[3] = \<const0> ;
  assign M_AXI_IC_CRRESP[2] = \<const0> ;
  assign M_AXI_IC_CRRESP[1] = \<const0> ;
  assign M_AXI_IC_CRRESP[0] = \<const0> ;
  assign M_AXI_IC_CRVALID = \<const0> ;
  assign M_AXI_IC_RACK = \<const0> ;
  assign M_AXI_IC_RREADY = \<const0> ;
  assign M_AXI_IC_WACK = \<const0> ;
  assign M_AXI_IC_WDATA[31] = \<const0> ;
  assign M_AXI_IC_WDATA[30] = \<const0> ;
  assign M_AXI_IC_WDATA[29] = \<const0> ;
  assign M_AXI_IC_WDATA[28] = \<const0> ;
  assign M_AXI_IC_WDATA[27] = \<const0> ;
  assign M_AXI_IC_WDATA[26] = \<const0> ;
  assign M_AXI_IC_WDATA[25] = \<const0> ;
  assign M_AXI_IC_WDATA[24] = \<const0> ;
  assign M_AXI_IC_WDATA[23] = \<const0> ;
  assign M_AXI_IC_WDATA[22] = \<const0> ;
  assign M_AXI_IC_WDATA[21] = \<const0> ;
  assign M_AXI_IC_WDATA[20] = \<const0> ;
  assign M_AXI_IC_WDATA[19] = \<const0> ;
  assign M_AXI_IC_WDATA[18] = \<const0> ;
  assign M_AXI_IC_WDATA[17] = \<const0> ;
  assign M_AXI_IC_WDATA[16] = \<const0> ;
  assign M_AXI_IC_WDATA[15] = \<const0> ;
  assign M_AXI_IC_WDATA[14] = \<const0> ;
  assign M_AXI_IC_WDATA[13] = \<const0> ;
  assign M_AXI_IC_WDATA[12] = \<const0> ;
  assign M_AXI_IC_WDATA[11] = \<const0> ;
  assign M_AXI_IC_WDATA[10] = \<const0> ;
  assign M_AXI_IC_WDATA[9] = \<const0> ;
  assign M_AXI_IC_WDATA[8] = \<const0> ;
  assign M_AXI_IC_WDATA[7] = \<const0> ;
  assign M_AXI_IC_WDATA[6] = \<const0> ;
  assign M_AXI_IC_WDATA[5] = \<const0> ;
  assign M_AXI_IC_WDATA[4] = \<const0> ;
  assign M_AXI_IC_WDATA[3] = \<const0> ;
  assign M_AXI_IC_WDATA[2] = \<const0> ;
  assign M_AXI_IC_WDATA[1] = \<const0> ;
  assign M_AXI_IC_WDATA[0] = \<const0> ;
  assign M_AXI_IC_WLAST = \<const0> ;
  assign M_AXI_IC_WSTRB[3] = \<const0> ;
  assign M_AXI_IC_WSTRB[2] = \<const0> ;
  assign M_AXI_IC_WSTRB[1] = \<const0> ;
  assign M_AXI_IC_WSTRB[0] = \<const0> ;
  assign M_AXI_IC_WUSER[0] = \<const0> ;
  assign M_AXI_IC_WVALID = \<const0> ;
  assign M_AXI_IP_ARADDR[31] = \<const0> ;
  assign M_AXI_IP_ARADDR[30] = \<const0> ;
  assign M_AXI_IP_ARADDR[29] = \<const0> ;
  assign M_AXI_IP_ARADDR[28] = \<const0> ;
  assign M_AXI_IP_ARADDR[27] = \<const0> ;
  assign M_AXI_IP_ARADDR[26] = \<const0> ;
  assign M_AXI_IP_ARADDR[25] = \<const0> ;
  assign M_AXI_IP_ARADDR[24] = \<const0> ;
  assign M_AXI_IP_ARADDR[23] = \<const0> ;
  assign M_AXI_IP_ARADDR[22] = \<const0> ;
  assign M_AXI_IP_ARADDR[21] = \<const0> ;
  assign M_AXI_IP_ARADDR[20] = \<const0> ;
  assign M_AXI_IP_ARADDR[19] = \<const0> ;
  assign M_AXI_IP_ARADDR[18] = \<const0> ;
  assign M_AXI_IP_ARADDR[17] = \<const0> ;
  assign M_AXI_IP_ARADDR[16] = \<const0> ;
  assign M_AXI_IP_ARADDR[15] = \<const0> ;
  assign M_AXI_IP_ARADDR[14] = \<const0> ;
  assign M_AXI_IP_ARADDR[13] = \<const0> ;
  assign M_AXI_IP_ARADDR[12] = \<const0> ;
  assign M_AXI_IP_ARADDR[11] = \<const0> ;
  assign M_AXI_IP_ARADDR[10] = \<const0> ;
  assign M_AXI_IP_ARADDR[9] = \<const0> ;
  assign M_AXI_IP_ARADDR[8] = \<const0> ;
  assign M_AXI_IP_ARADDR[7] = \<const0> ;
  assign M_AXI_IP_ARADDR[6] = \<const0> ;
  assign M_AXI_IP_ARADDR[5] = \<const0> ;
  assign M_AXI_IP_ARADDR[4] = \<const0> ;
  assign M_AXI_IP_ARADDR[3] = \<const0> ;
  assign M_AXI_IP_ARADDR[2] = \<const0> ;
  assign M_AXI_IP_ARADDR[1] = \<const0> ;
  assign M_AXI_IP_ARADDR[0] = \<const0> ;
  assign M_AXI_IP_ARBURST[1] = \<const0> ;
  assign M_AXI_IP_ARBURST[0] = \<const0> ;
  assign M_AXI_IP_ARCACHE[3] = \<const0> ;
  assign M_AXI_IP_ARCACHE[2] = \<const0> ;
  assign M_AXI_IP_ARCACHE[1] = \<const0> ;
  assign M_AXI_IP_ARCACHE[0] = \<const0> ;
  assign M_AXI_IP_ARID[0] = \<const0> ;
  assign M_AXI_IP_ARLEN[7] = \<const0> ;
  assign M_AXI_IP_ARLEN[6] = \<const0> ;
  assign M_AXI_IP_ARLEN[5] = \<const0> ;
  assign M_AXI_IP_ARLEN[4] = \<const0> ;
  assign M_AXI_IP_ARLEN[3] = \<const0> ;
  assign M_AXI_IP_ARLEN[2] = \<const0> ;
  assign M_AXI_IP_ARLEN[1] = \<const0> ;
  assign M_AXI_IP_ARLEN[0] = \<const0> ;
  assign M_AXI_IP_ARLOCK = \<const0> ;
  assign M_AXI_IP_ARPROT[2] = \<const0> ;
  assign M_AXI_IP_ARPROT[1] = \<const0> ;
  assign M_AXI_IP_ARPROT[0] = \<const0> ;
  assign M_AXI_IP_ARQOS[3] = \<const0> ;
  assign M_AXI_IP_ARQOS[2] = \<const0> ;
  assign M_AXI_IP_ARQOS[1] = \<const0> ;
  assign M_AXI_IP_ARQOS[0] = \<const0> ;
  assign M_AXI_IP_ARSIZE[2] = \<const0> ;
  assign M_AXI_IP_ARSIZE[1] = \<const0> ;
  assign M_AXI_IP_ARSIZE[0] = \<const0> ;
  assign M_AXI_IP_ARVALID = \<const0> ;
  assign M_AXI_IP_AWADDR[31] = \<const0> ;
  assign M_AXI_IP_AWADDR[30] = \<const0> ;
  assign M_AXI_IP_AWADDR[29] = \<const0> ;
  assign M_AXI_IP_AWADDR[28] = \<const0> ;
  assign M_AXI_IP_AWADDR[27] = \<const0> ;
  assign M_AXI_IP_AWADDR[26] = \<const0> ;
  assign M_AXI_IP_AWADDR[25] = \<const0> ;
  assign M_AXI_IP_AWADDR[24] = \<const0> ;
  assign M_AXI_IP_AWADDR[23] = \<const0> ;
  assign M_AXI_IP_AWADDR[22] = \<const0> ;
  assign M_AXI_IP_AWADDR[21] = \<const0> ;
  assign M_AXI_IP_AWADDR[20] = \<const0> ;
  assign M_AXI_IP_AWADDR[19] = \<const0> ;
  assign M_AXI_IP_AWADDR[18] = \<const0> ;
  assign M_AXI_IP_AWADDR[17] = \<const0> ;
  assign M_AXI_IP_AWADDR[16] = \<const0> ;
  assign M_AXI_IP_AWADDR[15] = \<const0> ;
  assign M_AXI_IP_AWADDR[14] = \<const0> ;
  assign M_AXI_IP_AWADDR[13] = \<const0> ;
  assign M_AXI_IP_AWADDR[12] = \<const0> ;
  assign M_AXI_IP_AWADDR[11] = \<const0> ;
  assign M_AXI_IP_AWADDR[10] = \<const0> ;
  assign M_AXI_IP_AWADDR[9] = \<const0> ;
  assign M_AXI_IP_AWADDR[8] = \<const0> ;
  assign M_AXI_IP_AWADDR[7] = \<const0> ;
  assign M_AXI_IP_AWADDR[6] = \<const0> ;
  assign M_AXI_IP_AWADDR[5] = \<const0> ;
  assign M_AXI_IP_AWADDR[4] = \<const0> ;
  assign M_AXI_IP_AWADDR[3] = \<const0> ;
  assign M_AXI_IP_AWADDR[2] = \<const0> ;
  assign M_AXI_IP_AWADDR[1] = \<const0> ;
  assign M_AXI_IP_AWADDR[0] = \<const0> ;
  assign M_AXI_IP_AWBURST[1] = \<const0> ;
  assign M_AXI_IP_AWBURST[0] = \<const0> ;
  assign M_AXI_IP_AWCACHE[3] = \<const0> ;
  assign M_AXI_IP_AWCACHE[2] = \<const0> ;
  assign M_AXI_IP_AWCACHE[1] = \<const0> ;
  assign M_AXI_IP_AWCACHE[0] = \<const0> ;
  assign M_AXI_IP_AWID[0] = \<const0> ;
  assign M_AXI_IP_AWLEN[7] = \<const0> ;
  assign M_AXI_IP_AWLEN[6] = \<const0> ;
  assign M_AXI_IP_AWLEN[5] = \<const0> ;
  assign M_AXI_IP_AWLEN[4] = \<const0> ;
  assign M_AXI_IP_AWLEN[3] = \<const0> ;
  assign M_AXI_IP_AWLEN[2] = \<const0> ;
  assign M_AXI_IP_AWLEN[1] = \<const0> ;
  assign M_AXI_IP_AWLEN[0] = \<const0> ;
  assign M_AXI_IP_AWLOCK = \<const0> ;
  assign M_AXI_IP_AWPROT[2] = \<const0> ;
  assign M_AXI_IP_AWPROT[1] = \<const0> ;
  assign M_AXI_IP_AWPROT[0] = \<const0> ;
  assign M_AXI_IP_AWQOS[3] = \<const0> ;
  assign M_AXI_IP_AWQOS[2] = \<const0> ;
  assign M_AXI_IP_AWQOS[1] = \<const0> ;
  assign M_AXI_IP_AWQOS[0] = \<const0> ;
  assign M_AXI_IP_AWSIZE[2] = \<const0> ;
  assign M_AXI_IP_AWSIZE[1] = \<const0> ;
  assign M_AXI_IP_AWSIZE[0] = \<const0> ;
  assign M_AXI_IP_AWVALID = \<const0> ;
  assign M_AXI_IP_BREADY = \<const0> ;
  assign M_AXI_IP_RREADY = \<const0> ;
  assign M_AXI_IP_WDATA[31] = \<const0> ;
  assign M_AXI_IP_WDATA[30] = \<const0> ;
  assign M_AXI_IP_WDATA[29] = \<const0> ;
  assign M_AXI_IP_WDATA[28] = \<const0> ;
  assign M_AXI_IP_WDATA[27] = \<const0> ;
  assign M_AXI_IP_WDATA[26] = \<const0> ;
  assign M_AXI_IP_WDATA[25] = \<const0> ;
  assign M_AXI_IP_WDATA[24] = \<const0> ;
  assign M_AXI_IP_WDATA[23] = \<const0> ;
  assign M_AXI_IP_WDATA[22] = \<const0> ;
  assign M_AXI_IP_WDATA[21] = \<const0> ;
  assign M_AXI_IP_WDATA[20] = \<const0> ;
  assign M_AXI_IP_WDATA[19] = \<const0> ;
  assign M_AXI_IP_WDATA[18] = \<const0> ;
  assign M_AXI_IP_WDATA[17] = \<const0> ;
  assign M_AXI_IP_WDATA[16] = \<const0> ;
  assign M_AXI_IP_WDATA[15] = \<const0> ;
  assign M_AXI_IP_WDATA[14] = \<const0> ;
  assign M_AXI_IP_WDATA[13] = \<const0> ;
  assign M_AXI_IP_WDATA[12] = \<const0> ;
  assign M_AXI_IP_WDATA[11] = \<const0> ;
  assign M_AXI_IP_WDATA[10] = \<const0> ;
  assign M_AXI_IP_WDATA[9] = \<const0> ;
  assign M_AXI_IP_WDATA[8] = \<const0> ;
  assign M_AXI_IP_WDATA[7] = \<const0> ;
  assign M_AXI_IP_WDATA[6] = \<const0> ;
  assign M_AXI_IP_WDATA[5] = \<const0> ;
  assign M_AXI_IP_WDATA[4] = \<const0> ;
  assign M_AXI_IP_WDATA[3] = \<const0> ;
  assign M_AXI_IP_WDATA[2] = \<const0> ;
  assign M_AXI_IP_WDATA[1] = \<const0> ;
  assign M_AXI_IP_WDATA[0] = \<const0> ;
  assign M_AXI_IP_WLAST = \<const0> ;
  assign M_AXI_IP_WSTRB[3] = \<const0> ;
  assign M_AXI_IP_WSTRB[2] = \<const0> ;
  assign M_AXI_IP_WSTRB[1] = \<const0> ;
  assign M_AXI_IP_WSTRB[0] = \<const0> ;
  assign M_AXI_IP_WVALID = \<const0> ;
  assign RAM_From[255] = \<const0> ;
  assign RAM_From[254] = \<const0> ;
  assign RAM_From[253] = \<const0> ;
  assign RAM_From[252] = \<const0> ;
  assign RAM_From[251] = \<const0> ;
  assign RAM_From[250] = \<const0> ;
  assign RAM_From[249] = \<const0> ;
  assign RAM_From[248] = \<const0> ;
  assign RAM_From[247] = \<const0> ;
  assign RAM_From[246] = \<const0> ;
  assign RAM_From[245] = \<const0> ;
  assign RAM_From[244] = \<const0> ;
  assign RAM_From[243] = \<const0> ;
  assign RAM_From[242] = \<const0> ;
  assign RAM_From[241] = \<const0> ;
  assign RAM_From[240] = \<const0> ;
  assign RAM_From[239] = \<const0> ;
  assign RAM_From[238] = \<const0> ;
  assign RAM_From[237] = \<const0> ;
  assign RAM_From[236] = \<const0> ;
  assign RAM_From[235] = \<const0> ;
  assign RAM_From[234] = \<const0> ;
  assign RAM_From[233] = \<const0> ;
  assign RAM_From[232] = \<const0> ;
  assign RAM_From[231] = \<const0> ;
  assign RAM_From[230] = \<const0> ;
  assign RAM_From[229] = \<const0> ;
  assign RAM_From[228] = \<const0> ;
  assign RAM_From[227] = \<const0> ;
  assign RAM_From[226] = \<const0> ;
  assign RAM_From[225] = \<const0> ;
  assign RAM_From[224] = \<const0> ;
  assign RAM_From[223] = \<const0> ;
  assign RAM_From[222] = \<const0> ;
  assign RAM_From[221] = \<const0> ;
  assign RAM_From[220] = \<const0> ;
  assign RAM_From[219] = \<const0> ;
  assign RAM_From[218] = \<const0> ;
  assign RAM_From[217] = \<const0> ;
  assign RAM_From[216] = \<const0> ;
  assign RAM_From[215] = \<const0> ;
  assign RAM_From[214] = \<const0> ;
  assign RAM_From[213] = \<const0> ;
  assign RAM_From[212] = \<const0> ;
  assign RAM_From[211] = \<const0> ;
  assign RAM_From[210] = \<const0> ;
  assign RAM_From[209] = \<const0> ;
  assign RAM_From[208] = \<const0> ;
  assign RAM_From[207] = \<const0> ;
  assign RAM_From[206] = \<const0> ;
  assign RAM_From[205] = \<const0> ;
  assign RAM_From[204] = \<const0> ;
  assign RAM_From[203] = \<const0> ;
  assign RAM_From[202] = \<const0> ;
  assign RAM_From[201] = \<const0> ;
  assign RAM_From[200] = \<const0> ;
  assign RAM_From[199] = \<const0> ;
  assign RAM_From[198] = \<const0> ;
  assign RAM_From[197] = \<const0> ;
  assign RAM_From[196] = \<const0> ;
  assign RAM_From[195] = \<const0> ;
  assign RAM_From[194] = \<const0> ;
  assign RAM_From[193] = \<const0> ;
  assign RAM_From[192] = \<const0> ;
  assign RAM_From[191] = \<const0> ;
  assign RAM_From[190] = \<const0> ;
  assign RAM_From[189] = \<const0> ;
  assign RAM_From[188] = \<const0> ;
  assign RAM_From[187] = \<const0> ;
  assign RAM_From[186] = \<const0> ;
  assign RAM_From[185] = \<const0> ;
  assign RAM_From[184] = \<const0> ;
  assign RAM_From[183] = \<const0> ;
  assign RAM_From[182] = \<const0> ;
  assign RAM_From[181] = \<const0> ;
  assign RAM_From[180] = \<const0> ;
  assign RAM_From[179] = \<const0> ;
  assign RAM_From[178] = \<const0> ;
  assign RAM_From[177] = \<const0> ;
  assign RAM_From[176] = \<const0> ;
  assign RAM_From[175] = \<const0> ;
  assign RAM_From[174] = \<const0> ;
  assign RAM_From[173] = \<const0> ;
  assign RAM_From[172] = \<const0> ;
  assign RAM_From[171] = \<const0> ;
  assign RAM_From[170] = \<const0> ;
  assign RAM_From[169] = \<const0> ;
  assign RAM_From[168] = \<const0> ;
  assign RAM_From[167] = \<const0> ;
  assign RAM_From[166] = \<const0> ;
  assign RAM_From[165] = \<const0> ;
  assign RAM_From[164] = \<const0> ;
  assign RAM_From[163] = \<const0> ;
  assign RAM_From[162] = \<const0> ;
  assign RAM_From[161] = \<const0> ;
  assign RAM_From[160] = \<const0> ;
  assign RAM_From[159] = \<const0> ;
  assign RAM_From[158] = \<const0> ;
  assign RAM_From[157] = \<const0> ;
  assign RAM_From[156] = \<const0> ;
  assign RAM_From[155] = \<const0> ;
  assign RAM_From[154] = \<const0> ;
  assign RAM_From[153] = \<const0> ;
  assign RAM_From[152] = \<const0> ;
  assign RAM_From[151] = \<const0> ;
  assign RAM_From[150] = \<const0> ;
  assign RAM_From[149] = \<const0> ;
  assign RAM_From[148] = \<const0> ;
  assign RAM_From[147] = \<const0> ;
  assign RAM_From[146] = \<const0> ;
  assign RAM_From[145] = \<const0> ;
  assign RAM_From[144] = \<const0> ;
  assign RAM_From[143] = \<const0> ;
  assign RAM_From[142] = \<const0> ;
  assign RAM_From[141] = \<const0> ;
  assign RAM_From[140] = \<const0> ;
  assign RAM_From[139] = \<const0> ;
  assign RAM_From[138] = \<const0> ;
  assign RAM_From[137] = \<const0> ;
  assign RAM_From[136] = \<const0> ;
  assign RAM_From[135] = \<const0> ;
  assign RAM_From[134] = \<const0> ;
  assign RAM_From[133] = \<const0> ;
  assign RAM_From[132] = \<const0> ;
  assign RAM_From[131] = \<const0> ;
  assign RAM_From[130] = \<const0> ;
  assign RAM_From[129] = \<const0> ;
  assign RAM_From[128] = \<const0> ;
  assign RAM_From[127] = \<const0> ;
  assign RAM_From[126] = \<const0> ;
  assign RAM_From[125] = \<const0> ;
  assign RAM_From[124] = \<const0> ;
  assign RAM_From[123] = \<const0> ;
  assign RAM_From[122] = \<const0> ;
  assign RAM_From[121] = \<const0> ;
  assign RAM_From[120] = \<const0> ;
  assign RAM_From[119] = \<const0> ;
  assign RAM_From[118] = \<const0> ;
  assign RAM_From[117] = \<const0> ;
  assign RAM_From[116] = \<const0> ;
  assign RAM_From[115] = \<const0> ;
  assign RAM_From[114] = \<const0> ;
  assign RAM_From[113] = \<const0> ;
  assign RAM_From[112] = \<const0> ;
  assign RAM_From[111] = \<const0> ;
  assign RAM_From[110] = \<const0> ;
  assign RAM_From[109] = \<const0> ;
  assign RAM_From[108] = \<const0> ;
  assign RAM_From[107] = \<const0> ;
  assign RAM_From[106] = \<const0> ;
  assign RAM_From[105] = \<const0> ;
  assign RAM_From[104] = \<const0> ;
  assign RAM_From[103] = \<const0> ;
  assign RAM_From[102] = \<const0> ;
  assign RAM_From[101] = \<const0> ;
  assign RAM_From[100] = \<const0> ;
  assign RAM_From[99] = \<const0> ;
  assign RAM_From[98] = \<const0> ;
  assign RAM_From[97] = \<const0> ;
  assign RAM_From[96] = \<const0> ;
  assign RAM_From[95] = \<const0> ;
  assign RAM_From[94] = \<const0> ;
  assign RAM_From[93] = \<const0> ;
  assign RAM_From[92] = \<const0> ;
  assign RAM_From[91] = \<const0> ;
  assign RAM_From[90] = \<const0> ;
  assign RAM_From[89] = \<const0> ;
  assign RAM_From[88] = \<const0> ;
  assign RAM_From[87] = \<const0> ;
  assign RAM_From[86] = \<const0> ;
  assign RAM_From[85] = \<const0> ;
  assign RAM_From[84] = \<const0> ;
  assign RAM_From[83] = \<const0> ;
  assign RAM_From[82] = \<const0> ;
  assign RAM_From[81] = \<const0> ;
  assign RAM_From[80] = \<const0> ;
  assign RAM_From[79] = \<const0> ;
  assign RAM_From[78] = \<const0> ;
  assign RAM_From[77] = \<const0> ;
  assign RAM_From[76] = \<const0> ;
  assign RAM_From[75] = \<const0> ;
  assign RAM_From[74] = \<const0> ;
  assign RAM_From[73] = \<const0> ;
  assign RAM_From[72] = \<const0> ;
  assign RAM_From[71] = \<const0> ;
  assign RAM_From[70] = \<const0> ;
  assign RAM_From[69] = \<const0> ;
  assign RAM_From[68] = \<const0> ;
  assign RAM_From[67] = \<const0> ;
  assign RAM_From[66] = \<const0> ;
  assign RAM_From[65] = \<const0> ;
  assign RAM_From[64] = \<const0> ;
  assign RAM_From[63] = \<const0> ;
  assign RAM_From[62] = \<const0> ;
  assign RAM_From[61] = \<const0> ;
  assign RAM_From[60] = \<const0> ;
  assign RAM_From[59] = \<const0> ;
  assign RAM_From[58] = \<const0> ;
  assign RAM_From[57] = \<const0> ;
  assign RAM_From[56] = \<const0> ;
  assign RAM_From[55] = \<const0> ;
  assign RAM_From[54] = \<const0> ;
  assign RAM_From[53] = \<const0> ;
  assign RAM_From[52] = \<const0> ;
  assign RAM_From[51] = \<const0> ;
  assign RAM_From[50] = \<const0> ;
  assign RAM_From[49] = \<const0> ;
  assign RAM_From[48] = \<const0> ;
  assign RAM_From[47] = \<const0> ;
  assign RAM_From[46] = \<const0> ;
  assign RAM_From[45] = \<const0> ;
  assign RAM_From[44] = \<const0> ;
  assign RAM_From[43] = \<const0> ;
  assign RAM_From[42] = \<const0> ;
  assign RAM_From[41] = \<const0> ;
  assign RAM_From[40] = \<const0> ;
  assign RAM_From[39] = \<const0> ;
  assign RAM_From[38] = \<const0> ;
  assign RAM_From[37] = \<const0> ;
  assign RAM_From[36] = \<const0> ;
  assign RAM_From[35] = \<const0> ;
  assign RAM_From[34] = \<const0> ;
  assign RAM_From[33] = \<const0> ;
  assign RAM_From[32] = \<const0> ;
  assign RAM_From[31] = \<const0> ;
  assign RAM_From[30] = \<const0> ;
  assign RAM_From[29] = \<const0> ;
  assign RAM_From[28] = \<const0> ;
  assign RAM_From[27] = \<const0> ;
  assign RAM_From[26] = \<const0> ;
  assign RAM_From[25] = \<const0> ;
  assign RAM_From[24] = \<const0> ;
  assign RAM_From[23] = \<const0> ;
  assign RAM_From[22] = \<const0> ;
  assign RAM_From[21] = \<const0> ;
  assign RAM_From[20] = \<const0> ;
  assign RAM_From[19] = \<const0> ;
  assign RAM_From[18] = \<const0> ;
  assign RAM_From[17] = \<const0> ;
  assign RAM_From[16] = \<const0> ;
  assign RAM_From[15] = \<const0> ;
  assign RAM_From[14] = \<const0> ;
  assign RAM_From[13] = \<const0> ;
  assign RAM_From[12] = \<const0> ;
  assign RAM_From[11] = \<const0> ;
  assign RAM_From[10] = \<const0> ;
  assign RAM_From[9] = \<const0> ;
  assign RAM_From[8] = \<const0> ;
  assign RAM_From[7] = \<const0> ;
  assign RAM_From[6] = \<const0> ;
  assign RAM_From[5] = \<const0> ;
  assign RAM_From[4] = \<const0> ;
  assign RAM_From[3] = \<const0> ;
  assign RAM_From[2] = \<const0> ;
  assign RAM_From[1] = \<const0> ;
  assign RAM_From[0] = \<const0> ;
  assign S0_AXIS_TREADY = \<const0> ;
  assign S10_AXIS_TREADY = \<const0> ;
  assign S11_AXIS_TREADY = \<const0> ;
  assign S12_AXIS_TREADY = \<const0> ;
  assign S13_AXIS_TREADY = \<const0> ;
  assign S14_AXIS_TREADY = \<const0> ;
  assign S15_AXIS_TREADY = \<const0> ;
  assign S1_AXIS_TREADY = \<const0> ;
  assign S2_AXIS_TREADY = \<const0> ;
  assign S3_AXIS_TREADY = \<const0> ;
  assign S4_AXIS_TREADY = \<const0> ;
  assign S5_AXIS_TREADY = \<const0> ;
  assign S6_AXIS_TREADY = \<const0> ;
  assign S7_AXIS_TREADY = \<const0> ;
  assign S8_AXIS_TREADY = \<const0> ;
  assign S9_AXIS_TREADY = \<const0> ;
  assign Trace_DCache_Hit = \<const0> ;
  assign Trace_DCache_Rdy = \<const0> ;
  assign Trace_DCache_Read = \<const0> ;
  assign Trace_DCache_Req = \<const0> ;
  assign Trace_Exception_Kind[0] = \<const0> ;
  assign Trace_Exception_Kind[1] = \^Trace_Exception_Kind [1];
  assign Trace_Exception_Kind[2] = \<const0> ;
  assign Trace_Exception_Kind[3] = \<const0> ;
  assign Trace_Exception_Kind[4] = \^Trace_Exception_Kind [4];
  assign Trace_ICache_Hit = \<const0> ;
  assign Trace_ICache_Rdy = \<const0> ;
  assign Trace_ICache_Req = \<const0> ;
  assign Trace_Jump_Hit = \<const0> ;
  assign Trace_MB_Halted = \^LOCKSTEP_Master_Out [10];
  assign Trace_MSR_Reg[0] = \<const0> ;
  assign Trace_MSR_Reg[1] = \<const0> ;
  assign Trace_MSR_Reg[2] = \<const0> ;
  assign Trace_MSR_Reg[3] = \<const0> ;
  assign Trace_MSR_Reg[4] = \<const0> ;
  assign Trace_MSR_Reg[5] = \<const0> ;
  assign Trace_MSR_Reg[6] = \<const0> ;
  assign Trace_MSR_Reg[7] = \<const0> ;
  assign Trace_MSR_Reg[8] = \<const0> ;
  assign Trace_MSR_Reg[9] = \<const0> ;
  assign Trace_MSR_Reg[10] = \<const0> ;
  assign Trace_MSR_Reg[11:13] = \^Trace_MSR_Reg [11:13];
  assign Trace_MSR_Reg[14] = \<const0> ;
  assign Trace_PID_Reg[0] = \<const0> ;
  assign Trace_PID_Reg[1] = \<const0> ;
  assign Trace_PID_Reg[2] = \<const0> ;
  assign Trace_PID_Reg[3] = \<const0> ;
  assign Trace_PID_Reg[4] = \<const0> ;
  assign Trace_PID_Reg[5] = \<const0> ;
  assign Trace_PID_Reg[6] = \<const0> ;
  assign Trace_PID_Reg[7] = \<const0> ;
  LUT5 #(
    .INIT(32'h00000040)) 
    Dbg_TDO_INST_0_i_1
       (.I0(MicroBlaze_Core_I_n_411),
        .I1(Dbg_Reg_En[6]),
        .I2(Dbg_Reg_En[7]),
        .I3(Dbg_Reg_En[4]),
        .I4(Dbg_Reg_En[5]),
        .O(\Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Status_Reg_En ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    Dbg_TDO_INST_0_i_11
       (.I0(Dbg_Reg_En[7]),
        .I1(Dbg_Reg_En[4]),
        .I2(Dbg_Reg_En[0]),
        .I3(Dbg_Reg_En[2]),
        .O(Dbg_TDO_INST_0_i_11_n_0));
  LUT5 #(
    .INIT(32'h00004000)) 
    Dbg_TDO_INST_0_i_14
       (.I0(Dbg_Reg_En[1]),
        .I1(Dbg_Reg_En[6]),
        .I2(Dbg_Reg_En[5]),
        .I3(Dbg_Reg_En[7]),
        .I4(Dbg_TDO_INST_0_i_26_n_0),
        .O(Config_Reg_En));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    Dbg_TDO_INST_0_i_26
       (.I0(Dbg_Reg_En[3]),
        .I1(Dbg_Reg_En[4]),
        .I2(Dbg_Reg_En[0]),
        .I3(Dbg_Reg_En[2]),
        .O(Dbg_TDO_INST_0_i_26_n_0));
  LUT5 #(
    .INIT(32'h00001000)) 
    Dbg_TDO_INST_0_i_4
       (.I0(Dbg_Reg_En[1]),
        .I1(Dbg_Reg_En[3]),
        .I2(Dbg_Reg_En[5]),
        .I3(Dbg_Reg_En[6]),
        .I4(Dbg_TDO_INST_0_i_11_n_0),
        .O(Data_Read_Reg_En));
  GND GND
       (.G(\<const0> ));
  FDRE \LOCKSTEP_Out_reg[0] 
       (.C(Clk),
        .CE(1'b1),
        .D(\^LOCKSTEP_Master_Out [10]),
        .Q(\^LOCKSTEP_Out [3228]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[10] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[6]),
        .Q(\^LOCKSTEP_Out [10]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[11] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[7]),
        .Q(\^LOCKSTEP_Out [11]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[12] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[8]),
        .Q(\^LOCKSTEP_Out [12]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[132] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[0]),
        .Q(\^LOCKSTEP_Out [132]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[133] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[1]),
        .Q(\^LOCKSTEP_Out [133]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[134] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[2]),
        .Q(\^LOCKSTEP_Out [134]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[135] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[3]),
        .Q(\^LOCKSTEP_Out [135]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[136] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[4]),
        .Q(\^LOCKSTEP_Out [136]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[137] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[5]),
        .Q(\^LOCKSTEP_Out [137]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[138] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[6]),
        .Q(\^LOCKSTEP_Out [138]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[139] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[7]),
        .Q(\^LOCKSTEP_Out [139]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[13] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[9]),
        .Q(\^LOCKSTEP_Out [13]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[140] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[8]),
        .Q(\^LOCKSTEP_Out [140]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[141] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[9]),
        .Q(\^LOCKSTEP_Out [141]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[142] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[10]),
        .Q(\^LOCKSTEP_Out [142]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[143] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[11]),
        .Q(\^LOCKSTEP_Out [143]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[144] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[12]),
        .Q(\^LOCKSTEP_Out [144]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[145] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[13]),
        .Q(\^LOCKSTEP_Out [145]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[146] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[14]),
        .Q(\^LOCKSTEP_Out [146]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[147] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[15]),
        .Q(\^LOCKSTEP_Out [147]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[148] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[16]),
        .Q(\^LOCKSTEP_Out [148]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[149] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[17]),
        .Q(\^LOCKSTEP_Out [149]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[14] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[10]),
        .Q(\^LOCKSTEP_Out [14]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[150] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[18]),
        .Q(\^LOCKSTEP_Out [150]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[151] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[19]),
        .Q(\^LOCKSTEP_Out [151]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[152] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[20]),
        .Q(\^LOCKSTEP_Out [152]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[153] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[21]),
        .Q(\^LOCKSTEP_Out [153]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[154] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[22]),
        .Q(\^LOCKSTEP_Out [154]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[155] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[23]),
        .Q(\^LOCKSTEP_Out [155]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[156] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[24]),
        .Q(\^LOCKSTEP_Out [156]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[157] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[25]),
        .Q(\^LOCKSTEP_Out [157]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[158] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[26]),
        .Q(\^LOCKSTEP_Out [158]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[159] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[27]),
        .Q(\^LOCKSTEP_Out [159]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[15] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[11]),
        .Q(\^LOCKSTEP_Out [15]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[160] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[28]),
        .Q(\^LOCKSTEP_Out [160]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[161] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[29]),
        .Q(\^LOCKSTEP_Out [161]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[162] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[30]),
        .Q(\^LOCKSTEP_Out [162]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[163] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Write[31]),
        .Q(\^LOCKSTEP_Out [163]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[16] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[12]),
        .Q(\^LOCKSTEP_Out [16]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[17] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[13]),
        .Q(\^LOCKSTEP_Out [17]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[18] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[14]),
        .Q(\^LOCKSTEP_Out [18]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[196] 
       (.C(Clk),
        .CE(1'b1),
        .D(D_AS),
        .Q(\^LOCKSTEP_Out [196]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[197] 
       (.C(Clk),
        .CE(1'b1),
        .D(Read_Strobe),
        .Q(\^LOCKSTEP_Out [197]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[198] 
       (.C(Clk),
        .CE(1'b1),
        .D(Write_Strobe),
        .Q(\^LOCKSTEP_Out [198]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[199] 
       (.C(Clk),
        .CE(1'b1),
        .D(Byte_Enable[0]),
        .Q(\^LOCKSTEP_Out [199]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[19] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[15]),
        .Q(\^LOCKSTEP_Out [19]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[200] 
       (.C(Clk),
        .CE(1'b1),
        .D(Byte_Enable[1]),
        .Q(\^LOCKSTEP_Out [200]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[201] 
       (.C(Clk),
        .CE(1'b1),
        .D(Byte_Enable[2]),
        .Q(\^LOCKSTEP_Out [201]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[202] 
       (.C(Clk),
        .CE(1'b1),
        .D(Byte_Enable[3]),
        .Q(\^LOCKSTEP_Out [202]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[20] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[16]),
        .Q(\^LOCKSTEP_Out [20]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[21] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[17]),
        .Q(\^LOCKSTEP_Out [21]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[22] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[18]),
        .Q(\^LOCKSTEP_Out [22]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[23] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[19]),
        .Q(\^LOCKSTEP_Out [23]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[24] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[20]),
        .Q(\^LOCKSTEP_Out [24]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[25] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[21]),
        .Q(\^LOCKSTEP_Out [25]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[26] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[22]),
        .Q(\^LOCKSTEP_Out [26]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[27] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[23]),
        .Q(\^LOCKSTEP_Out [27]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2881] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[0]),
        .Q(\^LOCKSTEP_Out [2881]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2882] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[1]),
        .Q(\^LOCKSTEP_Out [2882]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2883] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[2]),
        .Q(\^LOCKSTEP_Out [2883]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2884] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[3]),
        .Q(\^LOCKSTEP_Out [2884]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2885] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[4]),
        .Q(\^LOCKSTEP_Out [2885]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2886] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[5]),
        .Q(\^LOCKSTEP_Out [2886]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2887] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[6]),
        .Q(\^LOCKSTEP_Out [2887]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2888] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[7]),
        .Q(\^LOCKSTEP_Out [2888]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2889] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[8]),
        .Q(\^LOCKSTEP_Out [2889]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2890] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[9]),
        .Q(\^LOCKSTEP_Out [2890]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2891] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[10]),
        .Q(\^LOCKSTEP_Out [2891]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2892] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[11]),
        .Q(\^LOCKSTEP_Out [2892]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2893] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[12]),
        .Q(\^LOCKSTEP_Out [2893]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2894] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[13]),
        .Q(\^LOCKSTEP_Out [2894]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2895] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[14]),
        .Q(\^LOCKSTEP_Out [2895]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2896] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[15]),
        .Q(\^LOCKSTEP_Out [2896]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2897] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[16]),
        .Q(\^LOCKSTEP_Out [2897]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2898] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[17]),
        .Q(\^LOCKSTEP_Out [2898]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2899] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[18]),
        .Q(\^LOCKSTEP_Out [2899]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[28] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[24]),
        .Q(\^LOCKSTEP_Out [28]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2900] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[19]),
        .Q(\^LOCKSTEP_Out [2900]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2901] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[20]),
        .Q(\^LOCKSTEP_Out [2901]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2902] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[21]),
        .Q(\^LOCKSTEP_Out [2902]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2903] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[22]),
        .Q(\^LOCKSTEP_Out [2903]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2904] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[23]),
        .Q(\^LOCKSTEP_Out [2904]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2905] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[24]),
        .Q(\^LOCKSTEP_Out [2905]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2906] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[25]),
        .Q(\^LOCKSTEP_Out [2906]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2907] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[26]),
        .Q(\^LOCKSTEP_Out [2907]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2908] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[27]),
        .Q(\^LOCKSTEP_Out [2908]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2909] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[28]),
        .Q(\^LOCKSTEP_Out [2909]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2910] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[29]),
        .Q(\^LOCKSTEP_Out [2910]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2911] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[30]),
        .Q(\^LOCKSTEP_Out [2911]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2912] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Instruction[31]),
        .Q(\^LOCKSTEP_Out [2912]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2913] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Valid_Instr),
        .Q(\^LOCKSTEP_Out [2913]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2914] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[0]),
        .Q(\^LOCKSTEP_Out [2914]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2915] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[1]),
        .Q(\^LOCKSTEP_Out [2915]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2916] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[2]),
        .Q(\^LOCKSTEP_Out [2916]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2917] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[3]),
        .Q(\^LOCKSTEP_Out [2917]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2918] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[4]),
        .Q(\^LOCKSTEP_Out [2918]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2919] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[5]),
        .Q(\^LOCKSTEP_Out [2919]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2920] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[6]),
        .Q(\^LOCKSTEP_Out [2920]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2921] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[7]),
        .Q(\^LOCKSTEP_Out [2921]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2922] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[8]),
        .Q(\^LOCKSTEP_Out [2922]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2923] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[9]),
        .Q(\^LOCKSTEP_Out [2923]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2924] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[10]),
        .Q(\^LOCKSTEP_Out [2924]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2925] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[11]),
        .Q(\^LOCKSTEP_Out [2925]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2926] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[12]),
        .Q(\^LOCKSTEP_Out [2926]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2927] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[13]),
        .Q(\^LOCKSTEP_Out [2927]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2928] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[14]),
        .Q(\^LOCKSTEP_Out [2928]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2929] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[15]),
        .Q(\^LOCKSTEP_Out [2929]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2930] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[16]),
        .Q(\^LOCKSTEP_Out [2930]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2931] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[17]),
        .Q(\^LOCKSTEP_Out [2931]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2932] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[18]),
        .Q(\^LOCKSTEP_Out [2932]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2933] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[19]),
        .Q(\^LOCKSTEP_Out [2933]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2934] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[20]),
        .Q(\^LOCKSTEP_Out [2934]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2935] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[21]),
        .Q(\^LOCKSTEP_Out [2935]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2936] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[22]),
        .Q(\^LOCKSTEP_Out [2936]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2937] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[23]),
        .Q(\^LOCKSTEP_Out [2937]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2938] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[24]),
        .Q(\^LOCKSTEP_Out [2938]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2939] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[25]),
        .Q(\^LOCKSTEP_Out [2939]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2940] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[26]),
        .Q(\^LOCKSTEP_Out [2940]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2941] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[27]),
        .Q(\^LOCKSTEP_Out [2941]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2942] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[28]),
        .Q(\^LOCKSTEP_Out [2942]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2943] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[29]),
        .Q(\^LOCKSTEP_Out [2943]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2944] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[30]),
        .Q(\^LOCKSTEP_Out [2944]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2945] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_PC[31]),
        .Q(\^LOCKSTEP_Out [2945]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2978] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Reg_Write),
        .Q(\^LOCKSTEP_Out [2978]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2979] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Reg_Addr[0]),
        .Q(\^LOCKSTEP_Out [2979]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2980] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Reg_Addr[1]),
        .Q(\^LOCKSTEP_Out [2980]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2981] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Reg_Addr[2]),
        .Q(\^LOCKSTEP_Out [2981]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2982] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Reg_Addr[3]),
        .Q(\^LOCKSTEP_Out [2982]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2983] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Reg_Addr[4]),
        .Q(\^LOCKSTEP_Out [2983]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2995] 
       (.C(Clk),
        .CE(1'b1),
        .D(\^Trace_MSR_Reg [11]),
        .Q(\^LOCKSTEP_Out [2995]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2996] 
       (.C(Clk),
        .CE(1'b1),
        .D(\^Trace_MSR_Reg [12]),
        .Q(\^LOCKSTEP_Out [2996]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2997] 
       (.C(Clk),
        .CE(1'b1),
        .D(\^Trace_MSR_Reg [13]),
        .Q(\^LOCKSTEP_Out [2997]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[29] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[25]),
        .Q(\^LOCKSTEP_Out [29]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(IFetch),
        .Q(\^LOCKSTEP_Out [2]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3007] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[0]),
        .Q(\^LOCKSTEP_Out [3007]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3008] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[1]),
        .Q(\^LOCKSTEP_Out [3008]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3009] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[2]),
        .Q(\^LOCKSTEP_Out [3009]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3010] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[3]),
        .Q(\^LOCKSTEP_Out [3010]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3011] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[4]),
        .Q(\^LOCKSTEP_Out [3011]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3012] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[5]),
        .Q(\^LOCKSTEP_Out [3012]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3013] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[6]),
        .Q(\^LOCKSTEP_Out [3013]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3014] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[7]),
        .Q(\^LOCKSTEP_Out [3014]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3015] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[8]),
        .Q(\^LOCKSTEP_Out [3015]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3016] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[9]),
        .Q(\^LOCKSTEP_Out [3016]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3017] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[10]),
        .Q(\^LOCKSTEP_Out [3017]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3018] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[11]),
        .Q(\^LOCKSTEP_Out [3018]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3019] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[12]),
        .Q(\^LOCKSTEP_Out [3019]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3020] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[13]),
        .Q(\^LOCKSTEP_Out [3020]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3021] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[14]),
        .Q(\^LOCKSTEP_Out [3021]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3022] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[15]),
        .Q(\^LOCKSTEP_Out [3022]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3023] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[16]),
        .Q(\^LOCKSTEP_Out [3023]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3024] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[17]),
        .Q(\^LOCKSTEP_Out [3024]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3025] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[18]),
        .Q(\^LOCKSTEP_Out [3025]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3026] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[19]),
        .Q(\^LOCKSTEP_Out [3026]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3027] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[20]),
        .Q(\^LOCKSTEP_Out [3027]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3028] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[21]),
        .Q(\^LOCKSTEP_Out [3028]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3029] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[22]),
        .Q(\^LOCKSTEP_Out [3029]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3030] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[23]),
        .Q(\^LOCKSTEP_Out [3030]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3031] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[24]),
        .Q(\^LOCKSTEP_Out [3031]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3032] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[25]),
        .Q(\^LOCKSTEP_Out [3032]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3033] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[26]),
        .Q(\^LOCKSTEP_Out [3033]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3034] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[27]),
        .Q(\^LOCKSTEP_Out [3034]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3035] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[28]),
        .Q(\^LOCKSTEP_Out [3035]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3036] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[29]),
        .Q(\^LOCKSTEP_Out [3036]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3037] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[30]),
        .Q(\^LOCKSTEP_Out [3037]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3038] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_New_Reg_Value[31]),
        .Q(\^LOCKSTEP_Out [3038]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3071] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Exception_Taken),
        .Q(\^LOCKSTEP_Out [3071]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3073] 
       (.C(Clk),
        .CE(1'b1),
        .D(\^Trace_Exception_Kind [1]),
        .Q(\^LOCKSTEP_Out [3073]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3076] 
       (.C(Clk),
        .CE(1'b1),
        .D(\^Trace_Exception_Kind [4]),
        .Q(\^LOCKSTEP_Out [3076]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3077] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Jump_Taken),
        .Q(\^LOCKSTEP_Out [3077]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3078] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Delay_Slot),
        .Q(\^LOCKSTEP_Out [3078]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3079] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[0]),
        .Q(\^LOCKSTEP_Out [3079]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3080] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[1]),
        .Q(\^LOCKSTEP_Out [3080]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3081] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[2]),
        .Q(\^LOCKSTEP_Out [3081]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3082] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[3]),
        .Q(\^LOCKSTEP_Out [3082]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3083] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[4]),
        .Q(\^LOCKSTEP_Out [3083]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3084] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[5]),
        .Q(\^LOCKSTEP_Out [3084]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3085] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[6]),
        .Q(\^LOCKSTEP_Out [3085]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3086] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[7]),
        .Q(\^LOCKSTEP_Out [3086]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3087] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[8]),
        .Q(\^LOCKSTEP_Out [3087]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3088] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[9]),
        .Q(\^LOCKSTEP_Out [3088]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3089] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[10]),
        .Q(\^LOCKSTEP_Out [3089]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3090] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[11]),
        .Q(\^LOCKSTEP_Out [3090]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3091] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[12]),
        .Q(\^LOCKSTEP_Out [3091]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3092] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[13]),
        .Q(\^LOCKSTEP_Out [3092]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3093] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[14]),
        .Q(\^LOCKSTEP_Out [3093]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3094] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[15]),
        .Q(\^LOCKSTEP_Out [3094]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3095] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[16]),
        .Q(\^LOCKSTEP_Out [3095]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3096] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[17]),
        .Q(\^LOCKSTEP_Out [3096]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3097] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[18]),
        .Q(\^LOCKSTEP_Out [3097]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3098] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[19]),
        .Q(\^LOCKSTEP_Out [3098]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3099] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[20]),
        .Q(\^LOCKSTEP_Out [3099]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[30] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[26]),
        .Q(\^LOCKSTEP_Out [30]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3100] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[21]),
        .Q(\^LOCKSTEP_Out [3100]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3101] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[22]),
        .Q(\^LOCKSTEP_Out [3101]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3102] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[23]),
        .Q(\^LOCKSTEP_Out [3102]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3103] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[24]),
        .Q(\^LOCKSTEP_Out [3103]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3104] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[25]),
        .Q(\^LOCKSTEP_Out [3104]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3105] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[26]),
        .Q(\^LOCKSTEP_Out [3105]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3106] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[27]),
        .Q(\^LOCKSTEP_Out [3106]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3107] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[28]),
        .Q(\^LOCKSTEP_Out [3107]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3108] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[29]),
        .Q(\^LOCKSTEP_Out [3108]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3109] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[30]),
        .Q(\^LOCKSTEP_Out [3109]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3110] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Address[31]),
        .Q(\^LOCKSTEP_Out [3110]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3143] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[0]),
        .Q(\^LOCKSTEP_Out [3143]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3144] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[1]),
        .Q(\^LOCKSTEP_Out [3144]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3145] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[2]),
        .Q(\^LOCKSTEP_Out [3145]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3146] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[3]),
        .Q(\^LOCKSTEP_Out [3146]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3147] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[4]),
        .Q(\^LOCKSTEP_Out [3147]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3148] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[5]),
        .Q(\^LOCKSTEP_Out [3148]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3149] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[6]),
        .Q(\^LOCKSTEP_Out [3149]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3150] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[7]),
        .Q(\^LOCKSTEP_Out [3150]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3151] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[8]),
        .Q(\^LOCKSTEP_Out [3151]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3152] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[9]),
        .Q(\^LOCKSTEP_Out [3152]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3153] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[10]),
        .Q(\^LOCKSTEP_Out [3153]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3154] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[11]),
        .Q(\^LOCKSTEP_Out [3154]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3155] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[12]),
        .Q(\^LOCKSTEP_Out [3155]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3156] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[13]),
        .Q(\^LOCKSTEP_Out [3156]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3157] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[14]),
        .Q(\^LOCKSTEP_Out [3157]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3158] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[15]),
        .Q(\^LOCKSTEP_Out [3158]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3159] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[16]),
        .Q(\^LOCKSTEP_Out [3159]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3160] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[17]),
        .Q(\^LOCKSTEP_Out [3160]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3161] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[18]),
        .Q(\^LOCKSTEP_Out [3161]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3162] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[19]),
        .Q(\^LOCKSTEP_Out [3162]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3163] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[20]),
        .Q(\^LOCKSTEP_Out [3163]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3164] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[21]),
        .Q(\^LOCKSTEP_Out [3164]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3165] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[22]),
        .Q(\^LOCKSTEP_Out [3165]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3166] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[23]),
        .Q(\^LOCKSTEP_Out [3166]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3167] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[24]),
        .Q(\^LOCKSTEP_Out [3167]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3168] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[25]),
        .Q(\^LOCKSTEP_Out [3168]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3169] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[26]),
        .Q(\^LOCKSTEP_Out [3169]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3170] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[27]),
        .Q(\^LOCKSTEP_Out [3170]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3171] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[28]),
        .Q(\^LOCKSTEP_Out [3171]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3172] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[29]),
        .Q(\^LOCKSTEP_Out [3172]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3173] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[30]),
        .Q(\^LOCKSTEP_Out [3173]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3174] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write_Value[31]),
        .Q(\^LOCKSTEP_Out [3174]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[31] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[27]),
        .Q(\^LOCKSTEP_Out [31]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3207] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Byte_Enable[0]),
        .Q(\^LOCKSTEP_Out [3207]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3208] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Byte_Enable[1]),
        .Q(\^LOCKSTEP_Out [3208]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3209] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Byte_Enable[2]),
        .Q(\^LOCKSTEP_Out [3209]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3210] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Byte_Enable[3]),
        .Q(\^LOCKSTEP_Out [3210]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3215] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Access),
        .Q(\^LOCKSTEP_Out [3215]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3216] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Read),
        .Q(\^LOCKSTEP_Out [3216]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3217] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_Data_Write),
        .Q(\^LOCKSTEP_Out [3217]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3225] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_OF_PipeRun),
        .Q(\^LOCKSTEP_Out [3225]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3226] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_EX_PipeRun),
        .Q(\^LOCKSTEP_Out [3226]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3227] 
       (.C(Clk),
        .CE(1'b1),
        .D(Trace_MEM_PipeRun),
        .Q(\^LOCKSTEP_Out [3227]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[32] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[28]),
        .Q(\^LOCKSTEP_Out [32]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[33] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[29]),
        .Q(\^LOCKSTEP_Out [33]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[34] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[30]),
        .Q(\^LOCKSTEP_Out [34]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[35] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[31]),
        .Q(\^LOCKSTEP_Out [35]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[3] 
       (.C(Clk),
        .CE(1'b1),
        .D(I_AS),
        .Q(\^LOCKSTEP_Out [3]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[466] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[31]),
        .Q(\^LOCKSTEP_Out [632]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[467] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[30]),
        .Q(\^LOCKSTEP_Out [633]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[468] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[29]),
        .Q(\^LOCKSTEP_Out [634]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[469] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[28]),
        .Q(\^LOCKSTEP_Out [635]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[470] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[27]),
        .Q(\^LOCKSTEP_Out [636]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[471] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[26]),
        .Q(\^LOCKSTEP_Out [637]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[472] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[25]),
        .Q(\^LOCKSTEP_Out [638]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[473] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[24]),
        .Q(\^LOCKSTEP_Out [639]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[474] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[23]),
        .Q(\^LOCKSTEP_Out [640]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[475] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[22]),
        .Q(\^LOCKSTEP_Out [641]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[476] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[21]),
        .Q(\^LOCKSTEP_Out [642]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[477] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[20]),
        .Q(\^LOCKSTEP_Out [643]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[478] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[19]),
        .Q(\^LOCKSTEP_Out [644]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[479] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[18]),
        .Q(\^LOCKSTEP_Out [645]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[480] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[17]),
        .Q(\^LOCKSTEP_Out [646]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[481] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[16]),
        .Q(\^LOCKSTEP_Out [647]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[482] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[15]),
        .Q(\^LOCKSTEP_Out [648]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[483] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[14]),
        .Q(\^LOCKSTEP_Out [649]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[484] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[13]),
        .Q(\^LOCKSTEP_Out [650]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[485] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[12]),
        .Q(\^LOCKSTEP_Out [651]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[486] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[11]),
        .Q(\^LOCKSTEP_Out [652]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[487] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[10]),
        .Q(\^LOCKSTEP_Out [653]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[488] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[9]),
        .Q(\^LOCKSTEP_Out [654]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[489] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[8]),
        .Q(\^LOCKSTEP_Out [655]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[490] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[7]),
        .Q(\^LOCKSTEP_Out [656]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[491] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[6]),
        .Q(\^LOCKSTEP_Out [657]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[492] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[5]),
        .Q(\^LOCKSTEP_Out [658]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[493] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[4]),
        .Q(\^LOCKSTEP_Out [659]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[494] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[3]),
        .Q(\^LOCKSTEP_Out [660]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[495] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[2]),
        .Q(\^LOCKSTEP_Out [661]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[496] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[1]),
        .Q(\^LOCKSTEP_Out [662]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[497] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARADDR[0]),
        .Q(\^LOCKSTEP_Out [663]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[4] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[0]),
        .Q(\^LOCKSTEP_Out [4]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[539] 
       (.C(Clk),
        .CE(1'b1),
        .D(1'b1),
        .Q(\^LOCKSTEP_Out [542]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[555] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_AWVALID),
        .Q(\^LOCKSTEP_Out [555]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[556] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[31]),
        .Q(\^LOCKSTEP_Out [556]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[557] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[30]),
        .Q(\^LOCKSTEP_Out [557]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[558] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[29]),
        .Q(\^LOCKSTEP_Out [558]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[559] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[28]),
        .Q(\^LOCKSTEP_Out [559]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[560] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[27]),
        .Q(\^LOCKSTEP_Out [560]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[561] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[26]),
        .Q(\^LOCKSTEP_Out [561]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[562] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[25]),
        .Q(\^LOCKSTEP_Out [562]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[563] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[24]),
        .Q(\^LOCKSTEP_Out [563]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[564] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[23]),
        .Q(\^LOCKSTEP_Out [564]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[565] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[22]),
        .Q(\^LOCKSTEP_Out [565]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[566] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[21]),
        .Q(\^LOCKSTEP_Out [566]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[567] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[20]),
        .Q(\^LOCKSTEP_Out [567]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[568] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[19]),
        .Q(\^LOCKSTEP_Out [568]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[569] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[18]),
        .Q(\^LOCKSTEP_Out [569]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[570] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[17]),
        .Q(\^LOCKSTEP_Out [570]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[571] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[16]),
        .Q(\^LOCKSTEP_Out [571]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[572] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[15]),
        .Q(\^LOCKSTEP_Out [572]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[573] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[14]),
        .Q(\^LOCKSTEP_Out [573]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[574] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[13]),
        .Q(\^LOCKSTEP_Out [574]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[575] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[12]),
        .Q(\^LOCKSTEP_Out [575]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[576] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[11]),
        .Q(\^LOCKSTEP_Out [576]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[577] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[10]),
        .Q(\^LOCKSTEP_Out [577]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[578] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[9]),
        .Q(\^LOCKSTEP_Out [578]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[579] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[8]),
        .Q(\^LOCKSTEP_Out [579]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[580] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[7]),
        .Q(\^LOCKSTEP_Out [580]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[581] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[6]),
        .Q(\^LOCKSTEP_Out [581]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[582] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[5]),
        .Q(\^LOCKSTEP_Out [582]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[583] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[4]),
        .Q(\^LOCKSTEP_Out [583]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[584] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[3]),
        .Q(\^LOCKSTEP_Out [584]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[585] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[2]),
        .Q(\^LOCKSTEP_Out [585]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[586] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[1]),
        .Q(\^LOCKSTEP_Out [586]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[587] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WDATA[0]),
        .Q(\^LOCKSTEP_Out [587]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[5] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[1]),
        .Q(\^LOCKSTEP_Out [5]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[620] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WSTRB[3]),
        .Q(\^LOCKSTEP_Out [620]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[621] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WSTRB[2]),
        .Q(\^LOCKSTEP_Out [621]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[622] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WSTRB[1]),
        .Q(\^LOCKSTEP_Out [622]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[623] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WSTRB[0]),
        .Q(\^LOCKSTEP_Out [623]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[629] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_WVALID),
        .Q(\^LOCKSTEP_Out [629]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[68] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[0]),
        .Q(\^LOCKSTEP_Out [68]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[69] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[1]),
        .Q(\^LOCKSTEP_Out [69]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[6] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[2]),
        .Q(\^LOCKSTEP_Out [6]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[70] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[2]),
        .Q(\^LOCKSTEP_Out [70]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[71] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[3]),
        .Q(\^LOCKSTEP_Out [71]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[721] 
       (.C(Clk),
        .CE(1'b1),
        .D(M_AXI_DP_ARVALID),
        .Q(\^LOCKSTEP_Out [721]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[72] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[4]),
        .Q(\^LOCKSTEP_Out [72]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[73] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[5]),
        .Q(\^LOCKSTEP_Out [73]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[74] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[6]),
        .Q(\^LOCKSTEP_Out [74]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[75] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[7]),
        .Q(\^LOCKSTEP_Out [75]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[76] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[8]),
        .Q(\^LOCKSTEP_Out [76]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[77] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[9]),
        .Q(\^LOCKSTEP_Out [77]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[78] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[10]),
        .Q(\^LOCKSTEP_Out [78]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[79] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[11]),
        .Q(\^LOCKSTEP_Out [79]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[7] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[3]),
        .Q(\^LOCKSTEP_Out [7]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[80] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[12]),
        .Q(\^LOCKSTEP_Out [80]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[81] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[13]),
        .Q(\^LOCKSTEP_Out [81]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[82] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[14]),
        .Q(\^LOCKSTEP_Out [82]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[83] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[15]),
        .Q(\^LOCKSTEP_Out [83]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[84] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[16]),
        .Q(\^LOCKSTEP_Out [84]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[85] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[17]),
        .Q(\^LOCKSTEP_Out [85]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[86] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[18]),
        .Q(\^LOCKSTEP_Out [86]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[87] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[19]),
        .Q(\^LOCKSTEP_Out [87]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[88] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[20]),
        .Q(\^LOCKSTEP_Out [88]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[89] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[21]),
        .Q(\^LOCKSTEP_Out [89]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[8] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[4]),
        .Q(\^LOCKSTEP_Out [8]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[90] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[22]),
        .Q(\^LOCKSTEP_Out [90]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[91] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[23]),
        .Q(\^LOCKSTEP_Out [91]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[92] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[24]),
        .Q(\^LOCKSTEP_Out [92]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[93] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[25]),
        .Q(\^LOCKSTEP_Out [93]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[94] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[26]),
        .Q(\^LOCKSTEP_Out [94]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[95] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[27]),
        .Q(\^LOCKSTEP_Out [95]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[96] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[28]),
        .Q(\^LOCKSTEP_Out [96]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[97] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[29]),
        .Q(\^LOCKSTEP_Out [97]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[98] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[30]),
        .Q(\^LOCKSTEP_Out [98]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[99] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Addr[31]),
        .Q(\^LOCKSTEP_Out [99]),
        .R(Reset));
  FDRE \LOCKSTEP_Out_reg[9] 
       (.C(Clk),
        .CE(1'b1),
        .D(Instr_Addr[5]),
        .Q(\^LOCKSTEP_Out [9]),
        .R(Reset));
  design_1_microblaze_0_0_MicroBlaze_Core MicroBlaze_Core_I
       (.Clk(Clk),
        .Config_Reg_En(Config_Reg_En),
        .D({\^LOCKSTEP_Master_Out [10],IFetch,I_AS,Instr_Addr[0],Instr_Addr[1],Instr_Addr[2],Instr_Addr[3],Instr_Addr[4],Instr_Addr[5],Instr_Addr[6],Instr_Addr[7],Instr_Addr[8],Instr_Addr[9],Instr_Addr[10],Instr_Addr[11],Instr_Addr[12],Instr_Addr[13],Instr_Addr[14],Instr_Addr[15],Instr_Addr[16],Instr_Addr[17],Instr_Addr[18],Instr_Addr[19],Instr_Addr[20],Instr_Addr[21],Instr_Addr[22],Instr_Addr[23],Instr_Addr[24],Instr_Addr[25],Instr_Addr[26],Instr_Addr[27],Instr_Addr[28],Instr_Addr[29],Instr_Addr[30],Instr_Addr[31],Data_Addr[0],Data_Addr[1],Data_Addr[2],Data_Addr[3],Data_Addr[4],Data_Addr[5],Data_Addr[6],Data_Addr[7],Data_Addr[8],Data_Addr[9],Data_Addr[10],Data_Addr[11],Data_Addr[12],Data_Addr[13],Data_Addr[14],Data_Addr[15],Data_Addr[16],Data_Addr[17],Data_Addr[18],Data_Addr[19],Data_Addr[20],Data_Addr[21],Data_Addr[22],Data_Addr[23],Data_Addr[24],Data_Addr[25],Data_Addr[26],Data_Addr[27],Data_Addr[28],Data_Addr[29],Data_Addr[30],Data_Addr[31],Data_Write[0],Data_Write[1],Data_Write[2],Data_Write[3],Data_Write[4],Data_Write[5],Data_Write[6],Data_Write[7],Data_Write[8],Data_Write[9],Data_Write[10],Data_Write[11],Data_Write[12],Data_Write[13],Data_Write[14],Data_Write[15],Data_Write[16],Data_Write[17],Data_Write[18],Data_Write[19],Data_Write[20],Data_Write[21],Data_Write[22],Data_Write[23],Data_Write[24],Data_Write[25],Data_Write[26],Data_Write[27],Data_Write[28],Data_Write[29],Data_Write[30],Data_Write[31],D_AS,Read_Strobe,Write_Strobe,Byte_Enable[0],Byte_Enable[1],Byte_Enable[2],Byte_Enable[3],M_AXI_DP_ARADDR,M_AXI_DP_AWVALID,M_AXI_DP_WDATA,M_AXI_DP_WSTRB,M_AXI_DP_WVALID,M_AXI_DP_ARVALID,Trace_Instruction[0],Trace_Instruction[1],Trace_Instruction[2],Trace_Instruction[3],Trace_Instruction[4],Trace_Instruction[5],Trace_Instruction[6],Trace_Instruction[7],Trace_Instruction[8],Trace_Instruction[9],Trace_Instruction[10],Trace_Instruction[11],Trace_Instruction[12],Trace_Instruction[13],Trace_Instruction[14],Trace_Instruction[15],Trace_Instruction[16],Trace_Instruction[17],Trace_Instruction[18],Trace_Instruction[19],Trace_Instruction[20],Trace_Instruction[21],Trace_Instruction[22],Trace_Instruction[23],Trace_Instruction[24],Trace_Instruction[25],Trace_Instruction[26],Trace_Instruction[27],Trace_Instruction[28],Trace_Instruction[29],Trace_Instruction[30],Trace_Instruction[31],Trace_Valid_Instr,Trace_PC[0],Trace_PC[1],Trace_PC[2],Trace_PC[3],Trace_PC[4],Trace_PC[5],Trace_PC[6],Trace_PC[7],Trace_PC[8],Trace_PC[9],Trace_PC[10],Trace_PC[11],Trace_PC[12],Trace_PC[13],Trace_PC[14],Trace_PC[15],Trace_PC[16],Trace_PC[17],Trace_PC[18],Trace_PC[19],Trace_PC[20],Trace_PC[21],Trace_PC[22],Trace_PC[23],Trace_PC[24],Trace_PC[25],Trace_PC[26],Trace_PC[27],Trace_PC[28],Trace_PC[29],Trace_PC[30],Trace_PC[31],Trace_Reg_Write,Trace_Reg_Addr[0],Trace_Reg_Addr[1],Trace_Reg_Addr[2],Trace_Reg_Addr[3],Trace_Reg_Addr[4],\^Trace_MSR_Reg [11],\^Trace_MSR_Reg [12],\^Trace_MSR_Reg [13],Trace_New_Reg_Value[0],Trace_New_Reg_Value[1],Trace_New_Reg_Value[2],Trace_New_Reg_Value[3],Trace_New_Reg_Value[4],Trace_New_Reg_Value[5],Trace_New_Reg_Value[6],Trace_New_Reg_Value[7],Trace_New_Reg_Value[8],Trace_New_Reg_Value[9],Trace_New_Reg_Value[10],Trace_New_Reg_Value[11],Trace_New_Reg_Value[12],Trace_New_Reg_Value[13],Trace_New_Reg_Value[14],Trace_New_Reg_Value[15],Trace_New_Reg_Value[16],Trace_New_Reg_Value[17],Trace_New_Reg_Value[18],Trace_New_Reg_Value[19],Trace_New_Reg_Value[20],Trace_New_Reg_Value[21],Trace_New_Reg_Value[22],Trace_New_Reg_Value[23],Trace_New_Reg_Value[24],Trace_New_Reg_Value[25],Trace_New_Reg_Value[26],Trace_New_Reg_Value[27],Trace_New_Reg_Value[28],Trace_New_Reg_Value[29],Trace_New_Reg_Value[30],Trace_New_Reg_Value[31],Trace_Exception_Taken,\^Trace_Exception_Kind [1],\^Trace_Exception_Kind [4],Trace_Jump_Taken,Trace_Delay_Slot,Trace_Data_Address[0],Trace_Data_Address[1],Trace_Data_Address[2],Trace_Data_Address[3],Trace_Data_Address[4],Trace_Data_Address[5],Trace_Data_Address[6],Trace_Data_Address[7],Trace_Data_Address[8],Trace_Data_Address[9],Trace_Data_Address[10],Trace_Data_Address[11],Trace_Data_Address[12],Trace_Data_Address[13],Trace_Data_Address[14],Trace_Data_Address[15],Trace_Data_Address[16],Trace_Data_Address[17],Trace_Data_Address[18],Trace_Data_Address[19],Trace_Data_Address[20],Trace_Data_Address[21],Trace_Data_Address[22],Trace_Data_Address[23],Trace_Data_Address[24],Trace_Data_Address[25],Trace_Data_Address[26],Trace_Data_Address[27],Trace_Data_Address[28],Trace_Data_Address[29],Trace_Data_Address[30],Trace_Data_Address[31],Trace_Data_Write_Value[0],Trace_Data_Write_Value[1],Trace_Data_Write_Value[2],Trace_Data_Write_Value[3],Trace_Data_Write_Value[4],Trace_Data_Write_Value[5],Trace_Data_Write_Value[6],Trace_Data_Write_Value[7],Trace_Data_Write_Value[8],Trace_Data_Write_Value[9],Trace_Data_Write_Value[10],Trace_Data_Write_Value[11],Trace_Data_Write_Value[12],Trace_Data_Write_Value[13],Trace_Data_Write_Value[14],Trace_Data_Write_Value[15],Trace_Data_Write_Value[16],Trace_Data_Write_Value[17],Trace_Data_Write_Value[18],Trace_Data_Write_Value[19],Trace_Data_Write_Value[20],Trace_Data_Write_Value[21],Trace_Data_Write_Value[22],Trace_Data_Write_Value[23],Trace_Data_Write_Value[24],Trace_Data_Write_Value[25],Trace_Data_Write_Value[26],Trace_Data_Write_Value[27],Trace_Data_Write_Value[28],Trace_Data_Write_Value[29],Trace_Data_Write_Value[30],Trace_Data_Write_Value[31],Trace_Data_Byte_Enable[0],Trace_Data_Byte_Enable[1],Trace_Data_Byte_Enable[2],Trace_Data_Byte_Enable[3],Trace_Data_Access,Trace_Data_Read,Trace_Data_Write}),
        .DReady(DReady),
        .DWait(DWait),
        .Data_Read(Data_Read),
        .Data_Read_Reg_En(Data_Read_Reg_En),
        .Dbg_Capture(Dbg_Capture),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_Reg_En(Dbg_Reg_En),
        .Dbg_Reg_En_0_sp_1(MicroBlaze_Core_I_n_411),
        .Dbg_Shift(Dbg_Shift),
        .Dbg_Stop(Dbg_Stop),
        .Dbg_TDI(Dbg_TDI),
        .Dbg_TDO(Dbg_TDO),
        .Dbg_Trig_Ack_In({Dbg_Trig_Ack_In[0],Dbg_Trig_Ack_In[1]}),
        .Dbg_Trig_Ack_Out({\^Dbg_Trig_Ack_Out [0],\^Dbg_Trig_Ack_Out [1]}),
        .Dbg_Trig_In({\^Dbg_Trig_In [0],\^Dbg_Trig_In [1]}),
        .Dbg_Trig_Out({Dbg_Trig_Out[0],Dbg_Trig_Out[1]}),
        .Dbg_Update(Dbg_Update),
        .Debug_Rst(Debug_Rst),
        .Hibernate(Hibernate),
        .IReady(IReady),
        .Instr(Instr),
        .LOCKSTEP_Master_Out({\^LOCKSTEP_Master_Out [1],\^LOCKSTEP_Master_Out [3],\^LOCKSTEP_Master_Out [4],\^LOCKSTEP_Master_Out [5],\^LOCKSTEP_Master_Out [6],\^LOCKSTEP_Master_Out [7],\^LOCKSTEP_Master_Out [11],Dbg_Continue,\^LOCKSTEP_Master_Out [13],\^LOCKSTEP_Master_Out [15],\^LOCKSTEP_Master_Out [16],\^LOCKSTEP_Master_Out [17],\^LOCKSTEP_Master_Out [18],\^LOCKSTEP_Master_Out [19],\^LOCKSTEP_Master_Out [20],\^LOCKSTEP_Master_Out [21],\^LOCKSTEP_Master_Out [22],\^LOCKSTEP_Master_Out [23],\^LOCKSTEP_Master_Out [24],\^LOCKSTEP_Master_Out [25],\^LOCKSTEP_Master_Out [26],\^LOCKSTEP_Master_Out [27],\^LOCKSTEP_Master_Out [28],\^LOCKSTEP_Master_Out [29],\^LOCKSTEP_Master_Out [30],\^LOCKSTEP_Master_Out [31],\^LOCKSTEP_Master_Out [32],\^LOCKSTEP_Master_Out [33],\^LOCKSTEP_Master_Out [34],\^LOCKSTEP_Master_Out [35],\^LOCKSTEP_Master_Out [36],\^LOCKSTEP_Master_Out [37],\^LOCKSTEP_Master_Out [38],\^LOCKSTEP_Master_Out [39],\^LOCKSTEP_Master_Out [40],\^LOCKSTEP_Master_Out [41],\^LOCKSTEP_Master_Out [42],\^LOCKSTEP_Master_Out [43],\^LOCKSTEP_Master_Out [44],\^LOCKSTEP_Master_Out [45],\^LOCKSTEP_Master_Out [46]}),
        .M_AXI_DP_ARREADY(M_AXI_DP_ARREADY),
        .M_AXI_DP_AWREADY(M_AXI_DP_AWREADY),
        .M_AXI_DP_BVALID(M_AXI_DP_BVALID),
        .M_AXI_DP_RDATA(M_AXI_DP_RDATA),
        .M_AXI_DP_RVALID(M_AXI_DP_RVALID),
        .M_AXI_DP_WREADY(M_AXI_DP_WREADY),
        .Mb_Reset(Mb_Reset),
        .Pause(Pause),
        .Pause_Ack(Pause_Ack),
        .Reset(Reset),
        .Reset_Mode(Reset_Mode),
        .Scan_En(Scan_En),
        .Scan_Reset(Scan_Reset),
        .Scan_Reset_Sel(Scan_Reset_Sel),
        .Sleep(Sleep),
        .Status_Reg_En(\Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Status_Reg_En ),
        .Suspend(Suspend),
        .\Using_FPGA.Native (Trace_MEM_PipeRun),
        .\Using_FPGA.Native_0 (Trace_EX_PipeRun),
        .Wakeup(Wakeup),
        .of_pause_reg(Trace_OF_PipeRun));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* ORIG_REF_NAME = "MicroBlaze_Core" *) 
module design_1_microblaze_0_0_MicroBlaze_Core
   (of_pause_reg,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    Hibernate,
    Suspend,
    Pause_Ack,
    D,
    Sleep,
    LOCKSTEP_Master_Out,
    Dbg_Trig_In,
    Dbg_Trig_Ack_Out,
    Dbg_Reg_En_0_sp_1,
    Dbg_TDO,
    Clk,
    Dbg_Clk,
    Dbg_Trig_Ack_In,
    Dbg_Trig_Out,
    Pause,
    Dbg_Update,
    Dbg_Stop,
    Dbg_Capture,
    Reset,
    Mb_Reset,
    Debug_Rst,
    M_AXI_DP_BVALID,
    M_AXI_DP_RVALID,
    M_AXI_DP_WREADY,
    M_AXI_DP_AWREADY,
    M_AXI_DP_ARREADY,
    Reset_Mode,
    Data_Read_Reg_En,
    Config_Reg_En,
    IReady,
    Dbg_Shift,
    DReady,
    DWait,
    Dbg_Reg_En,
    Status_Reg_En,
    Scan_Reset_Sel,
    Scan_Reset,
    Scan_En,
    Instr,
    M_AXI_DP_RDATA,
    Dbg_TDI,
    Data_Read,
    Wakeup);
  output of_pause_reg;
  output \Using_FPGA.Native ;
  output \Using_FPGA.Native_0 ;
  output Hibernate;
  output Suspend;
  output Pause_Ack;
  output [358:0]D;
  output Sleep;
  output [40:0]LOCKSTEP_Master_Out;
  output [1:0]Dbg_Trig_In;
  output [1:0]Dbg_Trig_Ack_Out;
  output Dbg_Reg_En_0_sp_1;
  output Dbg_TDO;
  input Clk;
  input Dbg_Clk;
  input [1:0]Dbg_Trig_Ack_In;
  input [1:0]Dbg_Trig_Out;
  input Pause;
  input Dbg_Update;
  input Dbg_Stop;
  input Dbg_Capture;
  input Reset;
  input Mb_Reset;
  input Debug_Rst;
  input M_AXI_DP_BVALID;
  input M_AXI_DP_RVALID;
  input M_AXI_DP_WREADY;
  input M_AXI_DP_AWREADY;
  input M_AXI_DP_ARREADY;
  input [0:1]Reset_Mode;
  input Data_Read_Reg_En;
  input Config_Reg_En;
  input IReady;
  input Dbg_Shift;
  input DReady;
  input DWait;
  input [0:7]Dbg_Reg_En;
  input Status_Reg_En;
  input Scan_Reset_Sel;
  input Scan_Reset;
  input Scan_En;
  input [0:31]Instr;
  input [31:0]M_AXI_DP_RDATA;
  input Dbg_TDI;
  input [0:31]Data_Read;
  input [0:1]Wakeup;

  wire Clk;
  wire Config_Reg_En;
  wire [358:0]D;
  wire DReady;
  wire DWait;
  wire [0:31]Data_Read;
  wire Data_Read_Reg_En;
  wire Dbg_Capture;
  wire Dbg_Clk;
  wire [0:7]Dbg_Reg_En;
  wire Dbg_Reg_En_0_sn_1;
  wire Dbg_Shift;
  wire Dbg_Stop;
  wire Dbg_TDI;
  wire Dbg_TDO;
  wire [1:0]Dbg_Trig_Ack_In;
  wire [1:0]Dbg_Trig_Ack_Out;
  wire [1:0]Dbg_Trig_In;
  wire [1:0]Dbg_Trig_Out;
  wire Dbg_Update;
  wire Debug_Rst;
  wire Hibernate;
  wire IReady;
  wire [0:31]Instr;
  wire [40:0]LOCKSTEP_Master_Out;
  wire M_AXI_DP_ARREADY;
  wire M_AXI_DP_AWREADY;
  wire M_AXI_DP_BVALID;
  wire [31:0]M_AXI_DP_RDATA;
  wire M_AXI_DP_RVALID;
  wire M_AXI_DP_WREADY;
  wire Mb_Reset;
  wire Pause;
  wire Pause_Ack;
  wire Reset;
  wire [0:1]Reset_Mode;
  wire Scan_En;
  wire Scan_Reset;
  wire Scan_Reset_Sel;
  wire Sleep;
  wire Status_Reg_En;
  wire Suspend;
  wire Synced;
  wire \Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire [0:1]Wakeup;
  wire of_pause_reg;
  wire reset_temp__0;
  wire sync_reset;
  wire [0:1]wakeup_i;

  assign Dbg_Reg_En_0_sp_1 = Dbg_Reg_En_0_sn_1;
  design_1_microblaze_0_0_MicroBlaze_GTi \Performance.Core 
       (.Clk(Clk),
        .Config_Reg_En(Config_Reg_En),
        .D(D),
        .DReady(DReady),
        .DWait(DWait),
        .Data_Read(Data_Read),
        .Data_Read_Reg_En(Data_Read_Reg_En),
        .Dbg_Capture(Dbg_Capture),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_Reg_En(Dbg_Reg_En),
        .Dbg_Reg_En_0_sp_1(Dbg_Reg_En_0_sn_1),
        .Dbg_Shift(Dbg_Shift),
        .Dbg_Stop(Dbg_Stop),
        .Dbg_TDI(Dbg_TDI),
        .Dbg_TDO(Dbg_TDO),
        .Dbg_Trig_Ack_In(Dbg_Trig_Ack_In),
        .Dbg_Trig_Ack_Out(Dbg_Trig_Ack_Out),
        .Dbg_Trig_In(Dbg_Trig_In),
        .Dbg_Trig_Out(Dbg_Trig_Out),
        .Dbg_Update(Dbg_Update),
        .E(of_pause_reg),
        .Hibernate(Hibernate),
        .IReady(IReady),
        .Instr(Instr),
        .LOCKSTEP_Master_Out(LOCKSTEP_Master_Out),
        .M_AXI_DP_ARREADY(M_AXI_DP_ARREADY),
        .M_AXI_DP_AWREADY(M_AXI_DP_AWREADY),
        .M_AXI_DP_BVALID(M_AXI_DP_BVALID),
        .M_AXI_DP_RDATA(M_AXI_DP_RDATA),
        .M_AXI_DP_RVALID(M_AXI_DP_RVALID),
        .M_AXI_DP_WREADY(M_AXI_DP_WREADY),
        .Pause(Pause),
        .Pause_Ack(Pause_Ack),
        .Reset_Mode(Reset_Mode),
        .Scan_En(Scan_En),
        .Scan_Reset(Scan_Reset),
        .Scan_Reset_Sel(Scan_Reset_Sel),
        .Sleep(Sleep),
        .Status_Reg_En(Status_Reg_En),
        .Suspend(Suspend),
        .\Using_FPGA.Native (\Using_FPGA.Native ),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .sync_reset(sync_reset),
        .wakeup_i(wakeup_i));
  design_1_microblaze_0_0_mb_sync_bit Reset_DFF
       (.Clk(Clk),
        .out(Synced),
        .reset_temp(reset_temp__0));
  FDRE #(
    .INIT(1'b1)) 
    \Use_Async_Reset.sync_reset_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(Synced),
        .Q(sync_reset),
        .R(1'b0));
  design_1_microblaze_0_0_mb_sync_bit_0 \Using_Async_Wakeup_0.Wakeup_DFF 
       (.Clk(Clk),
        .SR(sync_reset),
        .Wakeup(Wakeup[0]),
        .out(wakeup_i[0]));
  design_1_microblaze_0_0_mb_sync_bit_1 \Using_Async_Wakeup_1.Wakeup_DFF 
       (.Clk(Clk),
        .SR(sync_reset),
        .Wakeup(Wakeup[1]),
        .out(wakeup_i[1]));
  LUT3 #(
    .INIT(8'hFE)) 
    reset_temp
       (.I0(Reset),
        .I1(Mb_Reset),
        .I2(Debug_Rst),
        .O(reset_temp__0));
endmodule

(* ORIG_REF_NAME = "MicroBlaze_GTi" *) 
module design_1_microblaze_0_0_MicroBlaze_GTi
   (E,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    Hibernate,
    Suspend,
    Pause_Ack,
    D,
    Sleep,
    LOCKSTEP_Master_Out,
    Dbg_Trig_In,
    Dbg_Trig_Ack_Out,
    Dbg_Reg_En_0_sp_1,
    Dbg_TDO,
    sync_reset,
    Clk,
    Dbg_Clk,
    Dbg_Trig_Ack_In,
    Dbg_Trig_Out,
    Pause,
    Dbg_Update,
    Dbg_Stop,
    Dbg_Capture,
    M_AXI_DP_BVALID,
    M_AXI_DP_RVALID,
    M_AXI_DP_WREADY,
    M_AXI_DP_AWREADY,
    M_AXI_DP_ARREADY,
    Reset_Mode,
    Data_Read_Reg_En,
    Config_Reg_En,
    IReady,
    Dbg_Shift,
    DReady,
    DWait,
    Dbg_Reg_En,
    wakeup_i,
    Status_Reg_En,
    Scan_Reset_Sel,
    Scan_Reset,
    Scan_En,
    Instr,
    M_AXI_DP_RDATA,
    Dbg_TDI,
    Data_Read);
  output [0:0]E;
  output [0:0]\Using_FPGA.Native ;
  output [0:0]\Using_FPGA.Native_0 ;
  output Hibernate;
  output Suspend;
  output Pause_Ack;
  output [358:0]D;
  output Sleep;
  output [40:0]LOCKSTEP_Master_Out;
  output [1:0]Dbg_Trig_In;
  output [1:0]Dbg_Trig_Ack_Out;
  output Dbg_Reg_En_0_sp_1;
  output Dbg_TDO;
  input sync_reset;
  input Clk;
  input Dbg_Clk;
  input [1:0]Dbg_Trig_Ack_In;
  input [1:0]Dbg_Trig_Out;
  input Pause;
  input Dbg_Update;
  input Dbg_Stop;
  input Dbg_Capture;
  input M_AXI_DP_BVALID;
  input M_AXI_DP_RVALID;
  input M_AXI_DP_WREADY;
  input M_AXI_DP_AWREADY;
  input M_AXI_DP_ARREADY;
  input [0:1]Reset_Mode;
  input Data_Read_Reg_En;
  input Config_Reg_En;
  input IReady;
  input Dbg_Shift;
  input DReady;
  input DWait;
  input [0:7]Dbg_Reg_En;
  input [0:1]wakeup_i;
  input Status_Reg_En;
  input Scan_Reset_Sel;
  input Scan_Reset;
  input Scan_En;
  input [0:31]Instr;
  input [31:0]M_AXI_DP_RDATA;
  input Dbg_TDI;
  input [0:31]Data_Read;

  wire \ALU_I/DI ;
  wire Clk;
  wire Config_Reg_En;
  wire [358:0]D;
  wire DReady;
  wire DWait;
  wire Data_Flow_I_n_0;
  wire Data_Flow_I_n_1;
  wire Data_Flow_I_n_10;
  wire Data_Flow_I_n_11;
  wire Data_Flow_I_n_12;
  wire Data_Flow_I_n_13;
  wire Data_Flow_I_n_14;
  wire Data_Flow_I_n_15;
  wire Data_Flow_I_n_16;
  wire Data_Flow_I_n_17;
  wire Data_Flow_I_n_18;
  wire Data_Flow_I_n_185;
  wire Data_Flow_I_n_188;
  wire Data_Flow_I_n_189;
  wire Data_Flow_I_n_19;
  wire Data_Flow_I_n_190;
  wire Data_Flow_I_n_191;
  wire Data_Flow_I_n_192;
  wire Data_Flow_I_n_193;
  wire Data_Flow_I_n_194;
  wire Data_Flow_I_n_195;
  wire Data_Flow_I_n_196;
  wire Data_Flow_I_n_2;
  wire Data_Flow_I_n_20;
  wire Data_Flow_I_n_21;
  wire Data_Flow_I_n_22;
  wire Data_Flow_I_n_23;
  wire Data_Flow_I_n_24;
  wire Data_Flow_I_n_25;
  wire Data_Flow_I_n_26;
  wire Data_Flow_I_n_27;
  wire Data_Flow_I_n_28;
  wire Data_Flow_I_n_29;
  wire Data_Flow_I_n_3;
  wire Data_Flow_I_n_30;
  wire Data_Flow_I_n_31;
  wire Data_Flow_I_n_33;
  wire Data_Flow_I_n_4;
  wire Data_Flow_I_n_429;
  wire Data_Flow_I_n_430;
  wire Data_Flow_I_n_5;
  wire Data_Flow_I_n_6;
  wire Data_Flow_I_n_7;
  wire Data_Flow_I_n_8;
  wire Data_Flow_I_n_9;
  wire \Data_Flow_Logic_I/R ;
  wire \Data_Flow_Logic_I/WB_MEM_Result0 ;
  wire [0:31]Data_Read;
  wire Data_Read_Reg_En;
  wire Dbg_Capture;
  wire Dbg_Clk;
  wire [0:7]Dbg_Reg_En;
  wire Dbg_Reg_En_0_sn_1;
  wire Dbg_Shift;
  wire Dbg_Stop;
  wire Dbg_TDI;
  wire Dbg_TDO;
  wire [1:0]Dbg_Trig_Ack_In;
  wire [1:0]Dbg_Trig_Ack_Out;
  wire [1:0]Dbg_Trig_In;
  wire [1:0]Dbg_Trig_Out;
  wire Dbg_Update;
  wire Decode_I_n_247;
  wire Decode_I_n_258;
  wire Decode_I_n_263;
  wire Decode_I_n_364;
  wire Decode_I_n_365;
  wire Decode_I_n_366;
  wire Decode_I_n_367;
  wire Decode_I_n_368;
  wire Decode_I_n_369;
  wire Decode_I_n_370;
  wire Decode_I_n_371;
  wire Decode_I_n_372;
  wire Decode_I_n_373;
  wire Decode_I_n_374;
  wire Decode_I_n_375;
  wire Decode_I_n_376;
  wire Decode_I_n_377;
  wire Decode_I_n_378;
  wire Decode_I_n_379;
  wire Decode_I_n_380;
  wire Decode_I_n_381;
  wire Decode_I_n_382;
  wire Decode_I_n_383;
  wire Decode_I_n_384;
  wire Decode_I_n_385;
  wire Decode_I_n_386;
  wire Decode_I_n_387;
  wire Decode_I_n_388;
  wire Decode_I_n_389;
  wire Decode_I_n_390;
  wire Decode_I_n_391;
  wire Decode_I_n_392;
  wire Decode_I_n_393;
  wire Decode_I_n_394;
  wire Decode_I_n_396;
  wire Decode_I_n_397;
  wire Decode_I_n_398;
  wire Decode_I_n_399;
  wire Decode_I_n_400;
  wire Decode_I_n_401;
  wire Decode_I_n_402;
  wire Decode_I_n_403;
  wire Decode_I_n_404;
  wire Decode_I_n_405;
  wire Decode_I_n_406;
  wire Decode_I_n_407;
  wire Decode_I_n_408;
  wire Decode_I_n_409;
  wire Decode_I_n_410;
  wire Decode_I_n_411;
  wire Decode_I_n_412;
  wire Decode_I_n_413;
  wire Decode_I_n_414;
  wire Decode_I_n_415;
  wire Decode_I_n_416;
  wire Decode_I_n_417;
  wire Decode_I_n_418;
  wire Decode_I_n_419;
  wire Decode_I_n_423;
  wire Decode_I_n_424;
  wire Decode_I_n_425;
  wire Decode_I_n_426;
  wire Decode_I_n_427;
  wire Decode_I_n_430;
  wire Decode_I_n_437;
  wire Decode_I_n_438;
  wire Decode_I_n_439;
  wire Decode_I_n_440;
  wire Decode_I_n_441;
  wire Decode_I_n_442;
  wire Decode_I_n_443;
  wire Decode_I_n_444;
  wire Decode_I_n_445;
  wire Decode_I_n_446;
  wire Decode_I_n_447;
  wire Decode_I_n_448;
  wire Decode_I_n_449;
  wire Decode_I_n_450;
  wire Decode_I_n_451;
  wire Decode_I_n_452;
  wire Decode_I_n_453;
  wire Decode_I_n_454;
  wire Decode_I_n_455;
  wire Decode_I_n_456;
  wire Decode_I_n_457;
  wire Decode_I_n_458;
  wire Decode_I_n_459;
  wire Decode_I_n_460;
  wire Decode_I_n_461;
  wire Decode_I_n_462;
  wire Decode_I_n_463;
  wire Decode_I_n_464;
  wire Decode_I_n_465;
  wire Decode_I_n_466;
  wire Decode_I_n_467;
  wire Decode_I_n_468;
  wire Decode_I_n_469;
  wire Decode_I_n_470;
  wire Decode_I_n_471;
  wire Decode_I_n_74;
  wire [0:0]E;
  wire EX_ALU_Sel_Logic;
  wire EX_Enable_ALU;
  wire [0:31]EX_Fwd;
  wire [0:31]EX_Op3;
  wire Hibernate;
  wire IReady;
  wire [0:31]Instr;
  wire [40:0]LOCKSTEP_Master_Out;
  wire MEM_DataBus_Ready;
  wire [0:31]MEM_Fwd;
  wire [0:31]MEM_PC;
  wire M_AXI_DP_ARREADY;
  wire M_AXI_DP_AWREADY;
  wire M_AXI_DP_BVALID;
  wire [31:0]M_AXI_DP_RDATA;
  wire M_AXI_DP_RVALID;
  wire M_AXI_DP_WREADY;
  wire \Operand_Select_I/I0 ;
  wire \Operand_Select_I/I1 ;
  wire Pause;
  wire Pause_Ack;
  wire \PreFetch_Buffer_I1/I139_out ;
  wire [0:0]\PreFetch_Buffer_I1/if_predecode ;
  wire \PreFetch_Buffer_I1/p_1_in49_in ;
  wire [0:1]Reset_Mode;
  wire SRI;
  wire Scan_En;
  wire Scan_Reset;
  wire Scan_Reset_Sel;
  wire \Shift_Logic_Module_I/I4 ;
  wire Sleep;
  wire Sleep_Decode;
  wire Sleep_Out;
  wire Status_Reg_En;
  wire Suspend;
  wire \Use_DBUS.DAXI_Interface_I1_n_14 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_15 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_16 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_17 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_18 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_19 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_20 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_21 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_22 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_23 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_24 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_25 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_26 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_27 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_28 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_29 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_30 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_31 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_32 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_33 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_34 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_35 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_36 ;
  wire \Use_DBUS.DAXI_Interface_I1_n_37 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_38 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_39 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_40 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_42 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_43 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_44 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_50 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_58 ;
  wire \Use_Debug_Logic.Master_Core.Debug_Perf_n_59 ;
  wire [0:0]\Using_FPGA.Native ;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire active_access;
  wire active_access_d1;
  wire dbg_clean_stop;
  wire dbg_stop_i;
  wire ex_Exception_Taken;
  wire [28:30]ex_MSR;
  wire ex_MSR_Load_ALU_C;
  wire ex_MSR_Load_LWX_SWX_C;
  wire ex_MSR_Load_Shift_C;
  wire ex_MSR_Set_SW_BIP;
  wire [0:1]ex_alu_op;
  wire ex_byte_access;
  wire ex_cmp_op;
  wire [30:31]ex_databus_addr;
  wire ex_doublet_access;
  wire ex_exception_no_load_store_mask;
  wire ex_is_load_instr_s;
  wire ex_load_shift_carry;
  wire ex_move_to_MSR_instr;
  wire ex_op1_cmp_equal;
  wire ex_op1_cmp_equal_n;
  wire ex_op1_neg;
  wire ex_op1_zero;
  wire ex_reverse_mem_access;
  wire [0:1]ex_sext_op;
  wire ex_swap_byte_instr;
  wire ex_swx_access__0;
  wire ex_unsigned_op;
  wire ex_use_carry;
  wire ex_valid;
  wire \exception_registers_I1/I1 ;
  wire [0:31]gpr_op1;
  wire [0:31]gpr_op2;
  wire [0:31]gpr_op3;
  wire [0:31]ib_data;
  wire [3:3]if_sel_input;
  wire [0:15]imm_reg;
  wire [1:1]instr_rd_reg;
  wire lopt;
  wire lopt_1;
  wire lopt_2;
  wire mem_Exception_Taken;
  wire mem_byte_access;
  wire mem_databus_access;
  wire mem_databus_read;
  wire mem_databus_write;
  wire mem_doublet_access;
  wire mem_sel_msr;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [0:15]of_imm_data;
  wire of_op1_sel_spr;
  wire [0:31]of_op2;
  wire [0:31]of_op3;
  wire of_pause;
  wire [0:31]of_pc;
  wire of_write_imm_reg;
  wire p_1_out;
  wire p_231_in;
  wire p_4_out__0;
  wire [8:31]swap_result;
  wire [0:7]swap_result_reg;
  wire sync_reset;
  wire [0:1]wakeup_i;
  wire wb_Halted;
  wire wb_byte_access;
  wire [24:31]wb_databus_steered_read_data;
  wire [0:31]wb_dlmb_valid_read_data;
  wire [0:31]wb_excep_return_addr;
  wire wb_gpr_wr_dbg;
  wire [0:31]wb_mem_result;
  wire wb_pc_valid;
  wire wb_piperun;
  wire wb_read_imm_reg;
  wire wb_read_imm_reg_1;
  wire wb_read_msb_doublet_sel;

  assign Dbg_Reg_En_0_sp_1 = Dbg_Reg_En_0_sn_1;
  design_1_microblaze_0_0_Data_Flow_gti Data_Flow_I
       (.Clk(Clk),
        .D({\Operand_Select_I/I0 ,Decode_I_n_364,Decode_I_n_365,Decode_I_n_366,Decode_I_n_367,Decode_I_n_368,Decode_I_n_369,Decode_I_n_370,Decode_I_n_371,Decode_I_n_372,Decode_I_n_373,Decode_I_n_374,Decode_I_n_375,Decode_I_n_376,Decode_I_n_377,Decode_I_n_378,Decode_I_n_379,Decode_I_n_380,Decode_I_n_381,Decode_I_n_382,Decode_I_n_383,Decode_I_n_384,Decode_I_n_385,Decode_I_n_386,Decode_I_n_387,Decode_I_n_388,Decode_I_n_389,Decode_I_n_390,Decode_I_n_391,Decode_I_n_392,Decode_I_n_393,Decode_I_n_394}),
        .DI(D[117]),
        .DI_0(\ALU_I/DI ),
        .E(of_write_imm_reg),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .\EX_Branch_CMP_Op1_reg[0] (ex_op1_neg),
        .\EX_Branch_CMP_Op1_reg[0]_0 (D[107]),
        .\EX_Branch_CMP_Op1_reg[0]_1 (D[106]),
        .\EX_Branch_CMP_Op1_reg[10] (D[97]),
        .\EX_Branch_CMP_Op1_reg[10]_0 (D[96]),
        .\EX_Branch_CMP_Op1_reg[12] (D[95]),
        .\EX_Branch_CMP_Op1_reg[12]_0 (D[94]),
        .\EX_Branch_CMP_Op1_reg[14] (D[93]),
        .\EX_Branch_CMP_Op1_reg[14]_0 (D[92]),
        .\EX_Branch_CMP_Op1_reg[18] (D[116]),
        .\EX_Branch_CMP_Op1_reg[18]_0 (D[115:111]),
        .\EX_Branch_CMP_Op1_reg[24] (D[83]),
        .\EX_Branch_CMP_Op1_reg[24]_0 (D[82]),
        .\EX_Branch_CMP_Op1_reg[26] (D[81]),
        .\EX_Branch_CMP_Op1_reg[26]_0 (D[80]),
        .\EX_Branch_CMP_Op1_reg[28] (D[79]),
        .\EX_Branch_CMP_Op1_reg[28]_0 (D[78]),
        .\EX_Branch_CMP_Op1_reg[2] (D[105]),
        .\EX_Branch_CMP_Op1_reg[2]_0 (D[104]),
        .\EX_Branch_CMP_Op1_reg[30] (D[77]),
        .\EX_Branch_CMP_Op1_reg[30]_0 (D[76]),
        .\EX_Branch_CMP_Op1_reg[4] (D[103]),
        .\EX_Branch_CMP_Op1_reg[4]_0 (D[102]),
        .\EX_Branch_CMP_Op1_reg[6] (D[101]),
        .\EX_Branch_CMP_Op1_reg[6]_0 (D[100]),
        .\EX_Branch_CMP_Op1_reg[8] (D[99]),
        .\EX_Branch_CMP_Op1_reg[8]_0 (D[98]),
        .EX_Enable_ALU(EX_Enable_ALU),
        .EX_Fwd(EX_Fwd),
        .\EX_Op1_reg[0] ({Data_Flow_I_n_0,Data_Flow_I_n_1,Data_Flow_I_n_2,Data_Flow_I_n_3,Data_Flow_I_n_4,Data_Flow_I_n_5,Data_Flow_I_n_6,Data_Flow_I_n_7,Data_Flow_I_n_8,Data_Flow_I_n_9,Data_Flow_I_n_10,Data_Flow_I_n_11,Data_Flow_I_n_12,Data_Flow_I_n_13,Data_Flow_I_n_14,Data_Flow_I_n_15,Data_Flow_I_n_16,Data_Flow_I_n_17,Data_Flow_I_n_18,Data_Flow_I_n_19,Data_Flow_I_n_20,Data_Flow_I_n_21,Data_Flow_I_n_22,Data_Flow_I_n_23,Data_Flow_I_n_24,Data_Flow_I_n_25,Data_Flow_I_n_26,Data_Flow_I_n_27,Data_Flow_I_n_28,Data_Flow_I_n_29,Data_Flow_I_n_30,Data_Flow_I_n_31}),
        .\EX_Op1_reg[10] (Decode_I_n_462),
        .\EX_Op1_reg[11] (Decode_I_n_461),
        .\EX_Op1_reg[12] (Decode_I_n_460),
        .\EX_Op1_reg[13] (Decode_I_n_459),
        .\EX_Op1_reg[14] (Decode_I_n_458),
        .\EX_Op1_reg[15] (Decode_I_n_457),
        .\EX_Op1_reg[16] (Decode_I_n_456),
        .\EX_Op1_reg[17] (Decode_I_n_455),
        .\EX_Op1_reg[18] (Decode_I_n_454),
        .\EX_Op1_reg[19] (Decode_I_n_453),
        .\EX_Op1_reg[1] (Decode_I_n_471),
        .\EX_Op1_reg[20] (Decode_I_n_452),
        .\EX_Op1_reg[21] (Decode_I_n_451),
        .\EX_Op1_reg[22] (Decode_I_n_450),
        .\EX_Op1_reg[23] (Decode_I_n_449),
        .\EX_Op1_reg[24] (Data_Flow_I_n_33),
        .\EX_Op1_reg[24]_0 (Decode_I_n_448),
        .\EX_Op1_reg[25] (Decode_I_n_447),
        .\EX_Op1_reg[26] (Decode_I_n_446),
        .\EX_Op1_reg[27] (Decode_I_n_445),
        .\EX_Op1_reg[28] (Data_Flow_I_n_188),
        .\EX_Op1_reg[28]_0 (Decode_I_n_444),
        .\EX_Op1_reg[29] (Decode_I_n_443),
        .\EX_Op1_reg[2] (Decode_I_n_470),
        .\EX_Op1_reg[30] (Decode_I_n_442),
        .\EX_Op1_reg[31] (Decode_I_n_441),
        .\EX_Op1_reg[3] (Decode_I_n_469),
        .\EX_Op1_reg[4] (Decode_I_n_468),
        .\EX_Op1_reg[5] (Decode_I_n_467),
        .\EX_Op1_reg[6] (Decode_I_n_466),
        .\EX_Op1_reg[7] (Decode_I_n_465),
        .\EX_Op1_reg[8] (Decode_I_n_464),
        .\EX_Op1_reg[9] (Decode_I_n_463),
        .\EX_Op2_reg[0] ({D[323:292],D[275:268],D[256:253],D[219:184],D[148],D[110:108],D[91:84]}),
        .\EX_Op2_reg[0]_0 ({of_op2[0],of_op2[1],of_op2[2],of_op2[3],of_op2[4],of_op2[5],of_op2[6],of_op2[7],of_op2[8],of_op2[9],of_op2[10],of_op2[11],of_op2[12],of_op2[13],of_op2[14],of_op2[15],of_op2[16],of_op2[17],of_op2[18],of_op2[19],of_op2[20],of_op2[21],of_op2[22],of_op2[23],of_op2[24],of_op2[25],of_op2[26],of_op2[27],of_op2[28],of_op2[29],of_op2[30],of_op2[31]}),
        .\EX_Op3_reg[0] ({EX_Op3[0],EX_Op3[1],EX_Op3[2],EX_Op3[3],EX_Op3[4],EX_Op3[5],EX_Op3[6],EX_Op3[7],EX_Op3[8],EX_Op3[9],EX_Op3[10],EX_Op3[11],EX_Op3[12],EX_Op3[13],EX_Op3[14],EX_Op3[15],EX_Op3[16],EX_Op3[17],EX_Op3[18],EX_Op3[19],EX_Op3[20],EX_Op3[21],EX_Op3[22],EX_Op3[23],EX_Op3[24],EX_Op3[25],EX_Op3[26],EX_Op3[27],EX_Op3[28],EX_Op3[29],EX_Op3[30],EX_Op3[31]}),
        .\EX_Op3_reg[0]_0 ({of_op3[0],of_op3[1],of_op3[2],of_op3[3],of_op3[4],of_op3[5],of_op3[6],of_op3[7],of_op3[8],of_op3[9],of_op3[10],of_op3[11],of_op3[12],of_op3[13],of_op3[14],of_op3[15],of_op3[16],of_op3[17],of_op3[18],of_op3[19],of_op3[20],of_op3[21],of_op3[22],of_op3[23],of_op3[24],of_op3[25],of_op3[26],of_op3[27],of_op3[28],of_op3[29],of_op3[30],of_op3[31]}),
        .\EX_Op3_reg[31] (E),
        .GPR_Op1(gpr_op1),
        .GPR_Op2(gpr_op2),
        .GPR_Op3(gpr_op3),
        .I1(\Operand_Select_I/I1 ),
        .I1_1(\exception_registers_I1/I1 ),
        .\LOCKSTEP_Out_reg[3023] (\Use_DBUS.DAXI_Interface_I1_n_14 ),
        .\LOCKSTEP_Out_reg[3024] (\Use_DBUS.DAXI_Interface_I1_n_15 ),
        .\LOCKSTEP_Out_reg[3025] (\Use_DBUS.DAXI_Interface_I1_n_16 ),
        .\LOCKSTEP_Out_reg[3026] (\Use_DBUS.DAXI_Interface_I1_n_17 ),
        .\LOCKSTEP_Out_reg[3027] (\Use_DBUS.DAXI_Interface_I1_n_18 ),
        .\LOCKSTEP_Out_reg[3028] (\Use_DBUS.DAXI_Interface_I1_n_19 ),
        .\LOCKSTEP_Out_reg[3029] (\Use_DBUS.DAXI_Interface_I1_n_20 ),
        .\LOCKSTEP_Out_reg[3030] (D[75]),
        .\LOCKSTEP_Out_reg[3030]_0 (\Use_DBUS.DAXI_Interface_I1_n_21 ),
        .\MEM_DataBus_Write_Data_reg[0] ({D[291:276],D[267:260]}),
        .MEM_Fwd(MEM_Fwd),
        .\No_Long.Reverse_Mem_Accesses.wb_read_lsb_1_sel_reg[0] (Data_Flow_I_n_185),
        .\No_Long.Reverse_Mem_Accesses.wb_read_lsb_sel_reg[0] ({Data_Flow_I_n_429,Data_Flow_I_n_430}),
        .Q({ex_alu_op[0],ex_alu_op[1]}),
        .R(\Data_Flow_Logic_I/R ),
        .SR(\Data_Flow_Logic_I/WB_MEM_Result0 ),
        .\Using_FPGA.Native (D[118]),
        .\Using_FPGA.Native_0 (D[119]),
        .\Using_FPGA.Native_1 (D[120]),
        .\Using_FPGA.Native_10 (D[129]),
        .\Using_FPGA.Native_11 (D[130]),
        .\Using_FPGA.Native_12 (D[131]),
        .\Using_FPGA.Native_13 (D[132]),
        .\Using_FPGA.Native_14 (D[133]),
        .\Using_FPGA.Native_15 (D[134]),
        .\Using_FPGA.Native_16 (D[135]),
        .\Using_FPGA.Native_17 (D[136]),
        .\Using_FPGA.Native_18 (D[137]),
        .\Using_FPGA.Native_19 (D[138]),
        .\Using_FPGA.Native_2 (D[121]),
        .\Using_FPGA.Native_20 (D[139]),
        .\Using_FPGA.Native_21 (D[140]),
        .\Using_FPGA.Native_22 (D[141]),
        .\Using_FPGA.Native_23 (D[142]),
        .\Using_FPGA.Native_24 (D[143]),
        .\Using_FPGA.Native_25 (D[144]),
        .\Using_FPGA.Native_26 (D[145]),
        .\Using_FPGA.Native_27 (D[146]),
        .\Using_FPGA.Native_28 (D[147]),
        .\Using_FPGA.Native_29 ({wb_excep_return_addr[0],wb_excep_return_addr[1],wb_excep_return_addr[2],wb_excep_return_addr[3],wb_excep_return_addr[4],wb_excep_return_addr[5],wb_excep_return_addr[6],wb_excep_return_addr[7],wb_excep_return_addr[8],wb_excep_return_addr[9],wb_excep_return_addr[10],wb_excep_return_addr[11],wb_excep_return_addr[12],wb_excep_return_addr[13],wb_excep_return_addr[14],wb_excep_return_addr[15],wb_excep_return_addr[24],wb_excep_return_addr[25],wb_excep_return_addr[26],wb_excep_return_addr[27],wb_excep_return_addr[28],wb_excep_return_addr[29],wb_excep_return_addr[30],wb_excep_return_addr[31]}),
        .\Using_FPGA.Native_3 (D[122]),
        .\Using_FPGA.Native_30 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_31 (Decode_I_n_263),
        .\Using_FPGA.Native_32 (D[74]),
        .\Using_FPGA.Native_33 ({MEM_PC[0],MEM_PC[1],MEM_PC[2],MEM_PC[3],MEM_PC[4],MEM_PC[5],MEM_PC[6],MEM_PC[7],MEM_PC[8],MEM_PC[9],MEM_PC[10],MEM_PC[11],MEM_PC[12],MEM_PC[13],MEM_PC[14],MEM_PC[15],MEM_PC[16],MEM_PC[17],MEM_PC[18],MEM_PC[19],MEM_PC[20],MEM_PC[21],MEM_PC[22],MEM_PC[23],MEM_PC[24],MEM_PC[25],MEM_PC[26],MEM_PC[27],MEM_PC[28],MEM_PC[29],MEM_PC[30],MEM_PC[31]}),
        .\Using_FPGA.Native_34 (Decode_I_n_439),
        .\Using_FPGA.Native_35 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_36 (Decode_I_n_247),
        .\Using_FPGA.Native_37 (LOCKSTEP_Master_Out[36]),
        .\Using_FPGA.Native_38 (LOCKSTEP_Master_Out[32]),
        .\Using_FPGA.Native_4 (D[123]),
        .\Using_FPGA.Native_5 (D[124]),
        .\Using_FPGA.Native_6 (D[125]),
        .\Using_FPGA.Native_7 (D[126]),
        .\Using_FPGA.Native_8 (D[127]),
        .\Using_FPGA.Native_9 (D[128]),
        .\Using_FPGA.Native_i_3__31 ({ex_sext_op[0],ex_sext_op[1]}),
        .\WB_MEM_Result_reg[0] ({wb_mem_result[0],wb_mem_result[1],wb_mem_result[2],wb_mem_result[3],wb_mem_result[4],wb_mem_result[5],wb_mem_result[6],wb_mem_result[7],wb_mem_result[8],wb_mem_result[9],wb_mem_result[10],wb_mem_result[11],wb_mem_result[12],wb_mem_result[13],wb_mem_result[14],wb_mem_result[15],wb_mem_result[24],wb_mem_result[25],wb_mem_result[26],wb_mem_result[27],wb_mem_result[28],wb_mem_result[29],wb_mem_result[30],wb_mem_result[31]}),
        .\data_rd_reg_reg[23] (\Use_Debug_Logic.Master_Core.Debug_Perf_n_40 ),
        .\data_rd_reg_reg[23]_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_39 ),
        .ex_MSR({ex_MSR[28],ex_MSR[29],ex_MSR[30]}),
        .ex_MSR_Load_ALU_C(ex_MSR_Load_ALU_C),
        .ex_MSR_Load_LWX_SWX_C(ex_MSR_Load_LWX_SWX_C),
        .ex_MSR_Load_Shift_C(ex_MSR_Load_Shift_C),
        .ex_byte_access(ex_byte_access),
        .ex_cmp_op(ex_cmp_op),
        .ex_databus_addr({ex_databus_addr[30],ex_databus_addr[31]}),
        .ex_doublet_access(ex_doublet_access),
        .ex_move_to_MSR_instr(ex_move_to_MSR_instr),
        .ex_op1_cmp_equal(ex_op1_cmp_equal),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .ex_op1_zero(ex_op1_zero),
        .ex_reverse_mem_access(ex_reverse_mem_access),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .ex_swx_access__0(ex_swx_access__0),
        .ex_unsigned_op(ex_unsigned_op),
        .ex_use_carry(ex_use_carry),
        .ex_valid(ex_valid),
        .\imm_reg_reg[0] ({imm_reg[0],imm_reg[1],imm_reg[2],imm_reg[3],imm_reg[4],imm_reg[5],imm_reg[6],imm_reg[7],imm_reg[8],imm_reg[9],imm_reg[10],imm_reg[11],imm_reg[12],imm_reg[13],imm_reg[14],imm_reg[15]}),
        .in0(Decode_I_n_437),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_2(lopt_2),
        .mem_byte_access(mem_byte_access),
        .mem_doublet_access(mem_doublet_access),
        .mem_sel_msr(mem_sel_msr),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data),
        .of_op1_sel_spr(of_op1_sel_spr),
        .out(\Shift_Logic_Module_I/I4 ),
        .p_231_in(p_231_in),
        .swap_result({swap_result[8],swap_result[9],swap_result[10],swap_result[11],swap_result[12],swap_result[13],swap_result[14],swap_result[15],swap_result[16],swap_result[17],swap_result[18],swap_result[19],swap_result[20],swap_result[21],swap_result[22],swap_result[23],swap_result[24],swap_result[25],swap_result[26],swap_result[27],swap_result[28],swap_result[29],swap_result[30],swap_result[31]}),
        .swap_result_reg(swap_result_reg),
        .sync_reset(sync_reset),
        .\wb_MSR_i_reg[30] (wb_piperun),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg({Data_Flow_I_n_189,Data_Flow_I_n_190,Data_Flow_I_n_191,Data_Flow_I_n_192,Data_Flow_I_n_193,Data_Flow_I_n_194,Data_Flow_I_n_195,Data_Flow_I_n_196}),
        .wb_read_msb_doublet_sel(wb_read_msb_doublet_sel));
  design_1_microblaze_0_0_Decode_gti Decode_I
       (.Clk(Clk),
        .D({of_pc[0],of_pc[1],of_pc[2],of_pc[3],of_pc[4],of_pc[5],of_pc[6],of_pc[7],of_pc[8],of_pc[9],of_pc[10],of_pc[11],of_pc[12],of_pc[13],of_pc[14],of_pc[15],of_pc[16],of_pc[17],of_pc[18],of_pc[19],of_pc[20],of_pc[21],of_pc[22],of_pc[23],of_pc[24],of_pc[25],of_pc[26],of_pc[27],of_pc[28],of_pc[29],of_pc[30],of_pc[31]}),
        .DI(\ALU_I/DI ),
        .DReady(DReady),
        .DWait(DWait),
        .E(of_write_imm_reg),
        .\EX_ALU_Op_reg[0]_0 ({ex_alu_op[0],ex_alu_op[1]}),
        .EX_ALU_Sel_Logic(EX_ALU_Sel_Logic),
        .EX_Enable_ALU(EX_Enable_ALU),
        .EX_Fwd(EX_Fwd),
        .\EX_Op2_reg[0] ({imm_reg[0],imm_reg[1],imm_reg[2],imm_reg[3],imm_reg[4],imm_reg[5],imm_reg[6],imm_reg[7],imm_reg[8],imm_reg[9],imm_reg[10],imm_reg[11],imm_reg[12],imm_reg[13],imm_reg[14],imm_reg[15]}),
        .\EX_Sext_Op_reg[0]_0 ({ex_sext_op[0],ex_sext_op[1]}),
        .GPR_Op1(gpr_op1),
        .GPR_Op2(gpr_op2),
        .GPR_Op3(gpr_op3),
        .Hibernate(Hibernate),
        .I1(\exception_registers_I1/I1 ),
        .I139_out(\PreFetch_Buffer_I1/I139_out ),
        .I1_0(\Operand_Select_I/I1 ),
        .IReady(IReady),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[40],LOCKSTEP_Master_Out[37],LOCKSTEP_Master_Out[35]}),
        .\LOCKSTEP_Out_reg[3007] ({wb_excep_return_addr[0],wb_excep_return_addr[1],wb_excep_return_addr[2],wb_excep_return_addr[3],wb_excep_return_addr[4],wb_excep_return_addr[5],wb_excep_return_addr[6],wb_excep_return_addr[7],wb_excep_return_addr[8],wb_excep_return_addr[9],wb_excep_return_addr[10],wb_excep_return_addr[11],wb_excep_return_addr[12],wb_excep_return_addr[13],wb_excep_return_addr[14],wb_excep_return_addr[15],wb_excep_return_addr[24],wb_excep_return_addr[25],wb_excep_return_addr[26],wb_excep_return_addr[27],wb_excep_return_addr[28],wb_excep_return_addr[29],wb_excep_return_addr[30],wb_excep_return_addr[31]}),
        .\LOCKSTEP_Out_reg[3007]_0 (\Use_DBUS.DAXI_Interface_I1_n_37 ),
        .\LOCKSTEP_Out_reg[3007]_1 ({wb_mem_result[0],wb_mem_result[1],wb_mem_result[2],wb_mem_result[3],wb_mem_result[4],wb_mem_result[5],wb_mem_result[6],wb_mem_result[7],wb_mem_result[8],wb_mem_result[9],wb_mem_result[10],wb_mem_result[11],wb_mem_result[12],wb_mem_result[13],wb_mem_result[14],wb_mem_result[15],wb_mem_result[24],wb_mem_result[25],wb_mem_result[26],wb_mem_result[27],wb_mem_result[28],wb_mem_result[29],wb_mem_result[30],wb_mem_result[31]}),
        .\LOCKSTEP_Out_reg[3008] (\Use_DBUS.DAXI_Interface_I1_n_36 ),
        .\LOCKSTEP_Out_reg[3009] (\Use_DBUS.DAXI_Interface_I1_n_35 ),
        .\LOCKSTEP_Out_reg[3010] (\Use_DBUS.DAXI_Interface_I1_n_34 ),
        .\LOCKSTEP_Out_reg[3011] (\Use_DBUS.DAXI_Interface_I1_n_33 ),
        .\LOCKSTEP_Out_reg[3012] (\Use_DBUS.DAXI_Interface_I1_n_32 ),
        .\LOCKSTEP_Out_reg[3013] (\Use_DBUS.DAXI_Interface_I1_n_31 ),
        .\LOCKSTEP_Out_reg[3014] (\Use_DBUS.DAXI_Interface_I1_n_30 ),
        .\LOCKSTEP_Out_reg[3015] (\Use_DBUS.DAXI_Interface_I1_n_29 ),
        .\LOCKSTEP_Out_reg[3016] (\Use_DBUS.DAXI_Interface_I1_n_28 ),
        .\LOCKSTEP_Out_reg[3017] (\Use_DBUS.DAXI_Interface_I1_n_27 ),
        .\LOCKSTEP_Out_reg[3018] (\Use_DBUS.DAXI_Interface_I1_n_26 ),
        .\LOCKSTEP_Out_reg[3019] (\Use_DBUS.DAXI_Interface_I1_n_25 ),
        .\LOCKSTEP_Out_reg[3020] (\Use_DBUS.DAXI_Interface_I1_n_24 ),
        .\LOCKSTEP_Out_reg[3021] (\Use_DBUS.DAXI_Interface_I1_n_23 ),
        .\LOCKSTEP_Out_reg[3022] (\Use_DBUS.DAXI_Interface_I1_n_22 ),
        .\MEM_DataBus_Addr_reg[0]_0 ({D[323:292],D[258],D[220],D[183:182],D[148:133],D[124:117],D[110:108],D[91:84]}),
        .MEM_DataBus_Ready(MEM_DataBus_Ready),
        .\MEM_DataBus_Write_Data_reg[0] ({EX_Op3[0],EX_Op3[1],EX_Op3[2],EX_Op3[3],EX_Op3[4],EX_Op3[5],EX_Op3[6],EX_Op3[7],EX_Op3[8],EX_Op3[9],EX_Op3[10],EX_Op3[11],EX_Op3[12],EX_Op3[13],EX_Op3[14],EX_Op3[15],EX_Op3[16],EX_Op3[17],EX_Op3[18],EX_Op3[19],EX_Op3[20],EX_Op3[21],EX_Op3[22],EX_Op3[23],EX_Op3[24],EX_Op3[25],EX_Op3[26],EX_Op3[27],EX_Op3[28],EX_Op3[29],EX_Op3[30],EX_Op3[31]}),
        .MEM_DataBus_Write_reg_0(Decode_I_n_424),
        .MEM_DataBus_Write_reg_1(Decode_I_n_425),
        .MEM_DataBus_Write_reg_2(Decode_I_n_426),
        .MEM_Fwd(MEM_Fwd),
        .M_AXI_DP_ARREADY(M_AXI_DP_ARREADY),
        .M_AXI_DP_AWREADY(M_AXI_DP_AWREADY),
        .M_AXI_DP_BVALID(M_AXI_DP_BVALID),
        .M_AXI_DP_BVALID_0(Decode_I_n_423),
        .M_AXI_DP_RVALID(M_AXI_DP_RVALID),
        .M_AXI_DP_WREADY(M_AXI_DP_WREADY),
        .Pause(Pause),
        .Pause_Ack(Pause_Ack),
        .\Performance_Debug_Control.dbg_freeze_nohalt_reg (Decode_I_n_439),
        .\Performance_Debug_Control.dbg_state_nohalt_reg ({D[358:324],D[291:276],D[267:260],D[257],D[252:221],D[181:149],D[116:111],D[107:92],D[83:71]}),
        .\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg (Decode_I_n_438),
        .\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_42 ),
        .Q(\Use_Debug_Logic.Master_Core.Debug_Perf_n_59 ),
        .R(\Data_Flow_Logic_I/R ),
        .Reset_Mode(Reset_Mode),
        .SR(\Data_Flow_Logic_I/WB_MEM_Result0 ),
        .SRI(SRI),
        .\Serial_Dbg_Intf.control_reg_reg[8] (Decode_I_n_430),
        .Sleep(Sleep),
        .Sleep_Decode(Sleep_Decode),
        .Sleep_Out(Sleep_Out),
        .Suspend(Suspend),
        .\Using_FPGA.Native (if_sel_input),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_10 (Decode_I_n_448),
        .\Using_FPGA.Native_11 (Decode_I_n_449),
        .\Using_FPGA.Native_12 (Decode_I_n_450),
        .\Using_FPGA.Native_13 (Decode_I_n_451),
        .\Using_FPGA.Native_14 (Decode_I_n_452),
        .\Using_FPGA.Native_15 (Decode_I_n_453),
        .\Using_FPGA.Native_16 (Decode_I_n_454),
        .\Using_FPGA.Native_17 (Decode_I_n_455),
        .\Using_FPGA.Native_18 (Decode_I_n_456),
        .\Using_FPGA.Native_19 (Decode_I_n_457),
        .\Using_FPGA.Native_2 (Decode_I_n_440),
        .\Using_FPGA.Native_20 (Decode_I_n_458),
        .\Using_FPGA.Native_21 (Decode_I_n_459),
        .\Using_FPGA.Native_22 (Decode_I_n_460),
        .\Using_FPGA.Native_23 (Decode_I_n_461),
        .\Using_FPGA.Native_24 (Decode_I_n_462),
        .\Using_FPGA.Native_25 (Decode_I_n_463),
        .\Using_FPGA.Native_26 (Decode_I_n_464),
        .\Using_FPGA.Native_27 (Decode_I_n_465),
        .\Using_FPGA.Native_28 (Decode_I_n_466),
        .\Using_FPGA.Native_29 (Decode_I_n_467),
        .\Using_FPGA.Native_3 (Decode_I_n_441),
        .\Using_FPGA.Native_30 (Decode_I_n_468),
        .\Using_FPGA.Native_31 (Decode_I_n_469),
        .\Using_FPGA.Native_32 (Decode_I_n_470),
        .\Using_FPGA.Native_33 (Decode_I_n_471),
        .\Using_FPGA.Native_34 (\PreFetch_Buffer_I1/p_1_in49_in ),
        .\Using_FPGA.Native_35 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_50 ),
        .\Using_FPGA.Native_36 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_58 ),
        .\Using_FPGA.Native_37 (ex_op1_neg),
        .\Using_FPGA.Native_38 (Data_Flow_I_n_188),
        .\Using_FPGA.Native_39 (LOCKSTEP_Master_Out[36]),
        .\Using_FPGA.Native_4 (Decode_I_n_442),
        .\Using_FPGA.Native_40 (LOCKSTEP_Master_Out[32]),
        .\Using_FPGA.Native_41 (LOCKSTEP_Master_Out[38]),
        .\Using_FPGA.Native_42 ({Data_Flow_I_n_0,Data_Flow_I_n_1,Data_Flow_I_n_2,Data_Flow_I_n_3,Data_Flow_I_n_4,Data_Flow_I_n_5,Data_Flow_I_n_6,Data_Flow_I_n_7,Data_Flow_I_n_8,Data_Flow_I_n_9,Data_Flow_I_n_10,Data_Flow_I_n_11,Data_Flow_I_n_12,Data_Flow_I_n_13,Data_Flow_I_n_14,Data_Flow_I_n_15,Data_Flow_I_n_16,Data_Flow_I_n_17,Data_Flow_I_n_18,Data_Flow_I_n_19,Data_Flow_I_n_20,Data_Flow_I_n_21,Data_Flow_I_n_22,Data_Flow_I_n_23,Data_Flow_I_n_24,Data_Flow_I_n_25,Data_Flow_I_n_26,Data_Flow_I_n_27,Data_Flow_I_n_28,Data_Flow_I_n_29,Data_Flow_I_n_30,Data_Flow_I_n_31}),
        .\Using_FPGA.Native_43 (Data_Flow_I_n_33),
        .\Using_FPGA.Native_5 (Decode_I_n_443),
        .\Using_FPGA.Native_6 (Decode_I_n_444),
        .\Using_FPGA.Native_7 (Decode_I_n_445),
        .\Using_FPGA.Native_8 (Decode_I_n_446),
        .\Using_FPGA.Native_9 (Decode_I_n_447),
        .Y(ib_data),
        .active_access(active_access),
        .active_access_d1(active_access_d1),
        .active_access_reg(\Use_Debug_Logic.Master_Core.Debug_Perf_n_38 ),
        .\data_rd_reg_reg[0] (\Use_Debug_Logic.Master_Core.Debug_Perf_n_39 ),
        .dbg_clean_stop(dbg_clean_stop),
        .dbg_halt_reset_mode_reg(Decode_I_n_427),
        .dbg_stop_i(dbg_stop_i),
        .ex_Exception_Taken(ex_Exception_Taken),
        .ex_MSR({ex_MSR[28],ex_MSR[29],ex_MSR[30]}),
        .ex_MSR_Load_LWX_SWX_C(ex_MSR_Load_LWX_SWX_C),
        .ex_MSR_Set_SW_BIP(ex_MSR_Set_SW_BIP),
        .ex_byte_access(ex_byte_access),
        .ex_cmp_op(ex_cmp_op),
        .ex_databus_addr({ex_databus_addr[30],ex_databus_addr[31]}),
        .ex_doublet_access(ex_doublet_access),
        .ex_exception_no_load_store_mask(ex_exception_no_load_store_mask),
        .ex_is_load_instr_s(ex_is_load_instr_s),
        .ex_load_alu_carry_reg_0(Decode_I_n_247),
        .ex_load_shift_carry(ex_load_shift_carry),
        .ex_move_to_MSR_instr(ex_move_to_MSR_instr),
        .ex_op1_cmp_equal(ex_op1_cmp_equal),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .ex_op1_zero(ex_op1_zero),
        .ex_reverse_mem_access(ex_reverse_mem_access),
        .ex_sel_alu_i_reg_0({of_op2[0],of_op2[1],of_op2[2],of_op2[3],of_op2[4],of_op2[5],of_op2[6],of_op2[7],of_op2[8],of_op2[9],of_op2[10],of_op2[11],of_op2[12],of_op2[13],of_op2[14],of_op2[15],of_op2[16],of_op2[17],of_op2[18],of_op2[19],of_op2[20],of_op2[21],of_op2[22],of_op2[23],of_op2[24],of_op2[25],of_op2[26],of_op2[27],of_op2[28],of_op2[29],of_op2[30],of_op2[31]}),
        .ex_sel_alu_i_reg_1({of_op3[0],of_op3[1],of_op3[2],of_op3[3],of_op3[4],of_op3[5],of_op3[6],of_op3[7],of_op3[8],of_op3[9],of_op3[10],of_op3[11],of_op3[12],of_op3[13],of_op3[14],of_op3[15],of_op3[16],of_op3[17],of_op3[18],of_op3[19],of_op3[20],of_op3[21],of_op3[22],of_op3[23],of_op3[24],of_op3[25],of_op3[26],of_op3[27],of_op3[28],of_op3[29],of_op3[30],of_op3[31]}),
        .ex_sel_alu_i_reg_2({\Operand_Select_I/I0 ,Decode_I_n_364,Decode_I_n_365,Decode_I_n_366,Decode_I_n_367,Decode_I_n_368,Decode_I_n_369,Decode_I_n_370,Decode_I_n_371,Decode_I_n_372,Decode_I_n_373,Decode_I_n_374,Decode_I_n_375,Decode_I_n_376,Decode_I_n_377,Decode_I_n_378,Decode_I_n_379,Decode_I_n_380,Decode_I_n_381,Decode_I_n_382,Decode_I_n_383,Decode_I_n_384,Decode_I_n_385,Decode_I_n_386,Decode_I_n_387,Decode_I_n_388,Decode_I_n_389,Decode_I_n_390,Decode_I_n_391,Decode_I_n_392,Decode_I_n_393,Decode_I_n_394}),
        .ex_set_bip_reg_0(Decode_I_n_74),
        .ex_set_bip_reg_1(Decode_I_n_263),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .ex_swx_access__0(ex_swx_access__0),
        .ex_unsigned_op(ex_unsigned_op),
        .ex_use_carry(ex_use_carry),
        .ex_valid(ex_valid),
        .exception_reg(instr_rd_reg),
        .if_missed_fetch_reg_0(\Use_Debug_Logic.Master_Core.Debug_Perf_n_43 ),
        .if_missed_fetch_reg_1(\Use_Debug_Logic.Master_Core.Debug_Perf_n_40 ),
        .in(\PreFetch_Buffer_I1/if_predecode ),
        .in0(Decode_I_n_437),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_2(lopt_2),
        .mem_Exception_Taken(mem_Exception_Taken),
        .mem_byte_access(mem_byte_access),
        .mem_databus_access(mem_databus_access),
        .mem_databus_read(mem_databus_read),
        .mem_databus_write(mem_databus_write),
        .mem_doublet_access(mem_doublet_access),
        .\mem_pc_i_reg[0] ({MEM_PC[0],MEM_PC[1],MEM_PC[2],MEM_PC[3],MEM_PC[4],MEM_PC[5],MEM_PC[6],MEM_PC[7],MEM_PC[8],MEM_PC[9],MEM_PC[10],MEM_PC[11],MEM_PC[12],MEM_PC[13],MEM_PC[14],MEM_PC[15],MEM_PC[16],MEM_PC[17],MEM_PC[18],MEM_PC[19],MEM_PC[20],MEM_PC[21],MEM_PC[22],MEM_PC[23],MEM_PC[24],MEM_PC[25],MEM_PC[26],MEM_PC[27],MEM_PC[28],MEM_PC[29],MEM_PC[30],MEM_PC[31]}),
        .\mem_pc_i_reg[0]_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_44 ),
        .mem_sel_msr(mem_sel_msr),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data),
        .of_op1_sel_spr(of_op1_sel_spr),
        .of_pause(of_pause),
        .of_pause_reg_0(E),
        .out(\Shift_Logic_Module_I/I4 ),
        .p_231_in(p_231_in),
        .p_4_out__0(p_4_out__0),
        .swap_result({swap_result[8],swap_result[9],swap_result[10],swap_result[11],swap_result[12],swap_result[13],swap_result[14],swap_result[15],swap_result[16],swap_result[17],swap_result[18],swap_result[19],swap_result[20],swap_result[21],swap_result[22],swap_result[23],swap_result[24],swap_result[25],swap_result[26],swap_result[27],swap_result[28],swap_result[29],swap_result[30],swap_result[31]}),
        .swap_result_reg(swap_result_reg),
        .sync_reset(sync_reset),
        .wakeup_i(wakeup_i),
        .wb_Halted(wb_Halted),
        .wb_PipeRun_i_reg_0(wb_piperun),
        .wb_byte_access(wb_byte_access),
        .wb_databus_steered_read_data({wb_databus_steered_read_data[24],wb_databus_steered_read_data[25],wb_databus_steered_read_data[26],wb_databus_steered_read_data[27],wb_databus_steered_read_data[28],wb_databus_steered_read_data[29],wb_databus_steered_read_data[30],wb_databus_steered_read_data[31]}),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg_0({Decode_I_n_396,Decode_I_n_397,Decode_I_n_398,Decode_I_n_399,Decode_I_n_400,Decode_I_n_401,Decode_I_n_402,Decode_I_n_403,Decode_I_n_404,Decode_I_n_405,Decode_I_n_406,Decode_I_n_407,Decode_I_n_408,Decode_I_n_409,Decode_I_n_410,Decode_I_n_411,Decode_I_n_412,Decode_I_n_413,Decode_I_n_414,Decode_I_n_415,Decode_I_n_416,Decode_I_n_417,Decode_I_n_418,Decode_I_n_419}),
        .wb_pc_valid(wb_pc_valid),
        .wb_read_imm_reg(wb_read_imm_reg),
        .wb_read_imm_reg_1(wb_read_imm_reg_1),
        .wb_valid_reg_0(Decode_I_n_258));
  design_1_microblaze_0_0_DAXI_interface \Use_DBUS.DAXI_Interface_I1 
       (.Clk(Clk),
        .D({D[220],D[183:182]}),
        .DReady(DReady),
        .\LOCKSTEP_Out_reg[3023] (Data_Flow_I_n_185),
        .\LOCKSTEP_Out_reg[3031] ({Data_Flow_I_n_429,Data_Flow_I_n_430}),
        .MEM_DataBus_Ready(MEM_DataBus_Ready),
        .M_AXI_DP_ARVALID_i_reg_0(Decode_I_n_426),
        .M_AXI_DP_AWVALID_i_reg_0(Decode_I_n_425),
        .M_AXI_DP_BVALID(M_AXI_DP_BVALID),
        .M_AXI_DP_RDATA(M_AXI_DP_RDATA),
        .M_AXI_DP_RVALID(M_AXI_DP_RVALID),
        .M_AXI_DP_WVALID_i_reg_0(Decode_I_n_424),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg (\Use_DBUS.DAXI_Interface_I1_n_14 ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_0 (\Use_DBUS.DAXI_Interface_I1_n_15 ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_1 (\Use_DBUS.DAXI_Interface_I1_n_16 ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_2 (\Use_DBUS.DAXI_Interface_I1_n_17 ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_3 (\Use_DBUS.DAXI_Interface_I1_n_18 ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_4 (\Use_DBUS.DAXI_Interface_I1_n_19 ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_5 (\Use_DBUS.DAXI_Interface_I1_n_20 ),
        .\No_Long.Reverse_Mem_Accesses.wb_read_msb_doublet_sel_reg_6 (\Use_DBUS.DAXI_Interface_I1_n_21 ),
        .Q({wb_dlmb_valid_read_data[0],wb_dlmb_valid_read_data[1],wb_dlmb_valid_read_data[2],wb_dlmb_valid_read_data[3],wb_dlmb_valid_read_data[4],wb_dlmb_valid_read_data[5],wb_dlmb_valid_read_data[6],wb_dlmb_valid_read_data[7],wb_dlmb_valid_read_data[8],wb_dlmb_valid_read_data[9],wb_dlmb_valid_read_data[10],wb_dlmb_valid_read_data[11],wb_dlmb_valid_read_data[12],wb_dlmb_valid_read_data[13],wb_dlmb_valid_read_data[14],wb_dlmb_valid_read_data[15],wb_dlmb_valid_read_data[16],wb_dlmb_valid_read_data[17],wb_dlmb_valid_read_data[18],wb_dlmb_valid_read_data[19],wb_dlmb_valid_read_data[20],wb_dlmb_valid_read_data[21],wb_dlmb_valid_read_data[22],wb_dlmb_valid_read_data[23],wb_dlmb_valid_read_data[24],wb_dlmb_valid_read_data[25],wb_dlmb_valid_read_data[26],wb_dlmb_valid_read_data[27],wb_dlmb_valid_read_data[28],wb_dlmb_valid_read_data[29],wb_dlmb_valid_read_data[30],wb_dlmb_valid_read_data[31]}),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[16] (\Use_DBUS.DAXI_Interface_I1_n_29 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[17] (\Use_DBUS.DAXI_Interface_I1_n_28 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[18] (\Use_DBUS.DAXI_Interface_I1_n_27 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[19] (\Use_DBUS.DAXI_Interface_I1_n_26 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[20] (\Use_DBUS.DAXI_Interface_I1_n_25 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[21] (\Use_DBUS.DAXI_Interface_I1_n_24 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[22] (\Use_DBUS.DAXI_Interface_I1_n_23 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[23] (\Use_DBUS.DAXI_Interface_I1_n_22 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[24] (\Use_DBUS.DAXI_Interface_I1_n_37 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[25] (\Use_DBUS.DAXI_Interface_I1_n_36 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[26] (\Use_DBUS.DAXI_Interface_I1_n_35 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[27] (\Use_DBUS.DAXI_Interface_I1_n_34 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[28] (\Use_DBUS.DAXI_Interface_I1_n_33 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[29] (\Use_DBUS.DAXI_Interface_I1_n_32 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[30] (\Use_DBUS.DAXI_Interface_I1_n_31 ),
        .\Use_DLMB.wb_dlmb_valid_read_data_reg[31] (\Use_DBUS.DAXI_Interface_I1_n_30 ),
        .active_access(active_access),
        .active_access_d1(active_access_d1),
        .active_access_reg_0(Decode_I_n_423),
        .sync_reset(sync_reset),
        .wb_databus_steered_read_data({wb_databus_steered_read_data[24],wb_databus_steered_read_data[25],wb_databus_steered_read_data[26],wb_databus_steered_read_data[27],wb_databus_steered_read_data[28],wb_databus_steered_read_data[29],wb_databus_steered_read_data[30],wb_databus_steered_read_data[31]}),
        .wb_read_msb_doublet_sel(wb_read_msb_doublet_sel));
  design_1_microblaze_0_0_MB_AND2B1L \Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1 
       (.D(D[259]),
        .E(\Using_FPGA.Native ),
        .SRI(SRI));
  LUT2 #(
    .INIT(4'hB)) 
    \Use_DLMB.wb_dlmb_valid_read_data[0]_i_1 
       (.I0(sync_reset),
        .I1(DReady),
        .O(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[0] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[0]),
        .Q(wb_dlmb_valid_read_data[0]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[10] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[10]),
        .Q(wb_dlmb_valid_read_data[10]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[11] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[11]),
        .Q(wb_dlmb_valid_read_data[11]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[12] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[12]),
        .Q(wb_dlmb_valid_read_data[12]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[13] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[13]),
        .Q(wb_dlmb_valid_read_data[13]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[14] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[14]),
        .Q(wb_dlmb_valid_read_data[14]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[15] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[15]),
        .Q(wb_dlmb_valid_read_data[15]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[16] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[16]),
        .Q(wb_dlmb_valid_read_data[16]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[17] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[17]),
        .Q(wb_dlmb_valid_read_data[17]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[18] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[18]),
        .Q(wb_dlmb_valid_read_data[18]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[19] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[19]),
        .Q(wb_dlmb_valid_read_data[19]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[1]),
        .Q(wb_dlmb_valid_read_data[1]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[20] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[20]),
        .Q(wb_dlmb_valid_read_data[20]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[21] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[21]),
        .Q(wb_dlmb_valid_read_data[21]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[22] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[22]),
        .Q(wb_dlmb_valid_read_data[22]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[23] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[23]),
        .Q(wb_dlmb_valid_read_data[23]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[24] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[24]),
        .Q(wb_dlmb_valid_read_data[24]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[25] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[25]),
        .Q(wb_dlmb_valid_read_data[25]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[26] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[26]),
        .Q(wb_dlmb_valid_read_data[26]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[27] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[27]),
        .Q(wb_dlmb_valid_read_data[27]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[28] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[28]),
        .Q(wb_dlmb_valid_read_data[28]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[29] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[29]),
        .Q(wb_dlmb_valid_read_data[29]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[2]),
        .Q(wb_dlmb_valid_read_data[2]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[30] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[30]),
        .Q(wb_dlmb_valid_read_data[30]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[31] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[31]),
        .Q(wb_dlmb_valid_read_data[31]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[3] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[3]),
        .Q(wb_dlmb_valid_read_data[3]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[4] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[4]),
        .Q(wb_dlmb_valid_read_data[4]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[5] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[5]),
        .Q(wb_dlmb_valid_read_data[5]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[6] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[6]),
        .Q(wb_dlmb_valid_read_data[6]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[7] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[7]),
        .Q(wb_dlmb_valid_read_data[7]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[8] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[8]),
        .Q(wb_dlmb_valid_read_data[8]),
        .R(p_1_out));
  FDRE \Use_DLMB.wb_dlmb_valid_read_data_reg[9] 
       (.C(Clk),
        .CE(1'b1),
        .D(Data_Read[9]),
        .Q(wb_dlmb_valid_read_data[9]),
        .R(p_1_out));
  design_1_microblaze_0_0_Debug \Use_Debug_Logic.Master_Core.Debug_Perf 
       (.Address(of_pc),
        .Clk(Clk),
        .Config_Reg_En(Config_Reg_En),
        .D({D[358:357],D[71]}),
        .Data_Read_Reg_En(Data_Read_Reg_En),
        .Dbg_Capture(Dbg_Capture),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_Reg_En(Dbg_Reg_En),
        .Dbg_Reg_En_0_sp_1(Dbg_Reg_En_0_sn_1),
        .Dbg_Shift(Dbg_Shift),
        .Dbg_Stop(Dbg_Stop),
        .Dbg_TDI(Dbg_TDI),
        .Dbg_TDO(Dbg_TDO),
        .Dbg_Trig_Ack_In(Dbg_Trig_Ack_In),
        .Dbg_Trig_Ack_Out(Dbg_Trig_Ack_Out),
        .Dbg_Trig_In(Dbg_Trig_In),
        .Dbg_Trig_Out(Dbg_Trig_Out),
        .Dbg_Update(Dbg_Update),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[39:38],LOCKSTEP_Master_Out[36],LOCKSTEP_Master_Out[34:0]}),
        .Pause(Pause),
        .\Performance_Debug_Control.dbg_freeze_nohalt_reg_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_44 ),
        .\Performance_Debug_Control.dbg_state_nohalt_reg_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_43 ),
        .\Performance_Debug_Control.dbg_stop_if_delay_i_reg_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_50 ),
        .\Performance_Debug_Control.dbg_stop_if_delay_i_reg_1 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_58 ),
        .\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_40 ),
        .\Performance_Debug_Control.dbg_stop_instr_fetch_nohalt_reg_1 (Decode_I_n_427),
        .\Performance_Debug_Control.ex_brki_hit_reg_0 (Decode_I_n_430),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 (D[258]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 (Decode_I_n_440),
        .\Performance_Debug_Control.m0_dbg_hit_reg[0]_0 (\Using_FPGA.Native_0 ),
        .\Performance_Debug_Control.wb_dbg_hit_reg[0]_0 (\Using_FPGA.Native ),
        .Q(\Use_Debug_Logic.Master_Core.Debug_Perf_n_59 ),
        .Reset_Mode(Reset_Mode),
        .Scan_En(Scan_En),
        .Scan_Reset(Scan_Reset),
        .Scan_Reset_Sel(Scan_Reset_Sel),
        .\Serial_Dbg_Intf.force_stop_cmd_i_reg_0 (\Use_Debug_Logic.Master_Core.Debug_Perf_n_38 ),
        .\Serial_Dbg_Intf.status_reg_reg[22]_0 (mem_databus_access),
        .Sleep(Sleep),
        .Sleep_Decode(Sleep_Decode),
        .Sleep_Out(Sleep_Out),
        .Status_Reg_En(Status_Reg_En),
        .\Using_FPGA.Native_i_2__21 (Decode_I_n_247),
        .\Using_LWX_SWX_instr.ex_reservation_i_3 (Decode_I_n_74),
        .\data_rd_reg_reg[0]_0 ({Decode_I_n_396,Decode_I_n_397,Decode_I_n_398,Decode_I_n_399,Decode_I_n_400,Decode_I_n_401,Decode_I_n_402,Decode_I_n_403,Decode_I_n_404,Decode_I_n_405,Decode_I_n_406,Decode_I_n_407,Decode_I_n_408,Decode_I_n_409,Decode_I_n_410,Decode_I_n_411,Data_Flow_I_n_189,Data_Flow_I_n_190,Data_Flow_I_n_191,Data_Flow_I_n_192,Data_Flow_I_n_193,Data_Flow_I_n_194,Data_Flow_I_n_195,Data_Flow_I_n_196,Decode_I_n_412,Decode_I_n_413,Decode_I_n_414,Decode_I_n_415,Decode_I_n_416,Decode_I_n_417,Decode_I_n_418,Decode_I_n_419}),
        .dbg_clean_stop(dbg_clean_stop),
        .dbg_halt_reset_mode_reg_0(\Use_Debug_Logic.Master_Core.Debug_Perf_n_42 ),
        .dbg_stop_i(dbg_stop_i),
        .ex_Exception_Taken(ex_Exception_Taken),
        .ex_MSR_Load_ALU_C(ex_MSR_Load_ALU_C),
        .ex_MSR_Load_Shift_C(ex_MSR_Load_Shift_C),
        .ex_MSR_Set_SW_BIP(ex_MSR_Set_SW_BIP),
        .ex_exception_no_load_store_mask(ex_exception_no_load_store_mask),
        .ex_is_load_instr_s(ex_is_load_instr_s),
        .ex_load_shift_carry(ex_load_shift_carry),
        .ex_valid(ex_valid),
        .exception_reg_0(instr_rd_reg),
        .exception_reg_1(Decode_I_n_438),
        .executing_reg_0(Decode_I_n_258),
        .mem_Exception_Taken(mem_Exception_Taken),
        .of_pause(of_pause),
        .p_231_in(p_231_in),
        .p_4_out__0(p_4_out__0),
        .read_register_MSR_1_reg_0(\Use_Debug_Logic.Master_Core.Debug_Perf_n_39 ),
        .single_Step_N_reg_0(E),
        .sync_reset(sync_reset),
        .wakeup_i(wakeup_i),
        .wb_Halted(wb_Halted),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_pc_valid(wb_pc_valid),
        .wb_read_imm_reg(wb_read_imm_reg),
        .wb_read_imm_reg_1(wb_read_imm_reg_1));
  design_1_microblaze_0_0_instr_mux instr_mux_I
       (.I139_out(\PreFetch_Buffer_I1/I139_out ),
        .Instr(Instr),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[38],LOCKSTEP_Master_Out[31:0]}),
        .\Using_FPGA.Native (\PreFetch_Buffer_I1/p_1_in49_in ),
        .\Using_FPGA.Native_0 (if_sel_input),
        .Y(ib_data),
        .in(\PreFetch_Buffer_I1/if_predecode ));
  FDRE trace_data_access_i_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(mem_databus_access),
        .Q(D[2]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[252]),
        .Q(D[70]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[10] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[242]),
        .Q(D[60]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[11] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[241]),
        .Q(D[59]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[12] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[240]),
        .Q(D[58]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[13] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[239]),
        .Q(D[57]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[14] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[238]),
        .Q(D[56]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[15] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[237]),
        .Q(D[55]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[16] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[236]),
        .Q(D[54]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[17] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[235]),
        .Q(D[53]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[18] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[234]),
        .Q(D[52]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[19] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[233]),
        .Q(D[51]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[251]),
        .Q(D[69]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[20] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[232]),
        .Q(D[50]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[21] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[231]),
        .Q(D[49]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[22] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[230]),
        .Q(D[48]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[23] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[229]),
        .Q(D[47]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[24] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[228]),
        .Q(D[46]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[25] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[227]),
        .Q(D[45]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[26] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[226]),
        .Q(D[44]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[27] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[225]),
        .Q(D[43]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[28] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[224]),
        .Q(D[42]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[29] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[223]),
        .Q(D[41]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[250]),
        .Q(D[68]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[30] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[222]),
        .Q(D[40]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[31] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[221]),
        .Q(D[39]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[249]),
        .Q(D[67]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[4] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[248]),
        .Q(D[66]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[5] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[247]),
        .Q(D[65]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[6] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[246]),
        .Q(D[64]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[7] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[245]),
        .Q(D[63]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[8] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[244]),
        .Q(D[62]),
        .R(1'b0));
  FDRE \trace_data_address_i_reg[9] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[243]),
        .Q(D[61]),
        .R(1'b0));
  FDRE \trace_data_byte_enable_i_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[187]),
        .Q(D[6]),
        .R(1'b0));
  FDRE \trace_data_byte_enable_i_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[186]),
        .Q(D[5]),
        .R(1'b0));
  FDRE \trace_data_byte_enable_i_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[185]),
        .Q(D[4]),
        .R(1'b0));
  FDRE \trace_data_byte_enable_i_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[184]),
        .Q(D[3]),
        .R(1'b0));
  FDRE trace_data_read_i_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(mem_databus_read),
        .Q(D[1]),
        .R(1'b0));
  FDRE trace_data_write_i_reg
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(mem_databus_write),
        .Q(D[0]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[0] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[219]),
        .Q(D[38]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[10] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[209]),
        .Q(D[28]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[11] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[208]),
        .Q(D[27]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[12] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[207]),
        .Q(D[26]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[13] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[206]),
        .Q(D[25]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[14] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[205]),
        .Q(D[24]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[15] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[204]),
        .Q(D[23]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[16] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[203]),
        .Q(D[22]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[17] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[202]),
        .Q(D[21]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[18] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[201]),
        .Q(D[20]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[19] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[200]),
        .Q(D[19]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[1] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[218]),
        .Q(D[37]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[20] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[199]),
        .Q(D[18]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[21] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[198]),
        .Q(D[17]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[22] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[197]),
        .Q(D[16]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[23] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[196]),
        .Q(D[15]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[24] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[195]),
        .Q(D[14]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[25] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[194]),
        .Q(D[13]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[26] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[193]),
        .Q(D[12]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[27] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[192]),
        .Q(D[11]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[28] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[191]),
        .Q(D[10]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[29] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[190]),
        .Q(D[9]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[2] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[217]),
        .Q(D[36]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[30] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[189]),
        .Q(D[8]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[31] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[188]),
        .Q(D[7]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[3] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[216]),
        .Q(D[35]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[4] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[215]),
        .Q(D[34]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[5] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[214]),
        .Q(D[33]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[6] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[213]),
        .Q(D[32]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[7] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[212]),
        .Q(D[31]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[8] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[211]),
        .Q(D[30]),
        .R(1'b0));
  FDRE \trace_data_write_value_i_reg[9] 
       (.C(Clk),
        .CE(\Using_FPGA.Native ),
        .D(D[210]),
        .Q(D[29]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "Operand_Select_gti" *) 
module design_1_microblaze_0_0_Operand_Select_gti
   (ex_load_alu_carry_reg,
    Q,
    \EX_Op1_reg[30]_0 ,
    \EX_Op1_reg[28]_0 ,
    S,
    \EX_Op2_reg[0]_0 ,
    I0,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    I2,
    in0,
    swap_result,
    swap_result_reg,
    \EX_Op3_reg[0]_0 ,
    \EX_Branch_CMP_Op1_reg[30]_0 ,
    \EX_Branch_CMP_Op1_reg[0]_0 ,
    \Using_FPGA.Native_1 ,
    \imm_reg_reg[0]_0 ,
    of_op1_sel_spr,
    D,
    I1,
    \EX_Op1_reg[1]_0 ,
    \EX_Op1_reg[2]_0 ,
    \EX_Op1_reg[3]_0 ,
    \EX_Op1_reg[4]_0 ,
    \EX_Op1_reg[5]_0 ,
    \EX_Op1_reg[6]_0 ,
    \EX_Op1_reg[7]_0 ,
    \EX_Op1_reg[8]_0 ,
    \EX_Op1_reg[9]_0 ,
    \EX_Op1_reg[10]_0 ,
    \EX_Op1_reg[11]_0 ,
    \EX_Op1_reg[12]_0 ,
    \EX_Op1_reg[13]_0 ,
    \EX_Op1_reg[14]_0 ,
    \EX_Op1_reg[15]_0 ,
    \EX_Op1_reg[16]_0 ,
    \EX_Op1_reg[17]_0 ,
    \EX_Op1_reg[18]_0 ,
    \EX_Op1_reg[19]_0 ,
    \EX_Op1_reg[20]_0 ,
    \EX_Op1_reg[21]_0 ,
    \EX_Op1_reg[22]_0 ,
    \EX_Op1_reg[23]_0 ,
    \EX_Op1_reg[24]_0 ,
    \EX_Op1_reg[25]_0 ,
    \EX_Op1_reg[26]_0 ,
    \EX_Op1_reg[27]_0 ,
    \EX_Op1_reg[28]_1 ,
    \EX_Op1_reg[29]_0 ,
    \EX_Op1_reg[30]_1 ,
    \EX_Op1_reg[31]_0 ,
    p_231_in,
    \Using_FPGA.Native_2 ,
    LO,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    ex_MSR_Load_ALU_C,
    ex_swx_access__0,
    ex_MSR_Load_Shift_C,
    ex_MSR_Load_LWX_SWX_C,
    ex_move_to_MSR_instr,
    ex_MSR,
    \Using_FPGA.Native_5 ,
    \Using_FPGA.Native_6 ,
    ex_valid,
    ex_cmp_op,
    EX_ALU_Sel_Logic,
    ex_reverse_mem_access,
    ex_byte_access,
    ex_doublet_access,
    \Using_FPGA.Native_i_3__31 ,
    ex_swap_byte_instr,
    sync_reset,
    E,
    of_imm_data,
    Clk,
    \EX_Op3_reg[31]_0 ,
    \EX_Op2_reg[0]_1 ,
    \EX_Op3_reg[0]_1 );
  output ex_load_alu_carry_reg;
  output [31:0]Q;
  output \EX_Op1_reg[30]_0 ;
  output \EX_Op1_reg[28]_0 ;
  output S;
  output [31:0]\EX_Op2_reg[0]_0 ;
  output I0;
  output [13:0]\Using_FPGA.Native ;
  output \Using_FPGA.Native_0 ;
  output I2;
  output in0;
  output [23:0]swap_result;
  output [0:7]swap_result_reg;
  output [31:0]\EX_Op3_reg[0]_0 ;
  output \EX_Branch_CMP_Op1_reg[30]_0 ;
  output [29:0]\EX_Branch_CMP_Op1_reg[0]_0 ;
  output [0:0]\Using_FPGA.Native_1 ;
  output [15:0]\imm_reg_reg[0]_0 ;
  input of_op1_sel_spr;
  input [31:0]D;
  input I1;
  input \EX_Op1_reg[1]_0 ;
  input \EX_Op1_reg[2]_0 ;
  input \EX_Op1_reg[3]_0 ;
  input \EX_Op1_reg[4]_0 ;
  input \EX_Op1_reg[5]_0 ;
  input \EX_Op1_reg[6]_0 ;
  input \EX_Op1_reg[7]_0 ;
  input \EX_Op1_reg[8]_0 ;
  input \EX_Op1_reg[9]_0 ;
  input \EX_Op1_reg[10]_0 ;
  input \EX_Op1_reg[11]_0 ;
  input \EX_Op1_reg[12]_0 ;
  input \EX_Op1_reg[13]_0 ;
  input \EX_Op1_reg[14]_0 ;
  input \EX_Op1_reg[15]_0 ;
  input \EX_Op1_reg[16]_0 ;
  input \EX_Op1_reg[17]_0 ;
  input \EX_Op1_reg[18]_0 ;
  input \EX_Op1_reg[19]_0 ;
  input \EX_Op1_reg[20]_0 ;
  input \EX_Op1_reg[21]_0 ;
  input \EX_Op1_reg[22]_0 ;
  input \EX_Op1_reg[23]_0 ;
  input \EX_Op1_reg[24]_0 ;
  input \EX_Op1_reg[25]_0 ;
  input \EX_Op1_reg[26]_0 ;
  input \EX_Op1_reg[27]_0 ;
  input \EX_Op1_reg[28]_1 ;
  input \EX_Op1_reg[29]_0 ;
  input \EX_Op1_reg[30]_1 ;
  input \EX_Op1_reg[31]_0 ;
  input p_231_in;
  input \Using_FPGA.Native_2 ;
  input LO;
  input \Using_FPGA.Native_3 ;
  input \Using_FPGA.Native_4 ;
  input ex_MSR_Load_ALU_C;
  input ex_swx_access__0;
  input ex_MSR_Load_Shift_C;
  input ex_MSR_Load_LWX_SWX_C;
  input ex_move_to_MSR_instr;
  input [1:0]ex_MSR;
  input \Using_FPGA.Native_5 ;
  input \Using_FPGA.Native_6 ;
  input ex_valid;
  input ex_cmp_op;
  input EX_ALU_Sel_Logic;
  input ex_reverse_mem_access;
  input ex_byte_access;
  input ex_doublet_access;
  input [1:0]\Using_FPGA.Native_i_3__31 ;
  input ex_swap_byte_instr;
  input sync_reset;
  input [0:0]E;
  input [0:15]of_imm_data;
  input Clk;
  input \EX_Op3_reg[31]_0 ;
  input [31:0]\EX_Op2_reg[0]_1 ;
  input [31:0]\EX_Op3_reg[0]_1 ;

  wire Clk;
  wire [31:0]D;
  wire [0:0]E;
  wire EX_ALU_Sel_Logic;
  wire [29:0]\EX_Branch_CMP_Op1_reg[0]_0 ;
  wire \EX_Branch_CMP_Op1_reg[30]_0 ;
  wire \EX_Op1_reg[10]_0 ;
  wire \EX_Op1_reg[11]_0 ;
  wire \EX_Op1_reg[12]_0 ;
  wire \EX_Op1_reg[13]_0 ;
  wire \EX_Op1_reg[14]_0 ;
  wire \EX_Op1_reg[15]_0 ;
  wire \EX_Op1_reg[16]_0 ;
  wire \EX_Op1_reg[17]_0 ;
  wire \EX_Op1_reg[18]_0 ;
  wire \EX_Op1_reg[19]_0 ;
  wire \EX_Op1_reg[1]_0 ;
  wire \EX_Op1_reg[20]_0 ;
  wire \EX_Op1_reg[21]_0 ;
  wire \EX_Op1_reg[22]_0 ;
  wire \EX_Op1_reg[23]_0 ;
  wire \EX_Op1_reg[24]_0 ;
  wire \EX_Op1_reg[25]_0 ;
  wire \EX_Op1_reg[26]_0 ;
  wire \EX_Op1_reg[27]_0 ;
  wire \EX_Op1_reg[28]_0 ;
  wire \EX_Op1_reg[28]_1 ;
  wire \EX_Op1_reg[29]_0 ;
  wire \EX_Op1_reg[2]_0 ;
  wire \EX_Op1_reg[30]_0 ;
  wire \EX_Op1_reg[30]_1 ;
  wire \EX_Op1_reg[31]_0 ;
  wire \EX_Op1_reg[3]_0 ;
  wire \EX_Op1_reg[4]_0 ;
  wire \EX_Op1_reg[5]_0 ;
  wire \EX_Op1_reg[6]_0 ;
  wire \EX_Op1_reg[7]_0 ;
  wire \EX_Op1_reg[8]_0 ;
  wire \EX_Op1_reg[9]_0 ;
  wire [31:0]\EX_Op2_reg[0]_0 ;
  wire [31:0]\EX_Op2_reg[0]_1 ;
  wire [31:0]\EX_Op3_reg[0]_0 ;
  wire [31:0]\EX_Op3_reg[0]_1 ;
  wire \EX_Op3_reg[31]_0 ;
  wire \Gen_Bit[31].MUXF7_I1_n_0 ;
  wire I0;
  wire I1;
  wire I2;
  wire LO;
  wire O;
  wire O0_out;
  wire O10_out;
  wire O11_out;
  wire O12_out;
  wire O13_out;
  wire O14_out;
  wire O15_out;
  wire O16_out;
  wire O17_out;
  wire O18_out;
  wire O19_out;
  wire O1_out;
  wire O20_out;
  wire O21_out;
  wire O22_out;
  wire O23_out;
  wire O24_out;
  wire O25_out;
  wire O26_out;
  wire O27_out;
  wire O28_out;
  wire O29_out;
  wire O2_out;
  wire O3_out;
  wire O4_out;
  wire O5_out;
  wire O6_out;
  wire O7_out;
  wire O8_out;
  wire O9_out;
  wire [31:0]Q;
  wire S;
  wire [13:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire [0:0]\Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_i_2__21_n_0 ;
  wire [1:0]\Using_FPGA.Native_i_3__31 ;
  wire \Using_FPGA.Native_i_3_n_0 ;
  wire [1:0]ex_MSR;
  wire ex_MSR_Load_ALU_C;
  wire ex_MSR_Load_LWX_SWX_C;
  wire ex_MSR_Load_Shift_C;
  wire [30:31]ex_branch_cmp_op1;
  wire ex_byte_access;
  wire ex_cmp_op;
  wire ex_doublet_access;
  wire ex_load_alu_carry_reg;
  wire ex_move_to_MSR_instr;
  wire ex_reverse_mem_access;
  wire ex_swap_byte_instr;
  wire ex_swx_access__0;
  wire ex_valid;
  wire [15:0]\imm_reg_reg[0]_0 ;
  wire in0;
  wire [0:15]of_imm_data;
  wire of_op1_sel_spr;
  wire p_231_in;
  wire [23:0]swap_result;
  wire [0:7]swap_result_reg;
  wire sync_reset;

  LUT6 #(
    .INIT(64'h0000969600FFFFFF)) 
    \Byte_Enable[0]_INST_0 
       (.I0(\EX_Op2_reg[0]_0 [0]),
        .I1(Q[0]),
        .I2(ex_reverse_mem_access),
        .I3(ex_doublet_access),
        .I4(\Using_FPGA.Native_0 ),
        .I5(ex_byte_access),
        .O(\Using_FPGA.Native [3]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h96696969)) 
    \Byte_Enable[0]_INST_0_i_1 
       (.I0(ex_reverse_mem_access),
        .I1(\EX_Op2_reg[0]_0 [1]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(\EX_Op2_reg[0]_0 [0]),
        .O(\Using_FPGA.Native_0 ));
  LUT6 #(
    .INIT(64'h0000696900FFFFFF)) 
    \Byte_Enable[1]_INST_0 
       (.I0(\EX_Op2_reg[0]_0 [0]),
        .I1(Q[0]),
        .I2(ex_reverse_mem_access),
        .I3(ex_doublet_access),
        .I4(\Using_FPGA.Native_0 ),
        .I5(ex_byte_access),
        .O(\Using_FPGA.Native [2]));
  LUT6 #(
    .INIT(64'h96FF000096FF00FF)) 
    \Byte_Enable[2]_INST_0 
       (.I0(\EX_Op2_reg[0]_0 [0]),
        .I1(Q[0]),
        .I2(ex_reverse_mem_access),
        .I3(ex_byte_access),
        .I4(\Using_FPGA.Native_0 ),
        .I5(ex_doublet_access),
        .O(\Using_FPGA.Native [1]));
  LUT6 #(
    .INIT(64'h69FF000069FF00FF)) 
    \Byte_Enable[3]_INST_0 
       (.I0(\EX_Op2_reg[0]_0 [0]),
        .I1(Q[0]),
        .I2(ex_reverse_mem_access),
        .I3(ex_byte_access),
        .I4(\Using_FPGA.Native_0 ),
        .I5(ex_doublet_access),
        .O(\Using_FPGA.Native [0]));
  LUT6 #(
    .INIT(64'hE00E0EE00EE00EE0)) 
    \Data_Addr[30]_INST_0 
       (.I0(ex_byte_access),
        .I1(ex_doublet_access),
        .I2(\EX_Op2_reg[0]_0 [1]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\EX_Op2_reg[0]_0 [0]),
        .O(\Using_FPGA.Native [13]));
  LUT3 #(
    .INIT(8'h28)) 
    \Data_Addr[31]_INST_0 
       (.I0(ex_byte_access),
        .I1(Q[0]),
        .I2(\EX_Op2_reg[0]_0 [0]),
        .O(\Using_FPGA.Native [12]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[16]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [7]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [23]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [15]),
        .O(\Using_FPGA.Native [11]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[17]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [6]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [22]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [14]),
        .O(\Using_FPGA.Native [10]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[18]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [5]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [21]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [13]),
        .O(\Using_FPGA.Native [9]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[19]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [4]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [20]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [12]),
        .O(\Using_FPGA.Native [8]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[20]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [3]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [19]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [11]),
        .O(\Using_FPGA.Native [7]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[21]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [2]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [18]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [10]),
        .O(\Using_FPGA.Native [6]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[22]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [1]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [17]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [9]),
        .O(\Using_FPGA.Native [5]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \Data_Write[23]_INST_0 
       (.I0(\EX_Op3_reg[0]_0 [0]),
        .I1(ex_byte_access),
        .I2(\EX_Op3_reg[0]_0 [16]),
        .I3(ex_reverse_mem_access),
        .I4(\EX_Op3_reg[0]_0 [8]),
        .O(\Using_FPGA.Native [4]));
  FDRE \EX_Branch_CMP_Op1_reg[0] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[31]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [29]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[10] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[21]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [19]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[11] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[20]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [18]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[12] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[19]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [17]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[13] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[18]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [16]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[14] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[17]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [15]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[15] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[16]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [14]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[16] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[15]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [13]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[17] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[14]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [12]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[18] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[13]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [11]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[19] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[12]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [10]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[1] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[30]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [28]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[20] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[11]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [9]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[21] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[10]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [8]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[22] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[9]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [7]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[23] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[8]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [6]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[24] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[7]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [5]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[25] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[6]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [4]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[26] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[5]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [3]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[27] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[4]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [2]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[28] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[3]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [1]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[29] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[2]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [0]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[2] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[29]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [27]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[30] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[1]),
        .Q(ex_branch_cmp_op1[30]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[31] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[0]),
        .Q(ex_branch_cmp_op1[31]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[3] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[28]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [26]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[4] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[27]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [25]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[5] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[26]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [24]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[6] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[25]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [23]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[7] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[24]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [22]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[8] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[23]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [21]),
        .R(sync_reset));
  FDRE \EX_Branch_CMP_Op1_reg[9] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(D[22]),
        .Q(\EX_Branch_CMP_Op1_reg[0]_0 [20]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[0] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O),
        .Q(Q[31]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[10] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O20_out),
        .Q(Q[21]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[11] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O19_out),
        .Q(Q[20]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[12] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O18_out),
        .Q(Q[19]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[13] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O17_out),
        .Q(Q[18]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[14] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O16_out),
        .Q(Q[17]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[15] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O15_out),
        .Q(Q[16]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[16] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O14_out),
        .Q(Q[15]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[17] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O13_out),
        .Q(Q[14]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[18] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O12_out),
        .Q(Q[13]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[19] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O11_out),
        .Q(Q[12]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[1] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O29_out),
        .Q(Q[30]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[20] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O10_out),
        .Q(Q[11]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[21] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O9_out),
        .Q(Q[10]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[22] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O8_out),
        .Q(Q[9]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[23] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O7_out),
        .Q(Q[8]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[24] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O6_out),
        .Q(Q[7]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[25] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O5_out),
        .Q(Q[6]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[26] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O4_out),
        .Q(Q[5]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[27] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O3_out),
        .Q(Q[4]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[28] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O2_out),
        .Q(Q[3]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[29] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O1_out),
        .Q(Q[2]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[2] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O28_out),
        .Q(Q[29]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[30] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O0_out),
        .Q(Q[1]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[31] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\Gen_Bit[31].MUXF7_I1_n_0 ),
        .Q(Q[0]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[3] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O27_out),
        .Q(Q[28]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[4] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O26_out),
        .Q(Q[27]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[5] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O25_out),
        .Q(Q[26]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[6] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O24_out),
        .Q(Q[25]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[7] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O23_out),
        .Q(Q[24]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[8] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O22_out),
        .Q(Q[23]),
        .R(sync_reset));
  FDRE \EX_Op1_reg[9] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(O21_out),
        .Q(Q[22]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[0] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [31]),
        .Q(\EX_Op2_reg[0]_0 [31]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[10] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [21]),
        .Q(\EX_Op2_reg[0]_0 [21]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[11] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [20]),
        .Q(\EX_Op2_reg[0]_0 [20]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[12] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [19]),
        .Q(\EX_Op2_reg[0]_0 [19]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[13] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [18]),
        .Q(\EX_Op2_reg[0]_0 [18]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[14] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [17]),
        .Q(\EX_Op2_reg[0]_0 [17]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[15] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [16]),
        .Q(\EX_Op2_reg[0]_0 [16]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[16] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [15]),
        .Q(\EX_Op2_reg[0]_0 [15]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[17] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [14]),
        .Q(\EX_Op2_reg[0]_0 [14]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[18] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [13]),
        .Q(\EX_Op2_reg[0]_0 [13]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[19] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [12]),
        .Q(\EX_Op2_reg[0]_0 [12]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[1] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [30]),
        .Q(\EX_Op2_reg[0]_0 [30]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[20] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [11]),
        .Q(\EX_Op2_reg[0]_0 [11]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[21] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [10]),
        .Q(\EX_Op2_reg[0]_0 [10]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[22] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [9]),
        .Q(\EX_Op2_reg[0]_0 [9]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[23] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [8]),
        .Q(\EX_Op2_reg[0]_0 [8]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[24] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [7]),
        .Q(\EX_Op2_reg[0]_0 [7]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[25] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [6]),
        .Q(\EX_Op2_reg[0]_0 [6]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[26] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [5]),
        .Q(\EX_Op2_reg[0]_0 [5]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[27] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [4]),
        .Q(\EX_Op2_reg[0]_0 [4]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[28] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [3]),
        .Q(\EX_Op2_reg[0]_0 [3]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[29] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [2]),
        .Q(\EX_Op2_reg[0]_0 [2]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[2] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [29]),
        .Q(\EX_Op2_reg[0]_0 [29]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[30] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [1]),
        .Q(\EX_Op2_reg[0]_0 [1]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[31] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [0]),
        .Q(\EX_Op2_reg[0]_0 [0]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[3] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [28]),
        .Q(\EX_Op2_reg[0]_0 [28]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[4] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [27]),
        .Q(\EX_Op2_reg[0]_0 [27]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[5] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [26]),
        .Q(\EX_Op2_reg[0]_0 [26]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[6] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [25]),
        .Q(\EX_Op2_reg[0]_0 [25]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[7] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [24]),
        .Q(\EX_Op2_reg[0]_0 [24]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[8] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [23]),
        .Q(\EX_Op2_reg[0]_0 [23]),
        .R(sync_reset));
  FDRE \EX_Op2_reg[9] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op2_reg[0]_1 [22]),
        .Q(\EX_Op2_reg[0]_0 [22]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[0] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [31]),
        .Q(\EX_Op3_reg[0]_0 [31]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[10] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [21]),
        .Q(\EX_Op3_reg[0]_0 [21]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[11] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [20]),
        .Q(\EX_Op3_reg[0]_0 [20]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[12] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [19]),
        .Q(\EX_Op3_reg[0]_0 [19]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[13] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [18]),
        .Q(\EX_Op3_reg[0]_0 [18]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[14] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [17]),
        .Q(\EX_Op3_reg[0]_0 [17]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[15] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [16]),
        .Q(\EX_Op3_reg[0]_0 [16]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[16] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [15]),
        .Q(\EX_Op3_reg[0]_0 [15]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[17] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [14]),
        .Q(\EX_Op3_reg[0]_0 [14]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[18] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [13]),
        .Q(\EX_Op3_reg[0]_0 [13]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[19] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [12]),
        .Q(\EX_Op3_reg[0]_0 [12]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[1] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [30]),
        .Q(\EX_Op3_reg[0]_0 [30]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[20] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [11]),
        .Q(\EX_Op3_reg[0]_0 [11]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[21] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [10]),
        .Q(\EX_Op3_reg[0]_0 [10]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[22] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [9]),
        .Q(\EX_Op3_reg[0]_0 [9]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[23] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [8]),
        .Q(\EX_Op3_reg[0]_0 [8]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[24] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [7]),
        .Q(\EX_Op3_reg[0]_0 [7]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[25] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [6]),
        .Q(\EX_Op3_reg[0]_0 [6]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[26] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [5]),
        .Q(\EX_Op3_reg[0]_0 [5]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[27] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [4]),
        .Q(\EX_Op3_reg[0]_0 [4]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[28] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [3]),
        .Q(\EX_Op3_reg[0]_0 [3]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[29] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [2]),
        .Q(\EX_Op3_reg[0]_0 [2]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[2] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [29]),
        .Q(\EX_Op3_reg[0]_0 [29]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[30] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [1]),
        .Q(\EX_Op3_reg[0]_0 [1]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[31] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [0]),
        .Q(\EX_Op3_reg[0]_0 [0]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[3] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [28]),
        .Q(\EX_Op3_reg[0]_0 [28]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[4] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [27]),
        .Q(\EX_Op3_reg[0]_0 [27]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[5] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [26]),
        .Q(\EX_Op3_reg[0]_0 [26]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[6] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [25]),
        .Q(\EX_Op3_reg[0]_0 [25]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[7] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [24]),
        .Q(\EX_Op3_reg[0]_0 [24]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[8] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [23]),
        .Q(\EX_Op3_reg[0]_0 [23]),
        .R(sync_reset));
  FDRE \EX_Op3_reg[9] 
       (.C(Clk),
        .CE(\EX_Op3_reg[31]_0 ),
        .D(\EX_Op3_reg[0]_1 [22]),
        .Q(\EX_Op3_reg[0]_0 [22]),
        .R(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_424 \Gen_Bit[0].MUXF7_I1 
       (.D(O),
        .\EX_Op1_reg[0] (D[31]),
        .I1(I1),
        .Q({Q[15],Q[7]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[0]));
  design_1_microblaze_0_0_MB_MUXF7_425 \Gen_Bit[10].MUXF7_I1 
       (.D(O20_out),
        .\EX_Op1_reg[10] (D[21]),
        .\EX_Op1_reg[10]_0 (\EX_Op1_reg[10]_0 ),
        .Q({Q[13],Q[5]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[21]));
  design_1_microblaze_0_0_MB_MUXF7_426 \Gen_Bit[11].MUXF7_I1 
       (.D(O19_out),
        .\EX_Op1_reg[11] (D[20]),
        .\EX_Op1_reg[11]_0 (\EX_Op1_reg[11]_0 ),
        .Q({Q[12],Q[4]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[20]));
  design_1_microblaze_0_0_MB_MUXF7_427 \Gen_Bit[12].MUXF7_I1 
       (.D(O18_out),
        .\EX_Op1_reg[12] (D[19]),
        .\EX_Op1_reg[12]_0 (\EX_Op1_reg[12]_0 ),
        .Q({Q[11],Q[3]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[19]));
  design_1_microblaze_0_0_MB_MUXF7_428 \Gen_Bit[13].MUXF7_I1 
       (.D(O17_out),
        .\EX_Op1_reg[13] (D[18]),
        .\EX_Op1_reg[13]_0 (\EX_Op1_reg[13]_0 ),
        .Q({Q[10],Q[2]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[18]));
  design_1_microblaze_0_0_MB_MUXF7_429 \Gen_Bit[14].MUXF7_I1 
       (.D(O16_out),
        .\EX_Op1_reg[14] (D[17]),
        .\EX_Op1_reg[14]_0 (\EX_Op1_reg[14]_0 ),
        .Q({Q[9],Q[1]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[17]));
  design_1_microblaze_0_0_MB_MUXF7_430 \Gen_Bit[15].MUXF7_I1 
       (.D(O15_out),
        .\EX_Op1_reg[15] (D[16]),
        .\EX_Op1_reg[15]_0 (\EX_Op1_reg[15]_0 ),
        .Q({Q[8],Q[0]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[16]));
  design_1_microblaze_0_0_MB_MUXF7_431 \Gen_Bit[16].MUXF7_I1 
       (.D(O14_out),
        .\EX_Op1_reg[16] (D[15]),
        .\EX_Op1_reg[16]_0 (\EX_Op1_reg[16]_0 ),
        .Q({Q[31],Q[23]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[15]));
  design_1_microblaze_0_0_MB_MUXF7_432 \Gen_Bit[17].MUXF7_I1 
       (.D(O13_out),
        .\EX_Op1_reg[17] (D[14]),
        .\EX_Op1_reg[17]_0 (\EX_Op1_reg[17]_0 ),
        .Q({Q[30],Q[22]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[14]));
  design_1_microblaze_0_0_MB_MUXF7_433 \Gen_Bit[18].MUXF7_I1 
       (.D(O12_out),
        .\EX_Op1_reg[18] (D[13]),
        .\EX_Op1_reg[18]_0 (\EX_Op1_reg[18]_0 ),
        .Q({Q[29],Q[21]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[13]));
  design_1_microblaze_0_0_MB_MUXF7_434 \Gen_Bit[19].MUXF7_I1 
       (.D(O11_out),
        .\EX_Op1_reg[19] (D[12]),
        .\EX_Op1_reg[19]_0 (\EX_Op1_reg[19]_0 ),
        .Q({Q[28],Q[20]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[12]));
  design_1_microblaze_0_0_MB_MUXF7_435 \Gen_Bit[1].MUXF7_I1 
       (.D(O29_out),
        .\EX_Op1_reg[1] (D[30]),
        .\EX_Op1_reg[1]_0 (\EX_Op1_reg[1]_0 ),
        .Q({Q[14],Q[6]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[1]));
  design_1_microblaze_0_0_MB_MUXF7_436 \Gen_Bit[20].MUXF7_I1 
       (.D(O10_out),
        .\EX_Op1_reg[20] (D[11]),
        .\EX_Op1_reg[20]_0 (\EX_Op1_reg[20]_0 ),
        .Q({Q[27],Q[19]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[11]));
  design_1_microblaze_0_0_MB_MUXF7_437 \Gen_Bit[21].MUXF7_I1 
       (.D(O9_out),
        .\EX_Op1_reg[21] (D[10]),
        .\EX_Op1_reg[21]_0 (\EX_Op1_reg[21]_0 ),
        .Q({Q[26],Q[18]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[10]));
  design_1_microblaze_0_0_MB_MUXF7_438 \Gen_Bit[22].MUXF7_I1 
       (.D(O8_out),
        .\EX_Op1_reg[22] (D[9]),
        .\EX_Op1_reg[22]_0 (\EX_Op1_reg[22]_0 ),
        .Q({Q[25],Q[17]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[9]));
  design_1_microblaze_0_0_MB_MUXF7_439 \Gen_Bit[23].MUXF7_I1 
       (.D(O7_out),
        .\EX_Op1_reg[23] (D[8]),
        .\EX_Op1_reg[23]_0 (\EX_Op1_reg[23]_0 ),
        .Q({Q[24],Q[16]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[8]));
  design_1_microblaze_0_0_MB_MUXF7_440 \Gen_Bit[24].MUXF7_I1 
       (.D(O6_out),
        .\EX_Op1_reg[24] (D[7]),
        .\EX_Op1_reg[24]_0 (\EX_Op1_reg[24]_0 ),
        .Q({Q[31],Q[23]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[7]));
  design_1_microblaze_0_0_MB_MUXF7_441 \Gen_Bit[25].MUXF7_I1 
       (.D(O5_out),
        .\EX_Op1_reg[25] (D[6]),
        .\EX_Op1_reg[25]_0 (\EX_Op1_reg[25]_0 ),
        .Q({Q[30],Q[22]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[6]));
  design_1_microblaze_0_0_MB_MUXF7_442 \Gen_Bit[26].MUXF7_I1 
       (.D(O4_out),
        .\EX_Op1_reg[26] (D[5]),
        .\EX_Op1_reg[26]_0 (\EX_Op1_reg[26]_0 ),
        .Q({Q[29],Q[21]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[5]));
  design_1_microblaze_0_0_MB_MUXF7_443 \Gen_Bit[27].MUXF7_I1 
       (.D(O3_out),
        .\EX_Op1_reg[27] (D[4]),
        .\EX_Op1_reg[27]_0 (\EX_Op1_reg[27]_0 ),
        .Q({Q[28],Q[20]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[4]));
  design_1_microblaze_0_0_MB_MUXF7_444 \Gen_Bit[28].MUXF7_I1 
       (.D(O2_out),
        .\EX_Op1_reg[28] (D[3]),
        .\EX_Op1_reg[28]_0 (\EX_Op1_reg[28]_1 ),
        .Q({Q[27],Q[19]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[3]));
  design_1_microblaze_0_0_MB_MUXF7_445 \Gen_Bit[29].MUXF7_I1 
       (.D(O1_out),
        .\EX_Op1_reg[29] (D[2]),
        .\EX_Op1_reg[29]_0 (\EX_Op1_reg[29]_0 ),
        .Q({Q[26],Q[18]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[2]));
  design_1_microblaze_0_0_MB_MUXF7_446 \Gen_Bit[2].MUXF7_I1 
       (.D(O28_out),
        .\EX_Op1_reg[2] (D[29]),
        .\EX_Op1_reg[2]_0 (\EX_Op1_reg[2]_0 ),
        .Q({Q[13],Q[5]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[2]));
  design_1_microblaze_0_0_MB_MUXF7_447 \Gen_Bit[30].MUXF7_I1 
       (.D(O0_out),
        .\EX_Op1_reg[30] (D[1]),
        .\EX_Op1_reg[30]_0 (\EX_Op1_reg[30]_1 ),
        .Q({Q[25],Q[17]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[1]));
  design_1_microblaze_0_0_MB_MUXF7_448 \Gen_Bit[31].MUXF7_I1 
       (.D(\Gen_Bit[31].MUXF7_I1_n_0 ),
        .\EX_Op1_reg[31] (D[0]),
        .\EX_Op1_reg[31]_0 (\EX_Op1_reg[31]_0 ),
        .Q({Q[24],Q[16]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[0]));
  design_1_microblaze_0_0_MB_MUXF7_449 \Gen_Bit[3].MUXF7_I1 
       (.D(O27_out),
        .\EX_Op1_reg[3] (D[28]),
        .\EX_Op1_reg[3]_0 (\EX_Op1_reg[3]_0 ),
        .Q({Q[12],Q[4]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[3]));
  design_1_microblaze_0_0_MB_MUXF7_450 \Gen_Bit[4].MUXF7_I1 
       (.D(O26_out),
        .\EX_Op1_reg[4] (D[27]),
        .\EX_Op1_reg[4]_0 (\EX_Op1_reg[4]_0 ),
        .Q({Q[11],Q[3]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[4]));
  design_1_microblaze_0_0_MB_MUXF7_451 \Gen_Bit[5].MUXF7_I1 
       (.D(O25_out),
        .\EX_Op1_reg[5] (D[26]),
        .\EX_Op1_reg[5]_0 (\EX_Op1_reg[5]_0 ),
        .Q({Q[10],Q[2]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[5]));
  design_1_microblaze_0_0_MB_MUXF7_452 \Gen_Bit[6].MUXF7_I1 
       (.D(O24_out),
        .\EX_Op1_reg[6] (D[25]),
        .\EX_Op1_reg[6]_0 (\EX_Op1_reg[6]_0 ),
        .Q({Q[9],Q[1]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[6]));
  design_1_microblaze_0_0_MB_MUXF7_453 \Gen_Bit[7].MUXF7_I1 
       (.D(O23_out),
        .\EX_Op1_reg[7] (D[24]),
        .\EX_Op1_reg[7]_0 (\EX_Op1_reg[7]_0 ),
        .Q({Q[8],Q[0]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result_reg(swap_result_reg[7]));
  design_1_microblaze_0_0_MB_MUXF7_454 \Gen_Bit[8].MUXF7_I1 
       (.D(O22_out),
        .\EX_Op1_reg[8] (D[23]),
        .\EX_Op1_reg[8]_0 (\EX_Op1_reg[8]_0 ),
        .Q({Q[15],Q[7]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[23]));
  design_1_microblaze_0_0_MB_MUXF7_455 \Gen_Bit[9].MUXF7_I1 
       (.D(O21_out),
        .\EX_Op1_reg[9] (D[22]),
        .\EX_Op1_reg[9]_0 (\EX_Op1_reg[9]_0 ),
        .Q({Q[14],Q[6]}),
        .ex_swap_byte_instr(ex_swap_byte_instr),
        .of_op1_sel_spr(of_op1_sel_spr),
        .swap_result(swap_result[22]));
  LUT6 #(
    .INIT(64'hEAAAFFFFEAAA0000)) 
    \Using_FPGA.Native_i_1__3 
       (.I0(\Using_FPGA.Native_i_2__21_n_0 ),
        .I1(p_231_in),
        .I2(\Using_FPGA.Native_2 ),
        .I3(LO),
        .I4(\Using_FPGA.Native_3 ),
        .I5(\Using_FPGA.Native_4 ),
        .O(ex_load_alu_carry_reg));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \Using_FPGA.Native_i_1__5 
       (.I0(Q[1]),
        .I1(p_231_in),
        .I2(ex_move_to_MSR_instr),
        .I3(\Using_FPGA.Native_3 ),
        .I4(ex_MSR[0]),
        .O(\EX_Op1_reg[30]_0 ));
  LUT4 #(
    .INIT(16'h009F)) 
    \Using_FPGA.Native_i_1__50 
       (.I0(\EX_Op2_reg[0]_0 [31]),
        .I1(Q[31]),
        .I2(ex_cmp_op),
        .I3(EX_ALU_Sel_Logic),
        .O(S));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \Using_FPGA.Native_i_1__51 
       (.I0(\EX_Op2_reg[0]_0 [31]),
        .I1(EX_ALU_Sel_Logic),
        .O(I0));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h9F)) 
    \Using_FPGA.Native_i_1__54 
       (.I0(\EX_Op2_reg[0]_0 [31]),
        .I1(Q[31]),
        .I2(ex_cmp_op),
        .O(I2));
  LUT2 #(
    .INIT(4'h1)) 
    \Using_FPGA.Native_i_1__94 
       (.I0(ex_branch_cmp_op1[30]),
        .I1(ex_branch_cmp_op1[31]),
        .O(\EX_Branch_CMP_Op1_reg[30]_0 ));
  LUT6 #(
    .INIT(64'h3030003330302222)) 
    \Using_FPGA.Native_i_2__21 
       (.I0(\Using_FPGA.Native_i_3_n_0 ),
        .I1(ex_MSR_Load_ALU_C),
        .I2(Q[0]),
        .I3(ex_swx_access__0),
        .I4(ex_MSR_Load_Shift_C),
        .I5(ex_MSR_Load_LWX_SWX_C),
        .O(\Using_FPGA.Native_i_2__21_n_0 ));
  LUT6 #(
    .INIT(64'hAEFFFFFFA2000000)) 
    \Using_FPGA.Native_i_2__22 
       (.I0(Q[3]),
        .I1(\Using_FPGA.Native_5 ),
        .I2(\Using_FPGA.Native_6 ),
        .I3(ex_valid),
        .I4(ex_move_to_MSR_instr),
        .I5(ex_MSR[1]),
        .O(\EX_Op1_reg[28]_0 ));
  LUT6 #(
    .INIT(64'hAEFFFFFFA2000000)) 
    \Using_FPGA.Native_i_3 
       (.I0(Q[2]),
        .I1(\Using_FPGA.Native_5 ),
        .I2(\Using_FPGA.Native_6 ),
        .I3(ex_valid),
        .I4(ex_move_to_MSR_instr),
        .I5(\Using_FPGA.Native_4 ),
        .O(\Using_FPGA.Native_i_3_n_0 ));
  FDRE \imm_reg_reg[0] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[0]),
        .Q(\imm_reg_reg[0]_0 [15]),
        .R(sync_reset));
  FDRE \imm_reg_reg[10] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[10]),
        .Q(\imm_reg_reg[0]_0 [5]),
        .R(sync_reset));
  FDRE \imm_reg_reg[11] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[11]),
        .Q(\imm_reg_reg[0]_0 [4]),
        .R(sync_reset));
  FDRE \imm_reg_reg[12] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[12]),
        .Q(\imm_reg_reg[0]_0 [3]),
        .R(sync_reset));
  FDRE \imm_reg_reg[13] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[13]),
        .Q(\imm_reg_reg[0]_0 [2]),
        .R(sync_reset));
  FDRE \imm_reg_reg[14] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[14]),
        .Q(\imm_reg_reg[0]_0 [1]),
        .R(sync_reset));
  FDRE \imm_reg_reg[15] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[15]),
        .Q(\imm_reg_reg[0]_0 [0]),
        .R(sync_reset));
  FDRE \imm_reg_reg[1] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[1]),
        .Q(\imm_reg_reg[0]_0 [14]),
        .R(sync_reset));
  FDRE \imm_reg_reg[2] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[2]),
        .Q(\imm_reg_reg[0]_0 [13]),
        .R(sync_reset));
  FDRE \imm_reg_reg[3] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[3]),
        .Q(\imm_reg_reg[0]_0 [12]),
        .R(sync_reset));
  FDRE \imm_reg_reg[4] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[4]),
        .Q(\imm_reg_reg[0]_0 [11]),
        .R(sync_reset));
  FDRE \imm_reg_reg[5] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[5]),
        .Q(\imm_reg_reg[0]_0 [10]),
        .R(sync_reset));
  FDRE \imm_reg_reg[6] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[6]),
        .Q(\imm_reg_reg[0]_0 [9]),
        .R(sync_reset));
  FDRE \imm_reg_reg[7] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[7]),
        .Q(\imm_reg_reg[0]_0 [8]),
        .R(sync_reset));
  FDRE \imm_reg_reg[8] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[8]),
        .Q(\imm_reg_reg[0]_0 [7]),
        .R(sync_reset));
  FDRE \imm_reg_reg[9] 
       (.C(Clk),
        .CE(E),
        .D(of_imm_data[9]),
        .Q(\imm_reg_reg[0]_0 [6]),
        .R(sync_reset));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \mem_byte_selects[1]_i_1 
       (.I0(ex_reverse_mem_access),
        .I1(Q[0]),
        .I2(\EX_Op2_reg[0]_0 [0]),
        .O(\Using_FPGA.Native_1 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    sign_doublet_inferred_i_1
       (.I0(Q[7]),
        .I1(\Using_FPGA.Native_i_3__31 [0]),
        .I2(Q[15]),
        .I3(\Using_FPGA.Native_i_3__31 [1]),
        .O(in0));
endmodule

(* ORIG_REF_NAME = "PC_Module_gti" *) 
module design_1_microblaze_0_0_PC_Module_gti
   (D,
    O56_out,
    IB_Ready,
    \if_pc_reg[30]_0 ,
    O,
    \if_pc_reg[28]_0 ,
    \if_pc_reg[27]_0 ,
    \if_pc_reg[26]_0 ,
    \if_pc_reg[25]_0 ,
    \if_pc_reg[24]_0 ,
    \if_pc_reg[23]_0 ,
    \if_pc_reg[22]_0 ,
    \if_pc_reg[21]_0 ,
    \if_pc_reg[20]_0 ,
    \if_pc_reg[19]_0 ,
    \if_pc_reg[18]_0 ,
    \if_pc_reg[17]_0 ,
    \if_pc_reg[16]_0 ,
    \if_pc_reg[15]_0 ,
    \if_pc_reg[14]_0 ,
    \if_pc_reg[13]_0 ,
    \if_pc_reg[12]_0 ,
    \if_pc_reg[11]_0 ,
    \if_pc_reg[10]_0 ,
    \if_pc_reg[9]_0 ,
    \if_pc_reg[8]_0 ,
    \if_pc_reg[7]_0 ,
    \if_pc_reg[6]_0 ,
    \if_pc_reg[5]_0 ,
    \if_pc_reg[4]_0 ,
    \if_pc_reg[3]_0 ,
    \if_pc_reg[2]_0 ,
    \if_pc_reg[1]_0 ,
    \mem_pc_i_reg[0]_0 ,
    \ex_pc_i_reg[31]_0 ,
    sync_reset,
    Clk,
    ex_jump_nodelay_reg,
    ex_jump_nodelay_reg_0,
    wb_exception,
    Q,
    IReady,
    \Using_FPGA.Native ,
    if_sel_input,
    \Using_FPGA.Native_0 ,
    CI,
    if_pre_buffer_addr,
    E,
    \if_pc_reg[0]_0 ,
    \if_pc_reg[0]_1 ,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19);
  output [31:0]D;
  output O56_out;
  output IB_Ready;
  output [1:0]\if_pc_reg[30]_0 ;
  output O;
  output \if_pc_reg[28]_0 ;
  output \if_pc_reg[27]_0 ;
  output \if_pc_reg[26]_0 ;
  output \if_pc_reg[25]_0 ;
  output \if_pc_reg[24]_0 ;
  output \if_pc_reg[23]_0 ;
  output \if_pc_reg[22]_0 ;
  output \if_pc_reg[21]_0 ;
  output \if_pc_reg[20]_0 ;
  output \if_pc_reg[19]_0 ;
  output \if_pc_reg[18]_0 ;
  output \if_pc_reg[17]_0 ;
  output \if_pc_reg[16]_0 ;
  output \if_pc_reg[15]_0 ;
  output \if_pc_reg[14]_0 ;
  output \if_pc_reg[13]_0 ;
  output \if_pc_reg[12]_0 ;
  output \if_pc_reg[11]_0 ;
  output \if_pc_reg[10]_0 ;
  output \if_pc_reg[9]_0 ;
  output \if_pc_reg[8]_0 ;
  output \if_pc_reg[7]_0 ;
  output \if_pc_reg[6]_0 ;
  output \if_pc_reg[5]_0 ;
  output \if_pc_reg[4]_0 ;
  output \if_pc_reg[3]_0 ;
  output \if_pc_reg[2]_0 ;
  output \if_pc_reg[1]_0 ;
  output [31:0]\mem_pc_i_reg[0]_0 ;
  input \ex_pc_i_reg[31]_0 ;
  input sync_reset;
  input Clk;
  input ex_jump_nodelay_reg;
  input ex_jump_nodelay_reg_0;
  input wb_exception;
  input [1:0]Q;
  input IReady;
  input \Using_FPGA.Native ;
  input [1:0]if_sel_input;
  input \Using_FPGA.Native_0 ;
  input CI;
  input [0:0]if_pre_buffer_addr;
  input [0:0]E;
  input [0:0]\if_pc_reg[0]_0 ;
  input [31:0]\if_pc_reg[0]_1 ;
  input lopt;
  output lopt_1;
  output lopt_2;
  input lopt_3;
  input lopt_4;
  input lopt_5;
  input lopt_6;
  input lopt_7;
  input lopt_8;
  input lopt_9;
  input lopt_10;
  input lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  output lopt_18;
  output lopt_19;

  wire CI;
  wire Clk;
  wire [31:0]D;
  wire [0:0]E;
  wire I0;
  wire I0101_out;
  wire I0105_out;
  wire I0109_out;
  wire I0113_out;
  wire I0117_out;
  wire I0121_out;
  wire I0125_out;
  wire I013_out;
  wire I017_out;
  wire I021_out;
  wire I025_out;
  wire I029_out;
  wire I033_out;
  wire I037_out;
  wire I041_out;
  wire I045_out;
  wire I049_out;
  wire I053_out;
  wire I057_out;
  wire I05_out;
  wire I061_out;
  wire I065_out;
  wire I069_out;
  wire I073_out;
  wire I077_out;
  wire I081_out;
  wire I085_out;
  wire I089_out;
  wire I093_out;
  wire I097_out;
  wire I09_out;
  wire IB_Ready;
  wire IReady;
  wire O;
  wire O56_out;
  wire \PC_Buffer_reg[3][31]_srl4_n_0 ;
  wire [1:0]Q;
  wire S;
  wire S102_in;
  wire S107_in;
  wire S112_in;
  wire S117_in;
  wire S122_in;
  wire S127_in;
  wire S12_in;
  wire S132_in;
  wire S137_in;
  wire S142_in;
  wire S147_in;
  wire S152_in;
  wire S17_in;
  wire S22_in;
  wire S27_in;
  wire S32_in;
  wire S37_in;
  wire S42_in;
  wire S47_in;
  wire S52_in;
  wire S57_in;
  wire S62_in;
  wire S67_in;
  wire S72_in;
  wire S77_in;
  wire S82_in;
  wire S87_in;
  wire S92_in;
  wire S97_in;
  wire \Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire ex_jump_nodelay_reg;
  wire ex_jump_nodelay_reg_0;
  wire [0:31]ex_pc;
  wire \ex_pc_i_reg[31]_0 ;
  wire [29:1]if_pc_carry;
  wire [0:0]\if_pc_reg[0]_0 ;
  wire [31:0]\if_pc_reg[0]_1 ;
  wire \if_pc_reg[10]_0 ;
  wire \if_pc_reg[11]_0 ;
  wire \if_pc_reg[12]_0 ;
  wire \if_pc_reg[13]_0 ;
  wire \if_pc_reg[14]_0 ;
  wire \if_pc_reg[15]_0 ;
  wire \if_pc_reg[16]_0 ;
  wire \if_pc_reg[17]_0 ;
  wire \if_pc_reg[18]_0 ;
  wire \if_pc_reg[19]_0 ;
  wire \if_pc_reg[1]_0 ;
  wire \if_pc_reg[20]_0 ;
  wire \if_pc_reg[21]_0 ;
  wire \if_pc_reg[22]_0 ;
  wire \if_pc_reg[23]_0 ;
  wire \if_pc_reg[24]_0 ;
  wire \if_pc_reg[25]_0 ;
  wire \if_pc_reg[26]_0 ;
  wire \if_pc_reg[27]_0 ;
  wire \if_pc_reg[28]_0 ;
  wire \if_pc_reg[2]_0 ;
  wire [1:0]\if_pc_reg[30]_0 ;
  wire \if_pc_reg[3]_0 ;
  wire \if_pc_reg[4]_0 ;
  wire \if_pc_reg[5]_0 ;
  wire \if_pc_reg[6]_0 ;
  wire \if_pc_reg[7]_0 ;
  wire \if_pc_reg[8]_0 ;
  wire \if_pc_reg[9]_0 ;
  wire [0:0]if_pre_buffer_addr;
  wire [1:0]if_sel_input;
  wire lopt;
  wire lopt_1;
  wire \^lopt_10 ;
  wire lopt_100;
  wire lopt_101;
  wire \^lopt_11 ;
  wire \^lopt_12 ;
  wire \^lopt_13 ;
  wire \^lopt_14 ;
  wire \^lopt_15 ;
  wire \^lopt_16 ;
  wire \^lopt_17 ;
  wire \^lopt_18 ;
  wire \^lopt_19 ;
  wire \^lopt_2 ;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_27;
  wire lopt_28;
  wire lopt_29;
  wire \^lopt_3 ;
  wire lopt_30;
  wire lopt_31;
  wire lopt_32;
  wire lopt_33;
  wire lopt_34;
  wire lopt_35;
  wire lopt_36;
  wire lopt_37;
  wire lopt_38;
  wire lopt_39;
  wire \^lopt_4 ;
  wire lopt_40;
  wire lopt_41;
  wire lopt_42;
  wire lopt_43;
  wire lopt_44;
  wire lopt_45;
  wire lopt_46;
  wire lopt_47;
  wire lopt_48;
  wire lopt_49;
  wire \^lopt_5 ;
  wire lopt_50;
  wire lopt_51;
  wire lopt_52;
  wire lopt_53;
  wire lopt_54;
  wire lopt_55;
  wire lopt_56;
  wire lopt_57;
  wire lopt_58;
  wire lopt_59;
  wire \^lopt_6 ;
  wire lopt_60;
  wire lopt_61;
  wire lopt_62;
  wire lopt_63;
  wire lopt_64;
  wire lopt_65;
  wire lopt_66;
  wire lopt_67;
  wire lopt_68;
  wire lopt_69;
  wire \^lopt_7 ;
  wire lopt_70;
  wire lopt_71;
  wire lopt_72;
  wire lopt_73;
  wire lopt_74;
  wire lopt_75;
  wire lopt_76;
  wire lopt_77;
  wire lopt_78;
  wire lopt_79;
  wire \^lopt_8 ;
  wire lopt_80;
  wire lopt_81;
  wire lopt_82;
  wire lopt_83;
  wire lopt_84;
  wire lopt_85;
  wire lopt_86;
  wire lopt_87;
  wire lopt_88;
  wire lopt_89;
  wire \^lopt_9 ;
  wire lopt_90;
  wire lopt_91;
  wire lopt_92;
  wire lopt_93;
  wire lopt_94;
  wire lopt_95;
  wire lopt_96;
  wire lopt_97;
  wire lopt_98;
  wire lopt_99;
  wire [31:0]\mem_pc_i_reg[0]_0 ;
  wire of_pc_ii_0;
  wire of_pc_ii_1;
  wire of_pc_ii_10;
  wire of_pc_ii_11;
  wire of_pc_ii_12;
  wire of_pc_ii_13;
  wire of_pc_ii_14;
  wire of_pc_ii_15;
  wire of_pc_ii_16;
  wire of_pc_ii_17;
  wire of_pc_ii_18;
  wire of_pc_ii_19;
  wire of_pc_ii_2;
  wire of_pc_ii_20;
  wire of_pc_ii_21;
  wire of_pc_ii_22;
  wire of_pc_ii_23;
  wire of_pc_ii_24;
  wire of_pc_ii_25;
  wire of_pc_ii_26;
  wire of_pc_ii_27;
  wire of_pc_ii_28;
  wire of_pc_ii_29;
  wire of_pc_ii_3;
  wire of_pc_ii_30;
  wire of_pc_ii_31;
  wire of_pc_ii_4;
  wire of_pc_ii_5;
  wire of_pc_ii_6;
  wire of_pc_ii_7;
  wire of_pc_ii_8;
  wire of_pc_ii_9;
  wire p_1_in103_in;
  wire p_1_in108_in;
  wire p_1_in113_in;
  wire p_1_in118_in;
  wire p_1_in123_in;
  wire p_1_in128_in;
  wire p_1_in133_in;
  wire p_1_in138_in;
  wire p_1_in13_in;
  wire p_1_in143_in;
  wire p_1_in148_in;
  wire p_1_in153_in;
  wire p_1_in18_in;
  wire p_1_in23_in;
  wire p_1_in28_in;
  wire p_1_in33_in;
  wire p_1_in38_in;
  wire p_1_in43_in;
  wire p_1_in48_in;
  wire p_1_in53_in;
  wire p_1_in58_in;
  wire p_1_in63_in;
  wire p_1_in68_in;
  wire p_1_in73_in;
  wire p_1_in78_in;
  wire p_1_in83_in;
  wire p_1_in88_in;
  wire p_1_in8_in;
  wire p_1_in93_in;
  wire p_1_in98_in;
  wire p_2_in4_in;
  wire sync_reset;
  wire wb_exception;

  assign \^lopt_2  = lopt_3;
  assign lopt_12 = \^lopt_8 ;
  assign lopt_13 = \^lopt_6 ;
  assign lopt_14 = \^lopt_4 ;
  assign lopt_15 = lopt_74;
  assign lopt_16 = S27_in;
  assign lopt_17 = S22_in;
  assign lopt_18 = S17_in;
  assign lopt_19 = S12_in;
  assign lopt_2 = S;
  assign lopt_66 = lopt_4;
  assign lopt_67 = lopt_5;
  assign lopt_68 = lopt_6;
  assign lopt_69 = lopt_7;
  assign lopt_70 = lopt_8;
  assign lopt_71 = lopt_9;
  assign lopt_72 = lopt_10;
  assign lopt_73 = lopt_11;
  LUT6 #(
    .INIT(64'hABBBBBBBAAAAAAAA)) 
    I_AS_INST_0_i_1
       (.I0(ex_jump_nodelay_reg),
        .I1(ex_jump_nodelay_reg_0),
        .I2(wb_exception),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(IReady),
        .O(IB_Ready));
  design_1_microblaze_0_0_MB_FDR_206 \Instruction_Prefetch_Mux[0].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[31]),
        .I0125_out(I0125_out),
        .Q(S152_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_31(of_pc_ii_31),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_207 \Instruction_Prefetch_Mux[0].PC_Mux_MUXF7 
       (.I0125_out(I0125_out),
        .Q(S152_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_31(of_pc_ii_31),
        .out(p_1_in153_in));
  design_1_microblaze_0_0_MB_FDR_208 \Instruction_Prefetch_Mux[10].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[21]),
        .I085_out(I085_out),
        .Q(S102_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_21(of_pc_ii_21),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_209 \Instruction_Prefetch_Mux[10].PC_Mux_MUXF7 
       (.I085_out(I085_out),
        .Q(S102_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_21(of_pc_ii_21),
        .out(p_1_in103_in));
  design_1_microblaze_0_0_MB_FDR_210 \Instruction_Prefetch_Mux[11].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[20]),
        .I081_out(I081_out),
        .Q(S97_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_20(of_pc_ii_20),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_211 \Instruction_Prefetch_Mux[11].PC_Mux_MUXF7 
       (.I081_out(I081_out),
        .Q(S97_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_20(of_pc_ii_20),
        .out(p_1_in98_in));
  design_1_microblaze_0_0_MB_FDR_212 \Instruction_Prefetch_Mux[12].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[19]),
        .I077_out(I077_out),
        .Q(S92_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_19(of_pc_ii_19),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_213 \Instruction_Prefetch_Mux[12].PC_Mux_MUXF7 
       (.I077_out(I077_out),
        .Q(S92_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_19(of_pc_ii_19),
        .out(p_1_in93_in));
  design_1_microblaze_0_0_MB_FDR_214 \Instruction_Prefetch_Mux[13].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[18]),
        .I073_out(I073_out),
        .Q(S87_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_18(of_pc_ii_18),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_215 \Instruction_Prefetch_Mux[13].PC_Mux_MUXF7 
       (.I073_out(I073_out),
        .Q(S87_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_18(of_pc_ii_18),
        .out(p_1_in88_in));
  design_1_microblaze_0_0_MB_FDR_216 \Instruction_Prefetch_Mux[14].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[17]),
        .I069_out(I069_out),
        .Q(S82_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_17(of_pc_ii_17),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_217 \Instruction_Prefetch_Mux[14].PC_Mux_MUXF7 
       (.I069_out(I069_out),
        .Q(S82_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_17(of_pc_ii_17),
        .out(p_1_in83_in));
  design_1_microblaze_0_0_MB_FDR_218 \Instruction_Prefetch_Mux[15].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[16]),
        .I065_out(I065_out),
        .Q(S77_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_16(of_pc_ii_16),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_219 \Instruction_Prefetch_Mux[15].PC_Mux_MUXF7 
       (.I065_out(I065_out),
        .Q(S77_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_16(of_pc_ii_16),
        .out(p_1_in78_in));
  design_1_microblaze_0_0_MB_FDR_220 \Instruction_Prefetch_Mux[16].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[15]),
        .I061_out(I061_out),
        .Q(S72_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_15(of_pc_ii_15),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_221 \Instruction_Prefetch_Mux[16].PC_Mux_MUXF7 
       (.I061_out(I061_out),
        .Q(S72_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_15(of_pc_ii_15),
        .out(p_1_in73_in));
  design_1_microblaze_0_0_MB_FDR_222 \Instruction_Prefetch_Mux[17].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[14]),
        .I057_out(I057_out),
        .Q(S67_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_14(of_pc_ii_14),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_223 \Instruction_Prefetch_Mux[17].PC_Mux_MUXF7 
       (.I057_out(I057_out),
        .Q(S67_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_14(of_pc_ii_14),
        .out(p_1_in68_in));
  design_1_microblaze_0_0_MB_FDR_224 \Instruction_Prefetch_Mux[18].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[13]),
        .I053_out(I053_out),
        .Q(S62_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_13(of_pc_ii_13),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_225 \Instruction_Prefetch_Mux[18].PC_Mux_MUXF7 
       (.I053_out(I053_out),
        .Q(S62_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_13(of_pc_ii_13),
        .out(p_1_in63_in));
  design_1_microblaze_0_0_MB_FDR_226 \Instruction_Prefetch_Mux[19].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[12]),
        .I049_out(I049_out),
        .Q(S57_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_12(of_pc_ii_12),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_227 \Instruction_Prefetch_Mux[19].PC_Mux_MUXF7 
       (.I049_out(I049_out),
        .Q(S57_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_12(of_pc_ii_12),
        .out(p_1_in58_in));
  design_1_microblaze_0_0_MB_FDR_228 \Instruction_Prefetch_Mux[1].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[30]),
        .I0121_out(I0121_out),
        .Q(S147_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_30(of_pc_ii_30),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_229 \Instruction_Prefetch_Mux[1].PC_Mux_MUXF7 
       (.I0121_out(I0121_out),
        .Q(S147_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_30(of_pc_ii_30),
        .out(p_1_in148_in));
  design_1_microblaze_0_0_MB_FDR_230 \Instruction_Prefetch_Mux[20].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[11]),
        .I045_out(I045_out),
        .Q(S52_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_11(of_pc_ii_11),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_231 \Instruction_Prefetch_Mux[20].PC_Mux_MUXF7 
       (.I045_out(I045_out),
        .Q(S52_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_11(of_pc_ii_11),
        .out(p_1_in53_in));
  design_1_microblaze_0_0_MB_FDR_232 \Instruction_Prefetch_Mux[21].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[10]),
        .I041_out(I041_out),
        .Q(S47_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_10(of_pc_ii_10),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_233 \Instruction_Prefetch_Mux[21].PC_Mux_MUXF7 
       (.I041_out(I041_out),
        .Q(S47_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_10(of_pc_ii_10),
        .out(p_1_in48_in));
  design_1_microblaze_0_0_MB_FDR_234 \Instruction_Prefetch_Mux[22].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[9]),
        .I037_out(I037_out),
        .Q(S42_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_9(of_pc_ii_9),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_235 \Instruction_Prefetch_Mux[22].PC_Mux_MUXF7 
       (.I037_out(I037_out),
        .Q(S42_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_9(of_pc_ii_9),
        .out(p_1_in43_in));
  design_1_microblaze_0_0_MB_FDR_236 \Instruction_Prefetch_Mux[23].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[8]),
        .I033_out(I033_out),
        .Q(S37_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_8(of_pc_ii_8),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_237 \Instruction_Prefetch_Mux[23].PC_Mux_MUXF7 
       (.I033_out(I033_out),
        .Q(S37_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_8(of_pc_ii_8),
        .out(p_1_in38_in));
  design_1_microblaze_0_0_MB_FDR_238 \Instruction_Prefetch_Mux[24].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[7]),
        .I029_out(I029_out),
        .Q(S32_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_7(of_pc_ii_7),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_239 \Instruction_Prefetch_Mux[24].PC_Mux_MUXF7 
       (.I029_out(I029_out),
        .Q(S32_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_7(of_pc_ii_7),
        .out(p_1_in33_in));
  design_1_microblaze_0_0_MB_FDR_240 \Instruction_Prefetch_Mux[25].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[6]),
        .I025_out(I025_out),
        .Q(S27_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_6(of_pc_ii_6),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_241 \Instruction_Prefetch_Mux[25].PC_Mux_MUXF7 
       (.I025_out(I025_out),
        .Q(S27_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_6(of_pc_ii_6),
        .out(p_1_in28_in));
  design_1_microblaze_0_0_MB_FDR_242 \Instruction_Prefetch_Mux[26].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[5]),
        .I021_out(I021_out),
        .Q(S22_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_5(of_pc_ii_5),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_243 \Instruction_Prefetch_Mux[26].PC_Mux_MUXF7 
       (.I021_out(I021_out),
        .Q(S22_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_5(of_pc_ii_5),
        .out(p_1_in23_in));
  design_1_microblaze_0_0_MB_FDR_244 \Instruction_Prefetch_Mux[27].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[4]),
        .I017_out(I017_out),
        .Q(S17_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_4(of_pc_ii_4),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_245 \Instruction_Prefetch_Mux[27].PC_Mux_MUXF7 
       (.I017_out(I017_out),
        .Q(S17_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_4(of_pc_ii_4),
        .out(p_1_in18_in));
  design_1_microblaze_0_0_MB_FDR_246 \Instruction_Prefetch_Mux[28].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[3]),
        .I013_out(I013_out),
        .Q(S12_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_3(of_pc_ii_3),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_247 \Instruction_Prefetch_Mux[28].PC_Mux_MUXF7 
       (.I013_out(I013_out),
        .Q(S12_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_3(of_pc_ii_3),
        .out(p_1_in13_in));
  design_1_microblaze_0_0_MB_FDR_248 \Instruction_Prefetch_Mux[29].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[2]),
        .I09_out(I09_out),
        .Q(S),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_2(of_pc_ii_2),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_249 \Instruction_Prefetch_Mux[29].PC_Mux_MUXF7 
       (.I09_out(I09_out),
        .Q(S),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_2(of_pc_ii_2),
        .out(p_1_in8_in));
  design_1_microblaze_0_0_MB_FDR_250 \Instruction_Prefetch_Mux[2].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[29]),
        .I0117_out(I0117_out),
        .Q(S142_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_29(of_pc_ii_29),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_251 \Instruction_Prefetch_Mux[2].PC_Mux_MUXF7 
       (.I0117_out(I0117_out),
        .Q(S142_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_29(of_pc_ii_29),
        .out(p_1_in143_in));
  design_1_microblaze_0_0_MB_FDR_252 \Instruction_Prefetch_Mux[30].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[1]),
        .I05_out(I05_out),
        .Q(\if_pc_reg[30]_0 [1]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_1(of_pc_ii_1),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_253 \Instruction_Prefetch_Mux[30].PC_Mux_MUXF7 
       (.I05_out(I05_out),
        .Q(\if_pc_reg[30]_0 [1]),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_1(of_pc_ii_1),
        .out(p_2_in4_in));
  design_1_microblaze_0_0_MB_FDR_254 \Instruction_Prefetch_Mux[31].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[0]),
        .I0(I0),
        .Q(\if_pc_reg[30]_0 [0]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_0(of_pc_ii_0),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_255 \Instruction_Prefetch_Mux[31].PC_Mux_MUXF7 
       (.I0(I0),
        .Q(\if_pc_reg[30]_0 [0]),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_0(of_pc_ii_0),
        .out(\PC_Buffer_reg[3][31]_srl4_n_0 ));
  design_1_microblaze_0_0_MB_FDR_256 \Instruction_Prefetch_Mux[3].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[28]),
        .I0113_out(I0113_out),
        .Q(S137_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_28(of_pc_ii_28),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_257 \Instruction_Prefetch_Mux[3].PC_Mux_MUXF7 
       (.I0113_out(I0113_out),
        .Q(S137_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_28(of_pc_ii_28),
        .out(p_1_in138_in));
  design_1_microblaze_0_0_MB_FDR_258 \Instruction_Prefetch_Mux[4].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[27]),
        .I0109_out(I0109_out),
        .Q(S132_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_27(of_pc_ii_27),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_259 \Instruction_Prefetch_Mux[4].PC_Mux_MUXF7 
       (.I0109_out(I0109_out),
        .Q(S132_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_27(of_pc_ii_27),
        .out(p_1_in133_in));
  design_1_microblaze_0_0_MB_FDR_260 \Instruction_Prefetch_Mux[5].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[26]),
        .I0105_out(I0105_out),
        .Q(S127_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_26(of_pc_ii_26),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_261 \Instruction_Prefetch_Mux[5].PC_Mux_MUXF7 
       (.I0105_out(I0105_out),
        .Q(S127_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_26(of_pc_ii_26),
        .out(p_1_in128_in));
  design_1_microblaze_0_0_MB_FDR_262 \Instruction_Prefetch_Mux[6].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[25]),
        .I0101_out(I0101_out),
        .Q(S122_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_25(of_pc_ii_25),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_263 \Instruction_Prefetch_Mux[6].PC_Mux_MUXF7 
       (.I0101_out(I0101_out),
        .Q(S122_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_25(of_pc_ii_25),
        .out(p_1_in123_in));
  design_1_microblaze_0_0_MB_FDR_264 \Instruction_Prefetch_Mux[7].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[24]),
        .I097_out(I097_out),
        .Q(S117_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_24(of_pc_ii_24),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_265 \Instruction_Prefetch_Mux[7].PC_Mux_MUXF7 
       (.I097_out(I097_out),
        .Q(S117_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_24(of_pc_ii_24),
        .out(p_1_in118_in));
  design_1_microblaze_0_0_MB_FDR_266 \Instruction_Prefetch_Mux[8].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[23]),
        .I093_out(I093_out),
        .Q(S112_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_23(of_pc_ii_23),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_267 \Instruction_Prefetch_Mux[8].PC_Mux_MUXF7 
       (.I093_out(I093_out),
        .Q(S112_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_23(of_pc_ii_23),
        .out(p_1_in113_in));
  design_1_microblaze_0_0_MB_FDR_268 \Instruction_Prefetch_Mux[9].Gen_Instr_DFF 
       (.Clk(Clk),
        .D(D[22]),
        .I089_out(I089_out),
        .Q(S107_in),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .if_sel_input(if_sel_input[0]),
        .of_pc_ii_22(of_pc_ii_22),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_269 \Instruction_Prefetch_Mux[9].PC_Mux_MUXF7 
       (.I089_out(I089_out),
        .Q(S107_in),
        .\Using_FPGA.Native_0 (\ex_pc_i_reg[31]_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .of_pc_ii_22(of_pc_ii_22),
        .out(p_1_in108_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][0]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][0]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S152_in),
        .Q(p_1_in153_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][10]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][10]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S102_in),
        .Q(p_1_in103_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][11]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][11]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S97_in),
        .Q(p_1_in98_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][12]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][12]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S92_in),
        .Q(p_1_in93_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][13]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][13]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S87_in),
        .Q(p_1_in88_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][14]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][14]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S82_in),
        .Q(p_1_in83_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][15]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][15]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S77_in),
        .Q(p_1_in78_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][16]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][16]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S72_in),
        .Q(p_1_in73_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][17]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][17]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S67_in),
        .Q(p_1_in68_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][18]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][18]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S62_in),
        .Q(p_1_in63_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][19]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][19]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S57_in),
        .Q(p_1_in58_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][1]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][1]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S147_in),
        .Q(p_1_in148_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][20]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][20]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S52_in),
        .Q(p_1_in53_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][21]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][21]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S47_in),
        .Q(p_1_in48_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][22]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][22]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S42_in),
        .Q(p_1_in43_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][23]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][23]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S37_in),
        .Q(p_1_in38_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][24]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][24]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S32_in),
        .Q(p_1_in33_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][25]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][25]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S27_in),
        .Q(p_1_in28_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][26]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][26]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S22_in),
        .Q(p_1_in23_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][27]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][27]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S17_in),
        .Q(p_1_in18_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][28]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][28]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S12_in),
        .Q(p_1_in13_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][29]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][29]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S),
        .Q(p_1_in8_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][2]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][2]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S142_in),
        .Q(p_1_in143_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][30]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][30]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(\if_pc_reg[30]_0 [1]),
        .Q(p_2_in4_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][31]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][31]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(\if_pc_reg[30]_0 [0]),
        .Q(\PC_Buffer_reg[3][31]_srl4_n_0 ));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][3]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][3]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S137_in),
        .Q(p_1_in138_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][4]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][4]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S132_in),
        .Q(p_1_in133_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][5]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][5]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S127_in),
        .Q(p_1_in128_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][6]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][6]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S122_in),
        .Q(p_1_in123_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][7]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][7]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S117_in),
        .Q(p_1_in118_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][8]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][8]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S112_in),
        .Q(p_1_in113_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][9]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \PC_Buffer_reg[3][9]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(if_sel_input[1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(\Using_FPGA.Native_0 ),
        .CLK(Clk),
        .D(S107_in),
        .Q(p_1_in108_in));
  design_1_microblaze_0_0_MB_MUXCY_XORCY \Using_FPGA.Incr_PC[0].MUXCY_XOR_I 
       (.LO(if_pc_carry[29]),
        .O56_out(O56_out),
        .Q(S152_in));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_270 \Using_FPGA.Incr_PC[10].MUXCY_XOR_I 
       (.LO(if_pc_carry[20]),
        .Q(S102_in),
        .\if_pc_reg[10] (\if_pc_reg[10]_0 ),
        .\if_pc_reg[10]_0 (if_pc_carry[19]),
        .lopt(lopt_41),
        .lopt_1(lopt_42),
        .lopt_2(lopt_46));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_271 \Using_FPGA.Incr_PC[11].MUXCY_XOR_I 
       (.LO(if_pc_carry[19]),
        .Q(S97_in),
        .\if_pc_reg[11] (\if_pc_reg[11]_0 ),
        .\if_pc_reg[11]_0 (if_pc_carry[18]),
        .lopt(lopt_39),
        .lopt_1(lopt_40),
        .lopt_2(lopt_45));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_272 \Using_FPGA.Incr_PC[12].MUXCY_XOR_I 
       (.LO(if_pc_carry[18]),
        .Q(S92_in),
        .\if_pc_reg[12] (\if_pc_reg[12]_0 ),
        .\if_pc_reg[12]_0 (if_pc_carry[17]),
        .lopt(lopt_39),
        .lopt_1(lopt_40),
        .lopt_10(lopt_46),
        .lopt_11(lopt_47),
        .lopt_12(lopt_84),
        .lopt_13(lopt_85),
        .lopt_14(lopt_86),
        .lopt_15(lopt_87),
        .lopt_16(lopt_88),
        .lopt_17(lopt_89),
        .lopt_18(lopt_90),
        .lopt_19(lopt_91),
        .lopt_2(S97_in),
        .lopt_20(lopt_92),
        .lopt_3(lopt_41),
        .lopt_4(lopt_42),
        .lopt_5(S102_in),
        .lopt_6(lopt_43),
        .lopt_7(lopt_44),
        .lopt_8(S107_in),
        .lopt_9(lopt_45));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_273 \Using_FPGA.Incr_PC[13].MUXCY_XOR_I 
       (.LO(if_pc_carry[17]),
        .Q(S87_in),
        .\if_pc_reg[13] (\if_pc_reg[13]_0 ),
        .\if_pc_reg[13]_0 (if_pc_carry[16]),
        .lopt(lopt_34),
        .lopt_1(lopt_35),
        .lopt_2(lopt_38));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_274 \Using_FPGA.Incr_PC[14].MUXCY_XOR_I 
       (.LO(if_pc_carry[16]),
        .Q(S82_in),
        .\if_pc_reg[14] (\if_pc_reg[14]_0 ),
        .\if_pc_reg[14]_0 (if_pc_carry[15]),
        .lopt(lopt_32),
        .lopt_1(lopt_33),
        .lopt_2(lopt_37));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_275 \Using_FPGA.Incr_PC[15].MUXCY_XOR_I 
       (.LO(if_pc_carry[15]),
        .Q(S77_in),
        .\if_pc_reg[15] (\if_pc_reg[15]_0 ),
        .\if_pc_reg[15]_0 (if_pc_carry[14]),
        .lopt(lopt_30),
        .lopt_1(lopt_31),
        .lopt_2(lopt_36));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_276 \Using_FPGA.Incr_PC[16].MUXCY_XOR_I 
       (.LO(if_pc_carry[14]),
        .Q(S72_in),
        .\if_pc_reg[16] (\if_pc_reg[16]_0 ),
        .\if_pc_reg[16]_0 (if_pc_carry[13]),
        .lopt(lopt_30),
        .lopt_1(lopt_31),
        .lopt_10(lopt_37),
        .lopt_11(lopt_38),
        .lopt_12(lopt_84),
        .lopt_13(lopt_85),
        .lopt_14(lopt_86),
        .lopt_15(lopt_87),
        .lopt_16(lopt_88),
        .lopt_17(lopt_89),
        .lopt_18(lopt_90),
        .lopt_19(lopt_91),
        .lopt_2(S77_in),
        .lopt_20(lopt_44),
        .lopt_21(lopt_42),
        .lopt_22(lopt_40),
        .lopt_23(lopt_92),
        .lopt_24(S107_in),
        .lopt_25(S102_in),
        .lopt_26(S97_in),
        .lopt_27(S92_in),
        .lopt_3(lopt_32),
        .lopt_4(lopt_33),
        .lopt_5(S82_in),
        .lopt_6(lopt_34),
        .lopt_7(lopt_35),
        .lopt_8(S87_in),
        .lopt_9(lopt_36));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_277 \Using_FPGA.Incr_PC[17].MUXCY_XOR_I 
       (.LO(if_pc_carry[13]),
        .Q(S67_in),
        .\if_pc_reg[17] (\if_pc_reg[17]_0 ),
        .\if_pc_reg[17]_0 (if_pc_carry[12]),
        .lopt(lopt_25),
        .lopt_1(lopt_26),
        .lopt_2(lopt_29));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_278 \Using_FPGA.Incr_PC[18].MUXCY_XOR_I 
       (.LO(if_pc_carry[12]),
        .Q(S62_in),
        .\if_pc_reg[18] (\if_pc_reg[18]_0 ),
        .\if_pc_reg[18]_0 (if_pc_carry[11]),
        .lopt(lopt_23),
        .lopt_1(lopt_24),
        .lopt_2(lopt_28));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_279 \Using_FPGA.Incr_PC[19].MUXCY_XOR_I 
       (.LO(if_pc_carry[11]),
        .Q(S57_in),
        .\if_pc_reg[19] (\if_pc_reg[19]_0 ),
        .\if_pc_reg[19]_0 (if_pc_carry[10]),
        .lopt(lopt_21),
        .lopt_1(lopt_22),
        .lopt_2(lopt_27));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_280 \Using_FPGA.Incr_PC[1].MUXCY_XOR_I 
       (.LO(if_pc_carry[29]),
        .Q(S147_in),
        .\if_pc_reg[1] (\if_pc_reg[1]_0 ),
        .\if_pc_reg[1]_0 (if_pc_carry[28]),
        .lopt(lopt_61),
        .lopt_1(lopt_62),
        .lopt_2(lopt_65));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_281 \Using_FPGA.Incr_PC[20].MUXCY_XOR_I 
       (.LO(if_pc_carry[10]),
        .Q(S52_in),
        .\if_pc_reg[20] (\if_pc_reg[20]_0 ),
        .\if_pc_reg[20]_0 (if_pc_carry[9]),
        .lopt(lopt_21),
        .lopt_1(lopt_22),
        .lopt_10(lopt_28),
        .lopt_11(lopt_29),
        .lopt_12(lopt_75),
        .lopt_13(lopt_76),
        .lopt_14(lopt_77),
        .lopt_15(lopt_78),
        .lopt_16(lopt_79),
        .lopt_17(lopt_80),
        .lopt_18(lopt_81),
        .lopt_19(lopt_82),
        .lopt_2(S57_in),
        .lopt_20(lopt_83),
        .lopt_3(lopt_23),
        .lopt_4(lopt_24),
        .lopt_5(S62_in),
        .lopt_6(lopt_25),
        .lopt_7(lopt_26),
        .lopt_8(S67_in),
        .lopt_9(lopt_27));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_282 \Using_FPGA.Incr_PC[21].MUXCY_XOR_I 
       (.LO(if_pc_carry[9]),
        .Q(S47_in),
        .\if_pc_reg[21] (\if_pc_reg[21]_0 ),
        .\if_pc_reg[21]_0 (if_pc_carry[8]),
        .lopt(\^lopt_16 ),
        .lopt_1(\^lopt_17 ),
        .lopt_2(lopt_20));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_283 \Using_FPGA.Incr_PC[22].MUXCY_XOR_I 
       (.LO(if_pc_carry[8]),
        .Q(S42_in),
        .\if_pc_reg[22] (\if_pc_reg[22]_0 ),
        .\if_pc_reg[22]_0 (if_pc_carry[7]),
        .lopt(\^lopt_14 ),
        .lopt_1(\^lopt_15 ),
        .lopt_2(\^lopt_19 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_284 \Using_FPGA.Incr_PC[23].MUXCY_XOR_I 
       (.LO(if_pc_carry[7]),
        .Q(S37_in),
        .\if_pc_reg[23] (\if_pc_reg[23]_0 ),
        .\if_pc_reg[23]_0 (if_pc_carry[6]),
        .lopt(\^lopt_12 ),
        .lopt_1(\^lopt_13 ),
        .lopt_2(\^lopt_18 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_285 \Using_FPGA.Incr_PC[24].MUXCY_XOR_I 
       (.LO(if_pc_carry[6]),
        .Q(S32_in),
        .\if_pc_reg[24] (\if_pc_reg[24]_0 ),
        .\if_pc_reg[24]_0 (if_pc_carry[5]),
        .lopt(\^lopt_12 ),
        .lopt_1(\^lopt_13 ),
        .lopt_10(\^lopt_19 ),
        .lopt_11(lopt_20),
        .lopt_12(lopt_75),
        .lopt_13(lopt_76),
        .lopt_14(lopt_77),
        .lopt_15(lopt_78),
        .lopt_16(lopt_79),
        .lopt_17(lopt_80),
        .lopt_18(lopt_81),
        .lopt_19(lopt_82),
        .lopt_2(S37_in),
        .lopt_20(lopt_26),
        .lopt_21(lopt_24),
        .lopt_22(lopt_22),
        .lopt_23(lopt_83),
        .lopt_24(S67_in),
        .lopt_25(S62_in),
        .lopt_26(S57_in),
        .lopt_27(S52_in),
        .lopt_3(\^lopt_14 ),
        .lopt_4(\^lopt_15 ),
        .lopt_5(S42_in),
        .lopt_6(\^lopt_16 ),
        .lopt_7(\^lopt_17 ),
        .lopt_8(S47_in),
        .lopt_9(\^lopt_18 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_286 \Using_FPGA.Incr_PC[25].MUXCY_XOR_I 
       (.LO(if_pc_carry[5]),
        .Q(S27_in),
        .\if_pc_reg[25] (\if_pc_reg[25]_0 ),
        .\if_pc_reg[25]_0 (if_pc_carry[4]),
        .lopt(\^lopt_7 ),
        .lopt_1(\^lopt_8 ),
        .lopt_2(\^lopt_11 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_287 \Using_FPGA.Incr_PC[26].MUXCY_XOR_I 
       (.LO(if_pc_carry[4]),
        .Q(S22_in),
        .\if_pc_reg[26] (\if_pc_reg[26]_0 ),
        .\if_pc_reg[26]_0 (if_pc_carry[3]),
        .lopt(\^lopt_5 ),
        .lopt_1(\^lopt_6 ),
        .lopt_2(\^lopt_10 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_288 \Using_FPGA.Incr_PC[27].MUXCY_XOR_I 
       (.LO(if_pc_carry[3]),
        .Q(S17_in),
        .\if_pc_reg[27] (\if_pc_reg[27]_0 ),
        .\if_pc_reg[27]_0 (if_pc_carry[2]),
        .lopt(\^lopt_3 ),
        .lopt_1(\^lopt_4 ),
        .lopt_2(\^lopt_9 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_289 \Using_FPGA.Incr_PC[28].MUXCY_XOR_I 
       (.LO(if_pc_carry[2]),
        .Q(S12_in),
        .\if_pc_reg[28] (\if_pc_reg[28]_0 ),
        .\if_pc_reg[28]_0 (if_pc_carry[1]),
        .lopt(\^lopt_3 ),
        .lopt_1(\^lopt_4 ),
        .lopt_10(\^lopt_10 ),
        .lopt_11(\^lopt_11 ),
        .lopt_12(lopt_66),
        .lopt_13(lopt_67),
        .lopt_14(lopt_68),
        .lopt_15(lopt_69),
        .lopt_16(lopt_70),
        .lopt_17(lopt_71),
        .lopt_18(lopt_72),
        .lopt_19(lopt_73),
        .lopt_2(S17_in),
        .lopt_20(lopt_74),
        .lopt_3(\^lopt_5 ),
        .lopt_4(\^lopt_6 ),
        .lopt_5(S22_in),
        .lopt_6(\^lopt_7 ),
        .lopt_7(\^lopt_8 ),
        .lopt_8(S27_in),
        .lopt_9(\^lopt_9 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_290 \Using_FPGA.Incr_PC[29].MUXCY_XOR_I 
       (.CI(CI),
        .LO(if_pc_carry[1]),
        .O(O),
        .Q(S),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_2(\^lopt_2 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_291 \Using_FPGA.Incr_PC[2].MUXCY_XOR_I 
       (.LO(if_pc_carry[28]),
        .Q(S142_in),
        .\if_pc_reg[2] (\if_pc_reg[2]_0 ),
        .\if_pc_reg[2]_0 (if_pc_carry[27]),
        .lopt(lopt_59),
        .lopt_1(lopt_60),
        .lopt_2(lopt_64));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_292 \Using_FPGA.Incr_PC[3].MUXCY_XOR_I 
       (.LO(if_pc_carry[27]),
        .Q(S137_in),
        .\if_pc_reg[3] (\if_pc_reg[3]_0 ),
        .\if_pc_reg[3]_0 (if_pc_carry[26]),
        .lopt(lopt_57),
        .lopt_1(lopt_58),
        .lopt_2(lopt_63));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_293 \Using_FPGA.Incr_PC[4].MUXCY_XOR_I 
       (.LO(if_pc_carry[26]),
        .Q(S132_in),
        .\if_pc_reg[4] (\if_pc_reg[4]_0 ),
        .\if_pc_reg[4]_0 (if_pc_carry[25]),
        .lopt(lopt_57),
        .lopt_1(lopt_58),
        .lopt_10(lopt_64),
        .lopt_11(lopt_65),
        .lopt_12(lopt_93),
        .lopt_13(lopt_94),
        .lopt_14(lopt_95),
        .lopt_15(lopt_96),
        .lopt_16(lopt_97),
        .lopt_17(lopt_98),
        .lopt_18(lopt_99),
        .lopt_19(lopt_100),
        .lopt_2(S137_in),
        .lopt_20(lopt_101),
        .lopt_3(lopt_59),
        .lopt_4(lopt_60),
        .lopt_5(S142_in),
        .lopt_6(lopt_61),
        .lopt_7(lopt_62),
        .lopt_8(S147_in),
        .lopt_9(lopt_63));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_294 \Using_FPGA.Incr_PC[5].MUXCY_XOR_I 
       (.LO(if_pc_carry[25]),
        .Q(S127_in),
        .\if_pc_reg[5] (\if_pc_reg[5]_0 ),
        .\if_pc_reg[5]_0 (if_pc_carry[24]),
        .lopt(lopt_52),
        .lopt_1(lopt_53),
        .lopt_2(lopt_56));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_295 \Using_FPGA.Incr_PC[6].MUXCY_XOR_I 
       (.LO(if_pc_carry[24]),
        .Q(S122_in),
        .\if_pc_reg[6] (\if_pc_reg[6]_0 ),
        .\if_pc_reg[6]_0 (if_pc_carry[23]),
        .lopt(lopt_50),
        .lopt_1(lopt_51),
        .lopt_2(lopt_55));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_296 \Using_FPGA.Incr_PC[7].MUXCY_XOR_I 
       (.LO(if_pc_carry[23]),
        .Q(S117_in),
        .\if_pc_reg[7] (\if_pc_reg[7]_0 ),
        .\if_pc_reg[7]_0 (if_pc_carry[22]),
        .lopt(lopt_48),
        .lopt_1(lopt_49),
        .lopt_2(lopt_54));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_297 \Using_FPGA.Incr_PC[8].MUXCY_XOR_I 
       (.LO(if_pc_carry[22]),
        .Q(S112_in),
        .\if_pc_reg[8] (\if_pc_reg[8]_0 ),
        .\if_pc_reg[8]_0 (if_pc_carry[21]),
        .lopt(lopt_48),
        .lopt_1(lopt_49),
        .lopt_10(lopt_55),
        .lopt_11(lopt_56),
        .lopt_12(lopt_93),
        .lopt_13(lopt_94),
        .lopt_14(lopt_95),
        .lopt_15(lopt_96),
        .lopt_16(lopt_97),
        .lopt_17(lopt_98),
        .lopt_18(lopt_99),
        .lopt_19(lopt_100),
        .lopt_2(S117_in),
        .lopt_20(lopt_62),
        .lopt_21(lopt_60),
        .lopt_22(lopt_58),
        .lopt_23(lopt_101),
        .lopt_24(S147_in),
        .lopt_25(S142_in),
        .lopt_26(S137_in),
        .lopt_27(S132_in),
        .lopt_3(lopt_50),
        .lopt_4(lopt_51),
        .lopt_5(S122_in),
        .lopt_6(lopt_52),
        .lopt_7(lopt_53),
        .lopt_8(S127_in),
        .lopt_9(lopt_54));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_298 \Using_FPGA.Incr_PC[9].MUXCY_XOR_I 
       (.CI(if_pc_carry[20]),
        .LO(if_pc_carry[21]),
        .Q(S107_in),
        .\if_pc_reg[9] (\if_pc_reg[9]_0 ),
        .lopt(lopt_43),
        .lopt_1(lopt_44),
        .lopt_2(lopt_47));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[0] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[31]),
        .Q(ex_pc[0]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[10] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[21]),
        .Q(ex_pc[10]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[11] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[20]),
        .Q(ex_pc[11]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[12] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[19]),
        .Q(ex_pc[12]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[13] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[18]),
        .Q(ex_pc[13]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[14] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[17]),
        .Q(ex_pc[14]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[15] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[16]),
        .Q(ex_pc[15]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[16] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[15]),
        .Q(ex_pc[16]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[17] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[14]),
        .Q(ex_pc[17]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[18] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[13]),
        .Q(ex_pc[18]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[19] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[12]),
        .Q(ex_pc[19]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[1] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[30]),
        .Q(ex_pc[1]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[20] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[11]),
        .Q(ex_pc[20]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[21] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[10]),
        .Q(ex_pc[21]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[22] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[9]),
        .Q(ex_pc[22]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[23] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[8]),
        .Q(ex_pc[23]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[24] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[7]),
        .Q(ex_pc[24]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[25] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[6]),
        .Q(ex_pc[25]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[26] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[5]),
        .Q(ex_pc[26]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[27] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[4]),
        .Q(ex_pc[27]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[28] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[3]),
        .Q(ex_pc[28]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[29] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[2]),
        .Q(ex_pc[29]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[2] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[29]),
        .Q(ex_pc[2]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[30] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[1]),
        .Q(ex_pc[30]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[31] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[0]),
        .Q(ex_pc[31]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[3] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[28]),
        .Q(ex_pc[3]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[4] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[27]),
        .Q(ex_pc[4]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[5] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[26]),
        .Q(ex_pc[5]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[6] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[25]),
        .Q(ex_pc[6]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[7] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[24]),
        .Q(ex_pc[7]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[8] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[23]),
        .Q(ex_pc[8]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \ex_pc_i_reg[9] 
       (.C(Clk),
        .CE(\ex_pc_i_reg[31]_0 ),
        .D(D[22]),
        .Q(ex_pc[9]),
        .R(sync_reset));
  FDSE \if_pc_reg[0] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [31]),
        .Q(S152_in),
        .S(sync_reset));
  FDSE \if_pc_reg[10] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [21]),
        .Q(S102_in),
        .S(sync_reset));
  FDSE \if_pc_reg[11] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [20]),
        .Q(S97_in),
        .S(sync_reset));
  FDSE \if_pc_reg[12] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [19]),
        .Q(S92_in),
        .S(sync_reset));
  FDSE \if_pc_reg[13] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [18]),
        .Q(S87_in),
        .S(sync_reset));
  FDSE \if_pc_reg[14] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [17]),
        .Q(S82_in),
        .S(sync_reset));
  FDSE \if_pc_reg[15] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [16]),
        .Q(S77_in),
        .S(sync_reset));
  FDSE \if_pc_reg[16] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [15]),
        .Q(S72_in),
        .S(sync_reset));
  FDSE \if_pc_reg[17] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [14]),
        .Q(S67_in),
        .S(sync_reset));
  FDSE \if_pc_reg[18] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [13]),
        .Q(S62_in),
        .S(sync_reset));
  FDSE \if_pc_reg[19] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [12]),
        .Q(S57_in),
        .S(sync_reset));
  FDSE \if_pc_reg[1] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [30]),
        .Q(S147_in),
        .S(sync_reset));
  FDSE \if_pc_reg[20] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [11]),
        .Q(S52_in),
        .S(sync_reset));
  FDSE \if_pc_reg[21] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [10]),
        .Q(S47_in),
        .S(sync_reset));
  FDSE \if_pc_reg[22] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [9]),
        .Q(S42_in),
        .S(sync_reset));
  FDSE \if_pc_reg[23] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [8]),
        .Q(S37_in),
        .S(sync_reset));
  FDSE \if_pc_reg[24] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [7]),
        .Q(S32_in),
        .S(sync_reset));
  FDSE \if_pc_reg[25] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [6]),
        .Q(S27_in),
        .S(sync_reset));
  FDSE \if_pc_reg[26] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [5]),
        .Q(S22_in),
        .S(sync_reset));
  FDSE \if_pc_reg[27] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [4]),
        .Q(S17_in),
        .S(sync_reset));
  FDSE \if_pc_reg[28] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [3]),
        .Q(S12_in),
        .S(sync_reset));
  FDSE \if_pc_reg[29] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [2]),
        .Q(S),
        .S(sync_reset));
  FDSE \if_pc_reg[2] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [29]),
        .Q(S142_in),
        .S(sync_reset));
  FDRE \if_pc_reg[30] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [1]),
        .Q(\if_pc_reg[30]_0 [1]),
        .R(sync_reset));
  FDRE \if_pc_reg[31] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [0]),
        .Q(\if_pc_reg[30]_0 [0]),
        .R(sync_reset));
  FDSE \if_pc_reg[3] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [28]),
        .Q(S137_in),
        .S(sync_reset));
  FDSE \if_pc_reg[4] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [27]),
        .Q(S132_in),
        .S(sync_reset));
  FDSE \if_pc_reg[5] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [26]),
        .Q(S127_in),
        .S(sync_reset));
  FDSE \if_pc_reg[6] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [25]),
        .Q(S122_in),
        .S(sync_reset));
  FDSE \if_pc_reg[7] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [24]),
        .Q(S117_in),
        .S(sync_reset));
  FDSE \if_pc_reg[8] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [23]),
        .Q(S112_in),
        .S(sync_reset));
  FDSE \if_pc_reg[9] 
       (.C(Clk),
        .CE(\if_pc_reg[0]_0 ),
        .D(\if_pc_reg[0]_1 [22]),
        .Q(S107_in),
        .S(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[0] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[0]),
        .Q(\mem_pc_i_reg[0]_0 [31]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[10] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[10]),
        .Q(\mem_pc_i_reg[0]_0 [21]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[11] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[11]),
        .Q(\mem_pc_i_reg[0]_0 [20]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[12] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[12]),
        .Q(\mem_pc_i_reg[0]_0 [19]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[13] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[13]),
        .Q(\mem_pc_i_reg[0]_0 [18]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[14] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[14]),
        .Q(\mem_pc_i_reg[0]_0 [17]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[15] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[15]),
        .Q(\mem_pc_i_reg[0]_0 [16]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[16] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[16]),
        .Q(\mem_pc_i_reg[0]_0 [15]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[17] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[17]),
        .Q(\mem_pc_i_reg[0]_0 [14]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[18] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[18]),
        .Q(\mem_pc_i_reg[0]_0 [13]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[19] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[19]),
        .Q(\mem_pc_i_reg[0]_0 [12]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[1] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[1]),
        .Q(\mem_pc_i_reg[0]_0 [30]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[20] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[20]),
        .Q(\mem_pc_i_reg[0]_0 [11]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[21] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[21]),
        .Q(\mem_pc_i_reg[0]_0 [10]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[22] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[22]),
        .Q(\mem_pc_i_reg[0]_0 [9]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[23] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[23]),
        .Q(\mem_pc_i_reg[0]_0 [8]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[24] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[24]),
        .Q(\mem_pc_i_reg[0]_0 [7]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[25] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[25]),
        .Q(\mem_pc_i_reg[0]_0 [6]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[26] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[26]),
        .Q(\mem_pc_i_reg[0]_0 [5]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[27] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[27]),
        .Q(\mem_pc_i_reg[0]_0 [4]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[28] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[28]),
        .Q(\mem_pc_i_reg[0]_0 [3]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[29] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[29]),
        .Q(\mem_pc_i_reg[0]_0 [2]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[2] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[2]),
        .Q(\mem_pc_i_reg[0]_0 [29]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[30] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[30]),
        .Q(\mem_pc_i_reg[0]_0 [1]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[31] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[31]),
        .Q(\mem_pc_i_reg[0]_0 [0]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[3] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[3]),
        .Q(\mem_pc_i_reg[0]_0 [28]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[4] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[4]),
        .Q(\mem_pc_i_reg[0]_0 [27]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[5] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[5]),
        .Q(\mem_pc_i_reg[0]_0 [26]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[6] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[6]),
        .Q(\mem_pc_i_reg[0]_0 [25]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[7] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[7]),
        .Q(\mem_pc_i_reg[0]_0 [24]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[8] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[8]),
        .Q(\mem_pc_i_reg[0]_0 [23]),
        .R(sync_reset));
  FDRE #(
    .INIT(1'b0)) 
    \mem_pc_i_reg[9] 
       (.C(Clk),
        .CE(E),
        .D(ex_pc[9]),
        .Q(\mem_pc_i_reg[0]_0 [22]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "PreFetch_Buffer_gti" *) 
module design_1_microblaze_0_0_PreFetch_Buffer_gti
   (\Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    IReady_0,
    of_valid,
    of_instr,
    D,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    of_predecode,
    \Using_FPGA.Native_5 ,
    ex_gpr_write_reg,
    ex_is_div_instr_I_reg,
    if_pre_buffer_addr,
    if_fetch_in_progress_reg,
    \Using_FPGA.Native_6 ,
    if_fetch_for_timing_optimization1,
    \Using_FPGA.Native_7 ,
    ex_op1_cmp_eq1,
    ex_op1_cmp_eq_n5_out,
    \Using_FPGA.Native_8 ,
    use_Reg_Neg_DI1_out,
    force_Val10_out,
    use_Reg_Neg_S3_out,
    force12_out,
    \Using_FPGA.Native_9 ,
    \Using_FPGA.Native_10 ,
    ex_move_to_MSR_instr93_out,
    of_Sel_SPR_MSR1,
    ex_sel_alu_i_reg,
    of_use_op2_s,
    ex_sel_alu_i_reg_0,
    ex_sel_alu_i_reg_1,
    \Using_FPGA.Native_11 ,
    p_9_in,
    ex_sel_alu_i0,
    \Using_FPGA.Native_12 ,
    ex_load_shift_carry0,
    ex_mbar_is_sleep_cmb,
    ex_mbar_decode_cmb,
    \Using_FPGA.Native_13 ,
    D224_out,
    p_2_in,
    \Using_FPGA.Native_14 ,
    \Using_FPGA.Native_15 ,
    \Using_FPGA.Native_16 ,
    \Serial_Dbg_Intf.control_reg_reg[8] ,
    ex_enable_sext_shift_i0,
    \Using_FPGA.Native_17 ,
    if_missed_fetch_reg,
    wb_exception_i_reg,
    \Using_FPGA.Native_18 ,
    \Using_FPGA.Native_19 ,
    \Using_FPGA.Native_20 ,
    \Using_FPGA.Native_21 ,
    \Using_FPGA.Native_22 ,
    ex_branch_with_delayslot_reg,
    \Using_FPGA.Native_23 ,
    \Using_FPGA.Native_24 ,
    \Using_FPGA.Native_25 ,
    \Using_FPGA.Native_26 ,
    \Using_FPGA.Native_27 ,
    \Using_FPGA.Native_28 ,
    \Using_FPGA.Native_29 ,
    \Using_FPGA.Native_30 ,
    \Using_FPGA.Native_31 ,
    \Using_FPGA.Native_32 ,
    \Using_FPGA.Native_33 ,
    \Using_FPGA.Native_34 ,
    \Using_FPGA.Native_35 ,
    \Using_FPGA.Native_36 ,
    \Using_FPGA.Native_37 ,
    \Using_FPGA.Native_38 ,
    \Using_FPGA.Native_39 ,
    \Using_FPGA.Native_40 ,
    \Using_FPGA.Native_41 ,
    \Using_FPGA.Native_42 ,
    \Using_FPGA.Native_43 ,
    \Using_FPGA.Native_44 ,
    \Using_FPGA.Native_45 ,
    \Using_FPGA.Native_46 ,
    \Using_FPGA.Native_47 ,
    \Using_FPGA.Native_48 ,
    \Using_FPGA.Native_49 ,
    \Using_FPGA.Native_50 ,
    \Using_FPGA.Native_51 ,
    \Using_FPGA.Native_52 ,
    \Using_FPGA.Native_53 ,
    \Using_FPGA.Native_54 ,
    \Using_FPGA.Native_55 ,
    \Using_FPGA.Native_56 ,
    \Using_FPGA.Native_57 ,
    \Using_FPGA.Native_58 ,
    I1_0,
    of_Sel_SPR_MSR88_out,
    ex_is_multi_or_load_instr0,
    of_op1_sel_spr,
    Dbg_Clean_Stop0,
    ex_set_bip,
    \Using_FPGA.Native_59 ,
    \Using_FPGA.Native_60 ,
    I5,
    sync_reset,
    Clk,
    I139_out,
    ex_branch_with_delayslot_i_reg_0,
    ex_gpr_write_reg_0,
    wb_exception,
    EX_Is_Div_Instr,
    E,
    ex_jump,
    out,
    if_fetch_in_progress,
    IB_Ready,
    in0,
    Q,
    in,
    \EX_Op2_reg[31] ,
    \EX_Op2_reg[31]_0 ,
    MEM_Fwd,
    GPR_Op2,
    \EX_Op2_reg[30] ,
    \EX_Op2_reg[30]_0 ,
    \EX_Op2_reg[29] ,
    \EX_Op2_reg[29]_0 ,
    \EX_Op2_reg[28] ,
    \EX_Op2_reg[28]_0 ,
    \EX_Op2_reg[27] ,
    \EX_Op2_reg[27]_0 ,
    \EX_Op2_reg[26] ,
    \EX_Op2_reg[26]_0 ,
    \EX_Op2_reg[25] ,
    \EX_Op2_reg[25]_0 ,
    \EX_Op2_reg[24] ,
    \EX_Op2_reg[24]_0 ,
    \EX_Op2_reg[23] ,
    \EX_Op2_reg[16] ,
    \EX_Op2_reg[22] ,
    \EX_Op2_reg[21] ,
    \EX_Op2_reg[20] ,
    \EX_Op2_reg[19] ,
    \EX_Op2_reg[18] ,
    \EX_Op2_reg[17] ,
    \EX_Op2_reg[16]_0 ,
    \EX_Op2_reg[15] ,
    \EX_Op2_reg[15]_0 ,
    \EX_Op2_reg[0] ,
    \EX_Op2_reg[0]_0 ,
    \EX_Op2_reg[14] ,
    \EX_Op2_reg[14]_0 ,
    \EX_Op2_reg[13] ,
    \EX_Op2_reg[13]_0 ,
    \EX_Op2_reg[12] ,
    \EX_Op2_reg[12]_0 ,
    \EX_Op2_reg[11] ,
    \EX_Op2_reg[11]_0 ,
    \EX_Op2_reg[10] ,
    \EX_Op2_reg[10]_0 ,
    \EX_Op2_reg[9] ,
    \EX_Op2_reg[9]_0 ,
    \EX_Op2_reg[8] ,
    \EX_Op2_reg[8]_0 ,
    \EX_Op2_reg[7] ,
    \EX_Op2_reg[7]_0 ,
    \EX_Op2_reg[6] ,
    \EX_Op2_reg[6]_0 ,
    \EX_Op2_reg[5] ,
    \EX_Op2_reg[5]_0 ,
    \EX_Op2_reg[4] ,
    \EX_Op2_reg[4]_0 ,
    \EX_Op2_reg[3] ,
    \EX_Op2_reg[3]_0 ,
    \EX_Op2_reg[2] ,
    \EX_Op2_reg[2]_0 ,
    \EX_Op2_reg[1] ,
    \EX_Op2_reg[1]_0 ,
    \EX_Op2_reg[0]_1 ,
    \EX_Op2_reg[0]_2 ,
    GPR_Op3,
    \Using_FPGA.Native_i_5__0 ,
    mem_valid_instr,
    mem_gpr_write,
    p_213_in,
    GPR_Op1,
    \EX_Op3[0]_i_2 ,
    \Using_FPGA.Native_i_5__0_0 ,
    p_216_in,
    \Using_FPGA.Native_i_5__0_1 ,
    ex_mbar_is_sleep,
    ex_mbar_decode,
    \Performance_Debug_Control.ex_brki_hit_reg ,
    \EX_Op3[0]_i_6 ,
    I4,
    I0,
    if_missed_fetch,
    ex_gpr_write_dbg__0,
    ex_jump_nodelay,
    IReady,
    \Using_FPGA.Native_61 ,
    \Using_FPGA.Native_62 ,
    ex_branch_with_delayslot,
    ex_jump_q,
    \EX_Op1_reg[0] ,
    ex_MSR);
  output [1:0]\Using_FPGA.Native ;
  output \Using_FPGA.Native_0 ;
  output IReady_0;
  output of_valid;
  output [5:0]of_instr;
  output [1:0]D;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  output \Using_FPGA.Native_3 ;
  output [20:0]\Using_FPGA.Native_4 ;
  output [0:10]of_predecode;
  output \Using_FPGA.Native_5 ;
  output ex_gpr_write_reg;
  output ex_is_div_instr_I_reg;
  output [0:0]if_pre_buffer_addr;
  output [0:0]if_fetch_in_progress_reg;
  output [1:0]\Using_FPGA.Native_6 ;
  output if_fetch_for_timing_optimization1;
  output \Using_FPGA.Native_7 ;
  output ex_op1_cmp_eq1;
  output ex_op1_cmp_eq_n5_out;
  output \Using_FPGA.Native_8 ;
  output use_Reg_Neg_DI1_out;
  output force_Val10_out;
  output use_Reg_Neg_S3_out;
  output force12_out;
  output [1:0]\Using_FPGA.Native_9 ;
  output \Using_FPGA.Native_10 ;
  output ex_move_to_MSR_instr93_out;
  output of_Sel_SPR_MSR1;
  output [31:0]ex_sel_alu_i_reg;
  output of_use_op2_s;
  output [31:0]ex_sel_alu_i_reg_0;
  output [31:0]ex_sel_alu_i_reg_1;
  output [0:0]\Using_FPGA.Native_11 ;
  output p_9_in;
  output ex_sel_alu_i0;
  output \Using_FPGA.Native_12 ;
  output ex_load_shift_carry0;
  output ex_mbar_is_sleep_cmb;
  output ex_mbar_decode_cmb;
  output \Using_FPGA.Native_13 ;
  output D224_out;
  output p_2_in;
  output [1:0]\Using_FPGA.Native_14 ;
  output \Using_FPGA.Native_15 ;
  output \Using_FPGA.Native_16 ;
  output \Serial_Dbg_Intf.control_reg_reg[8] ;
  output ex_enable_sext_shift_i0;
  output \Using_FPGA.Native_17 ;
  output if_missed_fetch_reg;
  output wb_exception_i_reg;
  output \Using_FPGA.Native_18 ;
  output \Using_FPGA.Native_19 ;
  output \Using_FPGA.Native_20 ;
  output \Using_FPGA.Native_21 ;
  output \Using_FPGA.Native_22 ;
  output ex_branch_with_delayslot_reg;
  output \Using_FPGA.Native_23 ;
  output \Using_FPGA.Native_24 ;
  output \Using_FPGA.Native_25 ;
  output \Using_FPGA.Native_26 ;
  output \Using_FPGA.Native_27 ;
  output \Using_FPGA.Native_28 ;
  output \Using_FPGA.Native_29 ;
  output \Using_FPGA.Native_30 ;
  output \Using_FPGA.Native_31 ;
  output \Using_FPGA.Native_32 ;
  output \Using_FPGA.Native_33 ;
  output \Using_FPGA.Native_34 ;
  output \Using_FPGA.Native_35 ;
  output \Using_FPGA.Native_36 ;
  output \Using_FPGA.Native_37 ;
  output \Using_FPGA.Native_38 ;
  output \Using_FPGA.Native_39 ;
  output \Using_FPGA.Native_40 ;
  output \Using_FPGA.Native_41 ;
  output \Using_FPGA.Native_42 ;
  output \Using_FPGA.Native_43 ;
  output \Using_FPGA.Native_44 ;
  output \Using_FPGA.Native_45 ;
  output \Using_FPGA.Native_46 ;
  output \Using_FPGA.Native_47 ;
  output \Using_FPGA.Native_48 ;
  output \Using_FPGA.Native_49 ;
  output \Using_FPGA.Native_50 ;
  output \Using_FPGA.Native_51 ;
  output \Using_FPGA.Native_52 ;
  output \Using_FPGA.Native_53 ;
  output \Using_FPGA.Native_54 ;
  output \Using_FPGA.Native_55 ;
  output \Using_FPGA.Native_56 ;
  output \Using_FPGA.Native_57 ;
  output \Using_FPGA.Native_58 ;
  output I1_0;
  output of_Sel_SPR_MSR88_out;
  output ex_is_multi_or_load_instr0;
  output of_op1_sel_spr;
  output Dbg_Clean_Stop0;
  output ex_set_bip;
  output [0:0]\Using_FPGA.Native_59 ;
  input \Using_FPGA.Native_60 ;
  input I5;
  input sync_reset;
  input Clk;
  input I139_out;
  input ex_branch_with_delayslot_i_reg_0;
  input ex_gpr_write_reg_0;
  input wb_exception;
  input EX_Is_Div_Instr;
  input [0:0]E;
  input ex_jump;
  input out;
  input if_fetch_in_progress;
  input IB_Ready;
  input in0;
  input [1:0]Q;
  input [32:0]in;
  input \EX_Op2_reg[31] ;
  input \EX_Op2_reg[31]_0 ;
  input [0:31]MEM_Fwd;
  input [0:31]GPR_Op2;
  input \EX_Op2_reg[30] ;
  input \EX_Op2_reg[30]_0 ;
  input \EX_Op2_reg[29] ;
  input \EX_Op2_reg[29]_0 ;
  input \EX_Op2_reg[28] ;
  input \EX_Op2_reg[28]_0 ;
  input \EX_Op2_reg[27] ;
  input \EX_Op2_reg[27]_0 ;
  input \EX_Op2_reg[26] ;
  input \EX_Op2_reg[26]_0 ;
  input \EX_Op2_reg[25] ;
  input \EX_Op2_reg[25]_0 ;
  input \EX_Op2_reg[24] ;
  input \EX_Op2_reg[24]_0 ;
  input \EX_Op2_reg[23] ;
  input [7:0]\EX_Op2_reg[16] ;
  input \EX_Op2_reg[22] ;
  input \EX_Op2_reg[21] ;
  input \EX_Op2_reg[20] ;
  input \EX_Op2_reg[19] ;
  input \EX_Op2_reg[18] ;
  input \EX_Op2_reg[17] ;
  input \EX_Op2_reg[16]_0 ;
  input \EX_Op2_reg[15] ;
  input \EX_Op2_reg[15]_0 ;
  input [15:0]\EX_Op2_reg[0] ;
  input \EX_Op2_reg[0]_0 ;
  input \EX_Op2_reg[14] ;
  input \EX_Op2_reg[14]_0 ;
  input \EX_Op2_reg[13] ;
  input \EX_Op2_reg[13]_0 ;
  input \EX_Op2_reg[12] ;
  input \EX_Op2_reg[12]_0 ;
  input \EX_Op2_reg[11] ;
  input \EX_Op2_reg[11]_0 ;
  input \EX_Op2_reg[10] ;
  input \EX_Op2_reg[10]_0 ;
  input \EX_Op2_reg[9] ;
  input \EX_Op2_reg[9]_0 ;
  input \EX_Op2_reg[8] ;
  input \EX_Op2_reg[8]_0 ;
  input \EX_Op2_reg[7] ;
  input \EX_Op2_reg[7]_0 ;
  input \EX_Op2_reg[6] ;
  input \EX_Op2_reg[6]_0 ;
  input \EX_Op2_reg[5] ;
  input \EX_Op2_reg[5]_0 ;
  input \EX_Op2_reg[4] ;
  input \EX_Op2_reg[4]_0 ;
  input \EX_Op2_reg[3] ;
  input \EX_Op2_reg[3]_0 ;
  input \EX_Op2_reg[2] ;
  input \EX_Op2_reg[2]_0 ;
  input \EX_Op2_reg[1] ;
  input \EX_Op2_reg[1]_0 ;
  input \EX_Op2_reg[0]_1 ;
  input \EX_Op2_reg[0]_2 ;
  input [0:31]GPR_Op3;
  input [4:0]\Using_FPGA.Native_i_5__0 ;
  input mem_valid_instr;
  input mem_gpr_write;
  input p_213_in;
  input [0:31]GPR_Op1;
  input \EX_Op3[0]_i_2 ;
  input [4:0]\Using_FPGA.Native_i_5__0_0 ;
  input p_216_in;
  input [1:0]\Using_FPGA.Native_i_5__0_1 ;
  input ex_mbar_is_sleep;
  input ex_mbar_decode;
  input [0:0]\Performance_Debug_Control.ex_brki_hit_reg ;
  input \EX_Op3[0]_i_6 ;
  input I4;
  input I0;
  input if_missed_fetch;
  input ex_gpr_write_dbg__0;
  input ex_jump_nodelay;
  input IReady;
  input \Using_FPGA.Native_61 ;
  input \Using_FPGA.Native_62 ;
  input ex_branch_with_delayslot;
  input ex_jump_q;
  input [31:0]\EX_Op1_reg[0] ;
  input [2:0]ex_MSR;

  wire Clk;
  wire [1:0]D;
  wire D224_out;
  wire Dbg_Clean_Stop0;
  wire [0:0]E;
  wire EX_ALU_Op1142_out__0;
  wire EX_Is_Div_Instr;
  wire [31:0]\EX_Op1_reg[0] ;
  wire [15:0]\EX_Op2_reg[0] ;
  wire \EX_Op2_reg[0]_0 ;
  wire \EX_Op2_reg[0]_1 ;
  wire \EX_Op2_reg[0]_2 ;
  wire \EX_Op2_reg[10] ;
  wire \EX_Op2_reg[10]_0 ;
  wire \EX_Op2_reg[11] ;
  wire \EX_Op2_reg[11]_0 ;
  wire \EX_Op2_reg[12] ;
  wire \EX_Op2_reg[12]_0 ;
  wire \EX_Op2_reg[13] ;
  wire \EX_Op2_reg[13]_0 ;
  wire \EX_Op2_reg[14] ;
  wire \EX_Op2_reg[14]_0 ;
  wire \EX_Op2_reg[15] ;
  wire \EX_Op2_reg[15]_0 ;
  wire [7:0]\EX_Op2_reg[16] ;
  wire \EX_Op2_reg[16]_0 ;
  wire \EX_Op2_reg[17] ;
  wire \EX_Op2_reg[18] ;
  wire \EX_Op2_reg[19] ;
  wire \EX_Op2_reg[1] ;
  wire \EX_Op2_reg[1]_0 ;
  wire \EX_Op2_reg[20] ;
  wire \EX_Op2_reg[21] ;
  wire \EX_Op2_reg[22] ;
  wire \EX_Op2_reg[23] ;
  wire \EX_Op2_reg[24] ;
  wire \EX_Op2_reg[24]_0 ;
  wire \EX_Op2_reg[25] ;
  wire \EX_Op2_reg[25]_0 ;
  wire \EX_Op2_reg[26] ;
  wire \EX_Op2_reg[26]_0 ;
  wire \EX_Op2_reg[27] ;
  wire \EX_Op2_reg[27]_0 ;
  wire \EX_Op2_reg[28] ;
  wire \EX_Op2_reg[28]_0 ;
  wire \EX_Op2_reg[29] ;
  wire \EX_Op2_reg[29]_0 ;
  wire \EX_Op2_reg[2] ;
  wire \EX_Op2_reg[2]_0 ;
  wire \EX_Op2_reg[30] ;
  wire \EX_Op2_reg[30]_0 ;
  wire \EX_Op2_reg[31] ;
  wire \EX_Op2_reg[31]_0 ;
  wire \EX_Op2_reg[3] ;
  wire \EX_Op2_reg[3]_0 ;
  wire \EX_Op2_reg[4] ;
  wire \EX_Op2_reg[4]_0 ;
  wire \EX_Op2_reg[5] ;
  wire \EX_Op2_reg[5]_0 ;
  wire \EX_Op2_reg[6] ;
  wire \EX_Op2_reg[6]_0 ;
  wire \EX_Op2_reg[7] ;
  wire \EX_Op2_reg[7]_0 ;
  wire \EX_Op2_reg[8] ;
  wire \EX_Op2_reg[8]_0 ;
  wire \EX_Op2_reg[9] ;
  wire \EX_Op2_reg[9]_0 ;
  wire \EX_Op3[0]_i_2 ;
  wire \EX_Op3[0]_i_6 ;
  wire [0:31]GPR_Op1;
  wire [0:31]GPR_Op2;
  wire [0:31]GPR_Op3;
  wire I0;
  wire I0101_out;
  wire I0105_out;
  wire I0109_out;
  wire I0113_out;
  wire I0117_out;
  wire I0121_out;
  wire I0125_out;
  wire I0129_out;
  wire I0133_out;
  wire I0137_out;
  wire I013_out;
  wire I0141_out;
  wire I0145_out;
  wire I0149_out;
  wire I0153_out;
  wire I0157_out;
  wire I0161_out;
  wire I0165_out;
  wire I0169_out;
  wire I017_out;
  wire I021_out;
  wire I025_out;
  wire I029_out;
  wire I033_out;
  wire I037_out;
  wire I041_out;
  wire I045_out;
  wire I049_out;
  wire I053_out;
  wire I057_out;
  wire I05_out;
  wire I061_out;
  wire I065_out;
  wire I069_out;
  wire I073_out;
  wire I077_out;
  wire I081_out;
  wire I085_out;
  wire I089_out;
  wire I093_out;
  wire I097_out;
  wire I09_out;
  wire I0_1;
  wire I1;
  wire I1103_out;
  wire I1107_out;
  wire I1111_out;
  wire I1115_out;
  wire I1119_out;
  wire I111_out;
  wire I1123_out;
  wire I1127_out;
  wire I1131_out;
  wire I1135_out;
  wire I1139_out;
  wire I1143_out;
  wire I1147_out;
  wire I1151_out;
  wire I1155_out;
  wire I1159_out;
  wire I115_out;
  wire I1163_out;
  wire I1167_out;
  wire I119_out;
  wire I123_out;
  wire I127_out;
  wire I131_out;
  wire I135_out;
  wire I139_out;
  wire I13_out;
  wire I143_out;
  wire I147_out;
  wire I151_out;
  wire I155_out;
  wire I159_out;
  wire I163_out;
  wire I167_out;
  wire I171_out;
  wire I175_out;
  wire I179_out;
  wire I17_out;
  wire I183_out;
  wire I187_out;
  wire I191_out;
  wire I195_out;
  wire I199_out;
  wire I1_0;
  wire I4;
  wire I4_0;
  wire I5;
  wire IB_Ready;
  wire IReady;
  wire IReady_0;
  wire \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_3 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_10 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_11 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_12 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_13 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_14 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_15 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_16 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_17 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_3 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_4 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_5 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_6 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_7 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_8 ;
  wire \Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_9 ;
  wire \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[18].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[19].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[20].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[22].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[23].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[25].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[27].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[28].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[29].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_3 ;
  wire \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4 ;
  wire \Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_5 ;
  wire \Instruction_Prefetch_Mux[30].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[31].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[32].Gen_Instr_DFF_n_33 ;
  wire \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_3 ;
  wire \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_13 ;
  wire \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_1 ;
  wire \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_3 ;
  wire \Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_2 ;
  wire \Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_3 ;
  wire [0:31]MEM_Fwd;
  wire OF_Op1_Sel_SPR_PC0__0;
  wire [0:0]\Performance_Debug_Control.ex_brki_hit_reg ;
  wire [1:0]Q;
  wire \Serial_Dbg_Intf.control_reg_reg[8] ;
  wire [1:0]\Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_10 ;
  wire [0:0]\Using_FPGA.Native_11 ;
  wire \Using_FPGA.Native_12 ;
  wire \Using_FPGA.Native_13 ;
  wire [1:0]\Using_FPGA.Native_14 ;
  wire \Using_FPGA.Native_15 ;
  wire \Using_FPGA.Native_16 ;
  wire \Using_FPGA.Native_17 ;
  wire \Using_FPGA.Native_18 ;
  wire \Using_FPGA.Native_19 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_20 ;
  wire \Using_FPGA.Native_21 ;
  wire \Using_FPGA.Native_22 ;
  wire \Using_FPGA.Native_23 ;
  wire \Using_FPGA.Native_24 ;
  wire \Using_FPGA.Native_25 ;
  wire \Using_FPGA.Native_26 ;
  wire \Using_FPGA.Native_27 ;
  wire \Using_FPGA.Native_28 ;
  wire \Using_FPGA.Native_29 ;
  wire \Using_FPGA.Native_3 ;
  wire \Using_FPGA.Native_30 ;
  wire \Using_FPGA.Native_31 ;
  wire \Using_FPGA.Native_32 ;
  wire \Using_FPGA.Native_33 ;
  wire \Using_FPGA.Native_34 ;
  wire \Using_FPGA.Native_35 ;
  wire \Using_FPGA.Native_36 ;
  wire \Using_FPGA.Native_37 ;
  wire \Using_FPGA.Native_38 ;
  wire \Using_FPGA.Native_39 ;
  wire [20:0]\Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_40 ;
  wire \Using_FPGA.Native_41 ;
  wire \Using_FPGA.Native_42 ;
  wire \Using_FPGA.Native_43 ;
  wire \Using_FPGA.Native_44 ;
  wire \Using_FPGA.Native_45 ;
  wire \Using_FPGA.Native_46 ;
  wire \Using_FPGA.Native_47 ;
  wire \Using_FPGA.Native_48 ;
  wire \Using_FPGA.Native_49 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_50 ;
  wire \Using_FPGA.Native_51 ;
  wire \Using_FPGA.Native_52 ;
  wire \Using_FPGA.Native_53 ;
  wire \Using_FPGA.Native_54 ;
  wire \Using_FPGA.Native_55 ;
  wire \Using_FPGA.Native_56 ;
  wire \Using_FPGA.Native_57 ;
  wire \Using_FPGA.Native_58 ;
  wire [0:0]\Using_FPGA.Native_59 ;
  wire [1:0]\Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_60 ;
  wire \Using_FPGA.Native_61 ;
  wire \Using_FPGA.Native_62 ;
  wire \Using_FPGA.Native_7 ;
  wire \Using_FPGA.Native_8 ;
  wire [1:0]\Using_FPGA.Native_9 ;
  wire [4:0]\Using_FPGA.Native_i_5__0 ;
  wire [4:0]\Using_FPGA.Native_i_5__0_0 ;
  wire [1:0]\Using_FPGA.Native_i_5__0_1 ;
  wire [2:0]ex_MSR;
  wire ex_branch_with_delayslot;
  wire ex_branch_with_delayslot_i;
  wire ex_branch_with_delayslot_i_reg_0;
  wire ex_branch_with_delayslot_reg;
  wire ex_enable_sext_shift_i0;
  wire ex_gpr_write111_out__0;
  wire ex_gpr_write_dbg__0;
  wire ex_gpr_write_reg;
  wire ex_gpr_write_reg_0;
  wire ex_is_div_instr_I_reg;
  wire ex_is_multi_or_load_instr0;
  wire ex_jump;
  wire ex_jump_nodelay;
  wire ex_jump_q;
  wire ex_load_shift_carry0;
  wire ex_mbar_decode;
  wire ex_mbar_decode_cmb;
  wire ex_mbar_is_sleep;
  wire ex_mbar_is_sleep_cmb;
  wire ex_move_to_MSR_instr93_out;
  wire ex_op1_cmp_eq1;
  wire ex_op1_cmp_eq_n5_out;
  wire ex_sel_alu_i0;
  wire [31:0]ex_sel_alu_i_reg;
  wire [31:0]ex_sel_alu_i_reg_0;
  wire [31:0]ex_sel_alu_i_reg_1;
  wire ex_set_bip;
  wire ex_set_bip0__1;
  wire force12_out;
  wire force_Val10_out;
  wire \ibuffer_reg[3][42]_srl4_n_0 ;
  wire if_fetch_for_timing_optimization1;
  wire if_fetch_in_progress;
  wire [0:0]if_fetch_in_progress_reg;
  wire if_missed_fetch;
  wire if_missed_fetch_reg;
  wire [0:0]if_pre_buffer_addr;
  wire [1:2]if_sel_input;
  wire [32:0]in;
  wire in0;
  wire mem_gpr_write;
  wire mem_valid_instr;
  wire of_Imm180;
  wire of_Sel_SPR_MSR1;
  wire of_Sel_SPR_MSR88_out;
  wire of_Valid_II;
  wire [5:0]of_instr;
  wire of_instr_ii_0;
  wire of_instr_ii_1;
  wire of_instr_ii_10;
  wire of_instr_ii_11;
  wire of_instr_ii_12;
  wire of_instr_ii_13;
  wire of_instr_ii_14;
  wire of_instr_ii_15;
  wire of_instr_ii_16;
  wire of_instr_ii_17;
  wire of_instr_ii_18;
  wire of_instr_ii_19;
  wire of_instr_ii_2;
  wire of_instr_ii_20;
  wire of_instr_ii_21;
  wire of_instr_ii_22;
  wire of_instr_ii_23;
  wire of_instr_ii_24;
  wire of_instr_ii_25;
  wire of_instr_ii_26;
  wire of_instr_ii_27;
  wire of_instr_ii_28;
  wire of_instr_ii_29;
  wire of_instr_ii_3;
  wire of_instr_ii_30;
  wire of_instr_ii_31;
  wire of_instr_ii_32;
  wire of_instr_ii_33;
  wire of_instr_ii_34;
  wire of_instr_ii_35;
  wire of_instr_ii_36;
  wire of_instr_ii_37;
  wire of_instr_ii_38;
  wire of_instr_ii_39;
  wire of_instr_ii_4;
  wire of_instr_ii_40;
  wire of_instr_ii_41;
  wire of_instr_ii_42;
  wire of_instr_ii_5;
  wire of_instr_ii_6;
  wire of_instr_ii_7;
  wire of_instr_ii_8;
  wire of_instr_ii_9;
  wire of_op1_sel_spr;
  wire of_op2_sel_imm;
  wire [0:10]of_predecode;
  wire of_read_mem_write_op3_conflict__1;
  wire of_use_op2_s;
  wire of_valid;
  wire out;
  wire p_0_in30_in;
  wire p_1_in104_in;
  wire p_1_in109_in;
  wire p_1_in114_in;
  wire p_1_in119_in;
  wire p_1_in124_in;
  wire p_1_in129_in;
  wire p_1_in134_in;
  wire p_1_in139_in;
  wire p_1_in144_in;
  wire p_1_in149_in;
  wire p_1_in14_in;
  wire p_1_in154_in;
  wire p_1_in159_in;
  wire p_1_in164_in;
  wire p_1_in169_in;
  wire p_1_in174_in;
  wire p_1_in179_in;
  wire p_1_in184_in;
  wire p_1_in189_in;
  wire p_1_in194_in;
  wire p_1_in199_in;
  wire p_1_in19_in;
  wire p_1_in204_in;
  wire p_1_in209_in;
  wire p_1_in24_in;
  wire p_1_in26_in;
  wire p_1_in29_in;
  wire p_1_in34_in;
  wire p_1_in39_in;
  wire p_1_in44_in;
  wire p_1_in4_in;
  wire p_1_in54_in;
  wire p_1_in59_in;
  wire p_1_in64_in;
  wire p_1_in69_in;
  wire p_1_in74_in;
  wire p_1_in79_in;
  wire p_1_in84_in;
  wire p_1_in89_in;
  wire p_1_in94_in;
  wire p_1_in99_in;
  wire p_1_in9_in;
  wire p_213_in;
  wire p_216_in;
  wire p_28_in;
  wire p_2_in;
  wire p_9_in;
  wire sel_input_delayslot;
  wire sel_input_i_0;
  wire sel_input_i_1;
  wire sel_input_iii_0;
  wire sel_input_iii_1;
  wire sel_input_iii_2;
  wire sel_input_iii_3;
  wire sync_reset;
  wire use_Reg_Neg_DI1_out;
  wire use_Reg_Neg_S3_out;
  wire wb_exception;
  wire wb_exception_i_reg;

  design_1_microblaze_0_0_MB_FDR_112 \Gen_Mux_Select_LUT6[1].Gen_Sel_DFF 
       (.Clk(Clk),
        .IB_Ready(IB_Ready),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_17 ),
        .addr(\Using_FPGA.Native [1]),
        .ex_jump(ex_jump),
        .if_fetch_in_progress(if_fetch_in_progress),
        .if_sel_input(if_sel_input[1]),
        .out(out),
        .sel_input_iii_3(sel_input_iii_3),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_LUT6 \Gen_Mux_Select_LUT6[1].Mux_Select_LUT6 
       (.I5(I5),
        .\Using_FPGA.Native_0 (IReady_0),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_60 ),
        .addr(\Using_FPGA.Native [1]),
        .if_sel_input(if_sel_input[1]),
        .sel_input_iii_3(sel_input_iii_3));
  design_1_microblaze_0_0_MB_FDR_113 \Gen_Mux_Select_LUT6[2].Gen_Sel_DFF 
       (.Clk(Clk),
        .IB_Ready(IB_Ready),
        .\Serial_Dbg_Intf.status_reg_reg[25] (\Using_FPGA.Native [1]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_6 ),
        .addr(if_pre_buffer_addr),
        .ex_jump(ex_jump),
        .if_fetch_for_timing_optimization1(if_fetch_for_timing_optimization1),
        .if_fetch_in_progress(if_fetch_in_progress),
        .if_fetch_in_progress_reg(if_fetch_in_progress_reg),
        .if_missed_fetch(if_missed_fetch),
        .if_missed_fetch_reg(if_missed_fetch_reg),
        .if_sel_input(if_sel_input[1]),
        .in0(in0),
        .out(out),
        .sel_input_iii_2(sel_input_iii_2),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_LUT6_114 \Gen_Mux_Select_LUT6[2].Mux_Select_LUT6 
       (.I5(I5),
        .\Using_FPGA.Native_0 (IReady_0),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_60 ),
        .addr(\Using_FPGA.Native [1]),
        .if_sel_input({if_sel_input[1],if_sel_input[2]}),
        .sel_input_iii_2(sel_input_iii_2));
  design_1_microblaze_0_0_MB_FDR_115 \Gen_Mux_Select_LUT6[3].Gen_Sel_DFF 
       (.Clk(Clk),
        .if_sel_input(if_sel_input[2]),
        .sel_input_iii_1(sel_input_iii_1),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_LUT6_116 \Gen_Mux_Select_LUT6[3].Mux_Select_LUT6 
       (.I5(I5),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_1 (IReady_0),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_60 ),
        .if_sel_input({if_sel_input[1],if_sel_input[2]}),
        .sel_input_iii_1(sel_input_iii_1));
  design_1_microblaze_0_0_MB_FDR_117 \Gen_Mux_Select_LUT6[4].Gen_Sel_DFF 
       (.Clk(Clk),
        .I1(I1),
        .I1103_out(I1103_out),
        .I1107_out(I1107_out),
        .I1111_out(I1111_out),
        .I1115_out(I1115_out),
        .I1119_out(I1119_out),
        .I111_out(I111_out),
        .I1123_out(I1123_out),
        .I1127_out(I1127_out),
        .I1131_out(I1131_out),
        .I1135_out(I1135_out),
        .I1139_out(I1139_out),
        .I1143_out(I1143_out),
        .I1147_out(I1147_out),
        .I1151_out(I1151_out),
        .I1155_out(I1155_out),
        .I1159_out(I1159_out),
        .I115_out(I115_out),
        .I1163_out(I1163_out),
        .I1167_out(I1167_out),
        .I119_out(I119_out),
        .I123_out(I123_out),
        .I127_out(I127_out),
        .I131_out(I131_out),
        .I135_out(I135_out),
        .I13_out(I13_out),
        .I143_out(I143_out),
        .I147_out(I147_out),
        .I151_out(I151_out),
        .I155_out(I155_out),
        .I159_out(I159_out),
        .I163_out(I163_out),
        .I167_out(I167_out),
        .I171_out(I171_out),
        .I175_out(I175_out),
        .I179_out(I179_out),
        .I17_out(I17_out),
        .I183_out(I183_out),
        .I187_out(I187_out),
        .I191_out(I191_out),
        .I195_out(I195_out),
        .I199_out(I199_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .in({in[32:11],in[9:0]}),
        .out({p_1_in209_in,p_1_in204_in,p_1_in199_in,p_1_in194_in,p_1_in189_in,p_1_in184_in,p_1_in179_in,p_1_in174_in,p_1_in169_in,p_1_in164_in,p_1_in159_in,p_1_in154_in,p_1_in149_in,p_1_in144_in,p_1_in139_in,p_1_in134_in,p_1_in129_in,p_1_in124_in,p_1_in119_in,p_1_in114_in,p_1_in109_in,p_1_in104_in,p_1_in99_in,p_1_in94_in,p_1_in89_in,p_1_in84_in,p_1_in79_in,p_1_in74_in,p_1_in69_in,p_1_in64_in,p_1_in59_in,p_1_in54_in,p_1_in44_in,p_1_in39_in,p_1_in34_in,p_1_in29_in,p_1_in24_in,p_1_in19_in,p_1_in14_in,p_1_in9_in,p_1_in4_in,\ibuffer_reg[3][42]_srl4_n_0 }),
        .sel_input_i_1(sel_input_i_1),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_LUT6_118 \Gen_Mux_Select_LUT6[4].Mux_Select_LUT6 
       (.I5(I5),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [0]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_2 (IReady_0),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_60 ),
        .if_sel_input(if_sel_input[2]),
        .sel_input_iii_0(sel_input_iii_0));
  design_1_microblaze_0_0_MB_LUT6__parameterized2 \Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Mux_Select_Delayslot_LUT6 
       (.I5(I5),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [0]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_2 (IReady_0),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_60 ),
        .if_sel_input(if_sel_input[2]),
        .sel_input_delayslot(sel_input_delayslot));
  design_1_microblaze_0_0_MB_MUXF7 \Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Sel_Mux_MUXF7 
       (.I4_0(I4_0),
        .Q(Q),
        .ex_branch_with_delayslot_i(ex_branch_with_delayslot_i),
        .sel_input_delayslot(sel_input_delayslot),
        .sel_input_i_1(sel_input_i_1),
        .sel_input_iii_0(sel_input_iii_0),
        .wb_exception(wb_exception));
  design_1_microblaze_0_0_MB_FDR_119 \Instruction_Prefetch_Mux[0].Gen_Instr_DFF 
       (.Clk(Clk),
        .EX_ALU_Op1142_out__0(EX_ALU_Op1142_out__0),
        .EX_CMP_Op_reg(\Using_FPGA.Native_4 [0]),
        .EX_Unsigned_Op_reg(of_instr[3]),
        .EX_Unsigned_Op_reg_0(\Using_FPGA.Native_4 [1]),
        .EX_Use_Carry_reg(of_instr[1]),
        .OF_Op1_Sel_SPR_PC0__0(OF_Op1_Sel_SPR_PC0__0),
        .\Using_FPGA.Native_0 (of_instr[5]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_18 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_19 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_20 ),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_21 ),
        .\Using_FPGA.Native_5 (\Using_FPGA.Native_25 ),
        .\Using_FPGA.Native_6 (of_instr[2]),
        .\Using_FPGA.Native_7 (of_instr[4]),
        .ex_jump(ex_jump),
        .ex_jump_nodelay(ex_jump_nodelay),
        .of_instr_ii_42(of_instr_ii_42),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_120 \Instruction_Prefetch_Mux[0].Instr_Mux_MUXF7 
       (.I0169_out(I0169_out),
        .I1167_out(I1167_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_42(of_instr_ii_42));
  design_1_microblaze_0_0_MB_FDR_121 \Instruction_Prefetch_Mux[10].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Op3[0]_i_4 (\Using_FPGA.Native_i_5__0 [2:0]),
        .\EX_Op3[0]_i_5 (\Using_FPGA.Native_i_5__0_0 [2:0]),
        .\EX_Op3[0]_i_6 (\Using_FPGA.Native_1 ),
        .\EX_Op3[0]_i_6_0 (\Using_FPGA.Native_2 ),
        .\EX_Op3[0]_i_6_1 (\EX_Op3[0]_i_6 ),
        .I0(I0),
        .I4(I4),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_3 ),
        .\ex_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_3 ),
        .\mem_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_32(of_instr_ii_32),
        .sync_reset(sync_reset),
        .\wb_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_2 ));
  design_1_microblaze_0_0_MB_MUXF7_122 \Instruction_Prefetch_Mux[10].Instr_Mux_MUXF7 
       (.I0129_out(I0129_out),
        .I1127_out(I1127_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_32(of_instr_ii_32));
  design_1_microblaze_0_0_MB_FDR_123 \Instruction_Prefetch_Mux[11].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [20]),
        .ex_set_bip0__1(ex_set_bip0__1),
        .ex_set_bip_reg(\Using_FPGA.Native_4 [18]),
        .ex_set_bip_reg_0(\Using_FPGA.Native_4 [19]),
        .of_instr_ii_31(of_instr_ii_31),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_124 \Instruction_Prefetch_Mux[11].Instr_Mux_MUXF7 
       (.I0125_out(I0125_out),
        .I1123_out(I1123_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_31(of_instr_ii_31));
  design_1_microblaze_0_0_MB_FDR_125 \Instruction_Prefetch_Mux[12].Gen_Instr_DFF 
       (.Clk(Clk),
        .EX_ALU_Op1142_out__0(EX_ALU_Op1142_out__0),
        .\EX_ALU_Op_reg[1] (of_instr[0]),
        .\EX_ALU_Op_reg[1]_0 (\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4 ),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [19]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_9 [0]),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_10 ),
        .ex_enable_alu_i_reg(of_instr[5]),
        .ex_enable_alu_i_reg_0(of_instr[2]),
        .ex_enable_alu_i_reg_1(of_instr[4]),
        .ex_enable_alu_i_reg_2(of_instr[3]),
        .ex_enable_alu_i_reg_3(\Using_FPGA.Native_4 [10]),
        .of_instr_ii_30(of_instr_ii_30),
        .p_28_in(p_28_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_126 \Instruction_Prefetch_Mux[12].Instr_Mux_MUXF7 
       (.I0121_out(I0121_out),
        .I1119_out(I1119_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_30(of_instr_ii_30));
  design_1_microblaze_0_0_MB_FDR_127 \Instruction_Prefetch_Mux[13].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [18]),
        .of_instr_ii_29(of_instr_ii_29),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_128 \Instruction_Prefetch_Mux[13].Instr_Mux_MUXF7 
       (.I0117_out(I0117_out),
        .I1115_out(I1115_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_29(of_instr_ii_29));
  design_1_microblaze_0_0_MB_FDR_129 \Instruction_Prefetch_Mux[14].Gen_Instr_DFF 
       (.Clk(Clk),
        .E(E),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [17]),
        .\Using_FPGA.Native_1 (ex_mbar_decode_cmb),
        .ex_mbar_decode(ex_mbar_decode),
        .ex_mbar_decode_reg(\Using_FPGA.Native_60 ),
        .of_instr_ii_28(of_instr_ii_28),
        .p_1_in26_in(p_1_in26_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_130 \Instruction_Prefetch_Mux[14].Instr_Mux_MUXF7 
       (.I0113_out(I0113_out),
        .I1111_out(I1111_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_28(of_instr_ii_28));
  design_1_microblaze_0_0_MB_FDR_131 \Instruction_Prefetch_Mux[15].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [16]),
        .of_instr_ii_27(of_instr_ii_27),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_132 \Instruction_Prefetch_Mux[15].Instr_Mux_MUXF7 
       (.I0109_out(I0109_out),
        .I1107_out(I1107_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_27(of_instr_ii_27));
  design_1_microblaze_0_0_MB_FDR_133 \Instruction_Prefetch_Mux[16].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Op2_reg[0] (\EX_Op2_reg[0] ),
        .\EX_Op2_reg[0]_0 (\EX_Op2_reg[0]_0 ),
        .GPR_Op2({GPR_Op2[0],GPR_Op2[1],GPR_Op2[2],GPR_Op2[3],GPR_Op2[4],GPR_Op2[5],GPR_Op2[6],GPR_Op2[7],GPR_Op2[8],GPR_Op2[9],GPR_Op2[10],GPR_Op2[11],GPR_Op2[12],GPR_Op2[13],GPR_Op2[14],GPR_Op2[15],GPR_Op2[16]}),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [15]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_1 ),
        .\imm_reg_reg[0] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_17 ),
        .\imm_reg_reg[10] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_7 ),
        .\imm_reg_reg[11] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_6 ),
        .\imm_reg_reg[12] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_5 ),
        .\imm_reg_reg[13] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_4 ),
        .\imm_reg_reg[14] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_3 ),
        .\imm_reg_reg[15] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_2 ),
        .\imm_reg_reg[1] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_16 ),
        .\imm_reg_reg[2] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_15 ),
        .\imm_reg_reg[3] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_14 ),
        .\imm_reg_reg[4] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_13 ),
        .\imm_reg_reg[5] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_12 ),
        .\imm_reg_reg[6] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_11 ),
        .\imm_reg_reg[7] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_10 ),
        .\imm_reg_reg[8] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_9 ),
        .\imm_reg_reg[9] (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_8 ),
        .of_instr_ii_26(of_instr_ii_26),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_134 \Instruction_Prefetch_Mux[16].Instr_Mux_MUXF7 
       (.I0105_out(I0105_out),
        .I1103_out(I1103_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_26(of_instr_ii_26));
  design_1_microblaze_0_0_MB_FDR_135 \Instruction_Prefetch_Mux[17].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[17]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 (\Using_FPGA.Native_4 [13]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 (\Using_FPGA.Native_4 [15]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [14]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_2 (\Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_2 ),
        .of_instr_ii_25(of_instr_ii_25),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_136 \Instruction_Prefetch_Mux[17].Instr_Mux_MUXF7 
       (.I0101_out(I0101_out),
        .I199_out(I199_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_25(of_instr_ii_25));
  design_1_microblaze_0_0_MB_FDR_137 \Instruction_Prefetch_Mux[18].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[18]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [13]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[18].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_24(of_instr_ii_24),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_138 \Instruction_Prefetch_Mux[18].Instr_Mux_MUXF7 
       (.I097_out(I097_out),
        .I195_out(I195_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_24(of_instr_ii_24));
  design_1_microblaze_0_0_MB_FDR_139 \Instruction_Prefetch_Mux[19].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[19]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [12]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[19].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_23(of_instr_ii_23),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_140 \Instruction_Prefetch_Mux[19].Instr_Mux_MUXF7 
       (.I093_out(I093_out),
        .I191_out(I191_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_23(of_instr_ii_23));
  design_1_microblaze_0_0_MB_FDR_141 \Instruction_Prefetch_Mux[1].Gen_Instr_DFF 
       (.Clk(Clk),
        .E(E),
        .EX_ALU_Op1142_out__0(EX_ALU_Op1142_out__0),
        .\EX_ALU_Op_reg[0] (\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4 ),
        .\EX_Op2[0]_i_2 (of_instr[3]),
        .\Using_FPGA.Native_0 (of_instr[4]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_9 [1]),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_27 ),
        .ex_gpr_write111_out__0(ex_gpr_write111_out__0),
        .ex_gpr_write_dbg__0(ex_gpr_write_dbg__0),
        .ex_gpr_write_dbg_reg(\Using_FPGA.Native_4 [3]),
        .ex_gpr_write_dbg_reg_0(\Using_FPGA.Native_4 [2]),
        .ex_gpr_write_i_2_0(\Using_FPGA.Native_4 [18]),
        .ex_gpr_write_i_2_1(\Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2 ),
        .ex_gpr_write_i_2_2(\Using_FPGA.Native_4 [14]),
        .ex_gpr_write_i_2_3(\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_1 ),
        .ex_gpr_write_reg(ex_gpr_write_reg),
        .ex_gpr_write_reg_0(ex_gpr_write_reg_0),
        .ex_gpr_write_reg_1(\Using_FPGA.Native_60 ),
        .ex_set_bip(ex_set_bip),
        .ex_set_bip0__1(ex_set_bip0__1),
        .ex_set_bip_reg(of_instr[5]),
        .ex_set_bip_reg_0(of_instr[1]),
        .ex_set_bip_reg_1(of_instr[2]),
        .ex_set_bip_reg_2(of_instr[0]),
        .of_instr_ii_41(of_instr_ii_41),
        .of_op2_sel_imm(of_op2_sel_imm),
        .of_use_op2_s(of_use_op2_s),
        .p_0_in30_in(p_0_in30_in),
        .p_28_in(p_28_in),
        .sync_reset(sync_reset),
        .wb_exception(wb_exception),
        .wb_exception_i_reg(wb_exception_i_reg));
  design_1_microblaze_0_0_MB_MUXF7_142 \Instruction_Prefetch_Mux[1].Instr_Mux_MUXF7 
       (.I0165_out(I0165_out),
        .I1163_out(I1163_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_41(of_instr_ii_41));
  design_1_microblaze_0_0_MB_FDR_143 \Instruction_Prefetch_Mux[20].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[20]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 (\Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 (\Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_2 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 (\Using_FPGA.Native_4 [12]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 (\Using_FPGA.Native_4 [9]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 (\Using_FPGA.Native_4 [10]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [11]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[20].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_24 ),
        .ex_set_bip0__1(ex_set_bip0__1),
        .of_Imm180(of_Imm180),
        .of_instr_ii_22(of_instr_ii_22),
        .of_op2_sel_imm(of_op2_sel_imm),
        .p_1_in26_in(p_1_in26_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_144 \Instruction_Prefetch_Mux[20].Instr_Mux_MUXF7 
       (.I089_out(I089_out),
        .I187_out(I187_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_22(of_instr_ii_22));
  design_1_microblaze_0_0_MB_FDR_145 \Instruction_Prefetch_Mux[21].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[21]),
        .\Performance_Debug_Control.ex_brki_hit_reg (\Using_FPGA.Native_4 [9]),
        .\Performance_Debug_Control.ex_brki_hit_reg_0 (\Using_FPGA.Native_4 [12]),
        .\Performance_Debug_Control.ex_brki_hit_reg_1 (\Using_FPGA.Native_4 [11]),
        .\Performance_Debug_Control.ex_brki_hit_reg_2 (\Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2 ),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [10]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_2 (\Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_2 ),
        .of_instr_ii_21(of_instr_ii_21),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_146 \Instruction_Prefetch_Mux[21].Instr_Mux_MUXF7 
       (.I085_out(I085_out),
        .I183_out(I183_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_21(of_instr_ii_21));
  design_1_microblaze_0_0_MB_FDR_147 \Instruction_Prefetch_Mux[22].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[22]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [9]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[22].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_26 ),
        .\Using_FPGA.Native_3 (of_instr[3]),
        .of_instr_ii_20(of_instr_ii_20),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_148 \Instruction_Prefetch_Mux[22].Instr_Mux_MUXF7 
       (.I081_out(I081_out),
        .I179_out(I179_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_20(of_instr_ii_20));
  design_1_microblaze_0_0_MB_FDR_149 \Instruction_Prefetch_Mux[23].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[23]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [8]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[23].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_19(of_instr_ii_19),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_150 \Instruction_Prefetch_Mux[23].Instr_Mux_MUXF7 
       (.I077_out(I077_out),
        .I175_out(I175_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_19(of_instr_ii_19));
  design_1_microblaze_0_0_MB_FDR_151 \Instruction_Prefetch_Mux[24].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[24]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 (\Using_FPGA.Native_4 [8]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 (\Using_FPGA.Native_4 [5]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 (\Using_FPGA.Native_4 [6]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [7]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_2 (\Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_2 ),
        .of_instr_ii_18(of_instr_ii_18),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_152 \Instruction_Prefetch_Mux[24].Instr_Mux_MUXF7 
       (.I073_out(I073_out),
        .I171_out(I171_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_18(of_instr_ii_18));
  design_1_microblaze_0_0_MB_FDR_153 \Instruction_Prefetch_Mux[25].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[25]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [6]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[25].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_17(of_instr_ii_17),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_154 \Instruction_Prefetch_Mux[25].Instr_Mux_MUXF7 
       (.I069_out(I069_out),
        .I167_out(I167_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_17(of_instr_ii_17));
  design_1_microblaze_0_0_MB_FDR_155 \Instruction_Prefetch_Mux[26].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Sext_Op_reg[0] (\Using_FPGA.Native_4 [6]),
        .GPR_Op2(GPR_Op2[26]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [5]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_2 (\Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_2 ),
        .of_instr_ii_16(of_instr_ii_16),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_156 \Instruction_Prefetch_Mux[26].Instr_Mux_MUXF7 
       (.I065_out(I065_out),
        .I163_out(I163_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_16(of_instr_ii_16));
  design_1_microblaze_0_0_MB_FDR_157 \Instruction_Prefetch_Mux[27].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[27]),
        .\Performance_Debug_Control.ex_brki_hit_reg (\Performance_Debug_Control.ex_brki_hit_reg ),
        .\Performance_Debug_Control.ex_brki_hit_reg_0 (\Using_FPGA.Native_4 [15]),
        .\Performance_Debug_Control.ex_brki_hit_reg_1 (\Using_FPGA.Native_4 [13]),
        .\Performance_Debug_Control.ex_brki_hit_reg_2 (\Using_FPGA.Native_4 [14]),
        .\Performance_Debug_Control.ex_brki_hit_reg_3 (\Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_2 ),
        .\Performance_Debug_Control.ex_brki_hit_reg_4 (\Using_FPGA.Native_4 [20]),
        .\Performance_Debug_Control.ex_brki_hit_reg_5 (\Using_FPGA.Native_4 [18]),
        .\Performance_Debug_Control.ex_brki_hit_reg_6 (\Using_FPGA.Native_4 [19]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3 (\Using_FPGA.Native_4 [2]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_0 (\Using_FPGA.Native_4 [3]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_1 (\Using_FPGA.Native_4 [1]),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_3_2 (\Using_FPGA.Native_4 [0]),
        .\Serial_Dbg_Intf.control_reg_reg[8] (\Serial_Dbg_Intf.control_reg_reg[8] ),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [4]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[27].Gen_Instr_DFF_n_1 ),
        .of_Imm180(of_Imm180),
        .of_instr_ii_15(of_instr_ii_15),
        .of_op2_sel_imm(of_op2_sel_imm),
        .p_1_in26_in(p_1_in26_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_158 \Instruction_Prefetch_Mux[27].Instr_Mux_MUXF7 
       (.I061_out(I061_out),
        .I159_out(I159_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_15(of_instr_ii_15));
  design_1_microblaze_0_0_MB_FDR_159 \Instruction_Prefetch_Mux[28].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[28]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [3]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[28].Gen_Instr_DFF_n_2 ),
        .ex_move_to_MSR_instr93_out(ex_move_to_MSR_instr93_out),
        .ex_move_to_MSR_instr_reg(\Using_FPGA.Native_4 [1]),
        .ex_move_to_MSR_instr_reg_0(\Using_FPGA.Native_4 [2]),
        .ex_move_to_MSR_instr_reg_1(\Using_FPGA.Native_4 [0]),
        .ex_move_to_MSR_instr_reg_2(\Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2 ),
        .ex_move_to_MSR_instr_reg_3(\Using_FPGA.Native_4 [14]),
        .of_instr_ii_14(of_instr_ii_14),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_160 \Instruction_Prefetch_Mux[28].Instr_Mux_MUXF7 
       (.I057_out(I057_out),
        .I155_out(I155_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_14(of_instr_ii_14));
  design_1_microblaze_0_0_MB_FDR_161 \Instruction_Prefetch_Mux[29].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[29]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [2]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[29].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_13(of_instr_ii_13),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_162 \Instruction_Prefetch_Mux[29].Instr_Mux_MUXF7 
       (.I053_out(I053_out),
        .I151_out(I151_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_13(of_instr_ii_13));
  design_1_microblaze_0_0_MB_FDR_163 \Instruction_Prefetch_Mux[2].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_ALU_Op_reg[0] (\Using_FPGA.Native_4 [10]),
        .\Using_FPGA.Native_0 (of_instr[3]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_2 (\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_3 ),
        .\Using_FPGA.Native_3 (\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_4 ),
        .\Using_FPGA.Native_4 (\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_5 ),
        .\Using_FPGA.Native_5 (of_instr[0]),
        .\Using_FPGA.Native_6 (of_instr[5]),
        .ex_mbar_decode_reg(of_instr[2]),
        .ex_mbar_decode_reg_0(of_instr[1]),
        .ex_mbar_decode_reg_1(of_instr[4]),
        .of_instr_ii_40(of_instr_ii_40),
        .p_1_in26_in(p_1_in26_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_164 \Instruction_Prefetch_Mux[2].Instr_Mux_MUXF7 
       (.I0161_out(I0161_out),
        .I1159_out(I1159_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_40(of_instr_ii_40));
  design_1_microblaze_0_0_MB_FDR_165 \Instruction_Prefetch_Mux[30].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[30]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [1]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[30].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_12(of_instr_ii_12),
        .of_op2_sel_imm(of_op2_sel_imm),
        .p_2_in(p_2_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_166 \Instruction_Prefetch_Mux[30].Instr_Mux_MUXF7 
       (.I049_out(I049_out),
        .I147_out(I147_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_12(of_instr_ii_12));
  design_1_microblaze_0_0_MB_FDR_167 \Instruction_Prefetch_Mux[31].Gen_Instr_DFF 
       (.Clk(Clk),
        .GPR_Op2(GPR_Op2[31]),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 [0]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[31].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_11(of_instr_ii_11),
        .of_op2_sel_imm(of_op2_sel_imm),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_168 \Instruction_Prefetch_Mux[31].Instr_Mux_MUXF7 
       (.I045_out(I045_out),
        .I143_out(I143_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_11(of_instr_ii_11));
  design_1_microblaze_0_0_MB_FDR_169 \Instruction_Prefetch_Mux[32].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Op3[0]_i_2_0 (\Using_FPGA.Native_i_5__0_1 [0]),
        .\EX_Op3[0]_i_2_1 (D[0]),
        .\EX_Op3[0]_i_2_2 (\Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_3 ),
        .\EX_Op3[0]_i_2_3 (\Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_3 ),
        .\EX_Op3[0]_i_2_4 (\EX_Op3[0]_i_2 ),
        .\EX_Op3[0]_i_2_5 (\Using_FPGA.Native_i_5__0_0 [3]),
        .\EX_Op3[0]_i_2_6 (\Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_2 ),
        .\EX_Op3[0]_i_2_7 (\Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_2 ),
        .\EX_Op3_reg[0] (\EX_Op2_reg[0]_1 ),
        .\EX_Op3_reg[0]_0 (\EX_Op2_reg[0]_2 ),
        .\EX_Op3_reg[10] (\EX_Op2_reg[10] ),
        .\EX_Op3_reg[10]_0 (\EX_Op2_reg[10]_0 ),
        .\EX_Op3_reg[11] (\EX_Op2_reg[11] ),
        .\EX_Op3_reg[11]_0 (\EX_Op2_reg[11]_0 ),
        .\EX_Op3_reg[12] (\EX_Op2_reg[12] ),
        .\EX_Op3_reg[12]_0 (\EX_Op2_reg[12]_0 ),
        .\EX_Op3_reg[13] (\EX_Op2_reg[13] ),
        .\EX_Op3_reg[13]_0 (\EX_Op2_reg[13]_0 ),
        .\EX_Op3_reg[14] (\EX_Op2_reg[14] ),
        .\EX_Op3_reg[14]_0 (\EX_Op2_reg[14]_0 ),
        .\EX_Op3_reg[15] (\EX_Op2_reg[15] ),
        .\EX_Op3_reg[15]_0 (\EX_Op2_reg[15]_0 ),
        .\EX_Op3_reg[16] (\EX_Op2_reg[16]_0 ),
        .\EX_Op3_reg[16]_0 (\EX_Op2_reg[16] ),
        .\EX_Op3_reg[17] (\EX_Op2_reg[17] ),
        .\EX_Op3_reg[18] (\EX_Op2_reg[18] ),
        .\EX_Op3_reg[19] (\EX_Op2_reg[19] ),
        .\EX_Op3_reg[1] (\EX_Op2_reg[1] ),
        .\EX_Op3_reg[1]_0 (\EX_Op2_reg[1]_0 ),
        .\EX_Op3_reg[20] (\EX_Op2_reg[20] ),
        .\EX_Op3_reg[21] (\EX_Op2_reg[21] ),
        .\EX_Op3_reg[22] (\EX_Op2_reg[22] ),
        .\EX_Op3_reg[23] (\EX_Op2_reg[23] ),
        .\EX_Op3_reg[24] (\EX_Op2_reg[24] ),
        .\EX_Op3_reg[24]_0 (\EX_Op2_reg[24]_0 ),
        .\EX_Op3_reg[25] (\EX_Op2_reg[25] ),
        .\EX_Op3_reg[25]_0 (\EX_Op2_reg[25]_0 ),
        .\EX_Op3_reg[26] (\EX_Op2_reg[26] ),
        .\EX_Op3_reg[26]_0 (\EX_Op2_reg[26]_0 ),
        .\EX_Op3_reg[27] (\EX_Op2_reg[27] ),
        .\EX_Op3_reg[27]_0 (\EX_Op2_reg[27]_0 ),
        .\EX_Op3_reg[28] (\EX_Op2_reg[28] ),
        .\EX_Op3_reg[28]_0 (\EX_Op2_reg[28]_0 ),
        .\EX_Op3_reg[29] (\EX_Op2_reg[29] ),
        .\EX_Op3_reg[29]_0 (\EX_Op2_reg[29]_0 ),
        .\EX_Op3_reg[2] (\EX_Op2_reg[2] ),
        .\EX_Op3_reg[2]_0 (\EX_Op2_reg[2]_0 ),
        .\EX_Op3_reg[30] (\EX_Op2_reg[30] ),
        .\EX_Op3_reg[30]_0 (\EX_Op2_reg[30]_0 ),
        .\EX_Op3_reg[31] (\EX_Op2_reg[31] ),
        .\EX_Op3_reg[31]_0 (\EX_Op2_reg[31]_0 ),
        .\EX_Op3_reg[3] (\EX_Op2_reg[3] ),
        .\EX_Op3_reg[3]_0 (\EX_Op2_reg[3]_0 ),
        .\EX_Op3_reg[4] (\EX_Op2_reg[4] ),
        .\EX_Op3_reg[4]_0 (\EX_Op2_reg[4]_0 ),
        .\EX_Op3_reg[5] (\EX_Op2_reg[5] ),
        .\EX_Op3_reg[5]_0 (\EX_Op2_reg[5]_0 ),
        .\EX_Op3_reg[6] (\EX_Op2_reg[6] ),
        .\EX_Op3_reg[6]_0 (\EX_Op2_reg[6]_0 ),
        .\EX_Op3_reg[7] (\EX_Op2_reg[7] ),
        .\EX_Op3_reg[7]_0 (\EX_Op2_reg[7]_0 ),
        .\EX_Op3_reg[8] (\EX_Op2_reg[8] ),
        .\EX_Op3_reg[8]_0 (\EX_Op2_reg[8]_0 ),
        .\EX_Op3_reg[9] (\EX_Op2_reg[9] ),
        .\EX_Op3_reg[9]_0 (\EX_Op2_reg[9]_0 ),
        .GPR_Op3(GPR_Op3),
        .MEM_Fwd(MEM_Fwd),
        .\Using_FPGA.Native_0 (of_predecode[0]),
        .ex_sel_alu_i_reg(ex_sel_alu_i_reg_0),
        .mem_gpr_write(mem_gpr_write),
        .mem_valid_instr(mem_valid_instr),
        .mem_valid_reg(\Instruction_Prefetch_Mux[32].Gen_Instr_DFF_n_33 ),
        .of_instr_ii_10(of_instr_ii_10),
        .of_read_mem_write_op3_conflict__1(of_read_mem_write_op3_conflict__1),
        .p_216_in(p_216_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_170 \Instruction_Prefetch_Mux[32].Instr_Mux_MUXF7 
       (.I041_out(I041_out),
        .I139_out(I139_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_10(of_instr_ii_10));
  design_1_microblaze_0_0_MB_FDR_171 \Instruction_Prefetch_Mux[33].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[0] (\EX_Op2_reg[0]_1 ),
        .\EX_Branch_CMP_Op1_reg[0]_0 (\EX_Op2_reg[0]_2 ),
        .\EX_Branch_CMP_Op1_reg[10] (\EX_Op2_reg[10] ),
        .\EX_Branch_CMP_Op1_reg[10]_0 (\EX_Op2_reg[10]_0 ),
        .\EX_Branch_CMP_Op1_reg[11] (\EX_Op2_reg[11] ),
        .\EX_Branch_CMP_Op1_reg[11]_0 (\EX_Op2_reg[11]_0 ),
        .\EX_Branch_CMP_Op1_reg[12] (\EX_Op2_reg[12] ),
        .\EX_Branch_CMP_Op1_reg[12]_0 (\EX_Op2_reg[12]_0 ),
        .\EX_Branch_CMP_Op1_reg[13] (\EX_Op2_reg[13] ),
        .\EX_Branch_CMP_Op1_reg[13]_0 (\EX_Op2_reg[13]_0 ),
        .\EX_Branch_CMP_Op1_reg[14] (\EX_Op2_reg[14] ),
        .\EX_Branch_CMP_Op1_reg[14]_0 (\EX_Op2_reg[14]_0 ),
        .\EX_Branch_CMP_Op1_reg[15] (\EX_Op2_reg[15] ),
        .\EX_Branch_CMP_Op1_reg[15]_0 (\EX_Op2_reg[15]_0 ),
        .\EX_Branch_CMP_Op1_reg[16] (\EX_Op2_reg[16]_0 ),
        .\EX_Branch_CMP_Op1_reg[16]_0 (\EX_Op2_reg[16] ),
        .\EX_Branch_CMP_Op1_reg[17] (\EX_Op2_reg[17] ),
        .\EX_Branch_CMP_Op1_reg[18] (\EX_Op2_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[19] (\EX_Op2_reg[19] ),
        .\EX_Branch_CMP_Op1_reg[1] (\EX_Op2_reg[1] ),
        .\EX_Branch_CMP_Op1_reg[1]_0 (\EX_Op2_reg[1]_0 ),
        .\EX_Branch_CMP_Op1_reg[20] (\EX_Op2_reg[20] ),
        .\EX_Branch_CMP_Op1_reg[21] (\EX_Op2_reg[21] ),
        .\EX_Branch_CMP_Op1_reg[22] (\EX_Op2_reg[22] ),
        .\EX_Branch_CMP_Op1_reg[23] (\EX_Op2_reg[23] ),
        .\EX_Branch_CMP_Op1_reg[24] (\EX_Op2_reg[24] ),
        .\EX_Branch_CMP_Op1_reg[24]_0 (\EX_Op2_reg[24]_0 ),
        .\EX_Branch_CMP_Op1_reg[25] (\EX_Op2_reg[25] ),
        .\EX_Branch_CMP_Op1_reg[25]_0 (\EX_Op2_reg[25]_0 ),
        .\EX_Branch_CMP_Op1_reg[26] (\EX_Op2_reg[26] ),
        .\EX_Branch_CMP_Op1_reg[26]_0 (\EX_Op2_reg[26]_0 ),
        .\EX_Branch_CMP_Op1_reg[27] (\EX_Op2_reg[27] ),
        .\EX_Branch_CMP_Op1_reg[27]_0 (\EX_Op2_reg[27]_0 ),
        .\EX_Branch_CMP_Op1_reg[28] (\EX_Op2_reg[28] ),
        .\EX_Branch_CMP_Op1_reg[28]_0 (\EX_Op2_reg[28]_0 ),
        .\EX_Branch_CMP_Op1_reg[29] (\EX_Op2_reg[29] ),
        .\EX_Branch_CMP_Op1_reg[29]_0 (\EX_Op2_reg[29]_0 ),
        .\EX_Branch_CMP_Op1_reg[2] (\EX_Op2_reg[2] ),
        .\EX_Branch_CMP_Op1_reg[2]_0 (\EX_Op2_reg[2]_0 ),
        .\EX_Branch_CMP_Op1_reg[30] (\EX_Op2_reg[30] ),
        .\EX_Branch_CMP_Op1_reg[30]_0 (\EX_Op2_reg[30]_0 ),
        .\EX_Branch_CMP_Op1_reg[31] (\EX_Op2_reg[31] ),
        .\EX_Branch_CMP_Op1_reg[31]_0 (\EX_Op2_reg[31]_0 ),
        .\EX_Branch_CMP_Op1_reg[3] (\EX_Op2_reg[3] ),
        .\EX_Branch_CMP_Op1_reg[3]_0 (\EX_Op2_reg[3]_0 ),
        .\EX_Branch_CMP_Op1_reg[4] (\EX_Op2_reg[4] ),
        .\EX_Branch_CMP_Op1_reg[4]_0 (\EX_Op2_reg[4]_0 ),
        .\EX_Branch_CMP_Op1_reg[5] (\EX_Op2_reg[5] ),
        .\EX_Branch_CMP_Op1_reg[5]_0 (\EX_Op2_reg[5]_0 ),
        .\EX_Branch_CMP_Op1_reg[6] (\EX_Op2_reg[6] ),
        .\EX_Branch_CMP_Op1_reg[6]_0 (\EX_Op2_reg[6]_0 ),
        .\EX_Branch_CMP_Op1_reg[7] (\EX_Op2_reg[7] ),
        .\EX_Branch_CMP_Op1_reg[7]_0 (\EX_Op2_reg[7]_0 ),
        .\EX_Branch_CMP_Op1_reg[8] (\EX_Op2_reg[8] ),
        .\EX_Branch_CMP_Op1_reg[8]_0 (\EX_Op2_reg[8]_0 ),
        .\EX_Branch_CMP_Op1_reg[9] (\EX_Op2_reg[9] ),
        .\EX_Branch_CMP_Op1_reg[9]_0 (\EX_Op2_reg[9]_0 ),
        .GPR_Op1(GPR_Op1),
        .MEM_Fwd(MEM_Fwd),
        .\Using_FPGA.Native_0 (of_predecode[1]),
        .\Using_FPGA.Native_i_5__0_0 (\Using_FPGA.Native_i_5__0 [4:3]),
        .\Using_FPGA.Native_i_5__0_1 (\Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_1 ),
        .\Using_FPGA.Native_i_5__0_2 (of_predecode[2]),
        .\Using_FPGA.Native_i_5__0_3 (\EX_Op3[0]_i_2 ),
        .\Using_FPGA.Native_i_5__0_4 (\Using_FPGA.Native_i_5__0_0 [4:3]),
        .\Using_FPGA.Native_i_5__0_5 (\Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_2 ),
        .\Using_FPGA.Native_i_5__0_6 (\Using_FPGA.Native_i_5__0_1 ),
        .\Using_FPGA.Native_i_5__0_7 (\Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_3 ),
        .ex_sel_alu_i_reg(ex_sel_alu_i_reg_1),
        .of_instr_ii_9(of_instr_ii_9),
        .p_213_in(p_213_in),
        .p_216_in(p_216_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_172 \Instruction_Prefetch_Mux[33].Instr_Mux_MUXF7 
       (.I037_out(I037_out),
        .I135_out(I135_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_9(of_instr_ii_9));
  design_1_microblaze_0_0_MB_FDR_173 \Instruction_Prefetch_Mux[34].Gen_Instr_DFF 
       (.Clk(Clk),
        .of_instr_ii_8(of_instr_ii_8),
        .of_predecode(of_predecode[2]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_174 \Instruction_Prefetch_Mux[34].Instr_Mux_MUXF7 
       (.I033_out(I033_out),
        .I131_out(I131_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_8(of_instr_ii_8));
  design_1_microblaze_0_0_MB_FDR_175 \Instruction_Prefetch_Mux[35].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_predecode[3]),
        .of_instr_ii_7(of_instr_ii_7),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_176 \Instruction_Prefetch_Mux[35].Instr_Mux_MUXF7 
       (.I029_out(I029_out),
        .I127_out(I127_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_7(of_instr_ii_7));
  design_1_microblaze_0_0_MB_FDR_177 \Instruction_Prefetch_Mux[36].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_predecode[4]),
        .of_instr_ii_6(of_instr_ii_6),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_178 \Instruction_Prefetch_Mux[36].Instr_Mux_MUXF7 
       (.I025_out(I025_out),
        .I123_out(I123_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_6(of_instr_ii_6));
  design_1_microblaze_0_0_MB_FDR_179 \Instruction_Prefetch_Mux[37].Gen_Instr_DFF 
       (.Clk(Clk),
        .I0(I0),
        .I4(I4),
        .\Using_FPGA.Native_0 (of_predecode[5]),
        .\Using_FPGA.Native_i_7 (\Using_FPGA.Native_i_5__0 [2:0]),
        .\Using_FPGA.Native_i_7_0 (of_predecode[3]),
        .\Using_FPGA.Native_i_7_1 (of_predecode[4]),
        .\Using_FPGA.Native_i_8 (\Using_FPGA.Native_i_5__0_0 [2:0]),
        .\Using_FPGA.Native_i_9 (\EX_Op3[0]_i_6 ),
        .\ex_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_3 ),
        .\mem_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_5(of_instr_ii_5),
        .sync_reset(sync_reset),
        .\wb_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[37].Gen_Instr_DFF_n_2 ));
  design_1_microblaze_0_0_MB_MUXF7_180 \Instruction_Prefetch_Mux[37].Instr_Mux_MUXF7 
       (.I021_out(I021_out),
        .I119_out(I119_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_5(of_instr_ii_5));
  design_1_microblaze_0_0_MB_FDR_181 \Instruction_Prefetch_Mux[38].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Op2[0]_i_3_0 (\Using_FPGA.Native_i_5__0 [4:3]),
        .\EX_Op2[0]_i_3_1 (\Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_1 ),
        .\EX_Op2[0]_i_3_2 (of_predecode[7]),
        .\EX_Op2[0]_i_3_3 (\Using_FPGA.Native_i_5__0_1 ),
        .\EX_Op2[0]_i_3_4 (\Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_3 ),
        .\EX_Op2[0]_i_3_5 (\EX_Op3[0]_i_2 ),
        .\EX_Op2[0]_i_3_6 (\Using_FPGA.Native_i_5__0_0 [4:3]),
        .\EX_Op2[0]_i_3_7 (\Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_2 ),
        .\EX_Op2_reg[0] (\EX_Op2_reg[0]_1 ),
        .\EX_Op2_reg[0]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_17 ),
        .\EX_Op2_reg[0]_1 (\EX_Op2_reg[0]_2 ),
        .\EX_Op2_reg[10] (\EX_Op2_reg[10] ),
        .\EX_Op2_reg[10]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_7 ),
        .\EX_Op2_reg[10]_1 (\EX_Op2_reg[10]_0 ),
        .\EX_Op2_reg[11] (\EX_Op2_reg[11] ),
        .\EX_Op2_reg[11]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_6 ),
        .\EX_Op2_reg[11]_1 (\EX_Op2_reg[11]_0 ),
        .\EX_Op2_reg[12] (\EX_Op2_reg[12] ),
        .\EX_Op2_reg[12]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_5 ),
        .\EX_Op2_reg[12]_1 (\EX_Op2_reg[12]_0 ),
        .\EX_Op2_reg[13] (\EX_Op2_reg[13] ),
        .\EX_Op2_reg[13]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_4 ),
        .\EX_Op2_reg[13]_1 (\EX_Op2_reg[13]_0 ),
        .\EX_Op2_reg[14] (\EX_Op2_reg[14] ),
        .\EX_Op2_reg[14]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_3 ),
        .\EX_Op2_reg[14]_1 (\EX_Op2_reg[14]_0 ),
        .\EX_Op2_reg[15] (\EX_Op2_reg[15] ),
        .\EX_Op2_reg[15]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_2 ),
        .\EX_Op2_reg[15]_1 (\EX_Op2_reg[15]_0 ),
        .\EX_Op2_reg[16] (\EX_Op2_reg[16] ),
        .\EX_Op2_reg[16]_0 (\EX_Op2_reg[16]_0 ),
        .\EX_Op2_reg[16]_1 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[17] (\EX_Op2_reg[17] ),
        .\EX_Op2_reg[17]_0 (\Instruction_Prefetch_Mux[17].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[18] (\EX_Op2_reg[18] ),
        .\EX_Op2_reg[18]_0 (\Instruction_Prefetch_Mux[18].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[19] (\EX_Op2_reg[19] ),
        .\EX_Op2_reg[19]_0 (\Instruction_Prefetch_Mux[19].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[1] (\EX_Op2_reg[1] ),
        .\EX_Op2_reg[1]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_16 ),
        .\EX_Op2_reg[1]_1 (\EX_Op2_reg[1]_0 ),
        .\EX_Op2_reg[20] (\EX_Op2_reg[20] ),
        .\EX_Op2_reg[20]_0 (\Instruction_Prefetch_Mux[20].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[21] (\EX_Op2_reg[21] ),
        .\EX_Op2_reg[21]_0 (\Instruction_Prefetch_Mux[21].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[22] (\EX_Op2_reg[22] ),
        .\EX_Op2_reg[22]_0 (\Instruction_Prefetch_Mux[22].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[23] (\EX_Op2_reg[23] ),
        .\EX_Op2_reg[23]_0 (\Instruction_Prefetch_Mux[23].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[24] (\EX_Op2_reg[24] ),
        .\EX_Op2_reg[24]_0 (\Instruction_Prefetch_Mux[24].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[24]_1 (\EX_Op2_reg[24]_0 ),
        .\EX_Op2_reg[25] (\EX_Op2_reg[25] ),
        .\EX_Op2_reg[25]_0 (\Instruction_Prefetch_Mux[25].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[25]_1 (\EX_Op2_reg[25]_0 ),
        .\EX_Op2_reg[26] (\EX_Op2_reg[26] ),
        .\EX_Op2_reg[26]_0 (\Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[26]_1 (\EX_Op2_reg[26]_0 ),
        .\EX_Op2_reg[27] (\EX_Op2_reg[27] ),
        .\EX_Op2_reg[27]_0 (\Instruction_Prefetch_Mux[27].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[27]_1 (\EX_Op2_reg[27]_0 ),
        .\EX_Op2_reg[28] (\EX_Op2_reg[28] ),
        .\EX_Op2_reg[28]_0 (\Instruction_Prefetch_Mux[28].Gen_Instr_DFF_n_2 ),
        .\EX_Op2_reg[28]_1 (\EX_Op2_reg[28]_0 ),
        .\EX_Op2_reg[29] (\EX_Op2_reg[29] ),
        .\EX_Op2_reg[29]_0 (\Instruction_Prefetch_Mux[29].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[29]_1 (\EX_Op2_reg[29]_0 ),
        .\EX_Op2_reg[2] (\EX_Op2_reg[2] ),
        .\EX_Op2_reg[2]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_15 ),
        .\EX_Op2_reg[2]_1 (\EX_Op2_reg[2]_0 ),
        .\EX_Op2_reg[30] (\EX_Op2_reg[30] ),
        .\EX_Op2_reg[30]_0 (\Instruction_Prefetch_Mux[30].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[30]_1 (\EX_Op2_reg[30]_0 ),
        .\EX_Op2_reg[31] (\EX_Op2_reg[31] ),
        .\EX_Op2_reg[31]_0 (\Instruction_Prefetch_Mux[31].Gen_Instr_DFF_n_1 ),
        .\EX_Op2_reg[31]_1 (\EX_Op2_reg[31]_0 ),
        .\EX_Op2_reg[3] (\EX_Op2_reg[3] ),
        .\EX_Op2_reg[3]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_14 ),
        .\EX_Op2_reg[3]_1 (\EX_Op2_reg[3]_0 ),
        .\EX_Op2_reg[4] (\EX_Op2_reg[4] ),
        .\EX_Op2_reg[4]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_13 ),
        .\EX_Op2_reg[4]_1 (\EX_Op2_reg[4]_0 ),
        .\EX_Op2_reg[5] (\EX_Op2_reg[5] ),
        .\EX_Op2_reg[5]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_12 ),
        .\EX_Op2_reg[5]_1 (\EX_Op2_reg[5]_0 ),
        .\EX_Op2_reg[6] (\EX_Op2_reg[6] ),
        .\EX_Op2_reg[6]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_11 ),
        .\EX_Op2_reg[6]_1 (\EX_Op2_reg[6]_0 ),
        .\EX_Op2_reg[7] (\EX_Op2_reg[7] ),
        .\EX_Op2_reg[7]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_10 ),
        .\EX_Op2_reg[7]_1 (\EX_Op2_reg[7]_0 ),
        .\EX_Op2_reg[8] (\EX_Op2_reg[8] ),
        .\EX_Op2_reg[8]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_9 ),
        .\EX_Op2_reg[8]_1 (\EX_Op2_reg[8]_0 ),
        .\EX_Op2_reg[9] (\EX_Op2_reg[9] ),
        .\EX_Op2_reg[9]_0 (\Instruction_Prefetch_Mux[16].Gen_Instr_DFF_n_8 ),
        .\EX_Op2_reg[9]_1 (\EX_Op2_reg[9]_0 ),
        .MEM_Fwd(MEM_Fwd),
        .\Using_FPGA.Native_0 (of_predecode[6]),
        .ex_sel_alu_i_reg(ex_sel_alu_i_reg),
        .of_instr_ii_4(of_instr_ii_4),
        .of_use_op2_s(of_use_op2_s),
        .p_213_in(p_213_in),
        .p_216_in(p_216_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_182 \Instruction_Prefetch_Mux[38].Instr_Mux_MUXF7 
       (.I017_out(I017_out),
        .I115_out(I115_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_4(of_instr_ii_4));
  design_1_microblaze_0_0_MB_FDR_183 \Instruction_Prefetch_Mux[39].Gen_Instr_DFF 
       (.Clk(Clk),
        .of_instr_ii_3(of_instr_ii_3),
        .of_predecode(of_predecode[7]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_184 \Instruction_Prefetch_Mux[39].Instr_Mux_MUXF7 
       (.I013_out(I013_out),
        .I111_out(I111_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_3(of_instr_ii_3));
  design_1_microblaze_0_0_MB_FDR_185 \Instruction_Prefetch_Mux[3].Gen_Instr_DFF 
       (.Clk(Clk),
        .EX_ALU_Op1142_out__0(EX_ALU_Op1142_out__0),
        .\EX_Sext_Op_reg[0] (of_instr[3]),
        .\EX_Sext_Op_reg[0]_0 (\Instruction_Prefetch_Mux[26].Gen_Instr_DFF_n_2 ),
        .\EX_Sext_Op_reg[0]_1 (\Using_FPGA.Native_15 ),
        .\Using_FPGA.Native_0 (of_instr[2]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_5 ),
        .\Using_FPGA.Native_2 (ex_op1_cmp_eq1),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_8 ),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_14 [1]),
        .\Using_FPGA.Native_5 (\Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_13 ),
        .\Using_FPGA.Native_6 (\Using_FPGA.Native_22 ),
        .ex_branch_with_delayslot_i(ex_branch_with_delayslot_i),
        .ex_branch_with_delayslot_i_reg(\Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_1 ),
        .ex_branch_with_delayslot_i_reg_0(\Using_FPGA.Native_60 ),
        .ex_branch_with_delayslot_i_reg_1(ex_branch_with_delayslot_i_reg_0),
        .ex_branch_with_delayslot_reg(\Using_FPGA.Native_4 [20]),
        .ex_branch_with_delayslot_reg_0(D[1]),
        .ex_enable_sext_shift_i0(ex_enable_sext_shift_i0),
        .ex_op1_cmp_eq_n5_out(ex_op1_cmp_eq_n5_out),
        .ex_op1_cmp_eq_n_reg(\Using_FPGA.Native_2 ),
        .ex_op1_cmp_eq_n_reg_0(\Using_FPGA.Native_3 ),
        .ex_op1_cmp_eq_n_reg_1(\Using_FPGA.Native_1 ),
        .ex_sel_alu_i0(ex_sel_alu_i0),
        .ex_sel_alu_i_reg(\Using_FPGA.Native_4 [10]),
        .force12_out(force12_out),
        .force2_reg(of_instr[5]),
        .force2_reg_0(of_instr[0]),
        .force2_reg_1(of_instr[4]),
        .force2_reg_2(of_instr[1]),
        .force_Val10_out(force_Val10_out),
        .of_instr_ii_39(of_instr_ii_39),
        .sync_reset(sync_reset),
        .use_Reg_Neg_DI1_out(use_Reg_Neg_DI1_out),
        .use_Reg_Neg_S3_out(use_Reg_Neg_S3_out));
  design_1_microblaze_0_0_MB_MUXF7_186 \Instruction_Prefetch_Mux[3].Instr_Mux_MUXF7 
       (.I0157_out(I0157_out),
        .I1155_out(I1155_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_39(of_instr_ii_39));
  design_1_microblaze_0_0_MB_FDR_187 \Instruction_Prefetch_Mux[40].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_predecode[8]),
        .of_instr_ii_2(of_instr_ii_2),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_188 \Instruction_Prefetch_Mux[40].Instr_Mux_MUXF7 
       (.I09_out(I09_out),
        .I17_out(I17_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_2(of_instr_ii_2));
  design_1_microblaze_0_0_MB_FDR_189 \Instruction_Prefetch_Mux[41].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (of_predecode[9]),
        .of_instr_ii_1(of_instr_ii_1),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_190 \Instruction_Prefetch_Mux[41].Instr_Mux_MUXF7 
       (.I05_out(I05_out),
        .I13_out(I13_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_1(of_instr_ii_1));
  design_1_microblaze_0_0_MB_FDR_191 \Instruction_Prefetch_Mux[42].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Op2[0]_i_6 (\EX_Op3[0]_i_6 ),
        .\EX_Op2[0]_i_7 (\Using_FPGA.Native_i_5__0_0 [2:0]),
        .\EX_Op2[0]_i_8 (\Using_FPGA.Native_i_5__0 [2:0]),
        .\EX_Op2[0]_i_8_0 (of_predecode[8]),
        .\EX_Op2[0]_i_8_1 (of_predecode[9]),
        .I0(I0),
        .I4(I4),
        .\Using_FPGA.Native_0 (of_predecode[10]),
        .\ex_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_3 ),
        .\mem_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_1 ),
        .of_instr_ii_0(of_instr_ii_0),
        .sync_reset(sync_reset),
        .\wb_gpr_write_addr_reg[4] (\Instruction_Prefetch_Mux[42].Gen_Instr_DFF_n_2 ));
  design_1_microblaze_0_0_MB_MUXF7_192 \Instruction_Prefetch_Mux[42].Instr_Mux_MUXF7 
       (.I0_1(I0_1),
        .I1(I1),
        .IReady(IReady),
        .IReady_0(IReady_0),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .\Using_FPGA.Native_1 (ex_branch_with_delayslot_i_reg_0),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_61 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_62 ),
        .if_missed_fetch(if_missed_fetch),
        .of_instr_ii_0(of_instr_ii_0));
  design_1_microblaze_0_0_MB_FDR_193 \Instruction_Prefetch_Mux[4].Gen_Instr_DFF 
       (.Clk(Clk),
        .D224_out(D224_out),
        .\EX_Op1_reg[0] (\EX_Op1_reg[0] ),
        .EX_SWAP_Instr_reg(\Using_FPGA.Native_4 [8]),
        .EX_SWAP_Instr_reg_0(\Using_FPGA.Native_4 [6]),
        .EX_SWAP_Instr_reg_1(\Using_FPGA.Native_4 [5]),
        .EX_SWAP_Instr_reg_2(\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_5 ),
        .\EX_Sext_Op_reg[1] (\Using_FPGA.Native_4 [0]),
        .I1_0(I1_0),
        .OF_Op1_Sel_SPR_PC0__0(OF_Op1_Sel_SPR_PC0__0),
        .\Using_FPGA.Native_0 (of_instr[1]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[4].Gen_Instr_DFF_n_2 ),
        .\Using_FPGA.Native_10 (\Using_FPGA.Native_32 ),
        .\Using_FPGA.Native_11 (\Using_FPGA.Native_33 ),
        .\Using_FPGA.Native_12 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_13 (\Using_FPGA.Native_35 ),
        .\Using_FPGA.Native_14 (\Using_FPGA.Native_36 ),
        .\Using_FPGA.Native_15 (\Using_FPGA.Native_37 ),
        .\Using_FPGA.Native_16 (\Using_FPGA.Native_38 ),
        .\Using_FPGA.Native_17 (\Using_FPGA.Native_39 ),
        .\Using_FPGA.Native_18 (\Using_FPGA.Native_40 ),
        .\Using_FPGA.Native_19 (\Using_FPGA.Native_41 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_12 ),
        .\Using_FPGA.Native_20 (\Using_FPGA.Native_42 ),
        .\Using_FPGA.Native_21 (\Using_FPGA.Native_43 ),
        .\Using_FPGA.Native_22 (\Using_FPGA.Native_44 ),
        .\Using_FPGA.Native_23 (\Using_FPGA.Native_45 ),
        .\Using_FPGA.Native_24 (\Using_FPGA.Native_46 ),
        .\Using_FPGA.Native_25 (\Using_FPGA.Native_47 ),
        .\Using_FPGA.Native_26 (\Using_FPGA.Native_48 ),
        .\Using_FPGA.Native_27 (\Using_FPGA.Native_49 ),
        .\Using_FPGA.Native_28 (\Using_FPGA.Native_50 ),
        .\Using_FPGA.Native_29 (\Using_FPGA.Native_51 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_13 ),
        .\Using_FPGA.Native_30 (\Using_FPGA.Native_52 ),
        .\Using_FPGA.Native_31 (\Using_FPGA.Native_53 ),
        .\Using_FPGA.Native_32 (\Using_FPGA.Native_54 ),
        .\Using_FPGA.Native_33 (\Using_FPGA.Native_55 ),
        .\Using_FPGA.Native_34 (\Using_FPGA.Native_56 ),
        .\Using_FPGA.Native_35 (\Using_FPGA.Native_57 ),
        .\Using_FPGA.Native_36 (\Using_FPGA.Native_58 ),
        .\Using_FPGA.Native_37 (of_instr[0]),
        .\Using_FPGA.Native_38 (\Instruction_Prefetch_Mux[2].Gen_Instr_DFF_n_3 ),
        .\Using_FPGA.Native_39 (\Using_FPGA.Native_4 [10]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_14 [0]),
        .\Using_FPGA.Native_40 (\Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_13 ),
        .\Using_FPGA.Native_5 (\Using_FPGA.Native_15 ),
        .\Using_FPGA.Native_6 (\Using_FPGA.Native_28 ),
        .\Using_FPGA.Native_7 (\Using_FPGA.Native_29 ),
        .\Using_FPGA.Native_8 (\Using_FPGA.Native_30 ),
        .\Using_FPGA.Native_9 (\Using_FPGA.Native_31 ),
        .ex_MSR(ex_MSR),
        .ex_is_multi_instr2_reg(\Using_FPGA.Native_4 [14]),
        .ex_is_multi_or_load_instr0(ex_is_multi_or_load_instr0),
        .ex_is_multi_or_load_instr_reg(of_instr[4]),
        .ex_is_multi_or_load_instr_reg_0(of_instr[2]),
        .ex_is_multi_or_load_instr_reg_1(of_instr[5]),
        .ex_load_shift_carry0(ex_load_shift_carry0),
        .ex_load_shift_carry_reg(of_instr[3]),
        .ex_mfsmsr_i_reg(\Using_FPGA.Native_4 [2]),
        .ex_mfsmsr_i_reg_0(\Using_FPGA.Native_4 [1]),
        .ex_mfsmsr_i_reg_1(\Using_FPGA.Native_4 [3]),
        .of_Sel_SPR_MSR1(of_Sel_SPR_MSR1),
        .of_Sel_SPR_MSR88_out(of_Sel_SPR_MSR88_out),
        .of_instr_ii_38(of_instr_ii_38),
        .of_op1_sel_spr(of_op1_sel_spr),
        .p_0_in30_in(p_0_in30_in),
        .p_9_in(p_9_in),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_194 \Instruction_Prefetch_Mux[4].Instr_Mux_MUXF7 
       (.I0153_out(I0153_out),
        .I1151_out(I1151_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_38(of_instr_ii_38));
  design_1_microblaze_0_0_MB_FDR_195 \Instruction_Prefetch_Mux[5].Gen_Instr_DFF 
       (.Clk(Clk),
        .E(E),
        .EX_Is_Div_Instr(EX_Is_Div_Instr),
        .\Using_FPGA.Native_0 (of_instr[0]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_16 ),
        .\Using_FPGA.Native_2 (of_instr[1]),
        .ex_is_div_instr_I_reg(ex_is_div_instr_I_reg),
        .ex_is_div_instr_I_reg_0(\Using_FPGA.Native_60 ),
        .ex_is_div_instr_I_reg_1(of_instr[2]),
        .ex_is_div_instr_I_reg_2(of_instr[5]),
        .ex_is_div_instr_I_reg_3(of_instr[4]),
        .of_instr_ii_37(of_instr_ii_37),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_196 \Instruction_Prefetch_Mux[5].Instr_Mux_MUXF7 
       (.I0149_out(I0149_out),
        .I1147_out(I1147_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_37(of_instr_ii_37));
  design_1_microblaze_0_0_MB_FDR_197 \Instruction_Prefetch_Mux[6].Gen_Instr_DFF 
       (.Clk(Clk),
        .\EX_Op3[0]_i_3 (\Using_FPGA.Native_i_5__0 [4:3]),
        .\EX_Op3[0]_i_3_0 (\Instruction_Prefetch_Mux[10].Gen_Instr_DFF_n_1 ),
        .\EX_Op3[0]_i_3_1 (D[0]),
        .\EX_Op3[0]_i_3_2 (\Instruction_Prefetch_Mux[32].Gen_Instr_DFF_n_33 ),
        .\EX_Op3[0]_i_5 (\Using_FPGA.Native_i_5__0_0 [4]),
        .\EX_Op3[0]_i_6 (\Using_FPGA.Native_i_5__0_1 [1]),
        .\Using_FPGA.Native_0 (D[1]),
        .\Using_FPGA.Native_1 (\Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_2 ),
        .\Using_FPGA.Native_2 (\Instruction_Prefetch_Mux[6].Gen_Instr_DFF_n_3 ),
        .of_instr_ii_36(of_instr_ii_36),
        .of_read_mem_write_op3_conflict__1(of_read_mem_write_op3_conflict__1),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_198 \Instruction_Prefetch_Mux[6].Instr_Mux_MUXF7 
       (.I0145_out(I0145_out),
        .I1143_out(I1143_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_36(of_instr_ii_36));
  design_1_microblaze_0_0_MB_FDR_199 \Instruction_Prefetch_Mux[7].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (D[0]),
        .\Using_FPGA.Native_1 (ex_mbar_is_sleep_cmb),
        .ex_mbar_is_sleep(ex_mbar_is_sleep),
        .ex_mbar_is_sleep_reg(D[1]),
        .ex_mbar_is_sleep_reg_0(\Using_FPGA.Native_60 ),
        .of_instr_ii_35(of_instr_ii_35),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_200 \Instruction_Prefetch_Mux[7].Instr_Mux_MUXF7 
       (.I0141_out(I0141_out),
        .I1139_out(I1139_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_35(of_instr_ii_35));
  design_1_microblaze_0_0_MB_FDR_201 \Instruction_Prefetch_Mux[8].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_7 ),
        .ex_gpr_write111_out__0(ex_gpr_write111_out__0),
        .ex_gpr_write_reg(\Using_FPGA.Native_60 ),
        .ex_gpr_write_reg_0(D[1]),
        .ex_gpr_write_reg_1(D[0]),
        .ex_op1_cmp_eq1(ex_op1_cmp_eq1),
        .ex_op1_cmp_eq_reg(\Using_FPGA.Native_3 ),
        .ex_op1_cmp_eq_reg_0(\Using_FPGA.Native_2 ),
        .of_instr_ii_34(of_instr_ii_34),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_202 \Instruction_Prefetch_Mux[8].Instr_Mux_MUXF7 
       (.I0137_out(I0137_out),
        .I1135_out(I1135_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_34(of_instr_ii_34));
  design_1_microblaze_0_0_MB_FDR_203 \Instruction_Prefetch_Mux[9].Gen_Instr_DFF 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_2 ),
        .of_instr_ii_33(of_instr_ii_33),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_MUXF7_204 \Instruction_Prefetch_Mux[9].Instr_Mux_MUXF7 
       (.I0133_out(I0133_out),
        .I1131_out(I1131_out),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_60 ),
        .of_instr_ii_33(of_instr_ii_33));
  design_1_microblaze_0_0_MB_FDS Last_Sel_DFF
       (.Clk(Clk),
        .I0101_out(I0101_out),
        .I0105_out(I0105_out),
        .I0109_out(I0109_out),
        .I0113_out(I0113_out),
        .I0117_out(I0117_out),
        .I0121_out(I0121_out),
        .I0125_out(I0125_out),
        .I0129_out(I0129_out),
        .I0133_out(I0133_out),
        .I0137_out(I0137_out),
        .I013_out(I013_out),
        .I0141_out(I0141_out),
        .I0145_out(I0145_out),
        .I0149_out(I0149_out),
        .I0153_out(I0153_out),
        .I0157_out(I0157_out),
        .I0161_out(I0161_out),
        .I0165_out(I0165_out),
        .I0169_out(I0169_out),
        .I017_out(I017_out),
        .I021_out(I021_out),
        .I025_out(I025_out),
        .I029_out(I029_out),
        .I033_out(I033_out),
        .I037_out(I037_out),
        .I041_out(I041_out),
        .I045_out(I045_out),
        .I049_out(I049_out),
        .I053_out(I053_out),
        .I057_out(I057_out),
        .I05_out(I05_out),
        .I061_out(I061_out),
        .I065_out(I065_out),
        .I069_out(I069_out),
        .I073_out(I073_out),
        .I077_out(I077_out),
        .I081_out(I081_out),
        .I085_out(I085_out),
        .I089_out(I089_out),
        .I093_out(I093_out),
        .I097_out(I097_out),
        .I09_out(I09_out),
        .I0_1(I0_1),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [0]),
        .\Using_FPGA.Native_1 (IReady_0),
        .\Using_FPGA.Native_10 (D[0]),
        .\Using_FPGA.Native_11 (D[1]),
        .\Using_FPGA.Native_12 (of_instr[0]),
        .\Using_FPGA.Native_13 (of_instr[1]),
        .\Using_FPGA.Native_14 (of_instr[2]),
        .\Using_FPGA.Native_15 (of_instr[3]),
        .\Using_FPGA.Native_16 (of_instr[4]),
        .\Using_FPGA.Native_17 (of_instr[5]),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_4 [0]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_4 [1]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_4 [2]),
        .\Using_FPGA.Native_5 (\Using_FPGA.Native_4 [3]),
        .\Using_FPGA.Native_6 (\Using_FPGA.Native_4 [20:4]),
        .\Using_FPGA.Native_7 (\Using_FPGA.Native_3 ),
        .\Using_FPGA.Native_8 (\Using_FPGA.Native_2 ),
        .\Using_FPGA.Native_9 (\Using_FPGA.Native_1 ),
        .in({in[32:11],in[9:0]}),
        .of_predecode(of_predecode),
        .sel_input_i_0(sel_input_i_0),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_LUT6__parameterized4 Mux_Select_Empty_LUT6
       (.I4_0(I4_0),
        .I5(I5),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [0]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_2 (IReady_0),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_60 ),
        .sel_input_i_0(sel_input_i_0));
  design_1_microblaze_0_0_MB_LUT6__parameterized6 Mux_Select_OF_Valid_LUT6
       (.I4_0(I4_0),
        .I5(I5),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native [0]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_2 (IReady_0),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_60 ),
        .of_Valid_II(of_Valid_II));
  design_1_microblaze_0_0_MB_FDR_205 OF_Valid_DFF
       (.Clk(Clk),
        .Dbg_Clean_Stop0(Dbg_Clean_Stop0),
        .Dbg_Clean_Stop_reg(\Using_FPGA.Native_5 ),
        .Q(Q),
        .\Using_FPGA.Native_0 (of_valid),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_11 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_23 ),
        .ex_branch_with_delayslot(ex_branch_with_delayslot),
        .ex_branch_with_delayslot_reg(ex_branch_with_delayslot_reg),
        .ex_jump(ex_jump),
        .ex_jump_nodelay(ex_jump_nodelay),
        .ex_jump_q(ex_jump_q),
        .of_Valid_II(of_Valid_II),
        .p_9_in(p_9_in),
        .sync_reset(sync_reset),
        .wb_exception(wb_exception));
  FDRE ex_branch_with_delayslot_i_reg
       (.C(Clk),
        .CE(1'b1),
        .D(\Instruction_Prefetch_Mux[3].Gen_Instr_DFF_n_1 ),
        .Q(ex_branch_with_delayslot_i),
        .R(1'b0));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][0]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][0]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[32]),
        .Q(p_1_in209_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][10]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][10]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[22]),
        .Q(p_1_in159_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][11]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][11]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[9]),
        .Q(p_1_in154_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][12]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][12]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[8]),
        .Q(p_1_in149_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][13]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][13]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[7]),
        .Q(p_1_in144_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][14]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][14]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[6]),
        .Q(p_1_in139_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][15]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][15]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[5]),
        .Q(p_1_in134_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][16]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][16]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[4]),
        .Q(p_1_in129_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][17]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][17]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[3]),
        .Q(p_1_in124_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][18]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][18]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[2]),
        .Q(p_1_in119_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][19]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][19]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[1]),
        .Q(p_1_in114_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][1]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][1]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[31]),
        .Q(p_1_in204_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][20]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][20]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[0]),
        .Q(p_1_in109_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][21]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][21]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[21]),
        .Q(p_1_in104_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][22]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][22]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[20]),
        .Q(p_1_in99_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][23]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][23]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[19]),
        .Q(p_1_in94_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][24]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][24]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[18]),
        .Q(p_1_in89_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][25]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][25]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[17]),
        .Q(p_1_in84_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][26]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][26]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[16]),
        .Q(p_1_in79_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][27]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][27]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[15]),
        .Q(p_1_in74_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][28]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][28]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[14]),
        .Q(p_1_in69_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][29]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][29]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[13]),
        .Q(p_1_in64_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][2]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][2]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[30]),
        .Q(p_1_in199_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][30]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][30]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[12]),
        .Q(p_1_in59_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][31]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][31]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[11]),
        .Q(p_1_in54_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][32]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][32]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[10]),
        .Q(\Using_FPGA.Native_59 ));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][33]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][33]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[9]),
        .Q(p_1_in44_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][34]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][34]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[8]),
        .Q(p_1_in39_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][35]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][35]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[7]),
        .Q(p_1_in34_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][36]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][36]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[6]),
        .Q(p_1_in29_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][37]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][37]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[5]),
        .Q(p_1_in24_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][38]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][38]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[4]),
        .Q(p_1_in19_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][39]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][39]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[3]),
        .Q(p_1_in14_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][3]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][3]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[29]),
        .Q(p_1_in194_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][40]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][40]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[2]),
        .Q(p_1_in9_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][41]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][41]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[1]),
        .Q(p_1_in4_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][42]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][42]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[0]),
        .Q(\ibuffer_reg[3][42]_srl4_n_0 ));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][4]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][4]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[28]),
        .Q(p_1_in189_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][5]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][5]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[27]),
        .Q(p_1_in184_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][6]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][6]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[26]),
        .Q(p_1_in179_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][7]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][7]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[25]),
        .Q(p_1_in174_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][8]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][8]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[24]),
        .Q(p_1_in169_in));
  (* srl_bus_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3] " *) 
  (* srl_name = "U0/\MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/ibuffer_reg[3][9]_srl4 " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \ibuffer_reg[3][9]_srl4 
       (.A0(if_pre_buffer_addr),
        .A1(\Using_FPGA.Native [1]),
        .A2(1'b0),
        .A3(1'b0),
        .CE(IReady_0),
        .CLK(Clk),
        .D(in[23]),
        .Q(p_1_in164_in));
endmodule

(* ORIG_REF_NAME = "Register_File_gti" *) 
module design_1_microblaze_0_0_Register_File_gti
   (GPR_Op1,
    GPR_Op2,
    GPR_Op3,
    Clk,
    \EX_Branch_CMP_Op1_reg[18] ,
    DID,
    of_gpr_op1_rd_addr,
    of_imm_data,
    of_gpr_op3_rd_addr,
    \EX_Branch_CMP_Op1_reg[18]_0 ,
    \EX_Branch_CMP_Op1_reg[2] ,
    \EX_Branch_CMP_Op1_reg[4] ,
    \EX_Branch_CMP_Op1_reg[6] ,
    \EX_Branch_CMP_Op1_reg[8] ,
    \EX_Branch_CMP_Op1_reg[10] ,
    \EX_Branch_CMP_Op1_reg[12] ,
    \EX_Branch_CMP_Op1_reg[14] ,
    \EX_Branch_CMP_Op1_reg[16] ,
    \EX_Branch_CMP_Op1_reg[18]_1 ,
    \EX_Branch_CMP_Op1_reg[20] ,
    \EX_Branch_CMP_Op1_reg[22] ,
    \EX_Branch_CMP_Op1_reg[24] ,
    \EX_Branch_CMP_Op1_reg[26] ,
    \EX_Branch_CMP_Op1_reg[28] ,
    \EX_Branch_CMP_Op1_reg[30] );
  output [0:31]GPR_Op1;
  output [0:31]GPR_Op2;
  output [0:31]GPR_Op3;
  input Clk;
  input \EX_Branch_CMP_Op1_reg[18] ;
  input [1:0]DID;
  input [0:4]of_gpr_op1_rd_addr;
  input [4:0]of_imm_data;
  input [0:4]of_gpr_op3_rd_addr;
  input [4:0]\EX_Branch_CMP_Op1_reg[18]_0 ;
  input [1:0]\EX_Branch_CMP_Op1_reg[2] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[4] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[6] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[8] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[10] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[12] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[14] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[16] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[18]_1 ;
  input [1:0]\EX_Branch_CMP_Op1_reg[20] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[22] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[24] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[26] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[28] ;
  input [1:0]\EX_Branch_CMP_Op1_reg[30] ;

  wire Clk;
  wire [1:0]DID;
  wire [1:0]\EX_Branch_CMP_Op1_reg[10] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[12] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[14] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[16] ;
  wire \EX_Branch_CMP_Op1_reg[18] ;
  wire [4:0]\EX_Branch_CMP_Op1_reg[18]_0 ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[18]_1 ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[20] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[22] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[24] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[26] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[28] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[2] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[30] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[4] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[6] ;
  wire [1:0]\EX_Branch_CMP_Op1_reg[8] ;
  wire [0:31]GPR_Op1;
  wire [0:31]GPR_Op2;
  wire [0:31]GPR_Op3;
  wire [0:4]of_gpr_op1_rd_addr;
  wire [0:4]of_gpr_op3_rd_addr;
  wire [4:0]of_imm_data;

  design_1_microblaze_0_0_MB_RAM32M \Using_LUT6.All_RAM32M[0].ram32m_i 
       (.Clk(Clk),
        .DID(DID),
        .\EX_Branch_CMP_Op1_reg[0] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[0]_0 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[0],GPR_Op1[1]}),
        .GPR_Op2({GPR_Op2[0],GPR_Op2[1]}),
        .GPR_Op3({GPR_Op3[0],GPR_Op3[1]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_409 \Using_LUT6.All_RAM32M[10].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[20] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[20]_0 (\EX_Branch_CMP_Op1_reg[20] ),
        .\EX_Branch_CMP_Op1_reg[20]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[20],GPR_Op1[21]}),
        .GPR_Op2({GPR_Op2[20],GPR_Op2[21]}),
        .GPR_Op3({GPR_Op3[20],GPR_Op3[21]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_410 \Using_LUT6.All_RAM32M[11].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[22] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[22]_0 (\EX_Branch_CMP_Op1_reg[22] ),
        .\EX_Branch_CMP_Op1_reg[22]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[22],GPR_Op1[23]}),
        .GPR_Op2({GPR_Op2[22],GPR_Op2[23]}),
        .GPR_Op3({GPR_Op3[22],GPR_Op3[23]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_411 \Using_LUT6.All_RAM32M[12].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[24] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[24]_0 (\EX_Branch_CMP_Op1_reg[24] ),
        .\EX_Branch_CMP_Op1_reg[24]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[24],GPR_Op1[25]}),
        .GPR_Op2({GPR_Op2[24],GPR_Op2[25]}),
        .GPR_Op3({GPR_Op3[24],GPR_Op3[25]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_412 \Using_LUT6.All_RAM32M[13].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[26] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[26]_0 (\EX_Branch_CMP_Op1_reg[26] ),
        .\EX_Branch_CMP_Op1_reg[26]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[26],GPR_Op1[27]}),
        .GPR_Op2({GPR_Op2[26],GPR_Op2[27]}),
        .GPR_Op3({GPR_Op3[26],GPR_Op3[27]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_413 \Using_LUT6.All_RAM32M[14].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[28] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[28]_0 (\EX_Branch_CMP_Op1_reg[28] ),
        .\EX_Branch_CMP_Op1_reg[28]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[28],GPR_Op1[29]}),
        .GPR_Op2({GPR_Op2[28],GPR_Op2[29]}),
        .GPR_Op3({GPR_Op3[28],GPR_Op3[29]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_414 \Using_LUT6.All_RAM32M[15].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[30] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[30]_0 (\EX_Branch_CMP_Op1_reg[30] ),
        .\EX_Branch_CMP_Op1_reg[30]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[30],GPR_Op1[31]}),
        .GPR_Op2({GPR_Op2[30],GPR_Op2[31]}),
        .GPR_Op3({GPR_Op3[30],GPR_Op3[31]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_415 \Using_LUT6.All_RAM32M[1].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[2] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[2]_0 (\EX_Branch_CMP_Op1_reg[2] ),
        .\EX_Branch_CMP_Op1_reg[2]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[2],GPR_Op1[3]}),
        .GPR_Op2({GPR_Op2[2],GPR_Op2[3]}),
        .GPR_Op3({GPR_Op3[2],GPR_Op3[3]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_416 \Using_LUT6.All_RAM32M[2].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[4] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[4]_0 (\EX_Branch_CMP_Op1_reg[4] ),
        .\EX_Branch_CMP_Op1_reg[4]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[4],GPR_Op1[5]}),
        .GPR_Op2({GPR_Op2[4],GPR_Op2[5]}),
        .GPR_Op3({GPR_Op3[4],GPR_Op3[5]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_417 \Using_LUT6.All_RAM32M[3].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[6] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[6]_0 (\EX_Branch_CMP_Op1_reg[6] ),
        .\EX_Branch_CMP_Op1_reg[6]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[6],GPR_Op1[7]}),
        .GPR_Op2({GPR_Op2[6],GPR_Op2[7]}),
        .GPR_Op3({GPR_Op3[6],GPR_Op3[7]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_418 \Using_LUT6.All_RAM32M[4].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[8] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[8]_0 (\EX_Branch_CMP_Op1_reg[8] ),
        .\EX_Branch_CMP_Op1_reg[8]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[8],GPR_Op1[9]}),
        .GPR_Op2({GPR_Op2[8],GPR_Op2[9]}),
        .GPR_Op3({GPR_Op3[8],GPR_Op3[9]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_419 \Using_LUT6.All_RAM32M[5].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[10] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[10]_0 (\EX_Branch_CMP_Op1_reg[10] ),
        .\EX_Branch_CMP_Op1_reg[10]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[10],GPR_Op1[11]}),
        .GPR_Op2({GPR_Op2[10],GPR_Op2[11]}),
        .GPR_Op3({GPR_Op3[10],GPR_Op3[11]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_420 \Using_LUT6.All_RAM32M[6].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[12] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[12]_0 (\EX_Branch_CMP_Op1_reg[12] ),
        .\EX_Branch_CMP_Op1_reg[12]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[12],GPR_Op1[13]}),
        .GPR_Op2({GPR_Op2[12],GPR_Op2[13]}),
        .GPR_Op3({GPR_Op3[12],GPR_Op3[13]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_421 \Using_LUT6.All_RAM32M[7].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[14] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[14]_0 (\EX_Branch_CMP_Op1_reg[14] ),
        .\EX_Branch_CMP_Op1_reg[14]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[14],GPR_Op1[15]}),
        .GPR_Op2({GPR_Op2[14],GPR_Op2[15]}),
        .GPR_Op3({GPR_Op3[14],GPR_Op3[15]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_422 \Using_LUT6.All_RAM32M[8].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[16] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[16]_0 (\EX_Branch_CMP_Op1_reg[16] ),
        .\EX_Branch_CMP_Op1_reg[16]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[16],GPR_Op1[17]}),
        .GPR_Op2({GPR_Op2[16],GPR_Op2[17]}),
        .GPR_Op3({GPR_Op3[16],GPR_Op3[17]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
  design_1_microblaze_0_0_MB_RAM32M_423 \Using_LUT6.All_RAM32M[9].ram32m_i 
       (.Clk(Clk),
        .\EX_Branch_CMP_Op1_reg[18] (\EX_Branch_CMP_Op1_reg[18] ),
        .\EX_Branch_CMP_Op1_reg[18]_0 (\EX_Branch_CMP_Op1_reg[18]_1 ),
        .\EX_Branch_CMP_Op1_reg[18]_1 (\EX_Branch_CMP_Op1_reg[18]_0 ),
        .GPR_Op1({GPR_Op1[18],GPR_Op1[19]}),
        .GPR_Op2({GPR_Op2[18],GPR_Op2[19]}),
        .GPR_Op3({GPR_Op3[18],GPR_Op3[19]}),
        .of_gpr_op1_rd_addr(of_gpr_op1_rd_addr),
        .of_gpr_op3_rd_addr(of_gpr_op3_rd_addr),
        .of_imm_data(of_imm_data));
endmodule

(* ORIG_REF_NAME = "Shift_Logic_Module_gti" *) 
module design_1_microblaze_0_0_Shift_Logic_Module_gti
   (out,
    \EX_Op1_reg[24] ,
    in0,
    \Using_FPGA.Native );
  output out;
  output \EX_Op1_reg[24] ;
  input in0;
  input \Using_FPGA.Native ;

  (* RTL_KEEP = "true" *) wire sign_byte;
  (* RTL_KEEP = "true" *) wire sign_doublet;

  assign \EX_Op1_reg[24]  = sign_doublet;
  assign out = sign_byte;
  assign sign_byte = in0;
  assign sign_doublet = \Using_FPGA.Native ;
endmodule

(* ORIG_REF_NAME = "Zero_Detect_gti" *) 
module design_1_microblaze_0_0_Zero_Detect_gti
   (ex_op1_zero,
    ex_op1_cmp_equal,
    ex_op1_cmp_equal_n,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    lopt,
    lopt_1,
    lopt_2);
  output ex_op1_zero;
  input ex_op1_cmp_equal;
  input ex_op1_cmp_equal_n;
  input \Using_FPGA.Native ;
  input [29:0]\Using_FPGA.Native_0 ;
  output lopt;
  input lopt_1;
  input lopt_2;

  wire S;
  wire \S0_inferred__0/i__n_0 ;
  wire \S0_inferred__1/i__n_0 ;
  wire \S0_inferred__2/i__n_0 ;
  wire \S0_inferred__3/i__n_0 ;
  wire \Using_FPGA.Native ;
  wire [29:0]\Using_FPGA.Native_0 ;
  wire ex_op1_cmp_equal;
  wire ex_op1_cmp_equal_n;
  wire ex_op1_zero;
  wire \^lopt ;
  wire \^lopt_1 ;
  wire lopt_10;
  wire lopt_11;
  wire \^lopt_2 ;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire zero_CI_1;
  wire zero_CI_2;
  wire zero_CI_3;
  wire zero_CI_4;
  wire zero_CI_5;
  wire zero_CI_6;

  assign lopt = lopt_5;
  assign lopt_6 = lopt_1;
  assign lopt_7 = lopt_2;
  design_1_microblaze_0_0_MB_MUXCY_402 Part_Of_Zero_Carry_Start
       (.ex_op1_cmp_equal(ex_op1_cmp_equal),
        .lopt(\^lopt ),
        .lopt_1(ex_op1_cmp_equal_n),
        .lopt_10(lopt_11),
        .lopt_11(lopt_6),
        .lopt_12(lopt_7),
        .lopt_13(\Using_FPGA.Native ),
        .lopt_14(\S0_inferred__0/i__n_0 ),
        .lopt_15(\S0_inferred__1/i__n_0 ),
        .lopt_2(S),
        .lopt_3(\^lopt_1 ),
        .lopt_4(\S0_inferred__3/i__n_0 ),
        .lopt_5(\^lopt_2 ),
        .lopt_6(\S0_inferred__2/i__n_0 ),
        .lopt_7(lopt_8),
        .lopt_8(lopt_9),
        .lopt_9(lopt_10),
        .zero_CI_6(zero_CI_6));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \S0_inferred__0/i_ 
       (.I0(\Using_FPGA.Native_0 [0]),
        .I1(\Using_FPGA.Native_0 [5]),
        .I2(\Using_FPGA.Native_0 [3]),
        .I3(\Using_FPGA.Native_0 [4]),
        .I4(\Using_FPGA.Native_0 [1]),
        .I5(\Using_FPGA.Native_0 [2]),
        .O(\S0_inferred__0/i__n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \S0_inferred__1/i_ 
       (.I0(\Using_FPGA.Native_0 [6]),
        .I1(\Using_FPGA.Native_0 [11]),
        .I2(\Using_FPGA.Native_0 [9]),
        .I3(\Using_FPGA.Native_0 [10]),
        .I4(\Using_FPGA.Native_0 [7]),
        .I5(\Using_FPGA.Native_0 [8]),
        .O(\S0_inferred__1/i__n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \S0_inferred__2/i_ 
       (.I0(\Using_FPGA.Native_0 [12]),
        .I1(\Using_FPGA.Native_0 [17]),
        .I2(\Using_FPGA.Native_0 [15]),
        .I3(\Using_FPGA.Native_0 [16]),
        .I4(\Using_FPGA.Native_0 [13]),
        .I5(\Using_FPGA.Native_0 [14]),
        .O(\S0_inferred__2/i__n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \S0_inferred__3/i_ 
       (.I0(\Using_FPGA.Native_0 [18]),
        .I1(\Using_FPGA.Native_0 [23]),
        .I2(\Using_FPGA.Native_0 [21]),
        .I3(\Using_FPGA.Native_0 [22]),
        .I4(\Using_FPGA.Native_0 [19]),
        .I5(\Using_FPGA.Native_0 [20]),
        .O(\S0_inferred__3/i__n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \S0_inferred__4/i_ 
       (.I0(\Using_FPGA.Native_0 [24]),
        .I1(\Using_FPGA.Native_0 [29]),
        .I2(\Using_FPGA.Native_0 [27]),
        .I3(\Using_FPGA.Native_0 [28]),
        .I4(\Using_FPGA.Native_0 [25]),
        .I5(\Using_FPGA.Native_0 [26]),
        .O(S));
  design_1_microblaze_0_0_MB_MUXCY_403 \Zero_Detecting[1].I_Part_Of_Zero_Detect 
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .ex_op1_zero(ex_op1_zero),
        .lopt(lopt_4),
        .zero_CI_1(zero_CI_1));
  design_1_microblaze_0_0_MB_MUXCY_404 \Zero_Detecting[2].I_Part_Of_Zero_Detect 
       (.\Using_FPGA.Native_0 (\S0_inferred__0/i__n_0 ),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .lopt(lopt_3),
        .zero_CI_1(zero_CI_1),
        .zero_CI_2(zero_CI_2));
  design_1_microblaze_0_0_MB_MUXCY_405 \Zero_Detecting[3].I_Part_Of_Zero_Detect 
       (.\Using_FPGA.Native_0 (\S0_inferred__1/i__n_0 ),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .lopt(lopt_3),
        .lopt_1(\S0_inferred__0/i__n_0 ),
        .lopt_10(lopt_11),
        .lopt_2(lopt_4),
        .lopt_3(\Using_FPGA.Native ),
        .lopt_4(lopt_5),
        .lopt_5(lopt_6),
        .lopt_6(lopt_7),
        .lopt_7(lopt_8),
        .lopt_8(lopt_9),
        .lopt_9(lopt_10),
        .zero_CI_2(zero_CI_2),
        .zero_CI_3(zero_CI_3));
  design_1_microblaze_0_0_MB_MUXCY_406 \Zero_Detecting[4].I_Part_Of_Zero_Detect 
       (.\Using_FPGA.Native_0 (\S0_inferred__2/i__n_0 ),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .lopt(\^lopt_2 ),
        .zero_CI_3(zero_CI_3),
        .zero_CI_4(zero_CI_4));
  design_1_microblaze_0_0_MB_MUXCY_407 \Zero_Detecting[5].I_Part_Of_Zero_Detect 
       (.\Using_FPGA.Native_0 (\S0_inferred__3/i__n_0 ),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .lopt(\^lopt_1 ),
        .zero_CI_4(zero_CI_4),
        .zero_CI_5(zero_CI_5));
  design_1_microblaze_0_0_MB_MUXCY_408 \Zero_Detecting[6].I_Part_Of_Zero_Detect 
       (.S(S),
        .ex_op1_cmp_equal_n(ex_op1_cmp_equal_n),
        .lopt(\^lopt ),
        .zero_CI_5(zero_CI_5),
        .zero_CI_6(zero_CI_6));
endmodule

(* ORIG_REF_NAME = "address_hit" *) 
module design_1_microblaze_0_0_address_hit
   (Hit,
    single_Step_N_reg,
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ,
    Q,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ,
    Dbg_Reg_En,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ,
    force_stop_i,
    single_Step_N,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ,
    \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ,
    ex_Exception_Taken,
    mem_Exception_Taken,
    \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 ,
    Dbg_TDI,
    Address,
    Dbg_Clk);
  output Hit;
  output single_Step_N_reg;
  output \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ;
  input [1:0]Q;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ;
  input [0:7]Dbg_Reg_En;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ;
  input force_stop_i;
  input single_Step_N;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ;
  input \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ;
  input ex_Exception_Taken;
  input mem_Exception_Taken;
  input \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 ;
  input Dbg_TDI;
  input [0:31]Address;
  input Dbg_Clk;

  wire [0:31]Address;
  wire Dbg_Clk;
  wire [0:7]Dbg_Reg_En;
  wire Dbg_TDI;
  wire Hit;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ;
  wire \Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ;
  wire [1:0]Q;
  wire SRL16_MC15_1;
  wire SRL16_MC15_2;
  wire SRL16_MC15_3;
  wire SRL16_MC15_4;
  wire SRL16_MC15_5;
  wire SRL16_MC15_6;
  wire SRL16_MC15_7;
  wire SRL16_Sel_0;
  wire SRL16_Sel_1;
  wire SRL16_Sel_2;
  wire SRL16_Sel_3;
  wire SRL16_Sel_4;
  wire SRL16_Sel_5;
  wire SRL16_Sel_6;
  wire SRL16_Sel_7;
  wire carry_0;
  wire carry_1;
  wire carry_2;
  wire carry_3;
  wire carry_4;
  wire carry_5;
  wire carry_6;
  wire carry_7;
  wire ex_Exception_Taken;
  wire force_stop_i;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire mem_Exception_Taken;
  wire single_Step_N;
  wire single_Step_N_reg;
  wire which_pc__0;

  design_1_microblaze_0_0_MB_MUXCY \Compare[0].MUXCY_I 
       (.Q(Q[1]),
        .SRL16_Sel_7(SRL16_Sel_7),
        .carry_7(carry_7),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_13),
        .lopt_11(lopt_14),
        .lopt_12(lopt_15),
        .lopt_13(lopt_11),
        .lopt_14(lopt_9),
        .lopt_15(lopt_7),
        .lopt_16(lopt_16),
        .lopt_17(SRL16_Sel_0),
        .lopt_18(SRL16_Sel_1),
        .lopt_19(SRL16_Sel_2),
        .lopt_2(SRL16_Sel_6),
        .lopt_20(SRL16_Sel_3),
        .lopt_3(lopt_2),
        .lopt_4(lopt_3),
        .lopt_5(SRL16_Sel_5),
        .lopt_6(lopt_4),
        .lopt_7(lopt_5),
        .lopt_8(SRL16_Sel_4),
        .lopt_9(lopt_12));
  design_1_microblaze_0_0_MB_SRLC16E \Compare[0].SRLC16E_I 
       (.Address({Address[28],Address[29],Address[30],Address[31]}),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_Reg_En(Dbg_Reg_En),
        .SRL16_MC15_7(SRL16_MC15_7),
        .SRL16_Sel_7(SRL16_Sel_7),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_31 \Compare[1].MUXCY_I 
       (.SRL16_Sel_6(SRL16_Sel_6),
        .carry_6(carry_6),
        .carry_7(carry_7),
        .lopt(lopt),
        .lopt_1(lopt_1));
  design_1_microblaze_0_0_MB_SRLC16E_32 \Compare[1].SRLC16E_I 
       (.Address({Address[24],Address[25],Address[26],Address[27]}),
        .Dbg_Clk(Dbg_Clk),
        .SRL16_MC15_6(SRL16_MC15_6),
        .SRL16_MC15_7(SRL16_MC15_7),
        .SRL16_Sel_6(SRL16_Sel_6),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_33 \Compare[2].MUXCY_I 
       (.SRL16_Sel_5(SRL16_Sel_5),
        .carry_5(carry_5),
        .carry_6(carry_6),
        .lopt(lopt_2),
        .lopt_1(lopt_3));
  design_1_microblaze_0_0_MB_SRLC16E_34 \Compare[2].SRLC16E_I 
       (.Address({Address[20],Address[21],Address[22],Address[23]}),
        .Dbg_Clk(Dbg_Clk),
        .SRL16_MC15_5(SRL16_MC15_5),
        .SRL16_MC15_6(SRL16_MC15_6),
        .SRL16_Sel_5(SRL16_Sel_5),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_35 \Compare[3].MUXCY_I 
       (.SRL16_Sel_4(SRL16_Sel_4),
        .carry_4(carry_4),
        .carry_5(carry_5),
        .lopt(lopt_4),
        .lopt_1(lopt_5));
  design_1_microblaze_0_0_MB_SRLC16E_36 \Compare[3].SRLC16E_I 
       (.Address({Address[16],Address[17],Address[18],Address[19]}),
        .Dbg_Clk(Dbg_Clk),
        .SRL16_MC15_4(SRL16_MC15_4),
        .SRL16_MC15_5(SRL16_MC15_5),
        .SRL16_Sel_4(SRL16_Sel_4),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_37 \Compare[4].MUXCY_I 
       (.SRL16_Sel_3(SRL16_Sel_3),
        .carry_3(carry_3),
        .carry_4(carry_4),
        .lopt(lopt_6),
        .lopt_1(lopt_7),
        .lopt_10(lopt_13),
        .lopt_11(lopt_14),
        .lopt_12(lopt_15),
        .lopt_13(lopt_16),
        .lopt_2(SRL16_Sel_2),
        .lopt_3(lopt_8),
        .lopt_4(lopt_9),
        .lopt_5(SRL16_Sel_1),
        .lopt_6(lopt_10),
        .lopt_7(lopt_11),
        .lopt_8(SRL16_Sel_0),
        .lopt_9(lopt_12));
  design_1_microblaze_0_0_MB_SRLC16E_38 \Compare[4].SRLC16E_I 
       (.Address({Address[12],Address[13],Address[14],Address[15]}),
        .Dbg_Clk(Dbg_Clk),
        .SRL16_MC15_3(SRL16_MC15_3),
        .SRL16_MC15_4(SRL16_MC15_4),
        .SRL16_Sel_3(SRL16_Sel_3),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_39 \Compare[5].MUXCY_I 
       (.SRL16_Sel_2(SRL16_Sel_2),
        .carry_2(carry_2),
        .carry_3(carry_3),
        .lopt(lopt_6),
        .lopt_1(lopt_7));
  design_1_microblaze_0_0_MB_SRLC16E_40 \Compare[5].SRLC16E_I 
       (.Address({Address[8],Address[9],Address[10],Address[11]}),
        .Dbg_Clk(Dbg_Clk),
        .SRL16_MC15_2(SRL16_MC15_2),
        .SRL16_MC15_3(SRL16_MC15_3),
        .SRL16_Sel_2(SRL16_Sel_2),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_41 \Compare[6].MUXCY_I 
       (.SRL16_Sel_1(SRL16_Sel_1),
        .carry_1(carry_1),
        .carry_2(carry_2),
        .lopt(lopt_8),
        .lopt_1(lopt_9));
  design_1_microblaze_0_0_MB_SRLC16E_42 \Compare[6].SRLC16E_I 
       (.Address({Address[4],Address[5],Address[6],Address[7]}),
        .Dbg_Clk(Dbg_Clk),
        .SRL16_MC15_1(SRL16_MC15_1),
        .SRL16_MC15_2(SRL16_MC15_2),
        .SRL16_Sel_1(SRL16_Sel_1),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_43 \Compare[7].MUXCY_I 
       (.SRL16_Sel_0(SRL16_Sel_0),
        .carry_0(carry_0),
        .carry_1(carry_1),
        .lopt(lopt_10),
        .lopt_1(lopt_11));
  design_1_microblaze_0_0_MB_SRLC16E_44 \Compare[7].SRLC16E_I 
       (.Address({Address[0],Address[1],Address[2],Address[3]}),
        .Dbg_Clk(Dbg_Clk),
        .Dbg_TDI(Dbg_TDI),
        .SRL16_MC15_1(SRL16_MC15_1),
        .SRL16_Sel_0(SRL16_Sel_0),
        .which_pc__0(which_pc__0));
  design_1_microblaze_0_0_MB_MUXCY_45 \The_First_BreakPoints.MUXCY_Post 
       (.Hit(Hit),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2_0 (\Performance_Debug_Control.ex_dbg_pc_hit_i_i_2 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_0 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_1 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_2 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_3 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 (\Performance_Debug_Control.ex_dbg_pc_hit_i_reg_4 ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg (\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg ),
        .\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 (\Performance_Debug_Control.ex_dbg_pc_hit_single_step_reg_0 ),
        .Q(Q[0]),
        .carry_0(carry_0),
        .ex_Exception_Taken(ex_Exception_Taken),
        .force_stop_i(force_stop_i),
        .mem_Exception_Taken(mem_Exception_Taken),
        .single_Step_N(single_Step_N),
        .single_Step_N_reg(single_Step_N_reg));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and
   (of_PipeRun_carry_1,
    use_Reg_Neg_S_reg,
    of_PipeRun_carry_2,
    lopt,
    lopt_1);
  output of_PipeRun_carry_1;
  input use_Reg_Neg_S_reg;
  input of_PipeRun_carry_2;
  input lopt;
  output lopt_1;

  wire lopt;
  wire lopt_1;
  wire of_PipeRun_carry_1;
  wire of_PipeRun_carry_2;
  wire use_Reg_Neg_S_reg;

  design_1_microblaze_0_0_MB_MUXCY_111 MUXCY_I
       (.lopt(lopt),
        .lopt_1(lopt_1),
        .of_PipeRun_carry_1(of_PipeRun_carry_1),
        .of_PipeRun_carry_2(of_PipeRun_carry_2),
        .use_Reg_Neg_S_reg(use_Reg_Neg_S_reg));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_57
   (of_PipeRun_for_ce,
    ex_jump_nodelay_reg,
    of_read_imm_reg_ii_reg,
    wb_exception_i_reg,
    wb_exception_i_reg_0,
    of_PipeRun_carry_1,
    ex_jump_nodelay,
    ex_jump,
    ex_jump_nodelay_reg_0,
    IB_Ready,
    if_missed_fetch,
    of_read_imm_reg_ii,
    p_9_in,
    of_read_imm_reg_ii_reg_0,
    wb_exception,
    sync_reset,
    E,
    of_pause,
    lopt,
    lopt_1,
    lopt_2);
  output of_PipeRun_for_ce;
  output ex_jump_nodelay_reg;
  output of_read_imm_reg_ii_reg;
  output wb_exception_i_reg;
  output wb_exception_i_reg_0;
  input of_PipeRun_carry_1;
  input ex_jump_nodelay;
  input ex_jump;
  input ex_jump_nodelay_reg_0;
  input IB_Ready;
  input if_missed_fetch;
  input of_read_imm_reg_ii;
  input p_9_in;
  input of_read_imm_reg_ii_reg_0;
  input wb_exception;
  input sync_reset;
  input [0:0]E;
  input of_pause;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire [0:0]E;
  wire IB_Ready;
  wire ex_jump;
  wire ex_jump_nodelay;
  wire ex_jump_nodelay_reg;
  wire ex_jump_nodelay_reg_0;
  wire if_missed_fetch;
  wire lopt;
  wire lopt_1;
  wire lopt_2;
  wire of_PipeRun_carry_1;
  wire of_PipeRun_for_ce;
  wire of_pause;
  wire of_read_imm_reg_ii;
  wire of_read_imm_reg_ii_reg;
  wire of_read_imm_reg_ii_reg_0;
  wire p_9_in;
  wire sync_reset;
  wire wb_exception;
  wire wb_exception_i_reg;
  wire wb_exception_i_reg_0;

  design_1_microblaze_0_0_MB_MUXCY_110 MUXCY_I
       (.E(E),
        .IB_Ready(IB_Ready),
        .ex_jump(ex_jump),
        .ex_jump_nodelay(ex_jump_nodelay),
        .ex_jump_nodelay_reg(ex_jump_nodelay_reg),
        .ex_jump_nodelay_reg_0(ex_jump_nodelay_reg_0),
        .if_missed_fetch(if_missed_fetch),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_2(lopt_2),
        .of_PipeRun_carry_1(of_PipeRun_carry_1),
        .of_pause(of_pause),
        .of_pause_reg(of_PipeRun_for_ce),
        .of_read_imm_reg_ii(of_read_imm_reg_ii),
        .of_read_imm_reg_ii_reg(of_read_imm_reg_ii_reg),
        .of_read_imm_reg_ii_reg_0(of_read_imm_reg_ii_reg_0),
        .p_9_in(p_9_in),
        .sync_reset(sync_reset),
        .wb_exception(wb_exception),
        .wb_exception_i_reg(wb_exception_i_reg),
        .wb_exception_i_reg_0(wb_exception_i_reg_0));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_58
   (of_PipeRun_carry_10,
    \Using_FPGA.Native ,
    lopt,
    lopt_1,
    lopt_2);
  output of_PipeRun_carry_10;
  input \Using_FPGA.Native ;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire \Using_FPGA.Native ;
  wire lopt;
  wire lopt_1;
  wire lopt_2;
  wire of_PipeRun_carry_10;

  design_1_microblaze_0_0_MB_MUXCY_109 MUXCY_I
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_2(lopt_2),
        .of_PipeRun_carry_10(of_PipeRun_carry_10));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_59
   (of_PipeRun_carry_9,
    EX_MBAR_Stall__1,
    \Using_FPGA.Native ,
    of_PipeRun_carry_10,
    ex_mbar_sleep,
    ex_mbar_decode,
    ex_first_cycle,
    ex_mbar_stall_no_sleep_1,
    ex_jump_hold,
    lopt,
    lopt_1);
  output of_PipeRun_carry_9;
  output EX_MBAR_Stall__1;
  input \Using_FPGA.Native ;
  input of_PipeRun_carry_10;
  input ex_mbar_sleep;
  input ex_mbar_decode;
  input ex_first_cycle;
  input ex_mbar_stall_no_sleep_1;
  input ex_jump_hold;
  input lopt;
  output lopt_1;

  wire EX_MBAR_Stall__1;
  wire \Using_FPGA.Native ;
  wire ex_first_cycle;
  wire ex_jump_hold;
  wire ex_mbar_decode;
  wire ex_mbar_sleep;
  wire ex_mbar_stall_no_sleep_1;
  wire lopt;
  wire lopt_1;
  wire of_PipeRun_carry_10;
  wire of_PipeRun_carry_9;

  design_1_microblaze_0_0_MB_MUXCY_108 MUXCY_I
       (.EX_MBAR_Stall__1(EX_MBAR_Stall__1),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .ex_first_cycle(ex_first_cycle),
        .ex_jump_hold(ex_jump_hold),
        .ex_mbar_decode(ex_mbar_decode),
        .ex_mbar_sleep(ex_mbar_sleep),
        .ex_mbar_stall_no_sleep_1(ex_mbar_stall_no_sleep_1),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .of_PipeRun_carry_10(of_PipeRun_carry_10),
        .of_PipeRun_carry_9(of_PipeRun_carry_9));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_60
   (E,
    \wb_exception_kind_i_reg[28] ,
    in0,
    ex_Write_ICache_i_cmb,
    of_PipeRun_carry_9,
    Q,
    wb_exception,
    \mem_pc_i_reg[0] ,
    ex_Write_DCache_decode_reg,
    ex_write_dcache_instr,
    ex_Write_ICache_i,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14);
  output [0:0]E;
  output [0:0]\wb_exception_kind_i_reg[28] ;
  output in0;
  output ex_Write_ICache_i_cmb;
  input of_PipeRun_carry_9;
  input [1:0]Q;
  input wb_exception;
  input \mem_pc_i_reg[0] ;
  input ex_Write_DCache_decode_reg;
  input ex_write_dcache_instr;
  input ex_Write_ICache_i;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  input lopt_9;
  input lopt_10;
  input lopt_11;
  input lopt_12;
  output lopt_13;
  output lopt_14;

  wire [0:0]E;
  wire [1:0]Q;
  wire ex_Write_DCache_decode_reg;
  wire ex_Write_ICache_i;
  wire ex_Write_ICache_i_cmb;
  wire ex_write_dcache_instr;
  wire in0;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire \mem_pc_i_reg[0] ;
  wire of_PipeRun_carry_9;
  wire wb_exception;
  wire [0:0]\wb_exception_kind_i_reg[28] ;

  design_1_microblaze_0_0_MB_MUXCY_107 MUXCY_I
       (.Q(Q),
        .\Using_FPGA.Native_0 (E),
        .ex_Write_DCache_decode_reg(ex_Write_DCache_decode_reg),
        .ex_Write_ICache_i(ex_Write_ICache_i),
        .ex_Write_ICache_i_reg(ex_Write_ICache_i_cmb),
        .ex_write_dcache_instr(ex_write_dcache_instr),
        .in0(in0),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_2(lopt_2),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9),
        .\mem_pc_i_reg[0] (\mem_pc_i_reg[0] ),
        .of_PipeRun_carry_9(of_PipeRun_carry_9),
        .wb_exception(wb_exception),
        .\wb_exception_kind_i_reg[28] (\wb_exception_kind_i_reg[28] ));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_61
   (of_PipeRun_carry_7,
    \Using_FPGA.Native ,
    E,
    lopt,
    lopt_1);
  output of_PipeRun_carry_7;
  input \Using_FPGA.Native ;
  input [0:0]E;
  input lopt;
  output lopt_1;

  wire [0:0]E;
  wire \Using_FPGA.Native ;
  wire lopt;
  wire lopt_1;
  wire of_PipeRun_carry_7;

  design_1_microblaze_0_0_MB_MUXCY_106 MUXCY_I
       (.E(E),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .of_PipeRun_carry_7(of_PipeRun_carry_7));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_62
   (of_PipeRun_carry_6,
    A,
    of_PipeRun_carry_7,
    lopt,
    lopt_1);
  output of_PipeRun_carry_6;
  input A;
  input of_PipeRun_carry_7;
  input lopt;
  output lopt_1;

  wire A;
  wire lopt;
  wire lopt_1;
  wire of_PipeRun_carry_6;
  wire of_PipeRun_carry_7;

  design_1_microblaze_0_0_MB_MUXCY_105 MUXCY_I
       (.A(A),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .of_PipeRun_carry_6(of_PipeRun_carry_6),
        .of_PipeRun_carry_7(of_PipeRun_carry_7));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_63
   (of_PipeRun_carry_5,
    \Using_FPGA.Native ,
    of_PipeRun_carry_6,
    lopt,
    lopt_1);
  output of_PipeRun_carry_5;
  input \Using_FPGA.Native ;
  input of_PipeRun_carry_6;
  input lopt;
  output lopt_1;

  wire \Using_FPGA.Native ;
  wire lopt;
  wire lopt_1;
  wire of_PipeRun_carry_5;
  wire of_PipeRun_carry_6;

  design_1_microblaze_0_0_MB_MUXCY_104 MUXCY_I
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .of_PipeRun_carry_5(of_PipeRun_carry_5),
        .of_PipeRun_carry_6(of_PipeRun_carry_6));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_64
   (of_PipeRun_carry_4,
    \Using_FPGA.Native ,
    of_PipeRun_carry_5,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11);
  output of_PipeRun_carry_4;
  input \Using_FPGA.Native ;
  input of_PipeRun_carry_5;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  input lopt_10;
  input lopt_11;

  wire \Using_FPGA.Native ;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_2;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire of_PipeRun_carry_4;
  wire of_PipeRun_carry_5;

  design_1_microblaze_0_0_MB_MUXCY_103 MUXCY_I
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_2(lopt_2),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9),
        .of_PipeRun_carry_4(of_PipeRun_carry_4),
        .of_PipeRun_carry_5(of_PipeRun_carry_5));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_65
   (of_PipeRun_carry_3,
    \Using_FPGA.Native ,
    of_PipeRun_carry_4,
    lopt,
    lopt_1);
  output of_PipeRun_carry_3;
  input \Using_FPGA.Native ;
  input of_PipeRun_carry_4;
  input lopt;
  output lopt_1;

  wire \Using_FPGA.Native ;
  wire lopt;
  wire lopt_1;
  wire of_PipeRun_carry_3;
  wire of_PipeRun_carry_4;

  design_1_microblaze_0_0_MB_MUXCY_102 MUXCY_I
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .of_PipeRun_carry_3(of_PipeRun_carry_3),
        .of_PipeRun_carry_4(of_PipeRun_carry_4));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_66
   (of_PipeRun_carry_2,
    \Using_FPGA.Native ,
    of_PipeRun_carry_3,
    lopt,
    lopt_1);
  output of_PipeRun_carry_2;
  input \Using_FPGA.Native ;
  input of_PipeRun_carry_3;
  input lopt;
  output lopt_1;

  wire \Using_FPGA.Native ;
  wire lopt;
  wire lopt_1;
  wire of_PipeRun_carry_2;
  wire of_PipeRun_carry_3;

  design_1_microblaze_0_0_MB_MUXCY_101 MUXCY_I
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .of_PipeRun_carry_2(of_PipeRun_carry_2),
        .of_PipeRun_carry_3(of_PipeRun_carry_3));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_86
   (if_pc_incr_carry1,
    \Using_FPGA.Native ,
    if_pc_incr_carry0,
    lopt,
    lopt_1);
  output if_pc_incr_carry1;
  input \Using_FPGA.Native ;
  input if_pc_incr_carry0;
  input lopt;
  output lopt_1;

  wire \Using_FPGA.Native ;
  wire if_pc_incr_carry0;
  wire if_pc_incr_carry1;
  wire lopt;
  wire lopt_1;

  design_1_microblaze_0_0_MB_MUXCY_100 MUXCY_I
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .if_pc_incr_carry0(if_pc_incr_carry0),
        .if_pc_incr_carry1(if_pc_incr_carry1),
        .lopt(lopt),
        .lopt_1(lopt_1));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_87
   (if_pc_incr_carry0,
    if_missed_fetch,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20,
    lopt_21,
    lopt_22,
    lopt_23,
    lopt_24,
    lopt_25);
  output if_pc_incr_carry0;
  input if_missed_fetch;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  output lopt_13;
  output lopt_14;
  output lopt_15;
  output lopt_16;
  output lopt_17;
  input lopt_18;
  input lopt_19;
  input lopt_20;
  input lopt_21;
  input lopt_22;
  input lopt_23;
  input lopt_24;
  input lopt_25;

  wire if_missed_fetch;
  wire if_pc_incr_carry0;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;

  design_1_microblaze_0_0_MB_MUXCY_99 MUXCY_I
       (.if_missed_fetch(if_missed_fetch),
        .if_pc_incr_carry0(if_pc_incr_carry0),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_20(lopt_20),
        .lopt_21(lopt_21),
        .lopt_22(lopt_22),
        .lopt_23(lopt_23),
        .lopt_24(lopt_24),
        .lopt_25(lopt_25),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_88
   (CI,
    if_fetch_for_timing_optimization1,
    if_pc_incr_carry1,
    lopt,
    lopt_1);
  output CI;
  input if_fetch_for_timing_optimization1;
  input if_pc_incr_carry1;
  input lopt;
  output lopt_1;

  wire CI;
  wire if_fetch_for_timing_optimization1;
  wire if_pc_incr_carry1;
  wire lopt;
  wire lopt_1;

  design_1_microblaze_0_0_MB_MUXCY_98 MUXCY_I
       (.CI(CI),
        .if_fetch_for_timing_optimization1(if_fetch_for_timing_optimization1),
        .if_pc_incr_carry1(if_pc_incr_carry1),
        .lopt(lopt),
        .lopt_1(lopt_1));
endmodule

(* ORIG_REF_NAME = "carry_and" *) 
module design_1_microblaze_0_0_carry_and_89
   (\Using_FPGA.Native ,
    mem_valid_reg,
    wb_valid_reg,
    wb_gpr_write_dbg0,
    wb_gpr_write_i0,
    mem_wait_on_ready_N,
    mem_valid_instr,
    mem_exception_from_ex,
    mem_valid_reg_0,
    E,
    flush_pipe,
    wb_valid_reg_0,
    wb_valid_reg_1,
    sync_reset,
    wb_exception,
    mem_gpr_write_dbg,
    mem_gpr_write,
    lopt,
    lopt_1,
    lopt_2);
  output \Using_FPGA.Native ;
  output mem_valid_reg;
  output wb_valid_reg;
  output wb_gpr_write_dbg0;
  output wb_gpr_write_i0;
  input mem_wait_on_ready_N;
  input mem_valid_instr;
  input mem_exception_from_ex;
  input mem_valid_reg_0;
  input [0:0]E;
  input flush_pipe;
  input wb_valid_reg_0;
  input [0:0]wb_valid_reg_1;
  input sync_reset;
  input wb_exception;
  input mem_gpr_write_dbg;
  input mem_gpr_write;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire [0:0]E;
  wire \Using_FPGA.Native ;
  wire flush_pipe;
  wire lopt;
  wire lopt_1;
  wire lopt_2;
  wire mem_exception_from_ex;
  wire mem_gpr_write;
  wire mem_gpr_write_dbg;
  wire mem_valid_instr;
  wire mem_valid_reg;
  wire mem_valid_reg_0;
  wire mem_wait_on_ready_N;
  wire sync_reset;
  wire wb_exception;
  wire wb_gpr_write_dbg0;
  wire wb_gpr_write_i0;
  wire wb_valid_reg;
  wire wb_valid_reg_0;
  wire [0:0]wb_valid_reg_1;

  design_1_microblaze_0_0_MB_MUXCY_91 MUXCY_I
       (.E(E),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .flush_pipe(flush_pipe),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_2(lopt_2),
        .mem_exception_from_ex(mem_exception_from_ex),
        .mem_gpr_write(mem_gpr_write),
        .mem_gpr_write_dbg(mem_gpr_write_dbg),
        .mem_valid_instr(mem_valid_instr),
        .mem_valid_reg(mem_valid_reg),
        .mem_valid_reg_0(mem_valid_reg_0),
        .mem_wait_on_ready_N(mem_wait_on_ready_N),
        .sync_reset(sync_reset),
        .wb_exception(wb_exception),
        .wb_gpr_write_dbg0(wb_gpr_write_dbg0),
        .wb_gpr_write_i0(wb_gpr_write_i0),
        .wb_valid_reg(wb_valid_reg),
        .wb_valid_reg_0(wb_valid_reg_0),
        .wb_valid_reg_1(wb_valid_reg_1));
endmodule

(* ORIG_REF_NAME = "carry_or" *) 
module design_1_microblaze_0_0_carry_or
   (mem_wait_on_ready_N,
    MEM_DataBus_Ready,
    mem_load_store_access,
    mem_Write_DCache,
    mem_valid_instr,
    lopt,
    lopt_1,
    lopt_2,
    lopt_3,
    lopt_4,
    lopt_5,
    lopt_6,
    lopt_7,
    lopt_8,
    lopt_9,
    lopt_10,
    lopt_11,
    lopt_12,
    lopt_13,
    lopt_14,
    lopt_15,
    lopt_16,
    lopt_17,
    lopt_18,
    lopt_19,
    lopt_20);
  output mem_wait_on_ready_N;
  input MEM_DataBus_Ready;
  input mem_load_store_access;
  input mem_Write_DCache;
  input mem_valid_instr;
  output lopt;
  input lopt_1;
  input lopt_2;
  output lopt_3;
  input lopt_4;
  input lopt_5;
  output lopt_6;
  input lopt_7;
  input lopt_8;
  output lopt_9;
  output lopt_10;
  output lopt_11;
  output lopt_12;
  input lopt_13;
  input lopt_14;
  input lopt_15;
  input lopt_16;
  input lopt_17;
  input lopt_18;
  input lopt_19;
  input lopt_20;

  wire MEM_DataBus_Ready;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_20;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire mem_Write_DCache;
  wire mem_load_store_access;
  wire mem_valid_instr;
  wire mem_wait_on_ready_N;

  design_1_microblaze_0_0_MB_MUXCY_90 MUXCY_I
       (.MEM_DataBus_Ready(MEM_DataBus_Ready),
        .lopt(lopt),
        .lopt_1(lopt_1),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_12),
        .lopt_13(lopt_13),
        .lopt_14(lopt_14),
        .lopt_15(lopt_15),
        .lopt_16(lopt_16),
        .lopt_17(lopt_17),
        .lopt_18(lopt_18),
        .lopt_19(lopt_19),
        .lopt_2(lopt_2),
        .lopt_20(lopt_20),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(lopt_5),
        .lopt_6(lopt_6),
        .lopt_7(lopt_7),
        .lopt_8(lopt_8),
        .lopt_9(lopt_9),
        .mem_Write_DCache(mem_Write_DCache),
        .mem_load_store_access(mem_load_store_access),
        .mem_valid_instr(mem_valid_instr),
        .mem_wait_on_ready_N(mem_wait_on_ready_N));
endmodule

(* ORIG_REF_NAME = "exception_registers_gti" *) 
module design_1_microblaze_0_0_exception_registers_gti
   (DI,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    \Using_FPGA.Native_2 ,
    \Using_FPGA.Native_3 ,
    \Using_FPGA.Native_4 ,
    \Using_FPGA.Native_5 ,
    \Using_FPGA.Native_6 ,
    \Using_FPGA.Native_7 ,
    \Using_FPGA.Native_8 ,
    \Using_FPGA.Native_9 ,
    \Using_FPGA.Native_10 ,
    \Using_FPGA.Native_11 ,
    \Using_FPGA.Native_12 ,
    \Using_FPGA.Native_13 ,
    \Using_FPGA.Native_14 ,
    \Using_FPGA.Native_15 ,
    \Using_FPGA.Native_16 ,
    \Using_FPGA.Native_17 ,
    \Using_FPGA.Native_18 ,
    \Using_FPGA.Native_19 ,
    \Using_FPGA.Native_20 ,
    \Using_FPGA.Native_21 ,
    \Using_FPGA.Native_22 ,
    \Using_FPGA.Native_23 ,
    \Using_FPGA.Native_24 ,
    \Using_FPGA.Native_25 ,
    \Using_FPGA.Native_26 ,
    \Using_FPGA.Native_27 ,
    \Using_FPGA.Native_28 ,
    \Using_FPGA.Native_29 ,
    \Using_FPGA.Native_30 ,
    wb_gpr_write_dbg_reg,
    \Using_FPGA.Native_31 ,
    \Using_FPGA.Native_32 ,
    \Using_FPGA.Native_33 ,
    \Using_FPGA.Native_34 ,
    Clk,
    I1_1,
    wb_gpr_wr_dbg,
    \data_rd_reg_reg[23] ,
    \data_rd_reg_reg[23]_0 ,
    \LOCKSTEP_Out_reg[3030] ,
    wb_byte_access,
    \LOCKSTEP_Out_reg[3024] ,
    Q,
    \LOCKSTEP_Out_reg[3026] ,
    \LOCKSTEP_Out_reg[3028] ,
    \LOCKSTEP_Out_reg[3030]_0 ,
    \LOCKSTEP_Out_reg[3029] ,
    \LOCKSTEP_Out_reg[3027] ,
    \LOCKSTEP_Out_reg[3025] ,
    \LOCKSTEP_Out_reg[3023] );
  output DI;
  output \Using_FPGA.Native ;
  output \Using_FPGA.Native_0 ;
  output \Using_FPGA.Native_1 ;
  output \Using_FPGA.Native_2 ;
  output \Using_FPGA.Native_3 ;
  output \Using_FPGA.Native_4 ;
  output \Using_FPGA.Native_5 ;
  output \Using_FPGA.Native_6 ;
  output \Using_FPGA.Native_7 ;
  output \Using_FPGA.Native_8 ;
  output \Using_FPGA.Native_9 ;
  output \Using_FPGA.Native_10 ;
  output \Using_FPGA.Native_11 ;
  output \Using_FPGA.Native_12 ;
  output \Using_FPGA.Native_13 ;
  output \Using_FPGA.Native_14 ;
  output \Using_FPGA.Native_15 ;
  output \Using_FPGA.Native_16 ;
  output \Using_FPGA.Native_17 ;
  output \Using_FPGA.Native_18 ;
  output \Using_FPGA.Native_19 ;
  output \Using_FPGA.Native_20 ;
  output \Using_FPGA.Native_21 ;
  output \Using_FPGA.Native_22 ;
  output \Using_FPGA.Native_23 ;
  output \Using_FPGA.Native_24 ;
  output \Using_FPGA.Native_25 ;
  output \Using_FPGA.Native_26 ;
  output \Using_FPGA.Native_27 ;
  output \Using_FPGA.Native_28 ;
  output [8:0]\Using_FPGA.Native_29 ;
  output [23:0]\Using_FPGA.Native_30 ;
  output [7:0]wb_gpr_write_dbg_reg;
  input [0:0]\Using_FPGA.Native_31 ;
  input [31:0]\Using_FPGA.Native_32 ;
  input \Using_FPGA.Native_33 ;
  input \Using_FPGA.Native_34 ;
  input Clk;
  input I1_1;
  input wb_gpr_wr_dbg;
  input \data_rd_reg_reg[23] ;
  input \data_rd_reg_reg[23]_0 ;
  input \LOCKSTEP_Out_reg[3030] ;
  input wb_byte_access;
  input \LOCKSTEP_Out_reg[3024] ;
  input [7:0]Q;
  input \LOCKSTEP_Out_reg[3026] ;
  input \LOCKSTEP_Out_reg[3028] ;
  input \LOCKSTEP_Out_reg[3030]_0 ;
  input \LOCKSTEP_Out_reg[3029] ;
  input \LOCKSTEP_Out_reg[3027] ;
  input \LOCKSTEP_Out_reg[3025] ;
  input \LOCKSTEP_Out_reg[3023] ;

  wire Clk;
  wire DI;
  wire I1_1;
  wire \LOCKSTEP_Out_reg[3023] ;
  wire \LOCKSTEP_Out_reg[3024] ;
  wire \LOCKSTEP_Out_reg[3025] ;
  wire \LOCKSTEP_Out_reg[3026] ;
  wire \LOCKSTEP_Out_reg[3027] ;
  wire \LOCKSTEP_Out_reg[3028] ;
  wire \LOCKSTEP_Out_reg[3029] ;
  wire \LOCKSTEP_Out_reg[3030] ;
  wire \LOCKSTEP_Out_reg[3030]_0 ;
  wire O5;
  wire [7:0]Q;
  wire \Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_10 ;
  wire \Using_FPGA.Native_11 ;
  wire \Using_FPGA.Native_12 ;
  wire \Using_FPGA.Native_13 ;
  wire \Using_FPGA.Native_14 ;
  wire \Using_FPGA.Native_15 ;
  wire \Using_FPGA.Native_16 ;
  wire \Using_FPGA.Native_17 ;
  wire \Using_FPGA.Native_18 ;
  wire \Using_FPGA.Native_19 ;
  wire \Using_FPGA.Native_2 ;
  wire \Using_FPGA.Native_20 ;
  wire \Using_FPGA.Native_21 ;
  wire \Using_FPGA.Native_22 ;
  wire \Using_FPGA.Native_23 ;
  wire \Using_FPGA.Native_24 ;
  wire \Using_FPGA.Native_25 ;
  wire \Using_FPGA.Native_26 ;
  wire \Using_FPGA.Native_27 ;
  wire \Using_FPGA.Native_28 ;
  wire [8:0]\Using_FPGA.Native_29 ;
  wire \Using_FPGA.Native_3 ;
  wire [23:0]\Using_FPGA.Native_30 ;
  wire [0:0]\Using_FPGA.Native_31 ;
  wire [31:0]\Using_FPGA.Native_32 ;
  wire \Using_FPGA.Native_33 ;
  wire \Using_FPGA.Native_34 ;
  wire \Using_FPGA.Native_4 ;
  wire \Using_FPGA.Native_5 ;
  wire \Using_FPGA.Native_6 ;
  wire \Using_FPGA.Native_7 ;
  wire \Using_FPGA.Native_8 ;
  wire \Using_FPGA.Native_9 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB_n_0 ;
  wire \Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0 ;
  wire addr_AddSub_0;
  wire addr_AddSub_1;
  wire addr_AddSub_10;
  wire addr_AddSub_11;
  wire addr_AddSub_12;
  wire addr_AddSub_13;
  wire addr_AddSub_14;
  wire addr_AddSub_15;
  wire addr_AddSub_16;
  wire addr_AddSub_17;
  wire addr_AddSub_18;
  wire addr_AddSub_19;
  wire addr_AddSub_2;
  wire addr_AddSub_20;
  wire addr_AddSub_21;
  wire addr_AddSub_22;
  wire addr_AddSub_23;
  wire addr_AddSub_24;
  wire addr_AddSub_25;
  wire addr_AddSub_26;
  wire addr_AddSub_27;
  wire addr_AddSub_28;
  wire addr_AddSub_29;
  wire addr_AddSub_3;
  wire addr_AddSub_30;
  wire addr_AddSub_31;
  wire addr_AddSub_4;
  wire addr_AddSub_5;
  wire addr_AddSub_6;
  wire addr_AddSub_7;
  wire addr_AddSub_8;
  wire addr_AddSub_9;
  wire carry_0;
  wire carry_1;
  wire carry_10;
  wire carry_11;
  wire carry_12;
  wire carry_13;
  wire carry_14;
  wire carry_15;
  wire carry_16;
  wire carry_17;
  wire carry_18;
  wire carry_19;
  wire carry_2;
  wire carry_20;
  wire carry_21;
  wire carry_22;
  wire carry_23;
  wire carry_24;
  wire carry_25;
  wire carry_26;
  wire carry_27;
  wire carry_28;
  wire carry_29;
  wire carry_3;
  wire carry_30;
  wire carry_31;
  wire carry_4;
  wire carry_5;
  wire carry_6;
  wire carry_7;
  wire carry_8;
  wire carry_9;
  wire \data_rd_reg_reg[23] ;
  wire \data_rd_reg_reg[23]_0 ;
  wire lopt;
  wire lopt_1;
  wire lopt_10;
  wire lopt_11;
  wire lopt_12;
  wire lopt_13;
  wire lopt_14;
  wire lopt_15;
  wire lopt_16;
  wire lopt_17;
  wire lopt_18;
  wire lopt_19;
  wire lopt_2;
  wire lopt_20;
  wire lopt_21;
  wire lopt_22;
  wire lopt_23;
  wire lopt_24;
  wire lopt_25;
  wire lopt_26;
  wire lopt_27;
  wire lopt_28;
  wire lopt_29;
  wire lopt_3;
  wire lopt_30;
  wire lopt_31;
  wire lopt_32;
  wire lopt_33;
  wire lopt_34;
  wire lopt_35;
  wire lopt_36;
  wire lopt_37;
  wire lopt_38;
  wire lopt_39;
  wire lopt_4;
  wire lopt_40;
  wire lopt_41;
  wire lopt_42;
  wire lopt_43;
  wire lopt_44;
  wire lopt_45;
  wire lopt_46;
  wire lopt_47;
  wire lopt_48;
  wire lopt_49;
  wire lopt_5;
  wire lopt_50;
  wire lopt_51;
  wire lopt_52;
  wire lopt_53;
  wire lopt_54;
  wire lopt_55;
  wire lopt_56;
  wire lopt_57;
  wire lopt_58;
  wire lopt_59;
  wire lopt_6;
  wire lopt_60;
  wire lopt_61;
  wire lopt_62;
  wire lopt_63;
  wire lopt_64;
  wire lopt_65;
  wire lopt_66;
  wire lopt_67;
  wire lopt_68;
  wire lopt_69;
  wire lopt_7;
  wire lopt_70;
  wire lopt_71;
  wire lopt_72;
  wire lopt_73;
  wire lopt_74;
  wire lopt_75;
  wire lopt_76;
  wire lopt_77;
  wire lopt_78;
  wire lopt_79;
  wire lopt_8;
  wire lopt_9;
  wire wb_byte_access;
  wire wb_gpr_wr_dbg;
  wire [7:0]wb_gpr_write_dbg_reg;

  design_1_microblaze_0_0_MB_MUXCY_307 CarryIn_MUXCY
       (.CI(carry_0),
        .\Using_FPGA.Native_I2 (\Using_FPGA.Native_31 ),
        .lopt(lopt),
        .lopt_1(DI),
        .lopt_10(lopt_4),
        .lopt_11(lopt_5),
        .lopt_12(lopt_48),
        .lopt_13(lopt_49),
        .lopt_14(lopt_50),
        .lopt_15(lopt_51),
        .lopt_16(lopt_52),
        .lopt_17(lopt_53),
        .lopt_18(lopt_54),
        .lopt_19(lopt_55),
        .lopt_2(addr_AddSub_0),
        .lopt_20(\Using_FPGA.Native_4 ),
        .lopt_21(\Using_FPGA.Native_3 ),
        .lopt_22(\Using_FPGA.Native_2 ),
        .lopt_23(\Using_FPGA.Native_1 ),
        .lopt_24(addr_AddSub_6),
        .lopt_25(addr_AddSub_5),
        .lopt_26(addr_AddSub_4),
        .lopt_27(addr_AddSub_3),
        .lopt_3(lopt_1),
        .lopt_4(\Using_FPGA.Native ),
        .lopt_5(addr_AddSub_1),
        .lopt_6(lopt_2),
        .lopt_7(\Using_FPGA.Native_0 ),
        .lopt_8(addr_AddSub_2),
        .lopt_9(lopt_3));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5 \Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB 
       (.\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_29 [8]),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [31]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ),
        .addr_AddSub_31(addr_AddSub_31));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_308 \Using_FPGA_LUT6.Gen_Ret_Addr[0].MUXCY_XOR_I 
       (.LO(carry_31),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [23]),
        .addr_AddSub_31(addr_AddSub_31));
  design_1_microblaze_0_0_MB_FDE \Using_FPGA_LUT6.Gen_Ret_Addr[0].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_29 [8]),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_309 \Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB 
       (.S(addr_AddSub_21),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_19 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [21]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_310 \Using_FPGA_LUT6.Gen_Ret_Addr[10].MUXCY_XOR_I 
       (.LO(carry_22),
        .\LOCKSTEP_Out_reg[3017] (carry_21),
        .S(addr_AddSub_21),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [13]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_19 ),
        .lopt(lopt_31),
        .lopt_1(lopt_34));
  design_1_microblaze_0_0_MB_FDE_311 \Using_FPGA_LUT6.Gen_Ret_Addr[10].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_19 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_312 \Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB 
       (.S(addr_AddSub_20),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_18 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [20]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_313 \Using_FPGA_LUT6.Gen_Ret_Addr[11].MUXCY_XOR_I 
       (.LO(carry_21),
        .\LOCKSTEP_Out_reg[3018] (carry_20),
        .S(addr_AddSub_20),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [12]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_18 ),
        .lopt(lopt_30),
        .lopt_1(lopt_33));
  design_1_microblaze_0_0_MB_FDE_314 \Using_FPGA_LUT6.Gen_Ret_Addr[11].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_18 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_315 \Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB 
       (.S(addr_AddSub_19),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_17 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [19]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_316 \Using_FPGA_LUT6.Gen_Ret_Addr[12].MUXCY_XOR_I 
       (.LO(carry_20),
        .\LOCKSTEP_Out_reg[3019] (carry_19),
        .S(addr_AddSub_19),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [11]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_17 ),
        .lopt(lopt_30),
        .lopt_1(\Using_FPGA.Native_18 ),
        .lopt_10(lopt_34),
        .lopt_11(lopt_35),
        .lopt_12(lopt_64),
        .lopt_13(lopt_65),
        .lopt_14(lopt_66),
        .lopt_15(lopt_67),
        .lopt_16(lopt_68),
        .lopt_17(lopt_69),
        .lopt_18(lopt_70),
        .lopt_19(lopt_71),
        .lopt_2(addr_AddSub_20),
        .lopt_3(lopt_31),
        .lopt_4(\Using_FPGA.Native_19 ),
        .lopt_5(addr_AddSub_21),
        .lopt_6(lopt_32),
        .lopt_7(\Using_FPGA.Native_20 ),
        .lopt_8(addr_AddSub_22),
        .lopt_9(lopt_33));
  design_1_microblaze_0_0_MB_FDE_317 \Using_FPGA_LUT6.Gen_Ret_Addr[12].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_17 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_318 \Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB 
       (.S(addr_AddSub_18),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_16 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [18]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_319 \Using_FPGA_LUT6.Gen_Ret_Addr[13].MUXCY_XOR_I 
       (.LO(carry_19),
        .\LOCKSTEP_Out_reg[3020] (carry_18),
        .S(addr_AddSub_18),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [10]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_16 ),
        .lopt(lopt_26),
        .lopt_1(lopt_29));
  design_1_microblaze_0_0_MB_FDE_320 \Using_FPGA_LUT6.Gen_Ret_Addr[13].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_16 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_321 \Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB 
       (.S(addr_AddSub_17),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_15 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [17]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_322 \Using_FPGA_LUT6.Gen_Ret_Addr[14].MUXCY_XOR_I 
       (.LO(carry_18),
        .\LOCKSTEP_Out_reg[3021] (carry_17),
        .S(addr_AddSub_17),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [9]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_15 ),
        .lopt(lopt_25),
        .lopt_1(lopt_28));
  design_1_microblaze_0_0_MB_FDE_323 \Using_FPGA_LUT6.Gen_Ret_Addr[14].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_15 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_324 \Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB 
       (.S(addr_AddSub_16),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_14 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [16]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_325 \Using_FPGA_LUT6.Gen_Ret_Addr[15].MUXCY_XOR_I 
       (.LO(carry_17),
        .\LOCKSTEP_Out_reg[3022] (carry_16),
        .S(addr_AddSub_16),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [8]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_14 ),
        .lopt(lopt_24),
        .lopt_1(lopt_27));
  design_1_microblaze_0_0_MB_FDE_326 \Using_FPGA_LUT6.Gen_Ret_Addr[15].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_14 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_327 \Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_13 ),
        .S(addr_AddSub_15),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [15]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_328 \Using_FPGA_LUT6.Gen_Ret_Addr[16].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_13 ),
        .LO(carry_16),
        .\LOCKSTEP_Out_reg[3023] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3023]_0 (\LOCKSTEP_Out_reg[3023] ),
        .\LOCKSTEP_Out_reg[3023]_1 (carry_15),
        .Q(Q[7]),
        .S(addr_AddSub_15),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [7]),
        .\data_rd_reg_reg[16] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[16]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_24),
        .lopt_1(\Using_FPGA.Native_14 ),
        .lopt_10(lopt_28),
        .lopt_11(lopt_29),
        .lopt_12(lopt_64),
        .lopt_13(lopt_65),
        .lopt_14(lopt_66),
        .lopt_15(lopt_67),
        .lopt_16(lopt_68),
        .lopt_17(lopt_69),
        .lopt_18(lopt_70),
        .lopt_19(lopt_71),
        .lopt_2(addr_AddSub_16),
        .lopt_20(\Using_FPGA.Native_20 ),
        .lopt_21(\Using_FPGA.Native_19 ),
        .lopt_22(\Using_FPGA.Native_18 ),
        .lopt_23(\Using_FPGA.Native_17 ),
        .lopt_24(addr_AddSub_22),
        .lopt_25(addr_AddSub_21),
        .lopt_26(addr_AddSub_20),
        .lopt_27(addr_AddSub_19),
        .lopt_3(lopt_25),
        .lopt_4(\Using_FPGA.Native_15 ),
        .lopt_5(addr_AddSub_17),
        .lopt_6(lopt_26),
        .lopt_7(\Using_FPGA.Native_16 ),
        .lopt_8(addr_AddSub_18),
        .lopt_9(lopt_27),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[7]));
  design_1_microblaze_0_0_MB_FDE_329 \Using_FPGA_LUT6.Gen_Ret_Addr[16].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_13 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_330 \Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_12 ),
        .S(addr_AddSub_14),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [14]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_331 \Using_FPGA_LUT6.Gen_Ret_Addr[17].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_12 ),
        .LO(carry_15),
        .\LOCKSTEP_Out_reg[3024] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3024]_0 (\LOCKSTEP_Out_reg[3024] ),
        .\LOCKSTEP_Out_reg[3024]_1 (carry_14),
        .Q(Q[6]),
        .S(addr_AddSub_14),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [6]),
        .\data_rd_reg_reg[17] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[17]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_20),
        .lopt_1(lopt_23),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[6]));
  design_1_microblaze_0_0_MB_FDE_332 \Using_FPGA_LUT6.Gen_Ret_Addr[17].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_12 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_333 \Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_11 ),
        .S(addr_AddSub_13),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [13]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_334 \Using_FPGA_LUT6.Gen_Ret_Addr[18].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_11 ),
        .LO(carry_14),
        .\LOCKSTEP_Out_reg[3025] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3025]_0 (\LOCKSTEP_Out_reg[3025] ),
        .\LOCKSTEP_Out_reg[3025]_1 (carry_13),
        .Q(Q[5]),
        .S(addr_AddSub_13),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [5]),
        .\data_rd_reg_reg[18] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[18]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_19),
        .lopt_1(lopt_22),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[5]));
  design_1_microblaze_0_0_MB_FDE_335 \Using_FPGA_LUT6.Gen_Ret_Addr[18].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_11 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_336 \Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_10 ),
        .S(addr_AddSub_12),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [12]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_337 \Using_FPGA_LUT6.Gen_Ret_Addr[19].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_10 ),
        .LO(carry_13),
        .\LOCKSTEP_Out_reg[3026] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3026]_0 (\LOCKSTEP_Out_reg[3026] ),
        .\LOCKSTEP_Out_reg[3026]_1 (carry_12),
        .Q(Q[4]),
        .S(addr_AddSub_12),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [4]),
        .\data_rd_reg_reg[19] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[19]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_18),
        .lopt_1(lopt_21),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[4]));
  design_1_microblaze_0_0_MB_FDE_338 \Using_FPGA_LUT6.Gen_Ret_Addr[19].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_10 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_339 \Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB 
       (.S(addr_AddSub_30),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_28 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [30]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_340 \Using_FPGA_LUT6.Gen_Ret_Addr[1].MUXCY_XOR_I 
       (.LO(carry_31),
        .\LOCKSTEP_Out_reg[3008] (carry_30),
        .S(addr_AddSub_30),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [22]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_28 ),
        .lopt(lopt_44),
        .lopt_1(lopt_47));
  design_1_microblaze_0_0_MB_FDE_341 \Using_FPGA_LUT6.Gen_Ret_Addr[1].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_28 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_342 \Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_9 ),
        .S(addr_AddSub_11),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [11]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_343 \Using_FPGA_LUT6.Gen_Ret_Addr[20].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_9 ),
        .LO(carry_12),
        .\LOCKSTEP_Out_reg[3027] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3027]_0 (\LOCKSTEP_Out_reg[3027] ),
        .\LOCKSTEP_Out_reg[3027]_1 (carry_11),
        .Q(Q[3]),
        .S(addr_AddSub_11),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [3]),
        .\data_rd_reg_reg[20] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[20]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_18),
        .lopt_1(\Using_FPGA.Native_10 ),
        .lopt_10(lopt_22),
        .lopt_11(lopt_23),
        .lopt_12(lopt_56),
        .lopt_13(lopt_57),
        .lopt_14(lopt_58),
        .lopt_15(lopt_59),
        .lopt_16(lopt_60),
        .lopt_17(lopt_61),
        .lopt_18(lopt_62),
        .lopt_19(lopt_63),
        .lopt_2(addr_AddSub_12),
        .lopt_3(lopt_19),
        .lopt_4(\Using_FPGA.Native_11 ),
        .lopt_5(addr_AddSub_13),
        .lopt_6(lopt_20),
        .lopt_7(\Using_FPGA.Native_12 ),
        .lopt_8(addr_AddSub_14),
        .lopt_9(lopt_21),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[3]));
  design_1_microblaze_0_0_MB_FDE_344 \Using_FPGA_LUT6.Gen_Ret_Addr[20].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_9 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_345 \Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_8 ),
        .S(addr_AddSub_10),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [10]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_346 \Using_FPGA_LUT6.Gen_Ret_Addr[21].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_8 ),
        .LO(carry_11),
        .\LOCKSTEP_Out_reg[3028] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3028]_0 (\LOCKSTEP_Out_reg[3028] ),
        .\LOCKSTEP_Out_reg[3028]_1 (carry_10),
        .Q(Q[2]),
        .S(addr_AddSub_10),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [2]),
        .\data_rd_reg_reg[21] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[21]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_14),
        .lopt_1(lopt_17),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[2]));
  design_1_microblaze_0_0_MB_FDE_347 \Using_FPGA_LUT6.Gen_Ret_Addr[21].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_8 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_348 \Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_7 ),
        .S(addr_AddSub_9),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [9]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_349 \Using_FPGA_LUT6.Gen_Ret_Addr[22].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_7 ),
        .LO(carry_10),
        .\LOCKSTEP_Out_reg[3029] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3029]_0 (\LOCKSTEP_Out_reg[3029] ),
        .\LOCKSTEP_Out_reg[3029]_1 (carry_9),
        .Q(Q[1]),
        .S(addr_AddSub_9),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [1]),
        .\data_rd_reg_reg[22] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[22]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_13),
        .lopt_1(lopt_16),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[1]));
  design_1_microblaze_0_0_MB_FDE_350 \Using_FPGA_LUT6.Gen_Ret_Addr[22].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_7 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_351 \Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB 
       (.DI(\Using_FPGA.Native_6 ),
        .S(addr_AddSub_8),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_32 [8]),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_352 \Using_FPGA_LUT6.Gen_Ret_Addr[23].MUXCY_XOR_I 
       (.DI(\Using_FPGA.Native_6 ),
        .LO(carry_9),
        .\LOCKSTEP_Out_reg[3030] (\LOCKSTEP_Out_reg[3030] ),
        .\LOCKSTEP_Out_reg[3030]_0 (\LOCKSTEP_Out_reg[3030]_0 ),
        .\LOCKSTEP_Out_reg[3030]_1 (carry_8),
        .Q(Q[0]),
        .S(addr_AddSub_8),
        .WB_Byte_Access_reg(\Using_FPGA.Native_29 [0]),
        .\data_rd_reg_reg[23] (\data_rd_reg_reg[23] ),
        .\data_rd_reg_reg[23]_0 (\data_rd_reg_reg[23]_0 ),
        .lopt(lopt_12),
        .lopt_1(lopt_15),
        .wb_byte_access(wb_byte_access),
        .wb_gpr_wr_dbg(wb_gpr_wr_dbg),
        .wb_gpr_write_dbg_reg(wb_gpr_write_dbg_reg[0]));
  design_1_microblaze_0_0_MB_FDE_353 \Using_FPGA_LUT6.Gen_Ret_Addr[23].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_6 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_354 \Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB 
       (.S(addr_AddSub_7),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_5 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [7]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_355 \Using_FPGA_LUT6.Gen_Ret_Addr[24].MUXCY_XOR_I 
       (.LO(carry_8),
        .\LOCKSTEP_Out_reg[3031] (carry_7),
        .S(addr_AddSub_7),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [7]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_5 ),
        .lopt(lopt_12),
        .lopt_1(\Using_FPGA.Native_6 ),
        .lopt_10(lopt_16),
        .lopt_11(lopt_17),
        .lopt_12(lopt_56),
        .lopt_13(lopt_57),
        .lopt_14(lopt_58),
        .lopt_15(lopt_59),
        .lopt_16(lopt_60),
        .lopt_17(lopt_61),
        .lopt_18(lopt_62),
        .lopt_19(lopt_63),
        .lopt_2(addr_AddSub_8),
        .lopt_20(\Using_FPGA.Native_12 ),
        .lopt_21(\Using_FPGA.Native_11 ),
        .lopt_22(\Using_FPGA.Native_10 ),
        .lopt_23(\Using_FPGA.Native_9 ),
        .lopt_24(addr_AddSub_14),
        .lopt_25(addr_AddSub_13),
        .lopt_26(addr_AddSub_12),
        .lopt_27(addr_AddSub_11),
        .lopt_3(lopt_13),
        .lopt_4(\Using_FPGA.Native_7 ),
        .lopt_5(addr_AddSub_9),
        .lopt_6(lopt_14),
        .lopt_7(\Using_FPGA.Native_8 ),
        .lopt_8(addr_AddSub_10),
        .lopt_9(lopt_15));
  design_1_microblaze_0_0_MB_FDE_356 \Using_FPGA_LUT6.Gen_Ret_Addr[24].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_5 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_357 \Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB 
       (.S(addr_AddSub_6),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_4 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [6]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_358 \Using_FPGA_LUT6.Gen_Ret_Addr[25].MUXCY_XOR_I 
       (.LO(carry_7),
        .\LOCKSTEP_Out_reg[3032] (carry_6),
        .S(addr_AddSub_6),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [6]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_4 ),
        .lopt(lopt_8),
        .lopt_1(lopt_11));
  design_1_microblaze_0_0_MB_FDE_359 \Using_FPGA_LUT6.Gen_Ret_Addr[25].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_4 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_360 \Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB 
       (.S(addr_AddSub_5),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_3 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [5]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_361 \Using_FPGA_LUT6.Gen_Ret_Addr[26].MUXCY_XOR_I 
       (.LO(carry_6),
        .\LOCKSTEP_Out_reg[3033] (carry_5),
        .S(addr_AddSub_5),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [5]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_3 ),
        .lopt(lopt_7),
        .lopt_1(lopt_10));
  design_1_microblaze_0_0_MB_FDE_362 \Using_FPGA_LUT6.Gen_Ret_Addr[26].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_3 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_363 \Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB 
       (.S(addr_AddSub_4),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_2 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [4]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_364 \Using_FPGA_LUT6.Gen_Ret_Addr[27].MUXCY_XOR_I 
       (.LO(carry_5),
        .\LOCKSTEP_Out_reg[3034] (carry_4),
        .S(addr_AddSub_4),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [4]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_2 ),
        .lopt(lopt_6),
        .lopt_1(lopt_9));
  design_1_microblaze_0_0_MB_FDE_365 \Using_FPGA_LUT6.Gen_Ret_Addr[27].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_2 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_366 \Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB 
       (.S(addr_AddSub_3),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [3]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_367 \Using_FPGA_LUT6.Gen_Ret_Addr[28].MUXCY_XOR_I 
       (.LO(carry_4),
        .\LOCKSTEP_Out_reg[3035] (carry_3),
        .S(addr_AddSub_3),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [3]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_1 ),
        .lopt(lopt_6),
        .lopt_1(\Using_FPGA.Native_2 ),
        .lopt_10(lopt_10),
        .lopt_11(lopt_11),
        .lopt_12(lopt_48),
        .lopt_13(lopt_49),
        .lopt_14(lopt_50),
        .lopt_15(lopt_51),
        .lopt_16(lopt_52),
        .lopt_17(lopt_53),
        .lopt_18(lopt_54),
        .lopt_19(lopt_55),
        .lopt_2(addr_AddSub_4),
        .lopt_3(lopt_7),
        .lopt_4(\Using_FPGA.Native_3 ),
        .lopt_5(addr_AddSub_5),
        .lopt_6(lopt_8),
        .lopt_7(\Using_FPGA.Native_4 ),
        .lopt_8(addr_AddSub_6),
        .lopt_9(lopt_9));
  design_1_microblaze_0_0_MB_FDE_368 \Using_FPGA_LUT6.Gen_Ret_Addr[28].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_369 \Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB 
       (.I1_1(I1_1),
        .S(addr_AddSub_2),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [2]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_370 \Using_FPGA_LUT6.Gen_Ret_Addr[29].MUXCY_XOR_I 
       (.LO(carry_3),
        .\LOCKSTEP_Out_reg[3036] (carry_2),
        .S(addr_AddSub_2),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [2]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_0 ),
        .lopt(lopt_2),
        .lopt_1(lopt_5));
  design_1_microblaze_0_0_MB_FDE_371 \Using_FPGA_LUT6.Gen_Ret_Addr[29].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_372 \Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB 
       (.S(addr_AddSub_29),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_27 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [29]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_373 \Using_FPGA_LUT6.Gen_Ret_Addr[2].MUXCY_XOR_I 
       (.LO(carry_30),
        .\LOCKSTEP_Out_reg[3009] (carry_29),
        .S(addr_AddSub_29),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [21]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_27 ),
        .lopt(lopt_43),
        .lopt_1(lopt_46));
  design_1_microblaze_0_0_MB_FDE_374 \Using_FPGA_LUT6.Gen_Ret_Addr[2].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_27 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_375 \Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB 
       (.S(addr_AddSub_1),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [1]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_376 \Using_FPGA_LUT6.Gen_Ret_Addr[30].MUXCY_XOR_I 
       (.LO(carry_2),
        .\LOCKSTEP_Out_reg[3037] (carry_1),
        .S(addr_AddSub_1),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [1]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native ),
        .lopt(lopt_1),
        .lopt_1(lopt_4));
  design_1_microblaze_0_0_MB_FDE_377 \Using_FPGA_LUT6.Gen_Ret_Addr[30].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_378 \Using_FPGA_LUT6.Gen_Ret_Addr[31].I_RET_ADDR_WB 
       (.DI(DI),
        .O5(O5),
        .S(addr_AddSub_0),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_32 [0]),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_379 \Using_FPGA_LUT6.Gen_Ret_Addr[31].MUXCY_XOR_I 
       (.CI(carry_0),
        .DI(DI),
        .LO(carry_1),
        .S(addr_AddSub_0),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [0]),
        .lopt(lopt),
        .lopt_1(lopt_3));
  design_1_microblaze_0_0_MB_FDE_380 \Using_FPGA_LUT6.Gen_Ret_Addr[31].WB_PC_FDE 
       (.Clk(Clk),
        .DI(DI),
        .O5(O5),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_34 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_381 \Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB 
       (.S(addr_AddSub_28),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_26 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [28]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_382 \Using_FPGA_LUT6.Gen_Ret_Addr[3].MUXCY_XOR_I 
       (.LO(carry_29),
        .\LOCKSTEP_Out_reg[3010] (carry_28),
        .S(addr_AddSub_28),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [20]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_26 ),
        .lopt(lopt_42),
        .lopt_1(lopt_45));
  design_1_microblaze_0_0_MB_FDE_383 \Using_FPGA_LUT6.Gen_Ret_Addr[3].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_26 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_384 \Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB 
       (.S(addr_AddSub_27),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_25 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [27]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_385 \Using_FPGA_LUT6.Gen_Ret_Addr[4].MUXCY_XOR_I 
       (.LO(carry_28),
        .\LOCKSTEP_Out_reg[3011] (carry_27),
        .S(addr_AddSub_27),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [19]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_25 ),
        .lopt(lopt_42),
        .lopt_1(\Using_FPGA.Native_26 ),
        .lopt_10(lopt_46),
        .lopt_11(lopt_47),
        .lopt_12(lopt_72),
        .lopt_13(lopt_73),
        .lopt_14(lopt_74),
        .lopt_15(lopt_75),
        .lopt_16(lopt_76),
        .lopt_17(lopt_77),
        .lopt_18(lopt_78),
        .lopt_19(lopt_79),
        .lopt_2(addr_AddSub_28),
        .lopt_3(lopt_43),
        .lopt_4(\Using_FPGA.Native_27 ),
        .lopt_5(addr_AddSub_29),
        .lopt_6(lopt_44),
        .lopt_7(\Using_FPGA.Native_28 ),
        .lopt_8(addr_AddSub_30),
        .lopt_9(lopt_45));
  design_1_microblaze_0_0_MB_FDE_386 \Using_FPGA_LUT6.Gen_Ret_Addr[4].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_25 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_387 \Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB 
       (.S(addr_AddSub_26),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_24 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [26]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_388 \Using_FPGA_LUT6.Gen_Ret_Addr[5].MUXCY_XOR_I 
       (.LO(carry_27),
        .\LOCKSTEP_Out_reg[3012] (carry_26),
        .S(addr_AddSub_26),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [18]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_24 ),
        .lopt(lopt_38),
        .lopt_1(lopt_41));
  design_1_microblaze_0_0_MB_FDE_389 \Using_FPGA_LUT6.Gen_Ret_Addr[5].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_24 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_390 \Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB 
       (.S(addr_AddSub_25),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_23 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [25]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_391 \Using_FPGA_LUT6.Gen_Ret_Addr[6].MUXCY_XOR_I 
       (.LO(carry_26),
        .\LOCKSTEP_Out_reg[3013] (carry_25),
        .S(addr_AddSub_25),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [17]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_23 ),
        .lopt(lopt_37),
        .lopt_1(lopt_40));
  design_1_microblaze_0_0_MB_FDE_392 \Using_FPGA_LUT6.Gen_Ret_Addr[6].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_23 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_393 \Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB 
       (.S(addr_AddSub_24),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_22 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [24]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_394 \Using_FPGA_LUT6.Gen_Ret_Addr[7].MUXCY_XOR_I 
       (.LO(carry_25),
        .\LOCKSTEP_Out_reg[3014] (carry_24),
        .S(addr_AddSub_24),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [16]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_22 ),
        .lopt(lopt_36),
        .lopt_1(lopt_39));
  design_1_microblaze_0_0_MB_FDE_395 \Using_FPGA_LUT6.Gen_Ret_Addr[7].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_22 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_396 \Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB 
       (.S(addr_AddSub_23),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_21 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [23]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_397 \Using_FPGA_LUT6.Gen_Ret_Addr[8].MUXCY_XOR_I 
       (.LO(carry_24),
        .\LOCKSTEP_Out_reg[3015] (carry_23),
        .S(addr_AddSub_23),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [15]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_21 ),
        .lopt(lopt_36),
        .lopt_1(\Using_FPGA.Native_22 ),
        .lopt_10(lopt_40),
        .lopt_11(lopt_41),
        .lopt_12(lopt_72),
        .lopt_13(lopt_73),
        .lopt_14(lopt_74),
        .lopt_15(lopt_75),
        .lopt_16(lopt_76),
        .lopt_17(lopt_77),
        .lopt_18(lopt_78),
        .lopt_19(lopt_79),
        .lopt_2(addr_AddSub_24),
        .lopt_20(\Using_FPGA.Native_28 ),
        .lopt_21(\Using_FPGA.Native_27 ),
        .lopt_22(\Using_FPGA.Native_26 ),
        .lopt_23(\Using_FPGA.Native_25 ),
        .lopt_24(addr_AddSub_30),
        .lopt_25(addr_AddSub_29),
        .lopt_26(addr_AddSub_28),
        .lopt_27(addr_AddSub_27),
        .lopt_3(lopt_37),
        .lopt_4(\Using_FPGA.Native_23 ),
        .lopt_5(addr_AddSub_25),
        .lopt_6(lopt_38),
        .lopt_7(\Using_FPGA.Native_24 ),
        .lopt_8(addr_AddSub_26),
        .lopt_9(lopt_39));
  design_1_microblaze_0_0_MB_FDE_398 \Using_FPGA_LUT6.Gen_Ret_Addr[8].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_21 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB_n_0 ));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized5_399 \Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB 
       (.S(addr_AddSub_22),
        .\Using_FPGA.Native_0 (\Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_20 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_31 ),
        .\Using_FPGA.Native_3 (\Using_FPGA.Native_32 [22]),
        .\Using_FPGA.Native_4 (\Using_FPGA.Native_33 ));
  design_1_microblaze_0_0_MB_MUXCY_XORCY_400 \Using_FPGA_LUT6.Gen_Ret_Addr[9].MUXCY_XOR_I 
       (.CI(carry_22),
        .LO(carry_23),
        .S(addr_AddSub_22),
        .\Using_FPGA.Native (\Using_FPGA.Native_30 [14]),
        .\Using_FPGA.Native_I2_0 (\Using_FPGA.Native_20 ),
        .lopt(lopt_32),
        .lopt_1(lopt_35));
  design_1_microblaze_0_0_MB_FDE_401 \Using_FPGA_LUT6.Gen_Ret_Addr[9].WB_PC_FDE 
       (.Clk(Clk),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_20 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_34 ),
        .\Using_FPGA.Native_2 (\Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB_n_0 ));
endmodule

(* ORIG_REF_NAME = "instr_mux" *) 
module design_1_microblaze_0_0_instr_mux
   (I139_out,
    Y,
    in,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    Instr,
    LOCKSTEP_Master_Out);
  output I139_out;
  output [0:31]Y;
  output [0:0]in;
  input [0:0]\Using_FPGA.Native ;
  input [0:0]\Using_FPGA.Native_0 ;
  input [0:31]Instr;
  input [32:0]LOCKSTEP_Master_Out;

  wire I139_out;
  wire [0:31]Instr;
  wire [32:0]LOCKSTEP_Master_Out;
  wire [0:0]\Using_FPGA.Native ;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire [0:31]Y;
  wire [0:0]in;

  design_1_microblaze_0_0_mux_bus \Mux_LD.LD_inst 
       (.I139_out(I139_out),
        .Instr(Instr),
        .LOCKSTEP_Master_Out(LOCKSTEP_Master_Out),
        .\Using_FPGA.Native (\Using_FPGA.Native ),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native_0 ),
        .Y(Y),
        .in(in));
endmodule

(* ORIG_REF_NAME = "jump_logic" *) 
module design_1_microblaze_0_0_jump_logic
   (ex_jump,
    ex_op1_cmp_equal,
    ex_op1_cmp_equal_n,
    ex_jump_q,
    I5,
    of_next_ex_valid,
    ex_jump_hold_reg,
    ex_delayslot_Instr0,
    keep_jump_taken_with_ds_reg,
    mem_jump_taken0,
    \if_pc_reg[0] ,
    \Using_FPGA.Native ,
    ex_op1_zero,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    sync_reset,
    use_Reg_Neg_S_reg_0,
    ex_op1_cmp_eq_reg_0,
    Clk,
    ex_op1_cmp_eq_n5_out,
    force_Val2_N_reg_0,
    ex_op1_cmp_eq1,
    use_Reg_Neg_DI1_out,
    force_Val10_out,
    use_Reg_Neg_S3_out,
    force12_out,
    \Using_FPGA.Native_2 ,
    wb_exception,
    Q,
    out,
    ex_Exception_Taken,
    ex_jump_nodelay,
    of_valid,
    mem_exception_from_ex,
    mem_valid_instr,
    ex_jump_hold,
    E,
    keep_jump_taken_with_ds,
    ex_branch_with_delayslot,
    ex_mbar_stall_no_sleep_1,
    ex_first_cycle,
    ex_mbar_decode,
    ex_mbar_sleep,
    ex_databus_addr,
    \if_pc_reg[30] ,
    \if_pc_reg[0]_0 ,
    O,
    \if_pc_reg[28] ,
    \if_pc_reg[27] ,
    \if_pc_reg[26] ,
    \if_pc_reg[25] ,
    \if_pc_reg[24] ,
    \if_pc_reg[23] ,
    \if_pc_reg[22] ,
    \if_pc_reg[21] ,
    \if_pc_reg[20] ,
    \if_pc_reg[19] ,
    \if_pc_reg[18] ,
    \if_pc_reg[17] ,
    \if_pc_reg[16] ,
    \if_pc_reg[15] ,
    \if_pc_reg[14] ,
    \if_pc_reg[13] ,
    \if_pc_reg[12] ,
    \if_pc_reg[11] ,
    \if_pc_reg[10] ,
    \if_pc_reg[9] ,
    \if_pc_reg[8] ,
    \if_pc_reg[7] ,
    \if_pc_reg[6] ,
    \if_pc_reg[5] ,
    \if_pc_reg[4] ,
    \if_pc_reg[3] ,
    \if_pc_reg[2] ,
    \if_pc_reg[1] ,
    O56_out,
    EX_MBAR_Stall__1,
    lopt,
    lopt_1,
    lopt_2);
  output ex_jump;
  output ex_op1_cmp_equal;
  output ex_op1_cmp_equal_n;
  output ex_jump_q;
  output I5;
  output of_next_ex_valid;
  output ex_jump_hold_reg;
  output ex_delayslot_Instr0;
  output keep_jump_taken_with_ds_reg;
  output mem_jump_taken0;
  output [31:0]\if_pc_reg[0] ;
  output \Using_FPGA.Native ;
  input ex_op1_zero;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input sync_reset;
  input use_Reg_Neg_S_reg_0;
  input ex_op1_cmp_eq_reg_0;
  input Clk;
  input ex_op1_cmp_eq_n5_out;
  input force_Val2_N_reg_0;
  input ex_op1_cmp_eq1;
  input use_Reg_Neg_DI1_out;
  input force_Val10_out;
  input use_Reg_Neg_S3_out;
  input force12_out;
  input [0:0]\Using_FPGA.Native_2 ;
  input wb_exception;
  input [1:0]Q;
  input out;
  input ex_Exception_Taken;
  input ex_jump_nodelay;
  input of_valid;
  input mem_exception_from_ex;
  input mem_valid_instr;
  input ex_jump_hold;
  input [0:0]E;
  input keep_jump_taken_with_ds;
  input ex_branch_with_delayslot;
  input ex_mbar_stall_no_sleep_1;
  input ex_first_cycle;
  input ex_mbar_decode;
  input ex_mbar_sleep;
  input [1:0]ex_databus_addr;
  input [1:0]\if_pc_reg[30] ;
  input [29:0]\if_pc_reg[0]_0 ;
  input O;
  input \if_pc_reg[28] ;
  input \if_pc_reg[27] ;
  input \if_pc_reg[26] ;
  input \if_pc_reg[25] ;
  input \if_pc_reg[24] ;
  input \if_pc_reg[23] ;
  input \if_pc_reg[22] ;
  input \if_pc_reg[21] ;
  input \if_pc_reg[20] ;
  input \if_pc_reg[19] ;
  input \if_pc_reg[18] ;
  input \if_pc_reg[17] ;
  input \if_pc_reg[16] ;
  input \if_pc_reg[15] ;
  input \if_pc_reg[14] ;
  input \if_pc_reg[13] ;
  input \if_pc_reg[12] ;
  input \if_pc_reg[11] ;
  input \if_pc_reg[10] ;
  input \if_pc_reg[9] ;
  input \if_pc_reg[8] ;
  input \if_pc_reg[7] ;
  input \if_pc_reg[6] ;
  input \if_pc_reg[5] ;
  input \if_pc_reg[4] ;
  input \if_pc_reg[3] ;
  input \if_pc_reg[2] ;
  input \if_pc_reg[1] ;
  input O56_out;
  input EX_MBAR_Stall__1;
  input lopt;
  output lopt_1;
  output lopt_2;

  wire Clk;
  wire DI;
  wire [0:0]E;
  wire EX_MBAR_Stall__1;
  wire I5;
  wire MUXCY_JUMP_CARRY6_n_39;
  wire O;
  wire O56_out;
  wire [1:0]Q;
  wire S;
  wire \Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire [0:0]\Using_FPGA.Native_2 ;
  wire ex_Exception_Taken;
  wire ex_branch_with_delayslot;
  wire [1:0]ex_databus_addr;
  wire ex_delayslot_Instr0;
  wire ex_first_cycle;
  wire ex_jump;
  wire ex_jump_hold;
  wire ex_jump_hold_reg;
  wire ex_jump_nodelay;
  wire ex_jump_q;
  wire ex_jump_wanted;
  wire ex_mbar_decode;
  wire ex_mbar_sleep;
  wire ex_mbar_stall_no_sleep_1;
  wire ex_op1_cmp_eq1;
  wire ex_op1_cmp_eq_n5_out;
  wire ex_op1_cmp_eq_reg_0;
  wire ex_op1_cmp_equal;
  wire ex_op1_cmp_equal_n;
  wire ex_op1_zero;
  wire force12_out;
  wire force1_reg_n_0;
  wire force2;
  wire force_Val10_out;
  wire force_Val1_reg_n_0;
  wire force_Val2_N;
  wire force_Val2_N_reg_0;
  wire [31:0]\if_pc_reg[0] ;
  wire [29:0]\if_pc_reg[0]_0 ;
  wire \if_pc_reg[10] ;
  wire \if_pc_reg[11] ;
  wire \if_pc_reg[12] ;
  wire \if_pc_reg[13] ;
  wire \if_pc_reg[14] ;
  wire \if_pc_reg[15] ;
  wire \if_pc_reg[16] ;
  wire \if_pc_reg[17] ;
  wire \if_pc_reg[18] ;
  wire \if_pc_reg[19] ;
  wire \if_pc_reg[1] ;
  wire \if_pc_reg[20] ;
  wire \if_pc_reg[21] ;
  wire \if_pc_reg[22] ;
  wire \if_pc_reg[23] ;
  wire \if_pc_reg[24] ;
  wire \if_pc_reg[25] ;
  wire \if_pc_reg[26] ;
  wire \if_pc_reg[27] ;
  wire \if_pc_reg[28] ;
  wire \if_pc_reg[2] ;
  wire [1:0]\if_pc_reg[30] ;
  wire \if_pc_reg[3] ;
  wire \if_pc_reg[4] ;
  wire \if_pc_reg[5] ;
  wire \if_pc_reg[6] ;
  wire \if_pc_reg[7] ;
  wire \if_pc_reg[8] ;
  wire \if_pc_reg[9] ;
  wire jump_carry1;
  wire jump_carry2;
  wire jump_carry4;
  wire jump_carry5;
  wire keep_jump_taken_with_ds;
  wire keep_jump_taken_with_ds_reg;
  wire lopt;
  wire \^lopt_1 ;
  wire lopt_10;
  wire \^lopt_2 ;
  wire lopt_3;
  wire lopt_4;
  wire lopt_5;
  wire lopt_6;
  wire lopt_7;
  wire lopt_8;
  wire lopt_9;
  wire mem_exception_from_ex;
  wire mem_jump_taken0;
  wire mem_valid_instr;
  (* DIRECT_ENABLE *) wire of_PipeRun_for_ce;
  wire of_next_ex_valid;
  wire of_valid;
  wire out;
  (* DIRECT_RESET *) wire reset_bool_for_rst;
  wire use_Reg_Neg_DI1_out;
  wire use_Reg_Neg_DI_reg_n_0;
  wire use_Reg_Neg_S3_out;
  wire use_Reg_Neg_S_reg_n_0;
  wire wb_exception;

  assign lopt_1 = DI;
  assign lopt_2 = S;
  assign of_PipeRun_for_ce = use_Reg_Neg_S_reg_0;
  assign reset_bool_for_rst = sync_reset;
  design_1_microblaze_0_0_MB_MUXCY_92 MUXCY_JUMP_CARRY
       (.DI(DI),
        .S(S),
        .ex_op1_zero(ex_op1_zero),
        .jump_carry1(jump_carry1),
        .lopt(lopt));
  design_1_microblaze_0_0_MB_MUXCY_93 MUXCY_JUMP_CARRY2
       (.force2(force2),
        .force_Val2_N(force_Val2_N),
        .jump_carry1(jump_carry1),
        .jump_carry2(jump_carry2),
        .lopt(\^lopt_1 ),
        .lopt_1(\^lopt_2 ),
        .lopt_10(lopt_9),
        .lopt_11(lopt_10),
        .lopt_2(\Using_FPGA.Native_0 ),
        .lopt_3(lopt_3),
        .lopt_4(lopt_4),
        .lopt_5(\Using_FPGA.Native_1 ),
        .lopt_6(lopt_5),
        .lopt_7(lopt_6),
        .lopt_8(lopt_7),
        .lopt_9(lopt_8),
        .out(out));
  design_1_microblaze_0_0_MB_MUXCY_94 MUXCY_JUMP_CARRY3
       (.EX_MBAR_Stall__1(EX_MBAR_Stall__1),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .ex_branch_with_delayslot(ex_branch_with_delayslot),
        .ex_jump_wanted(ex_jump_wanted),
        .jump_carry2(jump_carry2),
        .lopt(\^lopt_1 ),
        .lopt_1(\^lopt_2 ),
        .of_valid(of_valid));
  design_1_microblaze_0_0_MB_MUXCY_95 MUXCY_JUMP_CARRY4
       (.\Using_FPGA.Native_0 (\Using_FPGA.Native_1 ),
        .ex_jump_wanted(ex_jump_wanted),
        .jump_carry4(jump_carry4),
        .lopt(lopt_3),
        .lopt_1(lopt_4));
  design_1_microblaze_0_0_MB_MUXCY_96 MUXCY_JUMP_CARRY5
       (.jump_carry4(jump_carry4),
        .jump_carry5(jump_carry5),
        .lopt(lopt_5),
        .lopt_1(lopt_6),
        .lopt_2(lopt_7));
  design_1_microblaze_0_0_MB_MUXCY_97 MUXCY_JUMP_CARRY6
       (.E(E),
        .I5(I5),
        .O(O),
        .O56_out(O56_out),
        .Q(Q),
        .ex_Exception_Taken(ex_Exception_Taken),
        .ex_branch_with_delayslot(ex_branch_with_delayslot),
        .ex_databus_addr(ex_databus_addr),
        .ex_delayslot_Instr0(ex_delayslot_Instr0),
        .ex_first_cycle(ex_first_cycle),
        .ex_jump_hold(ex_jump_hold),
        .ex_jump_hold_reg(ex_jump),
        .ex_jump_hold_reg_0(ex_jump_hold_reg),
        .ex_jump_nodelay(ex_jump_nodelay),
        .ex_jump_q(ex_jump_q),
        .ex_jump_q_reg(MUXCY_JUMP_CARRY6_n_39),
        .ex_mbar_decode(ex_mbar_decode),
        .ex_mbar_sleep(ex_mbar_sleep),
        .ex_mbar_stall_no_sleep_1(ex_mbar_stall_no_sleep_1),
        .\if_pc_reg[0] (\if_pc_reg[0] ),
        .\if_pc_reg[0]_0 (\if_pc_reg[0]_0 ),
        .\if_pc_reg[10] (\if_pc_reg[10] ),
        .\if_pc_reg[11] (\if_pc_reg[11] ),
        .\if_pc_reg[12] (\if_pc_reg[12] ),
        .\if_pc_reg[13] (\if_pc_reg[13] ),
        .\if_pc_reg[14] (\if_pc_reg[14] ),
        .\if_pc_reg[15] (\if_pc_reg[15] ),
        .\if_pc_reg[16] (\if_pc_reg[16] ),
        .\if_pc_reg[17] (\if_pc_reg[17] ),
        .\if_pc_reg[18] (\if_pc_reg[18] ),
        .\if_pc_reg[19] (\if_pc_reg[19] ),
        .\if_pc_reg[1] (\if_pc_reg[1] ),
        .\if_pc_reg[20] (\if_pc_reg[20] ),
        .\if_pc_reg[21] (\if_pc_reg[21] ),
        .\if_pc_reg[22] (\if_pc_reg[22] ),
        .\if_pc_reg[23] (\if_pc_reg[23] ),
        .\if_pc_reg[24] (\if_pc_reg[24] ),
        .\if_pc_reg[25] (\if_pc_reg[25] ),
        .\if_pc_reg[26] (\if_pc_reg[26] ),
        .\if_pc_reg[27] (\if_pc_reg[27] ),
        .\if_pc_reg[28] (\if_pc_reg[28] ),
        .\if_pc_reg[2] (\if_pc_reg[2] ),
        .\if_pc_reg[30] (\if_pc_reg[30] ),
        .\if_pc_reg[3] (\if_pc_reg[3] ),
        .\if_pc_reg[4] (\if_pc_reg[4] ),
        .\if_pc_reg[5] (\if_pc_reg[5] ),
        .\if_pc_reg[6] (\if_pc_reg[6] ),
        .\if_pc_reg[7] (\if_pc_reg[7] ),
        .\if_pc_reg[8] (\if_pc_reg[8] ),
        .\if_pc_reg[9] (\if_pc_reg[9] ),
        .jump_carry5(jump_carry5),
        .keep_jump_taken_with_ds(keep_jump_taken_with_ds),
        .keep_jump_taken_with_ds_reg(keep_jump_taken_with_ds_reg),
        .keep_jump_taken_with_ds_reg_0(of_PipeRun_for_ce),
        .lopt(lopt_8),
        .lopt_1(lopt_9),
        .lopt_2(lopt_10),
        .mem_exception_from_ex(mem_exception_from_ex),
        .mem_jump_taken0(mem_jump_taken0),
        .mem_valid_instr(mem_valid_instr),
        .of_next_ex_valid(of_next_ex_valid),
        .of_valid(of_valid),
        .sync_reset(reset_bool_for_rst),
        .wb_exception(wb_exception));
  FDRE ex_jump_q_reg
       (.C(Clk),
        .CE(1'b1),
        .D(MUXCY_JUMP_CARRY6_n_39),
        .Q(ex_jump_q),
        .R(1'b0));
  FDRE ex_op1_cmp_eq_n_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_op1_cmp_eq_n5_out),
        .Q(ex_op1_cmp_equal_n),
        .R(reset_bool_for_rst));
  FDSE ex_op1_cmp_eq_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_op1_cmp_eq_reg_0),
        .Q(ex_op1_cmp_equal),
        .S(reset_bool_for_rst));
  FDRE force1_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(force12_out),
        .Q(force1_reg_n_0),
        .R(reset_bool_for_rst));
  FDRE force2_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(ex_op1_cmp_eq1),
        .Q(force2),
        .R(reset_bool_for_rst));
  LUT3 #(
    .INIT(8'hA6)) 
    force_DI1
       (.I0(force_Val1_reg_n_0),
        .I1(use_Reg_Neg_DI_reg_n_0),
        .I2(\Using_FPGA.Native_2 ),
        .O(DI));
  FDRE force_Val1_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(force_Val10_out),
        .Q(force_Val1_reg_n_0),
        .R(reset_bool_for_rst));
  FDSE force_Val2_N_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(force_Val2_N_reg_0),
        .Q(force_Val2_N),
        .S(reset_bool_for_rst));
  LUT3 #(
    .INIT(8'hA6)) 
    force_jump1
       (.I0(force1_reg_n_0),
        .I1(use_Reg_Neg_S_reg_n_0),
        .I2(\Using_FPGA.Native_2 ),
        .O(S));
  FDRE use_Reg_Neg_DI_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(use_Reg_Neg_DI1_out),
        .Q(use_Reg_Neg_DI_reg_n_0),
        .R(reset_bool_for_rst));
  FDRE use_Reg_Neg_S_reg
       (.C(Clk),
        .CE(of_PipeRun_for_ce),
        .D(use_Reg_Neg_S3_out),
        .Q(use_Reg_Neg_S_reg_n_0),
        .R(reset_bool_for_rst));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit
   (out,
    reset_temp,
    Clk);
  output [0:0]out;
  input reset_temp;
  input Clk;

  wire Clk;
  wire reset_temp;
  (* async_reg = "true" *) wire [1:2]sync;

  assign out[0] = sync[2];
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(reset_temp),
        .Q(sync[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_0
   (out,
    SR,
    Wakeup,
    Clk);
  output [0:0]out;
  input [0:0]SR;
  input [0:0]Wakeup;
  input Clk;

  wire Clk;
  wire [0:0]SR;
  wire [0:0]Wakeup;
  (* async_reg = "true" *) wire [1:2]sync;

  assign out[0] = sync[2];
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(Wakeup),
        .Q(sync[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_1
   (out,
    SR,
    Wakeup,
    Clk);
  output [0:0]out;
  input [0:0]SR;
  input [0:0]Wakeup;
  input Clk;

  wire Clk;
  wire [0:0]SR;
  wire [0:0]Wakeup;
  (* async_reg = "true" *) wire [1:2]sync;

  assign out[0] = sync[2];
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(Wakeup),
        .Q(sync[1]),
        .R(SR));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_46
   (sample_synced,
    p_94_out,
    Q,
    sync_reset,
    D,
    Clk);
  output [0:0]sample_synced;
  output p_94_out;
  input [0:0]Q;
  input sync_reset;
  input [0:0]D;
  input Clk;

  wire Clk;
  wire [0:0]D;
  wire [0:0]Q;
  wire p_94_out;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT2 #(
    .INIT(4'h2)) 
    \Serial_Dbg_Intf.normal_stop_cmd_i_i_1 
       (.I0(sync[2]),
        .I1(Q),
        .O(p_94_out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(D),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_47
   (sample_synced,
    p_91_out,
    Q,
    sync_reset,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    Clk);
  output [0:0]sample_synced;
  output p_91_out;
  input [0:0]Q;
  input sync_reset;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input Clk;

  wire Clk;
  wire [0:0]Q;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  wire p_91_out;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT2 #(
    .INIT(4'h2)) 
    \Serial_Dbg_Intf.force_stop_cmd_i_i_1 
       (.I0(sync[2]),
        .I1(Q),
        .O(p_91_out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_48
   (sample_synced,
    p_88_out,
    Q,
    sync_reset,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    Clk);
  output [0:0]sample_synced;
  output p_88_out;
  input [0:0]Q;
  input sync_reset;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input Clk;

  wire Clk;
  wire [0:0]Q;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  wire p_88_out;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT2 #(
    .INIT(4'h2)) 
    \Serial_Dbg_Intf.start_single_cmd_i_1 
       (.I0(sync[2]),
        .I1(Q),
        .O(p_88_out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_49
   (sample_synced,
    p_86_out,
    Q,
    sync_reset,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    Clk);
  output [0:0]sample_synced;
  output p_86_out;
  input [0:0]Q;
  input sync_reset;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input Clk;

  wire Clk;
  wire [0:0]Q;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  wire p_86_out;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT2 #(
    .INIT(4'h2)) 
    \Serial_Dbg_Intf.read_register_MSR_i_1 
       (.I0(sync[2]),
        .I1(Q),
        .O(p_86_out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_50
   (sample_synced,
    p_83_out,
    Q,
    sync_reset,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    Clk);
  output [0:0]sample_synced;
  output p_83_out;
  input [0:0]Q;
  input sync_reset;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input Clk;

  wire Clk;
  wire [0:0]Q;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  wire p_83_out;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT2 #(
    .INIT(4'h2)) 
    \Serial_Dbg_Intf.read_register_PC_i_1 
       (.I0(sync[2]),
        .I1(Q),
        .O(p_83_out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_51
   (sample_synced,
    \Use_Async_Reset.sync_reset_reg ,
    p_11_out,
    sync_reset,
    \Serial_Dbg_Intf.trig_in_1_reg ,
    Q,
    Dbg_Trig_In,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    Clk);
  output [0:0]sample_synced;
  output \Use_Async_Reset.sync_reset_reg ;
  output p_11_out;
  input sync_reset;
  input [2:0]\Serial_Dbg_Intf.trig_in_1_reg ;
  input [3:0]Q;
  input [0:0]Dbg_Trig_In;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input Clk;

  wire Clk;
  wire [0:0]Dbg_Trig_In;
  wire [3:0]Q;
  wire \Serial_Dbg_Intf.trig_in_1_i_2_n_0 ;
  wire [2:0]\Serial_Dbg_Intf.trig_in_1_reg ;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  wire \Use_Async_Reset.sync_reset_reg ;
  wire p_11_out;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT4 #(
    .INIT(16'h4F44)) 
    \Serial_Dbg_Intf.continue_from_brk_i_1 
       (.I0(Q[2]),
        .I1(sync[2]),
        .I2(Q[1]),
        .I3(\Serial_Dbg_Intf.trig_in_1_reg [1]),
        .O(p_11_out));
  LUT4 #(
    .INIT(16'h2202)) 
    \Serial_Dbg_Intf.trig_in_1_i_1 
       (.I0(\Serial_Dbg_Intf.trig_in_1_i_2_n_0 ),
        .I1(sync_reset),
        .I2(\Serial_Dbg_Intf.trig_in_1_reg [0]),
        .I3(Q[0]),
        .O(\Use_Async_Reset.sync_reset_reg ));
  LUT5 #(
    .INIT(32'hFFFF22F2)) 
    \Serial_Dbg_Intf.trig_in_1_i_2 
       (.I0(sync[2]),
        .I1(Q[2]),
        .I2(\Serial_Dbg_Intf.trig_in_1_reg [2]),
        .I3(Q[3]),
        .I4(Dbg_Trig_In),
        .O(\Serial_Dbg_Intf.trig_in_1_i_2_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_52
   (sample_synced,
    p_76_out,
    Q,
    sync_reset,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    Clk);
  output [0:0]sample_synced;
  output p_76_out;
  input [0:0]Q;
  input sync_reset;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input Clk;

  wire Clk;
  wire [0:0]Q;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  wire p_76_out;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT2 #(
    .INIT(4'h2)) 
    \Serial_Dbg_Intf.if_debug_ready_i_i_1 
       (.I0(sync[2]),
        .I1(Q),
        .O(p_76_out));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_53
   (sample_synced,
    \Serial_Dbg_Intf.trig_ack_out_1_reg ,
    Dbg_Trig_Ack_Out,
    sync_reset,
    Q,
    Dbg_Trig_Out,
    Clk);
  output [0:0]sample_synced;
  output \Serial_Dbg_Intf.trig_ack_out_1_reg ;
  input [0:0]Dbg_Trig_Ack_Out;
  input sync_reset;
  input [0:0]Q;
  input [0:0]Dbg_Trig_Out;
  input Clk;

  wire Clk;
  wire [0:0]Dbg_Trig_Ack_Out;
  wire [0:0]Dbg_Trig_Out;
  wire [0:0]Q;
  wire \Serial_Dbg_Intf.trig_ack_out_1_reg ;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  LUT4 #(
    .INIT(16'h2302)) 
    \Serial_Dbg_Intf.trig_ack_out_1_i_1 
       (.I0(Dbg_Trig_Ack_Out),
        .I1(sync_reset),
        .I2(Q),
        .I3(sync[2]),
        .O(\Serial_Dbg_Intf.trig_ack_out_1_reg ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(Dbg_Trig_Out),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_54
   (sample_synced,
    sync_reset,
    Dbg_Trig_Ack_In,
    Clk);
  output [0:0]sample_synced;
  input sync_reset;
  input [0:0]Dbg_Trig_Ack_In;
  input Clk;

  wire Clk;
  wire [0:0]Dbg_Trig_Ack_In;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(Dbg_Trig_Ack_In),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit_55
   (sample_synced,
    sync_reset,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    Clk);
  output [0:0]sample_synced;
  input sync_reset;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input Clk;

  wire Clk;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  (* async_reg = "true" *) wire [1:2]sync;
  wire sync_reset;

  assign sample_synced[0] = sync[2];
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[1] 
       (.C(Clk),
        .CE(1'b1),
        .D(\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .Q(sync[1]),
        .R(sync_reset));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE #(
    .INIT(1'b0)) 
    \Synchronize.use_sync_reset.sync_reg[2] 
       (.C(Clk),
        .CE(1'b1),
        .D(sync[1]),
        .Q(sync[2]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized2
   (D,
    dbg_brki_hit,
    Dbg_Clk,
    \Single_Synchronize.use_async_reset.sync_reg_0 );
  output [0:0]D;
  input dbg_brki_hit;
  input Dbg_Clk;
  input \Single_Synchronize.use_async_reset.sync_reg_0 ;

  wire [0:0]D;
  wire Dbg_Clk;
  wire \Single_Synchronize.use_async_reset.sync_reg_0 ;
  wire dbg_brki_hit;

  FDCE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_async_reset.sync_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Single_Synchronize.use_async_reset.sync_reg_0 ),
        .D(dbg_brki_hit),
        .Q(D));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized2_25
   (D,
    \Single_Synchronize.use_async_reset.sync_i_1_0 ,
    Pause,
    Dbg_Clk,
    Scan_En,
    Scan_Reset_Sel,
    Scan_Reset);
  output [0:0]D;
  output \Single_Synchronize.use_async_reset.sync_i_1_0 ;
  input Pause;
  input Dbg_Clk;
  input Scan_En;
  input Scan_Reset_Sel;
  input Scan_Reset;

  wire [0:0]D;
  wire Dbg_Clk;
  wire Pause;
  wire Scan_En;
  wire Scan_Reset;
  wire Scan_Reset_Sel;
  wire \Single_Synchronize.use_async_reset.sync_i_1_0 ;

  LUT3 #(
    .INIT(8'h40)) 
    \Single_Synchronize.use_async_reset.sync_i_1 
       (.I0(Scan_En),
        .I1(Scan_Reset_Sel),
        .I2(Scan_Reset),
        .O(\Single_Synchronize.use_async_reset.sync_i_1_0 ));
  FDCE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_async_reset.sync_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Single_Synchronize.use_async_reset.sync_i_1_0 ),
        .D(Pause),
        .Q(D));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized2_26
   (D,
    running_clock,
    Dbg_Clk,
    \Single_Synchronize.use_async_reset.sync_reg_0 );
  output [0:0]D;
  input running_clock;
  input Dbg_Clk;
  input \Single_Synchronize.use_async_reset.sync_reg_0 ;

  wire [0:0]D;
  wire Dbg_Clk;
  wire \Single_Synchronize.use_async_reset.sync_reg_0 ;
  wire running_clock;

  FDCE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_async_reset.sync_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Single_Synchronize.use_async_reset.sync_reg_0 ),
        .D(running_clock),
        .Q(D));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized2_27
   (D,
    Sleep,
    Dbg_Clk,
    \Single_Synchronize.use_async_reset.sync_reg_0 );
  output [0:0]D;
  input Sleep;
  input Dbg_Clk;
  input \Single_Synchronize.use_async_reset.sync_reg_0 ;

  wire [0:0]D;
  wire Dbg_Clk;
  wire \Single_Synchronize.use_async_reset.sync_reg_0 ;
  wire Sleep;

  FDCE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_async_reset.sync_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Single_Synchronize.use_async_reset.sync_reg_0 ),
        .D(Sleep),
        .Q(D));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized2_28
   (D,
    \Single_Synchronize.use_async_reset.sync_reg_0 ,
    Dbg_Clk,
    \Single_Synchronize.use_async_reset.sync_reg_1 );
  output [0:0]D;
  input \Single_Synchronize.use_async_reset.sync_reg_0 ;
  input Dbg_Clk;
  input \Single_Synchronize.use_async_reset.sync_reg_1 ;

  wire [0:0]D;
  wire Dbg_Clk;
  wire \Single_Synchronize.use_async_reset.sync_reg_0 ;
  wire \Single_Synchronize.use_async_reset.sync_reg_1 ;

  FDCE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_async_reset.sync_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Single_Synchronize.use_async_reset.sync_reg_1 ),
        .D(\Single_Synchronize.use_async_reset.sync_reg_0 ),
        .Q(D));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized2_56
   (D,
    dbg_hit,
    Dbg_Clk,
    \Single_Synchronize.use_async_reset.sync_reg_0 );
  output [0:0]D;
  input [0:0]dbg_hit;
  input Dbg_Clk;
  input \Single_Synchronize.use_async_reset.sync_reg_0 ;

  wire [0:0]D;
  wire Dbg_Clk;
  wire \Single_Synchronize.use_async_reset.sync_reg_0 ;
  wire [0:0]dbg_hit;

  FDCE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_async_reset.sync_reg 
       (.C(Dbg_Clk),
        .CE(1'b1),
        .CLR(\Single_Synchronize.use_async_reset.sync_reg_0 ),
        .D(dbg_hit),
        .Q(D));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized4
   (\Performance_Debug_Control.dbg_stop_i_reg ,
    sync_reset,
    LOCKSTEP_Master_Out,
    Clk,
    dbg_continue_i_reg,
    dbg_continue_i_reg_0,
    dbg_continue_i_reg_1,
    of_pause);
  output \Performance_Debug_Control.dbg_stop_i_reg ;
  input sync_reset;
  input [1:0]LOCKSTEP_Master_Out;
  input Clk;
  input dbg_continue_i_reg;
  input dbg_continue_i_reg_0;
  input dbg_continue_i_reg_1;
  input of_pause;

  wire Clk;
  wire [1:0]LOCKSTEP_Master_Out;
  wire \Performance_Debug_Control.dbg_stop_i_reg ;
  wire dbg_continue_i_reg;
  wire dbg_continue_i_reg_0;
  wire dbg_continue_i_reg_1;
  wire dbg_wakeup_synced;
  wire of_pause;
  wire sync_reset;

  FDRE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_sync_reset.sync_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(LOCKSTEP_Master_Out[1]),
        .Q(dbg_wakeup_synced),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'hFFFF0000FFFE0000)) 
    dbg_continue_i_i_1
       (.I0(dbg_continue_i_reg),
        .I1(dbg_wakeup_synced),
        .I2(dbg_continue_i_reg_0),
        .I3(dbg_continue_i_reg_1),
        .I4(of_pause),
        .I5(LOCKSTEP_Master_Out[0]),
        .O(\Performance_Debug_Control.dbg_stop_i_reg ));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized4_29
   (trig_ack_in_0_synced,
    trig_in_0_reg,
    sync_reset,
    Dbg_Trig_Ack_In,
    Clk,
    Dbg_Trig_In,
    D,
    mb_halted_1,
    trig_ack_in_0_synced_1);
  output trig_ack_in_0_synced;
  output trig_in_0_reg;
  input sync_reset;
  input [0:0]Dbg_Trig_Ack_In;
  input Clk;
  input [0:0]Dbg_Trig_In;
  input [0:0]D;
  input mb_halted_1;
  input trig_ack_in_0_synced_1;

  wire Clk;
  wire [0:0]D;
  wire [0:0]Dbg_Trig_Ack_In;
  wire [0:0]Dbg_Trig_In;
  wire mb_halted_1;
  wire sync_reset;
  wire trig_ack_in_0_synced;
  wire trig_ack_in_0_synced_1;
  wire trig_in_0_reg;

  FDRE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_sync_reset.sync_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(Dbg_Trig_Ack_In),
        .Q(trig_ack_in_0_synced),
        .R(sync_reset));
  LUT6 #(
    .INIT(64'h00AE00AE000000AE)) 
    trig_in_0_i_1
       (.I0(Dbg_Trig_In),
        .I1(D),
        .I2(mb_halted_1),
        .I3(sync_reset),
        .I4(trig_ack_in_0_synced),
        .I5(trig_ack_in_0_synced_1),
        .O(trig_in_0_reg));
endmodule

(* ORIG_REF_NAME = "mb_sync_bit" *) 
module design_1_microblaze_0_0_mb_sync_bit__parameterized4_30
   (trig_out_0_synced,
    \Performance_Debug_Control.trig_ack_out_0_reg ,
    \Performance_Debug_Control.trig_out_0_synced_1_reg ,
    sync_reset,
    Dbg_Trig_Out,
    Clk,
    Dbg_Trig_Ack_Out,
    trig_out_0_synced_1,
    D,
    Dbg_Stop,
    dbg_stop_1,
    \Performance_Debug_Control.dbg_stop_i_reg );
  output trig_out_0_synced;
  output \Performance_Debug_Control.trig_ack_out_0_reg ;
  output \Performance_Debug_Control.trig_out_0_synced_1_reg ;
  input sync_reset;
  input [0:0]Dbg_Trig_Out;
  input Clk;
  input [0:0]Dbg_Trig_Ack_Out;
  input trig_out_0_synced_1;
  input [0:0]D;
  input Dbg_Stop;
  input dbg_stop_1;
  input \Performance_Debug_Control.dbg_stop_i_reg ;

  wire Clk;
  wire [0:0]D;
  wire Dbg_Stop;
  wire [0:0]Dbg_Trig_Ack_Out;
  wire [0:0]Dbg_Trig_Out;
  wire \Performance_Debug_Control.dbg_stop_i_reg ;
  wire \Performance_Debug_Control.trig_ack_out_0_reg ;
  wire \Performance_Debug_Control.trig_out_0_synced_1_reg ;
  wire dbg_stop_1;
  wire sync_reset;
  wire trig_out_0_synced;
  wire trig_out_0_synced_1;

  LUT6 #(
    .INIT(64'hFFFFFFFF04040F04)) 
    \Performance_Debug_Control.dbg_stop_i_i_2 
       (.I0(trig_out_0_synced_1),
        .I1(trig_out_0_synced),
        .I2(D),
        .I3(Dbg_Stop),
        .I4(dbg_stop_1),
        .I5(\Performance_Debug_Control.dbg_stop_i_reg ),
        .O(\Performance_Debug_Control.trig_out_0_synced_1_reg ));
  LUT4 #(
    .INIT(16'h2302)) 
    \Performance_Debug_Control.trig_ack_out_0_i_1 
       (.I0(Dbg_Trig_Ack_Out),
        .I1(sync_reset),
        .I2(trig_out_0_synced_1),
        .I3(trig_out_0_synced),
        .O(\Performance_Debug_Control.trig_ack_out_0_reg ));
  FDRE #(
    .INIT(1'b0)) 
    \Single_Synchronize.use_sync_reset.sync_reg 
       (.C(Clk),
        .CE(1'b1),
        .D(Dbg_Trig_Out),
        .Q(trig_out_0_synced),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mb_sync_vec" *) 
module design_1_microblaze_0_0_mb_sync_vec
   (D,
    dbg_hit,
    Dbg_Clk,
    \Single_Synchronize.use_async_reset.sync_reg );
  output [0:0]D;
  input [0:0]dbg_hit;
  input Dbg_Clk;
  input \Single_Synchronize.use_async_reset.sync_reg ;

  wire [0:0]D;
  wire Dbg_Clk;
  wire \Single_Synchronize.use_async_reset.sync_reg ;
  wire [0:0]dbg_hit;

  design_1_microblaze_0_0_mb_sync_bit__parameterized2_56 \sync_bits[0].sync_bit 
       (.D(D),
        .Dbg_Clk(Dbg_Clk),
        .\Single_Synchronize.use_async_reset.sync_reg_0 (\Single_Synchronize.use_async_reset.sync_reg ),
        .dbg_hit(dbg_hit));
endmodule

(* ORIG_REF_NAME = "mb_sync_vec" *) 
module design_1_microblaze_0_0_mb_sync_vec__parameterized1
   (sample_synced,
    \Use_Async_Reset.sync_reset_reg ,
    p_11_out,
    \Serial_Dbg_Intf.trig_ack_out_1_reg ,
    p_88_out,
    p_91_out,
    p_76_out,
    p_86_out,
    p_83_out,
    p_94_out,
    sync_reset,
    Q,
    Dbg_Trig_Ack_Out,
    Dbg_Trig_In,
    D,
    Clk,
    \Synchronize.use_sync_reset.sync_reg[1] ,
    \Synchronize.use_sync_reset.sync_reg[1]_0 ,
    \Synchronize.use_sync_reset.sync_reg[1]_1 ,
    \Synchronize.use_sync_reset.sync_reg[1]_2 ,
    \Synchronize.use_sync_reset.sync_reg[1]_3 ,
    Dbg_Trig_Out,
    Dbg_Trig_Ack_In,
    \Synchronize.use_sync_reset.sync_reg[1]_4 );
  output [0:9]sample_synced;
  output \Use_Async_Reset.sync_reset_reg ;
  output p_11_out;
  output \Serial_Dbg_Intf.trig_ack_out_1_reg ;
  output p_88_out;
  output p_91_out;
  output p_76_out;
  output p_86_out;
  output p_83_out;
  output p_94_out;
  input sync_reset;
  input [8:0]Q;
  input [0:0]Dbg_Trig_Ack_Out;
  input [0:0]Dbg_Trig_In;
  input [0:0]D;
  input Clk;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1] ;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  input [1:0]\Synchronize.use_sync_reset.sync_reg[1]_1 ;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_2 ;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_3 ;
  input [0:0]Dbg_Trig_Out;
  input [0:0]Dbg_Trig_Ack_In;
  input [0:0]\Synchronize.use_sync_reset.sync_reg[1]_4 ;

  wire Clk;
  wire [0:0]D;
  wire [0:0]Dbg_Trig_Ack_In;
  wire [0:0]Dbg_Trig_Ack_Out;
  wire [0:0]Dbg_Trig_In;
  wire [0:0]Dbg_Trig_Out;
  wire [8:0]Q;
  wire \Serial_Dbg_Intf.trig_ack_out_1_reg ;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1] ;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_0 ;
  wire [1:0]\Synchronize.use_sync_reset.sync_reg[1]_1 ;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_2 ;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_3 ;
  wire [0:0]\Synchronize.use_sync_reset.sync_reg[1]_4 ;
  wire \Use_Async_Reset.sync_reset_reg ;
  wire p_11_out;
  wire p_76_out;
  wire p_83_out;
  wire p_86_out;
  wire p_88_out;
  wire p_91_out;
  wire p_94_out;
  wire [0:9]sample_synced;
  wire sync_reset;

  design_1_microblaze_0_0_mb_sync_bit_46 \sync_bits[0].sync_bit 
       (.Clk(Clk),
        .D(D),
        .Q(Q[8]),
        .p_94_out(p_94_out),
        .sample_synced(sample_synced[0]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_47 \sync_bits[1].sync_bit 
       (.Clk(Clk),
        .Q(Q[7]),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (\Synchronize.use_sync_reset.sync_reg[1] ),
        .p_91_out(p_91_out),
        .sample_synced(sample_synced[1]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_48 \sync_bits[2].sync_bit 
       (.Clk(Clk),
        .Q(Q[6]),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (\Synchronize.use_sync_reset.sync_reg[1]_0 ),
        .p_88_out(p_88_out),
        .sample_synced(sample_synced[2]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_49 \sync_bits[3].sync_bit 
       (.Clk(Clk),
        .Q(Q[5]),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (\Synchronize.use_sync_reset.sync_reg[1]_1 [1]),
        .p_86_out(p_86_out),
        .sample_synced(sample_synced[3]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_50 \sync_bits[4].sync_bit 
       (.Clk(Clk),
        .Q(Q[4]),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (\Synchronize.use_sync_reset.sync_reg[1]_1 [0]),
        .p_83_out(p_83_out),
        .sample_synced(sample_synced[4]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_51 \sync_bits[5].sync_bit 
       (.Clk(Clk),
        .Dbg_Trig_In(Dbg_Trig_In),
        .Q({Q[6],Q[3],Q[1:0]}),
        .\Serial_Dbg_Intf.trig_in_1_reg ({sample_synced[2],sample_synced[7],sample_synced[8]}),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (\Synchronize.use_sync_reset.sync_reg[1]_2 ),
        .\Use_Async_Reset.sync_reset_reg (\Use_Async_Reset.sync_reset_reg ),
        .p_11_out(p_11_out),
        .sample_synced(sample_synced[5]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_52 \sync_bits[6].sync_bit 
       (.Clk(Clk),
        .Q(Q[2]),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (\Synchronize.use_sync_reset.sync_reg[1]_3 ),
        .p_76_out(p_76_out),
        .sample_synced(sample_synced[6]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_53 \sync_bits[7].sync_bit 
       (.Clk(Clk),
        .Dbg_Trig_Ack_Out(Dbg_Trig_Ack_Out),
        .Dbg_Trig_Out(Dbg_Trig_Out),
        .Q(Q[1]),
        .\Serial_Dbg_Intf.trig_ack_out_1_reg (\Serial_Dbg_Intf.trig_ack_out_1_reg ),
        .sample_synced(sample_synced[7]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_54 \sync_bits[8].sync_bit 
       (.Clk(Clk),
        .Dbg_Trig_Ack_In(Dbg_Trig_Ack_In),
        .sample_synced(sample_synced[8]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_mb_sync_bit_55 \sync_bits[9].sync_bit 
       (.Clk(Clk),
        .\Synchronize.use_sync_reset.sync_reg[1]_0 (\Synchronize.use_sync_reset.sync_reg[1]_4 ),
        .sample_synced(sample_synced[9]),
        .sync_reset(sync_reset));
endmodule

(* ORIG_REF_NAME = "msr_reg_gti" *) 
module design_1_microblaze_0_0_msr_reg_gti
   (ex_MSR,
    MEM_Fwd,
    \wb_MSR_i_reg[28]_0 ,
    sync_reset,
    Clk,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    \Using_FPGA.Native_1 ,
    mem_sel_msr,
    \WB_MEM_Result_reg[0] ,
    \Using_FPGA.Native_2 ,
    \wb_MSR_i_reg[30]_0 );
  output [2:0]ex_MSR;
  output [3:0]MEM_Fwd;
  output [2:0]\wb_MSR_i_reg[28]_0 ;
  input sync_reset;
  input Clk;
  input \Using_FPGA.Native ;
  input \Using_FPGA.Native_0 ;
  input \Using_FPGA.Native_1 ;
  input mem_sel_msr;
  input [3:0]\WB_MEM_Result_reg[0] ;
  input \Using_FPGA.Native_2 ;
  input [0:0]\wb_MSR_i_reg[30]_0 ;

  wire Clk;
  wire [3:0]MEM_Fwd;
  wire \OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I_n_1 ;
  wire \OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I_n_1 ;
  wire \OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I_n_1 ;
  wire \Using_FPGA.Native ;
  wire \Using_FPGA.Native_0 ;
  wire \Using_FPGA.Native_1 ;
  wire \Using_FPGA.Native_2 ;
  wire [3:0]\WB_MEM_Result_reg[0] ;
  wire [2:0]ex_MSR;
  wire [28:30]mem_MSR;
  wire mem_sel_msr;
  wire sync_reset;
  wire [2:0]\wb_MSR_i_reg[28]_0 ;
  wire [0:0]\wb_MSR_i_reg[30]_0 ;

  design_1_microblaze_0_0_MB_FDR_301 \MEM_MSR_Bits[28].Using_FDR.MSR_I 
       (.Clk(Clk),
        .D(mem_MSR[28]),
        .MEM_Fwd(MEM_Fwd[2]),
        .\Using_FPGA.Native_0 (\OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I_n_1 ),
        .\WB_MEM_Result_reg[28] (\WB_MEM_Result_reg[0] [2]),
        .mem_sel_msr(mem_sel_msr),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_FDR_302 \MEM_MSR_Bits[29].Using_FDR.MSR_I 
       (.Clk(Clk),
        .MEM_Fwd({MEM_Fwd[3],MEM_Fwd[1]}),
        .\Using_FPGA.Native_0 (\OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I_n_1 ),
        .\WB_MEM_Result_reg[0] ({\WB_MEM_Result_reg[0] [3],\WB_MEM_Result_reg[0] [1]}),
        .mem_MSR(mem_MSR[29]),
        .mem_sel_msr(mem_sel_msr),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_FDR_303 \MEM_MSR_Bits[30].Using_FDR.MSR_I 
       (.Clk(Clk),
        .D(mem_MSR[30]),
        .MEM_Fwd(MEM_Fwd[0]),
        .\Using_FPGA.Native_0 (\OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I_n_1 ),
        .\WB_MEM_Result_reg[30] (\WB_MEM_Result_reg[0] [0]),
        .mem_sel_msr(mem_sel_msr),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_FDR_304 \OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I 
       (.Clk(Clk),
        .D(mem_MSR[28]),
        .\Using_FPGA.Native_0 (\OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I_n_1 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_2 ),
        .ex_MSR(ex_MSR[2]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_FDR_305 \OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I 
       (.Clk(Clk),
        .D(mem_MSR[29]),
        .\Using_FPGA.Native_0 (\OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I_n_1 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_2 ),
        .ex_MSR(ex_MSR[1]),
        .sync_reset(sync_reset));
  design_1_microblaze_0_0_MB_FDR_306 \OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I 
       (.Clk(Clk),
        .D(mem_MSR[30]),
        .\Using_FPGA.Native_0 (\OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I_n_1 ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_1 ),
        .\Using_FPGA.Native_2 (\Using_FPGA.Native_2 ),
        .ex_MSR(ex_MSR[0]),
        .sync_reset(sync_reset));
  FDRE \wb_MSR_i_reg[28] 
       (.C(Clk),
        .CE(\wb_MSR_i_reg[30]_0 ),
        .D(mem_MSR[28]),
        .Q(\wb_MSR_i_reg[28]_0 [2]),
        .R(sync_reset));
  FDRE \wb_MSR_i_reg[29] 
       (.C(Clk),
        .CE(\wb_MSR_i_reg[30]_0 ),
        .D(mem_MSR[29]),
        .Q(\wb_MSR_i_reg[28]_0 [1]),
        .R(sync_reset));
  FDRE \wb_MSR_i_reg[30] 
       (.C(Clk),
        .CE(\wb_MSR_i_reg[30]_0 ),
        .D(mem_MSR[30]),
        .Q(\wb_MSR_i_reg[28]_0 [0]),
        .R(sync_reset));
endmodule

(* ORIG_REF_NAME = "mux_bus" *) 
module design_1_microblaze_0_0_mux_bus
   (I139_out,
    Y,
    in,
    \Using_FPGA.Native ,
    \Using_FPGA.Native_0 ,
    Instr,
    LOCKSTEP_Master_Out);
  output I139_out;
  output [0:31]Y;
  output [0:0]in;
  input [0:0]\Using_FPGA.Native ;
  input [0:0]\Using_FPGA.Native_0 ;
  input [0:31]Instr;
  input [32:0]LOCKSTEP_Master_Out;

  wire I139_out;
  wire [0:31]Instr;
  wire [32:0]LOCKSTEP_Master_Out;
  wire [0:0]\Using_FPGA.Native ;
  wire [0:0]\Using_FPGA.Native_0 ;
  wire [0:31]Y;
  wire [0:0]in;

  design_1_microblaze_0_0_MB_LUT6_2__parameterized3 \Mux_Loop[0].I_MUX_LUT6 
       (.I139_out(I139_out),
        .Instr({Instr[0],Instr[16]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32:31],LOCKSTEP_Master_Out[15]}),
        .\Using_FPGA.Native_0 (\Using_FPGA.Native ),
        .\Using_FPGA.Native_1 (\Using_FPGA.Native_0 ),
        .\Using_FPGA.Native_2 ({Y[1],Y[3]}),
        .Y({Y[0],Y[16]}),
        .in(in));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_2 \Mux_Loop[10].I_MUX_LUT6 
       (.Instr({Instr[10],Instr[26]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[21],LOCKSTEP_Master_Out[5]}),
        .Y({Y[10],Y[26]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_3 \Mux_Loop[11].I_MUX_LUT6 
       (.Instr({Instr[11],Instr[27]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[20],LOCKSTEP_Master_Out[4]}),
        .Y({Y[11],Y[27]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_4 \Mux_Loop[12].I_MUX_LUT6 
       (.Instr({Instr[12],Instr[28]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[19],LOCKSTEP_Master_Out[3]}),
        .Y({Y[12],Y[28]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_5 \Mux_Loop[13].I_MUX_LUT6 
       (.Instr({Instr[13],Instr[29]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[18],LOCKSTEP_Master_Out[2]}),
        .Y({Y[13],Y[29]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_6 \Mux_Loop[14].I_MUX_LUT6 
       (.Instr({Instr[14],Instr[30]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[17],LOCKSTEP_Master_Out[1]}),
        .Y({Y[14],Y[30]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_7 \Mux_Loop[15].I_MUX_LUT6 
       (.Instr({Instr[15],Instr[31]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[16],LOCKSTEP_Master_Out[0]}),
        .Y({Y[15],Y[31]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_8 \Mux_Loop[1].I_MUX_LUT6 
       (.Instr({Instr[1],Instr[17]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[30],LOCKSTEP_Master_Out[14]}),
        .Y({Y[1],Y[17]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_9 \Mux_Loop[2].I_MUX_LUT6 
       (.Instr({Instr[2],Instr[18]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[29],LOCKSTEP_Master_Out[13]}),
        .Y({Y[2],Y[18]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_10 \Mux_Loop[3].I_MUX_LUT6 
       (.Instr({Instr[3],Instr[19]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[28],LOCKSTEP_Master_Out[12]}),
        .Y({Y[3],Y[19]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_11 \Mux_Loop[4].I_MUX_LUT6 
       (.Instr({Instr[4],Instr[20]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[27],LOCKSTEP_Master_Out[11]}),
        .Y({Y[4],Y[20]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_12 \Mux_Loop[5].I_MUX_LUT6 
       (.Instr({Instr[5],Instr[21]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[26],LOCKSTEP_Master_Out[10]}),
        .Y({Y[5],Y[21]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_13 \Mux_Loop[6].I_MUX_LUT6 
       (.Instr({Instr[6],Instr[22]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[25],LOCKSTEP_Master_Out[9]}),
        .Y({Y[6],Y[22]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_14 \Mux_Loop[7].I_MUX_LUT6 
       (.Instr({Instr[7],Instr[23]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[24],LOCKSTEP_Master_Out[8]}),
        .Y({Y[7],Y[23]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_15 \Mux_Loop[8].I_MUX_LUT6 
       (.Instr({Instr[8],Instr[24]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[23],LOCKSTEP_Master_Out[7]}),
        .Y({Y[8],Y[24]}));
  design_1_microblaze_0_0_MB_LUT6_2__parameterized3_16 \Mux_Loop[9].I_MUX_LUT6 
       (.Instr({Instr[9],Instr[25]}),
        .LOCKSTEP_Master_Out({LOCKSTEP_Master_Out[32],LOCKSTEP_Master_Out[22],LOCKSTEP_Master_Out[6]}),
        .Y({Y[9],Y[25]}));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
