#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Fri Jan  8 11:03:46 2021
# Process ID: 6292
# Current directory: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1
# Command line: vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl
# Log file: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/design_1_wrapper.vds
# Journal file: C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source design_1_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
add_files: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 415.594 ; gain = 47.766
Command: synth_design -top design_1_wrapper -part xcku5p-ffvb676-2-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcku5p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcku5p'
INFO: [Device 21-403] Loading part xcku5p-ffvb676-2-e
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 5112 
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Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1464.234 ; gain = 59.613
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INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v:12]
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v:24]
INFO: [Synth 8-6157] synthesizing module 'design_1' [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:13]
INFO: [Synth 8-6157] synthesizing module 'design_1_axi_gpio_0_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_axi_gpio_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_axi_gpio_0_0' (1#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_axi_gpio_0_0_stub.v:6]
WARNING: [Synth 8-7023] instance 'axi_gpio_0' of module 'design_1_axi_gpio_0_0' has 22 connections declared, but only 21 given [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:98]
INFO: [Synth 8-6157] synthesizing module 'design_1_clk_wiz_1_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_clk_wiz_1_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'design_1_clk_wiz_1_0' (2#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_clk_wiz_1_0_stub.v:5]
INFO: [Synth 8-6157] synthesizing module 'design_1_factorial_0_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_factorial_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_factorial_0_0' (3#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_factorial_0_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'design_1_mdm_1_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_mdm_1_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_mdm_1_0' (4#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_mdm_1_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'design_1_microblaze_0_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_microblaze_0_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_microblaze_0_0' (5#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_microblaze_0_0_stub.v:6]
WARNING: [Synth 8-7023] instance 'microblaze_0' of module 'design_1_microblaze_0_0' has 52 connections declared, but only 49 given [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:143]
INFO: [Synth 8-6157] synthesizing module 'design_1_microblaze_0_axi_periph_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:267]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_1RZP34U' [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:701]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_1RZP34U' (6#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:701]
INFO: [Synth 8-6155] done synthesizing module 'design_1_microblaze_0_axi_periph_0' (7#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:267]
INFO: [Synth 8-6157] synthesizing module 'microblaze_0_local_memory_imp_1K0VQXK' [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:467]
INFO: [Synth 8-6157] synthesizing module 'design_1_dlmb_bram_if_cntlr_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_dlmb_bram_if_cntlr_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_dlmb_bram_if_cntlr_0' (8#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_dlmb_bram_if_cntlr_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'design_1_dlmb_v10_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_dlmb_v10_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_dlmb_v10_0' (9#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_dlmb_v10_0_stub.v:6]
WARNING: [Synth 8-7023] instance 'dlmb_v10' of module 'design_1_dlmb_v10_0' has 25 connections declared, but only 24 given [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:613]
INFO: [Synth 8-6157] synthesizing module 'design_1_ilmb_bram_if_cntlr_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_ilmb_bram_if_cntlr_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_ilmb_bram_if_cntlr_0' (10#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_ilmb_bram_if_cntlr_0_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'design_1_ilmb_v10_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_ilmb_v10_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_ilmb_v10_0' (11#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_ilmb_v10_0_stub.v:6]
WARNING: [Synth 8-7023] instance 'ilmb_v10' of module 'design_1_ilmb_v10_0' has 25 connections declared, but only 24 given [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:659]
INFO: [Synth 8-6157] synthesizing module 'design_1_lmb_bram_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_lmb_bram_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_lmb_bram_0' (12#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_lmb_bram_0_stub.v:6]
WARNING: [Synth 8-7023] instance 'lmb_bram' of module 'design_1_lmb_bram_0' has 16 connections declared, but only 14 given [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:684]
INFO: [Synth 8-6155] done synthesizing module 'microblaze_0_local_memory_imp_1K0VQXK' (13#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:467]
INFO: [Synth 8-6157] synthesizing module 'design_1_rst_clk_wiz_1_100M_0' [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_rst_clk_wiz_1_100M_0_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'design_1_rst_clk_wiz_1_100M_0' (14#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/.Xil/Vivado-6292-Nemesys4/realtime/design_1_rst_clk_wiz_1_100M_0_stub.v:6]
WARNING: [Synth 8-7023] instance 'rst_clk_wiz_1_100M' of module 'design_1_rst_clk_wiz_1_100M_0' has 10 connections declared, but only 8 given [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:256]
INFO: [Synth 8-6155] done synthesizing module 'design_1' (15#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/synth/design_1.v:13]
INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (16#1) [C:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v:12]
WARNING: [Synth 8-3331] design s00_couplers_imp_1RZP34U has unconnected port M_ACLK
WARNING: [Synth 8-3331] design s00_couplers_imp_1RZP34U has unconnected port M_ARESETN
WARNING: [Synth 8-3331] design s00_couplers_imp_1RZP34U has unconnected port S_ACLK
WARNING: [Synth 8-3331] design s00_couplers_imp_1RZP34U has unconnected port S_ARESETN
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port ACLK
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port ARESETN
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Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1524.617 ; gain = 119.996
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Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1529.191 ; gain = 124.570
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1529.191 ; gain = 124.570
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INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0/design_1_microblaze_0_0_in_context.xdc] for cell 'design_1_i/microblaze_0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_microblaze_0_0/design_1_microblaze_0_0/design_1_microblaze_0_0_in_context.xdc] for cell 'design_1_i/microblaze_0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0/design_1_ilmb_v10_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/dlmb_v10'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_v10_0/design_1_dlmb_v10_0/design_1_ilmb_v10_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/dlmb_v10'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0/design_1_ilmb_v10_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/ilmb_v10'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_v10_0/design_1_ilmb_v10_0/design_1_ilmb_v10_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/ilmb_v10'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0/design_1_dlmb_bram_if_cntlr_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/ilmb_bram_if_cntlr'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0/design_1_ilmb_bram_if_cntlr_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/ilmb_bram_if_cntlr'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0/design_1_lmb_bram_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/lmb_bram'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_lmb_bram_0/design_1_lmb_bram_0/design_1_lmb_bram_0_in_context.xdc] for cell 'design_1_i/microblaze_0_local_memory/lmb_bram'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0/design_1_mdm_1_0_in_context.xdc] for cell 'design_1_i/mdm_1'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_mdm_1_0/design_1_mdm_1_0/design_1_mdm_1_0_in_context.xdc] for cell 'design_1_i/mdm_1'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_in_context.xdc] for cell 'design_1_i/clk_wiz_1'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_in_context.xdc] for cell 'design_1_i/clk_wiz_1'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'design_1_i/rst_clk_wiz_1_100M'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0/design_1_rst_clk_wiz_1_100M_0_in_context.xdc] for cell 'design_1_i/rst_clk_wiz_1_100M'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_in_context.xdc] for cell 'design_1_i/axi_gpio_0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0/design_1_axi_gpio_0_0_in_context.xdc] for cell 'design_1_i/axi_gpio_0'
Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_factorial_0_0/design_1_factorial_0_0/design_1_factorial_0_0_in_context.xdc] for cell 'design_1_i/factorial_0'
Finished Parsing XDC File [c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_factorial_0_0/design_1_factorial_0_0/design_1_factorial_0_0_in_context.xdc] for cell 'design_1_i/factorial_0'
Parsing XDC File [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1605.301 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1605.301 ; gain = 0.000
WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'design_1_i/microblaze_0_local_memory/lmb_bram' at clock pin 'clka' is different from the actual clock period '10.000', this can lead to different synthesis results.
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Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1605.301 ; gain = 200.680
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Start Loading Part and Timing Information
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Loading part: xcku5p-ffvb676-2-e
INFO: [Synth 8-6742] Reading net delay rules and data
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1605.301 ; gain = 200.680
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Start Applying 'set_property' XDC Constraints
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Applied set_property IO_BUFFER_TYPE = NONE for default_sysclk1_300_clk_n. (constraint file  c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_in_context.xdc, line 3).
Applied set_property CLOCK_BUFFER_TYPE = NONE for default_sysclk1_300_clk_n. (constraint file  c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_in_context.xdc, line 4).
Applied set_property IO_BUFFER_TYPE = NONE for default_sysclk1_300_clk_p. (constraint file  c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_in_context.xdc, line 5).
Applied set_property CLOCK_BUFFER_TYPE = NONE for default_sysclk1_300_clk_p. (constraint file  c:/Users/Emre/Desktop/asd/project_3/project_3.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0/design_1_clk_wiz_1_0_in_context.xdc, line 6).
Applied set_property DONT_TOUCH = true for design_1_i. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/microblaze_0. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/microblaze_0_local_memory/dlmb_v10. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/microblaze_0_local_memory/ilmb_v10. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/microblaze_0_local_memory/ilmb_bram_if_cntlr. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/microblaze_0_local_memory/lmb_bram. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/mdm_1. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/clk_wiz_1. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/rst_clk_wiz_1_100M. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/axi_gpio_0. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/microblaze_0_axi_periph. (constraint file  auto generated constraint, line ).
Applied set_property DONT_TOUCH = true for design_1_i/factorial_0. (constraint file  auto generated constraint, line ).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1605.301 ; gain = 200.680
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1605.301 ; gain = 200.680
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 1824 (col length:96)
BRAMs: 960 (col length: RAMB18 96 RAMB36 48)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
Warning: Parallel synthesis criteria is not met 
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port ACLK
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port ARESETN
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port M00_ACLK
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port M00_ARESETN
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port S00_ACLK
WARNING: [Synth 8-3331] design design_1_microblaze_0_axi_periph_0 has unconnected port S00_ARESETN
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1605.301 ; gain = 200.680
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
INFO: [Synth 8-5578] Moved timing constraint from pin 'design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr/BRAM_Clk_A' to pin 'design_1_i/microblaze_0_local_memory/dlmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'design_1_i/microblaze_0_local_memory/ilmb_bram_if_cntlr/BRAM_Clk_A' to pin 'design_1_i/microblaze_0_local_memory/ilmb_bram_if_cntlr/bbstub_BRAM_Clk_A/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'design_1_i/mdm_1/Dbg_Clk_0' to pin 'design_1_i/mdm_1/bbstub_Dbg_Clk_0/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'design_1_i/mdm_1/Dbg_Update_0' to pin 'design_1_i/mdm_1/bbstub_Dbg_Update_0/O'
INFO: [Synth 8-5578] Moved timing constraint from pin 'design_1_i/clk_wiz_1/clk_out1' to pin 'design_1_i/clk_wiz_1/bbstub_clk_out1/O'
INFO: [Synth 8-5819] Moved 5 constraints on hierarchical pins to their respective driving/loading pins
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2005.512 ; gain = 600.891
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2005.512 ; gain = 600.891
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 2015.789 ; gain = 611.168
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+------+------------------------------+----------+
|      |BlackBox name                 |Instances |
+------+------------------------------+----------+
|1     |design_1_axi_gpio_0_0         |         1|
|2     |design_1_clk_wiz_1_0          |         1|
|3     |design_1_factorial_0_0        |         1|
|4     |design_1_mdm_1_0              |         1|
|5     |design_1_microblaze_0_0       |         1|
|6     |design_1_rst_clk_wiz_1_100M_0 |         1|
|7     |design_1_dlmb_bram_if_cntlr_0 |         1|
|8     |design_1_dlmb_v10_0           |         1|
|9     |design_1_ilmb_bram_if_cntlr_0 |         1|
|10    |design_1_ilmb_v10_0           |         1|
|11    |design_1_lmb_bram_0           |         1|
+------+------------------------------+----------+

Report Cell Usage: 
+------+------------------------------+------+
|      |Cell                          |Count |
+------+------------------------------+------+
|1     |design_1_axi_gpio_0_0         |     1|
|2     |design_1_clk_wiz_1_0          |     1|
|3     |design_1_dlmb_bram_if_cntlr_0 |     1|
|4     |design_1_dlmb_v10_0           |     1|
|5     |design_1_factorial_0_0        |     1|
|6     |design_1_ilmb_bram_if_cntlr_0 |     1|
|7     |design_1_ilmb_v10_0           |     1|
|8     |design_1_lmb_bram_0           |     1|
|9     |design_1_mdm_1_0              |     1|
|10    |design_1_microblaze_0_0       |     1|
|11    |design_1_rst_clk_wiz_1_100M_0 |     1|
|12    |IBUF                          |     1|
+------+------------------------------+------+

Report Instance Areas: 
+------+------------------------------+--------------------------------------+------+
|      |Instance                      |Module                                |Cells |
+------+------------------------------+--------------------------------------+------+
|1     |top                           |                                      |   876|
|2     |  design_1_i                  |design_1                              |   875|
|3     |    microblaze_0_axi_periph   |design_1_microblaze_0_axi_periph_0    |     0|
|4     |    microblaze_0_local_memory |microblaze_0_local_memory_imp_1K0VQXK |   496|
+------+------------------------------+--------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2030.590 ; gain = 549.859
Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 2030.590 ; gain = 625.969
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2067.387 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 1 instances were transformed.
  IBUF => IBUF (IBUFCTRL, INBUF): 1 instances

INFO: [Common 17-83] Releasing license: Synthesis
53 Infos, 20 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2067.387 ; gain = 1651.793
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2067.387 ; gain = 0.000
WARNING: [Constraints 18-5210] No constraints selected for write.
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
INFO: [Common 17-1381] The checkpoint 'C:/Users/Emre/Desktop/asd/project_3/project_3.runs/synth_1/design_1_wrapper.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Jan  8 11:04:34 2021...
