Categories
Digital Design

Exams and Sample Questions

Midterm

  • Midterm Sample Questions
  • Midterm Questions
  • Midterm Solutions

Final

  • Final Sample Questions
Categories
Digital Design

LMS and Piazza

A question and answer system is offered where students can ask questions and get answers. It is a platform for course announcements, student questions and answers. You can access it below.

https://piazza.com/class/kdc44ttpuae1my

LMS (Learning Management System), some assignments will be required to be delivered through the LMS system.

Categories
Digital Design

Tools

Tool NameContentLink
Von Neumann Architecture SimulatorIt is the simulator tool of the von Neumann architecture.http://levent.tc/files/courses/tools/vonneumann/
IEEE-754 Binary to Decimal Conversion ToolIt is a tool that converts a given decimal number to IEEE-754 format.http://levent.tc/files/courses/tools/floatbin/
Decimal, Binary and Hexadecimal ConverterIt is a tool that converts a given number in decimal, binary and hexadecimal formats to other formats.http://levent.tc/files/courses/tools/hexdecbin/
Circuit SimulatorA Javascript-based circuit simulation tool is presented. You can access it at the following address. Usage; Select an item from the toolbox and go to the right. Link the added items by drag action. Click on an input node to disconnect it. To delete the added item, drag the item to the toolbox. To edit the item’s name, you can access it on a label section. double clickhttp://levent.tc/files/courses/tools/devresimulatoru/
Circuit Simulator 2It is a very comprehensive circuit simulator. User manual:
http://levent.tc/files/courses/tools/devresimulatoru2/devreSimulatoruKullanimKilavuzu.pdf
http://levent.tc/files/courses/tools/devresimulatoru2/
Bit Logic Operations CalculatorIt is a calculator that performs operations on a bit basis. This application is useful for learning the bitwise operations. And, or, xor, not, and scrolling operations are supported.http://levent.tc/files/courses/tools/bitislemleri/
Categories
Digital Design

Labs

LabTopicDownload
1Combinational Logic
2Sequential Logic
3Verification Approaches
4State Machines
5Memories
6FB-CPU RTL Design
7SOC Concepts, Xilinx IPI Design and Interfaces 

LAB Delivery Document
Categories
Digital Design

Projects

FB-CPU RTL Design

Within the scope of this project, RTL design of a processor named FB-CPU with Verilog language and various code snippets written in machine language on the designed processor will be written. At the end of the project, it will be observed how RAM, Control Unit and Stores in a simple processor can work together and execute code snippets in machine language. FBCPU demo will be made on Basys3 FPGA development board to be used.

Detailed project description: Will be announced after midterm

Categories
Digital Design

Homeworks

HomeworkTopicDateDue DateDelivery MethodDownloadSolution
1Combinational Logic 
2Sequential Logic 
3Verification Approaches 
4State Machines 
5FB-CPU RTL Design 
Categories
Digital Design

Lecture Notes

WeekTopicDownload
1Introduction
2Number Systems and Boolean Algebra
3Combinational Logic
4Sequential Logic
5Verification Approaches
6State Machines
7Databus Elements
8Midterm
9Memories
10FB-CPU RTL Design
11Optimizations and Trade-offs
12SOC Concepts I
13SOC Concepts II
14Multi-Clock Zone Design
15Final and Project Presentations
Categories
Digital Design

Syllabus

WeekTopic
1Introduction
2Number Systems and Boolean Algebra
3Combinational Logic
4Sequential Logic
5Verification Approaches
6State Machines
7Databus Elements
8Midterm
9Memories
10FB-CPU RTL Design
11Optimizations and Trade-offs
12SOC Concepts I
13SOC Concepts II
14Multi-Clock Zone Design
15Final and Project Presentations
Categories
Digital Design

Detailed Course Description

Course Description

This course covers combinatorial, sequential circuits, state machines, verification methodologies, memories, design principles, SOC concepts and interfaces, which are frequently used in the digital design world. Within the scope of the course, a processor named Fenerbahçe Processor will be designed for educational purposes and verified with Verilog HDL. FPGA based demo will be presented.

Course Hours (Theoretical + Lab)

Monday 9.00-13.00

Instructors

Assist. Prof. Vecdi Emre Levent

T. A. Uğur Özbalkan

Prerequisites

There are no prerequisites.

Helpful Resources

Reference sources of the course are listed below.

  • Introduction to Logic Design, Third Edition, Alan B. Marcovitz, McGraw-Hill, 2010
  • Digital Design, Moris Mano and Michael D. Ciletti, 5th edition, Prentice Hall, 2009
  • FPGA Prototyping by Verilog Examples, Pong Chu, John Wiley, 2008
  • Introduction to Logic Design, Alan Marcovitz, McGraw Hill, 2010

Softwares

Xilinx Vivado 2022.1

Courses

The course has 2 hours of theory and 2 hours of laboratory part per week. It is expected that the course materials given by the lecturer will be reviewed before the lesson and repeated after the lesson. 

Learning Outcomes

  • Logic minimization with KMAPs
  • Circuit development with RTL design languages
  • Accuracy measurement of RTL circuits
  • Design of interfaces frequently used in industry

Quizzes

There will be two quizzes during the semester. 30 minutes will be given. Quiz date will be announced one week in advance.

Grading

It is mandatory to attend classes at 80%.

Term grade; will be determined by midterm, labs, assignments, project and final exam. Evaluation percentages are given in the table below.

ActivitiesRates
Midterm%20
Homework/Quiz%10
Lab%15
Project%25
Final%30
BonusUp to 5 points

5 points will be deducted for each hour that passes over the delivery time of homework and quizzes.

The weight and letter grade corresponding to the end of term grade are given in the table below.

MarkWeightLetter grade
90-1004.00AA
85-893.50BA
80-843.00BB
75-792.50CB
65-742.00CC
50-641.50DC
45-491.00DD
0 -440FF

Expected Effort

The effort table that the student is expected to show during the term is given below.

ContentHoursTimesSub Total
Lesson Preparation21428
Lesson Repetition21428
Homeworks4624
Project48148
Course Lesson41456
Midterm and Final24248


Students are expected to spend an average of 232 hours during the semester to be successful in the course.

Coding Homeworks

Grading of coding assignments will be done by examining the accuracy, quality and details of the algorithmic implementation of the code.

Testing

Test entry and expected outputs will be shared for each assignment to be given. However, other test situations that have not been shared with you will be tried during the homework control. Code that takes longer to run than expected may be evaluated incorrectly.

Theory

The code should be the design of the desired algorithm. The optimal solution is not expected. But memory and runtime shouldn’t be too much than expected.

Written Assignments

The assignment should be written in your own handwriting. The homework answer sheet should contain the name of the course, student name and surname, student number and date. 

Academic Integrity

The aim of the homework is to learn to do in-depth research about the course and to gain practical knowledge. Working with other students on assigned assignments is encouraged. Students who form a study group are more successful in exams than students who study on their own.

But even if you work with others to solve an assignment, you must solve each problem yourself without help. If you obtain your solution through a search (eg an internet search), you should express the solution in your own sentence and/or code. When the solution is asked orally, the student is expected to be able to explain it.

If the given assignment is a code, you have to write it yourself. You can get help from others in debugging. Manual and automatic mechanisms will be used for plagiarism detection in code. Plagiarism, cheating in the exam and similar behaviors are punished according to the disciplinary regulations.

Categories
Digital Design

Digital Design

Course Description: This course covers combinatorial, sequential circuits, state machines, verification methodologies, memories, design principles, SOC concepts and interfaces, which are frequently used in the digital design world. Within the scope of the course, a processor named Fenerbahçe Processor will be designed for educational purposes and verified with Verilog HDL. FPGA based demo will be presented.