Category: Digital Design

Midterm

• Midterm Sample Questions
• Midterm Questions
• Midterm Solutions

Final

• Final Sample Questions

A question and answer system is offered where students can ask questions and get answers. It is a platform for course announcements, student questions and answers. You can access it below.

https://piazza.com/class/l92ben0xzvd6eh

LMS (Learning Management System), some assignments will be required to be delivered through the LMS system.

Tool Name	Content	Link
Von Neumann Architecture Simulator	It is the simulator tool of the von Neumann architecture.	http://levent.tc/files/courses/tools/vonneumann/
IEEE-754 Binary to Decimal Conversion Tool	It is a tool that converts a given decimal number to IEEE-754 format.	http://levent.tc/files/courses/tools/floatbin/
Decimal, Binary and Hexadecimal Converter	It is a tool that converts a given number in decimal, binary and hexadecimal formats to other formats.	http://levent.tc/files/courses/tools/hexdecbin/
Circuit Simulator	A Javascript-based circuit simulation tool is presented. You can access it at the following address. Usage; Select an item from the toolbox and go to the right. Link the added items by drag action. Click on an input node to disconnect it. To delete the added item, drag the item to the toolbox. To edit the item’s name, you can access it on a label section. double click	http://levent.tc/files/courses/tools/devresimulatoru/
Circuit Simulator 2	It is a very comprehensive circuit simulator. User manual: http://levent.tc/files/courses/tools/devresimulatoru2/devreSimulatoruKullanimKilavuzu.pdf	http://levent.tc/files/courses/tools/devresimulatoru2/
Bit Logic Operations Calculator	It is a calculator that performs operations on a bit basis. This application is useful for learning the bitwise operations. And, or, xor, not, and scrolling operations are supported.	http://levent.tc/files/courses/tools/bitislemleri/

Lab	Topic	Download
1	Combinational Logic
2	Sequential Logic
3	Verification Approaches
4	State Machines
5	Memories
6	FB-CPU RTL Design
7	SOC Concepts, Xilinx IPI Design and Interfaces

FB-CPU RTL Design

Within the scope of this project, RTL design of a processor named FB-CPU with Verilog language and various code snippets written in machine language on the designed processor will be written. At the end of the project, it will be observed how RAM, Control Unit and Stores in a simple processor can work together and execute code snippets in machine language. FBCPU demo will be made on Basys3 FPGA development board to be used.

Detailed project description: Will be announced after midterm

Homework	Topic	Date	Due Date	Delivery Method	Download	Solution
1	State Machines

Week	Topic	Download
1	Introduction
2	Number Systems and Boolean Algebra
3	Combinational Logic
4	Sequential Logic
5	Verification Approaches
6	State Machines
7	Databus Elements
8	Midterm
9	Memories
10	FB-CPU RTL Design
11	Optimizations and Trade-offs
12	SOC Concepts I
13	SOC Concepts II
14	Multi-Clock Zone Design
15	Final and Project Presentations

Week	Topic
1	Introduction
2	Number Systems and Boolean Algebra
3	Combinational Logic
4	Sequential Logic
5	Verification Approaches
6	State Machines
7	Databus Elements
8	Midterm
9	Memories
10	FB-CPU RTL Design
11	Optimizations and Trade-offs
12	SOC Concepts I
13	SOC Concepts II
14	Multi-Clock Zone Design
15	Final and Project Presentations

Course Description

This course covers combinatorial, sequential circuits, state machines, verification methodologies, memories, design principles, SOC concepts and interfaces, which are frequently used in the digital design world. Within the scope of the course, a processor named Fenerbahçe Processor will be designed for educational purposes and verified with Verilog HDL. FPGA based demo will be presented.

Course Hours (Theoretical + Lab)

Monday 9.00-13.00

Instructors

Assist. Prof. Vecdi Emre Levent

T. A. Uğur Özbalkan

Prerequisites

There are no prerequisites.

Helpful Resources

Reference sources of the course are listed below.

• Introduction to Logic Design, Third Edition, Alan B. Marcovitz, McGraw-Hill, 2010
• Digital Design, Moris Mano and Michael D. Ciletti, 5th edition, Prentice Hall, 2009
• FPGA Prototyping by Verilog Examples, Pong Chu, John Wiley, 2008
• Introduction to Logic Design, Alan Marcovitz, McGraw Hill, 2010

Softwares

Xilinx Vivado 2022.1

Courses

The course has 2 hours of theory and 2 hours of laboratory part per week. It is expected that the course materials given by the lecturer will be reviewed before the lesson and repeated after the lesson. 

Learning Outcomes

• Logic minimization with KMAPs
• Circuit development with RTL design languages
• Accuracy measurement of RTL circuits
• Design of interfaces frequently used in industry

Quizzes

There will be two quizzes during the semester. 30 minutes will be given. Quiz date will be announced one week in advance.

Grading

It is mandatory to attend classes at 80%.

Term grade; will be determined by midterm, labs, assignments, project and final exam. Evaluation percentages are given in the table below.

Activities	Rates
Midterm	%20
Homework/Quiz	%10
Lab	%15
Project	%25
Final	%30
Bonus	Up to 5 points

5 points will be deducted for each hour that passes over the delivery time of homework and quizzes.

The weight and letter grade corresponding to the end of term grade are given in the table below.

Mark	Weight	Letter grade
90-100	4.00	AA
85-89	3.50	BA
80-84	3.00	BB
75-79	2.50	CB
65-74	2.00	CC
50-64	1.50	DC
45-49	1.00	DD
0 -44	0	FF

Expected Effort

The effort table that the student is expected to show during the term is given below.

Content	Hours	Times	Sub Total
Lesson Preparation	2	14	28
Lesson Repetition	2	14	28
Homeworks	4	6	24
Project	48	1	48
Course Lesson	4	14	56
Midterm and Final	24	2	48

Students are expected to spend an average of 232 hours during the semester to be successful in the course.

Coding Homeworks

Grading of coding assignments will be done by examining the accuracy, quality and details of the algorithmic implementation of the code.

Testing

Test entry and expected outputs will be shared for each assignment to be given. However, other test situations that have not been shared with you will be tried during the homework control. Code that takes longer to run than expected may be evaluated incorrectly.

Theory

The code should be the design of the desired algorithm. The optimal solution is not expected. But memory and runtime shouldn’t be too much than expected.

Written Assignments

The assignment should be written in your own handwriting. The homework answer sheet should contain the name of the course, student name and surname, student number and date. 

Academic Integrity

The aim of the homework is to learn to do in-depth research about the course and to gain practical knowledge. Working with other students on assigned assignments is encouraged. Students who form a study group are more successful in exams than students who study on their own.

But even if you work with others to solve an assignment, you must solve each problem yourself without help. If you obtain your solution through a search (eg an internet search), you should express the solution in your own sentence and/or code. When the solution is asked orally, the student is expected to be able to explain it.

If the given assignment is a code, you have to write it yourself. You can get help from others in debugging. Manual and automatic mechanisms will be used for plagiarism detection in code. Plagiarism, cheating in the exam and similar behaviors are punished according to the disciplinary regulations.

Course Description: This course covers combinatorial, sequential circuits, state machines, verification methodologies, memories, design principles, SOC concepts and interfaces, which are frequently used in the digital design world. Within the scope of the course, a processor named Fenerbahçe Processor will be designed for educational purposes and verified with Verilog HDL. FPGA based demo will be presented.

• Detailed Course Description
• Syllabus
• Lecture Notes
• Homeworks
• Project
• Exams and Sample Questions
• Labs
• Tools
• LMS and Piazza